arch/arm/boot/dts/qcom-msm8660.dtsi

   1 /dts-v1/;
   2
   3 /include/ "skeleton.dtsi"
   4
   5 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
   6
   7 / {
   8         model = "Qualcomm MSM8660";
   9         compatible = "qcom,msm8660";
  10         interrupt-parent = <&intc>;
  11
  12         cpus {
  13                 #address-cells = <1>;
  14                 #size-cells = <0>;
  15                 compatible = "qcom,scorpion";
  16                 enable-method = "qcom,gcc-msm8660";
  17
  18                 cpu@0 {
  19                         device_type = "cpu";
  20                         reg = <0>;
  21                         next-level-cache = <&L2>;
  22                 };
  23
  24                 cpu@1 {
  25                         device_type = "cpu";
  26                         reg = <1>;
  27                         next-level-cache = <&L2>;
  28                 };
  29
  30                 L2: l2-cache {
  31                         compatible = "cache";
  32                         cache-level = <2>;
  33                 };
  34         };
  35
  36         intc: interrupt-controller@2080000 {
  37                 compatible = "qcom,msm-8660-qgic";
  38                 interrupt-controller;
  39                 #interrupt-cells = <3>;
  40                 reg = < 0x02080000 0x1000 >,
  41                       < 0x02081000 0x1000 >;
  42         };
  43
  44         timer@2000000 {
  45                 compatible = "qcom,scss-timer", "qcom,msm-timer";
  46                 interrupts = <1 0 0x301>,
  47                              <1 1 0x301>,
  48                              <1 2 0x301>;
  49                 reg = <0x02000000 0x100>;
  50                 clock-frequency = <27000000>,
  51                                   <32768>;
  52                 cpu-offset = <0x40000>;
  53         };
  54
  55         msmgpio: gpio@800000 {
  56                 compatible = "qcom,msm-gpio";
  57                 reg = <0x00800000 0x4000>;
  58                 gpio-controller;
  59                 #gpio-cells = <2>;
  60                 ngpio = <173>;
  61                 interrupts = <0 16 0x4>;
  62                 interrupt-controller;
  63                 #interrupt-cells = <2>;
  64         };
  65
  66         gcc: clock-controller@900000 {
  67                 compatible = "qcom,gcc-msm8660";
  68                 #clock-cells = <1>;
  69                 #reset-cells = <1>;
  70                 reg = <0x900000 0x4000>;
  71         };
  72
  73         serial@19c40000 {
  74                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  75                 reg = <0x19c40000 0x1000>,
  76                       <0x19c00000 0x1000>;
  77                 interrupts = <0 195 0x0>;
  78                 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
  79                 clock-names = "core", "iface";
  80         };
  81
  82         qcom,ssbi@500000 {
  83                 compatible = "qcom,ssbi";
  84                 reg = <0x500000 0x1000>;
  85                 qcom,controller-type = "pmic-arbiter";
  86         };
  87 };