arch/arm/boot/dts/imx6sl.dtsi

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  */
   9
  10 #include <dt-bindings/interrupt-controller/irq.h>
  11 #include "skeleton.dtsi"
  12 #include "imx6sl-pinfunc.h"
  13 #include <dt-bindings/clock/imx6sl-clock.h>
  14
  15 / {
  16         aliases {
  17                 gpio0 = &gpio1;
  18                 gpio1 = &gpio2;
  19                 gpio2 = &gpio3;
  20                 gpio3 = &gpio4;
  21                 gpio4 = &gpio5;
  22                 serial0 = &uart1;
  23                 serial1 = &uart2;
  24                 serial2 = &uart3;
  25                 serial3 = &uart4;
  26                 serial4 = &uart5;
  27                 spi0 = &ecspi1;
  28                 spi1 = &ecspi2;
  29                 spi2 = &ecspi3;
  30                 spi3 = &ecspi4;
  31                 usbphy0 = &usbphy1;
  32                 usbphy1 = &usbphy2;
  33         };
  34
  35         cpus {
  36                 #address-cells = <1>;
  37                 #size-cells = <0>;
  38
  39                 cpu@0 {
  40                         compatible = "arm,cortex-a9";
  41                         device_type = "cpu";
  42                         reg = <0x0>;
  43                         next-level-cache = <&L2>;
  44                         operating-points = <
  45                                 /* kHz    uV */
  46                                 996000  1275000
  47                                 792000  1175000
  48                                 396000  975000
  49                         >;
  50                         fsl,soc-operating-points = <
  51                                 /* ARM kHz      SOC-PU uV */
  52                                 996000          1225000
  53                                 792000          1175000
  54                                 396000          1175000
  55                         >;
  56                         clock-latency = <61036>; /* two CLK32 periods */
  57                         clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
  58                                         <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
  59                                         <&clks IMX6SL_CLK_PLL1_SYS>;
  60                         clock-names = "arm", "pll2_pfd2_396m", "step",
  61                                       "pll1_sw", "pll1_sys";
  62                         arm-supply = <&reg_arm>;
  63                         pu-supply = <&reg_pu>;
  64                         soc-supply = <&reg_soc>;
  65                 };
  66         };
  67
  68         intc: interrupt-controller@00a01000 {
  69                 compatible = "arm,cortex-a9-gic";
  70                 #interrupt-cells = <3>;
  71                 #address-cells = <1>;
  72                 #size-cells = <1>;
  73                 interrupt-controller;
  74                 reg = <0x00a01000 0x1000>,
  75                       <0x00a00100 0x100>;
  76         };
  77
  78         clocks {
  79                 #address-cells = <1>;
  80                 #size-cells = <0>;
  81
  82                 ckil {
  83                         compatible = "fixed-clock";
  84                         clock-frequency = <32768>;
  85                 };
  86
  87                 osc {
  88                         compatible = "fixed-clock";
  89                         clock-frequency = <24000000>;
  90                 };
  91         };
  92
  93         soc {
  94                 #address-cells = <1>;
  95                 #size-cells = <1>;
  96                 compatible = "simple-bus";
  97                 interrupt-parent = <&intc>;
  98                 ranges;
  99
 100                 ocram: sram@00900000 {
 101                         compatible = "mmio-sram";
 102                         reg = <0x00900000 0x20000>;
 103                         clocks = <&clks IMX6SL_CLK_OCRAM>;
 104                 };
 105
 106                 L2: l2-cache@00a02000 {
 107                         compatible = "arm,pl310-cache";
 108                         reg = <0x00a02000 0x1000>;
 109                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 110                         cache-unified;
 111                         cache-level = <2>;
 112                         arm,tag-latency = <4 2 3>;
 113                         arm,data-latency = <4 2 3>;
 114                 };
 115
 116                 pmu {
 117                         compatible = "arm,cortex-a9-pmu";
 118                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 119                 };
 120
 121                 aips1: aips-bus@02000000 {
 122                         compatible = "fsl,aips-bus", "simple-bus";
 123                         #address-cells = <1>;
 124                         #size-cells = <1>;
 125                         reg = <0x02000000 0x100000>;
 126                         ranges;
 127
 128                         spba: spba-bus@02000000 {
 129                                 compatible = "fsl,spba-bus", "simple-bus";
 130                                 #address-cells = <1>;
 131                                 #size-cells = <1>;
 132                                 reg = <0x02000000 0x40000>;
 133                                 ranges;
 134
 135                                 spdif: spdif@02004000 {
 136                                         reg = <0x02004000 0x4000>;
 137                                         interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
 138                                 };
 139
 140                                 ecspi1: ecspi@02008000 {
 141                                         #address-cells = <1>;
 142                                         #size-cells = <0>;
 143                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 144                                         reg = <0x02008000 0x4000>;
 145                                         interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
 146                                         clocks = <&clks IMX6SL_CLK_ECSPI1>,
 147                                                  <&clks IMX6SL_CLK_ECSPI1>;
 148                                         clock-names = "ipg", "per";
 149                                         status = "disabled";
 150                                 };
 151
 152                                 ecspi2: ecspi@0200c000 {
 153                                         #address-cells = <1>;
 154                                         #size-cells = <0>;
 155                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 156                                         reg = <0x0200c000 0x4000>;
 157                                         interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
 158                                         clocks = <&clks IMX6SL_CLK_ECSPI2>,
 159                                                  <&clks IMX6SL_CLK_ECSPI2>;
 160                                         clock-names = "ipg", "per";
 161                                         status = "disabled";
 162                                 };
 163
 164                                 ecspi3: ecspi@02010000 {
 165                                         #address-cells = <1>;
 166                                         #size-cells = <0>;
 167                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 168                                         reg = <0x02010000 0x4000>;
 169                                         interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
 170                                         clocks = <&clks IMX6SL_CLK_ECSPI3>,
 171                                                  <&clks IMX6SL_CLK_ECSPI3>;
 172                                         clock-names = "ipg", "per";
 173                                         status = "disabled";
 174                                 };
 175
 176                                 ecspi4: ecspi@02014000 {
 177                                         #address-cells = <1>;
 178                                         #size-cells = <0>;
 179                                         compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
 180                                         reg = <0x02014000 0x4000>;
 181                                         interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
 182                                         clocks = <&clks IMX6SL_CLK_ECSPI4>,
 183                                                  <&clks IMX6SL_CLK_ECSPI4>;
 184                                         clock-names = "ipg", "per";
 185                                         status = "disabled";
 186                                 };
 187
 188                                 uart5: serial@02018000 {
 189                                         compatible = "fsl,imx6sl-uart",
 190                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 191                                         reg = <0x02018000 0x4000>;
 192                                         interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
 193                                         clocks = <&clks IMX6SL_CLK_UART>,
 194                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 195                                         clock-names = "ipg", "per";
 196                                         dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
 197                                         dma-names = "rx", "tx";
 198                                         status = "disabled";
 199                                 };
 200
 201                                 uart1: serial@02020000 {
 202                                         compatible = "fsl,imx6sl-uart",
 203                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 204                                         reg = <0x02020000 0x4000>;
 205                                         interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
 206                                         clocks = <&clks IMX6SL_CLK_UART>,
 207                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 208                                         clock-names = "ipg", "per";
 209                                         dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
 210                                         dma-names = "rx", "tx";
 211                                         status = "disabled";
 212                                 };
 213
 214                                 uart2: serial@02024000 {
 215                                         compatible = "fsl,imx6sl-uart",
 216                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 217                                         reg = <0x02024000 0x4000>;
 218                                         interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
 219                                         clocks = <&clks IMX6SL_CLK_UART>,
 220                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 221                                         clock-names = "ipg", "per";
 222                                         dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
 223                                         dma-names = "rx", "tx";
 224                                         status = "disabled";
 225                                 };
 226
 227                                 ssi1: ssi@02028000 {
 228                                         compatible = "fsl,imx6sl-ssi",
 229                                                         "fsl,imx51-ssi",
 230                                                         "fsl,imx21-ssi";
 231                                         reg = <0x02028000 0x4000>;
 232                                         interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
 233                                         clocks = <&clks IMX6SL_CLK_SSI1>;
 234                                         dmas = <&sdma 37 1 0>,
 235                                                <&sdma 38 1 0>;
 236                                         dma-names = "rx", "tx";
 237                                         fsl,fifo-depth = <15>;
 238                                         status = "disabled";
 239                                 };
 240
 241                                 ssi2: ssi@0202c000 {
 242                                         compatible = "fsl,imx6sl-ssi",
 243                                                         "fsl,imx51-ssi",
 244                                                         "fsl,imx21-ssi";
 245                                         reg = <0x0202c000 0x4000>;
 246                                         interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
 247                                         clocks = <&clks IMX6SL_CLK_SSI2>;
 248                                         dmas = <&sdma 41 1 0>,
 249                                                <&sdma 42 1 0>;
 250                                         dma-names = "rx", "tx";
 251                                         fsl,fifo-depth = <15>;
 252                                         status = "disabled";
 253                                 };
 254
 255                                 ssi3: ssi@02030000 {
 256                                         compatible = "fsl,imx6sl-ssi",
 257                                                         "fsl,imx51-ssi",
 258                                                         "fsl,imx21-ssi";
 259                                         reg = <0x02030000 0x4000>;
 260                                         interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
 261                                         clocks = <&clks IMX6SL_CLK_SSI3>;
 262                                         dmas = <&sdma 45 1 0>,
 263                                                <&sdma 46 1 0>;
 264                                         dma-names = "rx", "tx";
 265                                         fsl,fifo-depth = <15>;
 266                                         status = "disabled";
 267                                 };
 268
 269                                 uart3: serial@02034000 {
 270                                         compatible = "fsl,imx6sl-uart",
 271                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 272                                         reg = <0x02034000 0x4000>;
 273                                         interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
 274                                         clocks = <&clks IMX6SL_CLK_UART>,
 275                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 276                                         clock-names = "ipg", "per";
 277                                         dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
 278                                         dma-names = "rx", "tx";
 279                                         status = "disabled";
 280                                 };
 281
 282                                 uart4: serial@02038000 {
 283                                         compatible = "fsl,imx6sl-uart",
 284                                                    "fsl,imx6q-uart", "fsl,imx21-uart";
 285                                         reg = <0x02038000 0x4000>;
 286                                         interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
 287                                         clocks = <&clks IMX6SL_CLK_UART>,
 288                                                  <&clks IMX6SL_CLK_UART_SERIAL>;
 289                                         clock-names = "ipg", "per";
 290                                         dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
 291                                         dma-names = "rx", "tx";
 292                                         status = "disabled";
 293                                 };
 294                         };
 295
 296                         pwm1: pwm@02080000 {
 297                                 #pwm-cells = <2>;
 298                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 299                                 reg = <0x02080000 0x4000>;
 300                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
 301                                 clocks = <&clks IMX6SL_CLK_PWM1>,
 302                                          <&clks IMX6SL_CLK_PWM1>;
 303                                 clock-names = "ipg", "per";
 304                         };
 305
 306                         pwm2: pwm@02084000 {
 307                                 #pwm-cells = <2>;
 308                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 309                                 reg = <0x02084000 0x4000>;
 310                                 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
 311                                 clocks = <&clks IMX6SL_CLK_PWM2>,
 312                                          <&clks IMX6SL_CLK_PWM2>;
 313                                 clock-names = "ipg", "per";
 314                         };
 315
 316                         pwm3: pwm@02088000 {
 317                                 #pwm-cells = <2>;
 318                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 319                                 reg = <0x02088000 0x4000>;
 320                                 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
 321                                 clocks = <&clks IMX6SL_CLK_PWM3>,
 322                                          <&clks IMX6SL_CLK_PWM3>;
 323                                 clock-names = "ipg", "per";
 324                         };
 325
 326                         pwm4: pwm@0208c000 {
 327                                 #pwm-cells = <2>;
 328                                 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
 329                                 reg = <0x0208c000 0x4000>;
 330                                 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
 331                                 clocks = <&clks IMX6SL_CLK_PWM4>,
 332                                          <&clks IMX6SL_CLK_PWM4>;
 333                                 clock-names = "ipg", "per";
 334                         };
 335
 336                         gpt: gpt@02098000 {
 337                                 compatible = "fsl,imx6sl-gpt";
 338                                 reg = <0x02098000 0x4000>;
 339                                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
 340                                 clocks = <&clks IMX6SL_CLK_GPT>,
 341                                          <&clks IMX6SL_CLK_GPT_SERIAL>;
 342                                 clock-names = "ipg", "per";
 343                         };
 344
 345                         gpio1: gpio@0209c000 {
 346                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 347                                 reg = <0x0209c000 0x4000>;
 348                                 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
 349                                              <0 67 IRQ_TYPE_LEVEL_HIGH>;
 350                                 gpio-controller;
 351                                 #gpio-cells = <2>;
 352                                 interrupt-controller;
 353                                 #interrupt-cells = <2>;
 354                         };
 355
 356                         gpio2: gpio@020a0000 {
 357                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 358                                 reg = <0x020a0000 0x4000>;
 359                                 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
 360                                              <0 69 IRQ_TYPE_LEVEL_HIGH>;
 361                                 gpio-controller;
 362                                 #gpio-cells = <2>;
 363                                 interrupt-controller;
 364                                 #interrupt-cells = <2>;
 365                         };
 366
 367                         gpio3: gpio@020a4000 {
 368                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 369                                 reg = <0x020a4000 0x4000>;
 370                                 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
 371                                              <0 71 IRQ_TYPE_LEVEL_HIGH>;
 372                                 gpio-controller;
 373                                 #gpio-cells = <2>;
 374                                 interrupt-controller;
 375                                 #interrupt-cells = <2>;
 376                         };
 377
 378                         gpio4: gpio@020a8000 {
 379                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 380                                 reg = <0x020a8000 0x4000>;
 381                                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
 382                                              <0 73 IRQ_TYPE_LEVEL_HIGH>;
 383                                 gpio-controller;
 384                                 #gpio-cells = <2>;
 385                                 interrupt-controller;
 386                                 #interrupt-cells = <2>;
 387                         };
 388
 389                         gpio5: gpio@020ac000 {
 390                                 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
 391                                 reg = <0x020ac000 0x4000>;
 392                                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
 393                                              <0 75 IRQ_TYPE_LEVEL_HIGH>;
 394                                 gpio-controller;
 395                                 #gpio-cells = <2>;
 396                                 interrupt-controller;
 397                                 #interrupt-cells = <2>;
 398                         };
 399
 400                         kpp: kpp@020b8000 {
 401                                 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
 402                                 reg = <0x020b8000 0x4000>;
 403                                 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
 404                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 405                         };
 406
 407                         wdog1: wdog@020bc000 {
 408                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 409                                 reg = <0x020bc000 0x4000>;
 410                                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 411                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 412                         };
 413
 414                         wdog2: wdog@020c0000 {
 415                                 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
 416                                 reg = <0x020c0000 0x4000>;
 417                                 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
 418                                 clocks = <&clks IMX6SL_CLK_DUMMY>;
 419                                 status = "disabled";
 420                         };
 421
 422                         clks: ccm@020c4000 {
 423                                 compatible = "fsl,imx6sl-ccm";
 424                                 reg = <0x020c4000 0x4000>;
 425                                 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
 426                                              <0 88 IRQ_TYPE_LEVEL_HIGH>;
 427                                 #clock-cells = <1>;
 428                         };
 429
 430                         anatop: anatop@020c8000 {
 431                                 compatible = "fsl,imx6sl-anatop",
 432                                              "fsl,imx6q-anatop",
 433                                              "syscon", "simple-bus";
 434                                 reg = <0x020c8000 0x1000>;
 435                                 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
 436                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
 437                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 438
 439                                 regulator-1p1@110 {
 440                                         compatible = "fsl,anatop-regulator";
 441                                         regulator-name = "vdd1p1";
 442                                         regulator-min-microvolt = <800000>;
 443                                         regulator-max-microvolt = <1375000>;
 444                                         regulator-always-on;
 445                                         anatop-reg-offset = <0x110>;
 446                                         anatop-vol-bit-shift = <8>;
 447                                         anatop-vol-bit-width = <5>;
 448                                         anatop-min-bit-val = <4>;
 449                                         anatop-min-voltage = <800000>;
 450                                         anatop-max-voltage = <1375000>;
 451                                 };
 452
 453                                 regulator-3p0@120 {
 454                                         compatible = "fsl,anatop-regulator";
 455                                         regulator-name = "vdd3p0";
 456                                         regulator-min-microvolt = <2800000>;
 457                                         regulator-max-microvolt = <3150000>;
 458                                         regulator-always-on;
 459                                         anatop-reg-offset = <0x120>;
 460                                         anatop-vol-bit-shift = <8>;
 461                                         anatop-vol-bit-width = <5>;
 462                                         anatop-min-bit-val = <0>;
 463                                         anatop-min-voltage = <2625000>;
 464                                         anatop-max-voltage = <3400000>;
 465                                 };
 466
 467                                 regulator-2p5@130 {
 468                                         compatible = "fsl,anatop-regulator";
 469                                         regulator-name = "vdd2p5";
 470                                         regulator-min-microvolt = <2100000>;
 471                                         regulator-max-microvolt = <2850000>;
 472                                         regulator-always-on;
 473                                         anatop-reg-offset = <0x130>;
 474                                         anatop-vol-bit-shift = <8>;
 475                                         anatop-vol-bit-width = <5>;
 476                                         anatop-min-bit-val = <0>;
 477                                         anatop-min-voltage = <2100000>;
 478                                         anatop-max-voltage = <2850000>;
 479                                 };
 480
 481                                 reg_arm: regulator-vddcore@140 {
 482                                         compatible = "fsl,anatop-regulator";
 483                                         regulator-name = "vddarm";
 484                                         regulator-min-microvolt = <725000>;
 485                                         regulator-max-microvolt = <1450000>;
 486                                         regulator-always-on;
 487                                         anatop-reg-offset = <0x140>;
 488                                         anatop-vol-bit-shift = <0>;
 489                                         anatop-vol-bit-width = <5>;
 490                                         anatop-delay-reg-offset = <0x170>;
 491                                         anatop-delay-bit-shift = <24>;
 492                                         anatop-delay-bit-width = <2>;
 493                                         anatop-min-bit-val = <1>;
 494                                         anatop-min-voltage = <725000>;
 495                                         anatop-max-voltage = <1450000>;
 496                                 };
 497
 498                                 reg_pu: regulator-vddpu@140 {
 499                                         compatible = "fsl,anatop-regulator";
 500                                         regulator-name = "vddpu";
 501                                         regulator-min-microvolt = <725000>;
 502                                         regulator-max-microvolt = <1450000>;
 503                                         regulator-always-on;
 504                                         anatop-reg-offset = <0x140>;
 505                                         anatop-vol-bit-shift = <9>;
 506                                         anatop-vol-bit-width = <5>;
 507                                         anatop-delay-reg-offset = <0x170>;
 508                                         anatop-delay-bit-shift = <26>;
 509                                         anatop-delay-bit-width = <2>;
 510                                         anatop-min-bit-val = <1>;
 511                                         anatop-min-voltage = <725000>;
 512                                         anatop-max-voltage = <1450000>;
 513                                 };
 514
 515                                 reg_soc: regulator-vddsoc@140 {
 516                                         compatible = "fsl,anatop-regulator";
 517                                         regulator-name = "vddsoc";
 518                                         regulator-min-microvolt = <725000>;
 519                                         regulator-max-microvolt = <1450000>;
 520                                         regulator-always-on;
 521                                         anatop-reg-offset = <0x140>;
 522                                         anatop-vol-bit-shift = <18>;
 523                                         anatop-vol-bit-width = <5>;
 524                                         anatop-delay-reg-offset = <0x170>;
 525                                         anatop-delay-bit-shift = <28>;
 526                                         anatop-delay-bit-width = <2>;
 527                                         anatop-min-bit-val = <1>;
 528                                         anatop-min-voltage = <725000>;
 529                                         anatop-max-voltage = <1450000>;
 530                                 };
 531                         };
 532
 533                         usbphy1: usbphy@020c9000 {
 534                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 535                                 reg = <0x020c9000 0x1000>;
 536                                 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
 537                                 clocks = <&clks IMX6SL_CLK_USBPHY1>;
 538                                 fsl,anatop = <&anatop>;
 539                         };
 540
 541                         usbphy2: usbphy@020ca000 {
 542                                 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
 543                                 reg = <0x020ca000 0x1000>;
 544                                 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
 545                                 clocks = <&clks IMX6SL_CLK_USBPHY2>;
 546                                 fsl,anatop = <&anatop>;
 547                         };
 548
 549                         snvs@020cc000 {
 550                                 compatible = "fsl,sec-v4.0-mon", "simple-bus";
 551                                 #address-cells = <1>;
 552                                 #size-cells = <1>;
 553                                 ranges = <0 0x020cc000 0x4000>;
 554
 555                                 snvs-rtc-lp@34 {
 556                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 557                                         reg = <0x34 0x58>;
 558                                         interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
 559                                                      <0 20 IRQ_TYPE_LEVEL_HIGH>;
 560                                 };
 561                         };
 562
 563                         epit1: epit@020d0000 {
 564                                 reg = <0x020d0000 0x4000>;
 565                                 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
 566                         };
 567
 568                         epit2: epit@020d4000 {
 569                                 reg = <0x020d4000 0x4000>;
 570                                 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
 571                         };
 572
 573                         src: src@020d8000 {
 574                                 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
 575                                 reg = <0x020d8000 0x4000>;
 576                                 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
 577                                              <0 96 IRQ_TYPE_LEVEL_HIGH>;
 578                                 #reset-cells = <1>;
 579                         };
 580
 581                         gpc: gpc@020dc000 {
 582                                 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
 583                                 reg = <0x020dc000 0x4000>;
 584                                 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
 585                         };
 586
 587                         gpr: iomuxc-gpr@020e0000 {
 588                                 compatible = "fsl,imx6sl-iomuxc-gpr",
 589                                              "fsl,imx6q-iomuxc-gpr", "syscon";
 590                                 reg = <0x020e0000 0x38>;
 591                         };
 592
 593                         iomuxc: iomuxc@020e0000 {
 594                                 compatible = "fsl,imx6sl-iomuxc";
 595                                 reg = <0x020e0000 0x4000>;
 596                         };
 597
 598                         csi: csi@020e4000 {
 599                                 reg = <0x020e4000 0x4000>;
 600                                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 601                         };
 602
 603                         spdc: spdc@020e8000 {
 604                                 reg = <0x020e8000 0x4000>;
 605                                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
 606                         };
 607
 608                         sdma: sdma@020ec000 {
 609                                 compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
 610                                 reg = <0x020ec000 0x4000>;
 611                                 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
 612                                 clocks = <&clks IMX6SL_CLK_SDMA>,
 613                                          <&clks IMX6SL_CLK_SDMA>;
 614                                 clock-names = "ipg", "ahb";
 615                                 #dma-cells = <3>;
 616                                 /* imx6sl reuses imx6q sdma firmware */
 617                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 618                         };
 619
 620                         pxp: pxp@020f0000 {
 621                                 reg = <0x020f0000 0x4000>;
 622                                 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 623                         };
 624
 625                         epdc: epdc@020f4000 {
 626                                 reg = <0x020f4000 0x4000>;
 627                                 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
 628                         };
 629
 630                         lcdif: lcdif@020f8000 {
 631                                 reg = <0x020f8000 0x4000>;
 632                                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 633                         };
 634
 635                         dcp: dcp@020fc000 {
 636                                 reg = <0x020fc000 0x4000>;
 637                                 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
 638                         };
 639                 };
 640
 641                 aips2: aips-bus@02100000 {
 642                         compatible = "fsl,aips-bus", "simple-bus";
 643                         #address-cells = <1>;
 644                         #size-cells = <1>;
 645                         reg = <0x02100000 0x100000>;
 646                         ranges;
 647
 648                         usbotg1: usb@02184000 {
 649                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 650                                 reg = <0x02184000 0x200>;
 651                                 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
 652                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 653                                 fsl,usbphy = <&usbphy1>;
 654                                 fsl,usbmisc = <&usbmisc 0>;
 655                                 status = "disabled";
 656                         };
 657
 658                         usbotg2: usb@02184200 {
 659                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 660                                 reg = <0x02184200 0x200>;
 661                                 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
 662                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 663                                 fsl,usbphy = <&usbphy2>;
 664                                 fsl,usbmisc = <&usbmisc 1>;
 665                                 status = "disabled";
 666                         };
 667
 668                         usbh: usb@02184400 {
 669                                 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
 670                                 reg = <0x02184400 0x200>;
 671                                 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
 672                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 673                                 fsl,usbmisc = <&usbmisc 2>;
 674                                 status = "disabled";
 675                         };
 676
 677                         usbmisc: usbmisc@02184800 {
 678                                 #index-cells = <1>;
 679                                 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
 680                                 reg = <0x02184800 0x200>;
 681                                 clocks = <&clks IMX6SL_CLK_USBOH3>;
 682                         };
 683
 684                         fec: ethernet@02188000 {
 685                                 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
 686                                 reg = <0x02188000 0x4000>;
 687                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 688                                 clocks = <&clks IMX6SL_CLK_ENET_REF>,
 689                                          <&clks IMX6SL_CLK_ENET_REF>;
 690                                 clock-names = "ipg", "ahb";
 691                                 status = "disabled";
 692                         };
 693
 694                         usdhc1: usdhc@02190000 {
 695                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 696                                 reg = <0x02190000 0x4000>;
 697                                 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
 698                                 clocks = <&clks IMX6SL_CLK_USDHC1>,
 699                                          <&clks IMX6SL_CLK_USDHC1>,
 700                                          <&clks IMX6SL_CLK_USDHC1>;
 701                                 clock-names = "ipg", "ahb", "per";
 702                                 bus-width = <4>;
 703                                 status = "disabled";
 704                         };
 705
 706                         usdhc2: usdhc@02194000 {
 707                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 708                                 reg = <0x02194000 0x4000>;
 709                                 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
 710                                 clocks = <&clks IMX6SL_CLK_USDHC2>,
 711                                          <&clks IMX6SL_CLK_USDHC2>,
 712                                          <&clks IMX6SL_CLK_USDHC2>;
 713                                 clock-names = "ipg", "ahb", "per";
 714                                 bus-width = <4>;
 715                                 status = "disabled";
 716                         };
 717
 718                         usdhc3: usdhc@02198000 {
 719                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 720                                 reg = <0x02198000 0x4000>;
 721                                 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
 722                                 clocks = <&clks IMX6SL_CLK_USDHC3>,
 723                                          <&clks IMX6SL_CLK_USDHC3>,
 724                                          <&clks IMX6SL_CLK_USDHC3>;
 725                                 clock-names = "ipg", "ahb", "per";
 726                                 bus-width = <4>;
 727                                 status = "disabled";
 728                         };
 729
 730                         usdhc4: usdhc@0219c000 {
 731                                 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
 732                                 reg = <0x0219c000 0x4000>;
 733                                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
 734                                 clocks = <&clks IMX6SL_CLK_USDHC4>,
 735                                          <&clks IMX6SL_CLK_USDHC4>,
 736                                          <&clks IMX6SL_CLK_USDHC4>;
 737                                 clock-names = "ipg", "ahb", "per";
 738                                 bus-width = <4>;
 739                                 status = "disabled";
 740                         };
 741
 742                         i2c1: i2c@021a0000 {
 743                                 #address-cells = <1>;
 744                                 #size-cells = <0>;
 745                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 746                                 reg = <0x021a0000 0x4000>;
 747                                 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
 748                                 clocks = <&clks IMX6SL_CLK_I2C1>;
 749                                 status = "disabled";
 750                         };
 751
 752                         i2c2: i2c@021a4000 {
 753                                 #address-cells = <1>;
 754                                 #size-cells = <0>;
 755                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 756                                 reg = <0x021a4000 0x4000>;
 757                                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
 758                                 clocks = <&clks IMX6SL_CLK_I2C2>;
 759                                 status = "disabled";
 760                         };
 761
 762                         i2c3: i2c@021a8000 {
 763                                 #address-cells = <1>;
 764                                 #size-cells = <0>;
 765                                 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
 766                                 reg = <0x021a8000 0x4000>;
 767                                 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
 768                                 clocks = <&clks IMX6SL_CLK_I2C3>;
 769                                 status = "disabled";
 770                         };
 771
 772                         mmdc: mmdc@021b0000 {
 773                                 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
 774                                 reg = <0x021b0000 0x4000>;
 775                         };
 776
 777                         rngb: rngb@021b4000 {
 778                                 reg = <0x021b4000 0x4000>;
 779                                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
 780                         };
 781
 782                         weim: weim@021b8000 {
 783                                 reg = <0x021b8000 0x4000>;
 784                                 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
 785                         };
 786
 787                         ocotp: ocotp@021bc000 {
 788                                 compatible = "fsl,imx6sl-ocotp";
 789                                 reg = <0x021bc000 0x4000>;
 790                         };
 791
 792                         audmux: audmux@021d8000 {
 793                                 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
 794                                 reg = <0x021d8000 0x4000>;
 795                                 status = "disabled";
 796                         };
 797                 };
 798         };
 799 };