arch/arm/boot/dts/imx53.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14 #include "imx53-pinfunc.h"
  15 #include <dt-bindings/clock/imx5-clock.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/input/input.h>
  18
  19 / {
  20         aliases {
  21                 gpio0 = &gpio1;
  22                 gpio1 = &gpio2;
  23                 gpio2 = &gpio3;
  24                 gpio3 = &gpio4;
  25                 gpio4 = &gpio5;
  26                 gpio5 = &gpio6;
  27                 gpio6 = &gpio7;
  28                 i2c0 = &i2c1;
  29                 i2c1 = &i2c2;
  30                 i2c2 = &i2c3;
  31                 mmc0 = &esdhc1;
  32                 mmc1 = &esdhc2;
  33                 mmc2 = &esdhc3;
  34                 mmc3 = &esdhc4;
  35                 serial0 = &uart1;
  36                 serial1 = &uart2;
  37                 serial2 = &uart3;
  38                 serial3 = &uart4;
  39                 serial4 = &uart5;
  40                 spi0 = &ecspi1;
  41                 spi1 = &ecspi2;
  42                 spi2 = &cspi;
  43         };
  44
  45         cpus {
  46                 #address-cells = <1>;
  47                 #size-cells = <0>;
  48                 cpu@0 {
  49                         device_type = "cpu";
  50                         compatible = "arm,cortex-a8";
  51                         reg = <0x0>;
  52                 };
  53         };
  54
  55         display-subsystem {
  56                 compatible = "fsl,imx-display-subsystem";
  57                 ports = <&ipu_di0>, <&ipu_di1>;
  58         };
  59
  60         tzic: tz-interrupt-controller@0fffc000 {
  61                 compatible = "fsl,imx53-tzic", "fsl,tzic";
  62                 interrupt-controller;
  63                 #interrupt-cells = <1>;
  64                 reg = <0x0fffc000 0x4000>;
  65         };
  66
  67         clocks {
  68                 #address-cells = <1>;
  69                 #size-cells = <0>;
  70
  71                 ckil {
  72                         compatible = "fsl,imx-ckil", "fixed-clock";
  73                         clock-frequency = <32768>;
  74                 };
  75
  76                 ckih1 {
  77                         compatible = "fsl,imx-ckih1", "fixed-clock";
  78                         clock-frequency = <22579200>;
  79                 };
  80
  81                 ckih2 {
  82                         compatible = "fsl,imx-ckih2", "fixed-clock";
  83                         clock-frequency = <0>;
  84                 };
  85
  86                 osc {
  87                         compatible = "fsl,imx-osc", "fixed-clock";
  88                         clock-frequency = <24000000>;
  89                 };
  90         };
  91
  92         soc {
  93                 #address-cells = <1>;
  94                 #size-cells = <1>;
  95                 compatible = "simple-bus";
  96                 interrupt-parent = <&tzic>;
  97                 ranges;
  98
  99                 sata: sata@10000000 {
 100                         compatible = "fsl,imx53-ahci";
 101                         reg = <0x10000000 0x1000>;
 102                         interrupts = <28>;
 103                         clocks = <&clks IMX5_CLK_SATA_GATE>,
 104                                  <&clks IMX5_CLK_SATA_REF>,
 105                                  <&clks IMX5_CLK_AHB>;
 106                         clock-names = "sata_gate", "sata_ref", "ahb";
 107                         status = "disabled";
 108                 };
 109
 110                 ipu: ipu@18000000 {
 111                         #address-cells = <1>;
 112                         #size-cells = <0>;
 113                         compatible = "fsl,imx53-ipu";
 114                         reg = <0x18000000 0x080000000>;
 115                         interrupts = <11 10>;
 116                         clocks = <&clks IMX5_CLK_IPU_GATE>,
 117                                  <&clks IMX5_CLK_IPU_DI0_GATE>,
 118                                  <&clks IMX5_CLK_IPU_DI1_GATE>;
 119                         clock-names = "bus", "di0", "di1";
 120                         resets = <&src 2>;
 121
 122                         ipu_di0: port@2 {
 123                                 #address-cells = <1>;
 124                                 #size-cells = <0>;
 125                                 reg = <2>;
 126
 127                                 ipu_di0_disp0: endpoint@0 {
 128                                         reg = <0>;
 129                                 };
 130
 131                                 ipu_di0_lvds0: endpoint@1 {
 132                                         reg = <1>;
 133                                         remote-endpoint = <&lvds0_in>;
 134                                 };
 135                         };
 136
 137                         ipu_di1: port@3 {
 138                                 #address-cells = <1>;
 139                                 #size-cells = <0>;
 140                                 reg = <3>;
 141
 142                                 ipu_di1_disp1: endpoint@0 {
 143                                         reg = <0>;
 144                                 };
 145
 146                                 ipu_di1_lvds1: endpoint@1 {
 147                                         reg = <1>;
 148                                         remote-endpoint = <&lvds1_in>;
 149                                 };
 150
 151                                 ipu_di1_tve: endpoint@2 {
 152                                         reg = <2>;
 153                                         remote-endpoint = <&tve_in>;
 154                                 };
 155                         };
 156                 };
 157
 158                 aips@50000000 { /* AIPS1 */
 159                         compatible = "fsl,aips-bus", "simple-bus";
 160                         #address-cells = <1>;
 161                         #size-cells = <1>;
 162                         reg = <0x50000000 0x10000000>;
 163                         ranges;
 164
 165                         spba@50000000 {
 166                                 compatible = "fsl,spba-bus", "simple-bus";
 167                                 #address-cells = <1>;
 168                                 #size-cells = <1>;
 169                                 reg = <0x50000000 0x40000>;
 170                                 ranges;
 171
 172                                 esdhc1: esdhc@50004000 {
 173                                         compatible = "fsl,imx53-esdhc";
 174                                         reg = <0x50004000 0x4000>;
 175                                         interrupts = <1>;
 176                                         clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
 177                                                  <&clks IMX5_CLK_DUMMY>,
 178                                                  <&clks IMX5_CLK_ESDHC1_PER_GATE>;
 179                                         clock-names = "ipg", "ahb", "per";
 180                                         bus-width = <4>;
 181                                         status = "disabled";
 182                                 };
 183
 184                                 esdhc2: esdhc@50008000 {
 185                                         compatible = "fsl,imx53-esdhc";
 186                                         reg = <0x50008000 0x4000>;
 187                                         interrupts = <2>;
 188                                         clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
 189                                                  <&clks IMX5_CLK_DUMMY>,
 190                                                  <&clks IMX5_CLK_ESDHC2_PER_GATE>;
 191                                         clock-names = "ipg", "ahb", "per";
 192                                         bus-width = <4>;
 193                                         status = "disabled";
 194                                 };
 195
 196                                 uart3: serial@5000c000 {
 197                                         compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 198                                         reg = <0x5000c000 0x4000>;
 199                                         interrupts = <33>;
 200                                         clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
 201                                                  <&clks IMX5_CLK_UART3_PER_GATE>;
 202                                         clock-names = "ipg", "per";
 203                                         status = "disabled";
 204                                 };
 205
 206                                 ecspi1: ecspi@50010000 {
 207                                         #address-cells = <1>;
 208                                         #size-cells = <0>;
 209                                         compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 210                                         reg = <0x50010000 0x4000>;
 211                                         interrupts = <36>;
 212                                         clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
 213                                                  <&clks IMX5_CLK_ECSPI1_PER_GATE>;
 214                                         clock-names = "ipg", "per";
 215                                         status = "disabled";
 216                                 };
 217
 218                                 ssi2: ssi@50014000 {
 219                                         compatible = "fsl,imx53-ssi",
 220                                                         "fsl,imx51-ssi",
 221                                                         "fsl,imx21-ssi";
 222                                         reg = <0x50014000 0x4000>;
 223                                         interrupts = <30>;
 224                                         clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
 225                                         dmas = <&sdma 24 1 0>,
 226                                                <&sdma 25 1 0>;
 227                                         dma-names = "rx", "tx";
 228                                         fsl,fifo-depth = <15>;
 229                                         fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
 230                                         status = "disabled";
 231                                 };
 232
 233                                 esdhc3: esdhc@50020000 {
 234                                         compatible = "fsl,imx53-esdhc";
 235                                         reg = <0x50020000 0x4000>;
 236                                         interrupts = <3>;
 237                                         clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
 238                                                  <&clks IMX5_CLK_DUMMY>,
 239                                                  <&clks IMX5_CLK_ESDHC3_PER_GATE>;
 240                                         clock-names = "ipg", "ahb", "per";
 241                                         bus-width = <4>;
 242                                         status = "disabled";
 243                                 };
 244
 245                                 esdhc4: esdhc@50024000 {
 246                                         compatible = "fsl,imx53-esdhc";
 247                                         reg = <0x50024000 0x4000>;
 248                                         interrupts = <4>;
 249                                         clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
 250                                                  <&clks IMX5_CLK_DUMMY>,
 251                                                  <&clks IMX5_CLK_ESDHC4_PER_GATE>;
 252                                         clock-names = "ipg", "ahb", "per";
 253                                         bus-width = <4>;
 254                                         status = "disabled";
 255                                 };
 256                         };
 257
 258                         usbphy0: usbphy@0 {
 259                                 compatible = "usb-nop-xceiv";
 260                                 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
 261                                 clock-names = "main_clk";
 262                                 status = "okay";
 263                         };
 264
 265                         usbphy1: usbphy@1 {
 266                                 compatible = "usb-nop-xceiv";
 267                                 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
 268                                 clock-names = "main_clk";
 269                                 status = "okay";
 270                         };
 271
 272                         usbotg: usb@53f80000 {
 273                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 274                                 reg = <0x53f80000 0x0200>;
 275                                 interrupts = <18>;
 276                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 277                                 fsl,usbmisc = <&usbmisc 0>;
 278                                 fsl,usbphy = <&usbphy0>;
 279                                 status = "disabled";
 280                         };
 281
 282                         usbh1: usb@53f80200 {
 283                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 284                                 reg = <0x53f80200 0x0200>;
 285                                 interrupts = <14>;
 286                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 287                                 fsl,usbmisc = <&usbmisc 1>;
 288                                 fsl,usbphy = <&usbphy1>;
 289                                 status = "disabled";
 290                         };
 291
 292                         usbh2: usb@53f80400 {
 293                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 294                                 reg = <0x53f80400 0x0200>;
 295                                 interrupts = <16>;
 296                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 297                                 fsl,usbmisc = <&usbmisc 2>;
 298                                 status = "disabled";
 299                         };
 300
 301                         usbh3: usb@53f80600 {
 302                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 303                                 reg = <0x53f80600 0x0200>;
 304                                 interrupts = <17>;
 305                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 306                                 fsl,usbmisc = <&usbmisc 3>;
 307                                 status = "disabled";
 308                         };
 309
 310                         usbmisc: usbmisc@53f80800 {
 311                                 #index-cells = <1>;
 312                                 compatible = "fsl,imx53-usbmisc";
 313                                 reg = <0x53f80800 0x200>;
 314                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 315                         };
 316
 317                         gpio1: gpio@53f84000 {
 318                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 319                                 reg = <0x53f84000 0x4000>;
 320                                 interrupts = <50 51>;
 321                                 gpio-controller;
 322                                 #gpio-cells = <2>;
 323                                 interrupt-controller;
 324                                 #interrupt-cells = <2>;
 325                         };
 326
 327                         gpio2: gpio@53f88000 {
 328                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 329                                 reg = <0x53f88000 0x4000>;
 330                                 interrupts = <52 53>;
 331                                 gpio-controller;
 332                                 #gpio-cells = <2>;
 333                                 interrupt-controller;
 334                                 #interrupt-cells = <2>;
 335                         };
 336
 337                         gpio3: gpio@53f8c000 {
 338                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 339                                 reg = <0x53f8c000 0x4000>;
 340                                 interrupts = <54 55>;
 341                                 gpio-controller;
 342                                 #gpio-cells = <2>;
 343                                 interrupt-controller;
 344                                 #interrupt-cells = <2>;
 345                         };
 346
 347                         gpio4: gpio@53f90000 {
 348                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 349                                 reg = <0x53f90000 0x4000>;
 350                                 interrupts = <56 57>;
 351                                 gpio-controller;
 352                                 #gpio-cells = <2>;
 353                                 interrupt-controller;
 354                                 #interrupt-cells = <2>;
 355                         };
 356
 357                         kpp: kpp@53f94000 {
 358                                 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
 359                                 reg = <0x53f94000 0x4000>;
 360                                 interrupts = <60>;
 361                                 clocks = <&clks IMX5_CLK_DUMMY>;
 362                                 status = "disabled";
 363                         };
 364
 365                         wdog1: wdog@53f98000 {
 366                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 367                                 reg = <0x53f98000 0x4000>;
 368                                 interrupts = <58>;
 369                                 clocks = <&clks IMX5_CLK_DUMMY>;
 370                         };
 371
 372                         wdog2: wdog@53f9c000 {
 373                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 374                                 reg = <0x53f9c000 0x4000>;
 375                                 interrupts = <59>;
 376                                 clocks = <&clks IMX5_CLK_DUMMY>;
 377                                 status = "disabled";
 378                         };
 379
 380                         gpt: timer@53fa0000 {
 381                                 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
 382                                 reg = <0x53fa0000 0x4000>;
 383                                 interrupts = <39>;
 384                                 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
 385                                          <&clks IMX5_CLK_GPT_HF_GATE>;
 386                                 clock-names = "ipg", "per";
 387                         };
 388
 389                         iomuxc: iomuxc@53fa8000 {
 390                                 compatible = "fsl,imx53-iomuxc";
 391                                 reg = <0x53fa8000 0x4000>;
 392                         };
 393
 394                         gpr: iomuxc-gpr@53fa8000 {
 395                                 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
 396                                 reg = <0x53fa8000 0xc>;
 397                         };
 398
 399                         ldb: ldb@53fa8008 {
 400                                 #address-cells = <1>;
 401                                 #size-cells = <0>;
 402                                 compatible = "fsl,imx53-ldb";
 403                                 reg = <0x53fa8008 0x4>;
 404                                 gpr = <&gpr>;
 405                                 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
 406                                          <&clks IMX5_CLK_LDB_DI1_SEL>,
 407                                          <&clks IMX5_CLK_IPU_DI0_SEL>,
 408                                          <&clks IMX5_CLK_IPU_DI1_SEL>,
 409                                          <&clks IMX5_CLK_LDB_DI0_GATE>,
 410                                          <&clks IMX5_CLK_LDB_DI1_GATE>;
 411                                 clock-names = "di0_pll", "di1_pll",
 412                                               "di0_sel", "di1_sel",
 413                                               "di0", "di1";
 414                                 status = "disabled";
 415
 416                                 lvds-channel@0 {
 417                                         reg = <0>;
 418                                         status = "disabled";
 419
 420                                         port {
 421                                                 lvds0_in: endpoint {
 422                                                         remote-endpoint = <&ipu_di0_lvds0>;
 423                                                 };
 424                                         };
 425                                 };
 426
 427                                 lvds-channel@1 {
 428                                         reg = <1>;
 429                                         status = "disabled";
 430
 431                                         port {
 432                                                 lvds1_in: endpoint {
 433                                                         remote-endpoint = <&ipu_di0_lvds0>;
 434                                                 };
 435                                         };
 436                                 };
 437                         };
 438
 439                         pwm1: pwm@53fb4000 {
 440                                 #pwm-cells = <2>;
 441                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 442                                 reg = <0x53fb4000 0x4000>;
 443                                 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
 444                                          <&clks IMX5_CLK_PWM1_HF_GATE>;
 445                                 clock-names = "ipg", "per";
 446                                 interrupts = <61>;
 447                         };
 448
 449                         pwm2: pwm@53fb8000 {
 450                                 #pwm-cells = <2>;
 451                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 452                                 reg = <0x53fb8000 0x4000>;
 453                                 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
 454                                          <&clks IMX5_CLK_PWM2_HF_GATE>;
 455                                 clock-names = "ipg", "per";
 456                                 interrupts = <94>;
 457                         };
 458
 459                         uart1: serial@53fbc000 {
 460                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 461                                 reg = <0x53fbc000 0x4000>;
 462                                 interrupts = <31>;
 463                                 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
 464                                          <&clks IMX5_CLK_UART1_PER_GATE>;
 465                                 clock-names = "ipg", "per";
 466                                 status = "disabled";
 467                         };
 468
 469                         uart2: serial@53fc0000 {
 470                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 471                                 reg = <0x53fc0000 0x4000>;
 472                                 interrupts = <32>;
 473                                 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
 474                                          <&clks IMX5_CLK_UART2_PER_GATE>;
 475                                 clock-names = "ipg", "per";
 476                                 status = "disabled";
 477                         };
 478
 479                         can1: can@53fc8000 {
 480                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 481                                 reg = <0x53fc8000 0x4000>;
 482                                 interrupts = <82>;
 483                                 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
 484                                          <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
 485                                 clock-names = "ipg", "per";
 486                                 status = "disabled";
 487                         };
 488
 489                         can2: can@53fcc000 {
 490                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 491                                 reg = <0x53fcc000 0x4000>;
 492                                 interrupts = <83>;
 493                                 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
 494                                          <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
 495                                 clock-names = "ipg", "per";
 496                                 status = "disabled";
 497                         };
 498
 499                         src: src@53fd0000 {
 500                                 compatible = "fsl,imx53-src", "fsl,imx51-src";
 501                                 reg = <0x53fd0000 0x4000>;
 502                                 #reset-cells = <1>;
 503                         };
 504
 505                         clks: ccm@53fd4000{
 506                                 compatible = "fsl,imx53-ccm";
 507                                 reg = <0x53fd4000 0x4000>;
 508                                 interrupts = <0 71 0x04 0 72 0x04>;
 509                                 #clock-cells = <1>;
 510                         };
 511
 512                         gpio5: gpio@53fdc000 {
 513                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 514                                 reg = <0x53fdc000 0x4000>;
 515                                 interrupts = <103 104>;
 516                                 gpio-controller;
 517                                 #gpio-cells = <2>;
 518                                 interrupt-controller;
 519                                 #interrupt-cells = <2>;
 520                         };
 521
 522                         gpio6: gpio@53fe0000 {
 523                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 524                                 reg = <0x53fe0000 0x4000>;
 525                                 interrupts = <105 106>;
 526                                 gpio-controller;
 527                                 #gpio-cells = <2>;
 528                                 interrupt-controller;
 529                                 #interrupt-cells = <2>;
 530                         };
 531
 532                         gpio7: gpio@53fe4000 {
 533                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 534                                 reg = <0x53fe4000 0x4000>;
 535                                 interrupts = <107 108>;
 536                                 gpio-controller;
 537                                 #gpio-cells = <2>;
 538                                 interrupt-controller;
 539                                 #interrupt-cells = <2>;
 540                         };
 541
 542                         i2c3: i2c@53fec000 {
 543                                 #address-cells = <1>;
 544                                 #size-cells = <0>;
 545                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 546                                 reg = <0x53fec000 0x4000>;
 547                                 interrupts = <64>;
 548                                 clocks = <&clks IMX5_CLK_I2C3_GATE>;
 549                                 status = "disabled";
 550                         };
 551
 552                         uart4: serial@53ff0000 {
 553                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 554                                 reg = <0x53ff0000 0x4000>;
 555                                 interrupts = <13>;
 556                                 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
 557                                          <&clks IMX5_CLK_UART4_PER_GATE>;
 558                                 clock-names = "ipg", "per";
 559                                 status = "disabled";
 560                         };
 561                 };
 562
 563                 aips@60000000 { /* AIPS2 */
 564                         compatible = "fsl,aips-bus", "simple-bus";
 565                         #address-cells = <1>;
 566                         #size-cells = <1>;
 567                         reg = <0x60000000 0x10000000>;
 568                         ranges;
 569
 570                         iim: iim@63f98000 {
 571                                 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
 572                                 reg = <0x63f98000 0x4000>;
 573                                 interrupts = <69>;
 574                                 clocks = <&clks IMX5_CLK_IIM_GATE>;
 575                         };
 576
 577                         uart5: serial@63f90000 {
 578                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 579                                 reg = <0x63f90000 0x4000>;
 580                                 interrupts = <86>;
 581                                 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
 582                                          <&clks IMX5_CLK_UART5_PER_GATE>;
 583                                 clock-names = "ipg", "per";
 584                                 status = "disabled";
 585                         };
 586
 587                         owire: owire@63fa4000 {
 588                                 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
 589                                 reg = <0x63fa4000 0x4000>;
 590                                 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
 591                                 status = "disabled";
 592                         };
 593
 594                         ecspi2: ecspi@63fac000 {
 595                                 #address-cells = <1>;
 596                                 #size-cells = <0>;
 597                                 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 598                                 reg = <0x63fac000 0x4000>;
 599                                 interrupts = <37>;
 600                                 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
 601                                          <&clks IMX5_CLK_ECSPI2_PER_GATE>;
 602                                 clock-names = "ipg", "per";
 603                                 status = "disabled";
 604                         };
 605
 606                         sdma: sdma@63fb0000 {
 607                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
 608                                 reg = <0x63fb0000 0x4000>;
 609                                 interrupts = <6>;
 610                                 clocks = <&clks IMX5_CLK_SDMA_GATE>,
 611                                          <&clks IMX5_CLK_SDMA_GATE>;
 612                                 clock-names = "ipg", "ahb";
 613                                 #dma-cells = <3>;
 614                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
 615                         };
 616
 617                         cspi: cspi@63fc0000 {
 618                                 #address-cells = <1>;
 619                                 #size-cells = <0>;
 620                                 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
 621                                 reg = <0x63fc0000 0x4000>;
 622                                 interrupts = <38>;
 623                                 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
 624                                          <&clks IMX5_CLK_CSPI_IPG_GATE>;
 625                                 clock-names = "ipg", "per";
 626                                 status = "disabled";
 627                         };
 628
 629                         i2c2: i2c@63fc4000 {
 630                                 #address-cells = <1>;
 631                                 #size-cells = <0>;
 632                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 633                                 reg = <0x63fc4000 0x4000>;
 634                                 interrupts = <63>;
 635                                 clocks = <&clks IMX5_CLK_I2C2_GATE>;
 636                                 status = "disabled";
 637                         };
 638
 639                         i2c1: i2c@63fc8000 {
 640                                 #address-cells = <1>;
 641                                 #size-cells = <0>;
 642                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 643                                 reg = <0x63fc8000 0x4000>;
 644                                 interrupts = <62>;
 645                                 clocks = <&clks IMX5_CLK_I2C1_GATE>;
 646                                 status = "disabled";
 647                         };
 648
 649                         ssi1: ssi@63fcc000 {
 650                                 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
 651                                                 "fsl,imx21-ssi";
 652                                 reg = <0x63fcc000 0x4000>;
 653                                 interrupts = <29>;
 654                                 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
 655                                 dmas = <&sdma 28 0 0>,
 656                                        <&sdma 29 0 0>;
 657                                 dma-names = "rx", "tx";
 658                                 fsl,fifo-depth = <15>;
 659                                 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
 660                                 status = "disabled";
 661                         };
 662
 663                         audmux: audmux@63fd0000 {
 664                                 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
 665                                 reg = <0x63fd0000 0x4000>;
 666                                 status = "disabled";
 667                         };
 668
 669                         nfc: nand@63fdb000 {
 670                                 compatible = "fsl,imx53-nand";
 671                                 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
 672                                 interrupts = <8>;
 673                                 clocks = <&clks IMX5_CLK_NFC_GATE>;
 674                                 status = "disabled";
 675                         };
 676
 677                         ssi3: ssi@63fe8000 {
 678                                 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
 679                                                 "fsl,imx21-ssi";
 680                                 reg = <0x63fe8000 0x4000>;
 681                                 interrupts = <96>;
 682                                 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
 683                                 dmas = <&sdma 46 0 0>,
 684                                        <&sdma 47 0 0>;
 685                                 dma-names = "rx", "tx";
 686                                 fsl,fifo-depth = <15>;
 687                                 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
 688                                 status = "disabled";
 689                         };
 690
 691                         fec: ethernet@63fec000 {
 692                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 693                                 reg = <0x63fec000 0x4000>;
 694                                 interrupts = <87>;
 695                                 clocks = <&clks IMX5_CLK_FEC_GATE>,
 696                                          <&clks IMX5_CLK_FEC_GATE>,
 697                                          <&clks IMX5_CLK_FEC_GATE>;
 698                                 clock-names = "ipg", "ahb", "ptp";
 699                                 status = "disabled";
 700                         };
 701
 702                         tve: tve@63ff0000 {
 703                                 compatible = "fsl,imx53-tve";
 704                                 reg = <0x63ff0000 0x1000>;
 705                                 interrupts = <92>;
 706                                 clocks = <&clks IMX5_CLK_TVE_GATE>,
 707                                          <&clks IMX5_CLK_IPU_DI1_SEL>;
 708                                 clock-names = "tve", "di_sel";
 709                                 status = "disabled";
 710
 711                                 port {
 712                                         tve_in: endpoint {
 713                                                 remote-endpoint = <&ipu_di1_tve>;
 714                                         };
 715                                 };
 716                         };
 717
 718                         vpu: vpu@63ff4000 {
 719                                 compatible = "fsl,imx53-vpu";
 720                                 reg = <0x63ff4000 0x1000>;
 721                                 interrupts = <9>;
 722                                 clocks = <&clks IMX5_CLK_VPU_GATE>,
 723                                          <&clks IMX5_CLK_VPU_GATE>;
 724                                 clock-names = "per", "ahb";
 725                                 iram = <&ocram>;
 726                                 status = "disabled";
 727                         };
 728                 };
 729
 730                 ocram: sram@f8000000 {
 731                         compatible = "mmio-sram";
 732                         reg = <0xf8000000 0x20000>;
 733                         clocks = <&clks IMX5_CLK_OCRAM>;
 734                 };
 735         };
 736 };