arch/arm/boot/dts/imx53-mba53.dts

   1 /*
   2  * Copyright 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
   3  * Copyright 2012 Steffen Trumtrar <s.trumtrar@pengutronix.de>, Pengutronix
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 /dts-v1/;
  14 #include "imx53-tqma53.dtsi"
  15
  16 / {
  17         model = "TQ MBa53 starter kit";
  18         compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
  19
  20         backlight {
  21                 compatible = "pwm-backlight";
  22                 pwms = <&pwm2 0 50000>;
  23                 brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
  24                 default-brightness-level = <10>;
  25                 enable-gpios = <&gpio7 7 0>;
  26                 power-supply = <&reg_backlight>;
  27         };
  28
  29         disp1: display@disp1 {
  30                 compatible = "fsl,imx-parallel-display";
  31                 pinctrl-names = "default";
  32                 pinctrl-0 = <&pinctrl_disp1_1>;
  33                 interface-pix-fmt = "rgb24";
  34                 status = "disabled";
  35
  36                 port {
  37                         display1_in: endpoint {
  38                                 remote-endpoint = <&ipu_di1_disp1>;
  39                         };
  40                 };
  41         };
  42
  43         regulators {
  44                 compatible = "simple-bus";
  45                 #address-cells = <1>;
  46                 #size-cells = <0>;
  47
  48                 reg_backlight: regulator@0 {
  49                         compatible = "regulator-fixed";
  50                         reg = <0>;
  51                         regulator-name = "lcd-supply";
  52                         gpio = <&gpio2 5 0>;
  53                         startup-delay-us = <5000>;
  54                 };
  55
  56                 reg_3p2v: regulator@1 {
  57                         compatible = "regulator-fixed";
  58                         reg = <1>;
  59                         regulator-name = "3P2V";
  60                         regulator-min-microvolt = <3200000>;
  61                         regulator-max-microvolt = <3200000>;
  62                         regulator-always-on;
  63                 };
  64         };
  65
  66         sound {
  67                 compatible = "tq,imx53-mba53-sgtl5000",
  68                              "fsl,imx-audio-sgtl5000";
  69                 model = "imx53-mba53-sgtl5000";
  70                 ssi-controller = <&ssi2>;
  71                 audio-codec = <&codec>;
  72                 audio-routing =
  73                         "MIC_IN", "Mic Jack",
  74                         "Mic Jack", "Mic Bias",
  75                         "Headphone Jack", "HP_OUT";
  76                 mux-int-port = <2>;
  77                 mux-ext-port = <5>;
  78         };
  79 };
  80
  81 &ldb {
  82         pinctrl-names = "default";
  83         pinctrl-0 = <&pinctrl_lvds1_1>;
  84         status = "disabled";
  85 };
  86
  87 &iomuxc {
  88         lvds1 {
  89                 pinctrl_lvds1_1: lvds1-grp1 {
  90                         fsl,pins = <
  91                                 MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
  92                                 MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
  93                                 MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
  94                                 MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
  95                                 MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
  96                         >;
  97                 };
  98
  99                 pinctrl_lvds1_2: lvds1-grp2 {
 100                         fsl,pins = <
 101                                 MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
 102                                 MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
 103                                 MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
 104                                 MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
 105                                 MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
 106                         >;
 107                 };
 108         };
 109
 110         disp1 {
 111                 pinctrl_disp1_1: disp1-grp1 {
 112                         fsl,pins = <
 113                                 MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
 114                                 MX53_PAD_EIM_DA10__IPU_DI1_PIN15   0x80000000 /* DISP1_DRDY */
 115                                 MX53_PAD_EIM_D23__IPU_DI1_PIN2     0x80000000 /* DISP1_HSYNC */
 116                                 MX53_PAD_EIM_EB3__IPU_DI1_PIN3     0x80000000 /* DISP1_VSYNC */
 117                                 MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
 118                                 MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
 119                                 MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
 120                                 MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
 121                                 MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
 122                                 MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
 123                                 MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
 124                                 MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
 125                                 MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
 126                                 MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
 127                                 MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
 128                                 MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
 129                                 MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
 130                                 MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
 131                                 MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9  0x80000000
 132                                 MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8  0x80000000
 133                                 MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7  0x80000000
 134                                 MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6  0x80000000
 135                                 MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5  0x80000000
 136                                 MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4  0x80000000
 137                                 MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3  0x80000000
 138                                 MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2  0x80000000
 139                                 MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1  0x80000000
 140                                 MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0  0x80000000
 141                         >;
 142                 };
 143         };
 144
 145         tve {
 146                 pinctrl_vga_sync_1: vgasync-grp1 {
 147                         fsl,pins = <
 148                                 /* VGA_VSYNC, HSYNC with max drive strength */
 149                                 MX53_PAD_EIM_CS1__IPU_DI1_PIN6     0xe6
 150                                 MX53_PAD_EIM_DA15__IPU_DI1_PIN4    0xe6
 151                         >;
 152                 };
 153         };
 154 };
 155
 156 &ipu_di1_disp1 {
 157         remote-endpoint = <&display1_in>;
 158 };
 159
 160 &cspi {
 161         status = "okay";
 162 };
 163
 164 &audmux {
 165         status = "okay";
 166         pinctrl-names = "default";
 167         pinctrl-0 = <&pinctrl_audmux>;
 168 };
 169
 170 &i2c2 {
 171         codec: sgtl5000@a {
 172                 compatible = "fsl,sgtl5000";
 173                 reg = <0x0a>;
 174                 clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
 175                 VDDA-supply = <&reg_3p2v>;
 176                 VDDIO-supply = <&reg_3p2v>;
 177         };
 178
 179         expander: pca9554@20 {
 180                 compatible = "pca9554";
 181                 reg = <0x20>;
 182                 interrupts = <109>;
 183                 #gpio-cells = <2>;
 184                 gpio-controller;
 185         };
 186
 187         sensor2: lm75@49 {
 188                 compatible = "lm75";
 189                 reg = <0x49>;
 190         };
 191 };
 192
 193 &fec {
 194         phy-reset-gpios = <&gpio7 6 0>;
 195         status = "okay";
 196 };
 197
 198 &esdhc2 {
 199         status = "okay";
 200 };
 201
 202 &uart3 {
 203         status = "okay";
 204 };
 205
 206 &ecspi1 {
 207         status = "okay";
 208 };
 209
 210 &usbotg {
 211         dr_mode = "host";
 212         status = "okay";
 213 };
 214
 215 &usbh1 {
 216         status = "okay";
 217 };
 218
 219 &uart1 {
 220         status = "okay";
 221 };
 222
 223 &ssi2 {
 224         fsl,mode = "i2s-slave";
 225         status = "okay";
 226 };
 227
 228 &uart2 {
 229         status = "okay";
 230 };
 231
 232 &can1 {
 233         status = "okay";
 234 };
 235
 236 &can2 {
 237         status = "okay";
 238 };
 239
 240 &i2c3 {
 241         status = "okay";
 242 };
 243
 244 &tve {
 245         pinctrl-names = "default";
 246         pinctrl-0 = <&pinctrl_vga_sync_1>;
 247         i2c-ddc-bus = <&i2c3>;
 248         fsl,tve-mode = "vga";
 249         fsl,hsync-pin = <4>;
 250         fsl,vsync-pin = <6>;
 251         status = "okay";
 252 };