arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts

   1 /*
   2  * The code contained herein is licensed under the GNU General Public
   3  * License. You may obtain a copy of the GNU General Public License
   4  * Version 2 or later at the following locations:
   5  *
   6  * http://www.opensource.org/licenses/gpl-license.html
   7  * http://www.gnu.org/copyleft/gpl.html
   8  */
   9
  10 #include "imx27-phytec-phycore-som.dtsi"
  11
  12 / {
  13         model = "Phytec pcm970";
  14         compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27";
  15 };
  16
  17 &cspi1 {
  18         fsl,spi-num-chipselects = <2>;
  19         cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
  20                    <&gpio4 27 GPIO_ACTIVE_LOW>;
  21 };
  22
  23 &i2c1 {
  24         clock-frequency = <400000>;
  25         pinctrl-names = "default";
  26         pinctrl-0 = <&pinctrl_i2c1>;
  27         status = "okay";
  28
  29         camgpio: pca9536@41 {
  30                 compatible = "nxp,pca9536";
  31                 reg = <0x41>;
  32                 gpio-controller;
  33                 #gpio-cells = <2>;
  34         };
  35 };
  36
  37 &iomuxc {
  38         imx27_phycore_rdk {
  39                 pinctrl_i2c1: i2c1grp {
  40                         /* Add pullup to DATA line */
  41                         fsl,pins = <
  42                                 MX27_PAD_I2C_DATA__I2C_DATA     0x1
  43                                 MX27_PAD_I2C_CLK__I2C_CLK       0x0
  44                         >;
  45                 };
  46
  47                 pinctrl_owire1: owire1grp {
  48                         fsl,pins = <
  49                                 MX27_PAD_RTCK__OWIRE 0x0
  50                         >;
  51                 };
  52
  53                 pinctrl_sdhc2: sdhc2grp {
  54                         fsl,pins = <
  55                                 MX27_PAD_SD2_CLK__SD2_CLK 0x0
  56                                 MX27_PAD_SD2_CMD__SD2_CMD 0x0
  57                                 MX27_PAD_SD2_D0__SD2_D0 0x0
  58                                 MX27_PAD_SD2_D1__SD2_D1 0x0
  59                                 MX27_PAD_SD2_D2__SD2_D2 0x0
  60                                 MX27_PAD_SD2_D3__SD2_D3 0x0
  61                                 MX27_PAD_SSI3_FS__GPIO3_28      0x0 /* WP */
  62                                 MX27_PAD_SSI3_RXDAT__GPIO3_29   0x0 /* CD */
  63                         >;
  64                 };
  65
  66                 pinctrl_uart1: uart1grp {
  67                         fsl,pins = <
  68                                 MX27_PAD_UART1_TXD__UART1_TXD 0x0
  69                                 MX27_PAD_UART1_RXD__UART1_RXD 0x0
  70                                 MX27_PAD_UART1_CTS__UART1_CTS 0x0
  71                                 MX27_PAD_UART1_RTS__UART1_RTS 0x0
  72                         >;
  73                 };
  74
  75                 pinctrl_uart2: uart2grp {
  76                         fsl,pins = <
  77                                 MX27_PAD_UART2_TXD__UART2_TXD 0x0
  78                                 MX27_PAD_UART2_RXD__UART2_RXD 0x0
  79                                 MX27_PAD_UART2_CTS__UART2_CTS 0x0
  80                                 MX27_PAD_UART2_RTS__UART2_RTS 0x0
  81                         >;
  82                 };
  83
  84                 pinctrl_usbh2: usbh2grp {
  85                         fsl,pins = <
  86                                 MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
  87                                 MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
  88                                 MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
  89                                 MX27_PAD_USBH2_STP__USBH2_STP 0x0
  90                                 MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
  91                                 MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
  92                                 MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
  93                                 MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
  94                                 MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
  95                                 MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
  96                                 MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
  97                                 MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
  98                         >;
  99                 };
 100
 101                 pinctrl_weim: weimgrp {
 102                         fsl,pins = <
 103                                 MX27_PAD_CS4_B__CS4_B           0x0 /* CS4 */
 104                                 MX27_PAD_SD1_D1__GPIO5_19       0x0 /* CAN IRQ */
 105                         >;
 106                 };
 107         };
 108 };
 109
 110 &owire {
 111         pinctrl-names = "default";
 112         pinctrl-0 = <&pinctrl_owire1>;
 113         status = "okay";
 114 };
 115
 116 &pmicleds {
 117         ledr1: led@3 {
 118                 reg = <3>;
 119                 label = "system:red1:user";
 120         };
 121
 122         ledg1: led@4 {
 123                 reg = <4>;
 124                 label = "system:green1:user";
 125         };
 126
 127         ledb1: led@5 {
 128                 reg = <5>;
 129                 label = "system:blue1:user";
 130         };
 131
 132         ledr2: led@6 {
 133                 reg = <6>;
 134                 label = "system:red2:user";
 135         };
 136
 137         ledg2: led@7 {
 138                 reg = <7>;
 139                 label = "system:green2:user";
 140         };
 141
 142         ledb2: led@8 {
 143                 reg = <8>;
 144                 label = "system:blue2:user";
 145         };
 146
 147         ledr3: led@9 {
 148                 reg = <9>;
 149                 label = "system:red3:nand";
 150                 linux,default-trigger = "nand-disk";
 151         };
 152
 153         ledg3: led@10 {
 154                 reg = <10>;
 155                 label = "system:green3:live";
 156                 linux,default-trigger = "heartbeat";
 157         };
 158
 159         ledb3: led@11 {
 160                 reg = <11>;
 161                 label = "system:blue3:cpu";
 162                 linux,default-trigger = "cpu0";
 163         };
 164 };
 165
 166 &sdhci2 {
 167         pinctrl-names = "default";
 168         pinctrl-0 = <&pinctrl_sdhc2>;
 169         bus-width = <4>;
 170         cd-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
 171         wp-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
 172         vmmc-supply = <&vmmc1_reg>;
 173         status = "okay";
 174 };
 175
 176 &uart1 {
 177         fsl,uart-has-rtscts;
 178         pinctrl-names = "default";
 179         pinctrl-0 = <&pinctrl_uart1>;
 180         status = "okay";
 181 };
 182
 183 &uart2 {
 184         fsl,uart-has-rtscts;
 185         pinctrl-names = "default";
 186         pinctrl-0 = <&pinctrl_uart2>;
 187         status = "okay";
 188 };
 189
 190 &usbh2 {
 191         pinctrl-names = "default";
 192         pinctrl-0 = <&pinctrl_usbh2>;
 193         dr_mode = "host";
 194         phy_type = "ulpi";
 195         vbus-supply = <&reg_5v0>;
 196         disable-over-current;
 197         status = "okay";
 198 };
 199
 200 &usbphy2 {
 201         vcc-supply = <&reg_5v0>;
 202 };
 203
 204 &weim {
 205         pinctrl-names = "default";
 206         pinctrl-0 = <&pinctrl_weim>;
 207
 208         can@d4000000 {
 209                 compatible = "nxp,sja1000";
 210                 reg = <4 0x00000000 0x00000100>;
 211                 interrupt-parent = <&gpio5>;
 212                 interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
 213                 nxp,external-clock-frequency = <16000000>;
 214                 nxp,tx-output-config = <0x16>;
 215                 nxp,no-comparator-bypass;
 216                 fsl,weim-cs-timing = <0x0000dcf6 0x444a0301 0x44443302>;
 217         };
 218 };