arch/arm/boot/dts/exynos4x12.dtsi

   1 /*
   2  * Samsung's Exynos4x12 SoCs device tree source
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
   8  * based board files can include this file and provide values for board specfic
   9  * bindings.
  10  *
  11  * Note: This file does not include device nodes for all the controllers in
  12  * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
  13  * nodes can be added to this file.
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18 */
  19
  20 #include "exynos4.dtsi"
  21 #include "exynos4x12-pinctrl.dtsi"
  22
  23 / {
  24         aliases {
  25                 pinctrl0 = &pinctrl_0;
  26                 pinctrl1 = &pinctrl_1;
  27                 pinctrl2 = &pinctrl_2;
  28                 pinctrl3 = &pinctrl_3;
  29                 fimc-lite0 = &fimc_lite_0;
  30                 fimc-lite1 = &fimc_lite_1;
  31                 mshc0 = &mshc_0;
  32         };
  33
  34         pmu {
  35                 compatible = "arm,cortex-a9-pmu";
  36                 interrupt-parent = <&combiner>;
  37                 interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
  38         };
  39
  40         pd_isp: isp-power-domain@10023CA0 {
  41                 compatible = "samsung,exynos4210-pd";
  42                 reg = <0x10023CA0 0x20>;
  43         };
  44
  45         clock: clock-controller@10030000 {
  46                 compatible = "samsung,exynos4412-clock";
  47                 reg = <0x10030000 0x20000>;
  48                 #clock-cells = <1>;
  49         };
  50
  51         mct@10050000 {
  52                 compatible = "samsung,exynos4412-mct";
  53                 reg = <0x10050000 0x800>;
  54                 interrupt-parent = <&mct_map>;
  55                 interrupts = <0>, <1>, <2>, <3>, <4>;
  56                 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
  57                 clock-names = "fin_pll", "mct";
  58
  59                 mct_map: mct-map {
  60                         #interrupt-cells = <1>;
  61                         #address-cells = <0>;
  62                         #size-cells = <0>;
  63                         interrupt-map = <0 &gic 0 57 0>,
  64                                         <1 &combiner 12 5>,
  65                                         <2 &combiner 12 6>,
  66                                         <3 &combiner 12 7>,
  67                                         <4 &gic 1 12 0>;
  68                 };
  69         };
  70
  71         combiner: interrupt-controller@10440000 {
  72                 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
  73                              <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
  74                              <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
  75                              <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
  76                              <0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
  77         };
  78
  79         pinctrl_0: pinctrl@11400000 {
  80                 compatible = "samsung,exynos4x12-pinctrl";
  81                 reg = <0x11400000 0x1000>;
  82                 interrupts = <0 47 0>;
  83         };
  84
  85         pinctrl_1: pinctrl@11000000 {
  86                 compatible = "samsung,exynos4x12-pinctrl";
  87                 reg = <0x11000000 0x1000>;
  88                 interrupts = <0 46 0>;
  89
  90                 wakup_eint: wakeup-interrupt-controller {
  91                         compatible = "samsung,exynos4210-wakeup-eint";
  92                         interrupt-parent = <&gic>;
  93                         interrupts = <0 32 0>;
  94                 };
  95         };
  96
  97         adc: adc@126C0000 {
  98                 compatible = "samsung,exynos-adc-v1";
  99                 reg = <0x126C0000 0x100>, <0x10020718 0x4>;
 100                 interrupt-parent = <&combiner>;
 101                 interrupts = <10 3>;
 102                 clocks = <&clock CLK_TSADC>;
 103                 clock-names = "adc";
 104                 #io-channel-cells = <1>;
 105                 io-channel-ranges;
 106                 status = "disabled";
 107         };
 108
 109         pinctrl_2: pinctrl@03860000 {
 110                 compatible = "samsung,exynos4x12-pinctrl";
 111                 reg = <0x03860000 0x1000>;
 112                 interrupt-parent = <&combiner>;
 113                 interrupts = <10 0>;
 114         };
 115
 116         pinctrl_3: pinctrl@106E0000 {
 117                 compatible = "samsung,exynos4x12-pinctrl";
 118                 reg = <0x106E0000 0x1000>;
 119                 interrupts = <0 72 0>;
 120         };
 121
 122         g2d@10800000 {
 123                 compatible = "samsung,exynos4212-g2d";
 124                 reg = <0x10800000 0x1000>;
 125                 interrupts = <0 89 0>;
 126                 clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
 127                 clock-names = "sclk_fimg2d", "fimg2d";
 128                 status = "disabled";
 129         };
 130
 131         camera {
 132                 clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
 133                          <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
 134                 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
 135
 136                 fimc_0: fimc@11800000 {
 137                         compatible = "samsung,exynos4212-fimc";
 138                         samsung,pix-limits = <4224 8192 1920 4224>;
 139                         samsung,mainscaler-ext;
 140                         samsung,isp-wb;
 141                         samsung,cam-if;
 142                 };
 143
 144                 fimc_1: fimc@11810000 {
 145                         compatible = "samsung,exynos4212-fimc";
 146                         samsung,pix-limits = <4224 8192 1920 4224>;
 147                         samsung,mainscaler-ext;
 148                         samsung,isp-wb;
 149                         samsung,cam-if;
 150                 };
 151
 152                 fimc_2: fimc@11820000 {
 153                         compatible = "samsung,exynos4212-fimc";
 154                         samsung,pix-limits = <4224 8192 1920 4224>;
 155                         samsung,mainscaler-ext;
 156                         samsung,isp-wb;
 157                         samsung,lcd-wb;
 158                         samsung,cam-if;
 159                 };
 160
 161                 fimc_3: fimc@11830000 {
 162                         compatible = "samsung,exynos4212-fimc";
 163                         samsung,pix-limits = <1920 8192 1366 1920>;
 164                         samsung,rotators = <0>;
 165                         samsung,mainscaler-ext;
 166                         samsung,isp-wb;
 167                         samsung,lcd-wb;
 168                 };
 169
 170                 fimc_lite_0: fimc-lite@12390000 {
 171                         compatible = "samsung,exynos4212-fimc-lite";
 172                         reg = <0x12390000 0x1000>;
 173                         interrupts = <0 105 0>;
 174                         samsung,power-domain = <&pd_isp>;
 175                         clocks = <&clock CLK_FIMC_LITE0>;
 176                         clock-names = "flite";
 177                         status = "disabled";
 178                 };
 179
 180                 fimc_lite_1: fimc-lite@123A0000 {
 181                         compatible = "samsung,exynos4212-fimc-lite";
 182                         reg = <0x123A0000 0x1000>;
 183                         interrupts = <0 106 0>;
 184                         samsung,power-domain = <&pd_isp>;
 185                         clocks = <&clock CLK_FIMC_LITE1>;
 186                         clock-names = "flite";
 187                         status = "disabled";
 188                 };
 189
 190                 fimc_is: fimc-is@12000000 {
 191                         compatible = "samsung,exynos4212-fimc-is", "simple-bus";
 192                         reg = <0x12000000 0x260000>;
 193                         interrupts = <0 90 0>, <0 95 0>;
 194                         samsung,power-domain = <&pd_isp>;
 195                         clocks = <&clock CLK_FIMC_LITE0>,
 196                                  <&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
 197                                  <&clock CLK_PPMUISPMX>,
 198                                  <&clock CLK_MOUT_MPLL_USER_T>,
 199                                  <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
 200                                  <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
 201                                  <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
 202                                  <&clock CLK_DIV_MCUISP0>,
 203                                  <&clock CLK_DIV_MCUISP1>,
 204                                  <&clock CLK_SCLK_UART_ISP>,
 205                                  <&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
 206                                  <&clock CLK_ACLK400_MCUISP>,
 207                                  <&clock CLK_DIV_ACLK400_MCUISP>;
 208                         clock-names = "lite0", "lite1", "ppmuispx",
 209                                       "ppmuispmx", "mpll", "isp",
 210                                       "drc", "fd", "mcuisp",
 211                                       "ispdiv0", "ispdiv1", "mcuispdiv0",
 212                                       "mcuispdiv1", "uart", "aclk200",
 213                                       "div_aclk200", "aclk400mcuisp",
 214                                       "div_aclk400mcuisp";
 215                         #address-cells = <1>;
 216                         #size-cells = <1>;
 217                         ranges;
 218                         status = "disabled";
 219
 220                         pmu {
 221                                 reg = <0x10020000 0x3000>;
 222                         };
 223
 224                         i2c1_isp: i2c-isp@12140000 {
 225                                 compatible = "samsung,exynos4212-i2c-isp";
 226                                 reg = <0x12140000 0x100>;
 227                                 clocks = <&clock CLK_I2C1_ISP>;
 228                                 clock-names = "i2c_isp";
 229                                 #address-cells = <1>;
 230                                 #size-cells = <0>;
 231                         };
 232                 };
 233         };
 234
 235         mshc_0: mmc@12550000 {
 236                 compatible = "samsung,exynos4412-dw-mshc";
 237                 reg = <0x12550000 0x1000>;
 238                 interrupts = <0 77 0>;
 239                 #address-cells = <1>;
 240                 #size-cells = <0>;
 241                 fifo-depth = <0x80>;
 242                 clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
 243                 clock-names = "biu", "ciu";
 244                 status = "disabled";
 245         };
 246 };