arch/arm/boot/dts/armada-xp-db.dts

   1 /*
   2  * Device Tree file for Marvell Armada XP evaluation board
   3  * (DB-78460-BP)
   4  *
   5  * Copyright (C) 2012-2014 Marvell
   6  *
   7  * Lior Amsalem <alior@marvell.com>
   8  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   9  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2.  This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14   *
  15  * Note: this Device Tree assumes that the bootloader has remapped the
  16  * internal registers to 0xf1000000 (instead of the default
  17  * 0xd0000000). The 0xf1000000 is the default used by the recent,
  18  * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
  19  * boards were delivered with an older version of the bootloader that
  20  * left internal registers mapped at 0xd0000000. If you are in this
  21  * situation, you should either update your bootloader (preferred
  22  * solution) or the below Device Tree should be adjusted.
  23  */
  24
  25 /dts-v1/;
  26 #include "armada-xp-mv78460.dtsi"
  27
  28 / {
  29         model = "Marvell Armada XP Evaluation Board";
  30         compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
  31
  32         chosen {
  33                 bootargs = "console=ttyS0,115200 earlyprintk";
  34         };
  35
  36         memory {
  37                 device_type = "memory";
  38                 reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
  39         };
  40
  41         soc {
  42                 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
  43                           MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
  44                           MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
  45
  46                 devbus-bootcs {
  47                         status = "okay";
  48
  49                         /* Device Bus parameters are required */
  50
  51                         /* Read parameters */
  52                         devbus,bus-width    = <8>;
  53                         devbus,turn-off-ps  = <60000>;
  54                         devbus,badr-skew-ps = <0>;
  55                         devbus,acc-first-ps = <124000>;
  56                         devbus,acc-next-ps  = <248000>;
  57                         devbus,rd-setup-ps  = <0>;
  58                         devbus,rd-hold-ps   = <0>;
  59
  60                         /* Write parameters */
  61                         devbus,sync-enable = <0>;
  62                         devbus,wr-high-ps  = <60000>;
  63                         devbus,wr-low-ps   = <60000>;
  64                         devbus,ale-wr-ps   = <60000>;
  65
  66                         /* NOR 16 MiB */
  67                         nor@0 {
  68                                 compatible = "cfi-flash";
  69                                 reg = <0 0x1000000>;
  70                                 bank-width = <2>;
  71                         };
  72                 };
  73
  74                 pcie-controller {
  75                         status = "okay";
  76
  77                         /*
  78                          * All 6 slots are physically present as
  79                          * standard PCIe slots on the board.
  80                          */
  81                         pcie@1,0 {
  82                                 /* Port 0, Lane 0 */
  83                                 status = "okay";
  84                         };
  85                         pcie@2,0 {
  86                                 /* Port 0, Lane 1 */
  87                                 status = "okay";
  88                         };
  89                         pcie@3,0 {
  90                                 /* Port 0, Lane 2 */
  91                                 status = "okay";
  92                         };
  93                         pcie@4,0 {
  94                                 /* Port 0, Lane 3 */
  95                                 status = "okay";
  96                         };
  97                         pcie@9,0 {
  98                                 /* Port 2, Lane 0 */
  99                                 status = "okay";
 100                         };
 101                         pcie@10,0 {
 102                                 /* Port 3, Lane 0 */
 103                                 status = "okay";
 104                         };
 105                 };
 106
 107                 internal-regs {
 108                         serial@12000 {
 109                                 clock-frequency = <250000000>;
 110                                 status = "okay";
 111                         };
 112                         serial@12100 {
 113                                 clock-frequency = <250000000>;
 114                                 status = "okay";
 115                         };
 116                         serial@12200 {
 117                                 clock-frequency = <250000000>;
 118                                 status = "okay";
 119                         };
 120                         serial@12300 {
 121                                 clock-frequency = <250000000>;
 122                                 status = "okay";
 123                         };
 124
 125                         sata@a0000 {
 126                                 nr-ports = <2>;
 127                                 status = "okay";
 128                         };
 129
 130                         mdio {
 131                                 phy0: ethernet-phy@0 {
 132                                         reg = <0>;
 133                                 };
 134
 135                                 phy1: ethernet-phy@1 {
 136                                         reg = <1>;
 137                                 };
 138
 139                                 phy2: ethernet-phy@2 {
 140                                         reg = <25>;
 141                                 };
 142
 143                                 phy3: ethernet-phy@3 {
 144                                         reg = <27>;
 145                                 };
 146                         };
 147
 148                         ethernet@70000 {
 149                                 status = "okay";
 150                                 phy = <&phy0>;
 151                                 phy-mode = "rgmii-id";
 152                         };
 153                         ethernet@74000 {
 154                                 status = "okay";
 155                                 phy = <&phy1>;
 156                                 phy-mode = "rgmii-id";
 157                         };
 158                         ethernet@30000 {
 159                                 status = "okay";
 160                                 phy = <&phy2>;
 161                                 phy-mode = "sgmii";
 162                         };
 163                         ethernet@34000 {
 164                                 status = "okay";
 165                                 phy = <&phy3>;
 166                                 phy-mode = "sgmii";
 167                         };
 168
 169                         mvsdio@d4000 {
 170                                 pinctrl-0 = <&sdio_pins>;
 171                                 pinctrl-names = "default";
 172                                 status = "okay";
 173                                 /* No CD or WP GPIOs */
 174                                 broken-cd;
 175                         };
 176
 177                         usb@50000 {
 178                                 status = "okay";
 179                         };
 180
 181                         usb@51000 {
 182                                 status = "okay";
 183                         };
 184
 185                         usb@52000 {
 186                                 status = "okay";
 187                         };
 188
 189                         spi0: spi@10600 {
 190                                 status = "okay";
 191
 192                                 spi-flash@0 {
 193                                         #address-cells = <1>;
 194                                         #size-cells = <1>;
 195                                         compatible = "m25p64";
 196                                         reg = <0>; /* Chip select 0 */
 197                                         spi-max-frequency = <20000000>;
 198                                 };
 199                         };
 200                 };
 201         };
 202 };