1 * Core Clock bindings for Marvell MVEBU SoCs
3 Marvell MVEBU SoCs usually allow to determine core clock frequencies by
4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
5 specify the desired clock by having the clock ID in its "clocks" phandle cell.
7 The following is a list of provided IDs and clock names on Armada 370/XP:
8 0 = tclk (Internal Bus clock)
10 2 = nbclk (L2 Cache clock)
11 3 = hclk (DRAM control clock)
12 4 = dramclk (DDR clock)
14 The following is a list of provided IDs and clock names on Armada 375:
15 0 = tclk (Internal Bus clock)
16 1 = cpuclk (CPU clock)
17 2 = l2clk (L2 Cache clock)
18 3 = ddrclk (DDR clock)
20 The following is a list of provided IDs and clock names on Armada 380/385:
21 0 = tclk (Internal Bus clock)
22 1 = cpuclk (CPU clock)
23 2 = l2clk (L2 Cache clock)
24 3 = ddrclk (DDR clock)
26 The following is a list of provided IDs and clock names on Kirkwood and Dove:
27 0 = tclk (Internal Bus clock)
28 1 = cpuclk (CPU0 clock)
29 2 = l2clk (L2 Cache clock derived from CPU0 clock)
30 3 = ddrclk (DDR controller clock derived from CPU0 clock)
33 - compatible : shall be one of the following:
34 "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
35 "marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
36 "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
37 "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
38 "marvell,dove-core-clock" - for Dove SoC core clocks
39 "marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
40 "marvell,mv88f6180-core-clock" - for Kirkwood MV88f6180 SoC
41 - reg : shall be the register address of the Sample-At-Reset (SAR) register
42 - #clock-cells : from common clock binding; shall be set to 1
45 - clock-output-names : from common clock binding; allows overwrite default clock
46 output names ("tclk", "cpuclk", "l2clk", "ddrclk")
50 core_clk: core-clocks@d0214 {
51 compatible = "marvell,dove-core-clock";
57 compatible = "marvell,orion-spi";
59 /* get tclk from core clock provider */
60 clocks = <&core_clk 0>;