clk: tegra: Add closed loop support for the DFLL
authorTuomas Tynkkynen <ttynkkynen@nvidia.com>
Wed, 13 May 2015 14:58:37 +0000 (17:58 +0300)
committerThierry Reding <treding@nvidia.com>
Thu, 16 Jul 2015 07:32:46 +0000 (09:32 +0200)
commitc4fe70ada40f53e8cd5e6f8d9a2433781e935835
treef75f6382424809a9dfc3633e71991dd306e35e67
parentd8d7a08fa82ff7c241c74c2461f342c5685dda27
clk: tegra: Add closed loop support for the DFLL

With closed loop support, the clock rate of the DFLL can be adjusted.

The oscillator itself in the DFLL is a free-running oscillator whose
rate is directly determined the supply voltage. However, the DFLL
module contains logic to compare the DFLL output rate to a fixed
reference clock (51 MHz) and make a decision to either lower or raise
the DFLL supply voltage. The DFLL module can then autonomously change
the supply voltage by communicating with an off-chip PMIC via either I2C
or PWM signals. This driver currently supports only I2C.

Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-dfll.c