linux-drm-fsl-dcu.git
4 years agoMIPS: SEAD3: Convert LED driver to module_platform_driver.
Ralf Baechle [Fri, 27 Mar 2015 20:47:01 +0000 (21:47 +0100)]
MIPS: SEAD3: Convert LED driver to module_platform_driver.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: SEAD3: Collect LED platform device registration in a single file.
Ralf Baechle [Thu, 23 Oct 2014 23:32:25 +0000 (01:32 +0200)]
MIPS: SEAD3: Collect LED platform device registration in a single file.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Bryan Wu <cooloney@gmail.com>
Cc: Richard Purdie <rpurdie@rpsys.net>
Cc: linux-leds@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8203/

4 years agoMIPS: BMIPS: restrict DTB selection to BMIPS_GENERIC
Florian Fainelli [Thu, 26 Mar 2015 04:55:15 +0000 (21:55 -0700)]
MIPS: BMIPS: restrict DTB selection to BMIPS_GENERIC

Since we are always sourcing arch/mips/bmips/Kconfig and there is no
dependency on BMIPS_GENERIC, we will offer building BMIPS-related DTBs
while this is not relevant for the other MIPS platforms.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: cernekee@gmail.com
Cc: jaedon.shin@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/9603/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: BMIPS: Flush the readahead cache after DMA.
Ralf Baechle [Fri, 27 Mar 2015 14:17:31 +0000 (15:17 +0100)]
MIPS: BMIPS: Flush the readahead cache after DMA.

BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
the L1/L2.  During a DMA operation, accesses adjacent to a DMA buffer
may cause parts of the DMA buffer to be prefetched into the RAC.  To
avoid possible coherency problems, flush the RAC upon DMA completion.

Derived from Kevin Cernekee's https://patchwork.linux-mips.org/patch/9602/.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: DMA: Implement platform hook to perform post-DMA cache flushes.
Ralf Baechle [Fri, 27 Mar 2015 14:10:30 +0000 (15:10 +0100)]
MIPS: DMA: Implement platform hook to perform post-DMA cache flushes.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: ath25: Remove unused DMA helper functions.
Ralf Baechle [Fri, 27 Mar 2015 12:11:51 +0000 (13:11 +0100)]
MIPS: ath25: Remove unused DMA helper functions.

These got merged with the ath25 support after 4e7f72660c39 (MIPS: Remove
unnecessary platform dma helper functions) had already removed them for
all other platforms.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Loongson-3: remove deprecated IRQF_DISABLED
Michael Opdenacker [Fri, 27 Mar 2015 01:33:41 +0000 (18:33 -0700)]
MIPS: Loongson-3: remove deprecated IRQF_DISABLED

This removes the use of the IRQF_DISABLED flag
from arch/mips/loongson/loongson-3/hpet.c

It's a NOOP since 2.6.35.

Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com>
Cc: chenhc@lemote.com
Cc: taohl@lemote.com
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9609/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: BCM47xx: Move NVRAM header to the include/linux/.
Rafał Miłecki [Mon, 1 Dec 2014 06:58:18 +0000 (07:58 +0100)]
MIPS: BCM47xx: Move NVRAM header to the include/linux/.

There are two reasons for having this header in the common place:
1) Simplifying drivers that read NVRAM entries. We will be able to
   safely call bcm47xx_nvram_* functions without #ifdef-s.
2) Getting NVRAM driver out of MIPS arch code. This is needed to support
   BCM5301X arch which also requires this NVRAM driver. Patch for that
   will follow once we get is reviewed.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: linux-mips@linux-mips.org
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: linux-soc@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8619/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Expand __swp_offset() to carry 40 significant bits for 64-bit kernel.
David Daney [Tue, 24 Feb 2015 23:35:34 +0000 (15:35 -0800)]
MIPS: Expand __swp_offset() to carry 40 significant bits for 64-bit kernel.

With CONFIG_MIGRATION, the PFN of the migrating pages is stored in
__swp_offset(), so we must have enough bits to store the largest
possible PFN.  OCTEON NUMA systems have 41 bits of physical address
space, so with 4K pages (12-bits), we need at least 29 bits to store
the PFN.

The current width of 24-bits is too narrow, so expand it all the way
out to 40-bits.  This leaves the low order 16 bits as zero which does
not interfere with any of the PTE bits.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9315/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: BCM47XX: Use strnchr to avoid reading out of the buffer
Rafał Miłecki [Wed, 10 Dec 2014 10:49:54 +0000 (11:49 +0100)]
MIPS: BCM47XX: Use strnchr to avoid reading out of the buffer

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8662/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: BCM47XX: Use helpers for reading NVRAM content
Rafał Miłecki [Wed, 10 Dec 2014 10:49:53 +0000 (11:49 +0100)]
MIPS: BCM47XX: Use helpers for reading NVRAM content

Also drop some unneeded memset-s.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8661/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: mark prom_free_prom_memory() everywhere with __init
Aaro Koskinen [Wed, 25 Feb 2015 23:31:04 +0000 (01:31 +0200)]
MIPS: mark prom_free_prom_memory() everywhere with __init

On OCTEON the function is non-trivial and we can potentially even save
some memory.

Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Acked-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9338/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Provide fallback reboot/poweroff/halt implementations
Andrew Bresticker [Wed, 25 Mar 2015 17:25:44 +0000 (10:25 -0700)]
MIPS: Provide fallback reboot/poweroff/halt implementations

If a machine-specific hook is not implemented for restart, poweroff,
or halt, fall back to halting secondary CPUs, disabling interrupts,
and spinning.  In the case of restart, attempt to restart the system
via do_kernel_restart() (which will call any registered restart
handlers) before halting.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9600/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: smp: Make stop_this_cpu() actually stop the CPU
Andrew Bresticker [Wed, 25 Mar 2015 17:25:43 +0000 (10:25 -0700)]
MIPS: smp: Make stop_this_cpu() actually stop the CPU

Since cpu_wait() enables interrupts upon return, CPUs which have
entered stop_this_cpu() may still end up handling interrupts.
This can lead to the softlockup detector firing on a panic or
restart/poweroff/halt.  Just disable interrupts and spin to ensure
nothing else runs on the CPU once it has entered stop_this_cpu().

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9601/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: ath79: Increase max memory limit to 256MByte
Helmut Schaa [Thu, 18 Dec 2014 12:05:40 +0000 (13:05 +0100)]
MIPS: ath79: Increase max memory limit to 256MByte

At least QCA955x can handle up to 256MBytes.

Signed-off-by: Helmut Schaa <helmut.schaa@googlemail.com>
Cc: linux-mips@linux-mips.org
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: Helmut Schaa <helmut.schaa@googlemail.com>
Patchwork: https://patchwork.linux-mips.org/patch/8738/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Add FPU emulator counter for emulated delay slots.
David Daney [Wed, 3 Dec 2014 19:12:23 +0000 (11:12 -0800)]
MIPS: Add FPU emulator counter for emulated delay slots.

Delay slot emulation in the FPU emulator is the only kernel user of an
executable stack, it is also very slow.  Add a counter so we can see
how many of these emulations are done.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8634/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Update arch/mips/include/asm/sgi/sgi.h
Joshua Kinard [Fri, 12 Dec 2014 02:15:35 +0000 (21:15 -0500)]
MIPS: Update arch/mips/include/asm/sgi/sgi.h

Update arch/mips/include/asm/sgi/sgi.h with some updated information on SGI
systems.

Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Cc: Linux MIPS List <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/8666/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: pci: Drop owner assignment from platform_drivers
Wolfram Sang [Sun, 21 Dec 2014 21:14:24 +0000 (22:14 +0100)]
MIPS: pci: Drop owner assignment from platform_drivers

This platform_driver does not need to set an owner, it will be populated by the
driver core.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Cc: linux-kernel@vger.kernel.org
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8824/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: lantiq: xway: drop owner assignment from platform_drivers
Wolfram Sang [Sun, 21 Dec 2014 21:14:23 +0000 (22:14 +0100)]
MIPS: lantiq: xway: drop owner assignment from platform_drivers

This platform_driver does not need to set an owner, it will be populated by the
driver core.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8823/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Netlogic: Add built-in dts for XLP5xx boards
Ganesan Ramalingam [Wed, 7 Jan 2015 11:28:38 +0000 (16:58 +0530)]
MIPS: Netlogic: Add built-in dts for XLP5xx boards

Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8896/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Netlogic: i2c IRQ mappings for XLP9XX
Subhendu Sekhar Behera [Wed, 7 Jan 2015 11:28:37 +0000 (16:58 +0530)]
MIPS: Netlogic: i2c IRQ mappings for XLP9XX

The new I2C block in XLP9XX has 4 interrupts, add the mapping for
these in nlm_hal.c

Signed-off-by: Subhendu Sekhar Behera <sbehera@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8897/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Netlogic: Add irq mapping and setup for XHCI port 3
Ganesan Ramalingam [Wed, 7 Jan 2015 11:28:36 +0000 (16:58 +0530)]
MIPS: Netlogic: Add irq mapping and setup for XHCI port 3

Add support for third XHCI port in XLPII processors.

Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8895/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Netlogic: Do not enable SUE for core
Jayachandran C [Wed, 7 Jan 2015 11:28:35 +0000 (16:58 +0530)]
MIPS: Netlogic: Do not enable SUE for core

Enabling the SUE bit for core can can result in rare cache errors
which are difficult to track down, so do not enable it. This can
cause a minor performance loss in some tests.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8894/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Netlogic: Handle XLP hardware errata
Jayachandran C [Fri, 9 Jan 2015 10:43:20 +0000 (16:13 +0530)]
MIPS: Netlogic: Handle XLP hardware errata

Core configuration register IFU_BRUB_RESERVE has to be setup to handle
a silicon errata which can result in a CPU hang.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8902/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Netlogic: Update function to read DRAM BARs
Jayachandran C [Wed, 7 Jan 2015 11:28:33 +0000 (16:58 +0530)]
MIPS: Netlogic: Update function to read DRAM BARs

Change name of xlp_get_dram_map to nlm_get_dram_map to be consistent
with the rest of the functions in the file. Pass the the size of the
array 'dram_map' to the function, and ensure that it does not write
past the end of the array.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8892/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Netlogic: Added HugeTLB as default
Prem Mallappa [Wed, 7 Jan 2015 11:28:32 +0000 (16:58 +0530)]
MIPS: Netlogic: Added HugeTLB as default

Enable CPU_SUPPORTS_HUGEPAGES for XLP processors.

Signed-off-by: Prem Mallappa <pmallapp@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8891/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Netlogic: nlm_core_id for xlp9xx
Jayachandran C [Wed, 7 Jan 2015 11:28:31 +0000 (16:58 +0530)]
MIPS: Netlogic: nlm_core_id for xlp9xx

XLP9XX has 5 bits that specify the core in the EBASE register. XLP5XX
case added as well for completeness.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8890/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Netlogic: Move cores per node out of multi-node.h
Jayachandran C [Wed, 7 Jan 2015 11:28:30 +0000 (16:58 +0530)]
MIPS: Netlogic: Move cores per node out of multi-node.h

Use the current_cpu_data package field to get the node of the current CPU.

This allows us to remove xlp_cores_per_node and move nlm_threads_per_node()
and nlm_cores_per_node() to netlogic/common.h, which simplifies code.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8889/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Netlogic: Use MIPS topology.h
Jayachandran C [Wed, 7 Jan 2015 11:28:29 +0000 (16:58 +0530)]
MIPS: Netlogic: Use MIPS topology.h

commit bda4584cd943 ("MIPS: Support CPU topology files in sysfs")
added topology related macros for all MIPS platforms and commit
bbbf6d8768f5 ("MIPS: NL: Fix nlm_xlp_defconfig build error")
removed most of the contents from mach-netlogic/topology.h.

The netlogic specific topology is not needed anymore, we just need
to setup the package field in current_cpu_data.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8888/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: MSI: Update MSI handling for XLP
Jayachandran C [Wed, 7 Jan 2015 11:28:28 +0000 (16:58 +0530)]
MIPS: MSI: Update MSI handling for XLP

The per-cpu interrupt ACK using EIRR has to be done just once after
all the bits in the status register are processed.

PIC ack has to be done once in case of MSI, and for every interrupt
in case of MSI-X

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8887/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Netlogic: Fix frequency calculation register
Ganesan Ramalingam [Wed, 7 Jan 2015 11:28:27 +0000 (16:58 +0530)]
MIPS: Netlogic: Fix frequency calculation register

Change the PIC frequency calculation to use the register that has the
current configuration. The existing code used the register that is
written to change frequency, which can have an invalid value if the
firmware did not set it up correctly.

Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8885/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Netlogic: Disable writing IRT for disabled blocks
Jayachandran C [Wed, 7 Jan 2015 11:28:25 +0000 (16:58 +0530)]
MIPS: Netlogic: Disable writing IRT for disabled blocks

If the device header of a block is not present, return invalid IRT
value so that we do not program an incorrect offset.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8882/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Netlogic: Fix cop0 prid check in AHCI init
Ganesan Ramalingam [Wed, 7 Jan 2015 11:28:24 +0000 (16:58 +0530)]
MIPS: Netlogic: Fix cop0 prid check in AHCI init

PRID register should be masked with IMP_MASK to get processor ID.

Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8883/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Netlogic: Fix nlm_xlp2_get_pic_frequency to use ref_div
Qingmin Liu [Wed, 7 Jan 2015 11:28:23 +0000 (16:58 +0530)]
MIPS: Netlogic: Fix nlm_xlp2_get_pic_frequency to use ref_div

The variable ref_div is initialized to the correct divisor but not
used in the frequency calculation. This caused incorrect frequency
to be reported when the clock divisor is not 3.

Signed-off-by: Qingmin Liu <qingmin@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8884/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Netlogic: Fix wait for slave CPUs
Shanghui Liu [Wed, 7 Jan 2015 11:28:22 +0000 (16:58 +0530)]
MIPS: Netlogic: Fix wait for slave CPUs

For core 0, the condition of "cpu == bootcpu" is always true, so it
does not wait for other three threads to become ready. Fix this by
using correct check.

Signed-off-by: Shanghui Liu <shliu@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8881/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: LLVMLinux: Silence variable self-assignment warnings.
Toma Tabacu [Tue, 24 Feb 2015 15:25:11 +0000 (15:25 +0000)]
MIPS: LLVMLinux: Silence variable self-assignment warnings.

Remove variable self-assignments.
This silences a bunch of -Wself-assign warnings reported by clang.
The changed code can be compiled without warnings by both gcc and clang.

Signed-off-by: Toma Tabacu <toma.tabacu@imgtec.com>
Signed-off-by: Daniel Sanders <daniel.sanders@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9314/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: LLVMLinux: Fix an 'inline asm input/output type mismatch' error.
Daniel Sanders [Tue, 24 Feb 2015 15:25:10 +0000 (15:25 +0000)]
MIPS: LLVMLinux: Fix an 'inline asm input/output type mismatch' error.

Replace incorrect matching constraint that caused the error with an alternative
that still has the required constraints on the inline assembly.

This is the error message reported by clang:
arch/mips/include/asm/checksum.h:285:27: error: unsupported inline asm: input with type '__be32' (aka 'unsigned int') matching output with type 'unsigned short'
          "0" (htonl(len)), "1" (htonl(proto)), "r" (sum));
                                 ^~~~~~~~~~~~

The changed code can be compiled successfully by both gcc and clang.

Signed-off-by: Daniel Sanders <daniel.sanders@imgtec.com>
Signed-off-by: Toma Tabacu <toma.tabacu@imgtec.com>
Suggested-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9313/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: LLVMLinux: Fix a 'cast to type not present in union' error.
Toma Tabacu [Tue, 24 Feb 2015 15:25:09 +0000 (15:25 +0000)]
MIPS: LLVMLinux: Fix a 'cast to type not present in union' error.

Remove a cast to the 'mips16e_instruction' union inside an if
condition and instead do an assignment to a local
'union mips16e_instruction' variable's 'full' member before the if
statement and use this variable in the if condition.

This is the error message reported by clang:
arch/mips/kernel/branch.c:38:8: error: cast to union type from type 'unsigned short' not present in union
                if (((union mips16e_instruction)inst).ri.opcode
                     ^                          ~~~~

The changed code can be compiled successfully by both gcc and clang.

Signed-off-by: Toma Tabacu <toma.tabacu@imgtec.com>
Signed-off-by: Daniel Sanders <daniel.sanders@imgtec.com>
Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: David Daney <david.daney@cavium.com>
Cc: Manuel Lauss <manuel.lauss@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9312/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Changed current_thread_info() to an equivalent supported by both clang and GCC
Daniel Sanders [Tue, 24 Feb 2015 15:02:57 +0000 (15:02 +0000)]
MIPS: Changed current_thread_info() to an equivalent supported by both clang and GCC

Without this, a 'break' instruction is executed very early in the boot and
the boot hangs.

The problem is that clang doesn't honour named registers on local variables
and silently treats them as normal uninitialized variables. However, it
does honour them on global variables.

Signed-off-by: Daniel Sanders <daniel.sanders@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Cc: David Daney <ddaney.cavm@gmail.com>
Acked-by: Behan Webster <behanw@converseincode.com>
Patchwork: https://patchwork.linux-mips.org/patch/9311/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: XPA: Add new configuration file.
Steven J. Hill [Fri, 27 Feb 2015 00:16:39 +0000 (18:16 -0600)]
MIPS: XPA: Add new configuration file.

Add in new config files for enabling a XPA platform.

Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9354/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: OCTEON: Use correct CSR to soft reset
Chandrakala Chavva [Thu, 5 Mar 2015 15:06:11 +0000 (18:06 +0300)]
MIPS: OCTEON: Use correct CSR to soft reset

This fixes reboot for Octeon III boards

[ralf@linux-mips.org: Dropped segment for function cvmx_reset_octeon()
which was removed by the preceeding commit.]

Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9464/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Octeon: Remove unused function cvmx_reset_octeon().
Ralf Baechle [Wed, 25 Mar 2015 10:44:09 +0000 (11:44 +0100)]
MIPS: Octeon: Remove unused function cvmx_reset_octeon().

As suggested by David Daney.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: OCTEON: Use device tree to probe for flash chips.
David Daney [Thu, 5 Mar 2015 14:31:31 +0000 (17:31 +0300)]
MIPS: OCTEON: Use device tree to probe for flash chips.

Don't assume they are there, the device tree will tell us.

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9461/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: OCTEON: Protect accesses to bootbus flash with octeon_bootbus_sem.
David Daney [Thu, 5 Mar 2015 14:31:30 +0000 (17:31 +0300)]
MIPS: OCTEON: Protect accesses to bootbus flash with octeon_bootbus_sem.

Without this, we get bus errors.

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9460/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: OCTEON: Add semaphore to serialize bootbus accesses.
David Daney [Thu, 5 Mar 2015 14:31:29 +0000 (17:31 +0300)]
MIPS: OCTEON: Add semaphore to serialize bootbus accesses.

Some hardware blocks attached to the OCTEON bootbus run asynchronously
to accesses from the CPUs.  These include MMC/SD host, CF(when using
DMA), and NAND controller.  A bus error, or corrupt data may occur if
a CPU is trying to access a bootbus connected device at the same time
the bus is running asynchronous operations.

To work around these problems we add this semaphore that must be
acquired before initiating bootbus activity.  Subsequent patches will
add users for this.

Signed-off-by: David Daney <david.daney@cavium.com>
[aleksey.makarov@auriga.com: combine the patches]
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9459/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: BMIPS: Add DTS files for several platforms
Kevin Cernekee [Thu, 25 Dec 2014 17:49:20 +0000 (09:49 -0800)]
MIPS: BMIPS: Add DTS files for several platforms

Most of the supported chips use legacy (non-DT) bootloaders, so they will
need to select an appropriate builtin DTB at compile time until the
bootloader is updated.  Provide suitable DTS files, and a means to compile
one of them into the kernel image.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
Cc: f.fainelli@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8858/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: BMIPS: Update DT bindings to reflect new SoC support
Kevin Cernekee [Thu, 25 Dec 2014 17:49:19 +0000 (09:49 -0800)]
MIPS: BMIPS: Update DT bindings to reflect new SoC support

Add an entry for each supported Broadcom SoC.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
Cc: f.fainelli@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8857/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: BMIPS: Refresh BCM3384 DTS files
Kevin Cernekee [Thu, 25 Dec 2014 17:49:18 +0000 (09:49 -0800)]
MIPS: BMIPS: Refresh BCM3384 DTS files

The DT bindings for this platform have changed as the bootloader and
product requirements evolved.  In particular, there are both
Linux-on-Zephyr and Linux-on-Viper configurations.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8856/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: BMIPS: Enable additional peripheral and CPU support in defconfig
Kevin Cernekee [Thu, 25 Dec 2014 17:49:17 +0000 (09:49 -0800)]
MIPS: BMIPS: Enable additional peripheral and CPU support in defconfig

Also, add an LE defconfig for set-top box (BCM7xxx).  This will allow the
BMIPS kernel to run on several non-BCM3384 platforms.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Jaedon Shin <jaedon.shin@gmail.com>
Cc: f.fainelli@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8855/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: BMIPS: Use a non-default FIXADDR_TOP setting
Kevin Cernekee [Thu, 25 Dec 2014 17:49:16 +0000 (09:49 -0800)]
MIPS: BMIPS: Use a non-default FIXADDR_TOP setting

This will be required to support BMIPS3300 platforms.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8854/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: BMIPS: Delete the irqchip driver from irq.c
Kevin Cernekee [Thu, 25 Dec 2014 17:49:15 +0000 (09:49 -0800)]
MIPS: BMIPS: Delete the irqchip driver from irq.c

BCM3384/BCM63xx can use the common drivers/irqchip/irq-bcm7120-l2.c for
this purpose; BCM7xxx will use drivers/irqchip/irq-bcm7038-l1.c.  We no
longer need this code under arch/mips.

[ralf@linux-mips.org: Fix conflicts.]

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8853/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: BMIPS: Add quirks for several Broadcom platforms
Kevin Cernekee [Thu, 25 Dec 2014 17:49:14 +0000 (09:49 -0800)]
MIPS: BMIPS: Add quirks for several Broadcom platforms

A couple of chips require special handling in order to make SMP secondary
boot and/or exception vectors work correctly.  Take care of these in
setup.c.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8852/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: BMIPS: Remove bogus bus name
Kevin Cernekee [Thu, 25 Dec 2014 17:49:13 +0000 (09:49 -0800)]
MIPS: BMIPS: Remove bogus bus name

There is no "bcm3384" bus so let's just remove it to avoid confusion.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8851/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: BMIPS: Rewrite DMA code to use "dma-ranges" property
Kevin Cernekee [Thu, 25 Dec 2014 17:49:12 +0000 (09:49 -0800)]
MIPS: BMIPS: Rewrite DMA code to use "dma-ranges" property

This is a more standardized way of handling DMA remapping, and it is
suitable for the memory map found on BCM3384.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8850/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: BMIPS: Document the firmware->kernel DTB interface
Kevin Cernekee [Thu, 25 Dec 2014 17:49:11 +0000 (09:49 -0800)]
MIPS: BMIPS: Document the firmware->kernel DTB interface

Add a new section covering the Generic BMIPS machine type.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8849/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Reorder MIPS_L1_CACHE_SHIFT priorities
Kevin Cernekee [Thu, 25 Dec 2014 17:49:09 +0000 (09:49 -0800)]
MIPS: Reorder MIPS_L1_CACHE_SHIFT priorities

Enabling support for more than one BMIPS CPU in the same build may
result in different L1_CACHE_SHIFT values, e.g.

    CPU_BMIPS5000 selects MIPS_L1_CACHE_SHIFT_7
    CPU_BMIPS4380 selects MIPS_L1_CACHE_SHIFT_6
    anything else defaults to MIPS_L1_CACHE_SHIFT_5

Ensure that if more than one MIPS_L1_CACHE_SHIFT_x option is selected,
Kconfig sets CONFIG_MIPS_L1_CACHE_SHIFT to the highest value.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8847/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Let __dt_register_buses accept a single bus type
Kevin Cernekee [Thu, 25 Dec 2014 17:49:07 +0000 (09:49 -0800)]
MIPS: Let __dt_register_buses accept a single bus type

Some machines only have one bus type to register (e.g. "simple-bus").

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8845/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoIRQCHIP: Add new driver for BCM7038-style level 1 interrupt controllers
Kevin Cernekee [Thu, 25 Dec 2014 17:49:06 +0000 (09:49 -0800)]
IRQCHIP: Add new driver for BCM7038-style level 1 interrupt controllers

This is the main peripheral IRQ controller on the BCM7xxx MIPS chips;
it has the following characteristics:

 - 64 to 160+ level IRQs
 - Atomic set/clear registers
 - Reasonably predictable register layout (N status words, then N
   mask status words, then N mask set words, then N mask clear words)
 - SMP affinity supported on most systems
 - Typically connected to MIPS IRQ 2,3,2,3 on CPUs 0,1,2,3

This driver registers one IRQ domain and one IRQ chip to cover all
instances of the block.  Up to 4 instances of the block may appear, as
it supports 4-way IRQ affinity on BCM7435.

The same block exists on the ARM BCM7xxx chips, but typically the ARM GIC
is used instead.  So this driver is primarily intended for MIPS STB chips.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8844/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoIRQCHIP: bcm7120-l2: Add support for BCM3380-style controllers
Kevin Cernekee [Thu, 25 Dec 2014 17:49:05 +0000 (09:49 -0800)]
IRQCHIP: bcm7120-l2: Add support for BCM3380-style controllers

These controllers support multiple enable/status pairs (64+ IRQs),
can put the enable/status words at different offsets, and do not
support multiple parent IRQs.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8843/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoIRQCHIP: bcm7120-l2: Split STB-specific logic into its own function
Kevin Cernekee [Thu, 25 Dec 2014 17:49:04 +0000 (09:49 -0800)]
IRQCHIP: bcm7120-l2: Split STB-specific logic into its own function

The BCM7xxx instances of this block (listed in the register manual as
simply "IRQ0") all have the following items in common:

 - brcm,int-map-mask: for routing different bits in the L2 to different
   parent IRQs

 - brcm,int-fwd-mask: for hardwiring certain IRQs to bypass the L2 and
   use dedicated L1 lines

 - one enable/status pair (32 bits only)

Much of the driver code can be shared with BCM3380-style controllers, but
in order to do this cleanly, let's split out the BCM7xxx-specific logic
first.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8842/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoIRQCHIP: bcm7120-l2: Refactor driver for arbitrary IRQEN/IRQSTAT offsets
Kevin Cernekee [Thu, 25 Dec 2014 17:49:03 +0000 (09:49 -0800)]
IRQCHIP: bcm7120-l2: Refactor driver for arbitrary IRQEN/IRQSTAT offsets

Currently the driver assumes that REG_BASE+0x00 is the IRQ enable mask,
and REG_BASE+0x04 is the IRQ status mask.  This is true on BCM3384 and
BCM7xxx, but it is not true for some of the controllers found on BCM63xx
chips.  So we will change a couple of key assumptions:

 - Don't assume that both the IRQEN and IRQSTAT registers will be
   covered by a single ioremap() operation.

 - Don't assume any particular ordering (IRQSTAT might show up before
   IRQEN on some chips).

 - For an L2 controller with >=64 IRQs, don't assume that every
   IRQEN/IRQSTAT pair will use the same register spacing.

This patch changes the "plumbing" but doesn't yet provide a way for users
to instantiate a controller with arbitrary IRQEN/IRQSTAT offsets.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8841/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoIRQCHIP: brcmstb-l2: don't clear wakeable interrupts at init time
Brian Norris [Thu, 25 Dec 2014 17:49:02 +0000 (09:49 -0800)]
IRQCHIP: brcmstb-l2: don't clear wakeable interrupts at init time

Wakeable interrupts might be pending at boot/init time, because wakeup
interrupts might have triggered a resume from S5. So don't clear such
wakeups.

This means that any driver which requests a wakeable interrupt bit
should be prepared to handle an interrupt as soon as they call
request_irq(). (This is technically already the correct development
practice, but some drivers probably expect not to receive interrupts
until they have performed some I/O.)

Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8840/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoIRQCHIP: Update docs regarding irq_domain_add_tree()
Kevin Cernekee [Thu, 25 Dec 2014 17:49:01 +0000 (09:49 -0800)]
IRQCHIP: Update docs regarding irq_domain_add_tree()

Several drivers now use this API, including the ARM GIC driver, so remove
the outdated comment.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8839/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: bcm3384: Rename "bcm3384" target to "bmips"
Kevin Cernekee [Thu, 25 Dec 2014 17:49:00 +0000 (09:49 -0800)]
MIPS: bcm3384: Rename "bcm3384" target to "bmips"

This platform is configured primarily through device tree, and we can
reuse the same code to support a bunch of other chips.  Change the name
to reflect this.

[ralf@linux-mips.org: Fix conflicts with other patches.]

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: abrestic@chromium.org
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8838/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Add dtbs_install target
Andrew Bresticker [Thu, 25 Dec 2014 17:48:58 +0000 (09:48 -0800)]
MIPS: Add dtbs_install target

Add the dtbs_install Makefile target to install the dtb files into
$INSTALL_DTBS_PATH.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8836/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Move device-trees into vendor sub-directories
Andrew Bresticker [Thu, 25 Dec 2014 17:48:57 +0000 (09:48 -0800)]
MIPS: Move device-trees into vendor sub-directories

Move the MIPS device-trees into the appropriate vendor sub-directories.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: jaedon.shin@gmail.com
Cc: tglx@linutronix.de
Cc: jason@lakedaemon.net
Cc: jogo@openwrt.org
Cc: arnd@arndb.de
Cc: computersforpeace@gmail.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8835/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Add support for fine granularity task level IRQ time accounting
Deng-Cheng Zhu [Sat, 7 Mar 2015 18:30:35 +0000 (10:30 -0800)]
MIPS: Add support for fine granularity task level IRQ time accounting

With sched_clock being ready, it makes sense to add the option of IRQ time
accounting -- When we have a fast enough sched_clock, IRQ time accounting
will be enabled (see sched_clock_register).

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9489/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: csrc-sb1250: Implement read_sched_clock
Deng-Cheng Zhu [Sat, 7 Mar 2015 18:30:34 +0000 (10:30 -0800)]
MIPS: csrc-sb1250: Implement read_sched_clock

Use sb1250 hpt for sched_clock source. This implementation will give high
resolution cputime accounting.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9488/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: csrc-sb1250: Remove FSF mail address from GPL notice
Deng-Cheng Zhu [Sat, 7 Mar 2015 18:30:33 +0000 (10:30 -0800)]
MIPS: csrc-sb1250: Remove FSF mail address from GPL notice

This is to make checkpatch.pl happy for the next patch. It would otherwise
say --

ERROR: Do not include the paragraph about writing to the Free Software
Foundation's mailing address from the sample GPL notice. The FSF has
changed addresses in the past, and may do so again. Linux already includes
a copy of the GPL.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9487/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: csrc-sb1250: Extract hpt cycle acquisition from sb1250_hpt_read
Deng-Cheng Zhu [Sat, 7 Mar 2015 18:30:32 +0000 (10:30 -0800)]
MIPS: csrc-sb1250: Extract hpt cycle acquisition from sb1250_hpt_read

This is to prepare for the upcoming read_sched_clock implementation, which
will also need to get cycles from the high precision timer.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9486/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: jz4740: Implement read_sched_clock
Deng-Cheng Zhu [Sat, 7 Mar 2015 18:30:31 +0000 (10:30 -0800)]
MIPS: jz4740: Implement read_sched_clock

Use jz4740 timer counter for sched_clock source. This implementation will
give high resolution cputime accounting.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9485/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: cevt-txx9: Implement read_sched_clock
Deng-Cheng Zhu [Sat, 7 Mar 2015 18:30:30 +0000 (10:30 -0800)]
MIPS: cevt-txx9: Implement read_sched_clock

Use txx9 up-counter for sched_clock source. This implementation will give
high resolution cputime accounting.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9484/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: sgi-ip27: Implement read_sched_clock
Deng-Cheng Zhu [Sat, 7 Mar 2015 18:30:29 +0000 (10:30 -0800)]
MIPS: sgi-ip27: Implement read_sched_clock

Use ip27 hub real time counter for sched_clock source. This implementation
will give high resolution cputime accounting.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9483/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: csrc-ioasic: Implement read_sched_clock
Deng-Cheng Zhu [Sat, 7 Mar 2015 18:30:28 +0000 (10:30 -0800)]
MIPS: csrc-ioasic: Implement read_sched_clock

Use DEC I/O ASIC's free-running counter for sched_clock source. This
implementation will give high resolution cputime accounting.

Acked-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9482/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: csrc-ioasic: Remove FSF mail address from GPL notice
Deng-Cheng Zhu [Sat, 7 Mar 2015 18:30:27 +0000 (10:30 -0800)]
MIPS: csrc-ioasic: Remove FSF mail address from GPL notice

This is to make checkpatch.pl happy for the next patch. It would otherwise
say --

ERROR: Do not include the paragraph about writing to the Free Software
Foundation's mailing address from the sample GPL notice. The FSF has
changed addresses in the past, and may do so again. Linux already includes
a copy of the GPL.

Acked-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9481/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: csrc-bcm1480: Implement read_sched_clock
Deng-Cheng Zhu [Sat, 7 Mar 2015 18:30:26 +0000 (10:30 -0800)]
MIPS: csrc-bcm1480: Implement read_sched_clock

Use the ZBbus cycle counter for sched_clock source. This implementation
will give high resolution cputime accounting.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9480/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: csrc-bcm1480: Remove FSF mail address from GPL notice
Deng-Cheng Zhu [Sat, 7 Mar 2015 18:30:25 +0000 (10:30 -0800)]
MIPS: csrc-bcm1480: Remove FSF mail address from GPL notice

This is to make checkpatch.pl happy for the next patch. It would otherwise
say --

ERROR: Do not include the paragraph about writing to the Free Software
Foundation's mailing address from the sample GPL notice. The FSF has
changed addresses in the past, and may do so again. Linux already includes
a copy of the GPL.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9479/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: csrc-r4k: Implement read_sched_clock
Deng-Cheng Zhu [Sat, 7 Mar 2015 18:30:24 +0000 (10:30 -0800)]
MIPS: csrc-r4k: Implement read_sched_clock

Use c0 count register for sched_clock source. This implementation will give
high resolution cputime accounting.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9478/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Add sched_clock support
Deng-Cheng Zhu [Sat, 7 Mar 2015 18:30:23 +0000 (10:30 -0800)]
MIPS: Add sched_clock support

This will provide sched_clock interface to implement individual
read_sched_clock(). Not for CAVIUM_OCTEON_SOC as it defines its own
sched_clock() directly (not using the sched_clock_register interface).

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9477/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoCLOCKSOURCE: versatile: Add PLAT_VERSATILE dependency
Deng-Cheng Zhu [Sat, 7 Mar 2015 18:30:22 +0000 (10:30 -0800)]
CLOCKSOURCE: versatile: Add PLAT_VERSATILE dependency

GENERIC_SCHED_CLOCK can be selected by architectures other than ARM. The
current dependencies of CLKSRC_VERSATILE make it possible that other
architectures will have CLKSRC_VERSATILE available in configuration once
they select GENERIC_SCHED_CLOCK, whereas this clock source should be solely
available to ARM in reality.

This patch adds one more dependency to CLKSRC_VERSATILE to fix the issue.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Reported-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: LKML <linux-kernel@vger.kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9476/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Add support for full dynticks CPU time accounting
Deng-Cheng Zhu [Sat, 7 Mar 2015 18:30:21 +0000 (10:30 -0800)]
MIPS: Add support for full dynticks CPU time accounting

With the correct cmpxchg64 on 32-bit platforms, we can now add the config
HAVE_VIRT_CPU_ACCOUNTING_GEN into arch/mips/Kconfig.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9475/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Fall back to generic implementation of cmpxchg64 on 32-bit platforms
Deng-Cheng Zhu [Sat, 7 Mar 2015 18:30:20 +0000 (10:30 -0800)]
MIPS: Fall back to generic implementation of cmpxchg64 on 32-bit platforms

This is in preparation of adding HAVE_VIRT_CPU_ACCOUNTING_GEN support in
the next patch.

Without having cmpxchg64 to use the generic implementation, kernel linking
will complain:

kernel/built-in.o: In function `cputime_adjust':
cputime.c:(.text+0x33748): undefined reference to `__cmpxchg_called_with_bad_pointer'
cputime.c:(.text+0x33810): undefined reference to `__cmpxchg_called_with_bad_pointer'

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9474/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Add SCHED_HRTICK support
Deng-Cheng Zhu [Sat, 7 Mar 2015 18:30:19 +0000 (10:30 -0800)]
MIPS: Add SCHED_HRTICK support

We have HIGH_RES_TIMERS to support SCHED_HRTICK. But SCHED_HRTICK is in
kernel/Kconfig.hz where HZ values unsuitable for MIPS are defined. So we
simply add this config in arch/mips/Kconfig as opposed to including the
whole kernel/Kconfig.hz.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: macro@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9473/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: OCTEON: Enable little endian kernel.
David Daney [Fri, 20 Mar 2015 16:11:58 +0000 (19:11 +0300)]
MIPS: OCTEON: Enable little endian kernel.

Now it is supported, so let people select it.

[ralf@linux-mips.org: Folded in fix for bogus CONFIG_ kconfig symbol
prefix.  Issue reported by Valentin Rothberg <valentinrothberg@gmail.com>.]

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Leonid Rosenboim <lrosenboim@caviumnetworks.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9592/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: OCTEON: Add mach-cavium-octeon/mangle-port.h
David Daney [Fri, 20 Mar 2015 16:11:57 +0000 (19:11 +0300)]
MIPS: OCTEON: Add mach-cavium-octeon/mangle-port.h

Needed for little-endian ioport access.
This fixes NOR flash in little-endian mode

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9591/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Octeon: Handle bootloader structures in little-endian mode.
David Daney [Fri, 20 Mar 2015 16:11:56 +0000 (19:11 +0300)]
MIPS: Octeon: Handle bootloader structures in little-endian mode.

Compensate for the differences in the layout of in-memory bootloader
information as seen from little-endian mode.

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9590/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Malta: malta-time: Ensure GIC counter is running
Markos Chandras [Mon, 23 Mar 2015 12:32:03 +0000 (12:32 +0000)]
MIPS: Malta: malta-time: Ensure GIC counter is running

Start the GIC counter before we try to determine its frequency.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9596/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoCLOCKSOURCE: mips-gic-timer: Ensure GIC counter is running
Markos Chandras [Mon, 23 Mar 2015 12:32:02 +0000 (12:32 +0000)]
CLOCKSOURCE: mips-gic-timer: Ensure GIC counter is running

Start the GIC counter after configuring the clocksource since there
are no guarantees the counter will be running after a CPU reset.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9595/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoIRQCHIP: irq-mips-gic: Add new functions to start/stop the GIC counter
Markos Chandras [Mon, 23 Mar 2015 12:32:01 +0000 (12:32 +0000)]
IRQCHIP: irq-mips-gic: Add new functions to start/stop the GIC counter

We add new functions to start and stop the GIC counter since there are no
guarantees the counter will be running after a CPU reset. The GIC counter
is stopped by setting the 29th bit on the GIC Config register and it is
started by clearing that bit.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9594/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agottyFDC: Implement KGDB IO operations.
James Hogan [Thu, 29 Jan 2015 11:14:14 +0000 (11:14 +0000)]
ttyFDC: Implement KGDB IO operations.

Implement KGDB IO operations for MIPS Fast Debug Channel (FDC). This can
be enabled via Kconfig, which also allows the channel number to be
chosen.

The magic sysrq hack is implemented in the TTY driver, detecting just ^C
for the KGDB channel, and ^O followed by a letter for the FDC console
channel.

The KGDB operations are reasonably efficient thanks to the flush
callback, with a 4 byte buffer being used in both directions to allow up
to 4 bytes to be encoded per FDC word. Reading of data for KGDB will
discard any data received on other channels, which clearly isn't ideal,
but given that there is a single FIFO shared between channels we can't
do much better.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jiri Slaby <jslaby@suse.cz>
Cc: Jason Wessel <jason.wessel@windriver.com>
Cc: linux-mips@linux-mips.org
Cc: kgdb-bugreport@lists.sourceforge.net
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9147/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS, ttyFDC: Add early FDC console support
James Hogan [Thu, 29 Jan 2015 11:14:13 +0000 (11:14 +0000)]
MIPS, ttyFDC: Add early FDC console support

Add support for early console of MIPS Fast Debug Channel (FDC) on
channel 1 with a call very early from the MIPS setup_arch().

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jiri Slaby <jslaby@suse.cz>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9145/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoTTY: Add MIPS EJTAG Fast Debug Channel TTY driver
James Hogan [Thu, 29 Jan 2015 11:14:12 +0000 (11:14 +0000)]
TTY: Add MIPS EJTAG Fast Debug Channel TTY driver

Add TTY driver and consoles for the MIPS EJTAG Fast Debug Channel (FDC),
which is found on the per-CPU MIPS Common Device Mapped Memory (CDMM)
bus.

The FDC is a per-CPU device which is used to communicate with an EJTAG
probe. RX and TX FIFOs exist, containing 32-bits of data and 4-bit
channel numbers. 16 general data streams are implemented on this for TTY
and console use by encoding up to 4 bytes on each 32-bit FDC word.

The TTY devices are named e.g. /dev/ttyFDC3c2 for channel 2 of the FDC
attached to logical CPU 3.

These can be used for getting the kernel log, a login prompt, or as a
GDB remote transport, all over EJTAG and without needing a serial port.

It can have an interrupt to notify of when incoming data is available in
the RX FIFO or when the TX FIFO is no longer full. The detection of this
interrupt occurs in architecture / platform code, but it may be shared
with the timer and/or performance counter interrupt.

Due to the per-CPU nature of the hardware, all outgoing TTY data is
written out from a kthread which is pinned to the appropriate CPU.

The console is not bound to a specific CPU, so output will appear on the
chosen channel on whichever CPU the code is executing on. Enable with
e.g. console=fdc1 in kernel arguments. /dev/console is bound to the same
channel on the boot CPU's FDC if it exists.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jiri Slaby <jslaby@suse.cz>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9146/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: idle: Workaround wait + FDC problems
James Hogan [Thu, 29 Jan 2015 11:14:11 +0000 (11:14 +0000)]
MIPS: idle: Workaround wait + FDC problems

On certain cores (namely proAptiv and P5600) incoming data via a Fast
Debug Channel (FDC) while the core is blocked on a wait instruction will
cause the wait not to wake up even when another interrupt is received.
This makes an idle target stop as soon as you send FDC data to it, until
the debug probe interrupts it and restarts the wait instruction.

This is worked around by avoiding using r4k_wait on these cores if
CONFIG_MIPS_EJTAG_FDC_TTY is enabled (which would imply the user intends
to use the FDC).

[ralf@linux-mips.org: Fix conflict.]

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9144/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Malta: Implement get_c0_fdc_int()
James Hogan [Thu, 29 Jan 2015 11:14:10 +0000 (11:14 +0000)]
MIPS: Malta: Implement get_c0_fdc_int()

Implement the weak get_c0_fdc_int() function for Malta. The Fast Debug
Channel (FDC) interrupt is obtained mainly depending on whether a GIC is
present. Vectored external interrupt mode isn't yet supported.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9143/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoIRQCHIP: mips-gic: Add function for retrieving FDC IRQ
James Hogan [Thu, 29 Jan 2015 11:14:09 +0000 (11:14 +0000)]
IRQCHIP: mips-gic: Add function for retrieving FDC IRQ

Add a function to the MIPS GIC driver for retrieving the Fast Debug
Channel (FDC) interrupt number, similar to the existing ones for the
timer and perf counter interrupts. This will be used by platform
implementations of get_c0_fdc_int() if a GIC is present.

A workaround exists for interAptiv and proAptiv which claim to be able
to route the FDC interrupt but don't seem to be able to in practice (at
least on Malta).

[ralf@linux-mips.org: Fix conflict.]

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9142/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoirqchip: mips-gic: Don't treat FDC IRQ as percpu devid
James Hogan [Thu, 29 Jan 2015 11:14:08 +0000 (11:14 +0000)]
irqchip: mips-gic: Don't treat FDC IRQ as percpu devid

Treat the Fast Debug Channel (FDC) interrupt the same as the timer and
performance counter interrupts. Like them, the FDC IRQ is also per-VPE,
and also doesn't use a per-CPU device ID yet. Per-CPU device IDs don't
seem to work with IRQF_SHARED which is needed for compatibility with
cores which don't route the FDC IRQ through the GIC. For hardware which
routes FDC IRQs through the GIC this is something that could be added
later.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9141/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Read CPU IRQ line that FDC to routed to
James Hogan [Thu, 29 Jan 2015 11:14:07 +0000 (11:14 +0000)]
MIPS: Read CPU IRQ line that FDC to routed to

Read the CPU IRQ line reportedly used for the Fast Debug Channel (FDC)
interrupt from the IntCtl register and store it in cp0_fdc_irq where
platform implementations of the new weak platform function
get_c0_fdc_int() can refer to it.

[ralf@linux-mips.org: Fixed conflict.]

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: James Hogan <james.hogan@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9140/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Add architectural FDC IRQ fields
James Hogan [Thu, 29 Jan 2015 11:14:06 +0000 (11:14 +0000)]
MIPS: Add architectural FDC IRQ fields

Add architectural field definitions relating to the Fast Debug Channel
(FDC) interrupt, namely the pending bit in Cause and the field in
IntCtl to specify which CPU IRQ line the FDC interrupt is routed to.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: James Hogan <james.hogan@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9139/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Malta: Implement mips_cdmm_phys_base()
James Hogan [Mon, 2 Feb 2015 11:45:10 +0000 (11:45 +0000)]
MIPS: Malta: Implement mips_cdmm_phys_base()

Implement mips_cdmm_phys_base() for Malta, returning the physical base
address 0x1fc10000 which is "typically unused".

This allows the Common Device Memory Map (CDMM) region to be mapped, and
devices in that region (such as the Fast Debug Channel (FDC) hardware
for communication over EJTAG) to be discovered.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9177/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
4 years agoMIPS: Add CDMM bus support
James Hogan [Wed, 25 Mar 2015 15:39:50 +0000 (15:39 +0000)]
MIPS: Add CDMM bus support

Add MIPS Common Device Memory Map (CDMM) support in the form of a bus in
the standard Linux device model. Each device attached via CDMM is
discoverable via an 8-bit type identifier and may contain a number of
blocks of memory mapped registers in the CDMM region. IRQs are expected
to be handled separately.

Due to the per-cpu (per-VPE for MT cores) nature of the CDMM devices,
all the driver callbacks take place from workqueues which are run on the
right CPU for the device in question, so that the driver doesn't need to
be as concerned about which CPU it is running on. Callbacks also exist
for when CPUs are taken offline, so that any per-CPU resources used by
the driver can be disabled so they don't get forcefully migrated. CDMM
devices are created as children of the CPU device they are attached to.

Any existing CDMM configuration by the bootloader will be inherited,
however platforms wishing to enable CDMM should implement the weak
mips_cdmm_phys_base() function (see asm/cdmm.h) so that the bus driver
knows where it should put the CDMM region in the physical address space
if the bootloader hasn't already enabled it.

A mips_cdmm_early_probe() function is also provided to allow early boot
or particularly low level code to set up the CDMM region and probe for a
specific device type, for example early console or KGDB IO drivers for
the EJTAG Fast Debug Channel (FDC) CDMM device.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/9599/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>