ath5k: Reset Tx interrupt bits also on PISR

Some cards don't update the PISR properly when all SISR bits
for Tx interrupts are being cleared and as a result we get
interrupt storm. Since we handle all tx queues all together
(so we don't really use the SISR bits to do per-queue interrupt
handling), we can manualy update PISR by doing a write-to-clear
on its Tx interrupt bits.

Signed-off-by: Nick Kossifidis <mickflemm@gmail.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

diff --git a/drivers/net/wireless/ath/ath5k/dma.c b/drivers/net/wireless/ath/ath5k/dma.c
index ba200b24be64cd307483fad13fef4a9283a93784..e6c52f7c26e73a1495cff43bed603059e517b9ab 100644 (file)
--- a/drivers/net/wireless/ath/ath5k/dma.c
+++ b/drivers/net/wireless/ath/ath5k/dma.c
@@ -616,7 +616,16 @@ ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
                 * SISRs will also clear PISR so no need to worry here.
                 */
 
-               pisr_clear = pisr & ~AR5K_ISR_BITS_FROM_SISRS;
+               /* XXX: There seems to be  an issue on some cards
+                *      with tx interrupt flags not being updated
+                *      on PISR despite that all Tx interrupt bits
+                *      are cleared on SISRs. Since we handle all
+                *      Tx queues all together it shouldn't be an
+                *      issue if we clear Tx interrupt flags also
+                *      on PISR to avoid that.
+                */
+               pisr_clear = (pisr & ~AR5K_ISR_BITS_FROM_SISRS) |
+                                       (pisr & AR5K_INT_TX_ALL);
 
                /*
                 * Write to clear them...