MIPS: Fix delay loops which may be removed by GCC.

GCC 4.1 and newer remove empty loops.  This becomes a problem when delay
loops get removed.  Fixed by rewriting to user the proper Linux interface
for such delays.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Reported-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Acked-by: John Crispin <blogic@openwrt.org>

diff --git a/arch/mips/pci/pci-rt2880.c b/arch/mips/pci/pci-rt2880.c
index 8a978022630b252fa0547dd137805d6b3c35ec3b..dbbeccc3d714add203aae3ebb5b3a0cd1522f0ae 100644 (file)
--- a/arch/mips/pci/pci-rt2880.c
+++ b/arch/mips/pci/pci-rt2880.c
@@ -11,6 +11,7 @@
  *  by the Free Software Foundation.
  */
 
  *  by the Free Software Foundation.
  */
 

+#include <linux/delay.h>

 #include <linux/types.h>
 #include <linux/pci.h>
 #include <linux/io.h>
 #include <linux/types.h>
 #include <linux/pci.h>
 #include <linux/io.h>


@@ -232,8 +233,7 @@ static int rt288x_pci_probe(struct platform_device *pdev)
        ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;
 
        rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
        ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;
 
        rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);

-       for (i = 0; i < 0xfffff; i++)
-               ;
+       udelay(1);

 
        rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
        rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
 
        rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
        rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);

diff --git a/arch/mips/pmcs-msp71xx/msp_setup.c b/arch/mips/pmcs-msp71xx/msp_setup.c
index 4f925e06c414663023765630cd84211d62679e16..78b2ef49dbc7a45adc720264f66cc9922453ceb2 100644 (file)
--- a/arch/mips/pmcs-msp71xx/msp_setup.c
+++ b/arch/mips/pmcs-msp71xx/msp_setup.c
@@ -10,6 +10,8 @@
  * option) any later version.
  */
 
  * option) any later version.
  */
 

+#include <linux/delay.h>
+

 #include <asm/bootinfo.h>
 #include <asm/cacheflush.h>
 #include <asm/idle.h>
 #include <asm/bootinfo.h>
 #include <asm/cacheflush.h>
 #include <asm/idle.h>


@@ -77,7 +79,7 @@ void msp7120_reset(void)
         */
 
        /* Wait a bit for the DDRC to settle */
         */
 
        /* Wait a bit for the DDRC to settle */

-       for (i = 0; i < 100000000; i++);
+       mdelay(125);

 
 #if defined(CONFIG_PMC_MSP7120_GW)
        /*
 
 #if defined(CONFIG_PMC_MSP7120_GW)
        /*

diff --git a/arch/mips/sni/reset.c b/arch/mips/sni/reset.c
index 244f9427625b5873003cc92132c96a32d99663eb..db8f88b6a3af9cb52dcb2a2a23df94a49cc0eccd 100644 (file)
--- a/arch/mips/sni/reset.c
+++ b/arch/mips/sni/reset.c
@@ -3,6 +3,8 @@
  *
  *  Reset a SNI machine.
  */
  *
  *  Reset a SNI machine.
  */

+#include <linux/delay.h>
+

 #include <asm/io.h>
 #include <asm/reboot.h>
 #include <asm/sni.h>
 #include <asm/io.h>
 #include <asm/reboot.h>
 #include <asm/sni.h>


@@ -32,9 +34,9 @@ void sni_machine_restart(char *command)
        for (;;) {
                for (i = 0; i < 100; i++) {
                        kb_wait();
        for (;;) {
                for (i = 0; i < 100; i++) {
                        kb_wait();

-                       for (j = 0; j < 100000 ; j++)
-                               /* nothing */;
+                       udelay(50);

                        outb_p(0xfe, 0x64);      /* pulse reset low */
                        outb_p(0xfe, 0x64);      /* pulse reset low */

+                       udelay(50);

                }
        }
 }
                }
        }
 }