irqchip/gic: Warn if GICv3 system registers are enabled

When using a GICv3 in compatibility (v2) mode, having GICv3 system
register access enabled is not really compliant with the architecture.

Warn if the firmware (or the hypervisor) has been lazy.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index d0ce7ed1ac8ad4f7c14e9b6414d0b61abd2770e5..a9f23cfa9c96800c9a9cb419615bfac9e218cee5 100644 (file)
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -51,6 +51,19 @@
 
 #include "irq-gic-common.h"
 
 
 #include "irq-gic-common.h"
 

+#ifdef CONFIG_ARM64
+#include <asm/cpufeature.h>
+
+static void gic_check_cpu_features(void)
+{
+       WARN_TAINT_ONCE(cpus_have_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
+                       TAINT_CPU_OUT_OF_SPEC,
+                       "GICv3 system registers enabled, broken firmware!\n");
+}
+#else
+#define gic_check_cpu_features()       do { } while(0)
+#endif
+

 union gic_base {
        void __iomem *common_base;
        void __percpu * __iomem *percpu_base;
 union gic_base {
        void __iomem *common_base;
        void __percpu * __iomem *percpu_base;


@@ -987,6 +1000,8 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
 
        BUG_ON(gic_nr >= MAX_GIC_NR);
 
 
        BUG_ON(gic_nr >= MAX_GIC_NR);
 

+       gic_check_cpu_features();
+

        gic = &gic_data[gic_nr];
 #ifdef CONFIG_GIC_NON_BANKED
        if (percpu_offset) { /* Frankein-GIC without banked registers... */
        gic = &gic_data[gic_nr];
 #ifdef CONFIG_GIC_NON_BANKED
        if (percpu_offset) { /* Frankein-GIC without banked registers... */