MIPS: Whitespace cleanup.

Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index f2dfd404550c787b4e8dda7acddae03c60e12282..6f7978f95090f5dbdfe5bf761b008becf0df6cb2 100644 (file)
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -191,7 +191,7 @@ endif
 include $(srctree)/arch/mips/Kbuild.platforms
 
 ifdef CONFIG_PHYSICAL_START
 include $(srctree)/arch/mips/Kbuild.platforms
 
 ifdef CONFIG_PHYSICAL_START

-load-y                                  = $(CONFIG_PHYSICAL_START)
+load-y                                 = $(CONFIG_PHYSICAL_START)

 endif
 
 cflags-y                       += -I$(srctree)/arch/mips/include/asm/mach-generic
 endif
 
 cflags-y                       += -I$(srctree)/arch/mips/include/asm/mach-generic

diff --git a/arch/mips/alchemy/Platform b/arch/mips/alchemy/Platform
index 942c5800a684e6516c5b7068b2f89d29ee63bf7e..fa1bdd1aea15875989e187c6d14728e245058f75 100644 (file)
--- a/arch/mips/alchemy/Platform
+++ b/arch/mips/alchemy/Platform
@@ -1,7 +1,7 @@
 #
 # Core Alchemy code
 #
 #
 # Core Alchemy code
 #

-platform-$(CONFIG_MIPS_ALCHEMY)        += alchemy/common/
+platform-$(CONFIG_MIPS_ALCHEMY) += alchemy/common/

 
 
 #
 
 
 #


@@ -45,7 +45,7 @@ load-$(CONFIG_MIPS_MTX1)      += 0xffffffff80100000
 #
 # MyCable eval board
 #
 #
 # MyCable eval board
 #

-platform-$(CONFIG_MIPS_XXS1500)        += alchemy/
+platform-$(CONFIG_MIPS_XXS1500) += alchemy/

 load-$(CONFIG_MIPS_XXS1500)    += 0xffffffff80100000
 
 #
 load-$(CONFIG_MIPS_XXS1500)    += 0xffffffff80100000
 
 #


@@ -56,7 +56,7 @@ load-$(CONFIG_MIPS_GPR)               += 0xffffffff80100000
 
 # boards can specify their own <gpio.h> in one of their include dirs.
 # If they do, placing this line here at the end will make sure the
 
 # boards can specify their own <gpio.h> in one of their include dirs.
 # If they do, placing this line here at the end will make sure the

-# compiler picks the board one.  If they don't, it will make sure
+# compiler picks the board one.         If they don't, it will make sure

 # the alchemy generic gpio header is picked up.
 
 cflags-$(CONFIG_MIPS_ALCHEMY)  += -I$(srctree)/arch/mips/include/asm/mach-au1x00
 # the alchemy generic gpio header is picked up.
 
 cflags-$(CONFIG_MIPS_ALCHEMY)  += -I$(srctree)/arch/mips/include/asm/mach-au1x00

diff --git a/arch/mips/alchemy/board-gpr.c b/arch/mips/alchemy/board-gpr.c
index ba3259086b9db602cc189845491ab448febf9ee3..cb0f6afb73894ef16019b7a53861330a49d72d27 100644 (file)
--- a/arch/mips/alchemy/board-gpr.c
+++ b/arch/mips/alchemy/board-gpr.c
@@ -135,33 +135,33 @@ static struct mtd_partition gpr_mtd_partitions[] = {
        {
                .name   = "kernel",
                .size   = 0x00200000,
        {
                .name   = "kernel",
                .size   = 0x00200000,

-               .offset = 0,
+               .offset = 0,

        },
        {
                .name   = "rootfs",
                .size   = 0x00800000,
        },
        {
                .name   = "rootfs",
                .size   = 0x00800000,

-               .offset = MTDPART_OFS_APPEND,
+               .offset = MTDPART_OFS_APPEND,

                .mask_flags = MTD_WRITEABLE,
        },
        {
                .name   = "config",
                .size   = 0x00200000,
                .mask_flags = MTD_WRITEABLE,
        },
        {
                .name   = "config",
                .size   = 0x00200000,

-               .offset = 0x01d00000,
+               .offset = 0x01d00000,

        },
        {
                .name   = "yamon",
                .size   = 0x00100000,
        },
        {
                .name   = "yamon",
                .size   = 0x00100000,

-               .offset = 0x01c00000,
+               .offset = 0x01c00000,

        },
        {
                .name   = "yamon env vars",
                .size   = 0x00040000,
        },
        {
                .name   = "yamon env vars",
                .size   = 0x00040000,

-               .offset = MTDPART_OFS_APPEND,
+               .offset = MTDPART_OFS_APPEND,

        },
        {
                .name   = "kernel+rootfs",
                .size   = 0x00a00000,
        },
        {
                .name   = "kernel+rootfs",
                .size   = 0x00a00000,

-               .offset = 0,
+               .offset = 0,

        },
 };
 
        },
 };
 

diff --git a/arch/mips/alchemy/board-mtx1.c b/arch/mips/alchemy/board-mtx1.c
index a124c251c0c92a2bbbcc8f86ab2674aa5a8ad6a4..4a9baa9f63300cab298d913009c3d840d8adbc12 100644 (file)
--- a/arch/mips/alchemy/board-mtx1.c
+++ b/arch/mips/alchemy/board-mtx1.c
@@ -173,23 +173,23 @@ static struct mtd_partition mtx1_mtd_partitions[] = {
        {
                .name   = "filesystem",
                .size   = 0x01C00000,
        {
                .name   = "filesystem",
                .size   = 0x01C00000,

-               .offset = 0,
+               .offset = 0,

        },
        {
                .name   = "yamon",
                .size   = 0x00100000,
        },
        {
                .name   = "yamon",
                .size   = 0x00100000,

-               .offset = MTDPART_OFS_APPEND,
+               .offset = MTDPART_OFS_APPEND,

                .mask_flags = MTD_WRITEABLE,
        },
        {
                .name   = "kernel",
                .size   = 0x002c0000,
                .mask_flags = MTD_WRITEABLE,
        },
        {
                .name   = "kernel",
                .size   = 0x002c0000,

-               .offset = MTDPART_OFS_APPEND,
+               .offset = MTDPART_OFS_APPEND,

        },
        {
                .name   = "yamon env",
                .size   = 0x00040000,
        },
        {
                .name   = "yamon env",
                .size   = 0x00040000,

-               .offset = MTDPART_OFS_APPEND,
+               .offset = MTDPART_OFS_APPEND,

        },
 };
 
        },
 };
 

diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index cf02d7dc2df0abbc24cd14f6a6de6ebb1800e03c..19d5642c16d9a6be96f9e62b1d931093988ab1a7 100644 (file)
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -252,7 +252,7 @@ EXPORT_SYMBOL(au1xxx_ddma_del_device);
 u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
        void (*callback)(int, void *), void *callparam)
 {
 u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
        void (*callback)(int, void *), void *callparam)
 {

-       unsigned long   flags;
+       unsigned long   flags;

        u32             used, chan;
        u32             dcp;
        int             i;
        u32             used, chan;
        u32             dcp;
        int             i;


@@ -512,7 +512,7 @@ u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
                break;
        }
 
                break;
        }
 

-       /* If source input is FIFO, set static address. */
+       /* If source input is FIFO, set static address. */

        if (stp->dev_flags & DEV_FLAGS_IN) {
                if (stp->dev_flags & DEV_FLAGS_BURSTABLE)
                        src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
        if (stp->dev_flags & DEV_FLAGS_IN) {
                if (stp->dev_flags & DEV_FLAGS_BURSTABLE)
                        src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);


@@ -635,7 +635,7 @@ u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
        dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
        ctp->chan_ptr->ddma_dbell = 0;
 
        dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
        ctp->chan_ptr->ddma_dbell = 0;
 

-       /* Get next descriptor pointer. */
+       /* Get next descriptor pointer. */

        ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
 
        /* Return something non-zero. */
        ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
 
        /* Return something non-zero. */


@@ -697,7 +697,7 @@ u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
        dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
        ctp->chan_ptr->ddma_dbell = 0;
 
        dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
        ctp->chan_ptr->ddma_dbell = 0;
 

-       /* Get next descriptor pointer. */
+       /* Get next descriptor pointer. */

        ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
 
        /* Return something non-zero. */
        ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
 
        /* Return something non-zero. */


@@ -742,7 +742,7 @@ u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes)
        *nbytes = dp->dscr_cmd1;
        rv = dp->dscr_stat;
 
        *nbytes = dp->dscr_cmd1;
        rv = dp->dscr_stat;
 

-       /* Get next descriptor pointer. */
+       /* Get next descriptor pointer. */

        ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
 
        /* Return something non-zero. */
        ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
 
        /* Return something non-zero. */


@@ -891,7 +891,7 @@ void au1xxx_dbdma_dump(u32 chanid)
        chan_tab_t       *ctp;
        au1x_ddma_desc_t *dp;
        dbdev_tab_t      *stp, *dtp;
        chan_tab_t       *ctp;
        au1x_ddma_desc_t *dp;
        dbdev_tab_t      *stp, *dtp;

-       au1x_dma_chan_t  *cp;
+       au1x_dma_chan_t  *cp;

        u32 i            = 0;
 
        ctp = *((chan_tab_t **)chanid);
        u32 i            = 0;
 
        ctp = *((chan_tab_t **)chanid);


@@ -969,7 +969,7 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr)
        dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
        ctp->chan_ptr->ddma_dbell = 0;
 
        dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
        ctp->chan_ptr->ddma_dbell = 0;
 

-       /* Get next descriptor pointer. */
+       /* Get next descriptor pointer. */

        ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
 
        /* Return something non-zero. */
        ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
 
        /* Return something non-zero. */

diff --git a/arch/mips/alchemy/common/gpiolib.c b/arch/mips/alchemy/common/gpiolib.c
index f1b50f0c01db470ce008f74c1855532ded04c4be..f9bc4f520440142b2be4b033c8166f684bd1fc75 100644 (file)
--- a/arch/mips/alchemy/common/gpiolib.c
+++ b/arch/mips/alchemy/common/gpiolib.c
@@ -106,14 +106,14 @@ struct gpio_chip alchemy_gpio_chip[] = {
                .ngpio                  = ALCHEMY_GPIO1_NUM,
        },
        [1] = {
                .ngpio                  = ALCHEMY_GPIO1_NUM,
        },
        [1] = {

-               .label                  = "alchemy-gpio2",
-               .direction_input        = gpio2_direction_input,
-               .direction_output       = gpio2_direction_output,
-               .get                    = gpio2_get,
-               .set                    = gpio2_set,
+               .label                  = "alchemy-gpio2",
+               .direction_input        = gpio2_direction_input,
+               .direction_output       = gpio2_direction_output,
+               .get                    = gpio2_get,
+               .set                    = gpio2_set,

                .to_irq                 = gpio2_to_irq,
                .to_irq                 = gpio2_to_irq,

-               .base                   = ALCHEMY_GPIO2_BASE,
-               .ngpio                  = ALCHEMY_GPIO2_NUM,
+               .base                   = ALCHEMY_GPIO2_BASE,
+               .ngpio                  = ALCHEMY_GPIO2_NUM,

        },
 };
 
        },
 };
 

diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index 94fbcd19eb9ca9631425a6cf20c055c3807e72ac..63a71817a00cbc92acdcab670aabb1f97eecf028 100644 (file)
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -84,20 +84,20 @@ static int au1300_gpic_settype(struct irq_data *d, unsigned int type);
  * needs the highest priority.
  */
 struct alchemy_irqmap au1000_irqmap[] __initdata = {
  * needs the highest priority.
  */
 struct alchemy_irqmap au1000_irqmap[] __initdata = {

-       { AU1000_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1000_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1000_UART2_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1000_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1000_SSI0_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1000_SSI1_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1000_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1000_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1000_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1000_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1000_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1000_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1000_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1000_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1000_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1000_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1000_UART2_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1000_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1000_SSI0_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1000_SSI1_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1000_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1000_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1000_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1000_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1000_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1000_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1000_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1000_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },

        { AU1000_TOY_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1000_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1000_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1000_TOY_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1000_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1000_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },


@@ -106,33 +106,33 @@ struct alchemy_irqmap au1000_irqmap[] __initdata = {
        { AU1000_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1000_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1000_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0, 0 },
        { AU1000_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1000_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1000_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0, 0 },

-       { AU1000_IRDA_TX_INT,     IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1000_IRDA_RX_INT,     IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  0, 0 },
+       { AU1000_IRDA_TX_INT,     IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1000_IRDA_RX_INT,     IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  0, 0 },

        { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },

-       { AU1000_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   1, 0 },
+       { AU1000_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   1, 0 },

        { AU1000_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1000_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 1, 0 },

-       { AU1000_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1000_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1000_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1000_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },

        { AU1000_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 1, 0 },
        { -1, },
 };
 
 struct alchemy_irqmap au1500_irqmap[] __initdata = {
        { AU1000_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 1, 0 },
        { -1, },
 };
 
 struct alchemy_irqmap au1500_irqmap[] __initdata = {

-       { AU1500_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1500_PCI_INTA,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
-       { AU1500_PCI_INTB,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
-       { AU1500_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1500_PCI_INTC,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
-       { AU1500_PCI_INTD,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
-       { AU1500_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1500_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1500_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1500_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1500_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1500_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1500_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1500_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1500_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1500_PCI_INTA,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
+       { AU1500_PCI_INTB,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
+       { AU1500_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1500_PCI_INTC,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
+       { AU1500_PCI_INTD,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
+       { AU1500_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1500_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1500_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1500_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1500_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1500_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1500_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1500_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },

        { AU1500_TOY_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1500_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1500_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1500_TOY_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1500_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1500_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },


@@ -141,31 +141,31 @@ struct alchemy_irqmap au1500_irqmap[] __initdata = {
        { AU1500_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1500_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1500_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0, 0 },
        { AU1500_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1500_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1500_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0, 0 },

-       { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  0, 0 },
+       { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  0, 0 },

        { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },

-       { AU1500_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   1, 0 },
+       { AU1500_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   1, 0 },

        { AU1500_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1500_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 1, 0 },

-       { AU1500_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1500_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1500_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1500_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },

        { AU1500_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 1, 0 },
        { -1, },
 };
 
 struct alchemy_irqmap au1100_irqmap[] __initdata = {
        { AU1500_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 1, 0 },
        { -1, },
 };
 
 struct alchemy_irqmap au1100_irqmap[] __initdata = {

-       { AU1100_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1100_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1100_SD_INT,          IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1100_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1100_SSI0_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1100_SSI1_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1100_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1100_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1100_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1100_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1100_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1100_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1100_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1100_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1100_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1100_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1100_SD_INT,          IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1100_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1100_SSI0_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1100_SSI1_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1100_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1100_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1100_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1100_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1100_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1100_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1100_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1100_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  1, 0 },

        { AU1100_TOY_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1100_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1100_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1100_TOY_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1100_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1100_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },


@@ -174,33 +174,33 @@ struct alchemy_irqmap au1100_irqmap[] __initdata = {
        { AU1100_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1100_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1100_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0, 0 },
        { AU1100_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1100_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1100_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0, 0 },

-       { AU1100_IRDA_TX_INT,     IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1100_IRDA_RX_INT,     IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  0, 0 },
+       { AU1100_IRDA_TX_INT,     IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1100_IRDA_RX_INT,     IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  0, 0 },

        { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },

-       { AU1100_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   1, 0 },
+       { AU1100_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   1, 0 },

        { AU1100_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1100_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 1, 0 },

-       { AU1100_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1100_LCD_INT,         IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1100_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1100_LCD_INT,         IRQ_TYPE_LEVEL_HIGH,  1, 0 },

        { AU1100_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 1, 0 },
        { -1, },
 };
 
 struct alchemy_irqmap au1550_irqmap[] __initdata = {
        { AU1100_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 1, 0 },
        { -1, },
 };
 
 struct alchemy_irqmap au1550_irqmap[] __initdata = {

-       { AU1550_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1550_PCI_INTA,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
-       { AU1550_PCI_INTB,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
-       { AU1550_DDMA_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1550_CRYPTO_INT,      IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1550_PCI_INTC,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
-       { AU1550_PCI_INTD,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
-       { AU1550_PCI_RST_INT,     IRQ_TYPE_LEVEL_LOW,   1, 0 },
-       { AU1550_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1550_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1550_PSC0_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1550_PSC1_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1550_PSC2_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1550_PSC3_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1550_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1550_PCI_INTA,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
+       { AU1550_PCI_INTB,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
+       { AU1550_DDMA_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1550_CRYPTO_INT,      IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1550_PCI_INTC,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
+       { AU1550_PCI_INTD,        IRQ_TYPE_LEVEL_LOW,   1, 0 },
+       { AU1550_PCI_RST_INT,     IRQ_TYPE_LEVEL_LOW,   1, 0 },
+       { AU1550_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1550_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1550_PSC0_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1550_PSC1_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1550_PSC2_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1550_PSC3_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },

        { AU1550_TOY_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1550_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1550_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1550_TOY_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1550_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1550_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },


@@ -210,26 +210,26 @@ struct alchemy_irqmap au1550_irqmap[] __initdata = {
        { AU1550_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1550_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0, 0 },
        { AU1550_NAND_INT,        IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1550_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1550_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0, 0 },
        { AU1550_NAND_INT,        IRQ_TYPE_EDGE_RISING, 1, 0 },

-       { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  0, 0 },
+       { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  0, 0 },

        { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1, 0 },

-       { AU1550_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   1, 0 },
-       { AU1550_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1550_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1550_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   1, 0 },
+       { AU1550_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1550_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },

        { -1, },
 };
 
 struct alchemy_irqmap au1200_irqmap[] __initdata = {
        { -1, },
 };
 
 struct alchemy_irqmap au1200_irqmap[] __initdata = {

-       { AU1200_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1200_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },

        { AU1200_SWT_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1200_SWT_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },

-       { AU1200_SD_INT,          IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1200_DDMA_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1200_MAE_BE_INT,      IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1200_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1200_MAE_FE_INT,      IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1200_PSC0_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1200_PSC1_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1200_AES_INT,         IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1200_CAMERA_INT,      IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1200_SD_INT,          IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1200_DDMA_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1200_MAE_BE_INT,      IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1200_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1200_MAE_FE_INT,      IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1200_PSC0_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1200_PSC1_INT,        IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1200_AES_INT,         IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1200_CAMERA_INT,      IRQ_TYPE_LEVEL_HIGH,  1, 0 },

        { AU1200_TOY_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1200_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1200_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1200_TOY_INT,         IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1200_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1200_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },


@@ -239,9 +239,9 @@ struct alchemy_irqmap au1200_irqmap[] __initdata = {
        { AU1200_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1200_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0, 0 },
        { AU1200_NAND_INT,        IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1200_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 1, 0 },
        { AU1200_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0, 0 },
        { AU1200_NAND_INT,        IRQ_TYPE_EDGE_RISING, 1, 0 },

-       { AU1200_USB_INT,         IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1200_LCD_INT,         IRQ_TYPE_LEVEL_HIGH,  1, 0 },
-       { AU1200_MAE_BOTH_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1200_USB_INT,         IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1200_LCD_INT,         IRQ_TYPE_LEVEL_HIGH,  1, 0 },
+       { AU1200_MAE_BOTH_INT,    IRQ_TYPE_LEVEL_HIGH,  1, 0 },

        { -1, },
 };
 
        { -1, },
 };
 

diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 7af941d8e717089cdb78b016368774a09e3bd4ef..9837a134a6d609eac55d6514a8f06b6766d05bbb 100644 (file)
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -53,7 +53,7 @@ static void alchemy_8250_pm(struct uart_port *port, unsigned int state,
                .irq            = _irq,                         \
                .regshift       = 2,                            \
                .iotype         = UPIO_AU,                      \
                .irq            = _irq,                         \
                .regshift       = 2,                            \
                .iotype         = UPIO_AU,                      \

-               .flags          = UPF_SKIP_TEST | UPF_IOREMAP | \
+               .flags          = UPF_SKIP_TEST | UPF_IOREMAP | \

                                  UPF_FIXED_TYPE,               \
                .type           = PORT_16550A,                  \
                .pm             = alchemy_8250_pm,              \
                                  UPF_FIXED_TYPE,               \
                .type           = PORT_16550A,                  \
                .pm             = alchemy_8250_pm,              \


@@ -137,7 +137,7 @@ static void alchemy_ehci_power_off(struct platform_device *pdev)
 }
 
 static struct usb_ehci_pdata alchemy_ehci_pdata = {
 }
 
 static struct usb_ehci_pdata alchemy_ehci_pdata = {

-       .no_io_watchdog = 1,
+       .no_io_watchdog = 1,

        .power_on       = alchemy_ehci_power_on,
        .power_off      = alchemy_ehci_power_off,
        .power_suspend  = alchemy_ehci_power_off,
        .power_on       = alchemy_ehci_power_on,
        .power_off      = alchemy_ehci_power_off,
        .power_suspend  = alchemy_ehci_power_off,

diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index 37ffd997c6165e2c0ebfab28b82d0c8872156a87..62b4e7bbeab9efde6e40953d34ef1f44bfbda02b 100644 (file)
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -59,7 +59,7 @@ void __init plat_mem_setup(void)
                /* Clear to obtain best system bus performance */
                clear_c0_config(1 << 19); /* Clear Config[OD] */
 
                /* Clear to obtain best system bus performance */
                clear_c0_config(1 << 19); /* Clear Config[OD] */
 

-       board_setup();  /* board specific setup */
+       board_setup();  /* board specific setup */

 
        /* IO/MEM resources. */
        set_io_port_base(0);
 
        /* IO/MEM resources. */
        set_io_port_base(0);

diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S
index c7bcc7e5c822bb571164e27fcfa284838cc92c38..706d933e00855ef507fafd13abf42539eea20084 100644 (file)
--- a/arch/mips/alchemy/common/sleeper.S
+++ b/arch/mips/alchemy/common/sleeper.S
@@ -102,12 +102,12 @@ LEAF(alchemy_sleep_au1000)
        cache   0x14, 96(t0)
        .set    mips0
 
        cache   0x14, 96(t0)
        .set    mips0
 

-1:     lui     a0, 0xb400              /* mem_xxx */
-       sw      zero, 0x001c(a0)        /* Precharge */
+1:     lui     a0, 0xb400              /* mem_xxx */
+       sw      zero, 0x001c(a0)        /* Precharge */

        sync
        sw      zero, 0x0020(a0)        /* Auto Refresh */
        sync
        sync
        sw      zero, 0x0020(a0)        /* Auto Refresh */
        sync

-       sw      zero, 0x0030(a0)        /* Sleep */
+       sw      zero, 0x0030(a0)        /* Sleep */

        sync
 
        DO_SLEEP
        sync
 
        DO_SLEEP


@@ -128,15 +128,15 @@ LEAF(alchemy_sleep_au1550)
        cache   0x14, 96(t0)
        .set    mips0
 
        cache   0x14, 96(t0)
        .set    mips0
 

-1:     lui     a0, 0xb400              /* mem_xxx */
-       sw      zero, 0x08c0(a0)        /* Precharge */
+1:     lui     a0, 0xb400              /* mem_xxx */
+       sw      zero, 0x08c0(a0)        /* Precharge */

        sync
        sw      zero, 0x08d0(a0)        /* Self Refresh */
        sync
 
        /* wait for sdram to enter self-refresh mode */
        sync
        sw      zero, 0x08d0(a0)        /* Self Refresh */
        sync
 
        /* wait for sdram to enter self-refresh mode */

-       lui     t0, 0x0100
-2:     lw      t1, 0x0850(a0)          /* mem_sdstat */
+       lui     t0, 0x0100
+2:     lw      t1, 0x0850(a0)          /* mem_sdstat */

        and     t2, t1, t0
        beq     t2, zero, 2b
         nop
        and     t2, t1, t0
        beq     t2, zero, 2b
         nop


@@ -144,9 +144,9 @@ LEAF(alchemy_sleep_au1550)
        /* disable SDRAM clocks */
        lui     t0, 0xcfff
        ori     t0, t0, 0xffff
        /* disable SDRAM clocks */
        lui     t0, 0xcfff
        ori     t0, t0, 0xffff

-       lw      t1, 0x0840(a0)          /* mem_sdconfiga */
-       and     t1, t0, t1              /* clear CE[1:0] */
-       sw      t1, 0x0840(a0)          /* mem_sdconfiga */
+       lw      t1, 0x0840(a0)          /* mem_sdconfiga */
+       and     t1, t0, t1              /* clear CE[1:0] */
+       sw      t1, 0x0840(a0)          /* mem_sdconfiga */

        sync
 
        DO_SLEEP
        sync
 
        DO_SLEEP

diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index b67930d1932510dbe90cfc64b2b937d135d162ce..38afb11ba2c4605e5c370f979eba3bc86a97621b 100644 (file)
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -85,7 +85,7 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = {
        .name           = "rtcmatch2",
        .features       = CLOCK_EVT_FEAT_ONESHOT,
        .rating         = 1500,
        .name           = "rtcmatch2",
        .features       = CLOCK_EVT_FEAT_ONESHOT,
        .rating         = 1500,

-       .set_next_event = au1x_rtcmatch2_set_next_event,
+       .set_next_event = au1x_rtcmatch2_set_next_event,

        .set_mode       = au1x_rtcmatch2_set_mode,
        .cpumask        = cpu_all_mask,
 };
        .set_mode       = au1x_rtcmatch2_set_mode,
        .cpumask        = cpu_all_mask,
 };

diff --git a/arch/mips/alchemy/common/usb.c b/arch/mips/alchemy/common/usb.c
index 936af8359fb2007f024b0dfa6b0499afe6983241..fcc69562611716957cdec6b268ff36dac49f0664 100644 (file)
--- a/arch/mips/alchemy/common/usb.c
+++ b/arch/mips/alchemy/common/usb.c
@@ -122,7 +122,7 @@ static inline void __au1300_ohci_control(void __iomem *base, int enable, int id)
        unsigned long r;
 
        if (enable) {
        unsigned long r;
 
        if (enable) {

-               __raw_writel(1, base + USB_DWC_CTRL7);  /* start OHCI clock */
+               __raw_writel(1, base + USB_DWC_CTRL7);  /* start OHCI clock */

                wmb();
 
                r = __raw_readl(base + USB_DWC_CTRL3);  /* enable OHCI block */
                wmb();
 
                r = __raw_readl(base + USB_DWC_CTRL3);  /* enable OHCI block */

diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c
index f2039ef2c293615470481733747b7e198d797d75..c98c9ea3372c53797d317f9b43c2614c82b0f58d 100644 (file)
--- a/arch/mips/alchemy/devboards/bcsr.c
+++ b/arch/mips/alchemy/devboards/bcsr.c
@@ -20,7 +20,7 @@ static struct bcsr_reg {
        spinlock_t lock;
 } bcsr_regs[BCSR_CNT];
 
        spinlock_t lock;
 } bcsr_regs[BCSR_CNT];
 

-static void __iomem *bcsr_virt;        /* KSEG1 addr of BCSR base */
+static void __iomem *bcsr_virt; /* KSEG1 addr of BCSR base */

 static int bcsr_csc_base;      /* linux-irq of first cascaded irq */
 
 void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys)
 static int bcsr_csc_base;      /* linux-irq of first cascaded irq */
 
 void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys)

diff --git a/arch/mips/alchemy/devboards/db1000.c b/arch/mips/alchemy/devboards/db1000.c
index 8187845650f70473f7c021f600dbc827fb5a773c..11f3ad20321ca64a1c5d6bf98b4d6d8a141cc92d 100644 (file)
--- a/arch/mips/alchemy/devboards/db1000.c
+++ b/arch/mips/alchemy/devboards/db1000.c
@@ -276,7 +276,7 @@ static void db1100_mmcled_set(struct led_classdev *led, enum led_brightness b)
 }
 
 static struct led_classdev db1100_mmc_led = {
 }
 
 static struct led_classdev db1100_mmc_led = {

-       .brightness_set = db1100_mmcled_set,
+       .brightness_set = db1100_mmcled_set,

 };
 
 static int db1100_mmc1_card_readonly(void *mmc_host)
 };
 
 static int db1100_mmc1_card_readonly(void *mmc_host)


@@ -314,7 +314,7 @@ static void db1100_mmc1led_set(struct led_classdev *led, enum led_brightness b)
 }
 
 static struct led_classdev db1100_mmc1_led = {
 }
 
 static struct led_classdev db1100_mmc1_led = {

-       .brightness_set = db1100_mmc1led_set,
+       .brightness_set = db1100_mmc1led_set,

 };
 
 static struct au1xmmc_platform_data db1100_mmc_platdata[2] = {
 };
 
 static struct au1xmmc_platform_data db1100_mmc_platdata[2] = {


@@ -357,7 +357,7 @@ static struct resource au1100_mmc0_resources[] = {
        }
 };
 
        }
 };
 

-static u64 au1xxx_mmc_dmamask =  DMA_BIT_MASK(32);
+static u64 au1xxx_mmc_dmamask =         DMA_BIT_MASK(32);

 
 static struct platform_device db1100_mmc0_dev = {
        .name           = "au1xxx-mmc",
 
 static struct platform_device db1100_mmc0_dev = {
        .name           = "au1xxx-mmc",


@@ -482,7 +482,7 @@ static struct spi_board_info db1100_spi_info[] __initdata = {
                .mode            = 0,
                .irq             = AU1100_GPIO21_INT,
                .platform_data   = &db1100_touch_pd,
                .mode            = 0,
                .irq             = AU1100_GPIO21_INT,
                .platform_data   = &db1100_touch_pd,

-               .controller_data = (void *)210, /* for spi_gpio: CS# GPIO210 */
+               .controller_data = (void *)210, /* for spi_gpio: CS# GPIO210 */

        },
 };
 
        },
 };
 


@@ -572,7 +572,7 @@ static int __init db1000_dev_init(void)
                irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_LOW);
                irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW);
                /* EPSON S1D13806 0x1b000000
                irq_set_irq_type(AU1500_GPIO204_INT, IRQ_TYPE_LEVEL_LOW);
                irq_set_irq_type(AU1500_GPIO205_INT, IRQ_TYPE_LEVEL_LOW);
                /* EPSON S1D13806 0x1b000000

-                * SRAM 1MB/2MB   0x1a000000
+                * SRAM 1MB/2MB   0x1a000000

                 * DS1693 RTC     0x0c000000
                 */
        } else if (board == BCSR_WHOAMI_PB1100) {
                 * DS1693 RTC     0x0c000000
                 */
        } else if (board == BCSR_WHOAMI_PB1100) {


@@ -586,7 +586,7 @@ static int __init db1000_dev_init(void)
                irq_set_irq_type(AU1100_GPIO12_INT, IRQ_TYPE_LEVEL_LOW);
                irq_set_irq_type(AU1100_GPIO13_INT, IRQ_TYPE_LEVEL_LOW);
                /* EPSON S1D13806 0x1b000000
                irq_set_irq_type(AU1100_GPIO12_INT, IRQ_TYPE_LEVEL_LOW);
                irq_set_irq_type(AU1100_GPIO13_INT, IRQ_TYPE_LEVEL_LOW);
                /* EPSON S1D13806 0x1b000000

-                * SRAM 1MB/2MB   0x1a000000
+                * SRAM 1MB/2MB   0x1a000000

                 * DiskOnChip     0x0d000000
                 * DS1693 RTC     0x0c000000
                 */
                 * DiskOnChip     0x0d000000
                 * DS1693 RTC     0x0c000000
                 */


@@ -605,7 +605,7 @@ static int __init db1000_dev_init(void)
                AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
                AU1000_PCMCIA_IO_PHYS_ADDR,
                AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
                AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
                AU1000_PCMCIA_IO_PHYS_ADDR,
                AU1000_PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,

-               c0, d0, /*s0*/0, 0, 0);
+               c0, d0, /*s0*/0, 0, 0);

 
        if (twosocks) {
                irq_set_irq_type(d1, IRQ_TYPE_EDGE_BOTH);
 
        if (twosocks) {
                irq_set_irq_type(d1, IRQ_TYPE_EDGE_BOTH);


@@ -619,7 +619,7 @@ static int __init db1000_dev_init(void)
                        AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,
                        AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004000000,
                        AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,
                        AU1000_PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,
                        AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004000000,
                        AU1000_PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,

-                       c1, d1, /*s1*/0, 0, 1);
+                       c1, d1, /*s1*/0, 0, 1);

        }
 
        platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs));
        }
 
        platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs));

diff --git a/arch/mips/alchemy/devboards/db1200.c b/arch/mips/alchemy/devboards/db1200.c
index 299b7d202bea79970b0195b6a42c9ddeadd04ba7..a84d98b8f96e8fbe2abfb4652f03c579ff3f3ab1 100644 (file)
--- a/arch/mips/alchemy/devboards/db1200.c
+++ b/arch/mips/alchemy/devboards/db1200.c
@@ -90,14 +90,14 @@ int __init db1200_board_setup(void)
 
        whoami = bcsr_read(BCSR_WHOAMI);
        printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d"
 
        whoami = bcsr_read(BCSR_WHOAMI);
        printk(KERN_INFO "Alchemy/AMD/RMI %s Board, CPLD Rev %d"

-               "  Board-ID %d  Daughtercard ID %d\n", get_system_type(),
+               "  Board-ID %d  Daughtercard ID %d\n", get_system_type(),

                (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
 
        /* SMBus/SPI on PSC0, Audio on PSC1 */
        pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
        pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
        pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
                (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
 
        /* SMBus/SPI on PSC0, Audio on PSC1 */
        pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
        pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
        pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);

-       pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
+       pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */

        __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
        wmb();
 
        __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
        wmb();
 


@@ -129,7 +129,7 @@ int __init db1200_board_setup(void)
 static struct mtd_partition db1200_spiflash_parts[] = {
        {
                .name   = "spi_flash",
 static struct mtd_partition db1200_spiflash_parts[] = {
        {
                .name   = "spi_flash",

-               .offset = 0,
+               .offset = 0,

                .size   = MTDPART_SIZ_FULL,
        },
 };
                .size   = MTDPART_SIZ_FULL,
        },
 };


@@ -200,12 +200,12 @@ static int au1200_nand_device_ready(struct mtd_info *mtd)
 static struct mtd_partition db1200_nand_parts[] = {
        {
                .name   = "NAND FS 0",
 static struct mtd_partition db1200_nand_parts[] = {
        {
                .name   = "NAND FS 0",

-               .offset = 0,
+               .offset = 0,

                .size   = 8 * 1024 * 1024,
        },
        {
                .name   = "NAND FS 1",
                .size   = 8 * 1024 * 1024,
        },
        {
                .name   = "NAND FS 1",

-               .offset = MTDPART_OFS_APPEND,
+               .offset = MTDPART_OFS_APPEND,

                .size   = MTDPART_SIZ_FULL
        },
 };
                .size   = MTDPART_SIZ_FULL
        },
 };


@@ -395,7 +395,7 @@ static void db1200_mmcled_set(struct led_classdev *led,
 }
 
 static struct led_classdev db1200_mmc_led = {
 }
 
 static struct led_classdev db1200_mmc_led = {

-       .brightness_set = db1200_mmcled_set,
+       .brightness_set = db1200_mmcled_set,

 };
 
 /* -- */
 };
 
 /* -- */


@@ -463,7 +463,7 @@ static void pb1200_mmc1led_set(struct led_classdev *led,
 }
 
 static struct led_classdev pb1200_mmc1_led = {
 }
 
 static struct led_classdev pb1200_mmc1_led = {

-       .brightness_set = pb1200_mmc1led_set,
+       .brightness_set = pb1200_mmc1led_set,

 };
 
 static void pb1200_mmc1_set_power(void *mmc_host, int state)
 };
 
 static void pb1200_mmc1_set_power(void *mmc_host, int state)


@@ -526,7 +526,7 @@ static struct resource au1200_mmc0_resources[] = {
        }
 };
 
        }
 };
 

-static u64 au1xxx_mmc_dmamask =  DMA_BIT_MASK(32);
+static u64 au1xxx_mmc_dmamask =         DMA_BIT_MASK(32);

 
 static struct platform_device db1200_mmc0_dev = {
        .name           = "au1xxx-mmc",
 
 static struct platform_device db1200_mmc0_dev = {
        .name           = "au1xxx-mmc",


@@ -601,7 +601,7 @@ static int db1200fb_panel_shutdown(void)
 static struct au1200fb_platdata db1200fb_pd = {
        .panel_index    = db1200fb_panel_index,
        .panel_init     = db1200fb_panel_init,
 static struct au1200fb_platdata db1200fb_pd = {
        .panel_index    = db1200fb_panel_index,
        .panel_init     = db1200fb_panel_init,

-       .panel_shutdown = db1200fb_panel_shutdown,
+       .panel_shutdown = db1200fb_panel_shutdown,

 };
 
 static struct resource au1200_lcd_res[] = {
 };
 
 static struct resource au1200_lcd_res[] = {


@@ -772,11 +772,11 @@ static int __init pb1200_res_fixup(void)
        }
 
        db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR;
        }
 
        db1200_nand_res[0].start = PB1200_NAND_PHYS_ADDR;

-       db1200_nand_res[0].end   = PB1200_NAND_PHYS_ADDR + 0xff;
+       db1200_nand_res[0].end   = PB1200_NAND_PHYS_ADDR + 0xff;

        db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR;
        db1200_ide_res[0].start = PB1200_IDE_PHYS_ADDR;

-       db1200_ide_res[0].end   = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1;
+       db1200_ide_res[0].end   = PB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1;

        db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR;
        db1200_eth_res[0].start = PB1200_ETH_PHYS_ADDR;

-       db1200_eth_res[0].end   = PB1200_ETH_PHYS_ADDR + 0xff;
+       db1200_eth_res[0].end   = PB1200_ETH_PHYS_ADDR + 0xff;

        return 0;
 }
 
        return 0;
 }
 


@@ -797,7 +797,7 @@ int __init db1200_dev_setup(void)
        irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW);
        bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
 
        irq_set_irq_type(AU1200_GPIO7_INT, IRQ_TYPE_LEVEL_LOW);
        bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
 

-       /* insert/eject pairs: one of both is always screaming.  To avoid
+       /* insert/eject pairs: one of both is always screaming.  To avoid

         * issues they must not be automatically enabled when initially
         * requested.
         */
         * issues they must not be automatically enabled when initially
         * requested.
         */


@@ -813,7 +813,7 @@ int __init db1200_dev_setup(void)
        spi_register_board_info(db1200_spi_devs,
                                ARRAY_SIZE(db1200_i2c_devs));
 
        spi_register_board_info(db1200_spi_devs,
                                ARRAY_SIZE(db1200_i2c_devs));
 

-       /* SWITCHES:    S6.8 I2C/SPI selector  (OFF=I2C  ON=SPI)
+       /* SWITCHES:    S6.8 I2C/SPI selector  (OFF=I2C  ON=SPI)

         *              S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
         *              or S12 on the PB1200.
         */
         *              S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
         *              or S12 on the PB1200.
         */

diff --git a/arch/mips/alchemy/devboards/db1300.c b/arch/mips/alchemy/devboards/db1300.c
index cdf37cbd3d1f80c3a1017be06a487b7d50a7adbe..6167e73eef9cb4d2e305109fbf0351a0373b6d76 100644 (file)
--- a/arch/mips/alchemy/devboards/db1300.c
+++ b/arch/mips/alchemy/devboards/db1300.c
@@ -80,7 +80,7 @@ static int db1300_dev_pins[] __initdata = {
        AU1300_PIN_PSC0D1,
        AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
        AU1300_PIN_PSC1D1,
        AU1300_PIN_PSC0D1,
        AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0,
        AU1300_PIN_PSC1D1,

-       AU1300_PIN_PSC2SYNC0,                       AU1300_PIN_PSC2D0,
+       AU1300_PIN_PSC2SYNC0,                       AU1300_PIN_PSC2D0,

        AU1300_PIN_PSC2D1,
        AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
        AU1300_PIN_PSC3D1,
        AU1300_PIN_PSC2D1,
        AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0,
        AU1300_PIN_PSC3D1,


@@ -143,12 +143,12 @@ static int au1300_nand_device_ready(struct mtd_info *mtd)
 static struct mtd_partition db1300_nand_parts[] = {
        {
                .name   = "NAND FS 0",
 static struct mtd_partition db1300_nand_parts[] = {
        {
                .name   = "NAND FS 0",

-               .offset = 0,
+               .offset = 0,

                .size   = 8 * 1024 * 1024,
        },
        {
                .name   = "NAND FS 1",
                .size   = 8 * 1024 * 1024,
        },
        {
                .name   = "NAND FS 1",

-               .offset = MTDPART_OFS_APPEND,
+               .offset = MTDPART_OFS_APPEND,

                .size   = MTDPART_SIZ_FULL
        },
 };
                .size   = MTDPART_SIZ_FULL
        },
 };


@@ -487,7 +487,7 @@ static void db1300_mmcled_set(struct led_classdev *led,
 }
 
 static struct led_classdev db1300_mmc_led = {
 }
 
 static struct led_classdev db1300_mmc_led = {

-       .brightness_set = db1300_mmcled_set,
+       .brightness_set = db1300_mmcled_set,

 };
 
 struct au1xmmc_platform_data db1300_sd1_platdata = {
 };
 
 struct au1xmmc_platform_data db1300_sd1_platdata = {


@@ -646,7 +646,7 @@ static int db1300fb_panel_shutdown(void)
 static struct au1200fb_platdata db1300fb_pd = {
        .panel_index    = db1300fb_panel_index,
        .panel_init     = db1300fb_panel_init,
 static struct au1200fb_platdata db1300fb_pd = {
        .panel_index    = db1300fb_panel_index,
        .panel_init     = db1300fb_panel_init,

-       .panel_shutdown = db1300fb_panel_shutdown,
+       .panel_shutdown = db1300fb_panel_shutdown,

 };
 
 static struct resource au1300_lcd_res[] = {
 };
 
 static struct resource au1300_lcd_res[] = {

diff --git a/arch/mips/alchemy/devboards/db1550.c b/arch/mips/alchemy/devboards/db1550.c
index 5a9ae609542879c7e6dcb219d0f3099bc4b939e1..016cddacd7ea34bb40717c183d94f12f99b75050 100644 (file)
--- a/arch/mips/alchemy/devboards/db1550.c
+++ b/arch/mips/alchemy/devboards/db1550.c
@@ -67,7 +67,7 @@ int __init db1550_board_setup(void)
                bcsr_init(PB1550_BCSR_PHYS_ADDR,
                          PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
 
                bcsr_init(PB1550_BCSR_PHYS_ADDR,
                          PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
 

-       pr_info("Alchemy/AMD %s Board, CPLD Rev %d Board-ID %d  "       \
+       pr_info("Alchemy/AMD %s Board, CPLD Rev %d Board-ID %d  "       \

                "Daughtercard ID %d\n", get_system_type(),
                (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
 
                "Daughtercard ID %d\n", get_system_type(),
                (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
 


@@ -80,7 +80,7 @@ int __init db1550_board_setup(void)
 static struct mtd_partition db1550_spiflash_parts[] = {
        {
                .name   = "spi_flash",
 static struct mtd_partition db1550_spiflash_parts[] = {
        {
                .name   = "spi_flash",

-               .offset = 0,
+               .offset = 0,

                .size   = MTDPART_SIZ_FULL,
        },
 };
                .size   = MTDPART_SIZ_FULL,
        },
 };


@@ -151,12 +151,12 @@ static int au1550_nand_device_ready(struct mtd_info *mtd)
 static struct mtd_partition db1550_nand_parts[] = {
        {
                .name   = "NAND FS 0",
 static struct mtd_partition db1550_nand_parts[] = {
        {
                .name   = "NAND FS 0",

-               .offset = 0,
+               .offset = 0,

                .size   = 8 * 1024 * 1024,
        },
        {
                .name   = "NAND FS 1",
                .size   = 8 * 1024 * 1024,
        },
        {
                .name   = "NAND FS 1",

-               .offset = MTDPART_OFS_APPEND,
+               .offset = MTDPART_OFS_APPEND,

                .size   = MTDPART_SIZ_FULL
        },
 };
                .size   = MTDPART_SIZ_FULL
        },
 };


@@ -495,10 +495,10 @@ static void __init db1550_devices(void)
 {
        alchemy_gpio_direction_output(203, 0);  /* red led on */
 
 {
        alchemy_gpio_direction_output(203, 0);  /* red led on */
 

-       irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH);  /* CD0# */
-       irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH);  /* CD1# */
-       irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW);  /* CARD0# */
-       irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW);  /* CARD1# */
+       irq_set_irq_type(AU1550_GPIO0_INT, IRQ_TYPE_EDGE_BOTH);  /* CD0# */
+       irq_set_irq_type(AU1550_GPIO1_INT, IRQ_TYPE_EDGE_BOTH);  /* CD1# */
+       irq_set_irq_type(AU1550_GPIO3_INT, IRQ_TYPE_LEVEL_LOW);  /* CARD0# */
+       irq_set_irq_type(AU1550_GPIO5_INT, IRQ_TYPE_LEVEL_LOW);  /* CARD1# */

        irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */
        irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */
 
        irq_set_irq_type(AU1550_GPIO21_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG0# */
        irq_set_irq_type(AU1550_GPIO22_INT, IRQ_TYPE_LEVEL_LOW); /* STSCHG1# */
 


@@ -539,7 +539,7 @@ static void __init pb1550_devices(void)
 
        /* Pb1550, like all others, also has statuschange irqs; however they're
        * wired up on one of the Au1550's shared GPIO201_205 line, which also
 
        /* Pb1550, like all others, also has statuschange irqs; however they're
        * wired up on one of the Au1550's shared GPIO201_205 line, which also

-       * services the PCMCIA card interrupts.  So we ignore statuschange and
+       * services the PCMCIA card interrupts.  So we ignore statuschange and

        * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia
        * drivers are used to shared irqs and b) statuschange isn't really use-
        * ful anyway.
        * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia
        * drivers are used to shared irqs and b) statuschange isn't really use-
        * ful anyway.

diff --git a/arch/mips/alchemy/devboards/pm.c b/arch/mips/alchemy/devboards/pm.c
index acaf91b5e4613dab28fb26983a1a026affa8c5f0..b86bff31d1d3ec3678944e69b7f76a3c67bbb6e6 100644 (file)
--- a/arch/mips/alchemy/devboards/pm.c
+++ b/arch/mips/alchemy/devboards/pm.c
@@ -194,7 +194,7 @@ static ssize_t db1x_pmattr_store(struct kobject *kobj,
 }
 
 #define ATTR(x)                                                        \
 }
 
 #define ATTR(x)                                                        \

-       static struct kobj_attribute x##_attribute =            \
+       static struct kobj_attribute x##_attribute =            \

                __ATTR(x, 0664, db1x_pmattr_show,               \
                                db1x_pmattr_store);
 
                __ATTR(x, 0664, db1x_pmattr_show,               \
                                db1x_pmattr_store);
 

diff --git a/arch/mips/ar7/Platform b/arch/mips/ar7/Platform
index 0bf85c416c6c6f28acea8c848729b1bbe0d57c43..21f9102d533cab05bf81616aee575a6fb217f3fb 100644 (file)
--- a/arch/mips/ar7/Platform
+++ b/arch/mips/ar7/Platform
@@ -1,6 +1,6 @@
 #
 # Texas Instruments AR7
 #
 #
 # Texas Instruments AR7
 #

-platform-$(CONFIG_AR7)          += ar7/
-cflags-$(CONFIG_AR7)            += -I$(srctree)/arch/mips/include/asm/mach-ar7
-load-$(CONFIG_AR7)              += 0xffffffff94100000
+platform-$(CONFIG_AR7)         += ar7/
+cflags-$(CONFIG_AR7)           += -I$(srctree)/arch/mips/include/asm/mach-ar7
+load-$(CONFIG_AR7)             += 0xffffffff94100000

diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index 7477fd2127ad52316e340da93c82522e2ab98fa7..7e2356fd5fd65eee45fe5838730a772bfcd2aeb8 100644 (file)
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -492,11 +492,11 @@ static struct gpio_led gt701_leds[] = {
                .active_low             = 1,
                .default_trigger        = "default-on",
        },
                .active_low             = 1,
                .default_trigger        = "default-on",
        },

-        {
-                .name                   = "ethernet",
-                .gpio                   = 10,
-                .active_low             = 1,
-        },
+       {
+               .name                   = "ethernet",
+               .gpio                   = 10,
+               .active_low             = 1,
+       },

 };
 
 static struct gpio_led_platform_data ar7_led_data;
 };
 
 static struct gpio_led_platform_data ar7_led_data;


@@ -512,7 +512,7 @@ static void __init detect_leds(void)
 {
        char *prid, *usb_prod;
 
 {
        char *prid, *usb_prod;
 

-       /* Default LEDs */
+       /* Default LEDs */

        ar7_led_data.num_leds = ARRAY_SIZE(default_leds);
        ar7_led_data.leds = default_leds;
 
        ar7_led_data.num_leds = ARRAY_SIZE(default_leds);
        ar7_led_data.leds = default_leds;
 

diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
index 579f452c0b456ec226828bd50ae856affd6f2aff..8c1b8bf9b32f8cc88c2ad9939f9a2333df34a264 100644 (file)
--- a/arch/mips/ath79/clock.c
+++ b/arch/mips/ath79/clock.c
@@ -198,7 +198,7 @@ static void __init ar934x_clocks_init(void)
        dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);
 
        bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
        dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);
 
        bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);

-       if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
+       if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)

                ath79_ref_clk.rate = 40 * 1000 * 1000;
        else
                ath79_ref_clk.rate = 25 * 1000 * 1000;
                ath79_ref_clk.rate = 40 * 1000 * 1000;
        else
                ath79_ref_clk.rate = 25 * 1000 * 1000;

diff --git a/arch/mips/ath79/mach-ap121.c b/arch/mips/ath79/mach-ap121.c
index 4c20200d7c72e07b92ed4a8f30bbbcc13cd5a1fa..1bf73f2a069d73d41030bae19249d16d9227d484 100644 (file)
--- a/arch/mips/ath79/mach-ap121.c
+++ b/arch/mips/ath79/mach-ap121.c
@@ -69,7 +69,7 @@ static struct spi_board_info ap121_spi_info[] = {
 
 static struct ath79_spi_platform_data ap121_spi_data = {
        .bus_num        = 0,
 
 static struct ath79_spi_platform_data ap121_spi_data = {
        .bus_num        = 0,

-       .num_chipselect = 1,
+       .num_chipselect = 1,

 };
 
 static void __init ap121_setup(void)
 };
 
 static void __init ap121_setup(void)

diff --git a/arch/mips/ath79/mach-ap81.c b/arch/mips/ath79/mach-ap81.c
index abe19836331c531448c17aba798181a952a66f8a..1c78d497f93064b1f4dd728ed5e0c2633e5cf01d 100644 (file)
--- a/arch/mips/ath79/mach-ap81.c
+++ b/arch/mips/ath79/mach-ap81.c
@@ -78,7 +78,7 @@ static struct spi_board_info ap81_spi_info[] = {
 
 static struct ath79_spi_platform_data ap81_spi_data = {
        .bus_num        = 0,
 
 static struct ath79_spi_platform_data ap81_spi_data = {
        .bus_num        = 0,

-       .num_chipselect = 1,
+       .num_chipselect = 1,

 };
 
 static void __init ap81_setup(void)
 };
 
 static void __init ap81_setup(void)

diff --git a/arch/mips/ath79/mach-db120.c b/arch/mips/ath79/mach-db120.c
index 42f540a724f43437e3f2c1a292cb2084a85cad51..4d661a1d2dae90d5308d63699be7287037657aa9 100644 (file)
--- a/arch/mips/ath79/mach-db120.c
+++ b/arch/mips/ath79/mach-db120.c
@@ -87,7 +87,7 @@ static struct spi_board_info db120_spi_info[] = {
 
 static struct ath79_spi_platform_data db120_spi_data = {
        .bus_num        = 0,
 
 static struct ath79_spi_platform_data db120_spi_data = {
        .bus_num        = 0,

-       .num_chipselect = 1,
+       .num_chipselect = 1,

 };
 
 #ifdef CONFIG_PCI
 };
 
 #ifdef CONFIG_PCI

diff --git a/arch/mips/ath79/mach-pb44.c b/arch/mips/ath79/mach-pb44.c
index c5f0ea5e00c38dc0e76312b401cf21793a91dcc5..67b980d94fb7aa6d3485b83616397e05f4cc6413 100644 (file)
--- a/arch/mips/ath79/mach-pb44.c
+++ b/arch/mips/ath79/mach-pb44.c
@@ -34,8 +34,8 @@
 #define PB44_KEYS_DEBOUNCE_INTERVAL    (3 * PB44_KEYS_POLL_INTERVAL)
 
 static struct i2c_gpio_platform_data pb44_i2c_gpio_data = {
 #define PB44_KEYS_DEBOUNCE_INTERVAL    (3 * PB44_KEYS_POLL_INTERVAL)
 
 static struct i2c_gpio_platform_data pb44_i2c_gpio_data = {

-       .sda_pin        = PB44_GPIO_I2C_SDA,
-       .scl_pin        = PB44_GPIO_I2C_SCL,
+       .sda_pin        = PB44_GPIO_I2C_SDA,
+       .scl_pin        = PB44_GPIO_I2C_SCL,

 };
 
 static struct platform_device pb44_i2c_gpio_device = {
 };
 
 static struct platform_device pb44_i2c_gpio_device = {


@@ -53,7 +53,7 @@ static struct pcf857x_platform_data pb44_pcf857x_data = {
 static struct i2c_board_info pb44_i2c_board_info[] __initdata = {
        {
                I2C_BOARD_INFO("pcf8575", 0x20),
 static struct i2c_board_info pb44_i2c_board_info[] __initdata = {
        {
                I2C_BOARD_INFO("pcf8575", 0x20),

-               .platform_data  = &pb44_pcf857x_data,
+               .platform_data  = &pb44_pcf857x_data,

        },
 };
 
        },
 };
 

diff --git a/arch/mips/bcm47xx/Makefile b/arch/mips/bcm47xx/Makefile
index 1a3567f07e734e9a81384e61e8d94c0f34c2a1fc..f3bf6d5bfb9d9430023d001e98c7468fa342b1eb 100644 (file)
--- a/arch/mips/bcm47xx/Makefile
+++ b/arch/mips/bcm47xx/Makefile
@@ -3,5 +3,5 @@
 # under Linux.
 #
 
 # under Linux.
 #
 

-obj-y                          += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o
+obj-y                          += irq.o nvram.o prom.o serial.o setup.o time.o sprom.o

 obj-$(CONFIG_BCM47XX_SSB)      += wgt634u.o
 obj-$(CONFIG_BCM47XX_SSB)      += wgt634u.o

diff --git a/arch/mips/bcm47xx/nvram.c b/arch/mips/bcm47xx/nvram.c
index 48a4c70b3842276486d88179b1919917106e773e..c37419c11c921a7fde30eaa42dace4fa47b820ec 100644 (file)
--- a/arch/mips/bcm47xx/nvram.c
+++ b/arch/mips/bcm47xx/nvram.c
@@ -5,8 +5,8 @@
  * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
  * Copyright (C) 2010-2011 Hauke Mehrtens <hauke@hauke-m.de>
  *
  * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
  * Copyright (C) 2010-2011 Hauke Mehrtens <hauke@hauke-m.de>
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/bcm47xx/sprom.c b/arch/mips/bcm47xx/sprom.c
index 289cc0a386380e9cfa6c49eb86b1b89c0f917352..b2a7c251e471fdf3137633e81c3519513d925ee7 100644 (file)
--- a/arch/mips/bcm47xx/sprom.c
+++ b/arch/mips/bcm47xx/sprom.c
@@ -60,8 +60,8 @@ static int get_nvram_var(const char *prefix, const char *postfix,
 
 #define NVRAM_READ_VAL(type)                                           \
 static void nvram_read_ ## type (const char *prefix,                   \
 
 #define NVRAM_READ_VAL(type)                                           \
 static void nvram_read_ ## type (const char *prefix,                   \

-                                const char *postfix, const char *name, \
-                                type *val, type allset, bool fallback) \
+                                const char *postfix, const char *name, \
+                                type *val, type allset, bool fallback) \

 {                                                                      \
        char buf[100];                                                  \
        int err;                                                        \
 {                                                                      \
        char buf[100];                                                  \
        int err;                                                        \

diff --git a/arch/mips/bcm47xx/wgt634u.c b/arch/mips/bcm47xx/wgt634u.c
index 9d111e8087ecff0c7740b9179db2ecdeacd4047c..c63a4c287b5c21f632952a7d3b1925d77b888d40 100644 (file)
--- a/arch/mips/bcm47xx/wgt634u.c
+++ b/arch/mips/bcm47xx/wgt634u.c
@@ -36,13 +36,13 @@ static struct gpio_led wgt634u_leds[] = {
 };
 
 static struct gpio_led_platform_data wgt634u_led_data = {
 };
 
 static struct gpio_led_platform_data wgt634u_led_data = {

-       .num_leds =     ARRAY_SIZE(wgt634u_leds),
-       .leds =         wgt634u_leds,
+       .num_leds =     ARRAY_SIZE(wgt634u_leds),
+       .leds =         wgt634u_leds,

 };
 
 static struct platform_device wgt634u_gpio_leds = {
 };
 
 static struct platform_device wgt634u_gpio_leds = {

-       .name =         "leds-gpio",
-       .id =           -1,
+       .name =         "leds-gpio",
+       .id =           -1,

        .dev = {
                .platform_data = &wgt634u_led_data,
        }
        .dev = {
                .platform_data = &wgt634u_led_data,
        }


@@ -53,35 +53,35 @@ static struct platform_device wgt634u_gpio_leds = {
    firmware. */
 static struct mtd_partition wgt634u_partitions[] = {
        {
    firmware. */
 static struct mtd_partition wgt634u_partitions[] = {
        {

-               .name       = "cfe",
-               .offset     = 0,
-               .size       = 0x60000,          /* 384k */
-               .mask_flags = MTD_WRITEABLE     /* force read-only */
+               .name       = "cfe",
+               .offset     = 0,
+               .size       = 0x60000,          /* 384k */
+               .mask_flags = MTD_WRITEABLE     /* force read-only */

        },
        {
        },
        {

-               .name   = "config",
+               .name   = "config",

                .offset = 0x60000,
                .offset = 0x60000,

-               .size   = 0x20000               /* 128k */
+               .size   = 0x20000               /* 128k */

        },
        {
        },
        {

-               .name   = "linux",
+               .name   = "linux",

                .offset = 0x80000,
                .offset = 0x80000,

-               .size   = 0x140000              /* 1280k */
+               .size   = 0x140000              /* 1280k */

        },
        {
        },
        {

-               .name   = "jffs",
+               .name   = "jffs",

                .offset = 0x1c0000,
                .offset = 0x1c0000,

-               .size   = 0x620000              /* 6272k */
+               .size   = 0x620000              /* 6272k */

        },
        {
        },
        {

-               .name   = "nvram",
+               .name   = "nvram",

                .offset = 0x7e0000,
                .offset = 0x7e0000,

-               .size   = 0x20000               /* 128k */
+               .size   = 0x20000               /* 128k */

        },
 };
 
 static struct physmap_flash_data wgt634u_flash_data = {
        },
 };
 
 static struct physmap_flash_data wgt634u_flash_data = {

-       .parts    = wgt634u_partitions,
+       .parts    = wgt634u_partitions,

        .nr_parts = ARRAY_SIZE(wgt634u_partitions)
 };
 
        .nr_parts = ARRAY_SIZE(wgt634u_partitions)
 };
 


@@ -90,9 +90,9 @@ static struct resource wgt634u_flash_resource = {
 };
 
 static struct platform_device wgt634u_flash = {
 };
 
 static struct platform_device wgt634u_flash = {

-       .name          = "physmap-flash",
-       .id            = 0,
-       .dev           = { .platform_data = &wgt634u_flash_data, },
+       .name          = "physmap-flash",
+       .id            = 0,
+       .dev           = { .platform_data = &wgt634u_flash_data, },

        .resource      = &wgt634u_flash_resource,
        .num_resources = 1,
 };
        .resource      = &wgt634u_flash_resource,
        .num_resources = 1,
 };

diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c
index 73be9b3496901510d7afdfc01e71e13c70ac52cb..ed1949c295087bf81ef951539c08400507e9d603 100644 (file)
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
@@ -406,9 +406,9 @@ static struct board_info __initdata board_FAST2404 = {
        .expected_cpu_id                = 0x6348,
 
        .has_uart0                      = 1,
        .expected_cpu_id                = 0x6348,
 
        .has_uart0                      = 1,

-        .has_enet0                     = 1,
-        .has_enet1                     = 1,
-        .has_pci                       = 1,
+       .has_enet0                      = 1,
+       .has_enet1                      = 1,
+       .has_pci                        = 1,

 
        .enet0 = {
                .has_phy                = 1,
 
        .enet0 = {
                .has_phy                = 1,


@@ -591,22 +591,22 @@ static struct board_info __initdata board_96358vw2 = {
 };
 
 static struct board_info __initdata board_AGPFS0 = {
 };
 
 static struct board_info __initdata board_AGPFS0 = {

-       .name                           = "AGPF-S0",
-       .expected_cpu_id                = 0x6358,
+       .name                           = "AGPF-S0",
+       .expected_cpu_id                = 0x6358,

 
        .has_uart0                      = 1,
 
        .has_uart0                      = 1,

-       .has_enet0                      = 1,
-       .has_enet1                      = 1,
-       .has_pci                        = 1,
+       .has_enet0                      = 1,
+       .has_enet1                      = 1,
+       .has_pci                        = 1,

 
        .enet0 = {
 
        .enet0 = {

-               .has_phy                = 1,
-               .use_internal_phy       = 1,
+               .has_phy                = 1,
+               .use_internal_phy       = 1,

        },
 
        .enet1 = {
        },
 
        .enet1 = {

-               .force_speed_100        = 1,
-               .force_duplex_full      = 1,
+               .force_speed_100        = 1,
+               .force_duplex_full      = 1,

        },
 
        .has_ohci0 = 1,
        },
 
        .has_ohci0 = 1,


@@ -677,7 +677,7 @@ static struct ssb_sprom bcm63xx_sprom = {
        .revision               = 0x02,
        .board_rev              = 0x17,
        .country_code           = 0x0,
        .revision               = 0x02,
        .board_rev              = 0x17,
        .country_code           = 0x0,

-       .ant_available_bg       = 0x3,
+       .ant_available_bg       = 0x3,

        .pa0b0                  = 0x15ae,
        .pa0b1                  = 0xfa85,
        .pa0b2                  = 0xfe8d,
        .pa0b0                  = 0x15ae,
        .pa0b1                  = 0xfa85,
        .pa0b2                  = 0xfe8d,

diff --git a/arch/mips/boot/Makefile b/arch/mips/boot/Makefile
index 85bcb5adc7cb16531a4ea93d41a101a83ee786ba..851261e9fdc0a948bb1bfbb9e1f930a0ff8beec1 100644 (file)
--- a/arch/mips/boot/Makefile
+++ b/arch/mips/boot/Makefile
@@ -24,7 +24,7 @@ strip-flags   := $(addprefix --remove-section=,$(drop-sections))
 hostprogs-y := elf2ecoff
 
 targets := vmlinux.ecoff
 hostprogs-y := elf2ecoff
 
 targets := vmlinux.ecoff

-quiet_cmd_ecoff = ECOFF   $@
+quiet_cmd_ecoff = ECOFF          $@

       cmd_ecoff = $(obj)/elf2ecoff $(VMLINUX) $@ $(e2eflag)
 $(obj)/vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX) FORCE
        $(call if_changed,ecoff)
       cmd_ecoff = $(obj)/elf2ecoff $(VMLINUX) $@ $(e2eflag)
 $(obj)/vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX) FORCE
        $(call if_changed,ecoff)

diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile
index c2a3fb0ffc873b971c8461257d5e422b91c832e6..bbaa1d4beb6df4661b11c661ec7f066c5dc36652 100644 (file)
--- a/arch/mips/boot/compressed/Makefile
+++ b/arch/mips/boot/compressed/Makefile
@@ -51,7 +51,7 @@ $(obj)/vmlinux.bin.z: $(obj)/vmlinux.bin FORCE
 
 targets += piggy.o
 OBJCOPYFLAGS_piggy.o := --add-section=.image=$(obj)/vmlinux.bin.z \
 
 targets += piggy.o
 OBJCOPYFLAGS_piggy.o := --add-section=.image=$(obj)/vmlinux.bin.z \

-                        --set-section-flags=.image=contents,alloc,load,readonly,data
+                       --set-section-flags=.image=contents,alloc,load,readonly,data

 $(obj)/piggy.o: $(obj)/dummy.o $(obj)/vmlinux.bin.z FORCE
        $(call if_changed,objcopy)
 
 $(obj)/piggy.o: $(obj)/dummy.o $(obj)/vmlinux.bin.z FORCE
        $(call if_changed,objcopy)
 


@@ -67,9 +67,9 @@ endif
 
 vmlinuzobjs-y += $(obj)/piggy.o
 
 
 vmlinuzobjs-y += $(obj)/piggy.o
 

-quiet_cmd_zld = LD      $@
+quiet_cmd_zld = LD     $@

       cmd_zld = $(LD) $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T $< $(vmlinuzobjs-y) -o $@
       cmd_zld = $(LD) $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T $< $(vmlinuzobjs-y) -o $@

-quiet_cmd_strip = STRIP   $@
+quiet_cmd_strip = STRIP          $@

       cmd_strip = $(STRIP) -s $@
 vmlinuz: $(src)/ld.script $(vmlinuzobjs-y) $(obj)/calc_vmlinuz_load_addr
        $(call cmd,zld)
       cmd_strip = $(STRIP) -s $@
 vmlinuz: $(src)/ld.script $(vmlinuzobjs-y) $(obj)/calc_vmlinuz_load_addr
        $(call cmd,zld)


@@ -96,7 +96,7 @@ quiet_cmd_32 = OBJCOPY $@
 vmlinuz.32: vmlinuz
        $(call cmd,32)
 
 vmlinuz.32: vmlinuz
        $(call cmd,32)
 

-quiet_cmd_ecoff = ECOFF   $@
+quiet_cmd_ecoff = ECOFF          $@

       cmd_ecoff = $< $(VMLINUZ) $@ $(e2eflag)
 vmlinuz.ecoff: $(obj)/../elf2ecoff $(VMLINUZ)
        $(call cmd,ecoff)
       cmd_ecoff = $< $(VMLINUZ) $@ $(e2eflag)
 vmlinuz.ecoff: $(obj)/../elf2ecoff $(VMLINUZ)
        $(call cmd,ecoff)

diff --git a/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c b/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c
index 9a6243676e2203b4c3f9addcc3c236fb27ba6060..37fe58c19a90f96feede3390b5f4374aeebbf7ac 100644 (file)
--- a/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c
+++ b/arch/mips/boot/compressed/calc_vmlinuz_load_addr.c
@@ -1,8 +1,8 @@
 /*
  * Copyright (C) 2010 "Wu Zhangjin" <wuzhangjin@gmail.com>
  *
 /*
  * Copyright (C) 2010 "Wu Zhangjin" <wuzhangjin@gmail.com>
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c
index 5cad0faefa17cdcd7425eb07e93e48554cc99f2f..2c9573098c0dab7889895de68c2dae5bb9ad9ba8 100644 (file)
--- a/arch/mips/boot/compressed/decompress.c
+++ b/arch/mips/boot/compressed/decompress.c
@@ -5,8 +5,8 @@
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  *
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
index 4e65a8420bee74481eeafa865459fc2c091d1b6e..409cb483a9ffc5bf1045a0a928b44c9a78904f28 100644 (file)
--- a/arch/mips/boot/compressed/head.S
+++ b/arch/mips/boot/compressed/head.S
@@ -32,8 +32,8 @@ start:
        bne     a2, a0, 1b
         addiu  a0, a0, 4
 
        bne     a2, a0, 1b
         addiu  a0, a0, 4
 

-       PTR_LA  a0, (.heap)          /* heap address */
-       PTR_LA  sp, (.stack + 8192)  /* stack address */
+       PTR_LA  a0, (.heap)          /* heap address */
+       PTR_LA  sp, (.stack + 8192)  /* stack address */

 
        PTR_LA  ra, 2f
        PTR_LA  k0, decompress_kernel
 
        PTR_LA  ra, 2f
        PTR_LA  k0, decompress_kernel

diff --git a/arch/mips/boot/ecoff.h b/arch/mips/boot/ecoff.h
index 8c3eed2877f26ec6c20083c11fbf88c78ae12ece..83e5c3813d676f168887ceb6af739700fea28734 100644 (file)
--- a/arch/mips/boot/ecoff.h
+++ b/arch/mips/boot/ecoff.h
@@ -2,48 +2,48 @@
  * Some ECOFF definitions.
  */
 typedef struct filehdr {
  * Some ECOFF definitions.
  */
 typedef struct filehdr {

-        unsigned short  f_magic;        /* magic number */
-        unsigned short  f_nscns;        /* number of sections */
-        long            f_timdat;       /* time & date stamp */
-        long            f_symptr;       /* file pointer to symbolic header */
-        long            f_nsyms;        /* sizeof(symbolic hdr) */
-        unsigned short  f_opthdr;       /* sizeof(optional hdr) */
-        unsigned short  f_flags;        /* flags */
+       unsigned short  f_magic;        /* magic number */
+       unsigned short  f_nscns;        /* number of sections */
+       long            f_timdat;       /* time & date stamp */
+       long            f_symptr;       /* file pointer to symbolic header */
+       long            f_nsyms;        /* sizeof(symbolic hdr) */
+       unsigned short  f_opthdr;       /* sizeof(optional hdr) */
+       unsigned short  f_flags;        /* flags */

 } FILHDR;
 } FILHDR;

-#define FILHSZ  sizeof(FILHDR)
+#define FILHSZ sizeof(FILHDR)

 
 #define OMAGIC         0407
 #define MIPSEBMAGIC    0x160
 #define MIPSELMAGIC    0x162
 
 typedef struct scnhdr {
 
 #define OMAGIC         0407
 #define MIPSEBMAGIC    0x160
 #define MIPSELMAGIC    0x162
 
 typedef struct scnhdr {

-        char            s_name[8];      /* section name */
-        long            s_paddr;        /* physical address, aliased s_nlib */
-        long            s_vaddr;        /* virtual address */
-        long            s_size;         /* section size */
-        long            s_scnptr;       /* file ptr to raw data for section */
-        long            s_relptr;       /* file ptr to relocation */
-        long            s_lnnoptr;      /* file ptr to gp histogram */
-        unsigned short  s_nreloc;       /* number of relocation entries */
-        unsigned short  s_nlnno;        /* number of gp histogram entries */
-        long            s_flags;        /* flags */
+       char            s_name[8];      /* section name */
+       long            s_paddr;        /* physical address, aliased s_nlib */
+       long            s_vaddr;        /* virtual address */
+       long            s_size;         /* section size */
+       long            s_scnptr;       /* file ptr to raw data for section */
+       long            s_relptr;       /* file ptr to relocation */
+       long            s_lnnoptr;      /* file ptr to gp histogram */
+       unsigned short  s_nreloc;       /* number of relocation entries */
+       unsigned short  s_nlnno;        /* number of gp histogram entries */
+       long            s_flags;        /* flags */

 } SCNHDR;
 #define SCNHSZ         sizeof(SCNHDR)
 #define SCNROUND       ((long)16)
 
 typedef struct aouthdr {
 } SCNHDR;
 #define SCNHSZ         sizeof(SCNHDR)
 #define SCNROUND       ((long)16)
 
 typedef struct aouthdr {

-        short   magic;          /* see above                            */
-        short   vstamp;         /* version stamp                        */
-        long    tsize;          /* text size in bytes, padded to DW bdry*/
-        long    dsize;          /* initialized data "  "                */
-        long    bsize;          /* uninitialized data "   "             */
-        long    entry;          /* entry pt.                            */
-        long    text_start;     /* base of text used for this file      */
-        long    data_start;     /* base of data used for this file      */
-        long    bss_start;      /* base of bss used for this file       */
-        long    gprmask;        /* general purpose register mask        */
-        long    cprmask[4];     /* co-processor register masks          */
-        long    gp_value;       /* the gp value used for this object    */
+       short   magic;          /* see above                            */
+       short   vstamp;         /* version stamp                        */
+       long    tsize;          /* text size in bytes, padded to DW bdry*/
+       long    dsize;          /* initialized data "  "                */
+       long    bsize;          /* uninitialized data "   "             */
+       long    entry;          /* entry pt.                            */
+       long    text_start;     /* base of text used for this file      */
+       long    data_start;     /* base of data used for this file      */
+       long    bss_start;      /* base of bss used for this file       */
+       long    gprmask;        /* general purpose register mask        */
+       long    cprmask[4];     /* co-processor register masks          */
+       long    gp_value;       /* the gp value used for this object    */

 } AOUTHDR;
 #define AOUTHSZ sizeof(AOUTHDR)
 
 } AOUTHDR;
 #define AOUTHSZ sizeof(AOUTHDR)
 


@@ -51,7 +51,7 @@ typedef struct aouthdr {
 #define NMAGIC         0410
 #define ZMAGIC         0413
 #define SMAGIC         0411
 #define NMAGIC         0410
 #define ZMAGIC         0413
 #define SMAGIC         0411

-#define LIBMAGIC        0443
+#define LIBMAGIC       0443

 
 #define N_TXTOFF(f, a) \
  ((a).magic == ZMAGIC || (a).magic == LIBMAGIC ? 0 : \
 
 #define N_TXTOFF(f, a) \
  ((a).magic == ZMAGIC || (a).magic == LIBMAGIC ? 0 : \

diff --git a/arch/mips/boot/elf2ecoff.c b/arch/mips/boot/elf2ecoff.c
index e19d906236af818be4df3bfe28bf76f0b9948710..8585078ae50e90d0cf3bc87217b68cf55512dd23 100644 (file)
--- a/arch/mips/boot/elf2ecoff.c
+++ b/arch/mips/boot/elf2ecoff.c
@@ -29,7 +29,7 @@
 /* elf2ecoff.c
 
    This program converts an elf executable to an ECOFF executable.
 /* elf2ecoff.c
 
    This program converts an elf executable to an ECOFF executable.

-   No symbol table is retained.   This is useful primarily in building
+   No symbol table is retained.          This is useful primarily in building

    net-bootable kernels for machines (e.g., DECstation and Alpha) which
    only support the ECOFF object file format. */
 
    net-bootable kernels for machines (e.g., DECstation and Alpha) which
    only support the ECOFF object file format. */
 


@@ -341,7 +341,7 @@ int main(int argc, char *argv[])
 
        /* Figure out if we can cram the program header into an ECOFF
           header...  Basically, we can't handle anything but loadable
 
        /* Figure out if we can cram the program header into an ECOFF
           header...  Basically, we can't handle anything but loadable

-          segments, but we can ignore some kinds of segments.  We can't
+          segments, but we can ignore some kinds of segments.  We can't

           handle holes in the address space.  Segments may be out of order,
           so we sort them first. */
 
           handle holes in the address space.  Segments may be out of order,
           so we sort them first. */
 


@@ -514,7 +514,7 @@ int main(int argc, char *argv[])
 
                for (i = 0; i < nosecs; i++) {
                        printf
 
                for (i = 0; i < nosecs; i++) {
                        printf

-                           ("Section %d: %s phys %lx  size %lx  file offset %lx\n",
+                           ("Section %d: %s phys %lx  size %lx  file offset %lx\n",

                             i, esecs[i].s_name, esecs[i].s_paddr,
                             esecs[i].s_size, esecs[i].s_scnptr);
                }
                             i, esecs[i].s_name, esecs[i].s_paddr,
                             esecs[i].s_size, esecs[i].s_scnptr);
                }


@@ -551,7 +551,7 @@ int main(int argc, char *argv[])
        }
 
        /*
        }
 
        /*

-        * Copy the loadable sections.   Zero-fill any gaps less than 64k;
+        * Copy the loadable sections.   Zero-fill any gaps less than 64k;

         * complain about any zero-filling, and die if we're asked to zero-fill
         * more than 64k.
         */
         * complain about any zero-filling, and die if we're asked to zero-fill
         * more than 64k.
         */

diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
index 6e927cf20df243a8e42f353baa54d5d9d74ef74e..3751c3918571477188993540df38a219ef0e9199 100644 (file)
--- a/arch/mips/cavium-octeon/Makefile
+++ b/arch/mips/cavium-octeon/Makefile
@@ -17,7 +17,7 @@ obj-y += dma-octeon.o flash_setup.o
 obj-y += octeon-memcpy.o
 obj-y += executive/
 
 obj-y += octeon-memcpy.o
 obj-y += executive/
 

-obj-$(CONFIG_SMP)                     += smp.o
+obj-$(CONFIG_SMP)                    += smp.o

 
 DTS_FILES = octeon_3xxx.dts octeon_68xx.dts
 DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES))
 
 DTS_FILES = octeon_3xxx.dts octeon_68xx.dts
 DTB_FILES = $(patsubst %.dts, %.dtb, $(DTS_FILES))

diff --git a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
index 6d5ddbc112cc355a8dbfbbddd3e2136e81a06957..504ed61a47cd9e4f2a4c6d57b6091c47f3128787 100644 (file)
--- a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
@@ -155,8 +155,8 @@ int cvmx_bootmem_init(void *mem_desc_ptr)
         *
         * Linux 64 bit: Set XKPHYS bit
         * Linux 32 bit: use mmap to create mapping, use virtual address
         *
         * Linux 64 bit: Set XKPHYS bit
         * Linux 32 bit: use mmap to create mapping, use virtual address

-        * CVMX 64 bit:  use physical address directly
-        * CVMX 32 bit:  use physical address directly
+        * CVMX 64 bit:  use physical address directly
+        * CVMX 32 bit:  use physical address directly

         *
         * Note that the CVMX environment assumes the use of 1-1 TLB
         * mappings so that the physical addresses can be used
         *
         * Note that the CVMX environment assumes the use of 1-1 TLB
         * mappings so that the physical addresses can be used


@@ -398,7 +398,7 @@ error_out:
 int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags)
 {
        uint64_t cur_addr;
 int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags)
 {
        uint64_t cur_addr;

-       uint64_t prev_addr = 0; /* zero is invalid */
+       uint64_t prev_addr = 0; /* zero is invalid */

        int retval = 0;
 
 #ifdef DEBUG
        int retval = 0;
 
 #ifdef DEBUG


@@ -424,7 +424,7 @@ int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags)
        if (cur_addr == 0 || phy_addr < cur_addr) {
                /* add at front of list - special case with changing head ptr */
                if (cur_addr && phy_addr + size > cur_addr)
        if (cur_addr == 0 || phy_addr < cur_addr) {
                /* add at front of list - special case with changing head ptr */
                if (cur_addr && phy_addr + size > cur_addr)

-                       goto bootmem_free_done; /* error, overlapping section */
+                       goto bootmem_free_done; /* error, overlapping section */

                else if (phy_addr + size == cur_addr) {
                        /* Add to front of existing first block */
                        cvmx_bootmem_phy_set_next(phy_addr,
                else if (phy_addr + size == cur_addr) {
                        /* Add to front of existing first block */
                        cvmx_bootmem_phy_set_next(phy_addr,


@@ -611,7 +611,7 @@ int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags)
        }
 
        cvmx_bootmem_unlock();
        }
 
        cvmx_bootmem_unlock();

-       return named_block_ptr != NULL; /* 0 on failure, 1 on success */
+       return named_block_ptr != NULL; /* 0 on failure, 1 on success */

 }
 
 int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr,
 }
 
 int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr,

diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
index fd2015331a207315c760ca195751b234c32ee1d3..7c6497781895a040af22a8911c01afd81272b619 100644 (file)
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-board.c
@@ -203,10 +203,10 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
  * enumeration from the bootloader.
  *
  * @ipd_port: IPD input port associated with the port we want to get link
  * enumeration from the bootloader.
  *
  * @ipd_port: IPD input port associated with the port we want to get link

- *                 status for.
+ *                status for.

  *
  * Returns The ports link status. If the link isn't fully resolved, this must
  *
  * Returns The ports link status. If the link isn't fully resolved, this must

- *         return zero.
+ *        return zero.

  */
 cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
 {
  */
 cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
 {


@@ -357,16 +357,16 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
                                result.s.link_up = 1;
                                result.s.full_duplex = ((phy_status >> 13) & 1);
                                switch ((phy_status >> 14) & 3) {
                                result.s.link_up = 1;
                                result.s.full_duplex = ((phy_status >> 13) & 1);
                                switch ((phy_status >> 14) & 3) {

-                               case 0: /* 10 Mbps */
+                               case 0: /* 10 Mbps */

                                        result.s.speed = 10;
                                        break;
                                        result.s.speed = 10;
                                        break;

-                               case 1: /* 100 Mbps */
+                               case 1: /* 100 Mbps */

                                        result.s.speed = 100;
                                        break;
                                        result.s.speed = 100;
                                        break;

-                               case 2: /* 1 Gbps */
+                               case 2: /* 1 Gbps */

                                        result.s.speed = 1000;
                                        break;
                                        result.s.speed = 1000;
                                        break;

-                               case 3: /* Illegal */
+                               case 3: /* Illegal */

                                        result.u64 = 0;
                                        break;
                                }
                                        result.u64 = 0;
                                        break;
                                }


@@ -391,16 +391,16 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
                result.s.link_up = inband_status.s.status;
                result.s.full_duplex = inband_status.s.duplex;
                switch (inband_status.s.speed) {
                result.s.link_up = inband_status.s.status;
                result.s.full_duplex = inband_status.s.duplex;
                switch (inband_status.s.speed) {

-               case 0: /* 10 Mbps */
+               case 0: /* 10 Mbps */

                        result.s.speed = 10;
                        break;
                        result.s.speed = 10;
                        break;

-               case 1: /* 100 Mbps */
+               case 1: /* 100 Mbps */

                        result.s.speed = 100;
                        break;
                        result.s.speed = 100;
                        break;

-               case 2: /* 1 Gbps */
+               case 2: /* 1 Gbps */

                        result.s.speed = 1000;
                        break;
                        result.s.speed = 1000;
                        break;

-               case 3: /* Illegal */
+               case 3: /* Illegal */

                        result.u64 = 0;
                        break;
                }
                        result.u64 = 0;
                        break;
                }


@@ -429,9 +429,9 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
  *
  * @phy_addr:  The address of the PHY to program
  * @enable_autoneg:
  *
  * @phy_addr:  The address of the PHY to program
  * @enable_autoneg:

- *                  Non zero if you want to enable auto-negotiation.
+ *                 Non zero if you want to enable auto-negotiation.

  * @link_info: Link speed to program. If the speed is zero and auto-negotiation
  * @link_info: Link speed to program. If the speed is zero and auto-negotiation

- *                  is enabled, all possible negotiation speeds are advertised.
+ *                 is enabled, all possible negotiation speeds are advertised.

  *
  * Returns Zero on success, negative on failure
  */
  *
  * Returns Zero on success, negative on failure
  */


@@ -607,10 +607,10 @@ int cvmx_helper_board_link_set_phy(int phy_addr,
  *
  * @interface: Interface to probe
  * @supported_ports:
  *
  * @interface: Interface to probe
  * @supported_ports:

- *                  Number of ports Octeon supports.
+ *                 Number of ports Octeon supports.

  *
  * Returns Number of ports the actual board supports. Many times this will
  *
  * Returns Number of ports the actual board supports. Many times this will

- *         simple be "support_ports".
+ *        simple be "support_ports".

  */
 int __cvmx_helper_board_interface_probe(int interface, int supported_ports)
 {
  */
 int __cvmx_helper_board_interface_probe(int interface, int supported_ports)
 {

diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c b/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c
index c1c54890bae0230f998441c8b2b473cfb766a9c7..607b4e65957977adcd03a467f07bbfa312c5be9d 100644 (file)
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-jtag.c
@@ -79,10 +79,10 @@ void cvmx_helper_qlm_jtag_init(void)
  * @qlm:    QLM to shift value into
  * @bits:   Number of bits to shift in (1-32).
  * @data:   Data to shift in. Bit 0 enters the chain first, followed by
  * @qlm:    QLM to shift value into
  * @bits:   Number of bits to shift in (1-32).
  * @data:   Data to shift in. Bit 0 enters the chain first, followed by

- *               bit 1, etc.
+ *              bit 1, etc.

  *
  * Returns The low order bits of the JTAG chain that shifted out of the
  *
  * Returns The low order bits of the JTAG chain that shifted out of the

- *         circle.
+ *        circle.

  */
 uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
 {
  */
 uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
 {

diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
index 82b21843421caefd270aa44e68c53df988472898..f59c88ee9b31cb667b45fdaac54f931244c9d2cb 100644 (file)
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-rgmii.c
@@ -131,7 +131,7 @@ void cvmx_helper_rgmii_internal_loopback(int port)
  * @interface: Interface to setup
  * @port:      Port to setup (0..3)
  * @cpu_clock_hz:
  * @interface: Interface to setup
  * @port:      Port to setup (0..3)
  * @cpu_clock_hz:

- *                  Chip frequency in Hertz
+ *                 Chip frequency in Hertz

  *
  * Returns Zero on success, negative on failure
  */
  *
  * Returns Zero on success, negative on failure
  */


@@ -409,14 +409,14 @@ int __cvmx_helper_rgmii_link_set(int ipd_port,
                        mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
 
        /*
                        mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
 
        /*

-        * Port  .en  .type  .p0mii  Configuration
-        * ----  ---  -----  ------  -----------------------------------------
-        *  X      0     X      X    All links are disabled.
-        *  0      1     X      0    Port 0 is RGMII
-        *  0      1     X      1    Port 0 is MII
-        *  1      1     0      X    Ports 1 and 2 are configured as RGMII ports.
-        *  1      1     1      X    Port 1: GMII/MII; Port 2: disabled. GMII or
-        *                           MII port is selected by GMX_PRT1_CFG[SPEED].
+        * Port  .en  .type  .p0mii  Configuration
+        * ----  ---  -----  ------  -----------------------------------------
+        *  X      0     X      X    All links are disabled.
+        *  0      1     X      0    Port 0 is RGMII
+        *  0      1     X      1    Port 0 is MII
+        *  1      1     0      X    Ports 1 and 2 are configured as RGMII ports.
+        *  1      1     1      X    Port 1: GMII/MII; Port 2: disabled. GMII or
+        *                           MII port is selected by GMX_PRT1_CFG[SPEED].

         */
 
                        /* In MII mode, CLK_CNT = 1. */
         */
 
                        /* In MII mode, CLK_CNT = 1. */


@@ -464,9 +464,9 @@ int __cvmx_helper_rgmii_link_set(int ipd_port,
  *
  * @ipd_port: IPD/PKO port to loopback.
  * @enable_internal:
  *
  * @ipd_port: IPD/PKO port to loopback.
  * @enable_internal:

- *                 Non zero if you want internal loopback
+ *                Non zero if you want internal loopback

  * @enable_external:
  * @enable_external:

- *                 Non zero if you want external loopback
+ *                Non zero if you want external loopback

  *
  * Returns Zero on success, negative on failure.
  */
  *
  * Returns Zero on success, negative on failure.
  */

diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
index 0c0bf5d30e70375203a31efef560ff8302705979..45f18cce31a9a606c9842ed1da334c0ae3880ffc 100644 (file)
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-sgmii.c
@@ -523,9 +523,9 @@ int __cvmx_helper_sgmii_link_set(int ipd_port,
  *
  * @ipd_port: IPD/PKO port to loopback.
  * @enable_internal:
  *
  * @ipd_port: IPD/PKO port to loopback.
  * @enable_internal:

- *                 Non zero if you want internal loopback
+ *                Non zero if you want internal loopback

  * @enable_external:
  * @enable_external:

- *                 Non zero if you want external loopback
+ *                Non zero if you want external loopback

  *
  * Returns Zero on success, negative on failure.
  */
  *
  * Returns Zero on success, negative on failure.
  */

diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c
index 2830e4bdf7f3f6d2faeaf753ef286805e27a4cce..1f3030c72d88706bee9d9558906360506ddbc970 100644 (file)
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-spi.c
@@ -160,16 +160,16 @@ cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port)
                result.s.link_up = inband.s.status;
                result.s.full_duplex = inband.s.duplex;
                switch (inband.s.speed) {
                result.s.link_up = inband.s.status;
                result.s.full_duplex = inband.s.duplex;
                switch (inband.s.speed) {

-               case 0: /* 10 Mbps */
+               case 0: /* 10 Mbps */

                        result.s.speed = 10;
                        break;
                        result.s.speed = 10;
                        break;

-               case 1: /* 100 Mbps */
+               case 1: /* 100 Mbps */

                        result.s.speed = 100;
                        break;
                        result.s.speed = 100;
                        break;

-               case 2: /* 1 Gbps */
+               case 2: /* 1 Gbps */

                        result.s.speed = 1000;
                        break;
                        result.s.speed = 1000;
                        break;

-               case 3: /* Illegal */
+               case 3: /* Illegal */

                        result.s.speed = 0;
                        result.s.link_up = 0;
                        break;
                        result.s.speed = 0;
                        result.s.link_up = 0;
                        break;

diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-util.c b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
index 116dea17acf5a3e0cbe273a352fe06ad4d126836..b72d9fbf97a327d4c5ff583db3f29fbdd4e6cd04 100644 (file)
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
@@ -96,9 +96,9 @@ int cvmx_helper_dump_packet(cvmx_wqe_t *work)
        uint8_t *end_of_data;
 
        cvmx_dprintf("Packet Length:   %u\n", work->len);
        uint8_t *end_of_data;
 
        cvmx_dprintf("Packet Length:   %u\n", work->len);

-       cvmx_dprintf("    Input Port:  %u\n", work->ipprt);
-       cvmx_dprintf("    QoS:         %u\n", work->qos);
-       cvmx_dprintf("    Buffers:     %u\n", work->word2.s.bufs);
+       cvmx_dprintf("    Input Port:  %u\n", work->ipprt);
+       cvmx_dprintf("    QoS:         %u\n", work->qos);
+       cvmx_dprintf("    Buffers:     %u\n", work->word2.s.bufs);

 
        if (work->word2.s.bufs == 0) {
                union cvmx_ipd_wqe_fpa_queue wqe_pool;
 
        if (work->word2.s.bufs == 0) {
                union cvmx_ipd_wqe_fpa_queue wqe_pool;


@@ -132,14 +132,14 @@ int cvmx_helper_dump_packet(cvmx_wqe_t *work)
        while (remaining_bytes) {
                start_of_buffer =
                    ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
        while (remaining_bytes) {
                start_of_buffer =
                    ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;

-               cvmx_dprintf("    Buffer Start:%llx\n",
+               cvmx_dprintf("    Buffer Start:%llx\n",

                             (unsigned long long)start_of_buffer);
                             (unsigned long long)start_of_buffer);

-               cvmx_dprintf("    Buffer I   : %u\n", buffer_ptr.s.i);
-               cvmx_dprintf("    Buffer Back: %u\n", buffer_ptr.s.back);
-               cvmx_dprintf("    Buffer Pool: %u\n", buffer_ptr.s.pool);
-               cvmx_dprintf("    Buffer Data: %llx\n",
+               cvmx_dprintf("    Buffer I   : %u\n", buffer_ptr.s.i);
+               cvmx_dprintf("    Buffer Back: %u\n", buffer_ptr.s.back);
+               cvmx_dprintf("    Buffer Pool: %u\n", buffer_ptr.s.pool);
+               cvmx_dprintf("    Buffer Data: %llx\n",

                             (unsigned long long)buffer_ptr.s.addr);
                             (unsigned long long)buffer_ptr.s.addr);

-               cvmx_dprintf("    Buffer Size: %u\n", buffer_ptr.s.size);
+               cvmx_dprintf("    Buffer Size: %u\n", buffer_ptr.s.size);

 
                cvmx_dprintf("\t\t");
                data_address = (uint8_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr);
 
                cvmx_dprintf("\t\t");
                data_address = (uint8_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr);


@@ -172,11 +172,11 @@ int cvmx_helper_dump_packet(cvmx_wqe_t *work)
  *
  * @queue:  Input queue to setup RED on (0-7)
  * @pass_thresh:
  *
  * @queue:  Input queue to setup RED on (0-7)
  * @pass_thresh:

- *               Packets will begin slowly dropping when there are less than
- *               this many packet buffers free in FPA 0.
+ *              Packets will begin slowly dropping when there are less than
+ *              this many packet buffers free in FPA 0.

  * @drop_thresh:
  * @drop_thresh:

- *               All incomming packets will be dropped when there are less
- *               than this many free packet buffers in FPA 0.
+ *              All incomming packets will be dropped when there are less
+ *              than this many free packet buffers in FPA 0.

  * Returns Zero on success. Negative on failure
  */
 int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh)
  * Returns Zero on success. Negative on failure
  */
 int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh)


@@ -207,11 +207,11 @@ int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh)
  * Setup Random Early Drop to automatically begin dropping packets.
  *
  * @pass_thresh:
  * Setup Random Early Drop to automatically begin dropping packets.
  *
  * @pass_thresh:

- *               Packets will begin slowly dropping when there are less than
- *               this many packet buffers free in FPA 0.
+ *              Packets will begin slowly dropping when there are less than
+ *              this many packet buffers free in FPA 0.

  * @drop_thresh:
  * @drop_thresh:

- *               All incomming packets will be dropped when there are less
- *               than this many free packet buffers in FPA 0.
+ *              All incomming packets will be dropped when there are less
+ *              than this many free packet buffers in FPA 0.

  * Returns Zero on success. Negative on failure
  */
 int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)
  * Returns Zero on success. Negative on failure
  */
 int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)

diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
index 1723248e987dcc07c6336d82e6b954e178ee1875..7653b7e92197f01d5091847172bb9c1087b2f29c 100644 (file)
--- a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c
@@ -321,9 +321,9 @@ int __cvmx_helper_xaui_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
  *
  * @ipd_port: IPD/PKO port to loopback.
  * @enable_internal:
  *
  * @ipd_port: IPD/PKO port to loopback.
  * @enable_internal:

- *                 Non zero if you want internal loopback
+ *                Non zero if you want internal loopback

  * @enable_external:
  * @enable_external:

- *                 Non zero if you want external loopback
+ *                Non zero if you want external loopback

  *
  * Returns Zero on success, negative on failure.
  */
  *
  * Returns Zero on success, negative on failure.
  */

diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c
index fa4963856353e46dffc55a0b1d22a794f85f94c0..d63d20dfbfb0d0b23bd5b681e658595f7a7b76b4 100644 (file)
--- a/arch/mips/cavium-octeon/executive/cvmx-helper.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c
@@ -111,7 +111,7 @@ int cvmx_helper_ports_on_interface(int interface)
  * @interface: Interface to probe
  *
  * Returns Mode of the interface. Unknown or unsupported interfaces return
  * @interface: Interface to probe
  *
  * Returns Mode of the interface. Unknown or unsupported interfaces return

- *         DISABLED.
+ *        DISABLED.

  */
 cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
 {
  */
 cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
 {


@@ -187,7 +187,7 @@ cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface)
  * the defines in executive-config.h.
  *
  * @ipd_port: Port to configure. This follows the IPD numbering, not the
  * the defines in executive-config.h.
  *
  * @ipd_port: Port to configure. This follows the IPD numbering, not the

- *                 per interface numbering
+ *                per interface numbering

  *
  * Returns Zero on success, negative on failure
  */
  *
  * Returns Zero on success, negative on failure
  */


@@ -591,7 +591,7 @@ static int __cvmx_helper_packet_hardware_enable(int interface)
  * Function to adjust internal IPD pointer alignments
  *
  * Returns 0 on success
  * Function to adjust internal IPD pointer alignments
  *
  * Returns 0 on success

- *         !0 on failure
+ *        !0 on failure

  */
 int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
 {
  */
 int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
 {


@@ -1068,9 +1068,9 @@ int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info)
  *
  * @ipd_port: IPD/PKO port to loopback.
  * @enable_internal:
  *
  * @ipd_port: IPD/PKO port to loopback.
  * @enable_internal:

- *                 Non zero if you want internal loopback
+ *                Non zero if you want internal loopback

  * @enable_external:
  * @enable_external:

- *                 Non zero if you want external loopback
+ *                Non zero if you want external loopback

  *
  * Returns Zero on success, negative on failure.
  */
  *
  * Returns Zero on success, negative on failure.
  */

diff --git a/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c
index 560e034aa024ed9397edd942375a5b51b2c86093..fa327ec891cd0c4d80075b132fa25e5c5a17b061 100644 (file)
--- a/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-interrupt-rsl.c
@@ -85,11 +85,11 @@ void __cvmx_interrupt_gmxx_enable(int interface)
        if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
                if (mode.s.en) {
                        switch (mode.cn56xx.mode) {
        if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
                if (mode.s.en) {
                        switch (mode.cn56xx.mode) {

-                       case 1: /* XAUI */
+                       case 1: /* XAUI */

                                num_ports = 1;
                                break;
                                num_ports = 1;
                                break;

-                       case 2: /* SGMII */
-                       case 3: /* PICMG */
+                       case 2: /* SGMII */
+                       case 3: /* PICMG */

                                num_ports = 4;
                                break;
                        default:        /* Disabled */
                                num_ports = 4;
                                break;
                        default:        /* Disabled */

diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
index 33b72144db3100625bd17991c1651ddd803ddf2b..42e38c30b540a361eaad725e668a46daa2636748 100644 (file)
--- a/arch/mips/cavium-octeon/executive/cvmx-l2c.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
@@ -147,7 +147,7 @@ int cvmx_l2c_set_hw_way_partition(uint32_t mask)
        mask &= valid_mask;
 
        /* A UMSK setting which blocks all L2C Ways is an error on some chips */
        mask &= valid_mask;
 
        /* A UMSK setting which blocks all L2C Ways is an error on some chips */

-       if (mask == valid_mask  && !OCTEON_IS_MODEL(OCTEON_CN63XX))
+       if (mask == valid_mask  && !OCTEON_IS_MODEL(OCTEON_CN63XX))

                return -1;
 
        if (OCTEON_IS_MODEL(OCTEON_CN63XX))
                return -1;
 
        if (OCTEON_IS_MODEL(OCTEON_CN63XX))


@@ -438,7 +438,7 @@ void cvmx_l2c_flush(void)
                for (set = 0; set < n_set; set++) {
                        for (assoc = 0; assoc < n_assoc; assoc++) {
                                address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
                for (set = 0; set < n_set; set++) {
                        for (assoc = 0; assoc < n_assoc; assoc++) {
                                address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,

-                                                      (assoc << assoc_shift) | (set << set_shift));
+                                                      (assoc << assoc_shift) | (set << set_shift));

                                CVMX_CACHE_WBIL2I(address, 0);
                        }
                }
                                CVMX_CACHE_WBIL2I(address, 0);
                        }
                }


@@ -573,8 +573,8 @@ union __cvmx_l2c_tag {
  * @index:  Index of the cacheline
  *
  * Returns The Octeon model specific tag structure.  This is
  * @index:  Index of the cacheline
  *
  * Returns The Octeon model specific tag structure.  This is

- *         translated by a wrapper function to a generic form that is
- *         easier for applications to use.
+ *        translated by a wrapper function to a generic form that is
+ *        easier for applications to use.

  */
 static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
 {
  */
 static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
 {


@@ -618,12 +618,12 @@ static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
                ".set push\n\t"
                ".set mips64\n\t"
                ".set noreorder\n\t"
                ".set push\n\t"
                ".set mips64\n\t"
                ".set noreorder\n\t"

-               "sd    %[dbg_val], 0(%[dbg_addr])\n\t"   /* Enter debug mode, wait for store */
+               "sd    %[dbg_val], 0(%[dbg_addr])\n\t"   /* Enter debug mode, wait for store */

                "ld    $0, 0(%[dbg_addr])\n\t"
                "ld    $0, 0(%[dbg_addr])\n\t"

-               "ld    %[tag_val], 0(%[tag_addr])\n\t"   /* Read L2C tag data */
-               "sd    $0, 0(%[dbg_addr])\n\t"          /* Exit debug mode, wait for store */
+               "ld    %[tag_val], 0(%[tag_addr])\n\t"   /* Read L2C tag data */
+               "sd    $0, 0(%[dbg_addr])\n\t"          /* Exit debug mode, wait for store */

                "ld    $0, 0(%[dbg_addr])\n\t"
                "ld    $0, 0(%[dbg_addr])\n\t"

-               "cache 9, 0($0)\n\t"             /* Invalidate dcache to discard debug data */
+               "cache 9, 0($0)\n\t"             /* Invalidate dcache to discard debug data */

                ".set pop"
                : [tag_val] "=r" (tag_val)
                : [dbg_addr] "r" (dbg_addr), [dbg_val] "r" (debug_val), [tag_addr] "r" (debug_tag_addr)
                ".set pop"
                : [tag_val] "=r" (tag_val)
                : [dbg_addr] "r" (dbg_addr), [dbg_val] "r" (debug_val), [tag_addr] "r" (debug_tag_addr)


@@ -664,10 +664,10 @@ union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index)
                CVMX_SYNC;   /* make sure CVMX_L2C_TADX_TAG is updated */
                l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0));
 
                CVMX_SYNC;   /* make sure CVMX_L2C_TADX_TAG is updated */
                l2c_tadx_tag.u64 = cvmx_read_csr(CVMX_L2C_TADX_TAG(0));
 

-               tag.s.V     = l2c_tadx_tag.s.valid;
-               tag.s.D     = l2c_tadx_tag.s.dirty;
-               tag.s.L     = l2c_tadx_tag.s.lock;
-               tag.s.U     = l2c_tadx_tag.s.use;
+               tag.s.V     = l2c_tadx_tag.s.valid;
+               tag.s.D     = l2c_tadx_tag.s.dirty;
+               tag.s.L     = l2c_tadx_tag.s.lock;
+               tag.s.U     = l2c_tadx_tag.s.use;

                tag.s.addr  = l2c_tadx_tag.s.tag;
        } else {
                union __cvmx_l2c_tag tmp_tag;
                tag.s.addr  = l2c_tadx_tag.s.tag;
        } else {
                union __cvmx_l2c_tag tmp_tag;


@@ -679,34 +679,34 @@ union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index)
                 * as it can represent all models.
                 */
                if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
                 * as it can represent all models.
                 */
                if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {

-                       tag.s.V    = tmp_tag.cn58xx.V;
-                       tag.s.D    = tmp_tag.cn58xx.D;
-                       tag.s.L    = tmp_tag.cn58xx.L;
-                       tag.s.U    = tmp_tag.cn58xx.U;
+                       tag.s.V    = tmp_tag.cn58xx.V;
+                       tag.s.D    = tmp_tag.cn58xx.D;
+                       tag.s.L    = tmp_tag.cn58xx.L;
+                       tag.s.U    = tmp_tag.cn58xx.U;

                        tag.s.addr = tmp_tag.cn58xx.addr;
                } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
                        tag.s.addr = tmp_tag.cn58xx.addr;
                } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {

-                       tag.s.V    = tmp_tag.cn38xx.V;
-                       tag.s.D    = tmp_tag.cn38xx.D;
-                       tag.s.L    = tmp_tag.cn38xx.L;
-                       tag.s.U    = tmp_tag.cn38xx.U;
+                       tag.s.V    = tmp_tag.cn38xx.V;
+                       tag.s.D    = tmp_tag.cn38xx.D;
+                       tag.s.L    = tmp_tag.cn38xx.L;
+                       tag.s.U    = tmp_tag.cn38xx.U;

                        tag.s.addr = tmp_tag.cn38xx.addr;
                } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
                        tag.s.addr = tmp_tag.cn38xx.addr;
                } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) {

-                       tag.s.V    = tmp_tag.cn31xx.V;
-                       tag.s.D    = tmp_tag.cn31xx.D;
-                       tag.s.L    = tmp_tag.cn31xx.L;
-                       tag.s.U    = tmp_tag.cn31xx.U;
+                       tag.s.V    = tmp_tag.cn31xx.V;
+                       tag.s.D    = tmp_tag.cn31xx.D;
+                       tag.s.L    = tmp_tag.cn31xx.L;
+                       tag.s.U    = tmp_tag.cn31xx.U;

                        tag.s.addr = tmp_tag.cn31xx.addr;
                } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
                        tag.s.addr = tmp_tag.cn31xx.addr;
                } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {

-                       tag.s.V    = tmp_tag.cn30xx.V;
-                       tag.s.D    = tmp_tag.cn30xx.D;
-                       tag.s.L    = tmp_tag.cn30xx.L;
-                       tag.s.U    = tmp_tag.cn30xx.U;
+                       tag.s.V    = tmp_tag.cn30xx.V;
+                       tag.s.D    = tmp_tag.cn30xx.D;
+                       tag.s.L    = tmp_tag.cn30xx.L;
+                       tag.s.U    = tmp_tag.cn30xx.U;

                        tag.s.addr = tmp_tag.cn30xx.addr;
                } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
                        tag.s.addr = tmp_tag.cn30xx.addr;
                } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {

-                       tag.s.V    = tmp_tag.cn50xx.V;
-                       tag.s.D    = tmp_tag.cn50xx.D;
-                       tag.s.L    = tmp_tag.cn50xx.L;
-                       tag.s.U    = tmp_tag.cn50xx.U;
+                       tag.s.V    = tmp_tag.cn50xx.V;
+                       tag.s.D    = tmp_tag.cn50xx.D;
+                       tag.s.L    = tmp_tag.cn50xx.L;
+                       tag.s.U    = tmp_tag.cn50xx.U;

                        tag.s.addr = tmp_tag.cn50xx.addr;
                } else {
                        cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
                        tag.s.addr = tmp_tag.cn50xx.addr;
                } else {
                        cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);


@@ -865,7 +865,7 @@ void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index)
                uint64_t address;
                /* Create the address based on index and association.
                 * Bits<20:17> select the way of the cache block involved in
                uint64_t address;
                /* Create the address based on index and association.
                 * Bits<20:17> select the way of the cache block involved in

-                *             the operation
+                *             the operation

                 * Bits<16:7> of the effect address select the index
                 */
                address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
                 * Bits<16:7> of the effect address select the index
                 */
                address = CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,

diff --git a/arch/mips/cavium-octeon/executive/cvmx-pko.c b/arch/mips/cavium-octeon/executive/cvmx-pko.c
index f557084b10924df198d018c8d79d6e3faa139f49..f2c877541597c6258282f1fb57b955a7ebffd744 100644 (file)
--- a/arch/mips/cavium-octeon/executive/cvmx-pko.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-pko.c
@@ -99,7 +99,7 @@ void cvmx_pko_initialize_global(void)
  * be called after the FPA has been initialized and filled with pages.
  *
  * Returns 0 on success
  * be called after the FPA has been initialized and filled with pages.
  *
  * Returns 0 on success

- *         !0 on failure
+ *        !0 on failure

  */
 int cvmx_pko_initialize_local(void)
 {
  */
 int cvmx_pko_initialize_local(void)
 {


@@ -186,19 +186,19 @@ void cvmx_pko_shutdown(void)
 /**
  * Configure a output port and the associated queues for use.
  *
 /**
  * Configure a output port and the associated queues for use.
  *

- * @port:       Port to configure.
+ * @port:      Port to configure.

  * @base_queue: First queue number to associate with this port.
  * @num_queues: Number of queues to associate with this port
  * @base_queue: First queue number to associate with this port.
  * @num_queues: Number of queues to associate with this port

- * @priority:   Array of priority levels for each queue. Values are
- *                   allowed to be 0-8. A value of 8 get 8 times the traffic
- *                   of a value of 1.  A value of 0 indicates that no rounds
- *                   will be participated in. These priorities can be changed
- *                   on the fly while the pko is enabled. A priority of 9
- *                   indicates that static priority should be used.  If static
- *                   priority is used all queues with static priority must be
- *                   contiguous starting at the base_queue, and lower numbered
- *                   queues have higher priority than higher numbered queues.
- *                   There must be num_queues elements in the array.
+ * @priority:  Array of priority levels for each queue. Values are
+ *                  allowed to be 0-8. A value of 8 get 8 times the traffic
+ *                  of a value of 1.  A value of 0 indicates that no rounds
+ *                  will be participated in. These priorities can be changed
+ *                  on the fly while the pko is enabled. A priority of 9
+ *                  indicates that static priority should be used.  If static
+ *                  priority is used all queues with static priority must be
+ *                  contiguous starting at the base_queue, and lower numbered
+ *                  queues have higher priority than higher numbered queues.
+ *                  There must be num_queues elements in the array.

  */
 cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue,
                                       uint64_t num_queues,
  */
 cvmx_pko_status_t cvmx_pko_config_port(uint64_t port, uint64_t base_queue,
                                       uint64_t num_queues,


@@ -440,7 +440,7 @@ void cvmx_pko_show_queue_map()
  * @port:      Port to rate limit
  * @packets_s: Maximum packet/sec
  * @burst:     Maximum number of packets to burst in a row before rate
  * @port:      Port to rate limit
  * @packets_s: Maximum packet/sec
  * @burst:     Maximum number of packets to burst in a row before rate

- *                  limiting cuts in.
+ *                 limiting cuts in.

  *
  * Returns Zero on success, negative on failure
  */
  *
  * Returns Zero on success, negative on failure
  */


@@ -473,7 +473,7 @@ int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst)
  * @port:   Port to rate limit
  * @bits_s: PKO rate limit in bits/sec
  * @burst:  Maximum number of bits to burst before rate
  * @port:   Port to rate limit
  * @bits_s: PKO rate limit in bits/sec
  * @burst:  Maximum number of bits to burst before rate

- *               limiting cuts in.
+ *              limiting cuts in.

  *
  * Returns Zero on success, negative on failure
  */
  *
  * Returns Zero on success, negative on failure
  */

diff --git a/arch/mips/cavium-octeon/executive/cvmx-spi.c b/arch/mips/cavium-octeon/executive/cvmx-spi.c
index 74afb1710cd98767d29837d0f9ed1630e5ebb5e9..ef5198d13a0edda220a3e91159da54fe0effe3d3 100644 (file)
--- a/arch/mips/cavium-octeon/executive/cvmx-spi.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-spi.c
@@ -69,7 +69,7 @@ static cvmx_spi_callbacks_t cvmx_spi_callbacks = {
 /**
  * Get current SPI4 initialization callbacks
  *
 /**
  * Get current SPI4 initialization callbacks
  *

- * @callbacks:  Pointer to the callbacks structure.to fill
+ * @callbacks: Pointer to the callbacks structure.to fill

  *
  * Returns Pointer to cvmx_spi_callbacks_t structure.
  */
  *
  * Returns Pointer to cvmx_spi_callbacks_t structure.
  */


@@ -92,11 +92,11 @@ void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks)
  * Initialize and start the SPI interface.
  *
  * @interface: The identifier of the packet interface to configure and
  * Initialize and start the SPI interface.
  *
  * @interface: The identifier of the packet interface to configure and

- *                  use as a SPI interface.
+ *                 use as a SPI interface.

  * @mode:      The operating mode for the SPI interface. The interface
  * @mode:      The operating mode for the SPI interface. The interface

- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
+ *                 can operate as a full duplex (both Tx and Rx data paths
+ *                 active) or as a halfplex (either the Tx data path is
+ *                 active or the Rx data path is active, but not both).

  * @timeout:   Timeout to wait for clock synchronization in seconds
  * @num_ports: Number of SPI ports to configure
  *
  * @timeout:   Timeout to wait for clock synchronization in seconds
  * @num_ports: Number of SPI ports to configure
  *


@@ -138,11 +138,11 @@ int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode, int timeout,
  * with its correspondent system.
  *
  * @interface: The identifier of the packet interface to configure and
  * with its correspondent system.
  *
  * @interface: The identifier of the packet interface to configure and

- *                  use as a SPI interface.
+ *                 use as a SPI interface.

  * @mode:      The operating mode for the SPI interface. The interface
  * @mode:      The operating mode for the SPI interface. The interface

- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
+ *                 can operate as a full duplex (both Tx and Rx data paths
+ *                 active) or as a halfplex (either the Tx data path is
+ *                 active or the Rx data path is active, but not both).

  * @timeout:   Timeout to wait for clock synchronization in seconds
  *
  * Returns Zero on success, negative of failure.
  * @timeout:   Timeout to wait for clock synchronization in seconds
  *
  * Returns Zero on success, negative of failure.


@@ -160,7 +160,7 @@ int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout)
        INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode);
 
        /* NOTE: Calendar setup is not performed during restart */
        INVOKE_CB(cvmx_spi_callbacks.reset_cb, interface, mode);
 
        /* NOTE: Calendar setup is not performed during restart */

-       /*       Refer to cvmx_spi_start_interface() for the full sequence */
+       /*       Refer to cvmx_spi_start_interface() for the full sequence */

 
        /* Callback to perform clock detection */
        INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout);
 
        /* Callback to perform clock detection */
        INVOKE_CB(cvmx_spi_callbacks.clock_detect_cb, interface, mode, timeout);


@@ -182,11 +182,11 @@ int cvmx_spi_restart_interface(int interface, cvmx_spi_mode_t mode, int timeout)
  * Callback to perform SPI4 reset
  *
  * @interface: The identifier of the packet interface to configure and
  * Callback to perform SPI4 reset
  *
  * @interface: The identifier of the packet interface to configure and

- *                  use as a SPI interface.
+ *                 use as a SPI interface.

  * @mode:      The operating mode for the SPI interface. The interface
  * @mode:      The operating mode for the SPI interface. The interface

- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
+ *                 can operate as a full duplex (both Tx and Rx data paths
+ *                 active) or as a halfplex (either the Tx data path is
+ *                 active or the Rx data path is active, but not both).

  *
  * Returns Zero on success, non-zero error code on failure (will cause
  * SPI initialization to abort)
  *
  * Returns Zero on success, non-zero error code on failure (will cause
  * SPI initialization to abort)


@@ -297,11 +297,11 @@ int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode)
  * Callback to setup calendar and miscellaneous settings before clock detection
  *
  * @interface: The identifier of the packet interface to configure and
  * Callback to setup calendar and miscellaneous settings before clock detection
  *
  * @interface: The identifier of the packet interface to configure and

- *                  use as a SPI interface.
+ *                 use as a SPI interface.

  * @mode:      The operating mode for the SPI interface. The interface
  * @mode:      The operating mode for the SPI interface. The interface

- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
+ *                 can operate as a full duplex (both Tx and Rx data paths
+ *                 active) or as a halfplex (either the Tx data path is
+ *                 active or the Rx data path is active, but not both).

  * @num_ports: Number of ports to configure on SPI
  *
  * Returns Zero on success, non-zero error code on failure (will cause
  * @num_ports: Number of ports to configure on SPI
  *
  * Returns Zero on success, non-zero error code on failure (will cause


@@ -382,7 +382,7 @@ int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode,
                stxx_spi4_dat.u64 = 0;
                /*Minimum needed by dynamic alignment */
                stxx_spi4_dat.s.alpha = 32;
                stxx_spi4_dat.u64 = 0;
                /*Minimum needed by dynamic alignment */
                stxx_spi4_dat.s.alpha = 32;

-               stxx_spi4_dat.s.max_t = 0xFFFF; /*Minimum interval is 0x20 */
+               stxx_spi4_dat.s.max_t = 0xFFFF; /*Minimum interval is 0x20 */

                cvmx_write_csr(CVMX_STXX_SPI4_DAT(interface),
                               stxx_spi4_dat.u64);
 
                cvmx_write_csr(CVMX_STXX_SPI4_DAT(interface),
                               stxx_spi4_dat.u64);
 


@@ -416,11 +416,11 @@ int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode,
  * Callback to perform clock detection
  *
  * @interface: The identifier of the packet interface to configure and
  * Callback to perform clock detection
  *
  * @interface: The identifier of the packet interface to configure and

- *                  use as a SPI interface.
+ *                 use as a SPI interface.

  * @mode:      The operating mode for the SPI interface. The interface
  * @mode:      The operating mode for the SPI interface. The interface

- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
+ *                 can operate as a full duplex (both Tx and Rx data paths
+ *                 active) or as a halfplex (either the Tx data path is
+ *                 active or the Rx data path is active, but not both).

  * @timeout:   Timeout to wait for clock synchronization in seconds
  *
  * Returns Zero on success, non-zero error code on failure (will cause
  * @timeout:   Timeout to wait for clock synchronization in seconds
  *
  * Returns Zero on success, non-zero error code on failure (will cause


@@ -494,11 +494,11 @@ int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode, int timeout)
  * Callback to perform link training
  *
  * @interface: The identifier of the packet interface to configure and
  * Callback to perform link training
  *
  * @interface: The identifier of the packet interface to configure and

- *                  use as a SPI interface.
+ *                 use as a SPI interface.

  * @mode:      The operating mode for the SPI interface. The interface
  * @mode:      The operating mode for the SPI interface. The interface

- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
+ *                 can operate as a full duplex (both Tx and Rx data paths
+ *                 active) or as a halfplex (either the Tx data path is
+ *                 active or the Rx data path is active, but not both).

  * @timeout:   Timeout to wait for link to be trained (in seconds)
  *
  * Returns Zero on success, non-zero error code on failure (will cause
  * @timeout:   Timeout to wait for link to be trained (in seconds)
  *
  * Returns Zero on success, non-zero error code on failure (will cause


@@ -563,11 +563,11 @@ int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode, int timeout)
  * Callback to perform calendar data synchronization
  *
  * @interface: The identifier of the packet interface to configure and
  * Callback to perform calendar data synchronization
  *
  * @interface: The identifier of the packet interface to configure and

- *                  use as a SPI interface.
+ *                 use as a SPI interface.

  * @mode:      The operating mode for the SPI interface. The interface
  * @mode:      The operating mode for the SPI interface. The interface

- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
+ *                 can operate as a full duplex (both Tx and Rx data paths
+ *                 active) or as a halfplex (either the Tx data path is
+ *                 active or the Rx data path is active, but not both).

  * @timeout:   Timeout to wait for calendar data in seconds
  *
  * Returns Zero on success, non-zero error code on failure (will cause
  * @timeout:   Timeout to wait for calendar data in seconds
  *
  * Returns Zero on success, non-zero error code on failure (will cause


@@ -620,11 +620,11 @@ int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode, int timeout)
  * Callback to handle interface up
  *
  * @interface: The identifier of the packet interface to configure and
  * Callback to handle interface up
  *
  * @interface: The identifier of the packet interface to configure and

- *                  use as a SPI interface.
+ *                 use as a SPI interface.

  * @mode:      The operating mode for the SPI interface. The interface
  * @mode:      The operating mode for the SPI interface. The interface

- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
+ *                 can operate as a full duplex (both Tx and Rx data paths
+ *                 active) or as a halfplex (either the Tx data path is
+ *                 active or the Rx data path is active, but not both).

  *
  * Returns Zero on success, non-zero error code on failure (will cause
  * SPI initialization to abort)
  *
  * Returns Zero on success, non-zero error code on failure (will cause
  * SPI initialization to abort)

diff --git a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
index 8b18a20cc7b3aace25c1cf60bdcdc7fc00958148..3d17fac293597a2b53bb9e9db19e679807423f89 100644 (file)
--- a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
+++ b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
@@ -74,26 +74,26 @@ EXPORT_SYMBOL(cvmx_sysinfo_get);
 
 /**
  * This function is used in non-simple executive environments (such as
 
 /**
  * This function is used in non-simple executive environments (such as

- * Linux kernel, u-boot, etc.)  to configure the minimal fields that
+ * Linux kernel, u-boot, etc.) to configure the minimal fields that

  * are required to use simple executive files directly.
  *
  * Locking (if required) must be handled outside of this
  * function
  *
  * @phy_mem_desc_ptr:
  * are required to use simple executive files directly.
  *
  * Locking (if required) must be handled outside of this
  * function
  *
  * @phy_mem_desc_ptr:

- *                   Pointer to global physical memory descriptor
- *                   (bootmem descriptor) @board_type: Octeon board
- *                   type enumeration
+ *                  Pointer to global physical memory descriptor
+ *                  (bootmem descriptor) @board_type: Octeon board
+ *                  type enumeration

  *
  * @board_rev_major:
  *
  * @board_rev_major:

- *                   Board major revision
+ *                  Board major revision

  * @board_rev_minor:
  * @board_rev_minor:

- *                   Board minor revision
+ *                  Board minor revision

  * @cpu_clock_hz:
  * @cpu_clock_hz:

- *                   CPU clock freqency in hertz
+ *                  CPU clock freqency in hertz

  *
  * Returns 0: Failure
  *
  * Returns 0: Failure

- *         1: success
+ *        1: success

  */
 int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr,
                                    uint16_t board_type,
  */
 int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr,
                                    uint16_t board_type,

diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index 46f5dbceeeccb3a04485a8adf816a91b2e3cef4e..156aa6143e1117646ab7b81ccf57ca623a258513 100644 (file)
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -1542,7 +1542,7 @@ static bool octeon_irq_ciu2_is_edge(unsigned int line, unsigned int bit)
 
        if (line == 3) /* MIO */
                switch (bit) {
 
        if (line == 3) /* MIO */
                switch (bit) {

-               case 2:  /* IPD_DRP */
+               case 2:  /* IPD_DRP */

                case 8 ... 11: /* Timers */
                case 48: /* PTP */
                        edge = true;
                case 8 ... 11: /* Timers */
                case 48: /* PTP */
                        edge = true;


@@ -1553,7 +1553,7 @@ static bool octeon_irq_ciu2_is_edge(unsigned int line, unsigned int bit)
        else if (line == 6) /* PKT */
                switch (bit) {
                case 52 ... 53: /* ILK_DRP */
        else if (line == 6) /* PKT */
                switch (bit) {
                case 52 ... 53: /* ILK_DRP */

-               case 8 ... 12:  /* GMX_DRP */
+               case 8 ... 12:  /* GMX_DRP */

                        edge = true;
                        break;
                default:
                        edge = true;
                        break;
                default:

diff --git a/arch/mips/cavium-octeon/octeon-memcpy.S b/arch/mips/cavium-octeon/octeon-memcpy.S
index 0ba0eb96d9ac1e3706c613335fd14104ff1c62b5..64e08df51d65f76b79310b1df6d52e2aa78e2a97 100644 (file)
--- a/arch/mips/cavium-octeon/octeon-memcpy.S
+++ b/arch/mips/cavium-octeon/octeon-memcpy.S
@@ -116,15 +116,15 @@
 
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 #define LDFIRST LOADR
 
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 #define LDFIRST LOADR

-#define LDREST  LOADL
+#define LDREST LOADL

 #define STFIRST STORER
 #define STFIRST STORER

-#define STREST  STOREL
+#define STREST STOREL

 #define SHIFT_DISCARD SLLV
 #else
 #define LDFIRST LOADL
 #define SHIFT_DISCARD SLLV
 #else
 #define LDFIRST LOADL

-#define LDREST  LOADR
+#define LDREST LOADR

 #define STFIRST STOREL
 #define STFIRST STOREL

-#define STREST  STORER
+#define STREST STORER

 #define SHIFT_DISCARD SRLV
 #endif
 
 #define SHIFT_DISCARD SRLV
 #endif
 


@@ -316,9 +316,9 @@ EXC(         STORE  t0, -8(dst),            s_exc_p1u)
 
 src_unaligned:
 #define rem t8
 
 src_unaligned:
 #define rem t8

-       SRL     t0, len, LOG_NBYTES+2    # +2 for 4 units/iter
+       SRL     t0, len, LOG_NBYTES+2    # +2 for 4 units/iter

        beqz    t0, cleanup_src_unaligned
        beqz    t0, cleanup_src_unaligned

-        and    rem, len, (4*NBYTES-1)   # rem = len % 4*NBYTES
+        and    rem, len, (4*NBYTES-1)   # rem = len % 4*NBYTES

 1:
 /*
  * Avoid consecutive LD*'s to the same register since some mips
 1:
 /*
  * Avoid consecutive LD*'s to the same register since some mips


@@ -326,13 +326,13 @@ src_unaligned:
  * It's OK to load FIRST(N+1) before REST(N) because the two addresses
  * are to the same unit (unless src is aligned, but it's not).
  */
  * It's OK to load FIRST(N+1) before REST(N) because the two addresses
  * are to the same unit (unless src is aligned, but it's not).
  */

-EXC(   LDFIRST t0, FIRST(0)(src),      l_exc)
-EXC(   LDFIRST t1, FIRST(1)(src),      l_exc_copy)
-       SUB     len, len, 4*NBYTES
+EXC(   LDFIRST t0, FIRST(0)(src),      l_exc)
+EXC(   LDFIRST t1, FIRST(1)(src),      l_exc_copy)
+       SUB     len, len, 4*NBYTES

 EXC(   LDREST  t0, REST(0)(src),       l_exc_copy)
 EXC(   LDREST  t1, REST(1)(src),       l_exc_copy)
 EXC(   LDREST  t0, REST(0)(src),       l_exc_copy)
 EXC(   LDREST  t1, REST(1)(src),       l_exc_copy)

-EXC(   LDFIRST t2, FIRST(2)(src),      l_exc_copy)
-EXC(   LDFIRST t3, FIRST(3)(src),      l_exc_copy)
+EXC(   LDFIRST t2, FIRST(2)(src),      l_exc_copy)
+EXC(   LDFIRST t3, FIRST(3)(src),      l_exc_copy)

 EXC(   LDREST  t2, REST(2)(src),       l_exc_copy)
 EXC(   LDREST  t3, REST(3)(src),       l_exc_copy)
        ADD     src, src, 4*NBYTES
 EXC(   LDREST  t2, REST(2)(src),       l_exc_copy)
 EXC(   LDREST  t3, REST(3)(src),       l_exc_copy)
        ADD     src, src, 4*NBYTES

diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c
index 3c1b625a5859046a9d186fb18f4ed691854e892c..389512e2abd6198d7ce16851f6ef7f0c6b36c127 100644 (file)
--- a/arch/mips/cavium-octeon/octeon-platform.c
+++ b/arch/mips/cavium-octeon/octeon-platform.c
@@ -410,7 +410,7 @@ int __init octeon_prune_device_tree(void)
        pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
        if (pip_path) {
                int pip = fdt_path_offset(initial_boot_params, pip_path);
        pip_path = fdt_getprop(initial_boot_params, aliases, "pip", NULL);
        if (pip_path) {
                int pip = fdt_path_offset(initial_boot_params, pip_path);

-               if (pip  >= 0)
+               if (pip  >= 0)

                        for (i = 0; i <= 4; i++)
                                octeon_fdt_pip_iface(pip, i, &mac_addr_base);
        }
                        for (i = 0; i <= 4; i++)
                                octeon_fdt_pip_iface(pip, i, &mac_addr_base);
        }

diff --git a/arch/mips/cavium-octeon/octeon_3xxx.dts b/arch/mips/cavium-octeon/octeon_3xxx.dts
index f28b2d0fde2226e5c73da4bc6029460a88886bcd..88cb42d4cc49f8d89c37e10210d03ffb9f57a508 100644 (file)
--- a/arch/mips/cavium-octeon/octeon_3xxx.dts
+++ b/arch/mips/cavium-octeon/octeon_3xxx.dts
@@ -3,7 +3,7 @@
  * OCTEON 3XXX, 5XXX, 63XX device tree skeleton.
  *
  * This device tree is pruned and patched by early boot code before
  * OCTEON 3XXX, 5XXX, 63XX device tree skeleton.
  *
  * This device tree is pruned and patched by early boot code before

- * use.  Because of this, it contains a super-set of the available
+ * use.         Because of this, it contains a super-set of the available

  * devices and properties.
  */
 / {
  * devices and properties.
  */
 / {


@@ -433,12 +433,12 @@
                                cavium,t-we   = <45>;
                                cavium,t-rd-hld = <35>;
                                cavium,t-wr-hld = <45>;
                                cavium,t-we   = <45>;
                                cavium,t-rd-hld = <35>;
                                cavium,t-wr-hld = <45>;

-                               cavium,t-pause  = <0>;
-                               cavium,t-wait   = <0>;
-                               cavium,t-page   = <35>;
+                               cavium,t-pause  = <0>;
+                               cavium,t-wait   = <0>;
+                               cavium,t-page   = <35>;

                                cavium,t-rd-dly = <0>;
 
                                cavium,t-rd-dly = <0>;
 

-                               cavium,pages     = <0>;
+                               cavium,pages     = <0>;

                                cavium,bus-width = <8>;
                        };
                        cavium,cs-config@4 {
                                cavium,bus-width = <8>;
                        };
                        cavium,cs-config@4 {


@@ -450,12 +450,12 @@
                                cavium,t-we   = <320>;
                                cavium,t-rd-hld = <320>;
                                cavium,t-wr-hld = <320>;
                                cavium,t-we   = <320>;
                                cavium,t-rd-hld = <320>;
                                cavium,t-wr-hld = <320>;

-                               cavium,t-pause  = <320>;
-                               cavium,t-wait   = <320>;
-                               cavium,t-page   = <320>;
+                               cavium,t-pause  = <320>;
+                               cavium,t-wait   = <320>;
+                               cavium,t-page   = <320>;

                                cavium,t-rd-dly = <0>;
 
                                cavium,t-rd-dly = <0>;
 

-                               cavium,pages     = <0>;
+                               cavium,pages     = <0>;

                                cavium,bus-width = <8>;
                        };
                        cavium,cs-config@5 {
                                cavium,bus-width = <8>;
                        };
                        cavium,cs-config@5 {


@@ -467,12 +467,12 @@
                                cavium,t-we   = <150>;
                                cavium,t-rd-hld = <100>;
                                cavium,t-wr-hld = <30>;
                                cavium,t-we   = <150>;
                                cavium,t-rd-hld = <100>;
                                cavium,t-wr-hld = <30>;

-                               cavium,t-pause  = <0>;
-                               cavium,t-wait   = <30>;
-                               cavium,t-page   = <320>;
+                               cavium,t-pause  = <0>;
+                               cavium,t-wait   = <30>;
+                               cavium,t-page   = <320>;

                                cavium,t-rd-dly = <0>;
 
                                cavium,t-rd-dly = <0>;
 

-                               cavium,pages     = <0>;
+                               cavium,pages     = <0>;

                                cavium,bus-width = <16>;
                        };
                        cavium,cs-config@6 {
                                cavium,bus-width = <16>;
                        };
                        cavium,cs-config@6 {


@@ -484,12 +484,12 @@
                                cavium,t-we   = <150>;
                                cavium,t-rd-hld = <100>;
                                cavium,t-wr-hld = <70>;
                                cavium,t-we   = <150>;
                                cavium,t-rd-hld = <100>;
                                cavium,t-wr-hld = <70>;

-                               cavium,t-pause  = <0>;
-                               cavium,t-wait   = <0>;
-                               cavium,t-page   = <320>;
+                               cavium,t-pause  = <0>;
+                               cavium,t-wait   = <0>;
+                               cavium,t-page   = <320>;

                                cavium,t-rd-dly = <0>;
 
                                cavium,t-rd-dly = <0>;
 

-                               cavium,pages     = <0>;
+                               cavium,pages     = <0>;

                                cavium,wait-mode;
                                cavium,bus-width = <16>;
                        };
                                cavium,wait-mode;
                                cavium,bus-width = <16>;
                        };

diff --git a/arch/mips/cavium-octeon/octeon_68xx.dts b/arch/mips/cavium-octeon/octeon_68xx.dts
index 1839468932b68a8964eb96b36afcd0e4e64976b5..79b46fcb0a1141756bacc047f1ae11328d4d214d 100644 (file)
--- a/arch/mips/cavium-octeon/octeon_68xx.dts
+++ b/arch/mips/cavium-octeon/octeon_68xx.dts
@@ -3,7 +3,7 @@
  * OCTEON 68XX device tree skeleton.
  *
  * This device tree is pruned and patched by early boot code before
  * OCTEON 68XX device tree skeleton.
  *
  * This device tree is pruned and patched by early boot code before

- * use.  Because of this, it contains a super-set of the available
+ * use.         Because of this, it contains a super-set of the available

  * devices and properties.
  */
 / {
  * devices and properties.
  */
 / {


@@ -469,12 +469,12 @@
                                cavium,t-we   = <35>;
                                cavium,t-rd-hld = <25>;
                                cavium,t-wr-hld = <35>;
                                cavium,t-we   = <35>;
                                cavium,t-rd-hld = <25>;
                                cavium,t-wr-hld = <35>;

-                               cavium,t-pause  = <0>;
-                               cavium,t-wait   = <300>;
-                               cavium,t-page   = <25>;
+                               cavium,t-pause  = <0>;
+                               cavium,t-wait   = <300>;
+                               cavium,t-page   = <25>;

                                cavium,t-rd-dly = <0>;
 
                                cavium,t-rd-dly = <0>;
 

-                               cavium,pages     = <0>;
+                               cavium,pages     = <0>;

                                cavium,bus-width = <8>;
                        };
                        cavium,cs-config@4 {
                                cavium,bus-width = <8>;
                        };
                        cavium,cs-config@4 {


@@ -486,12 +486,12 @@
                                cavium,t-we   = <320>;
                                cavium,t-rd-hld = <320>;
                                cavium,t-wr-hld = <320>;
                                cavium,t-we   = <320>;
                                cavium,t-rd-hld = <320>;
                                cavium,t-wr-hld = <320>;

-                               cavium,t-pause  = <320>;
-                               cavium,t-wait   = <320>;
-                               cavium,t-page   = <320>;
+                               cavium,t-pause  = <320>;
+                               cavium,t-wait   = <320>;
+                               cavium,t-page   = <320>;

                                cavium,t-rd-dly = <0>;
 
                                cavium,t-rd-dly = <0>;
 

-                               cavium,pages     = <0>;
+                               cavium,pages     = <0>;

                                cavium,bus-width = <8>;
                        };
                        cavium,cs-config@5 {
                                cavium,bus-width = <8>;
                        };
                        cavium,cs-config@5 {


@@ -503,12 +503,12 @@
                                cavium,t-we   = <150>;
                                cavium,t-rd-hld = <100>;
                                cavium,t-wr-hld = <300>;
                                cavium,t-we   = <150>;
                                cavium,t-rd-hld = <100>;
                                cavium,t-wr-hld = <300>;

-                               cavium,t-pause  = <0>;
-                               cavium,t-wait   = <300>;
-                               cavium,t-page   = <310>;
+                               cavium,t-pause  = <0>;
+                               cavium,t-wait   = <300>;
+                               cavium,t-page   = <310>;

                                cavium,t-rd-dly = <0>;
 
                                cavium,t-rd-dly = <0>;
 

-                               cavium,pages     = <0>;
+                               cavium,pages     = <0>;

                                cavium,bus-width = <16>;
                        };
                        cavium,cs-config@6 {
                                cavium,bus-width = <16>;
                        };
                        cavium,cs-config@6 {


@@ -520,12 +520,12 @@
                                cavium,t-we   = <150>;
                                cavium,t-rd-hld = <100>;
                                cavium,t-wr-hld = <30>;
                                cavium,t-we   = <150>;
                                cavium,t-rd-hld = <100>;
                                cavium,t-wr-hld = <30>;

-                               cavium,t-pause  = <0>;
-                               cavium,t-wait   = <30>;
-                               cavium,t-page   = <310>;
+                               cavium,t-pause  = <0>;
+                               cavium,t-wait   = <30>;
+                               cavium,t-page   = <310>;

                                cavium,t-rd-dly = <0>;
 
                                cavium,t-rd-dly = <0>;
 

-                               cavium,pages     = <0>;
+                               cavium,pages     = <0>;

                                cavium,wait-mode;
                                cavium,bus-width = <16>;
                        };
                                cavium,wait-mode;
                                cavium,bus-width = <16>;
                        };

diff --git a/arch/mips/cavium-octeon/octeon_boot.h b/arch/mips/cavium-octeon/octeon_boot.h
index 428864b2ba4133070c563023f9c170346e24c4ca..7b066bbca86d11f9020932475854e85944347db7 100644 (file)
--- a/arch/mips/cavium-octeon/octeon_boot.h
+++ b/arch/mips/cavium-octeon/octeon_boot.h
@@ -31,7 +31,7 @@ struct boot_init_vector {
        uint32_t k0_val;
        /* Address of boot info block structure */
        uint64_t boot_info_addr;
        uint32_t k0_val;
        /* Address of boot info block structure */
        uint64_t boot_info_addr;

-       uint32_t flags;         /* flags */
+       uint32_t flags;         /* flags */

        uint32_t pad;
 };
 
        uint32_t pad;
 };
 


@@ -53,20 +53,20 @@ struct linux_app_boot_info {
 
 /* If not to copy a lot of bootloader's structures
    here is only offset of requested member */
 
 /* If not to copy a lot of bootloader's structures
    here is only offset of requested member */

-#define AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK    0x765c
+#define AVAIL_COREMASK_OFFSET_IN_LINUX_APP_BOOT_BLOCK   0x765c

 
 /* hardcoded in bootloader */
 
 /* hardcoded in bootloader */

-#define  LABI_ADDR_IN_BOOTLOADER                         0x700
+#define         LABI_ADDR_IN_BOOTLOADER                         0x700

 
 #define LINUX_APP_BOOT_BLOCK_NAME "linux-app-boot"
 
 #define LABI_SIGNATURE 0xAABBCC01
 
 /*  from uboot-headers/octeon_mem_map.h */
 
 #define LINUX_APP_BOOT_BLOCK_NAME "linux-app-boot"
 
 #define LABI_SIGNATURE 0xAABBCC01
 
 /*  from uboot-headers/octeon_mem_map.h */

-#define EXCEPTION_BASE_INCR     (4 * 1024)
+#define EXCEPTION_BASE_INCR    (4 * 1024)

                               /* Increment size for exception base addresses (4k minimum) */
                               /* Increment size for exception base addresses (4k minimum) */

-#define EXCEPTION_BASE_BASE     0
-#define BOOTLOADER_PRIV_DATA_BASE       (EXCEPTION_BASE_BASE + 0x800)
-#define BOOTLOADER_BOOT_VECTOR          (BOOTLOADER_PRIV_DATA_BASE)
+#define EXCEPTION_BASE_BASE    0
+#define BOOTLOADER_PRIV_DATA_BASE      (EXCEPTION_BASE_BASE + 0x800)
+#define BOOTLOADER_BOOT_VECTOR         (BOOTLOADER_PRIV_DATA_BASE)

 
 #endif /* __OCTEON_BOOT_H__ */
 
 #endif /* __OCTEON_BOOT_H__ */

diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index d7e0a09f77c2db27ab7657b40d56894a24ab6c2e..c594a3d4f743be31d2933e5ed5589f423d8a3743 100644 (file)
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -319,7 +319,7 @@ EXPORT_SYMBOL(octeon_get_io_clock_rate);
  * exists on most Cavium evaluation boards. If it doesn't exist, then
  * this function doesn't do anything.
  *
  * exists on most Cavium evaluation boards. If it doesn't exist, then
  * this function doesn't do anything.
  *

- * @s:      String to write
+ * @s:     String to write

  */
 void octeon_write_lcd(const char *s)
 {
  */
 void octeon_write_lcd(const char *s)
 {


@@ -341,7 +341,7 @@ void octeon_write_lcd(const char *s)
 /**
  * Return the console uart passed by the bootloader
  *
 /**
  * Return the console uart passed by the bootloader
  *

- * Returns uart   (0 or 1)
+ * Returns uart          (0 or 1)

  */
 int octeon_get_boot_uart(void)
 {
  */
 int octeon_get_boot_uart(void)
 {


@@ -805,7 +805,7 @@ void __init prom_init(void)
                        /*
                         * To do: switch parsing to new style, something like:
                         * parse_crashkernel(arg, sysinfo->system_dram_size,
                        /*
                         * To do: switch parsing to new style, something like:
                         * parse_crashkernel(arg, sysinfo->system_dram_size,

-                        *                &crashk_size, &crashk_base);
+                        *                &crashk_size, &crashk_base);

                         */
 #endif
                } else if (strlen(arcs_cmdline) + strlen(arg) + 1 <
                         */
 #endif
                } else if (strlen(arcs_cmdline) + strlen(arg) + 1 <


@@ -1013,7 +1013,7 @@ void __init plat_mem_setup(void)
 }
 
 /*
 }
 
 /*

- * Emit one character to the boot UART.  Exported for use by the
+ * Emit one character to the boot UART.         Exported for use by the

  * watchdog timer.
  */
 int prom_putchar(char c)
  * watchdog timer.
  */
 int prom_putchar(char c)

diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index ee1fb9f7f517c29e1ce6781699cbf90e75a314ce..295137dfdc37ce61d323e45c1f7839e84f2245bc 100644 (file)
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -55,7 +55,7 @@ static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
 
 /**
  * Cause the function described by call_data to be executed on the passed
 
 /**
  * Cause the function described by call_data to be executed on the passed

- * cpu.  When the function has finished, increment the finished field of
+ * cpu.         When the function has finished, increment the finished field of

  * call_data.
  */
 void octeon_send_ipi_single(int cpu, unsigned int action)
  * call_data.
  */
 void octeon_send_ipi_single(int cpu, unsigned int action)


@@ -126,8 +126,8 @@ static void octeon_smp_setup(void)
 
 #ifdef CONFIG_HOTPLUG_CPU
        /*
 
 #ifdef CONFIG_HOTPLUG_CPU
        /*

-        * The possible CPUs are all those present on the chip.  We
-        * will assign CPU numbers for possible cores as well.  Cores
+        * The possible CPUs are all those present on the chip.  We
+        * will assign CPU numbers for possible cores as well.  Cores

         * are always consecutively numberd from 0.
         */
        for (id = 0; id < num_cores && id < NR_CPUS; id++) {
         * are always consecutively numberd from 0.
         */
        for (id = 0; id < num_cores && id < NR_CPUS; id++) {


@@ -332,7 +332,7 @@ extern void kernel_entry(unsigned long arg1, ...);
 
 static void start_after_reset(void)
 {
 
 static void start_after_reset(void)
 {

-       kernel_entry(0, 0, 0);  /* set a2 = 0 for secondary core */
+       kernel_entry(0, 0, 0);  /* set a2 = 0 for secondary core */

 }
 
 static int octeon_update_boot_vector(unsigned int cpu)
 }
 
 static int octeon_update_boot_vector(unsigned int cpu)


@@ -401,7 +401,7 @@ static int __cpuinit register_cavium_notifier(void)
 }
 late_initcall(register_cavium_notifier);
 
 }
 late_initcall(register_cavium_notifier);
 

-#endif  /* CONFIG_HOTPLUG_CPU */
+#endif /* CONFIG_HOTPLUG_CPU */

 
 struct plat_smp_ops octeon_smp_ops = {
        .send_ipi_single        = octeon_send_ipi_single,
 
 struct plat_smp_ops octeon_smp_ops = {
        .send_ipi_single        = octeon_send_ipi_single,

diff --git a/arch/mips/cobalt/led.c b/arch/mips/cobalt/led.c
index d3ce6fa1dc74cec54c66d6e973ae03eeb429e2e0..32265f514e3f1d2fd70737c0e8e6c40ca40c4692 100644 (file)
--- a/arch/mips/cobalt/led.c
+++ b/arch/mips/cobalt/led.c
@@ -1,7 +1,7 @@
 /*
  *  Registration of Cobalt LED platform device.
  *
 /*
  *  Registration of Cobalt LED platform device.
  *

- *  Copyright (C) 2007  Yoichi Yuasa <yuasa@linux-mips.org>
+ *  Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>

  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by

diff --git a/arch/mips/cobalt/mtd.c b/arch/mips/cobalt/mtd.c
index 691d620b6766a078b51c051ceeb4c57af4e76033..8db7b5d8156030dd3af64184cd58c4e41a42df85 100644 (file)
--- a/arch/mips/cobalt/mtd.c
+++ b/arch/mips/cobalt/mtd.c
@@ -25,7 +25,7 @@
 static struct mtd_partition cobalt_mtd_partitions[] = {
        {
                .name   = "firmware",
 static struct mtd_partition cobalt_mtd_partitions[] = {
        {
                .name   = "firmware",

-               .offset = 0x0,
+               .offset = 0x0,

                .size   = 0x80000,
        },
 };
                .size   = 0x80000,
        },
 };

diff --git a/arch/mips/cobalt/rtc.c b/arch/mips/cobalt/rtc.c
index 3ab39898b4e46b3a3b7c5615b8b5fe85b5e8473b..a6bc75ada9df94b58c7ea51cffbafbdedb224a61 100644 (file)
--- a/arch/mips/cobalt/rtc.c
+++ b/arch/mips/cobalt/rtc.c
@@ -46,7 +46,7 @@ static __init int cobalt_rtc_add(void)
                return -ENOMEM;
 
        retval = platform_device_add_resources(pdev, cobalt_rtc_resource,
                return -ENOMEM;
 
        retval = platform_device_add_resources(pdev, cobalt_rtc_resource,

-                                              ARRAY_SIZE(cobalt_rtc_resource));
+                                              ARRAY_SIZE(cobalt_rtc_resource));

        if (retval)
                goto err_free_device;
 
        if (retval)
                goto err_free_device;
 

diff --git a/arch/mips/dec/int-handler.S b/arch/mips/dec/int-handler.S
index 82c85281878143cfc6cc4d85131f978cc49c2467..22afed16ccde293a741e88c9f2fd9f56b733ccd1 100644 (file)
--- a/arch/mips/dec/int-handler.S
+++ b/arch/mips/dec/int-handler.S
@@ -55,70 +55,70 @@
  * DS2100/3100's, aka kn01, aka Pmax:
  *
  *     MIPS IRQ        Source
  * DS2100/3100's, aka kn01, aka Pmax:
  *
  *     MIPS IRQ        Source

- *      --------        ------
- *             0       Software (ignored)
- *             1        Software (ignored)
- *             2        SCSI
- *             3        Lance Ethernet
- *             4        DZ11 serial
- *             5        RTC
- *             6        Memory Controller & Video
- *             7        FPU
+ *     --------        ------
+ *            0        Software (ignored)
+ *            1        Software (ignored)
+ *            2        SCSI
+ *            3        Lance Ethernet
+ *            4        DZ11 serial
+ *            5        RTC
+ *            6        Memory Controller & Video
+ *            7        FPU

  *
  * DS5000/200, aka kn02, aka 3max:
  *
  *     MIPS IRQ        Source
  *
  * DS5000/200, aka kn02, aka 3max:
  *
  *     MIPS IRQ        Source

- *      --------        ------
- *             0       Software (ignored)
- *             1        Software (ignored)
- *             2        TurboChannel
- *             3        RTC
- *             4        Reserved
- *             5        Memory Controller
- *             6        Reserved
- *             7        FPU
+ *     --------        ------
+ *            0        Software (ignored)
+ *            1        Software (ignored)
+ *            2        TurboChannel
+ *            3        RTC
+ *            4        Reserved
+ *            5        Memory Controller
+ *            6        Reserved
+ *            7        FPU

  *
  * DS5000/1xx's, aka kn02ba, aka 3min:
  *
  *     MIPS IRQ        Source
  *
  * DS5000/1xx's, aka kn02ba, aka 3min:
  *
  *     MIPS IRQ        Source

- *      --------        ------
- *             0       Software (ignored)
- *             1        Software (ignored)
- *             2        TurboChannel Slot 0
- *             3        TurboChannel Slot 1
- *             4        TurboChannel Slot 2
- *             5        TurboChannel Slot 3 (ASIC)
- *             6        Halt button
- *             7        FPU/R4k timer
+ *     --------        ------
+ *            0        Software (ignored)
+ *            1        Software (ignored)
+ *            2        TurboChannel Slot 0
+ *            3        TurboChannel Slot 1
+ *            4        TurboChannel Slot 2
+ *            5        TurboChannel Slot 3 (ASIC)
+ *            6        Halt button
+ *            7        FPU/R4k timer

  *
  * DS5000/2x's, aka kn02ca, aka maxine:
  *
  *     MIPS IRQ        Source
  *
  * DS5000/2x's, aka kn02ca, aka maxine:
  *
  *     MIPS IRQ        Source

- *      --------        ------
- *             0       Software (ignored)
- *             1        Software (ignored)
- *             2        Periodic Interrupt (100usec)
- *             3        RTC
- *             4        I/O write timeout
- *             5        TurboChannel (ASIC)
- *             6        Halt Keycode from Access.Bus keyboard (CTRL-ALT-ENTER)
- *             7        FPU/R4k timer
+ *     --------        ------
+ *            0        Software (ignored)
+ *            1        Software (ignored)
+ *            2        Periodic Interrupt (100usec)
+ *            3        RTC
+ *            4        I/O write timeout
+ *            5        TurboChannel (ASIC)
+ *            6        Halt Keycode from Access.Bus keyboard (CTRL-ALT-ENTER)
+ *            7        FPU/R4k timer

  *
  * DS5000/2xx's, aka kn03, aka 3maxplus:
  *
  *     MIPS IRQ        Source
  *
  * DS5000/2xx's, aka kn03, aka 3maxplus:
  *
  *     MIPS IRQ        Source

- *      --------        ------
- *             0       Software (ignored)
- *             1        Software (ignored)
- *             2        System Board (ASIC)
- *             3        RTC
- *             4        Reserved
- *             5        Memory
- *             6        Halt Button
- *             7        FPU/R4k timer
+ *     --------        ------
+ *            0        Software (ignored)
+ *            1        Software (ignored)
+ *            2        System Board (ASIC)
+ *            3        RTC
+ *            4        Reserved
+ *            5        Memory
+ *            6        Halt Button
+ *            7        FPU/R4k timer

  *
  * We handle the IRQ according to _our_ priority (see setup.c),
  *
  * We handle the IRQ according to _our_ priority (see setup.c),

- * then we just return.  If multiple IRQs are pending then we will
+ * then we just return.         If multiple IRQs are pending then we will

  * just take another exception, big deal.
  */
                .align  5
  * just take another exception, big deal.
  */
                .align  5


@@ -146,7 +146,7 @@
                /*
                 * Find irq with highest priority
                 */
                /*
                 * Find irq with highest priority
                 */

-                PTR_LA t1,cpu_mask_nr_tbl
+                PTR_LA t1,cpu_mask_nr_tbl

 1:             lw      t2,(t1)
                nop
                and     t2,t0
 1:             lw      t2,(t1)
                nop
                and     t2,t0


@@ -195,7 +195,7 @@
                /*
                 * Find irq with highest priority
                 */
                /*
                 * Find irq with highest priority
                 */

-                PTR_LA t1,asic_mask_nr_tbl
+                PTR_LA t1,asic_mask_nr_tbl

 2:             lw      t2,(t1)
                nop
                and     t2,t0
 2:             lw      t2,(t1)
                nop
                and     t2,t0


@@ -221,7 +221,7 @@
                FEXPORT(cpu_all_int)            # HALT, timers, software junk
                li      a0,DEC_CPU_IRQ_BASE
                srl     t0,CAUSEB_IP
                FEXPORT(cpu_all_int)            # HALT, timers, software junk
                li      a0,DEC_CPU_IRQ_BASE
                srl     t0,CAUSEB_IP

-               li      t1,CAUSEF_IP>>CAUSEB_IP # mask
+               li      t1,CAUSEF_IP>>CAUSEB_IP # mask

                b       1f
                 li     t2,4                    # nr of bits / 2
 
                b       1f
                 li     t2,4                    # nr of bits / 2
 

diff --git a/arch/mips/dec/kn02xa-berr.c b/arch/mips/dec/kn02xa-berr.c
index ebb73c51d821e6c7fd45339686aed121668d96f4..f434b759e3b9aaa0f6eb9ab07f85fb783de4a6ad 100644 (file)
--- a/arch/mips/dec/kn02xa-berr.c
+++ b/arch/mips/dec/kn02xa-berr.c
@@ -128,8 +128,8 @@ void __init dec_kn02xa_be_init(void)
 {
        volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
 
 {
        volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
 

-        /* For KN04 we need to make sure EE (?) is enabled in the MB.  */
-        if (current_cpu_type() == CPU_R4000SC)
+       /* For KN04 we need to make sure EE (?) is enabled in the MB.  */
+       if (current_cpu_type() == CPU_R4000SC)

                *mbcs |= KN4K_MB_CSR_EE;
        fast_iob();
 
                *mbcs |= KN4K_MB_CSR_EE;
        fast_iob();
 

diff --git a/arch/mips/dec/prom/call_o32.S b/arch/mips/dec/prom/call_o32.S
index 8c8498159e434fa039f7ecae3e290ee0c31d6677..c0d1522d448f91591e06131454598232f931198a 100644 (file)
--- a/arch/mips/dec/prom/call_o32.S
+++ b/arch/mips/dec/prom/call_o32.S
@@ -14,7 +14,7 @@
 
 /* Maximum number of arguments supported.  Must be even!  */
 #define O32_ARGC       32
 
 /* Maximum number of arguments supported.  Must be even!  */
 #define O32_ARGC       32

-/* Number of static registers we save.  */
+/* Number of static registers we save. */

 #define O32_STATC      11
 /* Frame size for both of the above.  */
 #define O32_FRAMESZ    (4 * O32_ARGC + SZREG * O32_STATC)
 #define O32_STATC      11
 /* Frame size for both of the above.  */
 #define O32_FRAMESZ    (4 * O32_ARGC + SZREG * O32_STATC)

diff --git a/arch/mips/dec/prom/dectypes.h b/arch/mips/dec/prom/dectypes.h
index 707b6f1f5a9d57f91402bbaa25edb65fe0dac01f..69ea5b9c8190af718ea810767f27eb089b4134ce 100644 (file)
--- a/arch/mips/dec/prom/dectypes.h
+++ b/arch/mips/dec/prom/dectypes.h
@@ -1,5 +1,5 @@
 #ifndef DECTYPES
 #ifndef DECTYPES

-#define        DECTYPES
+#define DECTYPES

 
 #define DS2100_3100    1       /* DS2100/3100  Pmax            */
 #define DS5000_200     2       /* DS5000/200   3max            */
 
 #define DS2100_3100    1       /* DS2100/3100  Pmax            */
 #define DS5000_200     2       /* DS5000/200   3max            */

diff --git a/arch/mips/dec/prom/init.c b/arch/mips/dec/prom/init.c
index 93f1239af524485c03298e917b26d62e22cf9be6..ab169046e442a9c44a74e2db2fcb2cf14a11081f 100644 (file)
--- a/arch/mips/dec/prom/init.c
+++ b/arch/mips/dec/prom/init.c
@@ -103,7 +103,7 @@ void __init prom_init(void)
        if (prom_is_rex(magic))
                rex_clear_cache();
 
        if (prom_is_rex(magic))
                rex_clear_cache();
 

-       /* Register the early console.  */
+       /* Register the early console.  */

        register_prom_console();
 
        /* Were we compiled with the right CPU option? */
        register_prom_console();
 
        /* Were we compiled with the right CPU option? */

diff --git a/arch/mips/dec/prom/memory.c b/arch/mips/dec/prom/memory.c
index 8c62316f22f438b4b9cc18b23585f3e0ad8b7258..0aadac74290031dffd4d49a3d80de9054118e93a 100644 (file)
--- a/arch/mips/dec/prom/memory.c
+++ b/arch/mips/dec/prom/memory.c
@@ -22,7 +22,7 @@ volatile unsigned long mem_err;               /* So we know an error occurred */
 
 /*
  * Probe memory in 4MB chunks, waiting for an error to tell us we've fallen
 
 /*
  * Probe memory in 4MB chunks, waiting for an error to tell us we've fallen

- * off the end of real memory.  Only suitable for the 2100/3100's (PMAX).
+ * off the end of real memory. Only suitable for the 2100/3100's (PMAX).

  */
 
 #define CHUNK_SIZE 0x400000
  */
 
 #define CHUNK_SIZE 0x400000

diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index b874accd878a7cc33bfea390526e8f67340765de..741cb4235bde2106e2e152bcd1caa2ca63c020b9 100644 (file)
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -65,7 +65,7 @@ EXPORT_SYMBOL(ioasic_base);
 /*
  * IRQ routing and priority tables.  Priorites are set as follows:
  *
 /*
  * IRQ routing and priority tables.  Priorites are set as follows:
  *

- *             KN01    KN230   KN02    KN02-BA KN02-CA KN03
+ *             KN01    KN230   KN02    KN02-BA KN02-CA KN03

  *
  * MEMORY      CPU     CPU     CPU     ASIC    CPU     CPU
  * RTC         CPU     CPU     CPU     ASIC    CPU     CPU
  *
  * MEMORY      CPU     CPU     CPU     ASIC    CPU     CPU
  * RTC         CPU     CPU     CPU     ASIC    CPU     CPU


@@ -413,7 +413,7 @@ static void __init dec_init_kn02(void)
 
 /*
  * Machine-specific initialisation for KN02-BA, aka DS5000/1xx
 
 /*
  * Machine-specific initialisation for KN02-BA, aka DS5000/1xx

- * (xx = 20, 25, 33), aka 3min.  Also applies to KN04(-BA), aka
+ * (xx = 20, 25, 33), aka 3min.         Also applies to KN04(-BA), aka

  * DS5000/150, aka 4min.
  */
 static int kn02ba_interrupt[DEC_NR_INTS] __initdata = {
  * DS5000/150, aka 4min.
  */
 static int kn02ba_interrupt[DEC_NR_INTS] __initdata = {

diff --git a/arch/mips/dec/wbflush.c b/arch/mips/dec/wbflush.c
index 43feddd5e19c307685bae54bf499793aae331b41..56bda4a396b5c112e8563bef2b440697a58f5deb 100644 (file)
--- a/arch/mips/dec/wbflush.c
+++ b/arch/mips/dec/wbflush.c
@@ -2,9 +2,9 @@
  * Setup the right wbflush routine for the different DECstations.
  *
  * Created with information from:
  * Setup the right wbflush routine for the different DECstations.
  *
  * Created with information from:

- *      DECstation 3100 Desktop Workstation Functional Specification
- *      DECstation 5000/200 KN02 System Module Functional Specification
- *      mipsel-linux-objdump --disassemble vmunix | grep "wbflush" :-)
+ *     DECstation 3100 Desktop Workstation Functional Specification
+ *     DECstation 5000/200 KN02 System Module Functional Specification
+ *     mipsel-linux-objdump --disassemble vmunix | grep "wbflush" :-)

  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive

diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c
index b5f08255d9c73411d2b9bc0e01653e8c3d6e1909..b880a83e4d4e93b832d3349b838a96869ae4cf60 100644 (file)
--- a/arch/mips/emma/markeins/irq.c
+++ b/arch/mips/emma/markeins/irq.c
@@ -292,7 +292,7 @@ void __init arch_init_irq(void)
 
 asmlinkage void plat_irq_dispatch(void)
 {
 
 asmlinkage void plat_irq_dispatch(void)
 {

-        unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
+       unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;

 
        if (pending & STATUSF_IP7)
                do_IRQ(MIPS_CPU_IRQ_BASE + 7);
 
        if (pending & STATUSF_IP7)
                do_IRQ(MIPS_CPU_IRQ_BASE + 7);

diff --git a/arch/mips/emma/markeins/platform.c b/arch/mips/emma/markeins/platform.c
index b05b08b92a3466f8745e0d283f123e4ede1000ff..99ea004730a77da64d17ab1544a3bb58a901a3b5 100644 (file)
--- a/arch/mips/emma/markeins/platform.c
+++ b/arch/mips/emma/markeins/platform.c
@@ -190,7 +190,7 @@ static struct platform_device markeins_flash_device = {
        .name           = "physmap-flash",
        .id             = 0,
        .dev            = {
        .name           = "physmap-flash",
        .id             = 0,
        .dev            = {

-               .platform_data  = &markeins_flash_data,
+               .platform_data  = &markeins_flash_data,

        },
        .num_resources  = 1,
        .resource       = &markeins_flash_resource,
        },
        .num_resources  = 1,
        .resource       = &markeins_flash_resource,

diff --git a/arch/mips/emma/markeins/setup.c b/arch/mips/emma/markeins/setup.c
index feceebcfff4269bd9d740749d080aae7831673ba..d71005835c007aeb8df0f8b288fbfb1f3045457d 100644 (file)
--- a/arch/mips/emma/markeins/setup.c
+++ b/arch/mips/emma/markeins/setup.c
@@ -28,7 +28,7 @@
 
 #include <asm/emma/emma2rh.h>
 
 
 #include <asm/emma/emma2rh.h>
 

-#define        USE_CPU_COUNTER_TIMER   /* whether we use cpu counter */
+#define USE_CPU_COUNTER_TIMER  /* whether we use cpu counter */

 
 extern void markeins_led(const char *);
 
 
 extern void markeins_led(const char *);
 

diff --git a/arch/mips/fw/arc/file.c b/arch/mips/fw/arc/file.c
index 30335341b44750786bdde99226823f4be4d8801b..a8b08032348fb5a9a37b1dc57da504301f4235c6 100644 (file)
--- a/arch/mips/fw/arc/file.c
+++ b/arch/mips/fw/arc/file.c
@@ -15,7 +15,7 @@
 
 LONG
 ArcGetDirectoryEntry(ULONG FileID, struct linux_vdirent *Buffer,
 
 LONG
 ArcGetDirectoryEntry(ULONG FileID, struct linux_vdirent *Buffer,

-                     ULONG N, ULONG *Count)
+                    ULONG N, ULONG *Count)

 {
        return ARC_CALL4(get_vdirent, FileID, Buffer, N, Count);
 }
 {
        return ARC_CALL4(get_vdirent, FileID, Buffer, N, Count);
 }


@@ -69,7 +69,7 @@ ArcGetFileInformation(ULONG FileID, struct linux_finfo *Information)
 }
 
 LONG ArcSetFileInformation(ULONG FileID, ULONG AttributeFlags,
 }
 
 LONG ArcSetFileInformation(ULONG FileID, ULONG AttributeFlags,

-                           ULONG AttributeMask)
+                          ULONG AttributeMask)

 {
        return ARC_CALL3(set_finfo, FileID, AttributeFlags, AttributeMask);
 }
 {
        return ARC_CALL3(set_finfo, FileID, AttributeFlags, AttributeMask);
 }

diff --git a/arch/mips/fw/arc/identify.c b/arch/mips/fw/arc/identify.c
index 54a33c756f612dc3bf87432278cc79385ba37cae..f90266c02c9d4f6a0ce55c290481003bfe720fde 100644 (file)
--- a/arch/mips/fw/arc/identify.c
+++ b/arch/mips/fw/arc/identify.c
@@ -100,7 +100,7 @@ void __init prom_identify_arch(void)
        if (p == NULL) {
 #ifdef CONFIG_SGI_IP27
                /* IP27 PROM misbehaves, seems to not implement ARC
        if (p == NULL) {
 #ifdef CONFIG_SGI_IP27
                /* IP27 PROM misbehaves, seems to not implement ARC

-                  GetChild().  So we just assume it's an IP27.  */
+                  GetChild().  So we just assume it's an IP27.  */

                iname = "SGI-IP27";
 #else
                iname = "Unknown";
                iname = "SGI-IP27";
 #else
                iname = "Unknown";

diff --git a/arch/mips/fw/arc/memory.c b/arch/mips/fw/arc/memory.c
index 8b8eea2b6cf6f1a0699736667d7531832cd2d4ad..5537b94572b2d29f8da730d96bef202744779e32 100644 (file)
--- a/arch/mips/fw/arc/memory.c
+++ b/arch/mips/fw/arc/memory.c
@@ -1,6 +1,6 @@
 /*
  * memory.c: PROM library functions for acquiring/using memory descriptors
 /*
  * memory.c: PROM library functions for acquiring/using memory descriptors

- *           given to us from the ARCS firmware.
+ *          given to us from the ARCS firmware.

  *
  * Copyright (C) 1996 by David S. Miller
  * Copyright (C) 1999, 2000, 2001 by Ralf Baechle
  *
  * Copyright (C) 1996 by David S. Miller
  * Copyright (C) 1999, 2000, 2001 by Ralf Baechle

diff --git a/arch/mips/fw/arc/promlib.c b/arch/mips/fw/arc/promlib.c
index b7f9dd3c93c672cc67d897efd12c36c31cc914f5..7e8ba5ce95be0778c958d2772a2015e0450aaf85 100644 (file)
--- a/arch/mips/fw/arc/promlib.c
+++ b/arch/mips/fw/arc/promlib.c
@@ -11,7 +11,7 @@
 #include <asm/bcache.h>
 
 /*
 #include <asm/bcache.h>
 
 /*

- * IP22 boardcache is not compatible with board caches.  Thus we disable it
+ * IP22 boardcache is not compatible with board caches.         Thus we disable it

  * during romvec action.  Since r4xx0.c is always compiled and linked with your
  * kernel, this shouldn't cause any harm regardless what MIPS processor you
  * have.
  * during romvec action.  Since r4xx0.c is always compiled and linked with your
  * kernel, this shouldn't cause any harm regardless what MIPS processor you
  * have.

diff --git a/arch/mips/fw/lib/call_o32.S b/arch/mips/fw/lib/call_o32.S
index e0a68713b3c3ee0f07cda100fcfb79146f311324..b308b2a0613e210c1f7b068dfc6a7589f1ad2afb 100644 (file)
--- a/arch/mips/fw/lib/call_o32.S
+++ b/arch/mips/fw/lib/call_o32.S
@@ -14,7 +14,7 @@
 
 /* Maximum number of arguments supported.  Must be even!  */
 #define O32_ARGC       32
 
 /* Maximum number of arguments supported.  Must be even!  */
 #define O32_ARGC       32

-/* Number of static registers we save.  */
+/* Number of static registers we save. */

 #define O32_STATC      11
 /* Frame size for static register  */
 #define O32_FRAMESZ    (SZREG * O32_STATC)
 #define O32_STATC      11
 /* Frame size for static register  */
 #define O32_FRAMESZ    (SZREG * O32_STATC)

diff --git a/arch/mips/fw/sni/sniprom.c b/arch/mips/fw/sni/sniprom.c
index 96ba99202758a9c1609f9096e2025fefab4c083c..2c2cb182af4edd8673dc54c00c39aded85a6ed30 100644 (file)
--- a/arch/mips/fw/sni/sniprom.c
+++ b/arch/mips/fw/sni/sniprom.c
@@ -28,20 +28,20 @@
  * registers
  */
 #define PROM_GET_MEMCONF       58
  * registers
  */
 #define PROM_GET_MEMCONF       58

-#define PROM_GET_HWCONF         61
+#define PROM_GET_HWCONF                61

 
 #define PROM_VEC               (u64 *)CKSEG1ADDR(0x1fc00000)
 #define PROM_ENTRY(x)          (PROM_VEC + (x))
 
 
 #define PROM_VEC               (u64 *)CKSEG1ADDR(0x1fc00000)
 #define PROM_ENTRY(x)          (PROM_VEC + (x))
 

-#define ___prom_putchar         ((int *(*)(int))PROM_ENTRY(PROM_PUTCHAR))
-#define ___prom_getenv          ((char *(*)(char *))PROM_ENTRY(PROM_GETENV))
-#define ___prom_get_memconf     ((void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF))
-#define ___prom_get_hwconf      ((u32 (*)(void))PROM_ENTRY(PROM_GET_HWCONF))
+#define ___prom_putchar                ((int *(*)(int))PROM_ENTRY(PROM_PUTCHAR))
+#define ___prom_getenv         ((char *(*)(char *))PROM_ENTRY(PROM_GETENV))
+#define ___prom_get_memconf    ((void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF))
+#define ___prom_get_hwconf     ((u32 (*)(void))PROM_ENTRY(PROM_GET_HWCONF))

 
 #ifdef CONFIG_64BIT
 
 static u8 o32_stk[16384];
 
 #ifdef CONFIG_64BIT
 
 static u8 o32_stk[16384];

-#define O32_STK   &o32_stk[sizeof(o32_stk)]
+#define O32_STK          &o32_stk[sizeof(o32_stk)]

 
 #define __PROM_O32(fun, arg) fun arg __asm__(#fun); \
                                     __asm__(#fun " = call_o32")
 
 #define __PROM_O32(fun, arg) fun arg __asm__(#fun); \
                                     __asm__(#fun " = call_o32")


@@ -52,13 +52,13 @@ void  __PROM_O32(__prom_get_memconf, (void (*)(void *), void *, void *));
 u32   __PROM_O32(__prom_get_hwconf, (u32 (*)(void), void *));
 
 #define _prom_putchar(x)     __prom_putchar(___prom_putchar, O32_STK, x)
 u32   __PROM_O32(__prom_get_hwconf, (u32 (*)(void), void *));
 
 #define _prom_putchar(x)     __prom_putchar(___prom_putchar, O32_STK, x)

-#define _prom_getenv(x)      __prom_getenv(___prom_getenv, O32_STK, x)
+#define _prom_getenv(x)             __prom_getenv(___prom_getenv, O32_STK, x)

 #define _prom_get_memconf(x) __prom_get_memconf(___prom_get_memconf, O32_STK, x)
 #define _prom_get_hwconf()   __prom_get_hwconf(___prom_get_hwconf, O32_STK)
 
 #else
 #define _prom_putchar(x)     ___prom_putchar(x)
 #define _prom_get_memconf(x) __prom_get_memconf(___prom_get_memconf, O32_STK, x)
 #define _prom_get_hwconf()   __prom_get_hwconf(___prom_get_hwconf, O32_STK)
 
 #else
 #define _prom_putchar(x)     ___prom_putchar(x)

-#define _prom_getenv(x)      ___prom_getenv(x)
+#define _prom_getenv(x)             ___prom_getenv(x)

 #define _prom_get_memconf(x) ___prom_get_memconf(x)
 #define _prom_get_hwconf(x)  ___prom_get_hwconf(x)
 #endif
 #define _prom_get_memconf(x) ___prom_get_memconf(x)
 #define _prom_get_hwconf(x)  ___prom_get_hwconf(x)
 #endif

diff --git a/arch/mips/include/asm/abi.h b/arch/mips/include/asm/abi.h
index 9252d9b50e592c6df959f24bf90facd247c34a43..909bb69848666dafbd0f48e2ca32ada5cf2de60f 100644 (file)
--- a/arch/mips/include/asm/abi.h
+++ b/arch/mips/include/asm/abi.h
@@ -14,12 +14,12 @@
 
 struct mips_abi {
        int (* const setup_frame)(void *sig_return, struct k_sigaction *ka,
 
 struct mips_abi {
        int (* const setup_frame)(void *sig_return, struct k_sigaction *ka,

-                                 struct pt_regs *regs, int signr,
-                                 sigset_t *set);
+                                 struct pt_regs *regs, int signr,
+                                 sigset_t *set);

        const unsigned long     signal_return_offset;
        int (* const setup_rt_frame)(void *sig_return, struct k_sigaction *ka,
        const unsigned long     signal_return_offset;
        int (* const setup_rt_frame)(void *sig_return, struct k_sigaction *ka,

-                              struct pt_regs *regs, int signr,
-                              sigset_t *set, siginfo_t *info);
+                              struct pt_regs *regs, int signr,
+                              sigset_t *set, siginfo_t *info);

        const unsigned long     rt_signal_return_offset;
        const unsigned long     restart;
 };
        const unsigned long     rt_signal_return_offset;
        const unsigned long     restart;
 };

diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index 569f80aacbd2f0479bfb9f2cea2239afb7985dc8..13d61c002e4fc329ec6de191c31d43afb9020885 100644 (file)
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -51,14 +51,14 @@
  * Returns the physical address of a CKSEGx / XKPHYS address
  */
 #define CPHYSADDR(a)           ((_ACAST32_(a)) & 0x1fffffff)
  * Returns the physical address of a CKSEGx / XKPHYS address
  */
 #define CPHYSADDR(a)           ((_ACAST32_(a)) & 0x1fffffff)

-#define XPHYSADDR(a)            ((_ACAST64_(a)) &                      \
+#define XPHYSADDR(a)           ((_ACAST64_(a)) &                       \

                                 _CONST64_(0x000000ffffffffff))
 
 #ifdef CONFIG_64BIT
 
 /*
  * Memory segments (64bit kernel mode addresses)
                                 _CONST64_(0x000000ffffffffff))
 
 #ifdef CONFIG_64BIT
 
 /*
  * Memory segments (64bit kernel mode addresses)

- * The compatibility segments use the full 64-bit sign extended value.  Note
+ * The compatibility segments use the full 64-bit sign extended value. Note

  * the R8000 doesn't have them so don't reference these in generic MIPS code.
  */
 #define XKUSEG                 _CONST64_(0x0000000000000000)
  * the R8000 doesn't have them so don't reference these in generic MIPS code.
  */
 #define XKUSEG                 _CONST64_(0x0000000000000000)


@@ -131,7 +131,7 @@
 
 /*
  * The ultimate limited of the 64-bit MIPS architecture:  2 bits for selecting
 
 /*
  * The ultimate limited of the 64-bit MIPS architecture:  2 bits for selecting

- * the region, 3 bits for the CCA mode.  This leaves 59 bits of which the
+ * the region, 3 bits for the CCA mode.         This leaves 59 bits of which the

  * R8000 implements most with its 48-bit physical address space.
  */
 #define TO_PHYS_MASK   _CONST64_(0x07ffffffffffffff)   /* 2^^59 - 1 */
  * R8000 implements most with its 48-bit physical address space.
  */
 #define TO_PHYS_MASK   _CONST64_(0x07ffffffffffffff)   /* 2^^59 - 1 */

diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index 608cfcfbb3eaad36da1e19f539bb3efa5084cfef..164a21e65b421de9b7265a1bd403a3895e8092c7 100644 (file)
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -33,12 +33,12 @@
  * Not used for the kernel but here seems to be the right place.
  */
 #ifdef __PIC__
  * Not used for the kernel but here seems to be the right place.
  */
 #ifdef __PIC__

-#define CPRESTORE(register)                             \
+#define CPRESTORE(register)                            \

                .cprestore register
                .cprestore register

-#define CPADD(register)                                 \
+#define CPADD(register)                                        \

                .cpadd  register
                .cpadd  register

-#define CPLOAD(register)                                \
-               .cpload register
+#define CPLOAD(register)                               \
+               .cpload register

 #else
 #define CPRESTORE(register)
 #define CPADD(register)
 #else
 #define CPRESTORE(register)
 #define CPADD(register)


@@ -48,35 +48,35 @@
 /*
  * LEAF - declare leaf routine
  */
 /*
  * LEAF - declare leaf routine
  */

-#define        LEAF(symbol)                                    \
-               .globl  symbol;                         \
-               .align  2;                              \
-               .type   symbol, @function;              \
-               .ent    symbol, 0;                      \
+#define LEAF(symbol)                                   \
+               .globl  symbol;                         \
+               .align  2;                              \
+               .type   symbol, @function;              \
+               .ent    symbol, 0;                      \

 symbol:                .frame  sp, 0, ra
 
 /*
  * NESTED - declare nested routine entry point
  */
 symbol:                .frame  sp, 0, ra
 
 /*
  * NESTED - declare nested routine entry point
  */

-#define        NESTED(symbol, framesize, rpc)                  \
-               .globl  symbol;                         \
-               .align  2;                              \
-               .type   symbol, @function;              \
-               .ent    symbol, 0;                       \
+#define NESTED(symbol, framesize, rpc)                 \
+               .globl  symbol;                         \
+               .align  2;                              \
+               .type   symbol, @function;              \
+               .ent    symbol, 0;                       \

 symbol:                .frame  sp, framesize, rpc
 
 /*
  * END - mark end of function
  */
 symbol:                .frame  sp, framesize, rpc
 
 /*
  * END - mark end of function
  */

-#define        END(function)                                   \
-               .end    function;                       \
+#define END(function)                                  \
+               .end    function;                       \

                .size   function, .-function
 
 /*
  * EXPORT - export definition of symbol
  */
 #define EXPORT(symbol)                                 \
                .size   function, .-function
 
 /*
  * EXPORT - export definition of symbol
  */
 #define EXPORT(symbol)                                 \

-               .globl  symbol;                         \
+               .globl  symbol;                         \

 symbol:
 
 /*
 symbol:
 
 /*


@@ -90,16 +90,16 @@ symbol:
 /*
  * ABS - export absolute symbol
  */
 /*
  * ABS - export absolute symbol
  */

-#define        ABS(symbol,value)                               \
-               .globl  symbol;                         \
+#define ABS(symbol,value)                              \
+               .globl  symbol;                         \

 symbol         =       value
 
 symbol         =       value
 

-#define        PANIC(msg)                                      \
+#define PANIC(msg)                                     \

                .set    push;                           \
                .set    push;                           \

-               .set    reorder;                        \
-               PTR_LA  a0, 8f;                          \
-               jal     panic;                          \
-9:             b       9b;                             \
+               .set    reorder;                        \
+               PTR_LA  a0, 8f;                          \
+               jal     panic;                          \
+9:             b       9b;                             \

                .set    pop;                            \
                TEXT(msg)
 
                .set    pop;                            \
                TEXT(msg)
 


@@ -107,31 +107,31 @@ symbol            =       value
  * Print formatted string
  */
 #ifdef CONFIG_PRINTK
  * Print formatted string
  */
 #ifdef CONFIG_PRINTK

-#define PRINT(string)                                   \
+#define PRINT(string)                                  \

                .set    push;                           \
                .set    push;                           \

-               .set    reorder;                        \
-               PTR_LA  a0, 8f;                          \
-               jal     printk;                         \
+               .set    reorder;                        \
+               PTR_LA  a0, 8f;                          \
+               jal     printk;                         \

                .set    pop;                            \
                TEXT(string)
 #else
 #define PRINT(string)
 #endif
 
                .set    pop;                            \
                TEXT(string)
 #else
 #define PRINT(string)
 #endif
 

-#define        TEXT(msg)                                       \
+#define TEXT(msg)                                      \

                .pushsection .data;                     \
                .pushsection .data;                     \

-8:             .asciiz msg;                            \
+8:             .asciiz msg;                            \

                .popsection;
 
 /*
  * Build text tables
  */
                .popsection;
 
 /*
  * Build text tables
  */

-#define TTABLE(string)                                  \
+#define TTABLE(string)                                 \

                .pushsection .text;                     \
                .pushsection .text;                     \

-               .word   1f;                             \
+               .word   1f;                             \

                .popsection                             \
                .pushsection .data;                     \
                .popsection                             \
                .pushsection .data;                     \

-1:             .asciiz string;                         \
+1:             .asciiz string;                         \

                .popsection
 
 /*
                .popsection
 
 /*


@@ -143,13 +143,13 @@ symbol            =       value
  */
 #ifdef CONFIG_CPU_HAS_PREFETCH
 
  */
 #ifdef CONFIG_CPU_HAS_PREFETCH
 

-#define PREF(hint,addr)                                 \
+#define PREF(hint,addr)                                        \

                .set    push;                           \
                .set    mips4;                          \
                pref    hint, addr;                     \
                .set    pop
 
                .set    push;                           \
                .set    mips4;                          \
                pref    hint, addr;                     \
                .set    pop
 

-#define PREFX(hint,addr)                                \
+#define PREFX(hint,addr)                               \

                .set    push;                           \
                .set    mips4;                          \
                prefx   hint, addr;                     \
                .set    push;                           \
                .set    mips4;                          \
                prefx   hint, addr;                     \


@@ -166,42 +166,42 @@ symbol            =       value
  * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
  */
 #if (_MIPS_ISA == _MIPS_ISA_MIPS1)
  * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
  */
 #if (_MIPS_ISA == _MIPS_ISA_MIPS1)

-#define MOVN(rd, rs, rt)                                \
+#define MOVN(rd, rs, rt)                               \

                .set    push;                           \
                .set    reorder;                        \
                .set    push;                           \
                .set    reorder;                        \

-               beqz    rt, 9f;                         \
-               move    rd, rs;                         \
+               beqz    rt, 9f;                         \
+               move    rd, rs;                         \

                .set    pop;                            \
 9:
                .set    pop;                            \
 9:

-#define MOVZ(rd, rs, rt)                                \
+#define MOVZ(rd, rs, rt)                               \

                .set    push;                           \
                .set    reorder;                        \
                .set    push;                           \
                .set    reorder;                        \

-               bnez    rt, 9f;                         \
-               move    rd, rs;                         \
+               bnez    rt, 9f;                         \
+               move    rd, rs;                         \

                .set    pop;                            \
 9:
 #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
 #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
                .set    pop;                            \
 9:
 #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
 #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)

-#define MOVN(rd, rs, rt)                                \
+#define MOVN(rd, rs, rt)                               \

                .set    push;                           \
                .set    noreorder;                      \
                .set    push;                           \
                .set    noreorder;                      \

-               bnezl   rt, 9f;                         \
-                move   rd, rs;                         \
+               bnezl   rt, 9f;                         \
+                move   rd, rs;                         \

                .set    pop;                            \
 9:
                .set    pop;                            \
 9:

-#define MOVZ(rd, rs, rt)                                \
+#define MOVZ(rd, rs, rt)                               \

                .set    push;                           \
                .set    noreorder;                      \
                .set    push;                           \
                .set    noreorder;                      \

-               beqzl   rt, 9f;                         \
-                move   rd, rs;                         \
+               beqzl   rt, 9f;                         \
+                move   rd, rs;                         \

                .set    pop;                            \
 9:
 #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
 #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
     (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
                .set    pop;                            \
 9:
 #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
 #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
     (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)

-#define MOVN(rd, rs, rt)                                \
+#define MOVN(rd, rs, rt)                               \

                movn    rd, rs, rt
                movn    rd, rs, rt

-#define MOVZ(rd, rs, rt)                                \
+#define MOVZ(rd, rs, rt)                               \

                movz    rd, rs, rt
 #endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
 
                movz    rd, rs, rt
 #endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
 

diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h
index 01cc6ba64831f6973d2fb673a66f385612ea809d..08b607969a16978055f2b5e5cd1bf833fb8a4618 100644 (file)
--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -1,5 +1,5 @@
 /*
 /*

- * Atomic operations that C can't guarantee us.  Useful for
+ * Atomic operations that C can't guarantee us.         Useful for

  * resource counting etc..
  *
  * But use these as seldom as possible since they are much more slower
  * resource counting etc..
  *
  * But use these as seldom as possible since they are much more slower


@@ -21,7 +21,7 @@
 #include <asm/cmpxchg.h>
 #include <asm/war.h>
 
 #include <asm/cmpxchg.h>
 #include <asm/war.h>
 

-#define ATOMIC_INIT(i)    { (i) }
+#define ATOMIC_INIT(i)   { (i) }

 
 /*
  * atomic_read - read atomic variable
 
 /*
  * atomic_read - read atomic variable

diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
index f7fdc24e972da152ddadaa526f83aaba8bcc0f8b..314ab5532019603545add2b96249d98397d0c08e 100644 (file)
--- a/arch/mips/include/asm/barrier.h
+++ b/arch/mips/include/asm/barrier.h
@@ -18,7 +18,7 @@
  * over this barrier.  All reads preceding this primitive are guaranteed
  * to access memory (but not necessarily other CPUs' caches) before any
  * reads following this primitive that depend on the data return by
  * over this barrier.  All reads preceding this primitive are guaranteed
  * to access memory (but not necessarily other CPUs' caches) before any
  * reads following this primitive that depend on the data return by

- * any of the preceding reads.  This primitive is much lighter weight than
+ * any of the preceding reads. This primitive is much lighter weight than

  * rmb() on most CPUs, and is never heavier weight than is
  * rmb().
  *
  * rmb() on most CPUs, and is never heavier weight than is
  * rmb().
  *


@@ -43,7 +43,7 @@
  * </programlisting>
  *
  * because the read of "*q" depends on the read of "p" and these
  * </programlisting>
  *
  * because the read of "*q" depends on the read of "p" and these

- * two reads are separated by a read_barrier_depends().  However,
+ * two reads are separated by a read_barrier_depends().         However,

  * the following code, with the same initial values for "a" and "b":
  *
  * <programlisting>
  * the following code, with the same initial values for "a" and "b":
  *
  * <programlisting>


@@ -57,7 +57,7 @@
  * </programlisting>
  *
  * does not enforce ordering, since there is no data dependency between
  * </programlisting>
  *
  * does not enforce ordering, since there is no data dependency between

- * the read of "a" and the read of "b".  Therefore, on some CPUs, such
+ * the read of "a" and the read of "b".         Therefore, on some CPUs, such

  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
  * in cases like this where there are no data dependencies.
  */
  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
  * in cases like this where there are no data dependencies.
  */


@@ -92,7 +92,7 @@
                : "memory")
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 # define OCTEON_SYNCW_STR      ".set push\n.set arch=octeon\nsyncw\nsyncw\n.set pop\n"
                : "memory")
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 # define OCTEON_SYNCW_STR      ".set push\n.set arch=octeon\nsyncw\nsyncw\n.set pop\n"

-# define __syncw()     __asm__ __volatile__(OCTEON_SYNCW_STR : : : "memory")
+# define __syncw()     __asm__ __volatile__(OCTEON_SYNCW_STR : : : "memory")

 
 # define fast_wmb()    __syncw()
 # define fast_rmb()    barrier()
 
 # define fast_wmb()    __syncw()
 # define fast_rmb()    barrier()


@@ -158,7 +158,7 @@
 #endif
 
 #if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
 #endif
 
 #if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)

-#define __WEAK_LLSC_MB         "       sync    \n"
+#define __WEAK_LLSC_MB         "       sync    \n"

 #else
 #define __WEAK_LLSC_MB         "               \n"
 #endif
 #else
 #define __WEAK_LLSC_MB         "               \n"
 #endif

diff --git a/arch/mips/include/asm/bcache.h b/arch/mips/include/asm/bcache.h
index 0ba9d6ef76a7feb5342d37639fa6721302bf026c..8c34484cea827f516591dd9f3c775d36e81fac7b 100644 (file)
--- a/arch/mips/include/asm/bcache.h
+++ b/arch/mips/include/asm/bcache.h
@@ -11,7 +11,7 @@
 
 
 /* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
 
 
 /* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,

-   chipset implemented caches.  On machines with other CPUs the CPU does the
+   chipset implemented caches. On machines with other CPUs the CPU does the

    cache thing itself. */
 struct bcache_ops {
        void (*bc_enable)(void);
    cache thing itself. */
 struct bcache_ops {
        void (*bc_enable)(void);

diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 46ac73abd5ee950b2bd14e57ad07d1b08ff7e010..71305a8b3d78b8053b46a78d63f332cffc3a95db 100644 (file)
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -26,15 +26,15 @@
 #define SZLONG_MASK 31UL
 #define __LL           "ll     "
 #define __SC           "sc     "
 #define SZLONG_MASK 31UL
 #define __LL           "ll     "
 #define __SC           "sc     "

-#define __INS          "ins    "
-#define __EXT          "ext    "
+#define __INS          "ins    "
+#define __EXT          "ext    "

 #elif _MIPS_SZLONG == 64
 #define SZLONG_LOG 6
 #define SZLONG_MASK 63UL
 #define __LL           "lld    "
 #define __SC           "scd    "
 #elif _MIPS_SZLONG == 64
 #define SZLONG_LOG 6
 #define SZLONG_MASK 63UL
 #define __LL           "lld    "
 #define __SC           "scd    "

-#define __INS          "dins    "
-#define __EXT          "dext    "
+#define __INS          "dins    "
+#define __EXT          "dext    "

 #endif
 
 /*
 #endif
 
 /*


@@ -357,7 +357,7 @@ static inline int test_and_clear_bit(unsigned long nr,
                "1:     " __LL  "%0, %1         # test_and_clear_bit    \n"
                "       or      %2, %0, %3                              \n"
                "       xor     %2, %3                                  \n"
                "1:     " __LL  "%0, %1         # test_and_clear_bit    \n"
                "       or      %2, %0, %3                              \n"
                "       xor     %2, %3                                  \n"

-               "       " __SC  "%2, %1                                 \n"
+               "       " __SC  "%2, %1                                 \n"

                "       beqzl   %2, 1b                                  \n"
                "       and     %2, %0, %3                              \n"
                "       .set    mips0                                   \n"
                "       beqzl   %2, 1b                                  \n"
                "       and     %2, %0, %3                              \n"
                "       .set    mips0                                   \n"


@@ -371,10 +371,10 @@ static inline int test_and_clear_bit(unsigned long nr,
 
                do {
                        __asm__ __volatile__(
 
                do {
                        __asm__ __volatile__(

-                       "       " __LL  "%0, %1 # test_and_clear_bit    \n"
+                       "       " __LL  "%0, %1 # test_and_clear_bit    \n"

                        "       " __EXT "%2, %0, %3, 1                  \n"
                        "       " __EXT "%2, %0, %3, 1                  \n"

-                       "       " __INS "%0, $0, %3, 1                  \n"
-                       "       " __SC  "%0, %1                         \n"
+                       "       " __INS "%0, $0, %3, 1                  \n"
+                       "       " __SC  "%0, %1                         \n"

                        : "=&r" (temp), "+m" (*m), "=&r" (res)
                        : "ir" (bit)
                        : "memory");
                        : "=&r" (temp), "+m" (*m), "=&r" (res)
                        : "ir" (bit)
                        : "memory");


@@ -387,10 +387,10 @@ static inline int test_and_clear_bit(unsigned long nr,
                do {
                        __asm__ __volatile__(
                        "       .set    mips3                           \n"
                do {
                        __asm__ __volatile__(
                        "       .set    mips3                           \n"

-                       "       " __LL  "%0, %1 # test_and_clear_bit    \n"
+                       "       " __LL  "%0, %1 # test_and_clear_bit    \n"

                        "       or      %2, %0, %3                      \n"
                        "       xor     %2, %3                          \n"
                        "       or      %2, %0, %3                      \n"
                        "       xor     %2, %3                          \n"

-                       "       " __SC  "%2, %1                         \n"
+                       "       " __SC  "%2, %1                         \n"

                        "       .set    mips0                           \n"
                        : "=&r" (temp), "+m" (*m), "=&r" (res)
                        : "r" (1UL << bit)
                        "       .set    mips0                           \n"
                        : "=&r" (temp), "+m" (*m), "=&r" (res)
                        : "r" (1UL << bit)


@@ -444,7 +444,7 @@ static inline int test_and_change_bit(unsigned long nr,
                do {
                        __asm__ __volatile__(
                        "       .set    mips3                           \n"
                do {
                        __asm__ __volatile__(
                        "       .set    mips3                           \n"

-                       "       " __LL  "%0, %1 # test_and_change_bit   \n"
+                       "       " __LL  "%0, %1 # test_and_change_bit   \n"

                        "       xor     %2, %0, %3                      \n"
                        "       " __SC  "\t%2, %1                       \n"
                        "       .set    mips0                           \n"
                        "       xor     %2, %0, %3                      \n"
                        "       " __SC  "\t%2, %1                       \n"
                        "       .set    mips0                           \n"

diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
index 7a51d879e6ca2180c448812b9bc1591f3020f678..b71dd5b160854a0e8f7fb54e4845af0ba535d748 100644 (file)
--- a/arch/mips/include/asm/bootinfo.h
+++ b/arch/mips/include/asm/bootinfo.h
@@ -44,19 +44,19 @@
 /*
  * Valid machtype for group PMC-MSP
  */
 /*
  * Valid machtype for group PMC-MSP
  */

-#define MACH_MSP4200_EVAL       0      /* PMC-Sierra MSP4200 Evaluation */
-#define MACH_MSP4200_GW         1      /* PMC-Sierra MSP4200 Gateway demo */
-#define MACH_MSP4200_FPGA       2      /* PMC-Sierra MSP4200 Emulation */
-#define MACH_MSP7120_EVAL       3      /* PMC-Sierra MSP7120 Evaluation */
-#define MACH_MSP7120_GW         4      /* PMC-Sierra MSP7120 Residential GW */
-#define MACH_MSP7120_FPGA       5      /* PMC-Sierra MSP7120 Emulation */
-#define MACH_MSP_OTHER        255      /* PMC-Sierra unknown board type */
+#define MACH_MSP4200_EVAL      0       /* PMC-Sierra MSP4200 Evaluation */
+#define MACH_MSP4200_GW                1       /* PMC-Sierra MSP4200 Gateway demo */
+#define MACH_MSP4200_FPGA      2       /* PMC-Sierra MSP4200 Emulation */
+#define MACH_MSP7120_EVAL      3       /* PMC-Sierra MSP7120 Evaluation */
+#define MACH_MSP7120_GW                4       /* PMC-Sierra MSP7120 Residential GW */
+#define MACH_MSP7120_FPGA      5       /* PMC-Sierra MSP7120 Emulation */
+#define MACH_MSP_OTHER       255       /* PMC-Sierra unknown board type */

 
 /*
  * Valid machtype for group Mikrotik
  */
 
 /*
  * Valid machtype for group Mikrotik
  */

-#define        MACH_MIKROTIK_RB532     0       /* Mikrotik RouterBoard 532     */
-#define MACH_MIKROTIK_RB532A   1       /* Mikrotik RouterBoard 532A    */
+#define MACH_MIKROTIK_RB532    0       /* Mikrotik RouterBoard 532     */
+#define MACH_MIKROTIK_RB532A   1       /* Mikrotik RouterBoard 532A    */

 
 /*
  * Valid machtype for Loongson family
 
 /*
  * Valid machtype for Loongson family


@@ -67,7 +67,7 @@
 #define MACH_LEMOTE_ML2F7      3
 #define MACH_LEMOTE_YL2F89     4
 #define MACH_DEXXON_GDIUM2F10  5
 #define MACH_LEMOTE_ML2F7      3
 #define MACH_LEMOTE_YL2F89     4
 #define MACH_DEXXON_GDIUM2F10  5

-#define MACH_LEMOTE_NAS        6
+#define MACH_LEMOTE_NAS               6

 #define MACH_LEMOTE_LL2F       7
 #define MACH_LOONGSON_END      8
 
 #define MACH_LEMOTE_LL2F       7
 #define MACH_LOONGSON_END      8
 

diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 8f99c11ab6657d8f8ab68a61155f01b1ff20bfdb..68f37e3eccc7f5032e98a7aa854eeceeb1783ace 100644 (file)
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -8,20 +8,20 @@
  * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
  * (C) Copyright 1999 Silicon Graphics, Inc.
  */
  * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
  * (C) Copyright 1999 Silicon Graphics, Inc.
  */

-#ifndef        __ASM_CACHEOPS_H
-#define        __ASM_CACHEOPS_H
+#ifndef __ASM_CACHEOPS_H
+#define __ASM_CACHEOPS_H

 
 /*
  * Cache Operations available on all MIPS processors with R4000-style caches
  */
 
 /*
  * Cache Operations available on all MIPS processors with R4000-style caches
  */

-#define Index_Invalidate_I      0x00
-#define Index_Writeback_Inv_D   0x01
+#define Index_Invalidate_I     0x00
+#define Index_Writeback_Inv_D  0x01

 #define Index_Load_Tag_I       0x04
 #define Index_Load_Tag_D       0x05
 #define Index_Store_Tag_I      0x08
 #define Index_Store_Tag_D      0x09
 #if defined(CONFIG_CPU_LOONGSON2)
 #define Index_Load_Tag_I       0x04
 #define Index_Load_Tag_D       0x05
 #define Index_Store_Tag_I      0x08
 #define Index_Store_Tag_D      0x09
 #if defined(CONFIG_CPU_LOONGSON2)

-#define Hit_Invalidate_I       0x00
+#define Hit_Invalidate_I       0x00

 #else
 #define Hit_Invalidate_I       0x10
 #endif
 #else
 #define Hit_Invalidate_I       0x10
 #endif


@@ -39,8 +39,8 @@
 /*
  * R4000SC and R4400SC-specific cacheops
  */
 /*
  * R4000SC and R4400SC-specific cacheops
  */

-#define Index_Invalidate_SI     0x02
-#define Index_Writeback_Inv_SD  0x03
+#define Index_Invalidate_SI    0x02
+#define Index_Writeback_Inv_SD 0x03

 #define Index_Load_Tag_SI      0x06
 #define Index_Load_Tag_SD      0x07
 #define Index_Store_Tag_SI     0x0A
 #define Index_Load_Tag_SI      0x06
 #define Index_Load_Tag_SD      0x07
 #define Index_Store_Tag_SI     0x0A

diff --git a/arch/mips/include/asm/checksum.h b/arch/mips/include/asm/checksum.h
index f2f7c6c264da38bbe409dba7c44b84c0bb5dd70f..ac3d2b8a20d4bfa483fcb55d57e92670c2c08dd2 100644 (file)
--- a/arch/mips/include/asm/checksum.h
+++ b/arch/mips/include/asm/checksum.h
@@ -194,7 +194,7 @@ static inline __sum16 ip_compute_csum(const void *buff, int len)
 
 #define _HAVE_ARCH_IPV6_CSUM
 static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
 
 #define _HAVE_ARCH_IPV6_CSUM
 static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,

-                                         const struct in6_addr *daddr,
+                                         const struct in6_addr *daddr,

                                          __u32 len, unsigned short proto,
                                          __wsum sum)
 {
                                          __u32 len, unsigned short proto,
                                          __wsum sum)
 {

diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index eee10dc07ac100defc6b0f00f6d8616da692e2c0..466069bd846596c4e2940be2f42a5aaa82830bec 100644 (file)
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -146,7 +146,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
                "       .set    push                            \n"     \
                "       .set    noat                            \n"     \
                "       .set    mips3                           \n"     \
                "       .set    push                            \n"     \
                "       .set    noat                            \n"     \
                "       .set    mips3                           \n"     \

-               "1:     " ld "  %0, %2          # __cmpxchg_asm \n"     \
+               "1:     " ld "  %0, %2          # __cmpxchg_asm \n"     \

                "       bne     %0, %z3, 2f                     \n"     \
                "       .set    mips0                           \n"     \
                "       move    $1, %z4                         \n"     \
                "       bne     %0, %z3, 2f                     \n"     \
                "       .set    mips0                           \n"     \
                "       move    $1, %z4                         \n"     \


@@ -163,7 +163,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
                "       .set    push                            \n"     \
                "       .set    noat                            \n"     \
                "       .set    mips3                           \n"     \
                "       .set    push                            \n"     \
                "       .set    noat                            \n"     \
                "       .set    mips3                           \n"     \

-               "1:     " ld "  %0, %2          # __cmpxchg_asm \n"     \
+               "1:     " ld "  %0, %2          # __cmpxchg_asm \n"     \

                "       bne     %0, %z3, 2f                     \n"     \
                "       .set    mips0                           \n"     \
                "       move    $1, %z4                         \n"     \
                "       bne     %0, %z3, 2f                     \n"     \
                "       .set    mips0                           \n"     \
                "       move    $1, %z4                         \n"     \


@@ -205,7 +205,7 @@ extern void __cmpxchg_called_with_bad_pointer(void);
                                                                        \
        switch (sizeof(*(__ptr))) {                                     \
        case 4:                                                         \
                                                                        \
        switch (sizeof(*(__ptr))) {                                     \
        case 4:                                                         \

-               __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); \
+               __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); \

                break;                                                  \
        case 8:                                                         \
                if (sizeof(long) == 8) {                                \
                break;                                                  \
        case 8:                                                         \
                if (sizeof(long) == 8) {                                \

diff --git a/arch/mips/include/asm/compat-signal.h b/arch/mips/include/asm/compat-signal.h
index 6599a901b63ea20733ad9decf8bbebcc7ee8d8bd..64e0b9343b8c395537604f68a7be06aaea5d757a 100644 (file)
--- a/arch/mips/include/asm/compat-signal.h
+++ b/arch/mips/include/asm/compat-signal.h
@@ -18,9 +18,9 @@ static inline int __copy_conv_sigset_to_user(compat_sigset_t __user *d,
        BUG_ON(sizeof(*d) != sizeof(*s));
        BUG_ON(_NSIG_WORDS != 2);
 
        BUG_ON(sizeof(*d) != sizeof(*s));
        BUG_ON(_NSIG_WORDS != 2);
 

-       err  = __put_user(s->sig[0],       &d->sig[0]);
+       err  = __put_user(s->sig[0],       &d->sig[0]);

        err |= __put_user(s->sig[0] >> 32, &d->sig[1]);
        err |= __put_user(s->sig[0] >> 32, &d->sig[1]);

-       err |= __put_user(s->sig[1],       &d->sig[2]);
+       err |= __put_user(s->sig[1],       &d->sig[2]);

        err |= __put_user(s->sig[1] >> 32, &d->sig[3]);
 
        return err;
        err |= __put_user(s->sig[1] >> 32, &d->sig[3]);
 
        return err;

diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h
index 3c5d1464b7bde4d93f5d4345fbedd31ccda7e47a..988477e492b31d7b88516f8408fbb8179c2cb0e7 100644 (file)
--- a/arch/mips/include/asm/compat.h
+++ b/arch/mips/include/asm/compat.h
@@ -120,7 +120,7 @@ struct compat_statfs {
 
 typedef u32            compat_old_sigset_t;    /* at least 32 bits */
 
 
 typedef u32            compat_old_sigset_t;    /* at least 32 bits */
 

-#define _COMPAT_NSIG           128             /* Don't ask !$@#% ...  */
+#define _COMPAT_NSIG           128             /* Don't ask !$@#% ...  */

 #define _COMPAT_NSIG_BPW       32
 
 typedef u32            compat_sigset_word;
 #define _COMPAT_NSIG_BPW       32
 
 typedef u32            compat_sigset_word;


@@ -168,7 +168,7 @@ typedef struct compat_siginfo {
                        s32 _addr; /* faulting insn/memory ref. */
                } _sigfault;
 
                        s32 _addr; /* faulting insn/memory ref. */
                } _sigfault;
 

-               /* SIGPOLL, SIGXFSZ (To do ...)  */
+               /* SIGPOLL, SIGXFSZ (To do ...)  */

                struct {
                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
                        int _fd;
                struct {
                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
                        int _fd;


@@ -179,7 +179,7 @@ typedef struct compat_siginfo {
                        timer_t _tid;           /* timer id */
                        int _overrun;           /* overrun count */
                        compat_sigval_t _sigval;/* same as below */
                        timer_t _tid;           /* timer id */
                        int _overrun;           /* overrun count */
                        compat_sigval_t _sigval;/* same as below */

-                       int _sys_private;       /* not to be passed to user */
+                       int _sys_private;       /* not to be passed to user */

                } _timer;
 
                /* POSIX.1b signals */
                } _timer;
 
                /* POSIX.1b signals */

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index c507b931b484c69913fc2aedc1a9a960b2b317d4..e0ac24759d92d3ba9f403dd6a57f50022a4748c3 100644 (file)
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -14,7 +14,7 @@
 #include <cpu-feature-overrides.h>
 
 #ifndef current_cpu_type
 #include <cpu-feature-overrides.h>
 
 #ifndef current_cpu_type

-#define current_cpu_type()      current_cpu_data.cputype
+#define current_cpu_type()     current_cpu_data.cputype

 #endif
 
 /*
 #endif
 
 /*


@@ -87,10 +87,10 @@
 #define cpu_has_mips16         (cpu_data[0].ases & MIPS_ASE_MIPS16)
 #endif
 #ifndef cpu_has_mdmx
 #define cpu_has_mips16         (cpu_data[0].ases & MIPS_ASE_MIPS16)
 #endif
 #ifndef cpu_has_mdmx

-#define cpu_has_mdmx           (cpu_data[0].ases & MIPS_ASE_MDMX)
+#define cpu_has_mdmx          (cpu_data[0].ases & MIPS_ASE_MDMX)

 #endif
 #ifndef cpu_has_mips3d
 #endif
 #ifndef cpu_has_mips3d

-#define cpu_has_mips3d         (cpu_data[0].ases & MIPS_ASE_MIPS3D)
+#define cpu_has_mips3d        (cpu_data[0].ases & MIPS_ASE_MIPS3D)

 #endif
 #ifndef cpu_has_smartmips
 #define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
 #endif
 #ifndef cpu_has_smartmips
 #define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)


@@ -108,11 +108,11 @@
 #define cpu_has_ic_fills_f_dc  (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
 #endif
 #ifndef cpu_has_pindexed_dcache
 #define cpu_has_ic_fills_f_dc  (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
 #endif
 #ifndef cpu_has_pindexed_dcache

-#define cpu_has_pindexed_dcache        (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
+#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)

 #endif
 
 /*
 #endif
 
 /*

- * I-Cache snoops remote store.  This only matters on SMP.  Some multiprocessors
+ * I-Cache snoops remote store.         This only matters on SMP.  Some multiprocessors

  * such as the R10000 have I-Caches that snoop local stores; the embedded ones
  * don't.  For maintaining I-cache coherency this means we need to flush the
  * D-cache all the way back to whever the I-cache does refills from, so the
  * such as the R10000 have I-Caches that snoop local stores; the embedded ones
  * don't.  For maintaining I-cache coherency this means we need to flush the
  * D-cache all the way back to whever the I-cache does refills from, so the


@@ -148,8 +148,8 @@
  */
 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)
  */
 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2)
 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2)

-#define cpu_has_mips_r1        (cpu_has_mips32r1 | cpu_has_mips64r1)
-#define cpu_has_mips_r2        (cpu_has_mips32r2 | cpu_has_mips64r2)
+#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
+#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)

 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
                         cpu_has_mips64r1 | cpu_has_mips64r2)
 
 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
                         cpu_has_mips64r1 | cpu_has_mips64r2)
 


@@ -159,7 +159,7 @@
 
 /*
  * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
 
 /*
  * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other

- * pre-MIPS32/MIPS53 processors have CLO, CLZ.  The IDT RC64574 is 64-bit and
+ * pre-MIPS32/MIPS53 processors have CLO, CLZ. The IDT RC64574 is 64-bit and

  * has CLO and CLZ but not DCLO nor DCLZ.  For 64-bit kernels
  * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
  */
  * has CLO and CLZ but not DCLO nor DCLZ.  For 64-bit kernels
  * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
  */


@@ -191,7 +191,7 @@
 # define cpu_has_64bits                (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
 # endif
 # ifndef cpu_has_64bit_zero_reg
 # define cpu_has_64bits                (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
 # endif
 # ifndef cpu_has_64bit_zero_reg

-# define cpu_has_64bit_zero_reg        (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
+# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)

 # endif
 # ifndef cpu_has_64bit_gp_regs
 # define cpu_has_64bit_gp_regs         0
 # endif
 # ifndef cpu_has_64bit_gp_regs
 # define cpu_has_64bit_gp_regs         0

diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index c454550eb0c07195874926969578c1367a6bd19b..41401d8eb7d1a3ca13bfbe77c7d78575307e3531 100644 (file)
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -52,14 +52,14 @@ struct cpuinfo_mips {
        unsigned int            cputype;
        int                     isa_level;
        int                     tlbsize;
        unsigned int            cputype;
        int                     isa_level;
        int                     tlbsize;

-       struct cache_desc       icache; /* Primary I-cache */
-       struct cache_desc       dcache; /* Primary D or combined I/D cache */
-       struct cache_desc       scache; /* Secondary cache */
-       struct cache_desc       tcache; /* Tertiary/split secondary cache */
-       int                     srsets; /* Shadow register sets */
+       struct cache_desc       icache; /* Primary I-cache */
+       struct cache_desc       dcache; /* Primary D or combined I/D cache */
+       struct cache_desc       scache; /* Secondary cache */
+       struct cache_desc       tcache; /* Tertiary/split secondary cache */
+       int                     srsets; /* Shadow register sets */

        int                     core;   /* physical core number */
 #ifdef CONFIG_64BIT
        int                     core;   /* physical core number */
 #ifdef CONFIG_64BIT

-       int                     vmbits; /* Virtual memory size in bits */
+       int                     vmbits; /* Virtual memory size in bits */

 #endif
 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
        /*
 #endif
 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
        /*


@@ -68,12 +68,12 @@ struct cpuinfo_mips {
         * exception resources, ASID spaces, etc, are common
         * to all TCs within the same VPE.
         */
         * exception resources, ASID spaces, etc, are common
         * to all TCs within the same VPE.
         */

-       int                     vpe_id;  /* Virtual Processor number */
+       int                     vpe_id;  /* Virtual Processor number */

 #endif
 #ifdef CONFIG_MIPS_MT_SMTC
 #endif
 #ifdef CONFIG_MIPS_MT_SMTC

-       int                     tc_id;   /* Thread Context number */
+       int                     tc_id;   /* Thread Context number */

 #endif
 #endif

-       void                    *data;  /* Additional data */
+       void                    *data;  /* Additional data */

        unsigned int            watch_reg_count;   /* Number that exist */
        unsigned int            watch_reg_use_cnt; /* Usable by ptrace */
 #define NUM_WATCH_REGS 4
        unsigned int            watch_reg_count;   /* Number that exist */
        unsigned int            watch_reg_use_cnt; /* Usable by ptrace */
 #define NUM_WATCH_REGS 4

diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 90112adb194082a1e41b945d45a7c7091962e3bc..9904697bd7921100b20b7238e0d446b799d31d16 100644 (file)
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -1,6 +1,6 @@
 /*
  * cpu.h: Values of the PRId register used to match up
 /*
  * cpu.h: Values of the PRId register used to match up

- *        various MIPS cpu types.
+ *       various MIPS cpu types.

  *
  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  * Copyright (C) 2004  Maciej W. Rozycki
  *
  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  * Copyright (C) 2004  Maciej W. Rozycki


@@ -9,14 +9,14 @@
 #define _ASM_CPU_H
 
 /* Assigned Company values for bits 23:16 of the PRId Register
 #define _ASM_CPU_H
 
 /* Assigned Company values for bits 23:16 of the PRId Register

-   (CP0 register 15, select 0).  As of the MIPS32 and MIPS64 specs from
+   (CP0 register 15, select 0).         As of the MIPS32 and MIPS64 specs from

    MTI, the PRId register is defined in this (backwards compatible)
    way:
 
   +----------------+----------------+----------------+----------------+
    MTI, the PRId register is defined in this (backwards compatible)
    way:
 
   +----------------+----------------+----------------+----------------+

-  | Company Options| Company ID     | Processor ID   | Revision       |
+  | Company Options| Company ID            | Processor ID   | Revision       |

   +----------------+----------------+----------------+----------------+
   +----------------+----------------+----------------+----------------+

-   31            24 23            16 15             8 7
+   31           24 23            16 15             8 7

 
    I don't have docs for all the previous processors, but my impression is
    that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
 
    I don't have docs for all the previous processors, but my impression is
    that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64


@@ -29,7 +29,7 @@
 #define PRID_COMP_ALCHEMY      0x030000
 #define PRID_COMP_SIBYTE       0x040000
 #define PRID_COMP_SANDCRAFT    0x050000
 #define PRID_COMP_ALCHEMY      0x030000
 #define PRID_COMP_SIBYTE       0x040000
 #define PRID_COMP_SANDCRAFT    0x050000

-#define PRID_COMP_NXP          0x060000
+#define PRID_COMP_NXP          0x060000

 #define PRID_COMP_TOSHIBA      0x070000
 #define PRID_COMP_LSI          0x080000
 #define PRID_COMP_LEXRA                0x0b0000
 #define PRID_COMP_TOSHIBA      0x070000
 #define PRID_COMP_LSI          0x080000
 #define PRID_COMP_LEXRA                0x0b0000


@@ -38,9 +38,9 @@
 #define PRID_COMP_INGENIC      0xd00000
 
 /*
 #define PRID_COMP_INGENIC      0xd00000
 
 /*

- * Assigned values for the product ID register.  In order to detect a
+ * Assigned values for the product ID register.         In order to detect a

  * certain CPU type exactly eventually additional registers may need to
  * certain CPU type exactly eventually additional registers may need to

- * be examined.  These are valid when 23:16 == PRID_COMP_LEGACY
+ * be examined.         These are valid when 23:16 == PRID_COMP_LEGACY

  */
 #define PRID_IMP_R2000         0x0100
 #define PRID_IMP_AU1_REV1      0x0100
  */
 #define PRID_IMP_R2000         0x0100
 #define PRID_IMP_AU1_REV1      0x0100


@@ -101,14 +101,14 @@
  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
  */
 
  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
  */
 

-#define PRID_IMP_SB1            0x0100
-#define PRID_IMP_SB1A           0x1100
+#define PRID_IMP_SB1           0x0100
+#define PRID_IMP_SB1A          0x1100

 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
  */
 
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
  */
 

-#define PRID_IMP_SR71000        0x0400
+#define PRID_IMP_SR71000       0x0400

 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM


@@ -145,7 +145,7 @@
  * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
  */
 
  * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
  */
 

-#define PRID_IMP_JZRISC        0x0200
+#define PRID_IMP_JZRISC               0x0200

 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC


@@ -188,9 +188,9 @@
 #define PRID_REV_R3000A                0x0030
 #define PRID_REV_R3000         0x0020
 #define PRID_REV_R2000A                0x0010
 #define PRID_REV_R3000A                0x0030
 #define PRID_REV_R3000         0x0020
 #define PRID_REV_R2000A                0x0010

-#define PRID_REV_TX3912        0x0010
-#define PRID_REV_TX3922        0x0030
-#define PRID_REV_TX3927        0x0040
+#define PRID_REV_TX3912                0x0010
+#define PRID_REV_TX3922                0x0030
+#define PRID_REV_TX3927                0x0040

 #define PRID_REV_VR4111                0x0050
 #define PRID_REV_VR4181                0x0050  /* Same as VR4111 */
 #define PRID_REV_VR4121                0x0060
 #define PRID_REV_VR4111                0x0050
 #define PRID_REV_VR4181                0x0050  /* Same as VR4111 */
 #define PRID_REV_VR4121                0x0060


@@ -217,9 +217,9 @@
  * FPU implementation/revision register (CP1 control register 0).
  *
  * +---------------------------------+----------------+----------------+
  * FPU implementation/revision register (CP1 control register 0).
  *
  * +---------------------------------+----------------+----------------+

- * | 0                               | Implementation | Revision       |
+ * | 0                              | Implementation | Revision       |

  * +---------------------------------+----------------+----------------+
  * +---------------------------------+----------------+----------------+

- *  31                             16 15             8 7              0
+ *  31                            16 15             8 7              0

  */
 
 #define FPIR_IMP_NONE          0x0000
  */
 
 #define FPIR_IMP_NONE          0x0000

diff --git a/arch/mips/include/asm/dec/ioasic_addrs.h b/arch/mips/include/asm/dec/ioasic_addrs.h
index 4cbc1f8a11292b6394f93dbbe692733b2a2909d9..a8665a7611c2af3141313c8f21ad32eeae128dc2 100644 (file)
--- a/arch/mips/include/asm/dec/ioasic_addrs.h
+++ b/arch/mips/include/asm/dec/ioasic_addrs.h
@@ -25,22 +25,22 @@
  */
 #define IOASIC_SYS_ROM (0*IOASIC_SLOT_SIZE)    /* system board ROM */
 #define IOASIC_IOCTL   (1*IOASIC_SLOT_SIZE)    /* I/O ASIC */
  */
 #define IOASIC_SYS_ROM (0*IOASIC_SLOT_SIZE)    /* system board ROM */
 #define IOASIC_IOCTL   (1*IOASIC_SLOT_SIZE)    /* I/O ASIC */

-#define IOASIC_ESAR    (2*IOASIC_SLOT_SIZE)    /* LANCE MAC address chip */
-#define IOASIC_LANCE   (3*IOASIC_SLOT_SIZE)    /* LANCE Ethernet */
-#define IOASIC_SCC0    (4*IOASIC_SLOT_SIZE)    /* SCC #0 */
+#define IOASIC_ESAR    (2*IOASIC_SLOT_SIZE)    /* LANCE MAC address chip */
+#define IOASIC_LANCE   (3*IOASIC_SLOT_SIZE)    /* LANCE Ethernet */
+#define IOASIC_SCC0    (4*IOASIC_SLOT_SIZE)    /* SCC #0 */

 #define IOASIC_VDAC_HI (5*IOASIC_SLOT_SIZE)    /* VDAC (maxine) */
 #define IOASIC_VDAC_HI (5*IOASIC_SLOT_SIZE)    /* VDAC (maxine) */

-#define IOASIC_SCC1    (6*IOASIC_SLOT_SIZE)    /* SCC #1 (3min, 3max+) */
+#define IOASIC_SCC1    (6*IOASIC_SLOT_SIZE)    /* SCC #1 (3min, 3max+) */

 #define IOASIC_VDAC_LO (7*IOASIC_SLOT_SIZE)    /* VDAC (maxine) */
 #define IOASIC_VDAC_LO (7*IOASIC_SLOT_SIZE)    /* VDAC (maxine) */

-#define IOASIC_TOY     (8*IOASIC_SLOT_SIZE)    /* RTC */
-#define IOASIC_ISDN    (9*IOASIC_SLOT_SIZE)    /* ISDN (maxine) */
+#define IOASIC_TOY     (8*IOASIC_SLOT_SIZE)    /* RTC */
+#define IOASIC_ISDN    (9*IOASIC_SLOT_SIZE)    /* ISDN (maxine) */

 #define IOASIC_ERRADDR (9*IOASIC_SLOT_SIZE)    /* bus error address (3max+) */
 #define IOASIC_ERRADDR (9*IOASIC_SLOT_SIZE)    /* bus error address (3max+) */

-#define IOASIC_CHKSYN  (10*IOASIC_SLOT_SIZE)   /* ECC syndrome (3max+) */
+#define IOASIC_CHKSYN  (10*IOASIC_SLOT_SIZE)   /* ECC syndrome (3max+) */

 #define IOASIC_ACC_BUS (10*IOASIC_SLOT_SIZE)   /* ACCESS.bus (maxine) */
 #define IOASIC_ACC_BUS (10*IOASIC_SLOT_SIZE)   /* ACCESS.bus (maxine) */

-#define IOASIC_MCR     (11*IOASIC_SLOT_SIZE)   /* memory control (3max+) */
-#define IOASIC_FLOPPY  (11*IOASIC_SLOT_SIZE)   /* FDC (maxine) */
-#define IOASIC_SCSI    (12*IOASIC_SLOT_SIZE)   /* ASC SCSI */
+#define IOASIC_MCR     (11*IOASIC_SLOT_SIZE)   /* memory control (3max+) */
+#define IOASIC_FLOPPY  (11*IOASIC_SLOT_SIZE)   /* FDC (maxine) */
+#define IOASIC_SCSI    (12*IOASIC_SLOT_SIZE)   /* ASC SCSI */

 #define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE)   /* FDC DMA (maxine) */
 #define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE)   /* FDC DMA (maxine) */

-#define IOASIC_SCSI_DMA        (14*IOASIC_SLOT_SIZE)   /* ??? */
+#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE)  /* ??? */

 #define IOASIC_RES_15  (15*IOASIC_SLOT_SIZE)   /* unused? */
 
 
 #define IOASIC_RES_15  (15*IOASIC_SLOT_SIZE)   /* unused? */
 
 

diff --git a/arch/mips/include/asm/dec/kn01.h b/arch/mips/include/asm/dec/kn01.h
index 88d9ffd742588b41c99975943c7769fb75f18d25..0eb3241de7060883d6b72e2878da258d9b41caf2 100644 (file)
--- a/arch/mips/include/asm/dec/kn01.h
+++ b/arch/mips/include/asm/dec/kn01.h
@@ -57,12 +57,12 @@
 /*
  * System Control & Status Register bits.
  */
 /*
  * System Control & Status Register bits.
  */

-#define KN01_CSR_MNFMOD                (1<<15) /* MNFMOD manufacturing jumper */
-#define KN01_CSR_STATUS                (1<<14) /* self-test result status output */
-#define KN01_CSR_PARDIS                (1<<13) /* parity error disable */
-#define KN01_CSR_CRSRTST       (1<<12) /* PCC test output */
-#define KN01_CSR_MONO          (1<<11) /* mono/color fb SIMM installed */
-#define KN01_CSR_MEMERR                (1<<10) /* write timeout error status & ack*/
+#define KN01_CSR_MNFMOD                (1<<15) /* MNFMOD manufacturing jumper */
+#define KN01_CSR_STATUS                (1<<14) /* self-test result status output */
+#define KN01_CSR_PARDIS                (1<<13) /* parity error disable */
+#define KN01_CSR_CRSRTST       (1<<12) /* PCC test output */
+#define KN01_CSR_MONO          (1<<11) /* mono/color fb SIMM installed */
+#define KN01_CSR_MEMERR                (1<<10) /* write timeout error status & ack*/

 #define KN01_CSR_VINT          (1<<9)  /* PCC area detect #2 status & ack */
 #define KN01_CSR_TXDIS         (1<<8)  /* DZ11 transmit disable */
 #define KN01_CSR_VBGTRG                (1<<2)  /* blue DAC voltage over green (r/o) */
 #define KN01_CSR_VINT          (1<<9)  /* PCC area detect #2 status & ack */
 #define KN01_CSR_TXDIS         (1<<8)  /* DZ11 transmit disable */
 #define KN01_CSR_VBGTRG                (1<<2)  /* blue DAC voltage over green (r/o) */

diff --git a/arch/mips/include/asm/dec/kn02ca.h b/arch/mips/include/asm/dec/kn02ca.h
index 92c0fe2560997e901908eac961e8b27d34097f46..69dc2a9a2d0f5602d91c4b83306f6f0952572a52 100644 (file)
--- a/arch/mips/include/asm/dec/kn02ca.h
+++ b/arch/mips/include/asm/dec/kn02ca.h
@@ -68,7 +68,7 @@
 #define KN03CA_IO_SSR_ISDN_RST (1<<12)         /* ~ISDN (Am79C30A) reset */
 
 #define KN03CA_IO_SSR_FLOPPY_RST (1<<7)                /* ~FDC (82077) reset */
 #define KN03CA_IO_SSR_ISDN_RST (1<<12)         /* ~ISDN (Am79C30A) reset */
 
 #define KN03CA_IO_SSR_FLOPPY_RST (1<<7)                /* ~FDC (82077) reset */

-#define KN03CA_IO_SSR_VIDEO_RST        (1<<6)          /* ~framebuffer reset */
+#define KN03CA_IO_SSR_VIDEO_RST (1<<6)         /* ~framebuffer reset */

 #define KN03CA_IO_SSR_AB_RST   (1<<5)          /* ACCESS.bus reset */
 #define KN03CA_IO_SSR_RES_4    (1<<4)          /* unused */
 #define KN03CA_IO_SSR_RES_3    (1<<4)          /* unused */
 #define KN03CA_IO_SSR_AB_RST   (1<<5)          /* ACCESS.bus reset */
 #define KN03CA_IO_SSR_RES_4    (1<<4)          /* unused */
 #define KN03CA_IO_SSR_RES_3    (1<<4)          /* unused */

diff --git a/arch/mips/include/asm/dec/prom.h b/arch/mips/include/asm/dec/prom.h
index c0ead63138453c04d3b20918fbcfb1e1c02c5c3c..446577712bee23d45be3f9375a6d8ee8f2806a2e 100644 (file)
--- a/arch/mips/include/asm/dec/prom.h
+++ b/arch/mips/include/asm/dec/prom.h
@@ -49,7 +49,7 @@
 
 #ifdef CONFIG_64BIT
 
 
 #ifdef CONFIG_64BIT
 

-#define prom_is_rex(magic)     1       /* KN04 and KN05 are REX PROMs.  */
+#define prom_is_rex(magic)     1       /* KN04 and KN05 are REX PROMs.  */

 
 #else /* !CONFIG_64BIT */
 
 
 #else /* !CONFIG_64BIT */
 

diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
index 006b43e38a9c4f831bcc1135f0048c8b8c48aaf6..f8fc74b6cb47430b540d072833d62872192349d8 100644 (file)
--- a/arch/mips/include/asm/dma-mapping.h
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -5,7 +5,7 @@
 #include <asm/cache.h>
 #include <asm-generic/dma-coherent.h>
 
 #include <asm/cache.h>
 #include <asm-generic/dma-coherent.h>
 

-#ifndef CONFIG_SGI_IP27        /* Kludge to fix 2.6.39 build for IP27 */
+#ifndef CONFIG_SGI_IP27 /* Kludge to fix 2.6.39 build for IP27 */

 #include <dma-coherence.h>
 #endif
 
 #include <dma-coherence.h>
 #endif
 

diff --git a/arch/mips/include/asm/dma.h b/arch/mips/include/asm/dma.h
index f5097f65a8abae4e436588bbdc939ea4a30eaedb..5b9ed1bffdbcc419f7fe4bcee1c0040cb46273d7 100644 (file)
--- a/arch/mips/include/asm/dma.h
+++ b/arch/mips/include/asm/dma.h
@@ -47,21 +47,21 @@
  *
  *  Address mapping for channels 0-3:
  *
  *
  *  Address mapping for channels 0-3:
  *

- *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
- *    |  ...  |   |  ... |   |  ... |
- *    |  ...  |   |  ... |   |  ... |
- *    |  ...  |   |  ... |   |  ... |
- *   P7  ...  P0  A7 ... A0  A7 ... A0
- * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
+ *   A23 ... A16 A15 ... A8  A7 ... A0   (Physical addresses)
+ *    |         ...  |   |  ... |   |  ... |
+ *    |         ...  |   |  ... |   |  ... |
+ *    |         ...  |   |  ... |   |  ... |
+ *   P7         ...  P0  A7 ... A0  A7 ... A0
+ * |   Page    | Addr MSB | Addr LSB |   (DMA registers)

  *
  *  Address mapping for channels 5-7:
  *
  *
  *  Address mapping for channels 5-7:
  *

- *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
- *    |  ...  |   \   \   ... \  \  \  ... \  \
- *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
- *    |  ...  |     \   \   ... \  \  \  ... \
- *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
- * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
+ *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0           (Physical addresses)
+ *    |         ...  |   \   \   ... \  \  \  ... \  \
+ *    |         ...  |    \   \   ... \  \  \  ... \  (not used)
+ *    |         ...  |     \   \   ... \  \  \  ... \
+ *   P7         ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
+ * |     Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)

  *
  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
  *
  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at


@@ -102,55 +102,55 @@
 /* DMA controller registers */
 #define DMA1_CMD_REG           0x08    /* command register (w) */
 #define DMA1_STAT_REG          0x08    /* status register (r) */
 /* DMA controller registers */
 #define DMA1_CMD_REG           0x08    /* command register (w) */
 #define DMA1_STAT_REG          0x08    /* status register (r) */

-#define DMA1_REQ_REG            0x09    /* request register (w) */
+#define DMA1_REQ_REG           0x09    /* request register (w) */

 #define DMA1_MASK_REG          0x0A    /* single-channel mask (w) */
 #define DMA1_MODE_REG          0x0B    /* mode register (w) */
 #define DMA1_CLEAR_FF_REG      0x0C    /* clear pointer flip-flop (w) */
 #define DMA1_MASK_REG          0x0A    /* single-channel mask (w) */
 #define DMA1_MODE_REG          0x0B    /* mode register (w) */
 #define DMA1_CLEAR_FF_REG      0x0C    /* clear pointer flip-flop (w) */

-#define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
+#define DMA1_TEMP_REG          0x0D    /* Temporary Register (r) */

 #define DMA1_RESET_REG         0x0D    /* Master Clear (w) */
 #define DMA1_RESET_REG         0x0D    /* Master Clear (w) */

-#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
-#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
+#define DMA1_CLR_MASK_REG      0x0E    /* Clear Mask */
+#define DMA1_MASK_ALL_REG      0x0F    /* all-channels mask (w) */

 
 #define DMA2_CMD_REG           0xD0    /* command register (w) */
 #define DMA2_STAT_REG          0xD0    /* status register (r) */
 
 #define DMA2_CMD_REG           0xD0    /* command register (w) */
 #define DMA2_STAT_REG          0xD0    /* status register (r) */

-#define DMA2_REQ_REG            0xD2    /* request register (w) */
+#define DMA2_REQ_REG           0xD2    /* request register (w) */

 #define DMA2_MASK_REG          0xD4    /* single-channel mask (w) */
 #define DMA2_MODE_REG          0xD6    /* mode register (w) */
 #define DMA2_CLEAR_FF_REG      0xD8    /* clear pointer flip-flop (w) */
 #define DMA2_MASK_REG          0xD4    /* single-channel mask (w) */
 #define DMA2_MODE_REG          0xD6    /* mode register (w) */
 #define DMA2_CLEAR_FF_REG      0xD8    /* clear pointer flip-flop (w) */

-#define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
+#define DMA2_TEMP_REG          0xDA    /* Temporary Register (r) */

 #define DMA2_RESET_REG         0xDA    /* Master Clear (w) */
 #define DMA2_RESET_REG         0xDA    /* Master Clear (w) */

-#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
-#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
-
-#define DMA_ADDR_0              0x00    /* DMA address registers */
-#define DMA_ADDR_1              0x02
-#define DMA_ADDR_2              0x04
-#define DMA_ADDR_3              0x06
-#define DMA_ADDR_4              0xC0
-#define DMA_ADDR_5              0xC4
-#define DMA_ADDR_6              0xC8
-#define DMA_ADDR_7              0xCC
-
-#define DMA_CNT_0               0x01    /* DMA count registers */
-#define DMA_CNT_1               0x03
-#define DMA_CNT_2               0x05
-#define DMA_CNT_3               0x07
-#define DMA_CNT_4               0xC2
-#define DMA_CNT_5               0xC6
-#define DMA_CNT_6               0xCA
-#define DMA_CNT_7               0xCE
-
-#define DMA_PAGE_0              0x87    /* DMA page registers */
-#define DMA_PAGE_1              0x83
-#define DMA_PAGE_2              0x81
-#define DMA_PAGE_3              0x82
-#define DMA_PAGE_5              0x8B
-#define DMA_PAGE_6              0x89
-#define DMA_PAGE_7              0x8A
+#define DMA2_CLR_MASK_REG      0xDC    /* Clear Mask */
+#define DMA2_MASK_ALL_REG      0xDE    /* all-channels mask (w) */
+
+#define DMA_ADDR_0             0x00    /* DMA address registers */
+#define DMA_ADDR_1             0x02
+#define DMA_ADDR_2             0x04
+#define DMA_ADDR_3             0x06
+#define DMA_ADDR_4             0xC0
+#define DMA_ADDR_5             0xC4
+#define DMA_ADDR_6             0xC8
+#define DMA_ADDR_7             0xCC
+
+#define DMA_CNT_0              0x01    /* DMA count registers */
+#define DMA_CNT_1              0x03
+#define DMA_CNT_2              0x05
+#define DMA_CNT_3              0x07
+#define DMA_CNT_4              0xC2
+#define DMA_CNT_5              0xC6
+#define DMA_CNT_6              0xCA
+#define DMA_CNT_7              0xCE
+
+#define DMA_PAGE_0             0x87    /* DMA page registers */
+#define DMA_PAGE_1             0x83
+#define DMA_PAGE_2             0x81
+#define DMA_PAGE_3             0x82
+#define DMA_PAGE_5             0x8B
+#define DMA_PAGE_6             0x89
+#define DMA_PAGE_7             0x8A

 
 #define DMA_MODE_READ  0x44    /* I/O to memory, no autoinit, increment, single mode */
 #define DMA_MODE_WRITE 0x48    /* memory to I/O, no autoinit, increment, single mode */
 
 #define DMA_MODE_READ  0x44    /* I/O to memory, no autoinit, increment, single mode */
 #define DMA_MODE_WRITE 0x48    /* memory to I/O, no autoinit, increment, single mode */

-#define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
+#define DMA_MODE_CASCADE 0xC0  /* pass thru DREQ->HRQ, DACK<-HLDA only */

 
 #define DMA_AUTOINIT   0x10
 
 
 #define DMA_AUTOINIT   0x10
 


@@ -172,7 +172,7 @@ static __inline__ void release_dma_lock(unsigned long flags)
 static __inline__ void enable_dma(unsigned int dmanr)
 {
        if (dmanr<=3)
 static __inline__ void enable_dma(unsigned int dmanr)
 {
        if (dmanr<=3)

-               dma_outb(dmanr,  DMA1_MASK_REG);
+               dma_outb(dmanr,  DMA1_MASK_REG);

        else
                dma_outb(dmanr & 3,  DMA2_MASK_REG);
 }
        else
                dma_outb(dmanr & 3,  DMA2_MASK_REG);
 }


@@ -204,7 +204,7 @@ static __inline__ void clear_dma_ff(unsigned int dmanr)
 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
 {
        if (dmanr<=3)
 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
 {
        if (dmanr<=3)

-               dma_outb(mode | dmanr,  DMA1_MODE_REG);
+               dma_outb(mode | dmanr,  DMA1_MODE_REG);

        else
                dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
 }
        else
                dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
 }


@@ -248,10 +248,10 @@ static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
 {
        set_dma_page(dmanr, a>>16);
 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
 {
        set_dma_page(dmanr, a>>16);

-       if (dmanr <= 3)  {
+       if (dmanr <= 3)  {

            dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
            dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );

-            dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
-       }  else  {
+           dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
+       }  else  {

            dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
            dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
        }
            dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
            dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
        }


@@ -268,14 +268,14 @@ static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
  */
 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
 {
  */
 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
 {

-        count--;
-       if (dmanr <= 3)  {
+       count--;
+       if (dmanr <= 3)  {

            dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
            dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
            dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
            dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );

-        } else {
+       } else {

            dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
            dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
            dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
            dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );

-        }
+       }

 }
 
 
 }
 
 

diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h
index 455c0ac7d4ea84632cc41c40ee48e7dd9e82ce86..cf3ae2480b1d25f5dfd77e8e328e5745b413e2be 100644 (file)
--- a/arch/mips/include/asm/elf.h
+++ b/arch/mips/include/asm/elf.h
@@ -11,13 +11,13 @@
 
 /* ELF header e_flags defines. */
 /* MIPS architecture level. */
 
 /* ELF header e_flags defines. */
 /* MIPS architecture level. */

-#define EF_MIPS_ARCH_1         0x00000000      /* -mips1 code.  */
-#define EF_MIPS_ARCH_2         0x10000000      /* -mips2 code.  */
-#define EF_MIPS_ARCH_3         0x20000000      /* -mips3 code.  */
-#define EF_MIPS_ARCH_4         0x30000000      /* -mips4 code.  */
-#define EF_MIPS_ARCH_5         0x40000000      /* -mips5 code.  */
-#define EF_MIPS_ARCH_32                0x50000000      /* MIPS32 code.  */
-#define EF_MIPS_ARCH_64                0x60000000      /* MIPS64 code.  */
+#define EF_MIPS_ARCH_1         0x00000000      /* -mips1 code.  */
+#define EF_MIPS_ARCH_2         0x10000000      /* -mips2 code.  */
+#define EF_MIPS_ARCH_3         0x20000000      /* -mips3 code.  */
+#define EF_MIPS_ARCH_4         0x30000000      /* -mips4 code.  */
+#define EF_MIPS_ARCH_5         0x40000000      /* -mips5 code.  */
+#define EF_MIPS_ARCH_32                0x50000000      /* MIPS32 code.  */
+#define EF_MIPS_ARCH_64                0x60000000      /* MIPS64 code.  */

 #define EF_MIPS_ARCH_32R2      0x70000000      /* MIPS32 R2 code.  */
 #define EF_MIPS_ARCH_64R2      0x80000000      /* MIPS64 R2 code.  */
 
 #define EF_MIPS_ARCH_32R2      0x70000000      /* MIPS32 R2 code.  */
 #define EF_MIPS_ARCH_64R2      0x80000000      /* MIPS64 R2 code.  */
 


@@ -74,7 +74,7 @@
 #define R_MIPS_CALL16          11
 #define R_MIPS_GPREL32         12
 /* The remaining relocs are defined on Irix, although they are not
 #define R_MIPS_CALL16          11
 #define R_MIPS_GPREL32         12
 /* The remaining relocs are defined on Irix, although they are not

-   in the MIPS ELF ABI.  */
+   in the MIPS ELF ABI.         */

 #define R_MIPS_UNUSED1         13
 #define R_MIPS_UNUSED2         14
 #define R_MIPS_UNUSED3         15
 #define R_MIPS_UNUSED1         13
 #define R_MIPS_UNUSED2         14
 #define R_MIPS_UNUSED3         15


@@ -214,7 +214,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
                                                                        \
        if (__h->e_machine != EM_MIPS)                                  \
                __res = 0;                                              \
                                                                        \
        if (__h->e_machine != EM_MIPS)                                  \
                __res = 0;                                              \

-       if (__h->e_ident[EI_CLASS] != ELFCLASS64)                       \
+       if (__h->e_ident[EI_CLASS] != ELFCLASS64)                       \

                __res = 0;                                              \
                                                                        \
        __res;                                                          \
                __res = 0;                                              \
                                                                        \
        __res;                                                          \


@@ -292,7 +292,7 @@ do {                                                                        \
                __SET_PERSONALITY32_O32();                              \
 } while (0)
 #else
                __SET_PERSONALITY32_O32();                              \
 } while (0)
 #else

-#define __SET_PERSONALITY32(ex)        do { } while (0)
+#define __SET_PERSONALITY32(ex) do { } while (0)

 #endif
 
 #define SET_PERSONALITY(ex)                                            \
 #endif
 
 #define SET_PERSONALITY(ex)                                            \


@@ -337,11 +337,11 @@ extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
    instruction set this cpu supports.  This could be done in userspace,
    but it's not easy, and we've already done it here.  */
 
    instruction set this cpu supports.  This could be done in userspace,
    but it's not easy, and we've already done it here.  */
 

-#define ELF_HWCAP       (0)
+#define ELF_HWCAP      (0)

 
 /*
  * This yields a string that ld.so will use to load implementation
 
 /*
  * This yields a string that ld.so will use to load implementation

- * specific libraries for optimization.  This is more specific in
+ * specific libraries for optimization.         This is more specific in

  * intent than poking at uname or /proc/cpuinfo.
  */
 
  * intent than poking at uname or /proc/cpuinfo.
  */
 


@@ -365,11 +365,11 @@ extern const char *__elf_platform;
 
 /* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
    use of this is to invoke "./ld.so someprog" to test out a new version of
 
 /* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
    use of this is to invoke "./ld.so someprog" to test out a new version of

-   the loader.  We need to make sure that it is out of the way of the program
-   that it will "exec", and that there is sufficient room for the brk.  */
+   the loader. We need to make sure that it is out of the way of the program
+   that it will "exec", and that there is sufficient room for the brk. */

 
 #ifndef ELF_ET_DYN_BASE
 
 #ifndef ELF_ET_DYN_BASE

-#define ELF_ET_DYN_BASE         (TASK_SIZE / 3 * 2)
+#define ELF_ET_DYN_BASE                (TASK_SIZE / 3 * 2)

 #endif
 
 #define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1
 #endif
 
 #define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1

diff --git a/arch/mips/include/asm/emma/emma2rh.h b/arch/mips/include/asm/emma/emma2rh.h
index c1449d20ef0e3022e5e3ee9c229b800f4c017bbc..ecf059608bd86b154ffdbffa9233448328399aa9 100644 (file)
--- a/arch/mips/include/asm/emma/emma2rh.h
+++ b/arch/mips/include/asm/emma/emma2rh.h
@@ -2,7 +2,7 @@
  *  Copyright (C) NEC Electronics Corporation 2005-2006
  *
  *  This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
  *  Copyright (C) NEC Electronics Corporation 2005-2006
  *
  *  This file based on include/asm-mips/ddb5xxx/ddb5xxx.h

- *          Copyright 2001 MontaVista Software Inc.
+ *         Copyright 2001 MontaVista Software Inc.

  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by


@@ -40,7 +40,7 @@
 #define EMMA2RH_BHIF_INT1_EN_2 (0x000058+REGBASE)
 #define EMMA2RH_BHIF_SW_INT    (0x000070+REGBASE)
 #define EMMA2RH_BHIF_SW_INT_EN (0x000080+REGBASE)
 #define EMMA2RH_BHIF_INT1_EN_2 (0x000058+REGBASE)
 #define EMMA2RH_BHIF_SW_INT    (0x000070+REGBASE)
 #define EMMA2RH_BHIF_SW_INT_EN (0x000080+REGBASE)

-#define EMMA2RH_BHIF_SW_INT_CLR        (0x000090+REGBASE)
+#define EMMA2RH_BHIF_SW_INT_CLR (0x000090+REGBASE)

 #define EMMA2RH_BHIF_MAIN_CTRL (0x0000b4+REGBASE)
 #define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS  (0x0000c0+REGBASE)
 #define EMMA2RH_GPIO_DIR       (0x110d20+REGBASE)
 #define EMMA2RH_BHIF_MAIN_CTRL (0x0000b4+REGBASE)
 #define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS  (0x0000c0+REGBASE)
 #define EMMA2RH_GPIO_DIR       (0x110d20+REGBASE)


@@ -73,7 +73,7 @@
  *  Memory map (physical address)
  *
  *  Note most of the following address must be properly aligned by the
  *  Memory map (physical address)
  *
  *  Note most of the following address must be properly aligned by the

- *  corresponding size.  For example, if PCI_IO_SIZE is 16MB, then
+ *  corresponding size.         For example, if PCI_IO_SIZE is 16MB, then

  *  PCI_IO_BASE must be aligned along 16MB boundary.
  */
 
  *  PCI_IO_BASE must be aligned along 16MB boundary.
  */
 


@@ -96,8 +96,8 @@
 #define EMMA2RH_ROM_BASE       0x1c000000
 #define EMMA2RH_ROM_SIZE       0x04000000      /* 64 MB */
 
 #define EMMA2RH_ROM_BASE       0x1c000000
 #define EMMA2RH_ROM_SIZE       0x04000000      /* 64 MB */
 

-#define EMMA2RH_PCI_CONFIG_BASE        EMMA2RH_PCI_IO_BASE
-#define EMMA2RH_PCI_CONFIG_SIZE        EMMA2RH_PCI_IO_SIZE
+#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE
+#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE

 
 #define NUM_EMMA2RH_IRQ                96
 
 
 #define NUM_EMMA2RH_IRQ                96
 


@@ -169,51 +169,51 @@ static inline u8 emma2rh_in8(u32 offset)
  **/
 
 /*---------------------------------------------------------------------------*/
  **/
 
 /*---------------------------------------------------------------------------*/

-/* CNT - Control register (00H R/W)                                          */
+/* CNT - Control register (00H R/W)                                         */

 /*---------------------------------------------------------------------------*/
 /*---------------------------------------------------------------------------*/

-#define SPT         0x00000001
-#define STT         0x00000002
-#define ACKE        0x00000004
-#define WTIM        0x00000008
-#define SPIE        0x00000010
-#define WREL        0x00000020
-#define LREL        0x00000040
-#define IICE        0x00000080
-#define CNT_RESERVED    0x000000ff     /* reserved bit 0 */
-
-#define I2C_EMMA_START      (IICE | STT)
-#define I2C_EMMA_STOP       (IICE | SPT)
+#define SPT        0x00000001
+#define STT        0x00000002
+#define ACKE       0x00000004
+#define WTIM       0x00000008
+#define SPIE       0x00000010
+#define WREL       0x00000020
+#define LREL       0x00000040
+#define IICE       0x00000080
+#define CNT_RESERVED   0x000000ff      /* reserved bit 0 */
+
+#define I2C_EMMA_START     (IICE | STT)
+#define I2C_EMMA_STOP      (IICE | SPT)

 #define I2C_EMMA_REPSTART   I2C_EMMA_START
 
 /*---------------------------------------------------------------------------*/
 #define I2C_EMMA_REPSTART   I2C_EMMA_START
 
 /*---------------------------------------------------------------------------*/

-/* STA - Status register (10H Read)                                          */
+/* STA - Status register (10H Read)                                         */

 /*---------------------------------------------------------------------------*/
 /*---------------------------------------------------------------------------*/

-#define MSTS        0x00000080
-#define ALD         0x00000040
-#define EXC         0x00000020
-#define COI         0x00000010
-#define TRC         0x00000008
-#define ACKD        0x00000004
-#define STD         0x00000002
-#define SPD         0x00000001
+#define MSTS       0x00000080
+#define ALD        0x00000040
+#define EXC        0x00000020
+#define COI        0x00000010
+#define TRC        0x00000008
+#define ACKD       0x00000004
+#define STD        0x00000002
+#define SPD        0x00000001

 
 /*---------------------------------------------------------------------------*/
 
 /*---------------------------------------------------------------------------*/

-/* CSEL - Clock select register (20H R/W)                                    */
+/* CSEL - Clock select register (20H R/W)                                   */

 /*---------------------------------------------------------------------------*/
 /*---------------------------------------------------------------------------*/

-#define FCL         0x00000080
-#define ND50        0x00000040
-#define CLD         0x00000020
-#define DAD         0x00000010
-#define SMC         0x00000008
-#define DFC         0x00000004
-#define CL          0x00000003
-#define CSEL_RESERVED   0x000000ff     /* reserved bit 0 */
-
-#define FAST397     0x0000008b
-#define FAST297     0x0000008a
-#define FAST347     0x0000000b
-#define FAST260     0x0000000a
-#define FAST130     0x00000008
+#define FCL        0x00000080
+#define ND50       0x00000040
+#define CLD        0x00000020
+#define DAD        0x00000010
+#define SMC        0x00000008
+#define DFC        0x00000004
+#define CL         0x00000003
+#define CSEL_RESERVED  0x000000ff      /* reserved bit 0 */
+
+#define FAST397            0x0000008b
+#define FAST297            0x0000008a
+#define FAST347            0x0000000b
+#define FAST260            0x0000000a
+#define FAST130            0x00000008

 #define STANDARD108 0x00000083
 #define STANDARD83  0x00000082
 #define STANDARD95  0x00000003
 #define STANDARD108 0x00000083
 #define STANDARD83  0x00000082
 #define STANDARD95  0x00000003


@@ -222,32 +222,32 @@ static inline u8 emma2rh_in8(u32 offset)
 #define STANDARD71  0x00000000
 
 /*---------------------------------------------------------------------------*/
 #define STANDARD71  0x00000000
 
 /*---------------------------------------------------------------------------*/

-/* SVA - Slave address register (30H R/W)                                    */
+/* SVA - Slave address register (30H R/W)                                   */

 /*---------------------------------------------------------------------------*/
 /*---------------------------------------------------------------------------*/

-#define SVA         0x000000fe
+#define SVA        0x000000fe

 
 /*---------------------------------------------------------------------------*/
 
 /*---------------------------------------------------------------------------*/

-/* SHR - Shift register (40H R/W)                                            */
+/* SHR - Shift register (40H R/W)                                           */

 /*---------------------------------------------------------------------------*/
 /*---------------------------------------------------------------------------*/

-#define SR          0x000000ff
+#define SR         0x000000ff

 
 /*---------------------------------------------------------------------------*/
 
 /*---------------------------------------------------------------------------*/

-/* INT - Interrupt register (50H R/W)                                        */
-/* INTM - Interrupt mask register (60H R/W)                                  */
+/* INT - Interrupt register (50H R/W)                                       */
+/* INTM - Interrupt mask register (60H R/W)                                 */

 /*---------------------------------------------------------------------------*/
 /*---------------------------------------------------------------------------*/

-#define INTE0       0x00000001
+#define INTE0      0x00000001

 
 /***********************************************************************
  * I2C registers
  ***********************************************************************
  */
 
 /***********************************************************************
  * I2C registers
  ***********************************************************************
  */

-#define I2C_EMMA_CNT            0x00
-#define I2C_EMMA_STA            0x10
-#define I2C_EMMA_CSEL           0x20
-#define I2C_EMMA_SVA            0x30
-#define I2C_EMMA_SHR            0x40
-#define I2C_EMMA_INT            0x50
-#define I2C_EMMA_INTM           0x60
+#define I2C_EMMA_CNT           0x00
+#define I2C_EMMA_STA           0x10
+#define I2C_EMMA_CSEL          0x20
+#define I2C_EMMA_SVA           0x30
+#define I2C_EMMA_SHR           0x40
+#define I2C_EMMA_INT           0x50
+#define I2C_EMMA_INTM          0x60

 
 /*
  * include the board dependent part
 
 /*
  * include the board dependent part

diff --git a/arch/mips/include/asm/emma/markeins.h b/arch/mips/include/asm/emma/markeins.h
index bf2d229c2dae602738fc3ff3c14274d065881fbd..e55a67477820ec0ead971ca2da88253f26bed968 100644 (file)
--- a/arch/mips/include/asm/emma/markeins.h
+++ b/arch/mips/include/asm/emma/markeins.h
@@ -2,7 +2,7 @@
  *  Copyright (C) NEC Electronics Corporation 2005-2006
  *
  *  This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
  *  Copyright (C) NEC Electronics Corporation 2005-2006
  *
  *  This file based on include/asm-mips/ddb5xxx/ddb5xxx.h

- *          Copyright 2001 MontaVista Software Inc.
+ *         Copyright 2001 MontaVista Software Inc.

  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by

diff --git a/arch/mips/include/asm/fixmap.h b/arch/mips/include/asm/fixmap.h
index 98bcc98cf29b49f3b097dca2aa87b758875bb6b0..dfaaf493e9d4a552238372506b1a662a8e6c260e 100644 (file)
--- a/arch/mips/include/asm/fixmap.h
+++ b/arch/mips/include/asm/fixmap.h
@@ -95,7 +95,7 @@ static inline unsigned long fix_to_virt(const unsigned int idx)
        if (idx >= __end_of_fixed_addresses)
                __this_fixmap_does_not_exist();
 
        if (idx >= __end_of_fixed_addresses)
                __this_fixmap_does_not_exist();
 

-        return __fix_to_virt(idx);
+       return __fix_to_virt(idx);

 }
 
 static inline unsigned long virt_to_fix(const unsigned long vaddr)
 }
 
 static inline unsigned long virt_to_fix(const unsigned long vaddr)


@@ -111,7 +111,7 @@ static inline unsigned long virt_to_fix(const unsigned long vaddr)
  * Called from pgtable_init()
  */
 extern void fixrange_init(unsigned long start, unsigned long end,
  * Called from pgtable_init()
  */
 extern void fixrange_init(unsigned long start, unsigned long end,

-        pgd_t *pgd_base);
+       pgd_t *pgd_base);

 
 
 #endif
 
 
 #endif

diff --git a/arch/mips/include/asm/floppy.h b/arch/mips/include/asm/floppy.h
index 4456c9c47e2144c67cd2449c98f9c8e4e5a1728b..d75aed36480a843cfd7703741209e518638ca56f 100644 (file)
--- a/arch/mips/include/asm/floppy.h
+++ b/arch/mips/include/asm/floppy.h
@@ -24,9 +24,9 @@ static inline void fd_cacheflush(char * addr, long size)
  * And on Mips's the CMOS info fails also ...
  *
  * FIXME: This information should come from the ARC configuration tree
  * And on Mips's the CMOS info fails also ...
  *
  * FIXME: This information should come from the ARC configuration tree

- *        or wherever a particular machine has stored this ...
+ *       or wherever a particular machine has stored this ...

  */
  */

-#define FLOPPY0_TYPE           fd_drive_type(0)
+#define FLOPPY0_TYPE           fd_drive_type(0)

 #define FLOPPY1_TYPE           fd_drive_type(1)
 
 #define FDC1                   fd_getfdaddr1()
 #define FLOPPY1_TYPE           fd_drive_type(1)
 
 #define FDC1                   fd_getfdaddr1()

diff --git a/arch/mips/include/asm/fpregdef.h b/arch/mips/include/asm/fpregdef.h
index 2b5fddc8f487c82c13bb0d53dc6c36c23eb02694..429481f9028dd08119e9961ab8669c04181a6ad3 100644 (file)
--- a/arch/mips/include/asm/fpregdef.h
+++ b/arch/mips/include/asm/fpregdef.h
@@ -20,15 +20,15 @@
  * These definitions only cover the R3000-ish 16/32 register model.
  * But we're trying to be R3000 friendly anyway ...
  */
  * These definitions only cover the R3000-ish 16/32 register model.
  * But we're trying to be R3000 friendly anyway ...
  */

-#define fv0    $f0      /* return value */
+#define fv0    $f0      /* return value */

 #define fv0f   $f1
 #define fv1    $f2
 #define fv1f   $f3
 #define fv0f   $f1
 #define fv1    $f2
 #define fv1f   $f3

-#define fa0    $f12     /* argument registers */
+#define fa0    $f12     /* argument registers */

 #define fa0f   $f13
 #define fa1    $f14
 #define fa1f   $f15
 #define fa0f   $f13
 #define fa1    $f14
 #define fa1f   $f15

-#define ft0    $f4      /* caller saved */
+#define ft0    $f4      /* caller saved */

 #define ft0f   $f5
 #define ft1    $f6
 #define ft1f   $f7
 #define ft0f   $f5
 #define ft1    $f6
 #define ft1f   $f7


@@ -40,7 +40,7 @@
 #define ft4f   $f17
 #define ft5    $f18
 #define ft5f   $f19
 #define ft4f   $f17
 #define ft5    $f18
 #define ft5f   $f19

-#define fs0    $f20     /* callee saved */
+#define fs0    $f20     /* callee saved */

 #define fs0f   $f21
 #define fs1    $f22
 #define fs1f   $f23
 #define fs0f   $f21
 #define fs1    $f22
 #define fs1f   $f23


@@ -53,7 +53,7 @@
 #define fs5    $f30
 #define fs5f   $f31
 
 #define fs5    $f30
 #define fs5f   $f31
 

-#define fcr31  $31      /* FPU status register */
+#define fcr31  $31      /* FPU status register */

 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 

diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index 7fcef8ef3fab717e7fdb335c2e05315892b85a86..d088e5db49032bf3d2ed0f050ac49eb889446e8f 100644 (file)
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -35,14 +35,14 @@ extern void _restore_fp(struct task_struct *);
 
 #define __enable_fpu()                                                 \
 do {                                                                   \
 
 #define __enable_fpu()                                                 \
 do {                                                                   \

-        set_c0_status(ST0_CU1);                                                \
-        enable_fpu_hazard();                                           \
+       set_c0_status(ST0_CU1);                                         \
+       enable_fpu_hazard();                                            \

 } while (0)
 
 #define __disable_fpu()                                                        \
 do {                                                                   \
        clear_c0_status(ST0_CU1);                                       \
 } while (0)
 
 #define __disable_fpu()                                                        \
 do {                                                                   \
        clear_c0_status(ST0_CU1);                                       \

-        disable_fpu_hazard();                                          \
+       disable_fpu_hazard();                                           \

 } while (0)
 
 #define enable_fpu()                                                   \
 } while (0)
 
 #define enable_fpu()                                                   \

diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h
index 6ebf1734b411b5150412b21a6744ec7c177c2088..6ea15815d3ee2f83456f665b5fdfcacf2a537d9a 100644 (file)
--- a/arch/mips/include/asm/futex.h
+++ b/arch/mips/include/asm/futex.h
@@ -92,24 +92,24 @@ futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr)
 
        switch (op) {
        case FUTEX_OP_SET:
 
        switch (op) {
        case FUTEX_OP_SET:

-               __futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg);
+               __futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg);

                break;
 
        case FUTEX_OP_ADD:
                break;
 
        case FUTEX_OP_ADD:

-               __futex_atomic_op("addu $1, %1, %z5",
-                                 ret, oldval, uaddr, oparg);
+               __futex_atomic_op("addu $1, %1, %z5",
+                                 ret, oldval, uaddr, oparg);

                break;
        case FUTEX_OP_OR:
                __futex_atomic_op("or   $1, %1, %z5",
                break;
        case FUTEX_OP_OR:
                __futex_atomic_op("or   $1, %1, %z5",

-                                 ret, oldval, uaddr, oparg);
+                                 ret, oldval, uaddr, oparg);

                break;
        case FUTEX_OP_ANDN:
                __futex_atomic_op("and  $1, %1, %z5",
                break;
        case FUTEX_OP_ANDN:
                __futex_atomic_op("and  $1, %1, %z5",

-                                 ret, oldval, uaddr, ~oparg);
+                                 ret, oldval, uaddr, ~oparg);

                break;
        case FUTEX_OP_XOR:
                __futex_atomic_op("xor  $1, %1, %z5",
                break;
        case FUTEX_OP_XOR:
                __futex_atomic_op("xor  $1, %1, %z5",

-                                 ret, oldval, uaddr, oparg);
+                                 ret, oldval, uaddr, oparg);

                break;
        default:
                ret = -ENOSYS;
                break;
        default:
                ret = -ENOSYS;

diff --git a/arch/mips/include/asm/fw/arc/hinv.h b/arch/mips/include/asm/fw/arc/hinv.h
index e6ff4add04e2d31b48ea553d8dfce08fbf8e0cd2..f8d37d1df5de53cd091b696e1c5372878e38d000 100644 (file)
--- a/arch/mips/include/asm/fw/arc/hinv.h
+++ b/arch/mips/include/asm/fw/arc/hinv.h
@@ -12,7 +12,7 @@ typedef enum configclass {
        SystemClass,
        ProcessorClass,
        CacheClass,
        SystemClass,
        ProcessorClass,
        CacheClass,

-#ifndef        _NT_PROM
+#ifndef _NT_PROM

        MemoryClass,
        AdapterClass,
        ControllerClass,
        MemoryClass,
        AdapterClass,
        ControllerClass,


@@ -34,7 +34,7 @@ typedef enum configtype {
        SecondaryICache,
        SecondaryDCache,
        SecondaryCache,
        SecondaryICache,
        SecondaryDCache,
        SecondaryCache,

-#ifndef        _NT_PROM
+#ifndef _NT_PROM

        Memory,
 #endif
        EISAAdapter,
        Memory,
 #endif
        EISAAdapter,


@@ -93,7 +93,7 @@ typedef enum {
 } IDENTIFIERFLAG;
 
 #ifndef NULL                   /* for GetChild(NULL); */
 } IDENTIFIERFLAG;
 
 #ifndef NULL                   /* for GetChild(NULL); */

-#define        NULL    0
+#define NULL   0

 #endif
 
 union key_u {
 #endif
 
 union key_u {


@@ -125,7 +125,7 @@ typedef struct component {
        IDENTIFIERFLAG  Flags;
        USHORT          Version;
        USHORT          Revision;
        IDENTIFIERFLAG  Flags;
        USHORT          Version;
        USHORT          Revision;

-       ULONG           Key;
+       ULONG           Key;

        ULONG           AffinityMask;
        ULONG           ConfigurationDataSize;
        ULONG           IdentifierLength;
        ULONG           AffinityMask;
        ULONG           ConfigurationDataSize;
        ULONG           IdentifierLength;


@@ -149,7 +149,7 @@ typedef struct systemid {
 typedef enum memorytype {
        ExceptionBlock,
        SPBPage,                        /* ARCS == SystemParameterBlock */
 typedef enum memorytype {
        ExceptionBlock,
        SPBPage,                        /* ARCS == SystemParameterBlock */

-#ifndef        _NT_PROM
+#ifndef _NT_PROM

        FreeContiguous,
        FreeMemory,
        BadMemory,
        FreeContiguous,
        FreeMemory,
        BadMemory,

diff --git a/arch/mips/include/asm/fw/arc/types.h b/arch/mips/include/asm/fw/arc/types.h
index 2b11f87d6fb3a142f6330f87b8d481c12c7ddad1..ad163806148ab5e3b4e69d479d550f5560edfa92 100644 (file)
--- a/arch/mips/include/asm/fw/arc/types.h
+++ b/arch/mips/include/asm/fw/arc/types.h
@@ -15,7 +15,7 @@
 typedef char           CHAR;
 typedef short          SHORT;
 typedef long           LARGE_INTEGER __attribute__ ((__mode__ (__DI__)));
 typedef char           CHAR;
 typedef short          SHORT;
 typedef long           LARGE_INTEGER __attribute__ ((__mode__ (__DI__)));

-typedef        long            LONG __attribute__ ((__mode__ (__SI__)));
+typedef long           LONG __attribute__ ((__mode__ (__SI__)));

 typedef unsigned char  UCHAR;
 typedef unsigned short USHORT;
 typedef unsigned long  ULONG __attribute__ ((__mode__ (__SI__)));
 typedef unsigned char  UCHAR;
 typedef unsigned short USHORT;
 typedef unsigned long  ULONG __attribute__ ((__mode__ (__SI__)));


@@ -23,11 +23,11 @@ typedef void                VOID;
 
 /* The pointer types.  Note that we're using a 64-bit compiler but all
    pointer in the ARC structures are only 32-bit, so we need some disgusting
 
 /* The pointer types.  Note that we're using a 64-bit compiler but all
    pointer in the ARC structures are only 32-bit, so we need some disgusting

-   workarounds.  Keep your vomit bag handy.  */
+   workarounds.         Keep your vomit bag handy.  */

 typedef LONG           _PCHAR;
 typedef LONG           _PSHORT;
 typedef LONG           _PLARGE_INTEGER;
 typedef LONG           _PCHAR;
 typedef LONG           _PSHORT;
 typedef LONG           _PLARGE_INTEGER;

-typedef        LONG            _PLONG;
+typedef LONG           _PLONG;

 typedef LONG           _PUCHAR;
 typedef LONG           _PUSHORT;
 typedef LONG           _PULONG;
 typedef LONG           _PUCHAR;
 typedef LONG           _PUSHORT;
 typedef LONG           _PULONG;


@@ -40,7 +40,7 @@ typedef LONG          _PVOID;
 typedef char           CHAR;
 typedef short          SHORT;
 typedef long           LARGE_INTEGER __attribute__ ((__mode__ (__DI__)));
 typedef char           CHAR;
 typedef short          SHORT;
 typedef long           LARGE_INTEGER __attribute__ ((__mode__ (__DI__)));

-typedef        long            LONG __attribute__ ((__mode__ (__DI__)));
+typedef long           LONG __attribute__ ((__mode__ (__DI__)));

 typedef unsigned char  UCHAR;
 typedef unsigned short USHORT;
 typedef unsigned long  ULONG __attribute__ ((__mode__ (__DI__)));
 typedef unsigned char  UCHAR;
 typedef unsigned short USHORT;
 typedef unsigned long  ULONG __attribute__ ((__mode__ (__DI__)));


@@ -51,7 +51,7 @@ typedef void          VOID;
 typedef CHAR           *_PCHAR;
 typedef SHORT          *_PSHORT;
 typedef LARGE_INTEGER  *_PLARGE_INTEGER;
 typedef CHAR           *_PCHAR;
 typedef SHORT          *_PSHORT;
 typedef LARGE_INTEGER  *_PLARGE_INTEGER;

-typedef        LONG            *_PLONG;
+typedef LONG           *_PLONG;

 typedef UCHAR          *_PUCHAR;
 typedef USHORT         *_PUSHORT;
 typedef ULONG          *_PULONG;
 typedef UCHAR          *_PUCHAR;
 typedef USHORT         *_PUSHORT;
 typedef ULONG          *_PULONG;


@@ -62,7 +62,7 @@ typedef VOID          *_PVOID;
 typedef CHAR           *PCHAR;
 typedef SHORT          *PSHORT;
 typedef LARGE_INTEGER  *PLARGE_INTEGER;
 typedef CHAR           *PCHAR;
 typedef SHORT          *PSHORT;
 typedef LARGE_INTEGER  *PLARGE_INTEGER;

-typedef        LONG            *PLONG;
+typedef LONG           *PLONG;

 typedef UCHAR          *PUCHAR;
 typedef USHORT         *PUSHORT;
 typedef ULONG          *PULONG;
 typedef UCHAR          *PUCHAR;
 typedef USHORT         *PUSHORT;
 typedef ULONG          *PULONG;

diff --git a/arch/mips/include/asm/fw/cfe/cfe_api.h b/arch/mips/include/asm/fw/cfe/cfe_api.h
index 0995575db320eaf72e9e45d84009308954bc44f4..17347551a1b2afd930340f0ea99b973d230594b5 100644 (file)
--- a/arch/mips/include/asm/fw/cfe/cfe_api.h
+++ b/arch/mips/include/asm/fw/cfe/cfe_api.h
@@ -40,7 +40,7 @@ typedef long intptr_t;
 /* Seal indicating CFE's presence, passed to user program. */
 #define CFE_EPTSEAL 0x43464531
 
 /* Seal indicating CFE's presence, passed to user program. */
 #define CFE_EPTSEAL 0x43464531
 

-#define CFE_MI_RESERVED        0       /* memory is reserved, do not use */
+#define CFE_MI_RESERVED 0      /* memory is reserved, do not use */

 #define CFE_MI_AVAILABLE 1     /* memory is available */
 
 #define CFE_FLG_WARMSTART     0x00000001
 #define CFE_MI_AVAILABLE 1     /* memory is available */
 
 #define CFE_FLG_WARMSTART     0x00000001


@@ -52,13 +52,13 @@ typedef long intptr_t;
 
 #define CFE_STDHANDLE_CONSOLE  0
 
 
 #define CFE_STDHANDLE_CONSOLE  0
 

-#define CFE_DEV_NETWORK        1
+#define CFE_DEV_NETWORK                1

 #define CFE_DEV_DISK           2
 #define CFE_DEV_FLASH          3
 #define CFE_DEV_SERIAL         4
 #define CFE_DEV_CPU            5
 #define CFE_DEV_NVRAM          6
 #define CFE_DEV_DISK           2
 #define CFE_DEV_FLASH          3
 #define CFE_DEV_SERIAL         4
 #define CFE_DEV_CPU            5
 #define CFE_DEV_NVRAM          6

-#define CFE_DEV_CLOCK           7
+#define CFE_DEV_CLOCK          7

 #define CFE_DEV_OTHER          8
 #define CFE_DEV_MASK           0x0F
 
 #define CFE_DEV_OTHER          8
 #define CFE_DEV_MASK           0x0F
 

diff --git a/arch/mips/include/asm/fw/cfe/cfe_error.h b/arch/mips/include/asm/fw/cfe/cfe_error.h
index b80374636279ae58753705061271a490cea41677..fc0e91f07e225ae177b0bd2e6199aa136ad263d7 100644 (file)
--- a/arch/mips/include/asm/fw/cfe/cfe_error.h
+++ b/arch/mips/include/asm/fw/cfe/cfe_error.h
@@ -25,7 +25,7 @@
  */
 
 #define CFE_OK                  0
  */
 
 #define CFE_OK                  0

-#define CFE_ERR                 -1     /* generic error */
+#define CFE_ERR                        -1      /* generic error */

 #define CFE_ERR_INV_COMMAND    -2
 #define CFE_ERR_EOF            -3
 #define CFE_ERR_IOERR          -4
 #define CFE_ERR_INV_COMMAND    -2
 #define CFE_ERR_EOF            -3
 #define CFE_ERR_IOERR          -4


@@ -37,12 +37,12 @@
 #define CFE_ERR_ENVREADONLY    -10
 
 #define CFE_ERR_NOTELF         -11
 #define CFE_ERR_ENVREADONLY    -10
 
 #define CFE_ERR_NOTELF         -11

-#define CFE_ERR_NOT32BIT       -12
-#define CFE_ERR_WRONGENDIAN    -13
-#define CFE_ERR_BADELFVERS     -14
-#define CFE_ERR_NOTMIPS        -15
-#define CFE_ERR_BADELFFMT      -16
-#define CFE_ERR_BADADDR        -17
+#define CFE_ERR_NOT32BIT       -12
+#define CFE_ERR_WRONGENDIAN    -13
+#define CFE_ERR_BADELFVERS     -14
+#define CFE_ERR_NOTMIPS                -15
+#define CFE_ERR_BADELFFMT      -16
+#define CFE_ERR_BADADDR                -17

 
 #define CFE_ERR_FILENOTFOUND   -18
 #define CFE_ERR_UNSUPPORTED    -19
 
 #define CFE_ERR_FILENOTFOUND   -18
 #define CFE_ERR_UNSUPPORTED    -19


@@ -73,8 +73,8 @@
 
 #define CFE_ERR_NOTREADY       -36
 
 
 #define CFE_ERR_NOTREADY       -36
 

-#define CFE_ERR_GETMEM          -37
-#define CFE_ERR_SETMEM          -38
+#define CFE_ERR_GETMEM         -37
+#define CFE_ERR_SETMEM         -38

 
 #define CFE_ERR_NOTCONN                -39
 #define CFE_ERR_ADDRINUSE      -40
 
 #define CFE_ERR_NOTCONN                -39
 #define CFE_ERR_ADDRINUSE      -40

diff --git a/arch/mips/include/asm/gcmpregs.h b/arch/mips/include/asm/gcmpregs.h
index c0cf76a2ca890a8ace9f0e4caec0377eef7bd8d7..a7359f77a48eaa9f65e34c74b146d0ec7dc9e79a 100644 (file)
--- a/arch/mips/include/asm/gcmpregs.h
+++ b/arch/mips/include/asm/gcmpregs.h
@@ -32,7 +32,7 @@
 
 /* GCMP register access */
 #define GCMPGCB(reg)                   REGP(_gcmp_base, GCMPGCBOFS(reg))
 
 /* GCMP register access */
 #define GCMPGCB(reg)                   REGP(_gcmp_base, GCMPGCBOFS(reg))

-#define GCMPGCBn(reg, n)               REGP(_gcmp_base, GCMPGCBOFSn(reg, n))
+#define GCMPGCBn(reg, n)              REGP(_gcmp_base, GCMPGCBOFSn(reg, n))

 #define GCMPCLCB(reg)                  REGP(_gcmp_base, GCMPCLCBOFS(reg))
 #define GCMPCOCB(reg)                  REGP(_gcmp_base, GCMPCOCBOFS(reg))
 #define GCMPGDB(reg)                   REGP(_gcmp_base, GCMPGDBOFS(reg))
 #define GCMPCLCB(reg)                  REGP(_gcmp_base, GCMPCLCBOFS(reg))
 #define GCMPCOCB(reg)                  REGP(_gcmp_base, GCMPCOCBOFS(reg))
 #define GCMPGDB(reg)                   REGP(_gcmp_base, GCMPGDBOFS(reg))


@@ -45,76 +45,76 @@
 
 /* GCB registers */
 #define GCMP_GCB_GC_OFS                        0x0000  /* Global Config Register */
 
 /* GCB registers */
 #define GCMP_GCB_GC_OFS                        0x0000  /* Global Config Register */

-#define  GCMP_GCB_GC_NUMIOCU_SHF       8
-#define  GCMP_GCB_GC_NUMIOCU_MSK       GCMPGCBMSK(GC_NUMIOCU, 4)
-#define  GCMP_GCB_GC_NUMCORES_SHF      0
-#define  GCMP_GCB_GC_NUMCORES_MSK      GCMPGCBMSK(GC_NUMCORES, 8)
+#define         GCMP_GCB_GC_NUMIOCU_SHF        8
+#define         GCMP_GCB_GC_NUMIOCU_MSK        GCMPGCBMSK(GC_NUMIOCU, 4)
+#define         GCMP_GCB_GC_NUMCORES_SHF       0
+#define         GCMP_GCB_GC_NUMCORES_MSK       GCMPGCBMSK(GC_NUMCORES, 8)

 #define GCMP_GCB_GCMPB_OFS             0x0008          /* Global GCMP Base */
 #define GCMP_GCB_GCMPB_OFS             0x0008          /* Global GCMP Base */

-#define  GCMP_GCB_GCMPB_GCMPBASE_SHF   15
-#define  GCMP_GCB_GCMPB_GCMPBASE_MSK   GCMPGCBMSK(GCMPB_GCMPBASE, 17)
-#define  GCMP_GCB_GCMPB_CMDEFTGT_SHF   0
-#define  GCMP_GCB_GCMPB_CMDEFTGT_MSK   GCMPGCBMSK(GCMPB_CMDEFTGT, 2)
-#define  GCMP_GCB_GCMPB_CMDEFTGT_DISABLED      0
-#define  GCMP_GCB_GCMPB_CMDEFTGT_MEM           1
-#define  GCMP_GCB_GCMPB_CMDEFTGT_IOCU1         2
-#define  GCMP_GCB_GCMPB_CMDEFTGT_IOCU2         3
+#define         GCMP_GCB_GCMPB_GCMPBASE_SHF    15
+#define         GCMP_GCB_GCMPB_GCMPBASE_MSK    GCMPGCBMSK(GCMPB_GCMPBASE, 17)
+#define         GCMP_GCB_GCMPB_CMDEFTGT_SHF    0
+#define         GCMP_GCB_GCMPB_CMDEFTGT_MSK    GCMPGCBMSK(GCMPB_CMDEFTGT, 2)
+#define         GCMP_GCB_GCMPB_CMDEFTGT_DISABLED       0
+#define         GCMP_GCB_GCMPB_CMDEFTGT_MEM            1
+#define         GCMP_GCB_GCMPB_CMDEFTGT_IOCU1          2
+#define         GCMP_GCB_GCMPB_CMDEFTGT_IOCU2          3

 #define GCMP_GCB_CCMC_OFS              0x0010  /* Global CM Control */
 #define GCMP_GCB_GCSRAP_OFS            0x0020  /* Global CSR Access Privilege */
 #define GCMP_GCB_CCMC_OFS              0x0010  /* Global CM Control */
 #define GCMP_GCB_GCSRAP_OFS            0x0020  /* Global CSR Access Privilege */

-#define  GCMP_GCB_GCSRAP_CMACCESS_SHF  0
-#define  GCMP_GCB_GCSRAP_CMACCESS_MSK  GCMPGCBMSK(GCSRAP_CMACCESS, 8)
+#define         GCMP_GCB_GCSRAP_CMACCESS_SHF   0
+#define         GCMP_GCB_GCSRAP_CMACCESS_MSK   GCMPGCBMSK(GCSRAP_CMACCESS, 8)

 #define GCMP_GCB_GCMPREV_OFS           0x0030  /* GCMP Revision Register */
 #define GCMP_GCB_GCMEM_OFS             0x0040  /* Global CM Error Mask */
 #define GCMP_GCB_GCMEC_OFS             0x0048  /* Global CM Error Cause */
 #define GCMP_GCB_GCMPREV_OFS           0x0030  /* GCMP Revision Register */
 #define GCMP_GCB_GCMEM_OFS             0x0040  /* Global CM Error Mask */
 #define GCMP_GCB_GCMEC_OFS             0x0048  /* Global CM Error Cause */

-#define  GCMP_GCB_GMEC_ERROR_TYPE_SHF  27
-#define  GCMP_GCB_GMEC_ERROR_TYPE_MSK  GCMPGCBMSK(GMEC_ERROR_TYPE, 5)
-#define  GCMP_GCB_GMEC_ERROR_INFO_SHF  0
-#define  GCMP_GCB_GMEC_ERROR_INFO_MSK  GCMPGCBMSK(GMEC_ERROR_INFO, 27)
+#define         GCMP_GCB_GMEC_ERROR_TYPE_SHF   27
+#define         GCMP_GCB_GMEC_ERROR_TYPE_MSK   GCMPGCBMSK(GMEC_ERROR_TYPE, 5)
+#define         GCMP_GCB_GMEC_ERROR_INFO_SHF   0
+#define         GCMP_GCB_GMEC_ERROR_INFO_MSK   GCMPGCBMSK(GMEC_ERROR_INFO, 27)

 #define GCMP_GCB_GCMEA_OFS             0x0050  /* Global CM Error Address */
 #define GCMP_GCB_GCMEO_OFS             0x0058  /* Global CM Error Multiple */
 #define GCMP_GCB_GCMEA_OFS             0x0050  /* Global CM Error Address */
 #define GCMP_GCB_GCMEO_OFS             0x0058  /* Global CM Error Multiple */

-#define  GCMP_GCB_GMEO_ERROR_2ND_SHF   0
-#define  GCMP_GCB_GMEO_ERROR_2ND_MSK   GCMPGCBMSK(GMEO_ERROR_2ND, 5)
+#define         GCMP_GCB_GMEO_ERROR_2ND_SHF    0
+#define         GCMP_GCB_GMEO_ERROR_2ND_MSK    GCMPGCBMSK(GMEO_ERROR_2ND, 5)

 #define GCMP_GCB_GICBA_OFS             0x0080  /* Global Interrupt Controller Base Address */
 #define GCMP_GCB_GICBA_OFS             0x0080  /* Global Interrupt Controller Base Address */

-#define  GCMP_GCB_GICBA_BASE_SHF       17
-#define  GCMP_GCB_GICBA_BASE_MSK       GCMPGCBMSK(GICBA_BASE, 15)
-#define  GCMP_GCB_GICBA_EN_SHF         0
-#define  GCMP_GCB_GICBA_EN_MSK         GCMPGCBMSK(GICBA_EN, 1)
+#define         GCMP_GCB_GICBA_BASE_SHF        17
+#define         GCMP_GCB_GICBA_BASE_MSK        GCMPGCBMSK(GICBA_BASE, 15)
+#define         GCMP_GCB_GICBA_EN_SHF          0
+#define         GCMP_GCB_GICBA_EN_MSK          GCMPGCBMSK(GICBA_EN, 1)

 
 /* GCB Regions */
 #define GCMP_GCB_CMxBASE_OFS(n)                (0x0090+16*(n))         /* Global Region[0-3] Base Address */
 
 /* GCB Regions */
 #define GCMP_GCB_CMxBASE_OFS(n)                (0x0090+16*(n))         /* Global Region[0-3] Base Address */

-#define  GCMP_GCB_CMxBASE_BASE_SHF     16
-#define  GCMP_GCB_CMxBASE_BASE_MSK     GCMPGCBMSK(CMxBASE_BASE, 16)
+#define         GCMP_GCB_CMxBASE_BASE_SHF      16
+#define         GCMP_GCB_CMxBASE_BASE_MSK      GCMPGCBMSK(CMxBASE_BASE, 16)

 #define GCMP_GCB_CMxMASK_OFS(n)                (0x0098+16*(n))         /* Global Region[0-3] Address Mask */
 #define GCMP_GCB_CMxMASK_OFS(n)                (0x0098+16*(n))         /* Global Region[0-3] Address Mask */

-#define  GCMP_GCB_CMxMASK_MASK_SHF     16
-#define  GCMP_GCB_CMxMASK_MASK_MSK     GCMPGCBMSK(CMxMASK_MASK, 16)
-#define  GCMP_GCB_CMxMASK_CMREGTGT_SHF 0
-#define  GCMP_GCB_CMxMASK_CMREGTGT_MSK GCMPGCBMSK(CMxMASK_CMREGTGT, 2)
-#define  GCMP_GCB_CMxMASK_CMREGTGT_MEM  0
-#define  GCMP_GCB_CMxMASK_CMREGTGT_MEM1  1
-#define  GCMP_GCB_CMxMASK_CMREGTGT_IOCU1 2
-#define  GCMP_GCB_CMxMASK_CMREGTGT_IOCU2 3
+#define         GCMP_GCB_CMxMASK_MASK_SHF      16
+#define         GCMP_GCB_CMxMASK_MASK_MSK      GCMPGCBMSK(CMxMASK_MASK, 16)
+#define         GCMP_GCB_CMxMASK_CMREGTGT_SHF  0
+#define         GCMP_GCB_CMxMASK_CMREGTGT_MSK  GCMPGCBMSK(CMxMASK_CMREGTGT, 2)
+#define         GCMP_GCB_CMxMASK_CMREGTGT_MEM   0
+#define         GCMP_GCB_CMxMASK_CMREGTGT_MEM1  1
+#define         GCMP_GCB_CMxMASK_CMREGTGT_IOCU1 2
+#define         GCMP_GCB_CMxMASK_CMREGTGT_IOCU2 3

 
 
 /* Core local/Core other control block registers */
 #define GCMP_CCB_RESETR_OFS            0x0000                  /* Reset Release */
 
 
 /* Core local/Core other control block registers */
 #define GCMP_CCB_RESETR_OFS            0x0000                  /* Reset Release */

-#define  GCMP_CCB_RESETR_INRESET_SHF   0
-#define  GCMP_CCB_RESETR_INRESET_MSK   GCMPCCBMSK(RESETR_INRESET, 16)
+#define         GCMP_CCB_RESETR_INRESET_SHF    0
+#define         GCMP_CCB_RESETR_INRESET_MSK    GCMPCCBMSK(RESETR_INRESET, 16)

 #define GCMP_CCB_COHCTL_OFS            0x0008                  /* Coherence Control */
 #define GCMP_CCB_COHCTL_OFS            0x0008                  /* Coherence Control */

-#define  GCMP_CCB_COHCTL_DOMAIN_SHF    0
-#define  GCMP_CCB_COHCTL_DOMAIN_MSK    GCMPCCBMSK(COHCTL_DOMAIN, 8)
+#define         GCMP_CCB_COHCTL_DOMAIN_SHF     0
+#define         GCMP_CCB_COHCTL_DOMAIN_MSK     GCMPCCBMSK(COHCTL_DOMAIN, 8)

 #define GCMP_CCB_CFG_OFS               0x0010                  /* Config */
 #define GCMP_CCB_CFG_OFS               0x0010                  /* Config */

-#define  GCMP_CCB_CFG_IOCUTYPE_SHF     10
-#define  GCMP_CCB_CFG_IOCUTYPE_MSK     GCMPCCBMSK(CFG_IOCUTYPE, 2)
-#define   GCMP_CCB_CFG_IOCUTYPE_CPU    0
-#define   GCMP_CCB_CFG_IOCUTYPE_NCIOCU 1
-#define   GCMP_CCB_CFG_IOCUTYPE_CIOCU  2
-#define  GCMP_CCB_CFG_NUMVPE_SHF       0
-#define  GCMP_CCB_CFG_NUMVPE_MSK       GCMPCCBMSK(CFG_NUMVPE, 10)
+#define         GCMP_CCB_CFG_IOCUTYPE_SHF      10
+#define         GCMP_CCB_CFG_IOCUTYPE_MSK      GCMPCCBMSK(CFG_IOCUTYPE, 2)
+#define          GCMP_CCB_CFG_IOCUTYPE_CPU     0
+#define          GCMP_CCB_CFG_IOCUTYPE_NCIOCU  1
+#define          GCMP_CCB_CFG_IOCUTYPE_CIOCU   2
+#define         GCMP_CCB_CFG_NUMVPE_SHF        0
+#define         GCMP_CCB_CFG_NUMVPE_MSK        GCMPCCBMSK(CFG_NUMVPE, 10)

 #define GCMP_CCB_OTHER_OFS             0x0018          /* Other Address */
 #define GCMP_CCB_OTHER_OFS             0x0018          /* Other Address */

-#define  GCMP_CCB_OTHER_CORENUM_SHF    16
-#define  GCMP_CCB_OTHER_CORENUM_MSK    GCMPCCBMSK(OTHER_CORENUM, 16)
+#define         GCMP_CCB_OTHER_CORENUM_SHF     16
+#define         GCMP_CCB_OTHER_CORENUM_MSK     GCMPCCBMSK(OTHER_CORENUM, 16)

 #define GCMP_CCB_RESETBASE_OFS         0x0020          /* Reset Exception Base */
 #define GCMP_CCB_RESETBASE_OFS         0x0020          /* Reset Exception Base */

-#define  GCMP_CCB_RESETBASE_BEV_SHF    12
-#define  GCMP_CCB_RESETBASE_BEV_MSK    GCMPCCBMSK(RESETBASE_BEV, 20)
+#define         GCMP_CCB_RESETBASE_BEV_SHF     12
+#define         GCMP_CCB_RESETBASE_BEV_MSK     GCMPCCBMSK(RESETBASE_BEV, 20)

 #define GCMP_CCB_ID_OFS                        0x0028          /* Identification */
 #define GCMP_CCB_DINTGROUP_OFS         0x0030          /* DINT Group Participate */
 #define GCMP_CCB_DBGGROUP_OFS          0x0100          /* DebugBreak Group */
 #define GCMP_CCB_ID_OFS                        0x0028          /* Identification */
 #define GCMP_CCB_DINTGROUP_OFS         0x0030          /* DINT Group Participate */
 #define GCMP_CCB_DBGGROUP_OFS          0x0100          /* DebugBreak Group */

diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index 37620db588be899ec8725ec9e744332bae7d8f1b..61b06d7e7de1e955f88616158a8d77832c39a4d4 100644 (file)
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -66,7 +66,7 @@
 
 /* Register Map for Shared Section */
 
 
 /* Register Map for Shared Section */
 

-#define        GIC_SH_CONFIG_OFS               0x0000
+#define GIC_SH_CONFIG_OFS              0x0000

 
 /* Shared Global Counter */
 #define GIC_SH_COUNTER_31_00_OFS       0x0010
 
 /* Shared Global Counter */
 #define GIC_SH_COUNTER_31_00_OFS       0x0010


@@ -146,13 +146,13 @@
 #define GIC_SH_PEND_223_192_OFS                0x0498
 #define GIC_SH_PEND_255_224_OFS                0x049c
 
 #define GIC_SH_PEND_223_192_OFS                0x0498
 #define GIC_SH_PEND_255_224_OFS                0x049c
 

-#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS        0x0500
+#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500

 
 /* Maps Interrupt X to a Pin */
 #define GIC_SH_MAP_TO_PIN(intr) \
        (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
 
 
 /* Maps Interrupt X to a Pin */
 #define GIC_SH_MAP_TO_PIN(intr) \
        (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
 

-#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS        0x2000
+#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000

 
 /* Maps Interrupt X to a VPE */
 #define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
 
 /* Maps Interrupt X to a VPE */
 #define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \


@@ -326,7 +326,7 @@ struct gic_intr_map {
        unsigned int polarity;  /* Polarity : +/-       */
        unsigned int trigtype;  /* Trigger  : Edge/Levl */
        unsigned int flags;     /* Misc flags   */
        unsigned int polarity;  /* Polarity : +/-       */
        unsigned int trigtype;  /* Trigger  : Edge/Levl */
        unsigned int flags;     /* Misc flags   */

-#define GIC_FLAG_IPI           0x01
+#define GIC_FLAG_IPI          0x01

 #define GIC_FLAG_TRANSPARENT   0x02
 };
 
 #define GIC_FLAG_TRANSPARENT   0x02
 };
 


@@ -343,10 +343,10 @@ struct gic_shared_intr_map {
 
 /* GIC nomenclature for Core Interrupt Pins. */
 #define GIC_CPU_INT0           0 /* Core Interrupt 2 */
 
 /* GIC nomenclature for Core Interrupt Pins. */
 #define GIC_CPU_INT0           0 /* Core Interrupt 2 */

-#define GIC_CPU_INT1           1 /* .                */
-#define GIC_CPU_INT2           2 /* .                */
-#define GIC_CPU_INT3           3 /* .                */
-#define GIC_CPU_INT4           4 /* .                */
+#define GIC_CPU_INT1           1 /* .                */
+#define GIC_CPU_INT2           2 /* .                */
+#define GIC_CPU_INT3           3 /* .                */
+#define GIC_CPU_INT4           4 /* .                */

 #define GIC_CPU_INT5           5 /* Core Interrupt 5 */
 
 /* Local GIC interrupts. */
 #define GIC_CPU_INT5           5 /* Core Interrupt 5 */
 
 /* Local GIC interrupts. */

diff --git a/arch/mips/include/asm/gio_device.h b/arch/mips/include/asm/gio_device.h
index 5437c84664bfc80bb15901442b080c3753186163..0878701712f8dd90dd829b2d2edd51610cdd1449 100644 (file)
--- a/arch/mips/include/asm/gio_device.h
+++ b/arch/mips/include/asm/gio_device.h
@@ -6,15 +6,15 @@ struct gio_device_id {
 };
 
 struct gio_device {
 };
 
 struct gio_device {

-       struct device   dev;
+       struct device   dev;

        struct resource resource;
        struct resource resource;

-       unsigned int    irq;
-       unsigned int    slotno;
+       unsigned int    irq;
+       unsigned int    slotno;

 
 

-       const char      *name;
+       const char      *name;

        struct gio_device_id id;
        struct gio_device_id id;

-       unsigned        id32:1;
-       unsigned        gio64:1;
+       unsigned        id32:1;
+       unsigned        gio64:1;

 };
 #define to_gio_device(d) container_of(d, struct gio_device, dev)
 
 };
 #define to_gio_device(d) container_of(d, struct gio_device, dev)
 


@@ -50,7 +50,7 @@ static inline void gio_device_free(struct gio_device *dev)
 extern int gio_register_driver(struct gio_driver *);
 extern void gio_unregister_driver(struct gio_driver *);
 
 extern int gio_register_driver(struct gio_driver *);
 extern void gio_unregister_driver(struct gio_driver *);
 

-#define gio_get_drvdata(_dev)        drv_get_drvdata(&(_dev)->dev)
+#define gio_get_drvdata(_dev)       drv_get_drvdata(&(_dev)->dev)

 #define gio_set_drvdata(_dev, data)  drv_set_drvdata(&(_dev)->dev, (data))
 
 extern void gio_set_master(struct gio_device *);
 #define gio_set_drvdata(_dev, data)  drv_set_drvdata(&(_dev)->dev, (data))
 
 extern void gio_set_master(struct gio_device *);

diff --git a/arch/mips/include/asm/gt64120.h b/arch/mips/include/asm/gt64120.h
index 0aa44abc77fe588835334d9c164701b20af4d626..2e72abb9440e3d12ccf7bcfd43031c91f0dc2a41 100644 (file)
--- a/arch/mips/include/asm/gt64120.h
+++ b/arch/mips/include/asm/gt64120.h
@@ -34,7 +34,7 @@
 
 #define GT_MULTI_OFS           0x120
 
 
 #define GT_MULTI_OFS           0x120
 

-/* CPU Address Decode.  */
+/* CPU Address Decode. */

 #define GT_SCS10LD_OFS         0x008
 #define GT_SCS10HD_OFS         0x010
 #define GT_SCS32LD_OFS         0x018
 #define GT_SCS10LD_OFS         0x008
 #define GT_SCS10HD_OFS         0x010
 #define GT_SCS32LD_OFS         0x018


@@ -106,12 +106,12 @@
 
 #define GT_ADERR_OFS           0x470
 
 
 #define GT_ADERR_OFS           0x470
 

-/* SDRAM Configuration.  */
+/* SDRAM Configuration.         */

 #define GT_SDRAM_CFG_OFS       0x448
 
 #define GT_SDRAM_OPMODE_OFS    0x474
 #define GT_SDRAM_BM_OFS                0x478
 #define GT_SDRAM_CFG_OFS       0x448
 
 #define GT_SDRAM_OPMODE_OFS    0x474
 #define GT_SDRAM_BM_OFS                0x478

-#define GT_SDRAM_ADDRDECODE_OFS        0x47c
+#define GT_SDRAM_ADDRDECODE_OFS 0x47c

 
 /* SDRAM Parameters.  */
 #define GT_SDRAM_B0_OFS                0x44c
 
 /* SDRAM Parameters.  */
 #define GT_SDRAM_B0_OFS                0x44c


@@ -126,14 +126,14 @@
 #define GT_DEV_B3_OFS          0x468
 #define GT_DEV_BOOT_OFS                0x46c
 
 #define GT_DEV_B3_OFS          0x468
 #define GT_DEV_BOOT_OFS                0x46c
 

-/* ECC.  */
+/* ECC.         */

 #define GT_ECC_ERRDATALO       0x480                   /* GT-64120A only  */
 #define GT_ECC_ERRDATAHI       0x484                   /* GT-64120A only  */
 #define GT_ECC_MEM             0x488                   /* GT-64120A only  */
 #define GT_ECC_CALC            0x48c                   /* GT-64120A only  */
 #define GT_ECC_ERRADDR         0x490                   /* GT-64120A only  */
 
 #define GT_ECC_ERRDATALO       0x480                   /* GT-64120A only  */
 #define GT_ECC_ERRDATAHI       0x484                   /* GT-64120A only  */
 #define GT_ECC_MEM             0x488                   /* GT-64120A only  */
 #define GT_ECC_CALC            0x48c                   /* GT-64120A only  */
 #define GT_ECC_ERRADDR         0x490                   /* GT-64120A only  */
 

-/* DMA Record.  */
+/* DMA Record. */

 #define GT_DMA0_CNT_OFS                0x800
 #define GT_DMA1_CNT_OFS                0x804
 #define GT_DMA2_CNT_OFS                0x808
 #define GT_DMA0_CNT_OFS                0x800
 #define GT_DMA1_CNT_OFS                0x804
 #define GT_DMA2_CNT_OFS                0x808


@@ -156,13 +156,13 @@
 #define GT_DMA2_CUR_OFS                0x878
 #define GT_DMA3_CUR_OFS                0x87c
 
 #define GT_DMA2_CUR_OFS                0x878
 #define GT_DMA3_CUR_OFS                0x87c
 

-/* DMA Channel Control.  */
+/* DMA Channel Control.         */

 #define GT_DMA0_CTRL_OFS       0x840
 #define GT_DMA1_CTRL_OFS       0x844
 #define GT_DMA2_CTRL_OFS       0x848
 #define GT_DMA3_CTRL_OFS       0x84c
 
 #define GT_DMA0_CTRL_OFS       0x840
 #define GT_DMA1_CTRL_OFS       0x844
 #define GT_DMA2_CTRL_OFS       0x848
 #define GT_DMA3_CTRL_OFS       0x84c
 

-/* DMA Arbiter.  */
+/* DMA Arbiter.         */

 #define GT_DMA_ARB_OFS         0x860
 
 /* Timer/Counter.  */
 #define GT_DMA_ARB_OFS         0x860
 
 /* Timer/Counter.  */


@@ -220,7 +220,7 @@
 #define GT_PCI0_CFGADDR_OFS    0xcf8
 #define GT_PCI0_CFGDATA_OFS    0xcfc
 
 #define GT_PCI0_CFGADDR_OFS    0xcf8
 #define GT_PCI0_CFGDATA_OFS    0xcfc
 

-/* Interrupts.  */
+/* Interrupts. */

 #define GT_INTRCAUSE_OFS       0xc18
 #define GT_INTRMASK_OFS                0xc1c
 
 #define GT_INTRCAUSE_OFS       0xc18
 #define GT_INTRMASK_OFS                0xc1c
 


@@ -547,15 +547,15 @@
 #define GT_DEF_BASE            0x14000000UL
 
 #define GT_MAX_BANKSIZE                (256 * 1024 * 1024)     /* Max 256MB bank  */
 #define GT_DEF_BASE            0x14000000UL
 
 #define GT_MAX_BANKSIZE                (256 * 1024 * 1024)     /* Max 256MB bank  */

-#define GT_LATTIM_MIN          6                       /* Minimum lat  */
+#define GT_LATTIM_MIN          6                       /* Minimum lat  */

 
 /*
  * The gt64120_dep.h file must define the following macros
  *
  *   GT_READ(ofs, data_pointer)
 
 /*
  * The gt64120_dep.h file must define the following macros
  *
  *   GT_READ(ofs, data_pointer)

- *   GT_WRITE(ofs, data)           - read/write GT64120 registers in 32bit
+ *   GT_WRITE(ofs, data)          - read/write GT64120 registers in 32bit

  *
  *

- *   TIMER     - gt64120 timer irq, temporary solution until
+ *   TIMER     - gt64120 timer irq, temporary solution until

  *               full gt64120 cascade interrupt support is in place
  */
 
  *               full gt64120 cascade interrupt support is in place
  */
 

diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index f0324e92d0896824d593ac1194a96ed7fff182c9..568544b6e856eae34c84e534ec10b1a76d005b04 100644 (file)
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -25,7 +25,7 @@ static inline void name(void)                                         \
 }
 
 /*
 }
 
 /*

- * MIPS R2 instruction hazard barrier.   Needs to be called as a subroutine.
+ * MIPS R2 instruction hazard barrier.  Needs to be called as a subroutine.

  */
 extern void mips_ihb(void);
 
  */
 extern void mips_ihb(void);
 


@@ -68,7 +68,7 @@ ASMMACRO(back_to_back_c0_hazard,
        )
 /*
  * gcc has a tradition of misscompiling the previous construct using the
        )
 /*
  * gcc has a tradition of misscompiling the previous construct using the

- * address of a label as argument to inline assembler.  Gas otoh has the
+ * address of a label as argument to inline assembler. Gas otoh has the

  * annoying difference between la and dla which are only usable for 32-bit
  * rsp. 64-bit code, so can't be used without conditional compilation.
  * The alterantive is switching the assembler to 64-bit code which happens
  * annoying difference between la and dla which are only usable for 32-bit
  * rsp. 64-bit code, so can't be used without conditional compilation.
  * The alterantive is switching the assembler to 64-bit code which happens


@@ -114,7 +114,7 @@ ASMMACRO(back_to_back_c0_hazard,
        )
 /*
  * gcc has a tradition of misscompiling the previous construct using the
        )
 /*
  * gcc has a tradition of misscompiling the previous construct using the

- * address of a label as argument to inline assembler.  Gas otoh has the
+ * address of a label as argument to inline assembler. Gas otoh has the

  * annoying difference between la and dla which are only usable for 32-bit
  * rsp. 64-bit code, so can't be used without conditional compilation.
  * The alterantive is switching the assembler to 64-bit code which happens
  * annoying difference between la and dla which are only usable for 32-bit
  * rsp. 64-bit code, so can't be used without conditional compilation.
  * The alterantive is switching the assembler to 64-bit code which happens

diff --git a/arch/mips/include/asm/highmem.h b/arch/mips/include/asm/highmem.h
index 2d91888c9b744b5c29bd77c862896c5a229f5f4c..b0dd0c84df7040dadb1f8d82f5f8b849d2c5a5a4 100644 (file)
--- a/arch/mips/include/asm/highmem.h
+++ b/arch/mips/include/asm/highmem.h
@@ -39,8 +39,8 @@ extern pte_t *pkmap_page_table;
  */
 #define LAST_PKMAP 1024
 #define LAST_PKMAP_MASK (LAST_PKMAP-1)
  */
 #define LAST_PKMAP 1024
 #define LAST_PKMAP_MASK (LAST_PKMAP-1)

-#define PKMAP_NR(virt)  ((virt-PKMAP_BASE) >> PAGE_SHIFT)
-#define PKMAP_ADDR(nr)  (PKMAP_BASE + ((nr) << PAGE_SHIFT))
+#define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT)
+#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))

 
 extern void * kmap_high(struct page *page);
 extern void kunmap_high(struct page *page);
 
 extern void * kmap_high(struct page *page);
 extern void kunmap_high(struct page *page);

diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index ff2e0345e0132744eb57fcfc12969c950bc97bf0..1be13727323f7f2baf0395ee3360de5a78fcfaae 100644 (file)
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -7,7 +7,7 @@
  * Copyright (C) 1994 - 2000, 06 Ralf Baechle
  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  * Copyright (C) 2004, 2005  MIPS Technologies, Inc.  All rights reserved.
  * Copyright (C) 1994 - 2000, 06 Ralf Baechle
  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  * Copyright (C) 2004, 2005  MIPS Technologies, Inc.  All rights reserved.

- *     Author: Maciej W. Rozycki <macro@mips.com>
+ *     Author: Maciej W. Rozycki <macro@mips.com>

  */
 #ifndef _ASM_IO_H
 #define _ASM_IO_H
  */
 #ifndef _ASM_IO_H
 #define _ASM_IO_H


@@ -253,9 +253,9 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
        __ioremap_mode((offset), (size), _CACHE_UNCACHED)
 
 /*
        __ioremap_mode((offset), (size), _CACHE_UNCACHED)
 
 /*

- * ioremap_cachable -   map bus memory into CPU space
- * @offset:         bus address of the memory
- * @size:           size of the resource to map
+ * ioremap_cachable -  map bus memory into CPU space
+ * @offset:        bus address of the memory
+ * @size:          size of the resource to map

  *
  * ioremap_nocache performs a platform specific sequence of operations to
  * make bus memory CPU accessible via the readb/readw/readl/writeb/
  *
  * ioremap_nocache performs a platform specific sequence of operations to
  * make bus memory CPU accessible via the readb/readw/readl/writeb/


@@ -264,14 +264,14 @@ static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
  * address.
  *
  * This version of ioremap ensures that the memory is marked cachable by
  * address.
  *
  * This version of ioremap ensures that the memory is marked cachable by

- * the CPU.  Also enables full write-combining.  Useful for some
+ * the CPU.  Also enables full write-combining.         Useful for some

  * memory-like regions on I/O busses.
  */
 #define ioremap_cachable(offset, size)                                 \
        __ioremap_mode((offset), (size), _page_cachable_default)
 
 /*
  * memory-like regions on I/O busses.
  */
 #define ioremap_cachable(offset, size)                                 \
        __ioremap_mode((offset), (size), _page_cachable_default)
 
 /*

- * These two are MIPS specific ioremap variant.  ioremap_cacheable_cow
+ * These two are MIPS specific ioremap variant.         ioremap_cacheable_cow

  * requests a cachable mapping, ioremap_uncached_accelerated requests a
  * mapping using the uncached accelerated mode which isn't supported on
  * all processors.
  * requests a cachable mapping, ioremap_uncached_accelerated requests a
  * mapping using the uncached accelerated mode which isn't supported on
  * all processors.


@@ -298,7 +298,7 @@ static inline void iounmap(const volatile void __iomem *addr)
 }
 
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
 }
 
 #ifdef CONFIG_CPU_CAVIUM_OCTEON

-#define war_octeon_io_reorder_wmb()            wmb()
+#define war_octeon_io_reorder_wmb()            wmb()

 #else
 #define war_octeon_io_reorder_wmb()            do { } while (0)
 #endif
 #else
 #define war_octeon_io_reorder_wmb()            do { } while (0)
 #endif


@@ -317,7 +317,7 @@ static inline void pfx##write##bwlq(type val,                               \
                                                                        \
        __val = pfx##ioswab##bwlq(__mem, val);                          \
                                                                        \
                                                                        \
        __val = pfx##ioswab##bwlq(__mem, val);                          \
                                                                        \

-       if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
+       if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \

                *__mem = __val;                                         \
        else if (cpu_has_64bits) {                                      \
                unsigned long __flags;                                  \
                *__mem = __val;                                         \
        else if (cpu_has_64bits) {                                      \
                unsigned long __flags;                                  \


@@ -327,9 +327,9 @@ static inline void pfx##write##bwlq(type val,                               \
                        local_irq_save(__flags);                        \
                __asm__ __volatile__(                                   \
                        ".set   mips3"          "\t\t# __writeq""\n\t"  \
                        local_irq_save(__flags);                        \
                __asm__ __volatile__(                                   \
                        ".set   mips3"          "\t\t# __writeq""\n\t"  \

-                       "dsll32 %L0, %L0, 0"                    "\n\t"  \
-                       "dsrl32 %L0, %L0, 0"                    "\n\t"  \
-                       "dsll32 %M0, %M0, 0"                    "\n\t"  \
+                       "dsll32 %L0, %L0, 0"                    "\n\t"  \
+                       "dsrl32 %L0, %L0, 0"                    "\n\t"  \
+                       "dsll32 %M0, %M0, 0"                    "\n\t"  \

                        "or     %L0, %L0, %M0"                  "\n\t"  \
                        "sd     %L0, %2"                        "\n\t"  \
                        ".set   mips0"                          "\n"    \
                        "or     %L0, %L0, %M0"                  "\n\t"  \
                        "sd     %L0, %2"                        "\n\t"  \
                        ".set   mips0"                          "\n"    \


@@ -348,7 +348,7 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem)        \
                                                                        \
        __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
                                                                        \
                                                                        \
        __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
                                                                        \

-       if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
+       if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \

                __val = *__mem;                                         \
        else if (cpu_has_64bits) {                                      \
                unsigned long __flags;                                  \
                __val = *__mem;                                         \
        else if (cpu_has_64bits) {                                      \
                unsigned long __flags;                                  \


@@ -356,9 +356,9 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem)        \
                if (irq)                                                \
                        local_irq_save(__flags);                        \
                __asm__ __volatile__(                                   \
                if (irq)                                                \
                        local_irq_save(__flags);                        \
                __asm__ __volatile__(                                   \

-                       ".set   mips3"          "\t\t# __readq" "\n\t"  \
+                       ".set   mips3"          "\t\t# __readq" "\n\t"  \

                        "ld     %L0, %1"                        "\n\t"  \
                        "ld     %L0, %1"                        "\n\t"  \

-                       "dsra32 %M0, %L0, 0"                    "\n\t"  \
+                       "dsra32 %M0, %L0, 0"                    "\n\t"  \

                        "sll    %L0, %L0, 0"                    "\n\t"  \
                        ".set   mips0"                          "\n"    \
                        : "=r" (__val)                                  \
                        "sll    %L0, %L0, 0"                    "\n\t"  \
                        ".set   mips0"                          "\n"    \
                        : "=r" (__val)                                  \


@@ -586,7 +586,7 @@ extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
 
 #else /* Sane hardware */
 
 
 #else /* Sane hardware */
 

-#define dma_cache_wback_inv(start,size)        \
+#define dma_cache_wback_inv(start,size) \

        do { (void) (start); (void) (size); } while (0)
 #define dma_cache_wback(start,size)    \
        do { (void) (start); (void) (size); } while (0)
        do { (void) (start); (void) (size); } while (0)
 #define dma_cache_wback(start,size)    \
        do { (void) (start); (void) (size); } while (0)

diff --git a/arch/mips/include/asm/ip32/crime.h b/arch/mips/include/asm/ip32/crime.h
index 7c36b0e5b1c64b5879ea5546fd832de782887749..16c94a27bebad49963f25420c88d020ae1b281d1 100644 (file)
--- a/arch/mips/include/asm/ip32/crime.h
+++ b/arch/mips/include/asm/ip32/crime.h
@@ -74,7 +74,7 @@ struct sgi_crime {
 #define CRIME_RE_IDLE_E_INT            BIT(24)
 #define CRIME_RE_EMPTY_L_INT           BIT(25)
 #define CRIME_RE_FULL_L_INT            BIT(26)
 #define CRIME_RE_IDLE_E_INT            BIT(24)
 #define CRIME_RE_EMPTY_L_INT           BIT(25)
 #define CRIME_RE_FULL_L_INT            BIT(26)

-#define CRIME_RE_IDLE_L_INT                    BIT(27)
+#define CRIME_RE_IDLE_L_INT            BIT(27)

 #define CRIME_SOFT0_INT                        BIT(28)
 #define CRIME_SOFT1_INT                        BIT(29)
 #define CRIME_SOFT2_INT                        BIT(30)
 #define CRIME_SOFT0_INT                        BIT(28)
 #define CRIME_SOFT1_INT                        BIT(29)
 #define CRIME_SOFT2_INT                        BIT(30)


@@ -118,7 +118,7 @@ struct sgi_crime {
 #define CRIME_MEM_REF_COUNTER_MASK     0x3ff           /* 10bit */
 
        volatile unsigned long mem_error_stat;
 #define CRIME_MEM_REF_COUNTER_MASK     0x3ff           /* 10bit */
 
        volatile unsigned long mem_error_stat;

-#define CRIME_MEM_ERROR_STAT_MASK       0x0ff7ffff     /* 28-bit register */
+#define CRIME_MEM_ERROR_STAT_MASK      0x0ff7ffff      /* 28-bit register */

 #define CRIME_MEM_ERROR_MACE_ID                0x0000007f
 #define CRIME_MEM_ERROR_MACE_ACCESS    0x00000080
 #define CRIME_MEM_ERROR_RE_ID          0x00007f00
 #define CRIME_MEM_ERROR_MACE_ID                0x0000007f
 #define CRIME_MEM_ERROR_MACE_ACCESS    0x00000080
 #define CRIME_MEM_ERROR_RE_ID          0x00007f00


@@ -134,8 +134,8 @@ struct sgi_crime {
 #define CRIME_MEM_ERROR_MEM_ECC_RD     0x00800000
 #define CRIME_MEM_ERROR_MEM_ECC_RMW    0x01000000
 #define CRIME_MEM_ERROR_INV            0x0e000000
 #define CRIME_MEM_ERROR_MEM_ECC_RD     0x00800000
 #define CRIME_MEM_ERROR_MEM_ECC_RMW    0x01000000
 #define CRIME_MEM_ERROR_INV            0x0e000000

-#define CRIME_MEM_ERROR_INV_MEM_ADDR_RD        0x02000000
-#define CRIME_MEM_ERROR_INV_MEM_ADDR_WR        0x04000000
+#define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000
+#define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000

 #define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000
 
        volatile unsigned long mem_error_addr;
 #define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000
 
        volatile unsigned long mem_error_addr;

diff --git a/arch/mips/include/asm/ip32/ip32_ints.h b/arch/mips/include/asm/ip32/ip32_ints.h
index 85bc5302bce0142494a3a2e79599f1499e5f9780..72e3368de111a626aca995c12d18860a2d53c669 100644 (file)
--- a/arch/mips/include/asm/ip32/ip32_ints.h
+++ b/arch/mips/include/asm/ip32/ip32_ints.h
@@ -13,7 +13,7 @@
 
 /*
  * This list reflects the assignment of interrupt numbers to
 
 /*
  * This list reflects the assignment of interrupt numbers to

- * interrupting events.  Order is fairly irrelevant to handling
+ * interrupting events.         Order is fairly irrelevant to handling

  * priority.  This differs from irix.
  */
 
  * priority.  This differs from irix.
  */
 

diff --git a/arch/mips/include/asm/ip32/mace.h b/arch/mips/include/asm/ip32/mace.h
index c523123df380f41be9c131753f649e83fec5226d..253ed7ea80beaebcc0eff33f7740956204e30398 100644 (file)
--- a/arch/mips/include/asm/ip32/mace.h
+++ b/arch/mips/include/asm/ip32/mace.h
@@ -250,12 +250,12 @@ struct mace_ps2 {
  * -> drivers/i2c/algos/i2c-algo-sgi.c */
 struct mace_i2c {
        volatile unsigned long config;
  * -> drivers/i2c/algos/i2c-algo-sgi.c */
 struct mace_i2c {
        volatile unsigned long config;

-#define MACEI2C_RESET           BIT(0)
-#define MACEI2C_FAST            BIT(1)
-#define MACEI2C_DATA_OVERRIDE   BIT(2)
-#define MACEI2C_CLOCK_OVERRIDE  BIT(3)
-#define MACEI2C_DATA_STATUS     BIT(4)
-#define MACEI2C_CLOCK_STATUS    BIT(5)
+#define MACEI2C_RESET          BIT(0)
+#define MACEI2C_FAST           BIT(1)
+#define MACEI2C_DATA_OVERRIDE  BIT(2)
+#define MACEI2C_CLOCK_OVERRIDE BIT(3)
+#define MACEI2C_DATA_STATUS    BIT(4)
+#define MACEI2C_CLOCK_STATUS   BIT(5)

        volatile unsigned long control;
        volatile unsigned long data;
 };
        volatile unsigned long control;
        volatile unsigned long data;
 };

diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index 78dbb8a86da249d4bd4e6fa2db6b6c6b0c4bd4ed..7bc2cdb350578db2d2dcbf7108a0cc6a78e5235d 100644 (file)
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -32,7 +32,7 @@ struct irqaction;
 
 extern unsigned long irq_hwmask[];
 extern int setup_irq_smtc(unsigned int irq, struct irqaction * new,
 
 extern unsigned long irq_hwmask[];
 extern int setup_irq_smtc(unsigned int irq, struct irqaction * new,

-                          unsigned long hwmask);
+                         unsigned long hwmask);

 
 static inline void smtc_im_ack_irq(unsigned int irq)
 {
 
 static inline void smtc_im_ack_irq(unsigned int irq)
 {


@@ -60,7 +60,7 @@ extern void smtc_forward_irq(struct irq_data *d);
  * if option is enabled.
  *
  * Up through Linux 2.6.22 (at least) cpumask operations are very
  * if option is enabled.
  *
  * Up through Linux 2.6.22 (at least) cpumask operations are very

- * inefficient on MIPS.  Initial prototypes of SMTC IRQ affinity
+ * inefficient on MIPS.         Initial prototypes of SMTC IRQ affinity

  * used a "fast path" per-IRQ-descriptor cache of affinity information
  * to reduce latency.  As there is a project afoot to optimize the
  * cpumask implementations, this version is optimistically assuming
  * used a "fast path" per-IRQ-descriptor cache of affinity information
  * to reduce latency.  As there is a project afoot to optimize the
  * cpumask implementations, this version is optimistically assuming


@@ -133,7 +133,7 @@ extern void free_irqno(unsigned int irq);
 
 /*
  * Before R2 the timer and performance counter interrupts were both fixed to
 
 /*
  * Before R2 the timer and performance counter interrupts were both fixed to

- * IE7.  Since R2 their number has to be read from the c0_intctl register.
+ * IE7.         Since R2 their number has to be read from the c0_intctl register.

  */
 #define CP0_LEGACY_COMPARE_IRQ 7
 #define CP0_LEGACY_PERFCNT_IRQ 7
  */
 #define CP0_LEGACY_COMPARE_IRQ 7
 #define CP0_LEGACY_PERFCNT_IRQ 7

diff --git a/arch/mips/include/asm/isadep.h b/arch/mips/include/asm/isadep.h
index 24c6cda7937760e0ddd6e7ffa3d033b9e5ed4981..b4af6eb24ab9dfc90f992aec9c41162cf16c3581 100644 (file)
--- a/arch/mips/include/asm/isadep.h
+++ b/arch/mips/include/asm/isadep.h
@@ -18,7 +18,7 @@
  * kernel or user mode? (CP0_STATUS)
  */
 #define KU_MASK 0x08
  * kernel or user mode? (CP0_STATUS)
  */
 #define KU_MASK 0x08

-#define        KU_USER 0x08
+#define KU_USER 0x08

 #define KU_KERN 0x00
 
 #else
 #define KU_KERN 0x00
 
 #else


@@ -26,7 +26,7 @@
  * kernel or user mode?
  */
 #define KU_MASK 0x18
  * kernel or user mode?
  */
 #define KU_MASK 0x18

-#define        KU_USER 0x10
+#define KU_USER 0x10

 #define KU_KERN 0x00
 
 #endif
 #define KU_KERN 0x00
 
 #endif

diff --git a/arch/mips/include/asm/jazz.h b/arch/mips/include/asm/jazz.h
index 83f449dec95e98545fc951e40d1b22043790309f..a61970d01a81c030897438d85be354c4f940b1ef 100644 (file)
--- a/arch/mips/include/asm/jazz.h
+++ b/arch/mips/include/asm/jazz.h
@@ -16,7 +16,7 @@
  * instead of 0xe0000000.
  */
 
  * instead of 0xe0000000.
  */
 

-#define JAZZ_LOCAL_IO_SPACE     0xe0000000
+#define JAZZ_LOCAL_IO_SPACE    0xe0000000

 
 /*
  * Revision numbers in PICA_ASIC_REVISION
 
 /*
  * Revision numbers in PICA_ASIC_REVISION


@@ -25,24 +25,24 @@
  * 0xf0000001 - Rev2
  * 0xf0000002 - Rev3
  */
  * 0xf0000001 - Rev2
  * 0xf0000002 - Rev3
  */

-#define PICA_ASIC_REVISION      0xe0000008
+#define PICA_ASIC_REVISION     0xe0000008

 
 /*
  * The segments of the seven segment LED are mapped
  * to the control bits as follows:
  *
 
 /*
  * The segments of the seven segment LED are mapped
  * to the control bits as follows:
  *

- *         (7)
- *      ---------
- *      |       |
- *  (2) |       | (6)
- *      |  (1)  |
- *      ---------
- *      |       |
- *  (3) |       | (5)
- *      |  (4)  |
- *      --------- . (0)
+ *        (7)
+ *     ---------
+ *     |       |
+ *  (2) |      | (6)
+ *     |  (1)  |
+ *     ---------
+ *     |       |
+ *  (3) |      | (5)
+ *     |  (4)  |
+ *     --------- . (0)

  */
  */

-#define PICA_LED                0xe000f000
+#define PICA_LED               0xe000f000

 
 /*
  * Some characters for the LED control registers
 
 /*
  * Some characters for the LED control registers


@@ -51,24 +51,24 @@
  * control each of the seven segments and the dot independently.
  * It's only a toy, anyway...
  */
  * control each of the seven segments and the dot independently.
  * It's only a toy, anyway...
  */

-#define LED_DOT                 0x01
-#define LED_SPACE               0x00
-#define LED_0                   0xfc
-#define LED_1                   0x60
-#define LED_2                   0xda
-#define LED_3                   0xf2
-#define LED_4                   0x66
-#define LED_5                   0xb6
-#define LED_6                   0xbe
-#define LED_7                   0xe0
-#define LED_8                   0xfe
-#define LED_9                   0xf6
-#define LED_A                   0xee
-#define LED_b                   0x3e
-#define LED_C                   0x9c
-#define LED_d                   0x7a
-#define LED_E                   0x9e
-#define LED_F                   0x8e
+#define LED_DOT                        0x01
+#define LED_SPACE              0x00
+#define LED_0                  0xfc
+#define LED_1                  0x60
+#define LED_2                  0xda
+#define LED_3                  0xf2
+#define LED_4                  0x66
+#define LED_5                  0xb6
+#define LED_6                  0xbe
+#define LED_7                  0xe0
+#define LED_8                  0xfe
+#define LED_9                  0xf6
+#define LED_A                  0xee
+#define LED_b                  0x3e
+#define LED_C                  0x9c
+#define LED_d                  0x7a
+#define LED_E                  0x9e
+#define LED_F                  0x8e

 
 #ifndef __ASSEMBLY__
 
 
 #ifndef __ASSEMBLY__
 


@@ -96,9 +96,9 @@ static __inline__ void pica_set_led(unsigned int bits)
  * This address is just a guess and seems to differ from
  * other mips machines such as RC3xxx...
  */
  * This address is just a guess and seems to differ from
  * other mips machines such as RC3xxx...
  */

-#define JAZZ_KEYBOARD_ADDRESS   0xe0005000
-#define JAZZ_KEYBOARD_DATA      0xe0005000
-#define JAZZ_KEYBOARD_COMMAND   0xe0005001
+#define JAZZ_KEYBOARD_ADDRESS  0xe0005000
+#define JAZZ_KEYBOARD_DATA     0xe0005000
+#define JAZZ_KEYBOARD_COMMAND  0xe0005001

 
 #ifndef __ASSEMBLY__
 
 
 #ifndef __ASSEMBLY__
 


@@ -119,28 +119,28 @@ typedef struct {
 /*
  * For now. Needs to be changed for RC3xxx support. See below.
  */
 /*
  * For now. Needs to be changed for RC3xxx support. See below.
  */

-#define keyboard_hardware       jazz_keyboard_hardware
+#define keyboard_hardware      jazz_keyboard_hardware

 
 #endif /* !__ASSEMBLY__ */
 
 /*
  * i8042 keyboard controller for most other Mips machines.
  */
 
 #endif /* !__ASSEMBLY__ */
 
 /*
  * i8042 keyboard controller for most other Mips machines.
  */

-#define MIPS_KEYBOARD_ADDRESS   0xb9005000
-#define MIPS_KEYBOARD_DATA      0xb9005003
-#define MIPS_KEYBOARD_COMMAND   0xb9005007
+#define MIPS_KEYBOARD_ADDRESS  0xb9005000
+#define MIPS_KEYBOARD_DATA     0xb9005003
+#define MIPS_KEYBOARD_COMMAND  0xb9005007

 
 /*
  * Serial and parallel ports (WD 16C552) on the Mips JAZZ
  */
 
 /*
  * Serial and parallel ports (WD 16C552) on the Mips JAZZ
  */

-#define JAZZ_SERIAL1_BASE       (unsigned int)0xe0006000
-#define JAZZ_SERIAL2_BASE       (unsigned int)0xe0007000
-#define JAZZ_PARALLEL_BASE      (unsigned int)0xe0008000
+#define JAZZ_SERIAL1_BASE      (unsigned int)0xe0006000
+#define JAZZ_SERIAL2_BASE      (unsigned int)0xe0007000
+#define JAZZ_PARALLEL_BASE     (unsigned int)0xe0008000

 
 /*
  * Dummy Device Address. Used in jazzdma.c
  */
 
 /*
  * Dummy Device Address. Used in jazzdma.c
  */

-#define JAZZ_DUMMY_DEVICE       0xe000d000
+#define JAZZ_DUMMY_DEVICE      0xe000d000

 
 /*
  * JAZZ timer registers and interrupt no.
 
 /*
  * JAZZ timer registers and interrupt no.


@@ -148,8 +148,8 @@ typedef struct {
  * cpu level 6, but to keep compatibility with PC stuff
  * it is remapped to vector 0. See arch/mips/kernel/entry.S.
  */
  * cpu level 6, but to keep compatibility with PC stuff
  * it is remapped to vector 0. See arch/mips/kernel/entry.S.
  */

-#define JAZZ_TIMER_INTERVAL     0xe0000228
-#define JAZZ_TIMER_REGISTER     0xe0000230
+#define JAZZ_TIMER_INTERVAL    0xe0000228
+#define JAZZ_TIMER_REGISTER    0xe0000230

 
 /*
  * DRAM configuration register
 
 /*
  * DRAM configuration register


@@ -176,13 +176,13 @@ typedef struct {
 #endif
 #endif /* !__ASSEMBLY__ */
 
 #endif
 #endif /* !__ASSEMBLY__ */
 

-#define PICA_DRAM_CONFIG        0xe00fffe0
+#define PICA_DRAM_CONFIG       0xe00fffe0

 
 /*
  * JAZZ interrupt control registers
  */
 
 /*
  * JAZZ interrupt control registers
  */

-#define JAZZ_IO_IRQ_SOURCE      0xe0010000
-#define JAZZ_IO_IRQ_ENABLE      0xe0010002
+#define JAZZ_IO_IRQ_SOURCE     0xe0010000
+#define JAZZ_IO_IRQ_ENABLE     0xe0010002

 
 /*
  * JAZZ Interrupt Level definitions
 
 /*
  * JAZZ Interrupt Level definitions


@@ -190,20 +190,20 @@ typedef struct {
  * This is somewhat broken.  For reasons which nobody can remember anymore
  * we remap the Jazz interrupts to the usual ISA style interrupt numbers.
  */
  * This is somewhat broken.  For reasons which nobody can remember anymore
  * we remap the Jazz interrupts to the usual ISA style interrupt numbers.
  */

-#define JAZZ_IRQ_START          24
-#define JAZZ_IRQ_END            (24 + 9)
-#define JAZZ_PARALLEL_IRQ       (JAZZ_IRQ_START + 0)
-#define JAZZ_FLOPPY_IRQ         (JAZZ_IRQ_START + 1)
-#define JAZZ_SOUND_IRQ          (JAZZ_IRQ_START + 2)
-#define JAZZ_VIDEO_IRQ          (JAZZ_IRQ_START + 3)
-#define JAZZ_ETHERNET_IRQ       (JAZZ_IRQ_START + 4)
-#define JAZZ_SCSI_IRQ           (JAZZ_IRQ_START + 5)
-#define JAZZ_KEYBOARD_IRQ       (JAZZ_IRQ_START + 6)
-#define JAZZ_MOUSE_IRQ          (JAZZ_IRQ_START + 7)
-#define JAZZ_SERIAL1_IRQ        (JAZZ_IRQ_START + 8)
-#define JAZZ_SERIAL2_IRQ        (JAZZ_IRQ_START + 9)
-
-#define JAZZ_TIMER_IRQ          (MIPS_CPU_IRQ_BASE+6)
+#define JAZZ_IRQ_START         24
+#define JAZZ_IRQ_END           (24 + 9)
+#define JAZZ_PARALLEL_IRQ      (JAZZ_IRQ_START + 0)
+#define JAZZ_FLOPPY_IRQ                (JAZZ_IRQ_START + 1)
+#define JAZZ_SOUND_IRQ         (JAZZ_IRQ_START + 2)
+#define JAZZ_VIDEO_IRQ         (JAZZ_IRQ_START + 3)
+#define JAZZ_ETHERNET_IRQ      (JAZZ_IRQ_START + 4)
+#define JAZZ_SCSI_IRQ          (JAZZ_IRQ_START + 5)
+#define JAZZ_KEYBOARD_IRQ      (JAZZ_IRQ_START + 6)
+#define JAZZ_MOUSE_IRQ         (JAZZ_IRQ_START + 7)
+#define JAZZ_SERIAL1_IRQ       (JAZZ_IRQ_START + 8)
+#define JAZZ_SERIAL2_IRQ       (JAZZ_IRQ_START + 9)
+
+#define JAZZ_TIMER_IRQ         (MIPS_CPU_IRQ_BASE+6)

 
 
 /*
 
 
 /*


@@ -211,46 +211,46 @@ typedef struct {
  * Note: Channels 4...7 are not used with respect to the Acer PICA-61
  * chipset which does not provide these DMA channels.
  */
  * Note: Channels 4...7 are not used with respect to the Acer PICA-61
  * chipset which does not provide these DMA channels.
  */

-#define JAZZ_SCSI_DMA           0              /* SCSI */
-#define JAZZ_FLOPPY_DMA         1              /* FLOPPY */
-#define JAZZ_AUDIOL_DMA         2              /* AUDIO L */
-#define JAZZ_AUDIOR_DMA         3              /* AUDIO R */
+#define JAZZ_SCSI_DMA          0              /* SCSI */
+#define JAZZ_FLOPPY_DMA                1              /* FLOPPY */
+#define JAZZ_AUDIOL_DMA                2              /* AUDIO L */
+#define JAZZ_AUDIOR_DMA                3              /* AUDIO R */

 
 /*
  * JAZZ R4030 MCT_ADR chip (DMA controller)
  * Note: Virtual Addresses !
  */
 #define JAZZ_R4030_CONFIG      0xE0000000      /* R4030 config register */
 
 /*
  * JAZZ R4030 MCT_ADR chip (DMA controller)
  * Note: Virtual Addresses !
  */
 #define JAZZ_R4030_CONFIG      0xE0000000      /* R4030 config register */

-#define JAZZ_R4030_REVISION     0xE0000008     /* same as PICA_ASIC_REVISION */
+#define JAZZ_R4030_REVISION    0xE0000008      /* same as PICA_ASIC_REVISION */

 #define JAZZ_R4030_INV_ADDR    0xE0000010      /* Invalid Address register */
 
 #define JAZZ_R4030_INV_ADDR    0xE0000010      /* Invalid Address register */
 

-#define JAZZ_R4030_TRSTBL_BASE  0xE0000018     /* Translation Table Base */
-#define JAZZ_R4030_TRSTBL_LIM   0xE0000020     /* Translation Table Limit */
-#define JAZZ_R4030_TRSTBL_INV   0xE0000028     /* Translation Table Invalidate */
+#define JAZZ_R4030_TRSTBL_BASE 0xE0000018      /* Translation Table Base */
+#define JAZZ_R4030_TRSTBL_LIM  0xE0000020      /* Translation Table Limit */
+#define JAZZ_R4030_TRSTBL_INV  0xE0000028      /* Translation Table Invalidate */

 
 

-#define JAZZ_R4030_CACHE_MTNC   0xE0000030     /* Cache Maintenance */
-#define JAZZ_R4030_R_FAIL_ADDR  0xE0000038     /* Remote Failed Address */
-#define JAZZ_R4030_M_FAIL_ADDR  0xE0000040     /* Memory Failed Address */
+#define JAZZ_R4030_CACHE_MTNC  0xE0000030      /* Cache Maintenance */
+#define JAZZ_R4030_R_FAIL_ADDR 0xE0000038      /* Remote Failed Address */
+#define JAZZ_R4030_M_FAIL_ADDR 0xE0000040      /* Memory Failed Address */

 
 

-#define JAZZ_R4030_CACHE_PTAG   0xE0000048     /* I/O Cache Physical Tag */
-#define JAZZ_R4030_CACHE_LTAG   0xE0000050     /* I/O Cache Logical Tag */
-#define JAZZ_R4030_CACHE_BMASK  0xE0000058     /* I/O Cache Byte Mask */
-#define JAZZ_R4030_CACHE_BWIN   0xE0000060     /* I/O Cache Buffer Window */
+#define JAZZ_R4030_CACHE_PTAG  0xE0000048      /* I/O Cache Physical Tag */
+#define JAZZ_R4030_CACHE_LTAG  0xE0000050      /* I/O Cache Logical Tag */
+#define JAZZ_R4030_CACHE_BMASK 0xE0000058      /* I/O Cache Byte Mask */
+#define JAZZ_R4030_CACHE_BWIN  0xE0000060      /* I/O Cache Buffer Window */

 
 /*
  * Remote Speed Registers.
  *
 
 /*
  * Remote Speed Registers.
  *

- *  0: free,      1: Ethernet,  2: SCSI,      3: Floppy,
- *  4: RTC,       5: Kb./Mouse  6: serial 1,  7: serial 2,
- *  8: parallel,  9: NVRAM,    10: CPU,      11: PROM,
+ *  0: free,     1: Ethernet,  2: SCSI,      3: Floppy,
+ *  4: RTC,      5: Kb./Mouse  6: serial 1,  7: serial 2,
+ *  8: parallel,  9: NVRAM,    10: CPU,             11: PROM,

  * 12: reserved, 13: free,     14: 7seg LED, 15: ???
  */
 #define JAZZ_R4030_REM_SPEED   0xE0000070      /* 16 Remote Speed Registers */
                                                /* 0xE0000070,78,80... 0xE00000E8 */
  * 12: reserved, 13: free,     14: 7seg LED, 15: ???
  */
 #define JAZZ_R4030_REM_SPEED   0xE0000070      /* 16 Remote Speed Registers */
                                                /* 0xE0000070,78,80... 0xE00000E8 */

-#define JAZZ_R4030_IRQ_ENABLE   0xE00000E8     /* Internal Interrupt Enable */
-#define JAZZ_R4030_INVAL_ADDR   0xE0000010     /* Invalid address Register */
-#define JAZZ_R4030_IRQ_SOURCE   0xE0000200     /* Interrupt Source Register */
-#define JAZZ_R4030_I386_ERROR   0xE0000208     /* i386/EISA Bus Error */
+#define JAZZ_R4030_IRQ_ENABLE  0xE00000E8      /* Internal Interrupt Enable */
+#define JAZZ_R4030_INVAL_ADDR  0xE0000010      /* Invalid address Register */
+#define JAZZ_R4030_IRQ_SOURCE  0xE0000200      /* Interrupt Source Register */
+#define JAZZ_R4030_I386_ERROR  0xE0000208      /* i386/EISA Bus Error */

 
 /*
  * Virtual (E)ISA controller address
 
 /*
  * Virtual (E)ISA controller address

diff --git a/arch/mips/include/asm/jazzdma.h b/arch/mips/include/asm/jazzdma.h
index 8bb37bba68f0c32ea3f6a2c1fecdcf198e053d1b..2cefc3c47241a492a01bea0bdd7d2eebcfefee68 100644 (file)
--- a/arch/mips/include/asm/jazzdma.h
+++ b/arch/mips/include/asm/jazzdma.h
@@ -10,7 +10,7 @@
 extern unsigned long vdma_alloc(unsigned long paddr, unsigned long size);
 extern int vdma_free(unsigned long laddr);
 extern int vdma_remap(unsigned long laddr, unsigned long paddr,
 extern unsigned long vdma_alloc(unsigned long paddr, unsigned long size);
 extern int vdma_free(unsigned long laddr);
 extern int vdma_remap(unsigned long laddr, unsigned long paddr,

-                      unsigned long size);
+                     unsigned long size);

 extern unsigned long vdma_phys2log(unsigned long paddr);
 extern unsigned long vdma_log2phys(unsigned long laddr);
 extern void vdma_stats(void);          /* for debugging only */
 extern unsigned long vdma_phys2log(unsigned long paddr);
 extern unsigned long vdma_log2phys(unsigned long laddr);
 extern void vdma_stats(void);          /* for debugging only */


@@ -35,14 +35,14 @@ extern int vdma_get_enable(int channel);
  * Macros to get page no. and offset of a given address
  * Note that VDMA_PAGE() works for physical addresses only
  */
  * Macros to get page no. and offset of a given address
  * Note that VDMA_PAGE() works for physical addresses only
  */

-#define VDMA_PAGE(a)            ((unsigned int)(a) >> 12)
-#define VDMA_OFFSET(a)          ((unsigned int)(a) & (VDMA_PAGESIZE-1))
+#define VDMA_PAGE(a)           ((unsigned int)(a) >> 12)
+#define VDMA_OFFSET(a)         ((unsigned int)(a) & (VDMA_PAGESIZE-1))

 
 /*
  * error code returned by vdma_alloc()
  * (See also arch/mips/kernel/jazzdma.c)
  */
 
 /*
  * error code returned by vdma_alloc()
  * (See also arch/mips/kernel/jazzdma.c)
  */

-#define VDMA_ERROR              0xffffffff
+#define VDMA_ERROR             0xffffffff

 
 /*
  * VDMA pagetable entry description
 
 /*
  * VDMA pagetable entry description


@@ -59,37 +59,37 @@ typedef volatile struct VDMA_PGTBL_ENTRY {
  */
 #define JAZZ_R4030_CHNL_MODE   0xE0000100      /* 8 DMA Channel Mode Registers, */
                                                /* 0xE0000100,120,140... */
  */
 #define JAZZ_R4030_CHNL_MODE   0xE0000100      /* 8 DMA Channel Mode Registers, */
                                                /* 0xE0000100,120,140... */

-#define JAZZ_R4030_CHNL_ENABLE  0xE0000108     /* 8 DMA Channel Enable Regs, */
+#define JAZZ_R4030_CHNL_ENABLE 0xE0000108      /* 8 DMA Channel Enable Regs, */

                                                /* 0xE0000108,128,148... */
                                                /* 0xE0000108,128,148... */

-#define JAZZ_R4030_CHNL_COUNT   0xE0000110     /* 8 DMA Channel Byte Cnt Regs, */
+#define JAZZ_R4030_CHNL_COUNT  0xE0000110      /* 8 DMA Channel Byte Cnt Regs, */

                                                /* 0xE0000110,130,150... */
 #define JAZZ_R4030_CHNL_ADDR   0xE0000118      /* 8 DMA Channel Address Regs, */
                                                /* 0xE0000118,138,158... */
 
 /* channel enable register bits */
 
                                                /* 0xE0000110,130,150... */
 #define JAZZ_R4030_CHNL_ADDR   0xE0000118      /* 8 DMA Channel Address Regs, */
                                                /* 0xE0000118,138,158... */
 
 /* channel enable register bits */
 

-#define R4030_CHNL_ENABLE        (1<<0)
-#define R4030_CHNL_WRITE         (1<<1)
-#define R4030_TC_INTR            (1<<8)
-#define R4030_MEM_INTR           (1<<9)
-#define R4030_ADDR_INTR          (1<<10)
+#define R4030_CHNL_ENABLE       (1<<0)
+#define R4030_CHNL_WRITE        (1<<1)
+#define R4030_TC_INTR           (1<<8)
+#define R4030_MEM_INTR          (1<<9)
+#define R4030_ADDR_INTR                 (1<<10)

 
 /*
  * Channel mode register bits
  */
 
 /*
  * Channel mode register bits
  */

-#define R4030_MODE_ATIME_40      (0) /* device access time on remote bus */
-#define R4030_MODE_ATIME_80      (1)
-#define R4030_MODE_ATIME_120     (2)
-#define R4030_MODE_ATIME_160     (3)
-#define R4030_MODE_ATIME_200     (4)
-#define R4030_MODE_ATIME_240     (5)
-#define R4030_MODE_ATIME_280     (6)
-#define R4030_MODE_ATIME_320     (7)
-#define R4030_MODE_WIDTH_8       (1<<3)        /* device data bus width */
-#define R4030_MODE_WIDTH_16      (2<<3)
-#define R4030_MODE_WIDTH_32      (3<<3)
-#define R4030_MODE_INTR_EN       (1<<5)
-#define R4030_MODE_BURST         (1<<6)        /* Rev. 2 only */
-#define R4030_MODE_FAST_ACK      (1<<7)        /* Rev. 2 only */
+#define R4030_MODE_ATIME_40     (0) /* device access time on remote bus */
+#define R4030_MODE_ATIME_80     (1)
+#define R4030_MODE_ATIME_120    (2)
+#define R4030_MODE_ATIME_160    (3)
+#define R4030_MODE_ATIME_200    (4)
+#define R4030_MODE_ATIME_240    (5)
+#define R4030_MODE_ATIME_280    (6)
+#define R4030_MODE_ATIME_320    (7)
+#define R4030_MODE_WIDTH_8      (1<<3) /* device data bus width */
+#define R4030_MODE_WIDTH_16     (2<<3)
+#define R4030_MODE_WIDTH_32     (3<<3)
+#define R4030_MODE_INTR_EN      (1<<5)
+#define R4030_MODE_BURST        (1<<6) /* Rev. 2 only */
+#define R4030_MODE_FAST_ACK     (1<<7) /* Rev. 2 only */

 
 #endif /* _ASM_JAZZDMA_H */
 
 #endif /* _ASM_JAZZDMA_H */

diff --git a/arch/mips/include/asm/kmap_types.h b/arch/mips/include/asm/kmap_types.h
index 58e91ed0388f7393150b6da2569428f9828b8488..c1909dcada39566a7f04b1e67bca2538932a33a8 100644 (file)
--- a/arch/mips/include/asm/kmap_types.h
+++ b/arch/mips/include/asm/kmap_types.h
@@ -2,7 +2,7 @@
 #define _ASM_KMAP_TYPES_H
 
 #ifdef CONFIG_DEBUG_HIGHMEM
 #define _ASM_KMAP_TYPES_H
 
 #ifdef CONFIG_DEBUG_HIGHMEM

-#define  __WITH_KM_FENCE
+#define         __WITH_KM_FENCE

 #endif
 
 #include <asm-generic/kmap_types.h>
 #endif
 
 #include <asm-generic/kmap_types.h>

diff --git a/arch/mips/include/asm/kprobes.h b/arch/mips/include/asm/kprobes.h
index 1fbbca01e681976027044e8697603ef28f224755..daba1f9a4f7939070dd0a75c00ac67979055737e 100644 (file)
--- a/arch/mips/include/asm/kprobes.h
+++ b/arch/mips/include/asm/kprobes.h
@@ -29,7 +29,7 @@
 #include <asm/kdebug.h>
 #include <asm/inst.h>
 
 #include <asm/kdebug.h>
 #include <asm/inst.h>
 

-#define  __ARCH_WANT_KPROBES_INSN_SLOT
+#define         __ARCH_WANT_KPROBES_INSN_SLOT

 
 struct kprobe;
 struct pt_regs;
 
 struct kprobe;
 struct pt_regs;

diff --git a/arch/mips/include/asm/lasat/eeprom.h b/arch/mips/include/asm/lasat/eeprom.h
index 3dac203697faacc41888d8a485f87dd19e8ae0f4..d918b822e3767bd521ab156573a119cbac25ebfa 100644 (file)
--- a/arch/mips/include/asm/lasat/eeprom.h
+++ b/arch/mips/include/asm/lasat/eeprom.h
@@ -1,12 +1,12 @@
 #include <asm/addrspace.h>
 
 /* lasat 100 */
 #include <asm/addrspace.h>
 
 /* lasat 100 */

-#define AT93C_REG_100               KSEG1ADDR(0x1c810000)
-#define AT93C_RDATA_REG_100         AT93C_REG_100
-#define AT93C_RDATA_SHIFT_100       4
-#define AT93C_WDATA_SHIFT_100       4
-#define AT93C_CS_M_100              (1 << 5)
-#define AT93C_CLK_M_100             (1 << 3)
+#define AT93C_REG_100              KSEG1ADDR(0x1c810000)
+#define AT93C_RDATA_REG_100        AT93C_REG_100
+#define AT93C_RDATA_SHIFT_100      4
+#define AT93C_WDATA_SHIFT_100      4
+#define AT93C_CS_M_100             (1 << 5)
+#define AT93C_CLK_M_100                    (1 << 3)

 
 /* lasat 200 */
 #define AT93C_REG_200          KSEG1ADDR(0x11000000)
 
 /* lasat 200 */
 #define AT93C_REG_200          KSEG1ADDR(0x11000000)

diff --git a/arch/mips/include/asm/lasat/lasat.h b/arch/mips/include/asm/lasat/lasat.h
index e8ff70f80e13bd81e21cc955f213e13c5275219e..9e32b4da99e249acc03bd64c91d0c73ddee07f24 100644 (file)
--- a/arch/mips/include/asm/lasat/lasat.h
+++ b/arch/mips/include/asm/lasat/lasat.h
@@ -100,7 +100,7 @@ struct lasat_eeprom_struct_pre7 {
 
 /* Configuration descriptor encoding - see the doc for details */
 
 
 /* Configuration descriptor encoding - see the doc for details */
 

-#define LASAT_W0_DSCTYPE(v)            (((v))         & 0xf)
+#define LASAT_W0_DSCTYPE(v)            (((v))         & 0xf)

 #define LASAT_W0_BMID(v)               (((v) >> 0x04) & 0xf)
 #define LASAT_W0_CPUTYPE(v)            (((v) >> 0x08) & 0xf)
 #define LASAT_W0_BUSSPEED(v)           (((v) >> 0x0c) & 0xf)
 #define LASAT_W0_BMID(v)               (((v) >> 0x04) & 0xf)
 #define LASAT_W0_CPUTYPE(v)            (((v) >> 0x08) & 0xf)
 #define LASAT_W0_BUSSPEED(v)           (((v) >> 0x0c) & 0xf)


@@ -109,7 +109,7 @@ struct lasat_eeprom_struct_pre7 {
 #define LASAT_W0_SDRAMBANKS(v)         (((v) >> 0x18) & 0xf)
 #define LASAT_W0_L2CACHE(v)            (((v) >> 0x1c) & 0xf)
 
 #define LASAT_W0_SDRAMBANKS(v)         (((v) >> 0x18) & 0xf)
 #define LASAT_W0_L2CACHE(v)            (((v) >> 0x1c) & 0xf)
 

-#define LASAT_W1_EDHAC(v)              (((v))         & 0xf)
+#define LASAT_W1_EDHAC(v)              (((v))         & 0xf)

 #define LASAT_W1_HIFN(v)               (((v) >> 0x04) & 0x1)
 #define LASAT_W1_ISDN(v)               (((v) >> 0x05) & 0x1)
 #define LASAT_W1_IDE(v)                        (((v) >> 0x06) & 0x1)
 #define LASAT_W1_HIFN(v)               (((v) >> 0x04) & 0x1)
 #define LASAT_W1_ISDN(v)               (((v) >> 0x05) & 0x1)
 #define LASAT_W1_IDE(v)                        (((v) >> 0x06) & 0x1)


@@ -239,7 +239,7 @@ static inline void lasat_ndelay(unsigned int ns)
        __delay(ns / lasat_ndelay_divider);
 }
 
        __delay(ns / lasat_ndelay_divider);
 }
 

-#define IS_LASAT_200()     (current_cpu_data.cputype == CPU_R5000)
+#define IS_LASAT_200()    (current_cpu_data.cputype == CPU_R5000)

 
 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
 
 
 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
 


@@ -247,11 +247,11 @@ static inline void lasat_ndelay(unsigned int ns)
 #define LASAT_SERVICEMODE_MAGIC_2     0xfedeabba
 
 /* Lasat 100 boards */
 #define LASAT_SERVICEMODE_MAGIC_2     0xfedeabba
 
 /* Lasat 100 boards */

-#define LASAT_GT_BASE           (KSEG1ADDR(0x14000000))
+#define LASAT_GT_BASE          (KSEG1ADDR(0x14000000))

 
 /* Lasat 200 boards */
 
 /* Lasat 200 boards */

-#define Vrc5074_PHYS_BASE       0x1fa00000
-#define Vrc5074_BASE            (KSEG1ADDR(Vrc5074_PHYS_BASE))
-#define PCI_WINDOW1             0x1a000000
+#define Vrc5074_PHYS_BASE      0x1fa00000
+#define Vrc5074_BASE           (KSEG1ADDR(Vrc5074_PHYS_BASE))
+#define PCI_WINDOW1            0x1a000000

 
 #endif /* _LASAT_H */
 
 #endif /* _LASAT_H */

diff --git a/arch/mips/include/asm/lasat/serial.h b/arch/mips/include/asm/lasat/serial.h
index 1c37d70579b817a98e1cdadea91be801264e8339..a2f6c7a9cfe84843dc2f0ff645476ce75a00ddb2 100644 (file)
--- a/arch/mips/include/asm/lasat/serial.h
+++ b/arch/mips/include/asm/lasat/serial.h
@@ -1,7 +1,7 @@
 #include <asm/lasat/lasat.h>
 
 /* Lasat 100 boards serial configuration */
 #include <asm/lasat/lasat.h>
 
 /* Lasat 100 boards serial configuration */

-#define LASAT_BASE_BAUD_100            (7372800 / 16)
+#define LASAT_BASE_BAUD_100            (7372800 / 16)

 #define LASAT_UART_REGS_BASE_100       0x1c8b0000
 #define LASAT_UART_REGS_SHIFT_100      2
 #define LASATINT_UART_100              16
 #define LASAT_UART_REGS_BASE_100       0x1c8b0000
 #define LASAT_UART_REGS_SHIFT_100      2
 #define LASATINT_UART_100              16

diff --git a/arch/mips/include/asm/local.h b/arch/mips/include/asm/local.h
index 94fde8d0fac1c60e1ee5999d14f8e4f0ec4c1226..d44622cd74becb52ab33e80d8f21ab0e7d68ea05 100644 (file)
--- a/arch/mips/include/asm/local.h
+++ b/arch/mips/include/asm/local.h
@@ -15,10 +15,10 @@ typedef struct
 #define LOCAL_INIT(i)  { ATOMIC_LONG_INIT(i) }
 
 #define local_read(l)  atomic_long_read(&(l)->a)
 #define LOCAL_INIT(i)  { ATOMIC_LONG_INIT(i) }
 
 #define local_read(l)  atomic_long_read(&(l)->a)

-#define local_set(l, i)        atomic_long_set(&(l)->a, (i))
+#define local_set(l, i) atomic_long_set(&(l)->a, (i))

 
 

-#define local_add(i, l)        atomic_long_add((i), (&(l)->a))
-#define local_sub(i, l)        atomic_long_sub((i), (&(l)->a))
+#define local_add(i, l) atomic_long_add((i), (&(l)->a))
+#define local_sub(i, l) atomic_long_sub((i), (&(l)->a))

 #define local_inc(l)   atomic_long_inc(&(l)->a)
 #define local_dec(l)   atomic_long_dec(&(l)->a)
 
 #define local_inc(l)   atomic_long_inc(&(l)->a)
 #define local_dec(l)   atomic_long_dec(&(l)->a)
 

diff --git a/arch/mips/include/asm/m48t37.h b/arch/mips/include/asm/m48t37.h
index cabf86264f36030bb50a726d0802dac608c7f90c..e6eaf5339e4e65f2fa9b5d9bfd50957bba6c1ca9 100644 (file)
--- a/arch/mips/include/asm/m48t37.h
+++ b/arch/mips/include/asm/m48t37.h
@@ -9,7 +9,7 @@
 extern spinlock_t rtc_lock;
 
 struct m48t37_rtc {
 extern spinlock_t rtc_lock;
 
 struct m48t37_rtc {

-       volatile u8     pad[0x7ff0];    /* NVRAM */
+       volatile u8     pad[0x7ff0];    /* NVRAM */

        volatile u8     flags;
        volatile u8     century;
        volatile u8     alarm_sec;
        volatile u8     flags;
        volatile u8     century;
        volatile u8     alarm_sec;

diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h
index 07d3fadb24437e289bae5c8da747b2fdd647e8a5..a47ea0c852483aba4ccfb8d833fb29d277b14147 100644 (file)
--- a/arch/mips/include/asm/mach-ar7/ar7.h
+++ b/arch/mips/include/asm/mach-ar7/ar7.h
@@ -40,9 +40,9 @@
 #define AR7_REGS_USB   (AR7_REGS_BASE + 0x1200)
 #define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
 #define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C)
 #define AR7_REGS_USB   (AR7_REGS_BASE + 0x1200)
 #define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
 #define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C)

-#define AR7_REGS_VLYNQ0        (AR7_REGS_BASE + 0x1800)
+#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)

 #define AR7_REGS_DCL   (AR7_REGS_BASE + 0x1a00)
 #define AR7_REGS_DCL   (AR7_REGS_BASE + 0x1a00)

-#define AR7_REGS_VLYNQ1        (AR7_REGS_BASE + 0x1c00)
+#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)

 #define AR7_REGS_MDIO  (AR7_REGS_BASE + 0x1e00)
 #define AR7_REGS_IRQ   (AR7_REGS_BASE + 0x2400)
 #define AR7_REGS_MAC1  (AR7_REGS_BASE + 0x2800)
 #define AR7_REGS_MDIO  (AR7_REGS_BASE + 0x1e00)
 #define AR7_REGS_IRQ   (AR7_REGS_BASE + 0x2400)
 #define AR7_REGS_MAC1  (AR7_REGS_BASE + 0x2800)


@@ -52,7 +52,7 @@
 #define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
 
 /* Titan registers */
 #define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
 
 /* Titan registers */

-#define TITAN_REGS_ESWITCH_BASE        (0x08640000)
+#define TITAN_REGS_ESWITCH_BASE (0x08640000)

 #define TITAN_REGS_MAC0                (TITAN_REGS_ESWITCH_BASE)
 #define TITAN_REGS_MAC1                (TITAN_REGS_ESWITCH_BASE + 0x0800)
 #define TITAN_REGS_MDIO                (TITAN_REGS_ESWITCH_BASE + 0x02000)
 #define TITAN_REGS_MAC0                (TITAN_REGS_ESWITCH_BASE)
 #define TITAN_REGS_MAC1                (TITAN_REGS_ESWITCH_BASE + 0x0800)
 #define TITAN_REGS_MDIO                (TITAN_REGS_ESWITCH_BASE + 0x02000)


@@ -72,9 +72,9 @@
 
 /* GPIO control registers */
 #define AR7_GPIO_INPUT 0x0
 
 /* GPIO control registers */
 #define AR7_GPIO_INPUT 0x0

-#define AR7_GPIO_OUTPUT        0x4
+#define AR7_GPIO_OUTPUT 0x4

 #define AR7_GPIO_DIR   0x8
 #define AR7_GPIO_DIR   0x8

-#define AR7_GPIO_ENABLE        0xc
+#define AR7_GPIO_ENABLE 0xc

 #define TITAN_GPIO_INPUT_0     0x0
 #define TITAN_GPIO_INPUT_1     0x4
 #define TITAN_GPIO_OUTPUT_0    0x8
 #define TITAN_GPIO_INPUT_0     0x0
 #define TITAN_GPIO_INPUT_1     0x4
 #define TITAN_GPIO_OUTPUT_0    0x8


@@ -88,10 +88,10 @@
 #define AR7_CHIP_7200  0x2b
 #define AR7_CHIP_7300  0x05
 #define AR7_CHIP_TITAN 0x07
 #define AR7_CHIP_7200  0x2b
 #define AR7_CHIP_7300  0x05
 #define AR7_CHIP_TITAN 0x07

-#define TITAN_CHIP_1050        0x0f
-#define TITAN_CHIP_1055        0x0e
-#define TITAN_CHIP_1056        0x0d
-#define TITAN_CHIP_1060        0x07
+#define TITAN_CHIP_1050 0x0f
+#define TITAN_CHIP_1055 0x0e
+#define TITAN_CHIP_1056 0x0d
+#define TITAN_CHIP_1060 0x07

 
 /* Interrupts */
 #define AR7_IRQ_UART0  15
 
 /* Interrupts */
 #define AR7_IRQ_UART0  15

diff --git a/arch/mips/include/asm/mach-ar7/irq.h b/arch/mips/include/asm/mach-ar7/irq.h
index 39e9757e3d9388d8951e220202d4408ecf01d4a9..7ad10e379e2b51420868e546f3c3dc0fa86845c1 100644 (file)
--- a/arch/mips/include/asm/mach-ar7/irq.h
+++ b/arch/mips/include/asm/mach-ar7/irq.h
@@ -9,7 +9,7 @@
 #ifndef __ASM_AR7_IRQ_H
 #define __ASM_AR7_IRQ_H
 
 #ifndef __ASM_AR7_IRQ_H
 #define __ASM_AR7_IRQ_H
 

-#define NR_IRQS        256
+#define NR_IRQS 256

 
 #include_next <irq.h>
 
 
 #include_next <irq.h>
 

diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index a5e0f17ea77ce083371afe2dbc40e77afe3692ce..8dec938af115153b88660a7ee3a2ba92c666deaa 100644 (file)
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -34,8 +34,8 @@
 #define AR71XX_UART_SIZE       0x100
 #define AR71XX_USB_CTRL_BASE   (AR71XX_APB_BASE + 0x00030000)
 #define AR71XX_USB_CTRL_SIZE   0x100
 #define AR71XX_UART_SIZE       0x100
 #define AR71XX_USB_CTRL_BASE   (AR71XX_APB_BASE + 0x00030000)
 #define AR71XX_USB_CTRL_SIZE   0x100

-#define AR71XX_GPIO_BASE        (AR71XX_APB_BASE + 0x00040000)
-#define AR71XX_GPIO_SIZE        0x100
+#define AR71XX_GPIO_BASE       (AR71XX_APB_BASE + 0x00040000)
+#define AR71XX_GPIO_SIZE       0x100

 #define AR71XX_PLL_BASE                (AR71XX_APB_BASE + 0x00050000)
 #define AR71XX_PLL_SIZE                0x100
 #define AR71XX_RESET_BASE      (AR71XX_APB_BASE + 0x00060000)
 #define AR71XX_PLL_BASE                (AR71XX_APB_BASE + 0x00050000)
 #define AR71XX_PLL_SIZE                0x100
 #define AR71XX_RESET_BASE      (AR71XX_APB_BASE + 0x00060000)


@@ -312,7 +312,7 @@
 #define AR934X_BOOTSTRAP_EJTAG_MODE    BIT(5)
 #define AR934X_BOOTSTRAP_REF_CLK_40    BIT(4)
 #define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
 #define AR934X_BOOTSTRAP_EJTAG_MODE    BIT(5)
 #define AR934X_BOOTSTRAP_REF_CLK_40    BIT(4)
 #define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)

-#define AR934X_BOOTSTRAP_SDRAM_DISABLED        BIT(1)
+#define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)

 #define AR934X_BOOTSTRAP_DDR1          BIT(0)
 
 #define AR934X_PCIE_WMAC_INT_WMAC_MISC         BIT(0)
 #define AR934X_BOOTSTRAP_DDR1          BIT(0)
 
 #define AR934X_PCIE_WMAC_INT_WMAC_MISC         BIT(0)


@@ -362,7 +362,7 @@
 
 #define AR724X_REV_ID_REVISION_MASK    0x3
 
 
 #define AR724X_REV_ID_REVISION_MASK    0x3
 

-#define AR934X_REV_ID_REVISION_MASK     0xf
+#define AR934X_REV_ID_REVISION_MASK    0xf

 
 /*
  * SPI block
 
 /*
  * SPI block

diff --git a/arch/mips/include/asm/mach-ath79/ar933x_uart.h b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
index 52730555937f21541067dfccd8886de4462f1864..c2917b39966bf18797b6e4885d5f713b52e2b11d 100644 (file)
--- a/arch/mips/include/asm/mach-ath79/ar933x_uart.h
+++ b/arch/mips/include/asm/mach-ath79/ar933x_uart.h
@@ -26,14 +26,14 @@
 
 #define AR933X_UART_CS_PARITY_S                0
 #define AR933X_UART_CS_PARITY_M                0x3
 
 #define AR933X_UART_CS_PARITY_S                0
 #define AR933X_UART_CS_PARITY_M                0x3

-#define   AR933X_UART_CS_PARITY_NONE   0
-#define   AR933X_UART_CS_PARITY_ODD    1
-#define   AR933X_UART_CS_PARITY_EVEN   2
+#define          AR933X_UART_CS_PARITY_NONE    0
+#define          AR933X_UART_CS_PARITY_ODD     1
+#define          AR933X_UART_CS_PARITY_EVEN    2

 #define AR933X_UART_CS_IF_MODE_S       2
 #define AR933X_UART_CS_IF_MODE_M       0x3
 #define AR933X_UART_CS_IF_MODE_S       2
 #define AR933X_UART_CS_IF_MODE_M       0x3

-#define   AR933X_UART_CS_IF_MODE_NONE  0
-#define   AR933X_UART_CS_IF_MODE_DTE   1
-#define   AR933X_UART_CS_IF_MODE_DCE   2
+#define          AR933X_UART_CS_IF_MODE_NONE   0
+#define          AR933X_UART_CS_IF_MODE_DTE    1
+#define          AR933X_UART_CS_IF_MODE_DCE    2

 #define AR933X_UART_CS_FLOW_CTRL_S     4
 #define AR933X_UART_CS_FLOW_CTRL_M     0x3
 #define AR933X_UART_CS_DMA_EN          BIT(6)
 #define AR933X_UART_CS_FLOW_CTRL_S     4
 #define AR933X_UART_CS_FLOW_CTRL_M     0x3
 #define AR933X_UART_CS_DMA_EN          BIT(6)

diff --git a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
index ea4b66dccf6e85206cd42c50e4a1c0a7669f45a5..ddb947e9221f13e631ddef8c4164255abdbebed8 100644 (file)
--- a/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ath79/cpu-feature-overrides.h
@@ -49,7 +49,7 @@
 #define cpu_has_64bits         0
 #define cpu_has_64bit_zero_reg 0
 #define cpu_has_64bit_gp_regs  0
 #define cpu_has_64bits         0
 #define cpu_has_64bit_zero_reg 0
 #define cpu_has_64bit_gp_regs  0

-#define cpu_has_64bit_addresses        0
+#define cpu_has_64bit_addresses 0

 
 #define cpu_dcache_line_size() 32
 #define cpu_icache_line_size() 32
 
 #define cpu_dcache_line_size() 32
 #define cpu_icache_line_size() 32

diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 569828d3ccab48a9581743542849e0931044792e..3e11a468cdf83de964bba1d718adfc49222da395 100644 (file)
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -349,7 +349,7 @@ extern void au1300_vss_block_control(int block, int enable);
 #define AU1000_INTC0_INT_LAST  (AU1000_INTC0_INT_BASE + 31)
 #define AU1000_INTC1_INT_BASE  (AU1000_INTC0_INT_LAST + 1)
 #define AU1000_INTC1_INT_LAST  (AU1000_INTC1_INT_BASE + 31)
 #define AU1000_INTC0_INT_LAST  (AU1000_INTC0_INT_BASE + 31)
 #define AU1000_INTC1_INT_BASE  (AU1000_INTC0_INT_LAST + 1)
 #define AU1000_INTC1_INT_LAST  (AU1000_INTC1_INT_BASE + 31)

-#define AU1000_MAX_INTR        AU1000_INTC1_INT_LAST
+#define AU1000_MAX_INTR                AU1000_INTC1_INT_LAST

 
 /* Au1300-style (GPIC): 1 controller with up to 128 sources */
 #define ALCHEMY_GPIC_INT_BASE  (MIPS_CPU_IRQ_BASE + 8)
 
 /* Au1300-style (GPIC): 1 controller with up to 128 sources */
 #define ALCHEMY_GPIC_INT_BASE  (MIPS_CPU_IRQ_BASE + 8)


@@ -589,7 +589,7 @@ enum soc_au1550_ints {
        AU1550_GPIO14_INT,
        AU1550_GPIO15_INT,
        AU1550_GPIO200_INT,
        AU1550_GPIO14_INT,
        AU1550_GPIO15_INT,
        AU1550_GPIO200_INT,

-       AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */
+       AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */

        AU1550_GPIO16_INT,
        AU1550_GPIO17_INT,
        AU1550_GPIO20_INT,
        AU1550_GPIO16_INT,
        AU1550_GPIO17_INT,
        AU1550_GPIO20_INT,


@@ -603,7 +603,7 @@ enum soc_au1550_ints {
        AU1550_GPIO28_INT,
        AU1550_GPIO206_INT,
        AU1550_GPIO207_INT,
        AU1550_GPIO28_INT,
        AU1550_GPIO206_INT,
        AU1550_GPIO207_INT,

-       AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */
+       AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */

 };
 
 enum soc_au1200_ints {
 };
 
 enum soc_au1200_ints {


@@ -636,7 +636,7 @@ enum soc_au1200_ints {
        AU1200_GPIO205_INT,
        AU1200_GPIO206_INT,
        AU1200_GPIO207_INT,
        AU1200_GPIO205_INT,
        AU1200_GPIO206_INT,
        AU1200_GPIO207_INT,

-       AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */
+       AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */

        AU1200_USB_INT,
        AU1200_LCD_INT,
        AU1200_MAE_BOTH_INT,
        AU1200_USB_INT,
        AU1200_LCD_INT,
        AU1200_MAE_BOTH_INT,


@@ -823,7 +823,7 @@ enum soc_au1200_ints {
 #define GPIC_GPIO_TO_BIT(gpio) \
        (1 << ((gpio) & 0x1f))
 
 #define GPIC_GPIO_TO_BIT(gpio) \
        (1 << ((gpio) & 0x1f))
 

-#define GPIC_GPIO_BANKOFF(gpio)        \
+#define GPIC_GPIO_BANKOFF(gpio) \

        (((gpio) >> 5) * 4)
 
 /* Pin Control bits: who owns the pin, what does it do */
        (((gpio) >> 5) * 4)
 
 /* Pin Control bits: who owns the pin, what does it do */


@@ -958,32 +958,32 @@ enum soc_au1200_ints {
 #define MEM_STSTAT             0xB4001104
 
 #define MEM_STNAND_CMD         0x0
 #define MEM_STSTAT             0xB4001104
 
 #define MEM_STNAND_CMD         0x0

-#define MEM_STNAND_ADDR        0x4
-#define MEM_STNAND_DATA        0x20
+#define MEM_STNAND_ADDR                0x4
+#define MEM_STNAND_DATA                0x20

 
 
 /* Programmable Counters 0 and 1 */
 #define SYS_BASE               0xB1900000
 #define SYS_COUNTER_CNTRL      (SYS_BASE + 0x14)
 
 
 /* Programmable Counters 0 and 1 */
 #define SYS_BASE               0xB1900000
 #define SYS_COUNTER_CNTRL      (SYS_BASE + 0x14)

-#  define SYS_CNTRL_E1S        (1 << 23)
-#  define SYS_CNTRL_T1S        (1 << 20)
-#  define SYS_CNTRL_M21        (1 << 19)
-#  define SYS_CNTRL_M11        (1 << 18)
-#  define SYS_CNTRL_M01        (1 << 17)
-#  define SYS_CNTRL_C1S        (1 << 16)
+#  define SYS_CNTRL_E1S                (1 << 23)
+#  define SYS_CNTRL_T1S                (1 << 20)
+#  define SYS_CNTRL_M21                (1 << 19)
+#  define SYS_CNTRL_M11                (1 << 18)
+#  define SYS_CNTRL_M01                (1 << 17)
+#  define SYS_CNTRL_C1S                (1 << 16)

 #  define SYS_CNTRL_BP         (1 << 14)
 #  define SYS_CNTRL_BP         (1 << 14)

-#  define SYS_CNTRL_EN1        (1 << 13)
-#  define SYS_CNTRL_BT1        (1 << 12)
-#  define SYS_CNTRL_EN0        (1 << 11)
-#  define SYS_CNTRL_BT0        (1 << 10)
+#  define SYS_CNTRL_EN1                (1 << 13)
+#  define SYS_CNTRL_BT1                (1 << 12)
+#  define SYS_CNTRL_EN0                (1 << 11)
+#  define SYS_CNTRL_BT0                (1 << 10)

 #  define SYS_CNTRL_E0         (1 << 8)
 #  define SYS_CNTRL_E0         (1 << 8)

-#  define SYS_CNTRL_E0S        (1 << 7)
-#  define SYS_CNTRL_32S        (1 << 5)
-#  define SYS_CNTRL_T0S        (1 << 4)
-#  define SYS_CNTRL_M20        (1 << 3)
-#  define SYS_CNTRL_M10        (1 << 2)
-#  define SYS_CNTRL_M00        (1 << 1)
-#  define SYS_CNTRL_C0S        (1 << 0)
+#  define SYS_CNTRL_E0S                (1 << 7)
+#  define SYS_CNTRL_32S                (1 << 5)
+#  define SYS_CNTRL_T0S                (1 << 4)
+#  define SYS_CNTRL_M20                (1 << 3)
+#  define SYS_CNTRL_M10                (1 << 2)
+#  define SYS_CNTRL_M00                (1 << 1)
+#  define SYS_CNTRL_C0S                (1 << 0)

 
 /* Programmable Counter 0 Registers */
 #define SYS_TOYTRIM            (SYS_BASE + 0)
 
 /* Programmable Counter 0 Registers */
 #define SYS_TOYTRIM            (SYS_BASE + 0)


@@ -1003,33 +1003,33 @@ enum soc_au1200_ints {
 
 /* I2S Controller */
 #define I2S_DATA               0xB1000000
 
 /* I2S Controller */
 #define I2S_DATA               0xB1000000

-#  define I2S_DATA_MASK        0xffffff
+#  define I2S_DATA_MASK                0xffffff

 #define I2S_CONFIG             0xB1000004
 #define I2S_CONFIG             0xB1000004

-#  define I2S_CONFIG_XU        (1 << 25)
-#  define I2S_CONFIG_XO        (1 << 24)
-#  define I2S_CONFIG_RU        (1 << 23)
-#  define I2S_CONFIG_RO        (1 << 22)
-#  define I2S_CONFIG_TR        (1 << 21)
-#  define I2S_CONFIG_TE        (1 << 20)
-#  define I2S_CONFIG_TF        (1 << 19)
-#  define I2S_CONFIG_RR        (1 << 18)
-#  define I2S_CONFIG_RE        (1 << 17)
-#  define I2S_CONFIG_RF        (1 << 16)
-#  define I2S_CONFIG_PD        (1 << 11)
-#  define I2S_CONFIG_LB        (1 << 10)
-#  define I2S_CONFIG_IC        (1 << 9)
+#  define I2S_CONFIG_XU                (1 << 25)
+#  define I2S_CONFIG_XO                (1 << 24)
+#  define I2S_CONFIG_RU                (1 << 23)
+#  define I2S_CONFIG_RO                (1 << 22)
+#  define I2S_CONFIG_TR                (1 << 21)
+#  define I2S_CONFIG_TE                (1 << 20)
+#  define I2S_CONFIG_TF                (1 << 19)
+#  define I2S_CONFIG_RR                (1 << 18)
+#  define I2S_CONFIG_RE                (1 << 17)
+#  define I2S_CONFIG_RF                (1 << 16)
+#  define I2S_CONFIG_PD                (1 << 11)
+#  define I2S_CONFIG_LB                (1 << 10)
+#  define I2S_CONFIG_IC                (1 << 9)

 #  define I2S_CONFIG_FM_BIT    7
 #  define I2S_CONFIG_FM_MASK   (0x3 << I2S_CONFIG_FM_BIT)
 #    define I2S_CONFIG_FM_I2S  (0x0 << I2S_CONFIG_FM_BIT)
 #    define I2S_CONFIG_FM_LJ   (0x1 << I2S_CONFIG_FM_BIT)
 #    define I2S_CONFIG_FM_RJ   (0x2 << I2S_CONFIG_FM_BIT)
 #  define I2S_CONFIG_FM_BIT    7
 #  define I2S_CONFIG_FM_MASK   (0x3 << I2S_CONFIG_FM_BIT)
 #    define I2S_CONFIG_FM_I2S  (0x0 << I2S_CONFIG_FM_BIT)
 #    define I2S_CONFIG_FM_LJ   (0x1 << I2S_CONFIG_FM_BIT)
 #    define I2S_CONFIG_FM_RJ   (0x2 << I2S_CONFIG_FM_BIT)

-#  define I2S_CONFIG_TN        (1 << 6)
-#  define I2S_CONFIG_RN        (1 << 5)
+#  define I2S_CONFIG_TN                (1 << 6)
+#  define I2S_CONFIG_RN                (1 << 5)

 #  define I2S_CONFIG_SZ_BIT    0
 #  define I2S_CONFIG_SZ_MASK   (0x1F << I2S_CONFIG_SZ_BIT)
 
 #define I2S_CONTROL            0xB1000008
 #  define I2S_CONFIG_SZ_BIT    0
 #  define I2S_CONFIG_SZ_MASK   (0x1F << I2S_CONFIG_SZ_BIT)
 
 #define I2S_CONTROL            0xB1000008

-#  define I2S_CONTROL_D        (1 << 1)
+#  define I2S_CONTROL_D                (1 << 1)

 #  define I2S_CONTROL_CE       (1 << 0)
 
 
 #  define I2S_CONTROL_CE       (1 << 0)
 
 


@@ -1037,16 +1037,16 @@ enum soc_au1200_ints {
 
 /* 4 byte offsets from AU1000_ETH_BASE */
 #define MAC_CONTROL            0x0
 
 /* 4 byte offsets from AU1000_ETH_BASE */
 #define MAC_CONTROL            0x0

-#  define MAC_RX_ENABLE        (1 << 2)
-#  define MAC_TX_ENABLE        (1 << 3)
-#  define MAC_DEF_CHECK        (1 << 5)
-#  define MAC_SET_BL(X)        (((X) & 0x3) << 6)
+#  define MAC_RX_ENABLE                (1 << 2)
+#  define MAC_TX_ENABLE                (1 << 3)
+#  define MAC_DEF_CHECK                (1 << 5)
+#  define MAC_SET_BL(X)                (((X) & 0x3) << 6)

 #  define MAC_AUTO_PAD         (1 << 8)
 #  define MAC_DISABLE_RETRY    (1 << 10)
 #  define MAC_DISABLE_BCAST    (1 << 11)
 #  define MAC_LATE_COL         (1 << 12)
 #  define MAC_AUTO_PAD         (1 << 8)
 #  define MAC_DISABLE_RETRY    (1 << 10)
 #  define MAC_DISABLE_BCAST    (1 << 11)
 #  define MAC_LATE_COL         (1 << 12)

-#  define MAC_HASH_MODE        (1 << 13)
-#  define MAC_HASH_ONLY        (1 << 15)
+#  define MAC_HASH_MODE                (1 << 13)
+#  define MAC_HASH_ONLY                (1 << 15)

 #  define MAC_PASS_ALL         (1 << 16)
 #  define MAC_INVERSE_FILTER   (1 << 17)
 #  define MAC_PROMISCUOUS      (1 << 18)
 #  define MAC_PASS_ALL         (1 << 16)
 #  define MAC_INVERSE_FILTER   (1 << 17)
 #  define MAC_PROMISCUOUS      (1 << 18)


@@ -1083,9 +1083,9 @@ enum soc_au1200_ints {
 #  define MAC_EN_RESET0                (1 << 1)
 #  define MAC_EN_TOSS          (0 << 2)
 #  define MAC_EN_CACHEABLE     (1 << 3)
 #  define MAC_EN_RESET0                (1 << 1)
 #  define MAC_EN_TOSS          (0 << 2)
 #  define MAC_EN_CACHEABLE     (1 << 3)

-#  define MAC_EN_RESET1        (1 << 4)
-#  define MAC_EN_RESET2        (1 << 5)
-#  define MAC_DMA_RESET        (1 << 6)
+#  define MAC_EN_RESET1                (1 << 4)
+#  define MAC_EN_RESET2                (1 << 5)
+#  define MAC_DMA_RESET                (1 << 6)

 
 /* Ethernet Controller DMA Channels */
 
 
 /* Ethernet Controller DMA Channels */
 


@@ -1095,7 +1095,7 @@ enum soc_au1200_ints {
 #define MAC_TX_BUFF0_STATUS    0x0
 #  define TX_FRAME_ABORTED     (1 << 0)
 #  define TX_JAB_TIMEOUT       (1 << 1)
 #define MAC_TX_BUFF0_STATUS    0x0
 #  define TX_FRAME_ABORTED     (1 << 0)
 #  define TX_JAB_TIMEOUT       (1 << 1)

-#  define TX_NO_CARRIER        (1 << 2)
+#  define TX_NO_CARRIER                (1 << 2)

 #  define TX_LOSS_CARRIER      (1 << 3)
 #  define TX_EXC_DEF           (1 << 4)
 #  define TX_LATE_COLL_ABORT   (1 << 5)
 #  define TX_LOSS_CARRIER      (1 << 3)
 #  define TX_EXC_DEF           (1 << 4)
 #  define TX_LATE_COLL_ABORT   (1 << 5)


@@ -1106,7 +1106,7 @@ enum soc_au1200_ints {
 #  define TX_COLL_CNT_MASK     (0xF << 10)
 #  define TX_PKT_RETRY         (1 << 31)
 #define MAC_TX_BUFF0_ADDR      0x4
 #  define TX_COLL_CNT_MASK     (0xF << 10)
 #  define TX_PKT_RETRY         (1 << 31)
 #define MAC_TX_BUFF0_ADDR      0x4

-#  define TX_DMA_ENABLE        (1 << 0)
+#  define TX_DMA_ENABLE                (1 << 0)

 #  define TX_T_DONE            (1 << 1)
 #  define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
 #define MAC_TX_BUFF0_LEN       0x8
 #  define TX_T_DONE            (1 << 1)
 #  define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
 #define MAC_TX_BUFF0_LEN       0x8


@@ -1125,7 +1125,7 @@ enum soc_au1200_ints {
 /* offsets from MAC_RX_RING_ADDR */
 #define MAC_RX_BUFF0_STATUS    0x0
 #  define RX_FRAME_LEN_MASK    0x3fff
 /* offsets from MAC_RX_RING_ADDR */
 #define MAC_RX_BUFF0_STATUS    0x0
 #  define RX_FRAME_LEN_MASK    0x3fff

-#  define RX_WDOG_TIMER        (1 << 14)
+#  define RX_WDOG_TIMER                (1 << 14)

 #  define RX_RUNT              (1 << 15)
 #  define RX_OVERLEN           (1 << 16)
 #  define RX_COLL              (1 << 17)
 #  define RX_RUNT              (1 << 15)
 #  define RX_OVERLEN           (1 << 16)
 #  define RX_COLL              (1 << 17)


@@ -1148,7 +1148,7 @@ enum soc_au1200_ints {
                    RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
                    RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
 #define MAC_RX_BUFF0_ADDR      0x4
                    RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
                    RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
 #define MAC_RX_BUFF0_ADDR      0x4

-#  define RX_DMA_ENABLE        (1 << 0)
+#  define RX_DMA_ENABLE                (1 << 0)

 #  define RX_T_DONE            (1 << 1)
 #  define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
 #  define RX_SET_BUFF_ADDR(X)  ((X) & 0xffffffc0)
 #  define RX_T_DONE            (1 << 1)
 #  define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
 #  define RX_SET_BUFF_ADDR(X)  ((X) & 0xffffffc0)


@@ -1173,34 +1173,34 @@ enum soc_au1200_ints {
 
 /* SSIO */
 #define SSI0_STATUS            0xB1600000
 
 /* SSIO */
 #define SSI0_STATUS            0xB1600000

-#  define SSI_STATUS_BF        (1 << 4)
-#  define SSI_STATUS_OF        (1 << 3)
-#  define SSI_STATUS_UF        (1 << 2)
+#  define SSI_STATUS_BF                (1 << 4)
+#  define SSI_STATUS_OF                (1 << 3)
+#  define SSI_STATUS_UF                (1 << 2)

 #  define SSI_STATUS_D         (1 << 1)
 #  define SSI_STATUS_B         (1 << 0)
 #define SSI0_INT               0xB1600004
 #  define SSI_INT_OI           (1 << 3)
 #  define SSI_INT_UI           (1 << 2)
 #  define SSI_INT_DI           (1 << 1)
 #  define SSI_STATUS_D         (1 << 1)
 #  define SSI_STATUS_B         (1 << 0)
 #define SSI0_INT               0xB1600004
 #  define SSI_INT_OI           (1 << 3)
 #  define SSI_INT_UI           (1 << 2)
 #  define SSI_INT_DI           (1 << 1)

-#define SSI0_INT_ENABLE        0xB1600008
+#define SSI0_INT_ENABLE                0xB1600008

 #  define SSI_INTE_OIE         (1 << 3)
 #  define SSI_INTE_UIE         (1 << 2)
 #  define SSI_INTE_DIE         (1 << 1)
 #define SSI0_CONFIG            0xB1600020
 #  define SSI_INTE_OIE         (1 << 3)
 #  define SSI_INTE_UIE         (1 << 2)
 #  define SSI_INTE_DIE         (1 << 1)
 #define SSI0_CONFIG            0xB1600020

-#  define SSI_CONFIG_AO        (1 << 24)
-#  define SSI_CONFIG_DO        (1 << 23)
+#  define SSI_CONFIG_AO                (1 << 24)
+#  define SSI_CONFIG_DO                (1 << 23)

 #  define SSI_CONFIG_ALEN_BIT  20
 #  define SSI_CONFIG_ALEN_MASK (0x7 << 20)
 #  define SSI_CONFIG_DLEN_BIT  16
 #  define SSI_CONFIG_DLEN_MASK (0x7 << 16)
 #  define SSI_CONFIG_ALEN_BIT  20
 #  define SSI_CONFIG_ALEN_MASK (0x7 << 20)
 #  define SSI_CONFIG_DLEN_BIT  16
 #  define SSI_CONFIG_DLEN_MASK (0x7 << 16)

-#  define SSI_CONFIG_DD        (1 << 11)
-#  define SSI_CONFIG_AD        (1 << 10)
+#  define SSI_CONFIG_DD                (1 << 11)
+#  define SSI_CONFIG_AD                (1 << 10)

 #  define SSI_CONFIG_BM_BIT    8
 #  define SSI_CONFIG_BM_MASK   (0x3 << 8)
 #  define SSI_CONFIG_BM_BIT    8
 #  define SSI_CONFIG_BM_MASK   (0x3 << 8)

-#  define SSI_CONFIG_CE        (1 << 7)
-#  define SSI_CONFIG_DP        (1 << 6)
-#  define SSI_CONFIG_DL        (1 << 5)
-#  define SSI_CONFIG_EP        (1 << 4)
+#  define SSI_CONFIG_CE                (1 << 7)
+#  define SSI_CONFIG_DP                (1 << 6)
+#  define SSI_CONFIG_DL                (1 << 5)
+#  define SSI_CONFIG_EP                (1 << 4)

 #define SSI0_ADATA             0xB1600024
 #  define SSI_AD_D             (1 << 24)
 #  define SSI_AD_ADDR_BIT      16
 #define SSI0_ADATA             0xB1600024
 #  define SSI_AD_D             (1 << 24)
 #  define SSI_AD_ADDR_BIT      16


@@ -1210,12 +1210,12 @@ enum soc_au1200_ints {
 #define SSI0_CLKDIV            0xB1600028
 #define SSI0_CONTROL           0xB1600100
 #  define SSI_CONTROL_CD       (1 << 1)
 #define SSI0_CLKDIV            0xB1600028
 #define SSI0_CONTROL           0xB1600100
 #  define SSI_CONTROL_CD       (1 << 1)

-#  define SSI_CONTROL_E        (1 << 0)
+#  define SSI_CONTROL_E                (1 << 0)

 
 /* SSI1 */
 #define SSI1_STATUS            0xB1680000
 #define SSI1_INT               0xB1680004
 
 /* SSI1 */
 #define SSI1_STATUS            0xB1680000
 #define SSI1_INT               0xB1680004

-#define SSI1_INT_ENABLE        0xB1680008
+#define SSI1_INT_ENABLE                0xB1680008

 #define SSI1_CONFIG            0xB1680020
 #define SSI1_ADATA             0xB1680024
 #define SSI1_CLKDIV            0xB1680028
 #define SSI1_CONFIG            0xB1680020
 #define SSI1_ADATA             0xB1680024
 #define SSI1_CLKDIV            0xB1680028


@@ -1242,8 +1242,8 @@ enum soc_au1200_ints {
 
 #define SSI_CONFIG_AO          (1 << 24)
 #define SSI_CONFIG_DO          (1 << 23)
 
 #define SSI_CONFIG_AO          (1 << 24)
 #define SSI_CONFIG_DO          (1 << 23)

-#define SSI_CONFIG_ALEN        (7 << 20)
-#define SSI_CONFIG_DLEN        (15 << 16)
+#define SSI_CONFIG_ALEN                (7 << 20)
+#define SSI_CONFIG_DLEN                (15 << 16)

 #define SSI_CONFIG_DD          (1 << 11)
 #define SSI_CONFIG_AD          (1 << 10)
 #define SSI_CONFIG_BM          (3 << 8)
 #define SSI_CONFIG_DD          (1 << 11)
 #define SSI_CONFIG_AD          (1 << 10)
 #define SSI_CONFIG_BM          (3 << 8)


@@ -1305,7 +1305,7 @@ struct au1k_irda_platform_data {
 #  define SYS_PF_CS            (1 << 16)       /* EXTCLK0/32KHz to gpio2 */
 #  define SYS_PF_EX0           (1 << 9)        /* GPIO2/clock */
 
 #  define SYS_PF_CS            (1 << 16)       /* EXTCLK0/32KHz to gpio2 */
 #  define SYS_PF_EX0           (1 << 9)        /* GPIO2/clock */
 

-/* Au1550 only.  Redefines lots of pins */
+/* Au1550 only.         Redefines lots of pins */

 #  define SYS_PF_PSC2_MASK     (7 << 17)
 #  define SYS_PF_PSC2_AC97     0
 #  define SYS_PF_PSC2_SPI      0
 #  define SYS_PF_PSC2_MASK     (7 << 17)
 #  define SYS_PF_PSC2_AC97     0
 #  define SYS_PF_PSC2_SPI      0


@@ -1322,33 +1322,33 @@ struct au1k_irda_platform_data {
 #  define SYS_PF_MUST_BE_SET   ((1 << 5) | (1 << 2))
 
 /* Au1200 only */
 #  define SYS_PF_MUST_BE_SET   ((1 << 5) | (1 << 2))
 
 /* Au1200 only */

-#define SYS_PINFUNC_DMA        (1 << 31)
-#define SYS_PINFUNC_S0A        (1 << 30)
-#define SYS_PINFUNC_S1A        (1 << 29)
-#define SYS_PINFUNC_LP0        (1 << 28)
-#define SYS_PINFUNC_LP1        (1 << 27)
-#define SYS_PINFUNC_LD16       (1 << 26)
-#define SYS_PINFUNC_LD8        (1 << 25)
-#define SYS_PINFUNC_LD1        (1 << 24)
-#define SYS_PINFUNC_LD0        (1 << 23)
-#define SYS_PINFUNC_P1A        (3 << 21)
-#define SYS_PINFUNC_P1B        (1 << 20)
-#define SYS_PINFUNC_FS3        (1 << 19)
-#define SYS_PINFUNC_P0A        (3 << 17)
+#define SYS_PINFUNC_DMA                (1 << 31)
+#define SYS_PINFUNC_S0A                (1 << 30)
+#define SYS_PINFUNC_S1A                (1 << 29)
+#define SYS_PINFUNC_LP0                (1 << 28)
+#define SYS_PINFUNC_LP1                (1 << 27)
+#define SYS_PINFUNC_LD16       (1 << 26)
+#define SYS_PINFUNC_LD8                (1 << 25)
+#define SYS_PINFUNC_LD1                (1 << 24)
+#define SYS_PINFUNC_LD0                (1 << 23)
+#define SYS_PINFUNC_P1A                (3 << 21)
+#define SYS_PINFUNC_P1B                (1 << 20)
+#define SYS_PINFUNC_FS3                (1 << 19)
+#define SYS_PINFUNC_P0A                (3 << 17)

 #define SYS_PINFUNC_CS         (1 << 16)
 #define SYS_PINFUNC_CS         (1 << 16)

-#define SYS_PINFUNC_CIM        (1 << 15)
-#define SYS_PINFUNC_P1C        (1 << 14)
-#define SYS_PINFUNC_U1T        (1 << 12)
-#define SYS_PINFUNC_U1R        (1 << 11)
-#define SYS_PINFUNC_EX1        (1 << 10)
-#define SYS_PINFUNC_EX0        (1 << 9)
-#define SYS_PINFUNC_U0R        (1 << 8)
+#define SYS_PINFUNC_CIM                (1 << 15)
+#define SYS_PINFUNC_P1C                (1 << 14)
+#define SYS_PINFUNC_U1T                (1 << 12)
+#define SYS_PINFUNC_U1R                (1 << 11)
+#define SYS_PINFUNC_EX1                (1 << 10)
+#define SYS_PINFUNC_EX0                (1 << 9)
+#define SYS_PINFUNC_U0R                (1 << 8)

 #define SYS_PINFUNC_MC         (1 << 7)
 #define SYS_PINFUNC_MC         (1 << 7)

-#define SYS_PINFUNC_S0B        (1 << 6)
-#define SYS_PINFUNC_S0C        (1 << 5)
-#define SYS_PINFUNC_P0B        (1 << 4)
-#define SYS_PINFUNC_U0T        (1 << 3)
-#define SYS_PINFUNC_S1B        (1 << 2)
+#define SYS_PINFUNC_S0B                (1 << 6)
+#define SYS_PINFUNC_S0C                (1 << 5)
+#define SYS_PINFUNC_P0B                (1 << 4)
+#define SYS_PINFUNC_U0T                (1 << 3)
+#define SYS_PINFUNC_S1B                (1 << 2)

 
 /* Power Management */
 #define SYS_SCRATCH0           0xB1900018
 
 /* Power Management */
 #define SYS_SCRATCH0           0xB1900018


@@ -1405,7 +1405,7 @@ struct au1k_irda_platform_data {
 #  define SYS_CS_DI2           (1 << 16)
 #  define SYS_CS_CI2           (1 << 15)
 
 #  define SYS_CS_DI2           (1 << 16)
 #  define SYS_CS_CI2           (1 << 15)
 

-#  define SYS_CS_ML_BIT        7
+#  define SYS_CS_ML_BIT                7

 #  define SYS_CS_ML_MASK       (0x7 << SYS_CS_ML_BIT)
 #  define SYS_CS_DL            (1 << 6)
 #  define SYS_CS_CL            (1 << 5)
 #  define SYS_CS_ML_MASK       (0x7 << SYS_CS_ML_BIT)
 #  define SYS_CS_DL            (1 << 6)
 #  define SYS_CS_CL            (1 << 5)


@@ -1554,8 +1554,8 @@ struct au1k_irda_platform_data {
 #define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16)
 #define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff)
 #define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16)
 #define PCI_MWMASKDEV_MWMASK(x) (((x) & 0xffff) << 16)
 #define PCI_MWMASKDEV_DEVID(x) ((x) & 0xffff)
 #define PCI_MWBASEREVCCL_BASE(x) (((x) & 0xffff) << 16)

-#define PCI_MWBASEREVCCL_REV(x)  (((x) & 0xff) << 8)
-#define PCI_MWBASEREVCCL_CCL(x)  ((x) & 0xff)
+#define PCI_MWBASEREVCCL_REV(x)         (((x) & 0xff) << 8)
+#define PCI_MWBASEREVCCL_CCL(x)         ((x) & 0xff)

 #define PCI_ID_DID(x)          (((x) & 0xffff) << 16)
 #define PCI_ID_VID(x)          ((x) & 0xffff)
 #define PCI_STATCMD_STATUS(x)  (((x) & 0xffff) << 16)
 #define PCI_ID_DID(x)          (((x) & 0xffff) << 16)
 #define PCI_ID_VID(x)          ((x) & 0xffff)
 #define PCI_STATCMD_STATUS(x)  (((x) & 0xffff) << 16)

diff --git a/arch/mips/include/asm/mach-au1x00/au1000_dma.h b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
index ba4cf0e91c8b40a1306563f57f5d124a4ff305c0..7cedca5a305c1c25ef1a09cee5720a060d006f9c 100644 (file)
--- a/arch/mips/include/asm/mach-au1x00/au1000_dma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000_dma.h
@@ -34,7 +34,7 @@
 #include <linux/spinlock.h>    /* And spinlocks */
 #include <linux/delay.h>
 
 #include <linux/spinlock.h>    /* And spinlocks */
 #include <linux/delay.h>
 

-#define NUM_AU1000_DMA_CHANNELS        8
+#define NUM_AU1000_DMA_CHANNELS 8

 
 /* DMA Channel Register Offsets */
 #define DMA_MODE_SET           0x00000000
 
 /* DMA Channel Register Offsets */
 #define DMA_MODE_SET           0x00000000


@@ -47,7 +47,7 @@
 #define DMA_DS                 (1 << 15)
 #define DMA_BE                 (1 << 13)
 #define DMA_DR                 (1 << 12)
 #define DMA_DS                 (1 << 15)
 #define DMA_BE                 (1 << 13)
 #define DMA_DR                 (1 << 12)

-#define DMA_TS8                (1 << 11)
+#define DMA_TS8                        (1 << 11)

 #define DMA_DW_BIT             9
 #define DMA_DW_MASK            (0x03 << DMA_DW_BIT)
 #define DMA_DW8                        (0 << DMA_DW_BIT)
 #define DMA_DW_BIT             9
 #define DMA_DW_MASK            (0x03 << DMA_DW_BIT)
 #define DMA_DW8                        (0 << DMA_DW_BIT)


@@ -59,9 +59,9 @@
 #define DMA_GO                 (1 << 5)
 #define DMA_AB                 (1 << 4)
 #define DMA_D1                 (1 << 3)
 #define DMA_GO                 (1 << 5)
 #define DMA_AB                 (1 << 4)
 #define DMA_D1                 (1 << 3)

-#define DMA_BE1                (1 << 2)
+#define DMA_BE1                        (1 << 2)

 #define DMA_D0                 (1 << 1)
 #define DMA_D0                 (1 << 1)

-#define DMA_BE0                (1 << 0)
+#define DMA_BE0                        (1 << 0)

 
 #define DMA_PERIPHERAL_ADDR    0x00000008
 #define DMA_BUFFER0_START      0x0000000C
 
 #define DMA_PERIPHERAL_ADDR    0x00000008
 #define DMA_BUFFER0_START      0x0000000C


@@ -246,7 +246,7 @@ static inline void init_dma(unsigned int dmanr)
                mode |= DMA_IE;
 
        au_writel(~mode, chan->io + DMA_MODE_CLEAR);
                mode |= DMA_IE;
 
        au_writel(~mode, chan->io + DMA_MODE_CLEAR);

-       au_writel(mode,  chan->io + DMA_MODE_SET);
+       au_writel(mode,  chan->io + DMA_MODE_SET);

 }
 
 /*
 }
 
 /*

diff --git a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
index e221659f1bca5ae0f788b554b80d188a561b5eee..cadab91cee26977317eced8d62c946c9b42e2333 100644 (file)
--- a/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1100_mmc.h
@@ -148,7 +148,7 @@ struct au1xmmc_platform_data {
 /*
  *  SD_STATUS bit definitions.
  */
 /*
  *  SD_STATUS bit definitions.
  */

-#define SD_STATUS_DCRCW        (0x00000007)
+#define SD_STATUS_DCRCW (0x00000007)

 #define SD_STATUS_xx1  (0x00000008)
 #define SD_STATUS_CB   (0x00000010)
 #define SD_STATUS_DB   (0x00000020)
 #define SD_STATUS_xx1  (0x00000008)
 #define SD_STATUS_CB   (0x00000010)
 #define SD_STATUS_DB   (0x00000020)

diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index 217810e18361c3e31e351efd11a5bde15cc9fc70..ca8077afac4a78078226baff94c3faa77f80a977 100644 (file)
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -103,7 +103,7 @@ typedef volatile struct au1xxx_ddma_desc {
         * Lets have some SW data following -- make sure it's 32 bytes.
         */
        u32     sw_status;
         * Lets have some SW data following -- make sure it's 32 bytes.
         */
        u32     sw_status;

-       u32     sw_context;
+       u32     sw_context;

        u32     sw_reserved[6];
 } au1x_ddma_desc_t;
 
        u32     sw_reserved[6];
 } au1x_ddma_desc_t;
 


@@ -123,7 +123,7 @@ typedef volatile struct au1xxx_ddma_desc {
 #define DSCR_CMD0_CV           (0x1 << 2)      /* Clear Valid when done */
 #define DSCR_CMD0_ST_MASK      (0x3 << 0)      /* Status instruction */
 
 #define DSCR_CMD0_CV           (0x1 << 2)      /* Clear Valid when done */
 #define DSCR_CMD0_ST_MASK      (0x3 << 0)      /* Status instruction */
 

-#define SW_STATUS_INUSE        (1 << 0)
+#define SW_STATUS_INUSE                (1 << 0)

 
 /* Command 0 device IDs. */
 #define AU1550_DSCR_CMD0_UART0_TX      0
 
 /* Command 0 device IDs. */
 #define AU1550_DSCR_CMD0_UART0_TX      0


@@ -195,8 +195,8 @@ typedef volatile struct au1xxx_ddma_desc {
 #define AU1300_DSCR_CMD0_SDMS_RX0      9
 #define AU1300_DSCR_CMD0_SDMS_TX1      10
 #define AU1300_DSCR_CMD0_SDMS_RX1      11
 #define AU1300_DSCR_CMD0_SDMS_RX0      9
 #define AU1300_DSCR_CMD0_SDMS_TX1      10
 #define AU1300_DSCR_CMD0_SDMS_RX1      11

-#define AU1300_DSCR_CMD0_AES_TX        12
-#define AU1300_DSCR_CMD0_AES_RX        13
+#define AU1300_DSCR_CMD0_AES_TX               12
+#define AU1300_DSCR_CMD0_AES_RX               13

 #define AU1300_DSCR_CMD0_PSC0_TX       14
 #define AU1300_DSCR_CMD0_PSC0_RX       15
 #define AU1300_DSCR_CMD0_PSC1_TX       16
 #define AU1300_DSCR_CMD0_PSC0_TX       14
 #define AU1300_DSCR_CMD0_PSC0_RX       15
 #define AU1300_DSCR_CMD0_PSC1_TX       16


@@ -205,12 +205,12 @@ typedef volatile struct au1xxx_ddma_desc {
 #define AU1300_DSCR_CMD0_PSC2_RX       19
 #define AU1300_DSCR_CMD0_PSC3_TX       20
 #define AU1300_DSCR_CMD0_PSC3_RX       21
 #define AU1300_DSCR_CMD0_PSC2_RX       19
 #define AU1300_DSCR_CMD0_PSC3_TX       20
 #define AU1300_DSCR_CMD0_PSC3_RX       21

-#define AU1300_DSCR_CMD0_LCD           22
+#define AU1300_DSCR_CMD0_LCD          22

 #define AU1300_DSCR_CMD0_NAND_FLASH    23
 #define AU1300_DSCR_CMD0_SDMS_TX2      24
 #define AU1300_DSCR_CMD0_SDMS_RX2      25
 #define AU1300_DSCR_CMD0_CIM_SYNC      26
 #define AU1300_DSCR_CMD0_NAND_FLASH    23
 #define AU1300_DSCR_CMD0_SDMS_TX2      24
 #define AU1300_DSCR_CMD0_SDMS_RX2      25
 #define AU1300_DSCR_CMD0_CIM_SYNC      26

-#define AU1300_DSCR_CMD0_UDMA          27
+#define AU1300_DSCR_CMD0_UDMA         27

 #define AU1300_DSCR_CMD0_DMA_REQ0      28
 #define AU1300_DSCR_CMD0_DMA_REQ1      29
 
 #define AU1300_DSCR_CMD0_DMA_REQ0      28
 #define AU1300_DSCR_CMD0_DMA_REQ1      29
 


@@ -298,7 +298,7 @@ typedef volatile struct au1xxx_ddma_desc {
 #define DSCR_NXTPTR_MS         (1 << 27)
 
 /* The number of DBDMA channels. */
 #define DSCR_NXTPTR_MS         (1 << 27)
 
 /* The number of DBDMA channels. */

-#define NUM_DBDMA_CHANS        16
+#define NUM_DBDMA_CHANS 16

 
 /*
  * DDMA API definitions
 
 /*
  * DDMA API definitions


@@ -316,7 +316,7 @@ typedef struct dbdma_device_table {
 
 
 typedef struct dbdma_chan_config {
 
 
 typedef struct dbdma_chan_config {

-       spinlock_t      lock;
+       spinlock_t      lock;

 
        u32                     chan_flags;
        u32                     chan_index;
 
        u32                     chan_flags;
        u32                     chan_index;

diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
index e306384b1414f2cd35301e81f9705e3d052d0f6c..bb91b8923a49e22bb0683e3b0ee60ec4cefdcf15 100644 (file)
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
@@ -1,5 +1,5 @@
 /*
 /*

- * include/asm-mips/mach-au1x00/au1xxx_ide.h  version 01.30.00   Aug. 02 2005
+ * include/asm-mips/mach-au1x00/au1xxx_ide.h  version 01.30.00  Aug. 02 2005

  *
  * BRIEF MODULE DESCRIPTION
  * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
  *
  * BRIEF MODULE DESCRIPTION
  * AMD Alchemy Au1xxx IDE interface routines over the Static Bus


@@ -27,14 +27,14 @@
  * 675 Mass Ave, Cambridge, MA 02139, USA.
  *
  * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
  * 675 Mass Ave, Cambridge, MA 02139, USA.
  *
  * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE

- *       Interface and Linux Device Driver" Application Note.
+ *      Interface and Linux Device Driver" Application Note.

  */
 
 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 #define DMA_WAIT_TIMEOUT       100
  */
 
 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 #define DMA_WAIT_TIMEOUT       100

-#define NUM_DESCRIPTORS        PRD_ENTRIES
+#define NUM_DESCRIPTORS                PRD_ENTRIES

 #else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
 #else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */

-#define NUM_DESCRIPTORS        2
+#define NUM_DESCRIPTORS                2

 #endif
 
 #ifndef AU1XXX_ATA_RQSIZE
 #endif
 
 #ifndef AU1XXX_ATA_RQSIZE


@@ -84,8 +84,8 @@ typedef struct {
 #define TWP_MASK               (0x3F << 14)
 #define TCSW_MASK              (0x0F << 10)
 #define TPM_MASK               (0x0F << 6)
 #define TWP_MASK               (0x3F << 14)
 #define TCSW_MASK              (0x0F << 10)
 #define TPM_MASK               (0x0F << 6)

-#define TA_MASK                (0x3F << 0)
-#define TS_MASK                (1 << 8)
+#define TA_MASK                        (0x3F << 0)
+#define TS_MASK                        (1 << 8)

 
 /* Timing parameters PIO mode 0 */
 #define SBC_IDE_PIO0_TCSOE     (0x04 << 29)
 
 /* Timing parameters PIO mode 0 */
 #define SBC_IDE_PIO0_TCSOE     (0x04 << 29)


@@ -96,7 +96,7 @@ typedef struct {
 #define SBC_IDE_PIO0_TWP       (0x10 << 14)
 #define SBC_IDE_PIO0_TCSW      (0x04 << 10)
 #define SBC_IDE_PIO0_TPM       (0x00 << 6)
 #define SBC_IDE_PIO0_TWP       (0x10 << 14)
 #define SBC_IDE_PIO0_TCSW      (0x04 << 10)
 #define SBC_IDE_PIO0_TPM       (0x00 << 6)

-#define SBC_IDE_PIO0_TA        (0x15 << 0)
+#define SBC_IDE_PIO0_TA                (0x15 << 0)

 /* Timing parameters PIO mode 1 */
 #define SBC_IDE_PIO1_TCSOE     (0x03 << 29)
 #define SBC_IDE_PIO1_TOECS     (0x01 << 26)
 /* Timing parameters PIO mode 1 */
 #define SBC_IDE_PIO1_TCSOE     (0x03 << 29)
 #define SBC_IDE_PIO1_TOECS     (0x01 << 26)


@@ -106,7 +106,7 @@ typedef struct {
 #define SBC_IDE_PIO1_TWP       (0x08 << 14)
 #define SBC_IDE_PIO1_TCSW      (0x03 << 10)
 #define SBC_IDE_PIO1_TPM       (0x00 << 6)
 #define SBC_IDE_PIO1_TWP       (0x08 << 14)
 #define SBC_IDE_PIO1_TCSW      (0x03 << 10)
 #define SBC_IDE_PIO1_TPM       (0x00 << 6)

-#define SBC_IDE_PIO1_TA        (0x0B << 0)
+#define SBC_IDE_PIO1_TA                (0x0B << 0)

 /* Timing parameters PIO mode 2 */
 #define SBC_IDE_PIO2_TCSOE     (0x05 << 29)
 #define SBC_IDE_PIO2_TOECS     (0x01 << 26)
 /* Timing parameters PIO mode 2 */
 #define SBC_IDE_PIO2_TCSOE     (0x05 << 29)
 #define SBC_IDE_PIO2_TOECS     (0x01 << 26)


@@ -116,7 +116,7 @@ typedef struct {
 #define SBC_IDE_PIO2_TWP       (0x1F << 14)
 #define SBC_IDE_PIO2_TCSW      (0x05 << 10)
 #define SBC_IDE_PIO2_TPM       (0x00 << 6)
 #define SBC_IDE_PIO2_TWP       (0x1F << 14)
 #define SBC_IDE_PIO2_TCSW      (0x05 << 10)
 #define SBC_IDE_PIO2_TPM       (0x00 << 6)

-#define SBC_IDE_PIO2_TA        (0x22 << 0)
+#define SBC_IDE_PIO2_TA                (0x22 << 0)

 /* Timing parameters PIO mode 3 */
 #define SBC_IDE_PIO3_TCSOE     (0x05 << 29)
 #define SBC_IDE_PIO3_TOECS     (0x01 << 26)
 /* Timing parameters PIO mode 3 */
 #define SBC_IDE_PIO3_TCSOE     (0x05 << 29)
 #define SBC_IDE_PIO3_TOECS     (0x01 << 26)


@@ -126,7 +126,7 @@ typedef struct {
 #define SBC_IDE_PIO3_TWP       (0x15 << 14)
 #define SBC_IDE_PIO3_TCSW      (0x05 << 10)
 #define SBC_IDE_PIO3_TPM       (0x00 << 6)
 #define SBC_IDE_PIO3_TWP       (0x15 << 14)
 #define SBC_IDE_PIO3_TCSW      (0x05 << 10)
 #define SBC_IDE_PIO3_TPM       (0x00 << 6)

-#define SBC_IDE_PIO3_TA        (0x1A << 0)
+#define SBC_IDE_PIO3_TA                (0x1A << 0)

 /* Timing parameters PIO mode 4 */
 #define SBC_IDE_PIO4_TCSOE     (0x04 << 29)
 #define SBC_IDE_PIO4_TOECS     (0x01 << 26)
 /* Timing parameters PIO mode 4 */
 #define SBC_IDE_PIO4_TCSOE     (0x04 << 29)
 #define SBC_IDE_PIO4_TOECS     (0x01 << 26)


@@ -136,7 +136,7 @@ typedef struct {
 #define SBC_IDE_PIO4_TWP       (0x0D << 14)
 #define SBC_IDE_PIO4_TCSW      (0x03 << 10)
 #define SBC_IDE_PIO4_TPM       (0x00 << 6)
 #define SBC_IDE_PIO4_TWP       (0x0D << 14)
 #define SBC_IDE_PIO4_TCSW      (0x03 << 10)
 #define SBC_IDE_PIO4_TPM       (0x00 << 6)

-#define SBC_IDE_PIO4_TA        (0x12 << 0)
+#define SBC_IDE_PIO4_TA                (0x12 << 0)

 /* Timing parameters MDMA mode 0 */
 #define SBC_IDE_MDMA0_TCSOE    (0x03 << 29)
 #define SBC_IDE_MDMA0_TOECS    (0x01 << 26)
 /* Timing parameters MDMA mode 0 */
 #define SBC_IDE_MDMA0_TCSOE    (0x03 << 29)
 #define SBC_IDE_MDMA0_TOECS    (0x01 << 26)

diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
index 4e3f3bc26c6071af89a74f4dd75c77ea05969ca4..8a9cd754be2da9e414b0b3083af05fd8e9679a4c 100644 (file)
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_psc.h
@@ -53,7 +53,7 @@
 
 #define PSC_CTRL_DISABLE       0
 #define PSC_CTRL_SUSPEND       2
 
 #define PSC_CTRL_DISABLE       0
 #define PSC_CTRL_SUSPEND       2

-#define PSC_CTRL_ENABLE        3
+#define PSC_CTRL_ENABLE                3

 
 /* AC97 Registers. */
 #define PSC_AC97CFG_OFFSET     0x00000008
 
 /* AC97 Registers. */
 #define PSC_AC97CFG_OFFSET     0x00000008


@@ -85,8 +85,8 @@
 #define PSC_AC97CFG_SE_ENABLE  (1 << 25)
 
 #define PSC_AC97CFG_LEN_MASK   (0xf << 21)
 #define PSC_AC97CFG_SE_ENABLE  (1 << 25)
 
 #define PSC_AC97CFG_LEN_MASK   (0xf << 21)

-#define PSC_AC97CFG_TXSLOT_MASK        (0x3ff << 11)
-#define PSC_AC97CFG_RXSLOT_MASK        (0x3ff << 1)
+#define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11)
+#define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1)

 #define PSC_AC97CFG_GE_ENABLE  (1)
 
 /* Enable slots 3-12. */
 #define PSC_AC97CFG_GE_ENABLE  (1)
 
 /* Enable slots 3-12. */


@@ -95,7 +95,7 @@
 
 /*
  * The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
 
 /*
  * The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.

- * The only sensible numbers are 7, 9, or possibly 11.  Nah, just do the
+ * The only sensible numbers are 7, 9, or possibly 11. Nah, just do the

  * arithmetic in the macro.
  */
 #define PSC_AC97CFG_SET_LEN(x) (((((x) - 2) / 2) & 0xf) << 21)
  * arithmetic in the macro.
  */
 #define PSC_AC97CFG_SET_LEN(x) (((((x) - 2) / 2) & 0xf) << 21)

diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
index 73853b5a2a31d1ace4cf4cf4e7bc150825d9273e..796afd051c35ee24cd8c20ad074927d3643fcf0e 100644 (file)
--- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h
@@ -12,14 +12,14 @@
 #include <asm/mach-au1x00/au1000.h>
 
 /* The default GPIO numberspace as documented in the Alchemy manuals.
 #include <asm/mach-au1x00/au1000.h>
 
 /* The default GPIO numberspace as documented in the Alchemy manuals.

- * GPIO0-31 from GPIO1 block,   GPIO200-215 from GPIO2 block.
+ * GPIO0-31 from GPIO1 block,  GPIO200-215 from GPIO2 block.

  */
 #define ALCHEMY_GPIO1_BASE     0
 #define ALCHEMY_GPIO2_BASE     200
 
 #define ALCHEMY_GPIO1_NUM      32
 #define ALCHEMY_GPIO2_NUM      16
  */
 #define ALCHEMY_GPIO1_BASE     0
 #define ALCHEMY_GPIO2_BASE     200
 
 #define ALCHEMY_GPIO1_NUM      32
 #define ALCHEMY_GPIO2_NUM      16

-#define ALCHEMY_GPIO1_MAX      (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
+#define ALCHEMY_GPIO1_MAX      (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)

 #define ALCHEMY_GPIO2_MAX      (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
 
 #define MAKE_IRQ(intc, off)    (AU1000_INTC##intc##_INT_BASE + (off))
 #define ALCHEMY_GPIO2_MAX      (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
 
 #define MAKE_IRQ(intc, off)    (AU1000_INTC##intc##_INT_BASE + (off))


@@ -67,7 +67,7 @@ static inline int au1500_gpio1_to_irq(int gpio)
        switch (gpio) {
        case 0 ... 15:
        case 20:
        switch (gpio) {
        case 0 ... 15:
        case 20:

-       case 23 ... 28: return MAKE_IRQ(1, gpio);
+       case 23 ... 28: return MAKE_IRQ(1, gpio);

        }
 
        return -ENXIO;
        }
 
        return -ENXIO;


@@ -139,8 +139,8 @@ static inline int au1550_gpio1_to_irq(int gpio)
 
        switch (gpio) {
        case 0 ... 15:
 
        switch (gpio) {
        case 0 ... 15:

-       case 20 ... 28: return MAKE_IRQ(1, gpio);
-       case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16);
+       case 20 ... 28: return MAKE_IRQ(1, gpio);
+       case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16);

        }
 
        return -ENXIO;
        }
 
        return -ENXIO;


@@ -152,9 +152,9 @@ static inline int au1550_gpio2_to_irq(int gpio)
 
        switch (gpio) {
        case 0:         return MAKE_IRQ(1, 16);
 
        switch (gpio) {
        case 0:         return MAKE_IRQ(1, 16);

-       case 1 ... 5:   return MAKE_IRQ(1, 17); /* shared GPIO201_205 */
+       case 1 ... 5:   return MAKE_IRQ(1, 17); /* shared GPIO201_205 */

        case 6 ... 7:   return MAKE_IRQ(1, 29 + gpio - 6);
        case 6 ... 7:   return MAKE_IRQ(1, 29 + gpio - 6);

-       case 8 ... 15:  return MAKE_IRQ(1, 31); /* shared GPIO208_215 */
+       case 8 ... 15:  return MAKE_IRQ(1, 31); /* shared GPIO208_215 */

        }
 
        return -ENXIO;
        }
 
        return -ENXIO;


@@ -190,7 +190,7 @@ static inline int au1200_gpio2_to_irq(int gpio)
        case 0 ... 2:   return MAKE_IRQ(0, 5 + gpio - 0);
        case 3:         return MAKE_IRQ(0, 22);
        case 4 ... 7:   return MAKE_IRQ(0, 24 + gpio - 4);
        case 0 ... 2:   return MAKE_IRQ(0, 5 + gpio - 0);
        case 3:         return MAKE_IRQ(0, 22);
        case 4 ... 7:   return MAKE_IRQ(0, 24 + gpio - 4);

-       case 8 ... 15:  return MAKE_IRQ(0, 28); /* shared GPIO208_215 */
+       case 8 ... 15:  return MAKE_IRQ(0, 28); /* shared GPIO208_215 */

        }
 
        return -ENXIO;
        }
 
        return -ENXIO;


@@ -428,7 +428,7 @@ static inline void alchemy_gpio2_disable_int(int gpio2)
 /**
  * alchemy_gpio2_enable -  Activate GPIO2 block.
  *
 /**
  * alchemy_gpio2_enable -  Activate GPIO2 block.
  *

- * The GPIO2 block must be enabled excplicitly to work.  On systems
+ * The GPIO2 block must be enabled excplicitly to work.         On systems

  * where this isn't done by the bootloader, this macro can be used.
  */
 static inline void alchemy_gpio2_enable(void)
  * where this isn't done by the bootloader, this macro can be used.
  */
 static inline void alchemy_gpio2_enable(void)


@@ -533,7 +533,7 @@ static inline int alchemy_irq_to_gpio(int irq)
  *     2 (1 for Au1000) gpio_chips are registered.
  *
  *(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
  *     2 (1 for Au1000) gpio_chips are registered.
  *
  *(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:

- *     the boards' gpio.h must provide the linux gpio wrapper functions,
+ *     the boards' gpio.h must provide the linux gpio wrapper functions,

  *
  *(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
  *     inlinable gpio functions are provided which enable access to the
  *
  *(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
  *     inlinable gpio functions are provided which enable access to the

diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
index fb9975c74c571a01526f42667a8f0d7cbedf235e..ce02894271c6d7539e2b264a897b2d74067bfe2b 100644 (file)
--- a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
+++ b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h
@@ -130,7 +130,7 @@ static inline int au1300_gpio_getinitlvl(unsigned int gpio)
 *      A gpiochip for the 75 GPIOs is registered.
 *
 *(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:
 *      A gpiochip for the 75 GPIOs is registered.
 *
 *(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y:

-*      the boards' gpio.h must provide the linux gpio wrapper functions,
+*      the boards' gpio.h must provide the linux gpio wrapper functions,

 *
 *(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
 *      inlinable gpio functions are provided which enable access to the
 *
 *(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n:
 *      inlinable gpio functions are provided which enable access to the

diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index dbd5b5ad07a59b6f65dd9a48600e21ac335e2ea3..cb922b9cb0e9b1e7cc96f36149a24bd8b97e70cb 100644 (file)
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -182,7 +182,7 @@ enum bcm63xx_regs_set {
 #define BCM_6328_PERF_BASE             (0xb0000000)
 #define BCM_6328_TIMER_BASE            (0xb0000040)
 #define BCM_6328_WDT_BASE              (0xb000005c)
 #define BCM_6328_PERF_BASE             (0xb0000000)
 #define BCM_6328_TIMER_BASE            (0xb0000040)
 #define BCM_6328_WDT_BASE              (0xb000005c)

-#define BCM_6328_UART0_BASE             (0xb0000100)
+#define BCM_6328_UART0_BASE            (0xb0000100)

 #define BCM_6328_UART1_BASE            (0xb0000120)
 #define BCM_6328_GPIO_BASE             (0xb0000080)
 #define BCM_6328_SPI_BASE              (0xdeadbeef)
 #define BCM_6328_UART1_BASE            (0xb0000120)
 #define BCM_6328_GPIO_BASE             (0xb0000080)
 #define BCM_6328_SPI_BASE              (0xdeadbeef)

diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
index 03a54df5fb86a6a4d2753422c48eda5126d9d6e0..7033144aab2db0446c1ae3b3023440cb3d235620 100644 (file)
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
@@ -88,7 +88,7 @@
 #define bcm_mpi_readl(o)       bcm_rset_readl(RSET_MPI, (o))
 #define bcm_mpi_writel(v, o)   bcm_rset_writel(RSET_MPI, (v), (o))
 #define bcm_pcmcia_readl(o)    bcm_rset_readl(RSET_PCMCIA, (o))
 #define bcm_mpi_readl(o)       bcm_rset_readl(RSET_MPI, (o))
 #define bcm_mpi_writel(v, o)   bcm_rset_writel(RSET_MPI, (v), (o))
 #define bcm_pcmcia_readl(o)    bcm_rset_readl(RSET_PCMCIA, (o))

-#define bcm_pcmcia_writel(v, o)        bcm_rset_writel(RSET_PCMCIA, (v), (o))
+#define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o))

 #define bcm_pcie_readl(o)      bcm_rset_readl(RSET_PCIE, (o))
 #define bcm_pcie_writel(v, o)  bcm_rset_writel(RSET_PCIE, (v), (o))
 #define bcm_sdram_readl(o)     bcm_rset_readl(RSET_SDRAM, (o))
 #define bcm_pcie_readl(o)      bcm_rset_readl(RSET_PCIE, (o))
 #define bcm_pcie_writel(v, o)  bcm_rset_writel(RSET_PCIE, (v), (o))
 #define bcm_sdram_readl(o)     bcm_rset_readl(RSET_SDRAM, (o))

diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h
index a5bbff31c898226192ce47a3b779f3bf47a0fa52..1e89df7244bdfc006bbc688db6fbf17d1a3d6188 100644 (file)
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h
@@ -19,7 +19,7 @@ struct bcm_enet_desc {
 #define DMADESC_SOP_MASK       (1 << 13)
 #define DMADESC_ESOP_MASK      (DMADESC_EOP_MASK | DMADESC_SOP_MASK)
 #define DMADESC_WRAP_MASK      (1 << 12)
 #define DMADESC_SOP_MASK       (1 << 13)
 #define DMADESC_ESOP_MASK      (DMADESC_EOP_MASK | DMADESC_SOP_MASK)
 #define DMADESC_WRAP_MASK      (1 << 12)

-#define DMADESC_USB_NOZERO_MASK        (1 << 1)
+#define DMADESC_USB_NOZERO_MASK (1 << 1)

 #define DMADESC_USB_ZERO_MASK  (1 << 0)
 
 /* status */
 #define DMADESC_USB_ZERO_MASK  (1 << 0)
 
 /* status */

diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index c3eeb90b480a9ede77019b1d06712ae9fb9e1079..81b4702f792a81693dbfc49db980276296967cff 100644 (file)
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -143,7 +143,7 @@
                                        CKCTL_6368_NAND_EN |            \
                                        CKCTL_6368_IPSEC_EN)
 
                                        CKCTL_6368_NAND_EN |            \
                                        CKCTL_6368_IPSEC_EN)
 

-/* System PLL Control register  */
+/* System PLL Control register */

 #define PERF_SYS_PLL_CTL_REG           0x8
 #define SYS_PLL_SOFT_RESET             0x1
 
 #define PERF_SYS_PLL_CTL_REG           0x8
 #define SYS_PLL_SOFT_RESET             0x1
 


@@ -219,7 +219,7 @@
 #define SOFTRESET_6338_DMAMEM_MASK     (1 << 6)
 #define SOFTRESET_6338_SAR_MASK                (1 << 7)
 #define SOFTRESET_6338_ACLC_MASK       (1 << 8)
 #define SOFTRESET_6338_DMAMEM_MASK     (1 << 6)
 #define SOFTRESET_6338_SAR_MASK                (1 << 7)
 #define SOFTRESET_6338_ACLC_MASK       (1 << 8)

-#define SOFTRESET_6338_ADSLMIPSPLL_MASK        (1 << 10)
+#define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10)

 #define SOFTRESET_6338_ALL      (SOFTRESET_6338_SPI_MASK |             \
                                  SOFTRESET_6338_ENET_MASK |            \
                                  SOFTRESET_6338_USBH_MASK |            \
 #define SOFTRESET_6338_ALL      (SOFTRESET_6338_SPI_MASK |             \
                                  SOFTRESET_6338_ENET_MASK |            \
                                  SOFTRESET_6338_USBH_MASK |            \


@@ -238,7 +238,7 @@
 #define SOFTRESET_6348_DMAMEM_MASK     (1 << 6)
 #define SOFTRESET_6348_SAR_MASK                (1 << 7)
 #define SOFTRESET_6348_ACLC_MASK       (1 << 8)
 #define SOFTRESET_6348_DMAMEM_MASK     (1 << 6)
 #define SOFTRESET_6348_SAR_MASK                (1 << 7)
 #define SOFTRESET_6348_ACLC_MASK       (1 << 8)

-#define SOFTRESET_6348_ADSLMIPSPLL_MASK        (1 << 10)
+#define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10)

 
 #define SOFTRESET_6348_ALL      (SOFTRESET_6348_SPI_MASK |             \
                                  SOFTRESET_6348_ENET_MASK |            \
 
 #define SOFTRESET_6348_ALL      (SOFTRESET_6348_SPI_MASK |             \
                                  SOFTRESET_6348_ENET_MASK |            \


@@ -560,7 +560,7 @@
 
 
 #define GPIO_PINMUX_OTHR_REG           0x24
 
 
 #define GPIO_PINMUX_OTHR_REG           0x24

-#define GPIO_PINMUX_OTHR_6328_USB_SHIFT        12
+#define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12

 #define GPIO_PINMUX_OTHR_6328_USB_MASK (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
 #define GPIO_PINMUX_OTHR_6328_USB_HOST (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
 #define GPIO_PINMUX_OTHR_6328_USB_DEV  (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
 #define GPIO_PINMUX_OTHR_6328_USB_MASK (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
 #define GPIO_PINMUX_OTHR_6328_USB_HOST (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
 #define GPIO_PINMUX_OTHR_6328_USB_DEV  (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)


@@ -572,12 +572,12 @@
 /* those bits must be kept as read in gpio basemode register*/
 
 #define GPIO_STRAPBUS_REG              0x40
 /* those bits must be kept as read in gpio basemode register*/
 
 #define GPIO_STRAPBUS_REG              0x40

-#define STRAPBUS_6358_BOOT_SEL_PARALLEL        (1 << 1)
+#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)

 #define STRAPBUS_6358_BOOT_SEL_SERIAL  (0 << 1)
 #define STRAPBUS_6368_BOOT_SEL_MASK    0x3
 #define STRAPBUS_6368_BOOT_SEL_NAND    0
 #define STRAPBUS_6368_BOOT_SEL_SERIAL  1
 #define STRAPBUS_6358_BOOT_SEL_SERIAL  (0 << 1)
 #define STRAPBUS_6368_BOOT_SEL_MASK    0x3
 #define STRAPBUS_6368_BOOT_SEL_NAND    0
 #define STRAPBUS_6368_BOOT_SEL_SERIAL  1

-#define STRAPBUS_6368_BOOT_SEL_PARALLEL        3
+#define STRAPBUS_6368_BOOT_SEL_PARALLEL 3

 
 
 /*************************************************************************
 
 
 /*************************************************************************


@@ -812,7 +812,7 @@
 #define USBH_PRIV_SWAP_OHCI_DATA_MASK  (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
 
 #define USBH_PRIV_UTMI_CTL_6368_REG    0x10
 #define USBH_PRIV_SWAP_OHCI_DATA_MASK  (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
 
 #define USBH_PRIV_UTMI_CTL_6368_REG    0x10

-#define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT        12
+#define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12

 #define USBH_PRIV_UTMI_CTL_NODRIV_MASK (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT)
 #define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT 0
 #define USBH_PRIV_UTMI_CTL_HOSTB_MASK  (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT)
 #define USBH_PRIV_UTMI_CTL_NODRIV_MASK (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT)
 #define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT 0
 #define USBH_PRIV_UTMI_CTL_HOSTB_MASK  (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT)


@@ -841,7 +841,7 @@
 #define USBD_CONTROL_INIT_SEL_MASK     (0xf << USBD_CONTROL_INIT_SEL_SHIFT)
 #define USBD_CONTROL_FIFO_RESET_SHIFT  6
 #define USBD_CONTROL_FIFO_RESET_MASK   (3 << USBD_CONTROL_FIFO_RESET_SHIFT)
 #define USBD_CONTROL_INIT_SEL_MASK     (0xf << USBD_CONTROL_INIT_SEL_SHIFT)
 #define USBD_CONTROL_FIFO_RESET_SHIFT  6
 #define USBD_CONTROL_FIFO_RESET_MASK   (3 << USBD_CONTROL_FIFO_RESET_SHIFT)

-#define USBD_CONTROL_SETUPERRLOCK_SHIFT        5
+#define USBD_CONTROL_SETUPERRLOCK_SHIFT 5

 #define USBD_CONTROL_SETUPERRLOCK_MASK (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT)
 #define USBD_CONTROL_DONE_CSRS_SHIFT   0
 #define USBD_CONTROL_DONE_CSRS_MASK    (1 << USBD_CONTROL_DONE_CSRS_SHIFT)
 #define USBD_CONTROL_SETUPERRLOCK_MASK (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT)
 #define USBD_CONTROL_DONE_CSRS_SHIFT   0
 #define USBD_CONTROL_DONE_CSRS_MASK    (1 << USBD_CONTROL_DONE_CSRS_SHIFT)


@@ -852,7 +852,7 @@
 #define USBD_STRAPS_APP_SELF_PWR_MASK  (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT)
 #define USBD_STRAPS_APP_DISCON_SHIFT   9
 #define USBD_STRAPS_APP_DISCON_MASK    (1 << USBD_STRAPS_APP_DISCON_SHIFT)
 #define USBD_STRAPS_APP_SELF_PWR_MASK  (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT)
 #define USBD_STRAPS_APP_DISCON_SHIFT   9
 #define USBD_STRAPS_APP_DISCON_MASK    (1 << USBD_STRAPS_APP_DISCON_SHIFT)

-#define USBD_STRAPS_APP_CSRPRGSUP_SHIFT        8
+#define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8

 #define USBD_STRAPS_APP_CSRPRGSUP_MASK (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT)
 #define USBD_STRAPS_APP_RMTWKUP_SHIFT  6
 #define USBD_STRAPS_APP_RMTWKUP_MASK   (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT)
 #define USBD_STRAPS_APP_CSRPRGSUP_MASK (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT)
 #define USBD_STRAPS_APP_RMTWKUP_SHIFT  6
 #define USBD_STRAPS_APP_RMTWKUP_MASK   (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT)


@@ -943,7 +943,7 @@
 #define USBD_EPNUM_TYPEMAP_REG         0x50
 #define USBD_EPNUM_TYPEMAP_TYPE_SHIFT  8
 #define USBD_EPNUM_TYPEMAP_TYPE_MASK   (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT)
 #define USBD_EPNUM_TYPEMAP_REG         0x50
 #define USBD_EPNUM_TYPEMAP_TYPE_SHIFT  8
 #define USBD_EPNUM_TYPEMAP_TYPE_MASK   (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT)

-#define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT        0
+#define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0

 #define USBD_EPNUM_TYPEMAP_DMA_CH_MASK (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT)
 
 /* Misc per-endpoint settings */
 #define USBD_EPNUM_TYPEMAP_DMA_CH_MASK (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT)
 
 /* Misc per-endpoint settings */


@@ -1048,8 +1048,8 @@
 #define MPI_L2PREMAP_IS_CARDBUS_MASK   (1 << 2)
 
 #define MPI_PCIMODESEL_REG             0x144
 #define MPI_L2PREMAP_IS_CARDBUS_MASK   (1 << 2)
 
 #define MPI_PCIMODESEL_REG             0x144

-#define MPI_PCIMODESEL_BAR1_NOSWAP_MASK        (1 << 0)
-#define MPI_PCIMODESEL_BAR2_NOSWAP_MASK        (1 << 1)
+#define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
+#define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)

 #define MPI_PCIMODESEL_EXT_ARB_MASK    (1 << 2)
 #define MPI_PCIMODESEL_PREFETCH_SHIFT  4
 #define MPI_PCIMODESEL_PREFETCH_MASK   (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
 #define MPI_PCIMODESEL_EXT_ARB_MASK    (1 << 2)
 #define MPI_PCIMODESEL_PREFETCH_SHIFT  4
 #define MPI_PCIMODESEL_PREFETCH_MASK   (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)

diff --git a/arch/mips/include/asm/mach-bcm63xx/irq.h b/arch/mips/include/asm/mach-bcm63xx/irq.h
index 9332e788a5c914eed326b699d61b4a8d2c0d01c8..2bbfc8d1f30762c7d6b258e277343325560affa3 100644 (file)
--- a/arch/mips/include/asm/mach-bcm63xx/irq.h
+++ b/arch/mips/include/asm/mach-bcm63xx/irq.h
@@ -1,7 +1,7 @@
 #ifndef __ASM_MACH_BCM63XX_IRQ_H
 #define __ASM_MACH_BCM63XX_IRQ_H
 
 #ifndef __ASM_MACH_BCM63XX_IRQ_H
 #define __ASM_MACH_BCM63XX_IRQ_H
 

-#define NR_IRQS        128
+#define NR_IRQS 128

 #define MIPS_CPU_IRQ_BASE 0
 
 #endif
 #define MIPS_CPU_IRQ_BASE 0
 
 #endif

diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
index 502bb1815ae8912c5341fc5826822e91cfdd0a2d..60fc4c347c44a222adafa54f05253506ec454b74 100644 (file)
--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -51,8 +51,8 @@ enum octeon_irq {
 /* 256 - 511 represent the MSI interrupts 0-255 */
 #define OCTEON_IRQ_MSI_BIT0    (256)
 
 /* 256 - 511 represent the MSI interrupts 0-255 */
 #define OCTEON_IRQ_MSI_BIT0    (256)
 

-#define OCTEON_IRQ_MSI_LAST      (OCTEON_IRQ_MSI_BIT0 + 255)
-#define OCTEON_IRQ_LAST          (OCTEON_IRQ_MSI_LAST + 1)
+#define OCTEON_IRQ_MSI_LAST     (OCTEON_IRQ_MSI_BIT0 + 255)
+#define OCTEON_IRQ_LAST                 (OCTEON_IRQ_MSI_LAST + 1)

 #endif
 
 #endif
 #endif
 
 #endif

diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
index dedef7d2b01f579f9081a536e7540c54c353e154..1e7dbb192657fb454c6ef91fe9db9e2fd0f4f7e9 100644 (file)
--- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -16,7 +16,7 @@
 #define CP0_PRID_OCTEON_PASS1 0x000d0000
 #define CP0_PRID_OCTEON_CN30XX 0x000d0200
 
 #define CP0_PRID_OCTEON_PASS1 0x000d0000
 #define CP0_PRID_OCTEON_CN30XX 0x000d0200
 

-.macro  kernel_entry_setup
+.macro kernel_entry_setup

        # Registers set by bootloader:
        # (only 32 bits set by bootloader, all addresses are physical
        # addresses, and need to have the appropriate memory region set
        # Registers set by bootloader:
        # (only 32 bits set by bootloader, all addresses are physical
        # addresses, and need to have the appropriate memory region set


@@ -28,12 +28,12 @@
        .set push
        .set arch=octeon
        # Read the cavium mem control register
        .set push
        .set arch=octeon
        # Read the cavium mem control register

-       dmfc0   v0, CP0_CVMMEMCTL_REG
+       dmfc0   v0, CP0_CVMMEMCTL_REG

        # Clear the lower 6 bits, the CVMSEG size
        # Clear the lower 6 bits, the CVMSEG size

-       dins    v0, $0, 0, 6
-       ori     v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
-       dmtc0   v0, CP0_CVMMEMCTL_REG   # Write the cavium mem control register
-       dmfc0   v0, CP0_CVMCTL_REG      # Read the cavium control register
+       dins    v0, $0, 0, 6
+       ori     v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
+       dmtc0   v0, CP0_CVMMEMCTL_REG   # Write the cavium mem control register
+       dmfc0   v0, CP0_CVMCTL_REG      # Read the cavium control register

 #ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED
        # Disable unaligned load/store support but leave HW fixup enabled
        or  v0, v0, 0x5001
 #ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED
        # Disable unaligned load/store support but leave HW fixup enabled
        or  v0, v0, 0x5001


@@ -69,14 +69,14 @@ skip:
        and     v0, v0, v1
        ori     v0, v0, (6 << 7)
        # Write the cavium control register
        and     v0, v0, v1
        ori     v0, v0, (6 << 7)
        # Write the cavium control register

-       dmtc0   v0, CP0_CVMCTL_REG
+       dmtc0   v0, CP0_CVMCTL_REG

        sync
        # Flush dcache after config change
        sync
        # Flush dcache after config change

-       cache   9, 0($0)
+       cache   9, 0($0)

        # Get my core id
        # Get my core id

-       rdhwr   v0, $0
+       rdhwr   v0, $0

        # Jump the master to kernel_entry
        # Jump the master to kernel_entry

-       bne     a2, zero, octeon_main_processor
+       bne     a2, zero, octeon_main_processor

        nop
 
 #ifdef CONFIG_SMP
        nop
 
 #ifdef CONFIG_SMP


@@ -87,21 +87,21 @@ skip:
        #
 
        # This is the variable where the next core to boot os stored
        #
 
        # This is the variable where the next core to boot os stored

-       PTR_LA  t0, octeon_processor_boot
+       PTR_LA  t0, octeon_processor_boot

 octeon_spin_wait_boot:
        # Get the core id of the next to be booted
 octeon_spin_wait_boot:
        # Get the core id of the next to be booted

-       LONG_L  t1, (t0)
+       LONG_L  t1, (t0)

        # Keep looping if it isn't me
        bne t1, v0, octeon_spin_wait_boot
        nop
        # Get my GP from the global variable
        # Keep looping if it isn't me
        bne t1, v0, octeon_spin_wait_boot
        nop
        # Get my GP from the global variable

-       PTR_LA  t0, octeon_processor_gp
-       LONG_L  gp, (t0)
+       PTR_LA  t0, octeon_processor_gp
+       LONG_L  gp, (t0)

        # Get my SP from the global variable
        # Get my SP from the global variable

-       PTR_LA  t0, octeon_processor_sp
-       LONG_L  sp, (t0)
+       PTR_LA  t0, octeon_processor_sp
+       LONG_L  sp, (t0)

        # Set the SP global variable to zero so the master knows we've started
        # Set the SP global variable to zero so the master knows we've started

-       LONG_S  zero, (t0)
+       LONG_S  zero, (t0)

 #ifdef __OCTEON__
        syncw
        syncw
 #ifdef __OCTEON__
        syncw
        syncw


@@ -130,7 +130,7 @@ octeon_main_processor:
 /*
  * Do SMP slave processor setup necessary before we can savely execute C code.
  */
 /*
  * Do SMP slave processor setup necessary before we can savely execute C code.
  */

-       .macro  smp_slave_setup
+       .macro  smp_slave_setup

        .endm
 
 #endif /* __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H */
        .endm
 
 #endif /* __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H */

diff --git a/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
index babc8374e3786d9aed1a7715cb7e8adc35c8e109..71d4bface1dc6ea9796e902d2beb52243a0c0eac 100644 (file)
--- a/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cobalt/cpu-feature-overrides.h
@@ -32,9 +32,9 @@
 #define cpu_scache_line_size() 0
 
 #ifdef CONFIG_64BIT
 #define cpu_scache_line_size() 0
 
 #ifdef CONFIG_64BIT

-#define cpu_has_llsc            0
+#define cpu_has_llsc           0

 #else
 #else

-#define cpu_has_llsc            1
+#define cpu_has_llsc           1

 #endif
 
 #define cpu_has_mips16         0
 #endif
 
 #define cpu_has_mips16         0

diff --git a/arch/mips/include/asm/mach-cobalt/mach-gt64120.h b/arch/mips/include/asm/mach-cobalt/mach-gt64120.h
index f8afec3f294330ea4322211f7b640f4146aabad8..6fe475b9e96555035d0651afd455816435d284e2 100644 (file)
--- a/arch/mips/include/asm/mach-cobalt/mach-gt64120.h
+++ b/arch/mips/include/asm/mach-cobalt/mach-gt64120.h
@@ -1,5 +1,5 @@
 /*
 /*

- *  Copyright (C) 2006  Yoichi Yuasa <yuasa@linux-mips.org>
+ *  Copyright (C) 2006 Yoichi Yuasa <yuasa@linux-mips.org>

  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by

diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h
index 16f1cf5982b92af76948e721bdf9ac08c0c4f81d..3c3ed4ae45e28ab66b166bf91fc6cb4d662020d0 100644 (file)
--- a/arch/mips/include/asm/mach-db1x00/bcsr.h
+++ b/arch/mips/include/asm/mach-db1x00/bcsr.h
@@ -110,7 +110,7 @@ enum bcsr_whoami_boards {
        BCSR_WHOAMI_DB1300,
 };
 
        BCSR_WHOAMI_DB1300,
 };
 

-/* STATUS reg.  Unless otherwise noted, they're valid on all boards.
+/* STATUS reg. Unless otherwise noted, they're valid on all boards.

  * PB1200 = DB1200.
  */
 #define BCSR_STATUS_PC0VS              0x0003
  * PB1200 = DB1200.
  */
 #define BCSR_STATUS_PC0VS              0x0003


@@ -190,7 +190,7 @@ enum bcsr_whoami_boards {
 #define BCSR_RESETS_OTPWRPROT          0x1000  /* DB1300 */
 #define BCSR_RESETS_OTPCSB             0x2000  /* DB1300 */
 #define BCSR_RESETS_OTGPWR             0x4000  /* DB1300 */
 #define BCSR_RESETS_OTPWRPROT          0x1000  /* DB1300 */
 #define BCSR_RESETS_OTPCSB             0x2000  /* DB1300 */
 #define BCSR_RESETS_OTGPWR             0x4000  /* DB1300 */

-#define BCSR_RESETS_USBHPWR            0x8000  /* DB1300 */
+#define BCSR_RESETS_USBHPWR            0x8000  /* DB1300 */

 
 #define BCSR_BOARD_LCDVEE              0x0001
 #define BCSR_BOARD_LCDVDD              0x0002
 
 #define BCSR_BOARD_LCDVEE              0x0001
 #define BCSR_BOARD_LCDVDD              0x0002

diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h
index b2a8319521e5ed253d4f18d6c513968dd8cd1b7d..d3cce7326dd4d07612d0d88a8f00934048b93796 100644 (file)
--- a/arch/mips/include/asm/mach-db1x00/db1200.h
+++ b/arch/mips/include/asm/mach-db1x00/db1200.h
@@ -63,7 +63,7 @@
  * the interrupt define and subtracting the DB1200_INT_BEGIN value.
  *
  *   Example: IDE bis pos is  = 64 - 64
  * the interrupt define and subtracting the DB1200_INT_BEGIN value.
  *
  *   Example: IDE bis pos is  = 64 - 64

- *            ETH bit pos is  = 65 - 64
+ *           ETH bit pos is  = 65 - 64

  */
 enum external_db1200_ints {
        DB1200_INT_BEGIN        = AU1000_MAX_INTR + 1,
  */
 enum external_db1200_ints {
        DB1200_INT_BEGIN        = AU1000_MAX_INTR + 1,

diff --git a/arch/mips/include/asm/mach-db1x00/db1300.h b/arch/mips/include/asm/mach-db1x00/db1300.h
index 7fe5fb3ba87707448fec932ad4da6bea26834b70..3d1ede46f059709c171f35e952687a99b789e34b 100644 (file)
--- a/arch/mips/include/asm/mach-db1x00/db1300.h
+++ b/arch/mips/include/asm/mach-db1x00/db1300.h
@@ -21,7 +21,7 @@
 #define DB1300_SD1_INSERT_INT  (DB1300_FIRST_INT + 12)
 #define DB1300_SD1_EJECT_INT   (DB1300_FIRST_INT + 13)
 #define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14)
 #define DB1300_SD1_INSERT_INT  (DB1300_FIRST_INT + 12)
 #define DB1300_SD1_EJECT_INT   (DB1300_FIRST_INT + 13)
 #define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14)

-#define DB1300_HOST_VBUS_OC_INT        (DB1300_FIRST_INT + 15)
+#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15)

 #define DB1300_LAST_INT                (DB1300_FIRST_INT + 15)
 
 /* SMSC9210 CS */
 #define DB1300_LAST_INT                (DB1300_FIRST_INT + 15)
 
 /* SMSC9210 CS */

diff --git a/arch/mips/include/asm/mach-emma2rh/irq.h b/arch/mips/include/asm/mach-emma2rh/irq.h
index 5439eb85646101b36c80c2727eb0a17d9f822be9..2f7155dade292f918f6097cb4482ea7ca3cdad09 100644 (file)
--- a/arch/mips/include/asm/mach-emma2rh/irq.h
+++ b/arch/mips/include/asm/mach-emma2rh/irq.h
@@ -8,7 +8,7 @@
 #ifndef __ASM_MACH_EMMA2RH_IRQ_H
 #define __ASM_MACH_EMMA2RH_IRQ_H
 
 #ifndef __ASM_MACH_EMMA2RH_IRQ_H
 #define __ASM_MACH_EMMA2RH_IRQ_H
 

-#define NR_IRQS        256
+#define NR_IRQS 256

 
 #include_next <irq.h>
 
 
 #include_next <irq.h>
 

diff --git a/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h b/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h
index 7c185bb06f13085c3e136b8a70097089a511659b..42be9e9ced2c0f5da458eead132f0c8aa70cc400 100644 (file)
--- a/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-generic/cpu-feature-overrides.h
@@ -8,6 +8,6 @@
 #ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
 #define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
 
 #ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
 #define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
 

-/* Intentionally empty file ...  */
+/* Intentionally empty file ...         */

 
 #endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */
 
 #endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */

diff --git a/arch/mips/include/asm/mach-generic/floppy.h b/arch/mips/include/asm/mach-generic/floppy.h
index a38f4d43e5e575e8ad47145ae5c5b3729f284488..5b5cd689a2f7a0ef466bff9bcef694698525e529 100644 (file)
--- a/arch/mips/include/asm/mach-generic/floppy.h
+++ b/arch/mips/include/asm/mach-generic/floppy.h
@@ -98,7 +98,7 @@ static inline void fd_disable_irq(void)
 static inline int fd_request_irq(void)
 {
        return request_irq(FLOPPY_IRQ, floppy_interrupt,
 static inline int fd_request_irq(void)
 {
        return request_irq(FLOPPY_IRQ, floppy_interrupt,

-                          0, "floppy", NULL);
+                          0, "floppy", NULL);

 }
 
 static inline void fd_free_irq(void)
 }
 
 static inline void fd_free_irq(void)


@@ -106,7 +106,7 @@ static inline void fd_free_irq(void)
        free_irq(FLOPPY_IRQ, NULL);
 }
 
        free_irq(FLOPPY_IRQ, NULL);
 }
 

-#define fd_free_irq()           free_irq(FLOPPY_IRQ, NULL);
+#define fd_free_irq()          free_irq(FLOPPY_IRQ, NULL);

 
 
 static inline unsigned long fd_getfdaddr1(void)
 
 
 static inline unsigned long fd_getfdaddr1(void)

diff --git a/arch/mips/include/asm/mach-generic/ide.h b/arch/mips/include/asm/mach-generic/ide.h
index 9c93a5b36f2a2dfd14a84fcfea813fb8ed3634e8..affa66f5c2dab0c1b616248c4100e1ed02587350 100644 (file)
--- a/arch/mips/include/asm/mach-generic/ide.h
+++ b/arch/mips/include/asm/mach-generic/ide.h
@@ -51,7 +51,7 @@ static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long si
 /*
  * insw() and gang might be called with interrupts disabled, so we can't
  * send IPIs for flushing due to the potencial of deadlocks, see the comment
 /*
  * insw() and gang might be called with interrupts disabled, so we can't
  * send IPIs for flushing due to the potencial of deadlocks, see the comment

- * above smp_call_function() in arch/mips/kernel/smp.c.  We work around the
+ * above smp_call_function() in arch/mips/kernel/smp.c.         We work around the

  * problem by disabling preemption so we know we actually perform the flush
  * on the processor that actually has the lines to be flushed which hopefully
  * is even better for performance anyway.
  * problem by disabling preemption so we know we actually perform the flush
  * on the processor that actually has the lines to be flushed which hopefully
  * is even better for performance anyway.


@@ -123,7 +123,7 @@ static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count)
        __ide_flush_epilogue();
 }
 
        __ide_flush_epilogue();
 }
 

-/* ide_insw calls insw, not __ide_insw.  Why? */
+/* ide_insw calls insw, not __ide_insw.         Why? */

 #undef insw
 #undef insl
 #undef outsw
 #undef insw
 #undef insl
 #undef outsw

diff --git a/arch/mips/include/asm/mach-generic/irq.h b/arch/mips/include/asm/mach-generic/irq.h
index e014264b2be2da8397116475b449024123924030..139cd200e79d291449198df6b8f65d128aaa12fc 100644 (file)
--- a/arch/mips/include/asm/mach-generic/irq.h
+++ b/arch/mips/include/asm/mach-generic/irq.h
@@ -9,12 +9,12 @@
 #define __ASM_MACH_GENERIC_IRQ_H
 
 #ifndef NR_IRQS
 #define __ASM_MACH_GENERIC_IRQ_H
 
 #ifndef NR_IRQS

-#define NR_IRQS        128
+#define NR_IRQS 128

 #endif
 
 #ifdef CONFIG_I8259
 #ifndef I8259A_IRQ_BASE
 #endif
 
 #ifdef CONFIG_I8259
 #ifndef I8259A_IRQ_BASE

-#define I8259A_IRQ_BASE        0
+#define I8259A_IRQ_BASE 0

 #endif
 #endif
 
 #endif
 #endif
 

diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h
index d7a9efd3a5ce217973ecebb0e2ce4c09be083efa..73d717a75cb0a1038e2f10009d67e657e23ab429 100644 (file)
--- a/arch/mips/include/asm/mach-generic/spaces.h
+++ b/arch/mips/include/asm/mach-generic/spaces.h
@@ -69,7 +69,7 @@
 #define HIGHMEM_START          (_AC(1, UL) << _AC(59, UL))
 #endif
 
 #define HIGHMEM_START          (_AC(1, UL) << _AC(59, UL))
 #endif
 

-#define TO_PHYS(x)             (             ((x) & TO_PHYS_MASK))
+#define TO_PHYS(x)             (             ((x) & TO_PHYS_MASK))

 #define TO_CAC(x)              (CAC_BASE   | ((x) & TO_PHYS_MASK))
 #define TO_UNCAC(x)            (UNCAC_BASE | ((x) & TO_PHYS_MASK))
 
 #define TO_CAC(x)              (CAC_BASE   | ((x) & TO_PHYS_MASK))
 #define TO_UNCAC(x)            (UNCAC_BASE | ((x) & TO_PHYS_MASK))
 

diff --git a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
index 624d66c7f290268d08916f056d43451c124aeefc..a323efb720dc01018792f76ab88f0ff093043658 100644 (file)
--- a/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-ip27/kernel-entry-init.h
@@ -51,8 +51,8 @@
         * We might not get launched at the address the kernel is linked to,
         * so we jump there.
         */
         * We might not get launched at the address the kernel is linked to,
         * so we jump there.
         */

-       PTR_LA  t0, 0f
-       jr      t0
+       PTR_LA  t0, 0f
+       jr      t0

 0:
        .endm
 
 0:
        .endm
 

diff --git a/arch/mips/include/asm/mach-ip27/mmzone.h b/arch/mips/include/asm/mach-ip27/mmzone.h
index 986a3b9b59a7c0cefd0a7dbcb3a078bc7c456e9b..ebc9377ff87661006d1140e00d8ec8ee8ce2db61 100644 (file)
--- a/arch/mips/include/asm/mach-ip27/mmzone.h
+++ b/arch/mips/include/asm/mach-ip27/mmzone.h
@@ -7,7 +7,7 @@
 
 #define pa_to_nid(addr)                NASID_TO_COMPACT_NODEID(NASID_GET(addr))
 
 
 #define pa_to_nid(addr)                NASID_TO_COMPACT_NODEID(NASID_GET(addr))
 

-#define LEVELS_PER_SLICE        128
+#define LEVELS_PER_SLICE       128

 
 struct slice_data {
        unsigned long irq_enable_mask[2];
 
 struct slice_data {
        unsigned long irq_enable_mask[2];

diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h
index b2cf641f206f0bad0b3dbf0c80d481984160737c..defd135e7ac8d726f320962cc97cb403aba56d63 100644 (file)
--- a/arch/mips/include/asm/mach-ip27/topology.h
+++ b/arch/mips/include/asm/mach-ip27/topology.h
@@ -34,7 +34,7 @@ extern int pcibus_to_node(struct pci_bus *);
 
 extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
 
 
 extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
 

-#define node_distance(from, to)        (__node_distances[(from)][(to)])
+#define node_distance(from, to) (__node_distances[(from)][(to)])

 
 #include <asm-generic/topology.h>
 
 
 #include <asm-generic/topology.h>
 

diff --git a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
index 50d344ca60a84ff460f2a1ca902a778884c2761c..65e9c856390d9d43fcf24f7d7c301c4dea665a74 100644 (file)
--- a/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
@@ -28,7 +28,7 @@
 #define cpu_has_ic_fills_f_dc  0
 #define cpu_has_dsp            0
 #define cpu_has_dsp2           0
 #define cpu_has_ic_fills_f_dc  0
 #define cpu_has_dsp            0
 #define cpu_has_dsp2           0

-#define cpu_icache_snoops_remote_store  1
+#define cpu_icache_snoops_remote_store 1

 #define cpu_has_mipsmt         0
 #define cpu_has_userlocal      0
 
 #define cpu_has_mipsmt         0
 #define cpu_has_userlocal      0
 

diff --git a/arch/mips/include/asm/mach-ip28/spaces.h b/arch/mips/include/asm/mach-ip28/spaces.h
index 05aabb27e5e7bf3e0ca735e8f9dcafaf9899fa1f..5edf05d9dad8b648f100905c1b9b08dcdb6ca817 100644 (file)
--- a/arch/mips/include/asm/mach-ip28/spaces.h
+++ b/arch/mips/include/asm/mach-ip28/spaces.h
@@ -6,7 +6,7 @@
  * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
  * Copyright (C) 2000, 2002  Maciej W. Rozycki
  * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
  * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
  * Copyright (C) 2000, 2002  Maciej W. Rozycki
  * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.

- * 2004        pf
+ * 2004 pf

  */
 #ifndef _ASM_MACH_IP28_SPACES_H
 #define _ASM_MACH_IP28_SPACES_H
  */
 #ifndef _ASM_MACH_IP28_SPACES_H
 #define _ASM_MACH_IP28_SPACES_H

diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h
index c8fb5aacf50a412eb89e0397f5a55b73655ce8d3..073f0c4760ba8cc3cc7cf59380dfbc58c6a409bd 100644 (file)
--- a/arch/mips/include/asm/mach-ip32/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h
@@ -50,7 +50,7 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
        return pa;
 }
 
        return pa;
 }
 

-/* This is almost certainly wrong but it's what dma-ip32.c used to use  */
+/* This is almost certainly wrong but it's what dma-ip32.c used to use */

 static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
        dma_addr_t dma_addr)
 {
 static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
        dma_addr_t dma_addr)
 {

diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index 7237a935a133c9163585ffa983e9755b9d38a19b..9807ecda5a88a96ec34eb5e1023fc89dc52a51c4 100644 (file)
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -17,7 +17,7 @@
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0
 #define MIPS4K_ICACHE_REFILL_WAR       0
 #define MIPS_CACHE_SYNC_WAR            0
 #define TX49XX_ICACHE_INDEX_INV_WAR    0

-#define ICACHE_REFILLS_WORKAROUND_WAR   1
+#define ICACHE_REFILLS_WORKAROUND_WAR  1

 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
 
 #define R10000_LLSC_WAR                        0
 #define MIPS34K_MISSED_ITLB_WAR                0
 

diff --git a/arch/mips/include/asm/mach-jazz/floppy.h b/arch/mips/include/asm/mach-jazz/floppy.h
index 88b5acb751456ce520501b387088cbf4b1150be7..62aa1e287fba1782010e4aed0b31d704e6691990 100644 (file)
--- a/arch/mips/include/asm/mach-jazz/floppy.h
+++ b/arch/mips/include/asm/mach-jazz/floppy.h
@@ -90,7 +90,7 @@ static inline void fd_disable_irq(void)
 static inline int fd_request_irq(void)
 {
        return request_irq(FLOPPY_IRQ, floppy_interrupt,
 static inline int fd_request_irq(void)
 {
        return request_irq(FLOPPY_IRQ, floppy_interrupt,

-                          0, "floppy", NULL);
+                          0, "floppy", NULL);

 }
 
 static inline void fd_free_irq(void)
 }
 
 static inline void fd_free_irq(void)

diff --git a/arch/mips/include/asm/mach-jz4740/clock.h b/arch/mips/include/asm/mach-jz4740/clock.h
index 1b7408dd0e23b89113d96635b133d29d539e0816..16659cd76d4e7caa863e7ebeadd19ccb6b06392c 100644 (file)
--- a/arch/mips/include/asm/mach-jz4740/clock.h
+++ b/arch/mips/include/asm/mach-jz4740/clock.h
@@ -2,7 +2,7 @@
  *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
  *
  *  This program is free software; you can redistribute it and/or modify it

- *  under  the terms of the GNU General  Public License as published by the
+ *  under  the terms of the GNU General         Public License as published by the

  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *
  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *

diff --git a/arch/mips/include/asm/mach-jz4740/dma.h b/arch/mips/include/asm/mach-jz4740/dma.h
index a3be12183599c0253614d12b9ccd1565d5781f63..98b4e7c0dbae7ae0ee99856f6afcc19333679a71 100644 (file)
--- a/arch/mips/include/asm/mach-jz4740/dma.h
+++ b/arch/mips/include/asm/mach-jz4740/dma.h
@@ -3,7 +3,7 @@
  *  JZ7420/JZ4740 DMA definitions
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  JZ7420/JZ4740 DMA definitions
  *
  *  This program is free software; you can redistribute it and/or modify it

- *  under  the terms of the GNU General  Public License as published by the
+ *  under  the terms of the GNU General         Public License as published by the

  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *
  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *


@@ -40,9 +40,9 @@ enum jz4740_dma_width {
 };
 
 enum jz4740_dma_transfer_size {
 };
 
 enum jz4740_dma_transfer_size {

-       JZ4740_DMA_TRANSFER_SIZE_4BYTE  = 0,
-       JZ4740_DMA_TRANSFER_SIZE_1BYTE  = 1,
-       JZ4740_DMA_TRANSFER_SIZE_2BYTE  = 2,
+       JZ4740_DMA_TRANSFER_SIZE_4BYTE  = 0,
+       JZ4740_DMA_TRANSFER_SIZE_1BYTE  = 1,
+       JZ4740_DMA_TRANSFER_SIZE_2BYTE  = 2,

        JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
        JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
 };
        JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
        JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
 };


@@ -87,4 +87,4 @@ uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma);
 void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
        jz4740_dma_complete_callback_t cb);
 
 void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
        jz4740_dma_complete_callback_t cb);
 

-#endif  /* __ASM_JZ4740_DMA_H__ */
+#endif /* __ASM_JZ4740_DMA_H__ */

diff --git a/arch/mips/include/asm/mach-jz4740/gpio.h b/arch/mips/include/asm/mach-jz4740/gpio.h
index 1a6482ea0bb37d6413a51cbeb880f96563da96fc..eaacba79cf18c9905731f7e0760d6697de795b23 100644 (file)
--- a/arch/mips/include/asm/mach-jz4740/gpio.h
+++ b/arch/mips/include/asm/mach-jz4740/gpio.h
@@ -198,7 +198,7 @@ uint32_t jz_gpio_port_get_value(int port, uint32_t mask);
 #define JZ_GPIO_FUNC_MEM_ADDR14                JZ_GPIO_FUNC1
 #define JZ_GPIO_FUNC_MEM_ADDR15                JZ_GPIO_FUNC1
 #define JZ_GPIO_FUNC_MEM_ADDR16                JZ_GPIO_FUNC1
 #define JZ_GPIO_FUNC_MEM_ADDR14                JZ_GPIO_FUNC1
 #define JZ_GPIO_FUNC_MEM_ADDR15                JZ_GPIO_FUNC1
 #define JZ_GPIO_FUNC_MEM_ADDR16                JZ_GPIO_FUNC1

-#define JZ_GPIO_FUNC_LCD_CLS           JZ_GPIO_FUNC1
+#define JZ_GPIO_FUNC_LCD_CLS           JZ_GPIO_FUNC1

 #define JZ_GPIO_FUNC_LCD_SPL           JZ_GPIO_FUNC1
 #define JZ_GPIO_FUNC_MEM_DCS           JZ_GPIO_FUNC1
 #define JZ_GPIO_FUNC_MEM_RAS           JZ_GPIO_FUNC1
 #define JZ_GPIO_FUNC_LCD_SPL           JZ_GPIO_FUNC1
 #define JZ_GPIO_FUNC_MEM_DCS           JZ_GPIO_FUNC1
 #define JZ_GPIO_FUNC_MEM_RAS           JZ_GPIO_FUNC1

diff --git a/arch/mips/include/asm/mach-jz4740/irq.h b/arch/mips/include/asm/mach-jz4740/irq.h
index 5ad1a9c113c624136c6f2bfd584906c72f62d7a5..df50736749c16d2860bd5e4d48b2b6f655b86eb8 100644 (file)
--- a/arch/mips/include/asm/mach-jz4740/irq.h
+++ b/arch/mips/include/asm/mach-jz4740/irq.h
@@ -3,7 +3,7 @@
  *  JZ4740 IRQ definitions
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  JZ4740 IRQ definitions
  *
  *  This program is free software; you can redistribute it and/or modify it

- *  under  the terms of the GNU General  Public License as published by the
+ *  under  the terms of the GNU General         Public License as published by the

  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *
  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *

diff --git a/arch/mips/include/asm/mach-jz4740/platform.h b/arch/mips/include/asm/mach-jz4740/platform.h
index 163e81db880dc5d6b46a07eca5be4e179d21b266..72cfebdb5a47dbfd91b01f00acca65cfc7cdfc12 100644 (file)
--- a/arch/mips/include/asm/mach-jz4740/platform.h
+++ b/arch/mips/include/asm/mach-jz4740/platform.h
@@ -3,7 +3,7 @@
  *  JZ4740 platform device definitions
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  JZ4740 platform device definitions
  *
  *  This program is free software; you can redistribute it and/or modify it

- *  under  the terms of the GNU General  Public License as published by the
+ *  under  the terms of the GNU General         Public License as published by the

  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *
  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *

diff --git a/arch/mips/include/asm/mach-jz4740/timer.h b/arch/mips/include/asm/mach-jz4740/timer.h
index a7759fb1f73d576bcd6388588096aea764620143..8750a1d04e2272583e5c6c5bbcded25498b57458 100644 (file)
--- a/arch/mips/include/asm/mach-jz4740/timer.h
+++ b/arch/mips/include/asm/mach-jz4740/timer.h
@@ -3,7 +3,7 @@
  *  JZ4740 platform timer support
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  JZ4740 platform timer support
  *
  *  This program is free software; you can redistribute it and/or modify it

- *  under  the terms of the GNU General  Public License as published by the
+ *  under  the terms of the GNU General         Public License as published by the

  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *
  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *

diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
index fccac3592651c306bb2b59bfcf1139bfd509dceb..98d6a2f14aafcfa4f89f0db644f2351f8b8ad453 100644 (file)
--- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
@@ -44,7 +44,7 @@
 
 /* BOOT_SEL - find what boot media we have */
 #define BS_FLASH               0x1
 
 /* BOOT_SEL - find what boot media we have */
 #define BS_FLASH               0x1

-#define BS_SPI                  0x4
+#define BS_SPI                 0x4

 
 /* global register ranges */
 extern __iomem void *ltq_ebu_membase;
 
 /* global register ranges */
 extern __iomem void *ltq_ebu_membase;

diff --git a/arch/mips/include/asm/mach-lantiq/war.h b/arch/mips/include/asm/mach-lantiq/war.h
index b6c568c280ef038dec56801a6a56bc3304a18187..358ca979c1bd6aed338acc76f3140ba1a8df6b27 100644 (file)
--- a/arch/mips/include/asm/mach-lantiq/war.h
+++ b/arch/mips/include/asm/mach-lantiq/war.h
@@ -7,17 +7,17 @@
 #ifndef __ASM_MIPS_MACH_LANTIQ_WAR_H
 #define __ASM_MIPS_MACH_LANTIQ_WAR_H
 
 #ifndef __ASM_MIPS_MACH_LANTIQ_WAR_H
 #define __ASM_MIPS_MACH_LANTIQ_WAR_H
 

-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
+#define R4600_V1_INDEX_ICACHEOP_WAR    0
+#define R4600_V1_HIT_CACHEOP_WAR       0
+#define R4600_V2_HIT_CACHEOP_WAR       0
+#define R5432_CP0_INTERRUPT_WAR                0
+#define BCM1250_M3_WAR                 0
+#define SIBYTE_1956_WAR                        0
+#define MIPS4K_ICACHE_REFILL_WAR       0
+#define MIPS_CACHE_SYNC_WAR            0
+#define TX49XX_ICACHE_INDEX_INV_WAR    0
+#define ICACHE_REFILLS_WORKAROUND_WAR  0
+#define R10000_LLSC_WAR                        0
+#define MIPS34K_MISSED_ITLB_WAR                0

 
 #endif
 
 #endif

diff --git a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
index 872943a4b90ef2845c1d28dcc524972a8bd7ee7f..5f8693d5ab126a843429a69eb0ba2eed4742d6af 100644 (file)
--- a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
+++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h
@@ -21,7 +21,7 @@
 #define LTQ_DESC_SIZE          0x08    /* each descriptor is 64bit */
 #define LTQ_DESC_NUM           0x40    /* 64 descriptors / channel */
 
 #define LTQ_DESC_SIZE          0x08    /* each descriptor is 64bit */
 #define LTQ_DESC_NUM           0x40    /* 64 descriptors / channel */
 

-#define LTQ_DMA_OWN            BIT(31) /* owner bit */
+#define LTQ_DMA_OWN            BIT(31) /* owner bit */

 #define LTQ_DMA_C              BIT(30) /* complete bit */
 #define LTQ_DMA_SOP            BIT(29) /* start of packet */
 #define LTQ_DMA_EOP            BIT(28) /* end of packet */
 #define LTQ_DMA_C              BIT(30) /* complete bit */
 #define LTQ_DMA_SOP            BIT(29) /* start of packet */
 #define LTQ_DMA_EOP            BIT(28) /* end of packet */


@@ -38,7 +38,7 @@ struct ltq_dma_channel {
        int nr;                         /* the channel number */
        int irq;                        /* the mapped irq */
        int desc;                       /* the current descriptor */
        int nr;                         /* the channel number */
        int irq;                        /* the mapped irq */
        int desc;                       /* the current descriptor */

-       struct ltq_dma_desc *desc_base; /* the descriptor base */
+       struct ltq_dma_desc *desc_base; /* the descriptor base */

        int phys;                       /* physical addr */
 };
 
        int phys;                       /* physical addr */
 };
 

diff --git a/arch/mips/include/asm/mach-lasat/mach-gt64120.h b/arch/mips/include/asm/mach-lasat/mach-gt64120.h
index 1a9ad45cc13531e6d2d034d7ff04bcdc407dcb26..c253d3fa5167bdb3ec456ee3621cb028af230796 100644 (file)
--- a/arch/mips/include/asm/mach-lasat/mach-gt64120.h
+++ b/arch/mips/include/asm/mach-lasat/mach-gt64120.h
@@ -1,6 +1,6 @@
 /*
  *  This is a direct copy of the ev96100.h file, with a global
 /*
  *  This is a direct copy of the ev96100.h file, with a global

- * search and replace.  The numbers are the same.
+ * search and replace. The numbers are the same.

  *
  *  The reason I'm duplicating this is so that the 64120/96100
  * defines won't be confusing in the source code.
  *
  *  The reason I'm duplicating this is so that the 64120/96100
  * defines won't be confusing in the source code.


@@ -18,8 +18,8 @@
  *
  *   (Guessing ...)
  */
  *
  *   (Guessing ...)
  */

-#define GT_PCI_MEM_BASE        0x12000000UL
-#define GT_PCI_MEM_SIZE        0x02000000UL
+#define GT_PCI_MEM_BASE 0x12000000UL
+#define GT_PCI_MEM_SIZE 0x02000000UL

 #define GT_PCI_IO_BASE 0x10000000UL
 #define GT_PCI_IO_SIZE 0x02000000UL
 #define GT_ISA_IO_BASE PCI_IO_BASE
 #define GT_PCI_IO_BASE 0x10000000UL
 #define GT_PCI_IO_SIZE 0x02000000UL
 #define GT_ISA_IO_BASE PCI_IO_BASE

diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
index 1a05d854e34c05abfa2ab52c0e4206ce912a7533..75fd8c0f986eaff51a02ce2807a5c92442e657be 100644 (file)
--- a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h
@@ -8,9 +8,9 @@
  * Copyright (C) 2009 Zhang Le <r0bertz@gentoo.org>
  *
  * reference: /proc/cpuinfo,
  * Copyright (C) 2009 Zhang Le <r0bertz@gentoo.org>
  *
  * reference: /proc/cpuinfo,

- *     arch/mips/kernel/cpu-probe.c(cpu_probe_legacy),
- *     arch/mips/kernel/proc.c(show_cpuinfo),
- *      loongson2f user manual.
+ *     arch/mips/kernel/cpu-probe.c(cpu_probe_legacy),
+ *     arch/mips/kernel/proc.c(show_cpuinfo),
+ *     loongson2f user manual.

  */
 
 #ifndef __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H
  */
 
 #ifndef __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H


@@ -37,7 +37,7 @@
 #define cpu_has_fpu            1
 #define cpu_has_ic_fills_f_dc  0
 #define cpu_has_inclusive_pcaches      1
 #define cpu_has_fpu            1
 #define cpu_has_ic_fills_f_dc  0
 #define cpu_has_inclusive_pcaches      1

-#define cpu_has_llsc           1
+#define cpu_has_llsc           1

 #define cpu_has_mcheck         0
 #define cpu_has_mdmx           0
 #define cpu_has_mips16         0
 #define cpu_has_mcheck         0
 #define cpu_has_mdmx           0
 #define cpu_has_mips16         0

diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
index 2a8e2bb5d53989a4311547fafb25fd2cac35bba9..a0ee0cb775ad1dc64b8608fdeb9dccf93a57cf5c 100644 (file)
--- a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h
@@ -5,8 +5,8 @@
  * Author : jlliu <liujl@lemote.com>
  */
 
  * Author : jlliu <liujl@lemote.com>
  */
 

-#ifndef        _CS5536_H
-#define        _CS5536_H
+#ifndef _CS5536_H
+#define _CS5536_H

 
 #include <linux/types.h>
 
 
 #include <linux/types.h>
 


@@ -16,237 +16,237 @@ extern void _wrmsr(u32 msr, u32 hi, u32 lo);
 /*
  * MSR module base
  */
 /*
  * MSR module base
  */

-#define        CS5536_SB_MSR_BASE      (0x00000000)
-#define        CS5536_GLIU_MSR_BASE    (0x10000000)
-#define        CS5536_ILLEGAL_MSR_BASE (0x20000000)
-#define        CS5536_USB_MSR_BASE     (0x40000000)
-#define        CS5536_IDE_MSR_BASE     (0x60000000)
-#define        CS5536_DIVIL_MSR_BASE   (0x80000000)
-#define        CS5536_ACC_MSR_BASE     (0xa0000000)
-#define        CS5536_UNUSED_MSR_BASE  (0xc0000000)
-#define        CS5536_GLCP_MSR_BASE    (0xe0000000)
+#define CS5536_SB_MSR_BASE     (0x00000000)
+#define CS5536_GLIU_MSR_BASE   (0x10000000)
+#define CS5536_ILLEGAL_MSR_BASE (0x20000000)
+#define CS5536_USB_MSR_BASE    (0x40000000)
+#define CS5536_IDE_MSR_BASE    (0x60000000)
+#define CS5536_DIVIL_MSR_BASE  (0x80000000)
+#define CS5536_ACC_MSR_BASE    (0xa0000000)
+#define CS5536_UNUSED_MSR_BASE (0xc0000000)
+#define CS5536_GLCP_MSR_BASE   (0xe0000000)

 
 

-#define        SB_MSR_REG(offset)      (CS5536_SB_MSR_BASE     | (offset))
-#define        GLIU_MSR_REG(offset)    (CS5536_GLIU_MSR_BASE   | (offset))
-#define        ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset))
-#define        USB_MSR_REG(offset)     (CS5536_USB_MSR_BASE    | (offset))
-#define        IDE_MSR_REG(offset)     (CS5536_IDE_MSR_BASE    | (offset))
-#define        DIVIL_MSR_REG(offset)   (CS5536_DIVIL_MSR_BASE  | (offset))
-#define        ACC_MSR_REG(offset)     (CS5536_ACC_MSR_BASE    | (offset))
-#define        UNUSED_MSR_REG(offset)  (CS5536_UNUSED_MSR_BASE | (offset))
-#define        GLCP_MSR_REG(offset)    (CS5536_GLCP_MSR_BASE   | (offset))
+#define SB_MSR_REG(offset)     (CS5536_SB_MSR_BASE     | (offset))
+#define GLIU_MSR_REG(offset)   (CS5536_GLIU_MSR_BASE   | (offset))
+#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset))
+#define USB_MSR_REG(offset)    (CS5536_USB_MSR_BASE    | (offset))
+#define IDE_MSR_REG(offset)    (CS5536_IDE_MSR_BASE    | (offset))
+#define DIVIL_MSR_REG(offset)  (CS5536_DIVIL_MSR_BASE  | (offset))
+#define ACC_MSR_REG(offset)    (CS5536_ACC_MSR_BASE    | (offset))
+#define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | (offset))
+#define GLCP_MSR_REG(offset)   (CS5536_GLCP_MSR_BASE   | (offset))

 
 /*
  * BAR SPACE OF VIRTUAL PCI :
  * range for pci probe use, length is the actual size.
  */
 /* IO space for all DIVIL modules */
 
 /*
  * BAR SPACE OF VIRTUAL PCI :
  * range for pci probe use, length is the actual size.
  */
 /* IO space for all DIVIL modules */

-#define        CS5536_IRQ_RANGE        0xffffffe0 /* USERD FOR PCI PROBE */
-#define        CS5536_IRQ_LENGTH       0x20    /* THE REGS ACTUAL LENGTH */
-#define        CS5536_SMB_RANGE        0xfffffff8
-#define        CS5536_SMB_LENGTH       0x08
-#define        CS5536_GPIO_RANGE       0xffffff00
-#define        CS5536_GPIO_LENGTH      0x100
-#define        CS5536_MFGPT_RANGE      0xffffffc0
-#define        CS5536_MFGPT_LENGTH     0x40
-#define        CS5536_ACPI_RANGE       0xffffffe0
-#define        CS5536_ACPI_LENGTH      0x20
-#define        CS5536_PMS_RANGE        0xffffff80
-#define        CS5536_PMS_LENGTH       0x80
+#define CS5536_IRQ_RANGE       0xffffffe0 /* USERD FOR PCI PROBE */
+#define CS5536_IRQ_LENGTH      0x20    /* THE REGS ACTUAL LENGTH */
+#define CS5536_SMB_RANGE       0xfffffff8
+#define CS5536_SMB_LENGTH      0x08
+#define CS5536_GPIO_RANGE      0xffffff00
+#define CS5536_GPIO_LENGTH     0x100
+#define CS5536_MFGPT_RANGE     0xffffffc0
+#define CS5536_MFGPT_LENGTH    0x40
+#define CS5536_ACPI_RANGE      0xffffffe0
+#define CS5536_ACPI_LENGTH     0x20
+#define CS5536_PMS_RANGE       0xffffff80
+#define CS5536_PMS_LENGTH      0x80

 /* IO space for IDE */
 /* IO space for IDE */

-#define        CS5536_IDE_RANGE        0xfffffff0
-#define        CS5536_IDE_LENGTH       0x10
+#define CS5536_IDE_RANGE       0xfffffff0
+#define CS5536_IDE_LENGTH      0x10

 /* IO space for ACC */
 /* IO space for ACC */

-#define        CS5536_ACC_RANGE        0xffffff80
-#define        CS5536_ACC_LENGTH       0x80
+#define CS5536_ACC_RANGE       0xffffff80
+#define CS5536_ACC_LENGTH      0x80

 /* MEM space for ALL USB modules */
 /* MEM space for ALL USB modules */

-#define        CS5536_OHCI_RANGE       0xfffff000
-#define        CS5536_OHCI_LENGTH      0x1000
-#define        CS5536_EHCI_RANGE       0xfffff000
-#define        CS5536_EHCI_LENGTH      0x1000
+#define CS5536_OHCI_RANGE      0xfffff000
+#define CS5536_OHCI_LENGTH     0x1000
+#define CS5536_EHCI_RANGE      0xfffff000
+#define CS5536_EHCI_LENGTH     0x1000

 
 /*
  * PCI MSR ACCESS
  */
 
 /*
  * PCI MSR ACCESS
  */

-#define        PCI_MSR_CTRL            0xF0
-#define        PCI_MSR_ADDR            0xF4
-#define        PCI_MSR_DATA_LO         0xF8
-#define        PCI_MSR_DATA_HI         0xFC
+#define PCI_MSR_CTRL           0xF0
+#define PCI_MSR_ADDR           0xF4
+#define PCI_MSR_DATA_LO                0xF8
+#define PCI_MSR_DATA_HI                0xFC

 
 /**************** MSR *****************************/
 
 /*
  * GLIU STANDARD MSR
  */
 
 /**************** MSR *****************************/
 
 /*
  * GLIU STANDARD MSR
  */

-#define        GLIU_CAP                0x00
-#define        GLIU_CONFIG             0x01
-#define        GLIU_SMI                0x02
-#define        GLIU_ERROR              0x03
-#define        GLIU_PM                 0x04
-#define        GLIU_DIAG               0x05
+#define GLIU_CAP               0x00
+#define GLIU_CONFIG            0x01
+#define GLIU_SMI               0x02
+#define GLIU_ERROR             0x03
+#define GLIU_PM                        0x04
+#define GLIU_DIAG              0x05

 
 /*
  * GLIU SPEC. MSR
  */
 
 /*
  * GLIU SPEC. MSR
  */

-#define        GLIU_P2D_BM0            0x20
-#define        GLIU_P2D_BM1            0x21
-#define        GLIU_P2D_BM2            0x22
-#define        GLIU_P2D_BMK0           0x23
-#define        GLIU_P2D_BMK1           0x24
-#define        GLIU_P2D_BM3            0x25
-#define        GLIU_P2D_BM4            0x26
-#define        GLIU_COH                0x80
-#define        GLIU_PAE                0x81
-#define        GLIU_ARB                0x82
-#define        GLIU_ASMI               0x83
-#define        GLIU_AERR               0x84
-#define        GLIU_DEBUG              0x85
-#define        GLIU_PHY_CAP            0x86
-#define        GLIU_NOUT_RESP          0x87
-#define        GLIU_NOUT_WDATA         0x88
-#define        GLIU_WHOAMI             0x8B
-#define        GLIU_SLV_DIS            0x8C
-#define        GLIU_IOD_BM0            0xE0
-#define        GLIU_IOD_BM1            0xE1
-#define        GLIU_IOD_BM2            0xE2
-#define        GLIU_IOD_BM3            0xE3
-#define        GLIU_IOD_BM4            0xE4
-#define        GLIU_IOD_BM5            0xE5
-#define        GLIU_IOD_BM6            0xE6
-#define        GLIU_IOD_BM7            0xE7
-#define        GLIU_IOD_BM8            0xE8
-#define        GLIU_IOD_BM9            0xE9
-#define        GLIU_IOD_SC0            0xEA
-#define        GLIU_IOD_SC1            0xEB
-#define        GLIU_IOD_SC2            0xEC
-#define        GLIU_IOD_SC3            0xED
-#define        GLIU_IOD_SC4            0xEE
-#define        GLIU_IOD_SC5            0xEF
-#define        GLIU_IOD_SC6            0xF0
-#define        GLIU_IOD_SC7            0xF1
+#define GLIU_P2D_BM0           0x20
+#define GLIU_P2D_BM1           0x21
+#define GLIU_P2D_BM2           0x22
+#define GLIU_P2D_BMK0          0x23
+#define GLIU_P2D_BMK1          0x24
+#define GLIU_P2D_BM3           0x25
+#define GLIU_P2D_BM4           0x26
+#define GLIU_COH               0x80
+#define GLIU_PAE               0x81
+#define GLIU_ARB               0x82
+#define GLIU_ASMI              0x83
+#define GLIU_AERR              0x84
+#define GLIU_DEBUG             0x85
+#define GLIU_PHY_CAP           0x86
+#define GLIU_NOUT_RESP         0x87
+#define GLIU_NOUT_WDATA                0x88
+#define GLIU_WHOAMI            0x8B
+#define GLIU_SLV_DIS           0x8C
+#define GLIU_IOD_BM0           0xE0
+#define GLIU_IOD_BM1           0xE1
+#define GLIU_IOD_BM2           0xE2
+#define GLIU_IOD_BM3           0xE3
+#define GLIU_IOD_BM4           0xE4
+#define GLIU_IOD_BM5           0xE5
+#define GLIU_IOD_BM6           0xE6
+#define GLIU_IOD_BM7           0xE7
+#define GLIU_IOD_BM8           0xE8
+#define GLIU_IOD_BM9           0xE9
+#define GLIU_IOD_SC0           0xEA
+#define GLIU_IOD_SC1           0xEB
+#define GLIU_IOD_SC2           0xEC
+#define GLIU_IOD_SC3           0xED
+#define GLIU_IOD_SC4           0xEE
+#define GLIU_IOD_SC5           0xEF
+#define GLIU_IOD_SC6           0xF0
+#define GLIU_IOD_SC7           0xF1

 
 /*
  * SB STANDARD
  */
 
 /*
  * SB STANDARD
  */

-#define        SB_CAP          0x00
-#define        SB_CONFIG       0x01
-#define        SB_SMI          0x02
-#define        SB_ERROR        0x03
-#define        SB_MAR_ERR_EN           0x00000001
-#define        SB_TAR_ERR_EN           0x00000002
-#define        SB_RSVD_BIT1            0x00000004
-#define        SB_EXCEP_ERR_EN         0x00000008
-#define        SB_SYSE_ERR_EN          0x00000010
-#define        SB_PARE_ERR_EN          0x00000020
-#define        SB_TAS_ERR_EN           0x00000040
-#define        SB_MAR_ERR_FLAG         0x00010000
-#define        SB_TAR_ERR_FLAG         0x00020000
-#define        SB_RSVD_BIT2            0x00040000
-#define        SB_EXCEP_ERR_FLAG       0x00080000
-#define        SB_SYSE_ERR_FLAG        0x00100000
-#define        SB_PARE_ERR_FLAG        0x00200000
-#define        SB_TAS_ERR_FLAG         0x00400000
-#define        SB_PM           0x04
-#define        SB_DIAG         0x05
+#define SB_CAP         0x00
+#define SB_CONFIG      0x01
+#define SB_SMI         0x02
+#define SB_ERROR       0x03
+#define SB_MAR_ERR_EN          0x00000001
+#define SB_TAR_ERR_EN          0x00000002
+#define SB_RSVD_BIT1           0x00000004
+#define SB_EXCEP_ERR_EN                0x00000008
+#define SB_SYSE_ERR_EN         0x00000010
+#define SB_PARE_ERR_EN         0x00000020
+#define SB_TAS_ERR_EN          0x00000040
+#define SB_MAR_ERR_FLAG                0x00010000
+#define SB_TAR_ERR_FLAG                0x00020000
+#define SB_RSVD_BIT2           0x00040000
+#define SB_EXCEP_ERR_FLAG      0x00080000
+#define SB_SYSE_ERR_FLAG       0x00100000
+#define SB_PARE_ERR_FLAG       0x00200000
+#define SB_TAS_ERR_FLAG                0x00400000
+#define SB_PM          0x04
+#define SB_DIAG                0x05

 
 /*
  * SB SPEC.
  */
 
 /*
  * SB SPEC.
  */

-#define        SB_CTRL         0x10
-#define        SB_R0           0x20
-#define        SB_R1           0x21
-#define        SB_R2           0x22
-#define        SB_R3           0x23
-#define        SB_R4           0x24
-#define        SB_R5           0x25
-#define        SB_R6           0x26
-#define        SB_R7           0x27
-#define        SB_R8           0x28
-#define        SB_R9           0x29
-#define        SB_R10          0x2A
-#define        SB_R11          0x2B
-#define        SB_R12          0x2C
-#define        SB_R13          0x2D
-#define        SB_R14          0x2E
-#define        SB_R15          0x2F
+#define SB_CTRL                0x10
+#define SB_R0          0x20
+#define SB_R1          0x21
+#define SB_R2          0x22
+#define SB_R3          0x23
+#define SB_R4          0x24
+#define SB_R5          0x25
+#define SB_R6          0x26
+#define SB_R7          0x27
+#define SB_R8          0x28
+#define SB_R9          0x29
+#define SB_R10         0x2A
+#define SB_R11         0x2B
+#define SB_R12         0x2C
+#define SB_R13         0x2D
+#define SB_R14         0x2E
+#define SB_R15         0x2F

 
 /*
  * GLCP STANDARD
  */
 
 /*
  * GLCP STANDARD
  */

-#define        GLCP_CAP                0x00
-#define        GLCP_CONFIG             0x01
-#define        GLCP_SMI                0x02
-#define        GLCP_ERROR              0x03
-#define        GLCP_PM                 0x04
-#define        GLCP_DIAG               0x05
+#define GLCP_CAP               0x00
+#define GLCP_CONFIG            0x01
+#define GLCP_SMI               0x02
+#define GLCP_ERROR             0x03
+#define GLCP_PM                        0x04
+#define GLCP_DIAG              0x05

 
 /*
  * GLCP SPEC.
  */
 
 /*
  * GLCP SPEC.
  */

-#define        GLCP_CLK_DIS_DELAY      0x08
-#define        GLCP_PM_CLK_DISABLE     0x09
-#define        GLCP_GLB_PM             0x0B
-#define        GLCP_DBG_OUT            0x0C
-#define        GLCP_RSVD1              0x0D
-#define        GLCP_SOFT_COM           0x0E
-#define        SOFT_BAR_SMB_FLAG       0x00000001
-#define        SOFT_BAR_GPIO_FLAG      0x00000002
-#define        SOFT_BAR_MFGPT_FLAG     0x00000004
-#define        SOFT_BAR_IRQ_FLAG       0x00000008
-#define        SOFT_BAR_PMS_FLAG       0x00000010
-#define        SOFT_BAR_ACPI_FLAG      0x00000020
-#define        SOFT_BAR_IDE_FLAG       0x00000400
-#define        SOFT_BAR_ACC_FLAG       0x00000800
-#define        SOFT_BAR_OHCI_FLAG      0x00001000
-#define        SOFT_BAR_EHCI_FLAG      0x00002000
-#define        GLCP_RSVD2              0x0F
-#define        GLCP_CLK_OFF            0x10
-#define        GLCP_CLK_ACTIVE         0x11
-#define        GLCP_CLK_DISABLE        0x12
-#define        GLCP_CLK4ACK            0x13
-#define        GLCP_SYS_RST            0x14
-#define        GLCP_RSVD3              0x15
-#define        GLCP_DBG_CLK_CTRL       0x16
-#define        GLCP_CHIP_REV_ID        0x17
+#define GLCP_CLK_DIS_DELAY     0x08
+#define GLCP_PM_CLK_DISABLE    0x09
+#define GLCP_GLB_PM            0x0B
+#define GLCP_DBG_OUT           0x0C
+#define GLCP_RSVD1             0x0D
+#define GLCP_SOFT_COM          0x0E
+#define SOFT_BAR_SMB_FLAG      0x00000001
+#define SOFT_BAR_GPIO_FLAG     0x00000002
+#define SOFT_BAR_MFGPT_FLAG    0x00000004
+#define SOFT_BAR_IRQ_FLAG      0x00000008
+#define SOFT_BAR_PMS_FLAG      0x00000010
+#define SOFT_BAR_ACPI_FLAG     0x00000020
+#define SOFT_BAR_IDE_FLAG      0x00000400
+#define SOFT_BAR_ACC_FLAG      0x00000800
+#define SOFT_BAR_OHCI_FLAG     0x00001000
+#define SOFT_BAR_EHCI_FLAG     0x00002000
+#define GLCP_RSVD2             0x0F
+#define GLCP_CLK_OFF           0x10
+#define GLCP_CLK_ACTIVE                0x11
+#define GLCP_CLK_DISABLE       0x12
+#define GLCP_CLK4ACK           0x13
+#define GLCP_SYS_RST           0x14
+#define GLCP_RSVD3             0x15
+#define GLCP_DBG_CLK_CTRL      0x16
+#define GLCP_CHIP_REV_ID       0x17

 
 /* PIC */
 
 /* PIC */

-#define        PIC_YSEL_LOW            0x20
-#define        PIC_YSEL_LOW_USB_SHIFT          8
-#define        PIC_YSEL_LOW_ACC_SHIFT          16
-#define        PIC_YSEL_LOW_FLASH_SHIFT        24
-#define        PIC_YSEL_HIGH           0x21
-#define        PIC_ZSEL_LOW            0x22
-#define        PIC_ZSEL_HIGH           0x23
-#define        PIC_IRQM_PRIM           0x24
-#define        PIC_IRQM_LPC            0x25
-#define        PIC_XIRR_STS_LOW        0x26
-#define        PIC_XIRR_STS_HIGH       0x27
-#define        PCI_SHDW                0x34
+#define PIC_YSEL_LOW           0x20
+#define PIC_YSEL_LOW_USB_SHIFT         8
+#define PIC_YSEL_LOW_ACC_SHIFT         16
+#define PIC_YSEL_LOW_FLASH_SHIFT       24
+#define PIC_YSEL_HIGH          0x21
+#define PIC_ZSEL_LOW           0x22
+#define PIC_ZSEL_HIGH          0x23
+#define PIC_IRQM_PRIM          0x24
+#define PIC_IRQM_LPC           0x25
+#define PIC_XIRR_STS_LOW       0x26
+#define PIC_XIRR_STS_HIGH      0x27
+#define PCI_SHDW               0x34

 
 /*
  * DIVIL STANDARD
  */
 
 /*
  * DIVIL STANDARD
  */

-#define        DIVIL_CAP               0x00
-#define        DIVIL_CONFIG            0x01
-#define        DIVIL_SMI               0x02
-#define        DIVIL_ERROR             0x03
-#define        DIVIL_PM                0x04
-#define        DIVIL_DIAG              0x05
+#define DIVIL_CAP              0x00
+#define DIVIL_CONFIG           0x01
+#define DIVIL_SMI              0x02
+#define DIVIL_ERROR            0x03
+#define DIVIL_PM               0x04
+#define DIVIL_DIAG             0x05

 
 /*
  * DIVIL SPEC.
  */
 
 /*
  * DIVIL SPEC.
  */

-#define        DIVIL_LBAR_IRQ          0x08
-#define        DIVIL_LBAR_KEL          0x09
-#define        DIVIL_LBAR_SMB          0x0B
-#define        DIVIL_LBAR_GPIO         0x0C
-#define        DIVIL_LBAR_MFGPT        0x0D
-#define        DIVIL_LBAR_ACPI         0x0E
-#define        DIVIL_LBAR_PMS          0x0F
-#define        DIVIL_LEG_IO            0x14
-#define        DIVIL_BALL_OPTS         0x15
-#define        DIVIL_SOFT_IRQ          0x16
-#define        DIVIL_SOFT_RESET        0x17
+#define DIVIL_LBAR_IRQ         0x08
+#define DIVIL_LBAR_KEL         0x09
+#define DIVIL_LBAR_SMB         0x0B
+#define DIVIL_LBAR_GPIO                0x0C
+#define DIVIL_LBAR_MFGPT       0x0D
+#define DIVIL_LBAR_ACPI                0x0E
+#define DIVIL_LBAR_PMS         0x0F
+#define DIVIL_LEG_IO           0x14
+#define DIVIL_BALL_OPTS                0x15
+#define DIVIL_SOFT_IRQ         0x16
+#define DIVIL_SOFT_RESET       0x17

 
 /* MFGPT */
 #define MFGPT_IRQ      0x28
 
 /* MFGPT */
 #define MFGPT_IRQ      0x28


@@ -254,52 +254,52 @@ extern void _wrmsr(u32 msr, u32 hi, u32 lo);
 /*
  * IDE STANDARD
  */
 /*
  * IDE STANDARD
  */

-#define        IDE_CAP         0x00
-#define        IDE_CONFIG      0x01
-#define        IDE_SMI         0x02
-#define        IDE_ERROR       0x03
-#define        IDE_PM          0x04
-#define        IDE_DIAG        0x05
+#define IDE_CAP                0x00
+#define IDE_CONFIG     0x01
+#define IDE_SMI                0x02
+#define IDE_ERROR      0x03
+#define IDE_PM         0x04
+#define IDE_DIAG       0x05

 
 /*
  * IDE SPEC.
  */
 
 /*
  * IDE SPEC.
  */

-#define        IDE_IO_BAR      0x08
-#define        IDE_CFG         0x10
-#define        IDE_DTC         0x12
-#define        IDE_CAST        0x13
-#define        IDE_ETC         0x14
-#define        IDE_INTERNAL_PM 0x15
+#define IDE_IO_BAR     0x08
+#define IDE_CFG                0x10
+#define IDE_DTC                0x12
+#define IDE_CAST       0x13
+#define IDE_ETC                0x14
+#define IDE_INTERNAL_PM 0x15

 
 /*
  * ACC STANDARD
  */
 
 /*
  * ACC STANDARD
  */

-#define        ACC_CAP         0x00
-#define        ACC_CONFIG      0x01
-#define        ACC_SMI         0x02
-#define        ACC_ERROR       0x03
-#define        ACC_PM          0x04
-#define        ACC_DIAG        0x05
+#define ACC_CAP                0x00
+#define ACC_CONFIG     0x01
+#define ACC_SMI                0x02
+#define ACC_ERROR      0x03
+#define ACC_PM         0x04
+#define ACC_DIAG       0x05

 
 /*
  * USB STANDARD
  */
 
 /*
  * USB STANDARD
  */

-#define        USB_CAP         0x00
-#define        USB_CONFIG      0x01
-#define        USB_SMI         0x02
-#define        USB_ERROR       0x03
-#define        USB_PM          0x04
-#define        USB_DIAG        0x05
+#define USB_CAP                0x00
+#define USB_CONFIG     0x01
+#define USB_SMI                0x02
+#define USB_ERROR      0x03
+#define USB_PM         0x04
+#define USB_DIAG       0x05

 
 /*
  * USB SPEC.
  */
 
 /*
  * USB SPEC.
  */

-#define        USB_OHCI        0x08
-#define        USB_EHCI        0x09
+#define USB_OHCI       0x08
+#define USB_EHCI       0x09

 
 /****************** NATIVE ***************************/
 /* GPIO : I/O SPACE; REG : 32BITS */
 
 /****************** NATIVE ***************************/
 /* GPIO : I/O SPACE; REG : 32BITS */

-#define        GPIOL_OUT_VAL           0x00
-#define        GPIOL_OUT_EN            0x04
+#define GPIOL_OUT_VAL          0x00
+#define GPIOL_OUT_EN           0x04

 
 #endif                         /* _CS5536_H */
 
 #endif                         /* _CS5536_H */

diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h
index 4b493d6772c2e9fc0f04d585e07867ca63836dcf..021d0172dad65d48f5d8e6eb09cde321b7e5880a 100644 (file)
--- a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h
@@ -25,7 +25,7 @@ static inline void __maybe_unused enable_mfgpt0_counter(void)
 #endif
 
 #define MFGPT_TICK_RATE 14318000
 #endif
 
 #define MFGPT_TICK_RATE 14318000

-#define COMPARE  ((MFGPT_TICK_RATE + HZ/2) / HZ)
+#define COMPARE         ((MFGPT_TICK_RATE + HZ/2) / HZ)

 
 #define MFGPT_BASE     mfgpt_base
 #define MFGPT0_CMP2    (MFGPT_BASE + 2)
 
 #define MFGPT_BASE     mfgpt_base
 #define MFGPT0_CMP2    (MFGPT_BASE + 2)

diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h
index 0dca9c89ee7cf53968344bf78cdd4c0033420fe5..8a7ecb4d5c64d266eb082d3fade03027872bc232 100644 (file)
--- a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h
@@ -8,8 +8,8 @@
  * Author : jlliu, liujl@lemote.com
  */
 
  * Author : jlliu, liujl@lemote.com
  */
 

-#ifndef        _CS5536_PCI_H
-#define        _CS5536_PCI_H
+#ifndef _CS5536_PCI_H
+#define _CS5536_PCI_H

 
 #include <linux/types.h>
 #include <linux/pci_regs.h>
 
 #include <linux/types.h>
 #include <linux/pci_regs.h>


@@ -17,20 +17,20 @@
 extern void cs5536_pci_conf_write4(int function, int reg, u32 value);
 extern u32 cs5536_pci_conf_read4(int function, int reg);
 
 extern void cs5536_pci_conf_write4(int function, int reg, u32 value);
 extern u32 cs5536_pci_conf_read4(int function, int reg);
 

-#define        CS5536_ACC_INTR         9
-#define        CS5536_IDE_INTR         14
-#define        CS5536_USB_INTR         11
-#define        CS5536_MFGPT_INTR       5
-#define        CS5536_UART1_INTR       4
-#define        CS5536_UART2_INTR       3
+#define CS5536_ACC_INTR                9
+#define CS5536_IDE_INTR                14
+#define CS5536_USB_INTR                11
+#define CS5536_MFGPT_INTR      5
+#define CS5536_UART1_INTR      4
+#define CS5536_UART2_INTR      3

 
 /************** PCI BUS DEVICE FUNCTION ***************/
 
 /*
  * PCI bus device function
  */
 
 /************** PCI BUS DEVICE FUNCTION ***************/
 
 /*
  * PCI bus device function
  */

-#define        PCI_BUS_CS5536          0
-#define        PCI_IDSEL_CS5536        14
+#define PCI_BUS_CS5536         0
+#define PCI_IDSEL_CS5536       14

 
 /********** STANDARD PCI-2.2 EXPANSION ****************/
 
 
 /********** STANDARD PCI-2.2 EXPANSION ****************/
 


@@ -45,21 +45,21 @@ extern u32 cs5536_pci_conf_read4(int function, int reg);
        (((mod_dev_id) << 16) | (sys_vendor_id))
 
 /* VENDOR ID */
        (((mod_dev_id) << 16) | (sys_vendor_id))
 
 /* VENDOR ID */

-#define        CS5536_VENDOR_ID        0x1022
+#define CS5536_VENDOR_ID       0x1022

 
 /* DEVICE ID */
 
 /* DEVICE ID */

-#define        CS5536_ISA_DEVICE_ID            0x2090
-#define        CS5536_IDE_DEVICE_ID            0x209a
-#define        CS5536_ACC_DEVICE_ID            0x2093
-#define        CS5536_OHCI_DEVICE_ID           0x2094
-#define        CS5536_EHCI_DEVICE_ID           0x2095
+#define CS5536_ISA_DEVICE_ID           0x2090
+#define CS5536_IDE_DEVICE_ID           0x209a
+#define CS5536_ACC_DEVICE_ID           0x2093
+#define CS5536_OHCI_DEVICE_ID          0x2094
+#define CS5536_EHCI_DEVICE_ID          0x2095

 
 /* CLASS CODE : CLASS SUB-CLASS INTERFACE */
 
 /* CLASS CODE : CLASS SUB-CLASS INTERFACE */

-#define        CS5536_ISA_CLASS_CODE           0x060100
+#define CS5536_ISA_CLASS_CODE          0x060100

 #define CS5536_IDE_CLASS_CODE          0x010180
 #define CS5536_IDE_CLASS_CODE          0x010180

-#define        CS5536_ACC_CLASS_CODE           0x040100
-#define        CS5536_OHCI_CLASS_CODE          0x0C0310
-#define        CS5536_EHCI_CLASS_CODE          0x0C0320
+#define CS5536_ACC_CLASS_CODE          0x040100
+#define CS5536_OHCI_CLASS_CODE         0x0C0310
+#define CS5536_EHCI_CLASS_CODE         0x0C0320

 
 /* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */
 
 
 /* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */
 


@@ -67,40 +67,40 @@ extern u32 cs5536_pci_conf_read4(int function, int reg);
        ((PCI_NONE_BIST << 24) | ((header_type) << 16) \
                | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE);
 
        ((PCI_NONE_BIST << 24) | ((header_type) << 16) \
                | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE);
 

-#define        PCI_NONE_BIST                   0x00    /* RO not implemented yet. */
-#define        PCI_BRIDGE_HEADER_TYPE          0x80    /* RO */
-#define        PCI_NORMAL_HEADER_TYPE          0x00
-#define        PCI_NORMAL_LATENCY_TIMER        0x00
-#define        PCI_NORMAL_CACHE_LINE_SIZE      0x08    /* RW */
+#define PCI_NONE_BIST                  0x00    /* RO not implemented yet. */
+#define PCI_BRIDGE_HEADER_TYPE         0x80    /* RO */
+#define PCI_NORMAL_HEADER_TYPE         0x00
+#define PCI_NORMAL_LATENCY_TIMER       0x00
+#define PCI_NORMAL_CACHE_LINE_SIZE     0x08    /* RW */

 
 /* BAR */
 
 /* BAR */

-#define        PCI_BAR0_REG                    0x10
-#define        PCI_BAR1_REG                    0x14
-#define        PCI_BAR2_REG                    0x18
-#define        PCI_BAR3_REG                    0x1c
-#define        PCI_BAR4_REG                    0x20
-#define        PCI_BAR5_REG                    0x24
-#define        PCI_BAR_COUNT                   6
-#define        PCI_BAR_RANGE_MASK              0xFFFFFFFF
+#define PCI_BAR0_REG                   0x10
+#define PCI_BAR1_REG                   0x14
+#define PCI_BAR2_REG                   0x18
+#define PCI_BAR3_REG                   0x1c
+#define PCI_BAR4_REG                   0x20
+#define PCI_BAR5_REG                   0x24
+#define PCI_BAR_COUNT                  6
+#define PCI_BAR_RANGE_MASK             0xFFFFFFFF

 
 /* CARDBUS CIS POINTER */
 
 /* CARDBUS CIS POINTER */

-#define        PCI_CARDBUS_CIS_POINTER         0x00000000
+#define PCI_CARDBUS_CIS_POINTER                0x00000000

 
 

-/* SUBSYSTEM VENDOR ID  */
-#define        CS5536_SUB_VENDOR_ID            CS5536_VENDOR_ID
+/* SUBSYSTEM VENDOR ID */
+#define CS5536_SUB_VENDOR_ID           CS5536_VENDOR_ID

 
 /* SUBSYSTEM ID */
 
 /* SUBSYSTEM ID */

-#define        CS5536_ISA_SUB_ID               CS5536_ISA_DEVICE_ID
-#define        CS5536_IDE_SUB_ID               CS5536_IDE_DEVICE_ID
-#define        CS5536_ACC_SUB_ID               CS5536_ACC_DEVICE_ID
-#define        CS5536_OHCI_SUB_ID              CS5536_OHCI_DEVICE_ID
-#define        CS5536_EHCI_SUB_ID              CS5536_EHCI_DEVICE_ID
+#define CS5536_ISA_SUB_ID              CS5536_ISA_DEVICE_ID
+#define CS5536_IDE_SUB_ID              CS5536_IDE_DEVICE_ID
+#define CS5536_ACC_SUB_ID              CS5536_ACC_DEVICE_ID
+#define CS5536_OHCI_SUB_ID             CS5536_OHCI_DEVICE_ID
+#define CS5536_EHCI_SUB_ID             CS5536_EHCI_DEVICE_ID

 
 /* EXPANSION ROM BAR */
 
 /* EXPANSION ROM BAR */

-#define        PCI_EXPANSION_ROM_BAR           0x00000000
+#define PCI_EXPANSION_ROM_BAR          0x00000000

 
 /* CAPABILITIES POINTER */
 
 /* CAPABILITIES POINTER */

-#define        PCI_CAPLIST_POINTER             0x00000000
+#define PCI_CAPLIST_POINTER            0x00000000

 #define PCI_CAPLIST_USB_POINTER                0x40
 /* INTERRUPT */
 
 #define PCI_CAPLIST_USB_POINTER                0x40
 /* INTERRUPT */
 


@@ -108,46 +108,46 @@ extern u32 cs5536_pci_conf_read4(int function, int reg);
        ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \
                ((pin) << 8) | (mod_intr))
 
        ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \
                ((pin) << 8) | (mod_intr))
 

-#define        PCI_MAX_LATENCY                 0x40
-#define        PCI_MIN_GRANT                   0x00
-#define        PCI_DEFAULT_PIN                 0x01
+#define PCI_MAX_LATENCY                        0x40
+#define PCI_MIN_GRANT                  0x00
+#define PCI_DEFAULT_PIN                        0x01

 
 /*********** EXPANSION PCI REG ************************/
 
 /*
  * ISA EXPANSION
  */
 
 /*********** EXPANSION PCI REG ************************/
 
 /*
  * ISA EXPANSION
  */

-#define        PCI_UART1_INT_REG       0x50
+#define PCI_UART1_INT_REG      0x50

 #define PCI_UART2_INT_REG      0x54
 #define PCI_UART2_INT_REG      0x54

-#define        PCI_ISA_FIXUP_REG       0x58
+#define PCI_ISA_FIXUP_REG      0x58

 
 /*
  * IDE EXPANSION
  */
 
 /*
  * IDE EXPANSION
  */

-#define        PCI_IDE_CFG_REG         0x40
-#define        CS5536_IDE_FLASH_SIGNATURE      0xDEADBEEF
-#define        PCI_IDE_DTC_REG         0x48
-#define        PCI_IDE_CAST_REG        0x4C
-#define        PCI_IDE_ETC_REG         0x50
-#define        PCI_IDE_PM_REG          0x54
-#define        PCI_IDE_INT_REG         0x60
+#define PCI_IDE_CFG_REG                0x40
+#define CS5536_IDE_FLASH_SIGNATURE     0xDEADBEEF
+#define PCI_IDE_DTC_REG                0x48
+#define PCI_IDE_CAST_REG       0x4C
+#define PCI_IDE_ETC_REG                0x50
+#define PCI_IDE_PM_REG         0x54
+#define PCI_IDE_INT_REG                0x60

 
 /*
  * ACC EXPANSION
  */
 
 /*
  * ACC EXPANSION
  */

-#define        PCI_ACC_INT_REG         0x50
+#define PCI_ACC_INT_REG                0x50

 
 /*
  * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI
  */
 
 /*
  * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI
  */

-#define        PCI_OHCI_PM_REG         0x40
-#define        PCI_OHCI_INT_REG        0x50
+#define PCI_OHCI_PM_REG                0x40
+#define PCI_OHCI_INT_REG       0x50

 
 /*
  * EHCI EXPANSION
  */
 
 /*
  * EHCI EXPANSION
  */

-#define        PCI_EHCI_LEGSMIEN_REG   0x50
-#define        PCI_EHCI_LEGSMISTS_REG  0x54
-#define        PCI_EHCI_FLADJ_REG      0x60
+#define PCI_EHCI_LEGSMIEN_REG  0x50
+#define PCI_EHCI_LEGSMISTS_REG 0x54
+#define PCI_EHCI_FLADJ_REG     0x60

 
 #endif                         /* _CS5536_PCI_H_ */
 
 #endif                         /* _CS5536_PCI_H_ */

diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
index 21c4ecedebe78013adf8c56f1eea989eaa2cecd6..1f17c1815ee5e0c1d4a9c36f8fd1b0181f698054 100644 (file)
--- a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
+++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h
@@ -5,8 +5,8 @@
  * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  */
 
  * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  */
 

-#ifndef        _CS5536_VSM_H
-#define        _CS5536_VSM_H
+#ifndef _CS5536_VSM_H
+#define _CS5536_VSM_H

 
 #include <linux/types.h>
 
 
 #include <linux/types.h>
 

diff --git a/arch/mips/include/asm/mach-loongson/gpio.h b/arch/mips/include/asm/mach-loongson/gpio.h
index e30e73d443df8f022b0a8d68ddfb0a481eab3826..211a7b7138fe320c2cebde9a1cca9656a6b112f4 100644 (file)
--- a/arch/mips/include/asm/mach-loongson/gpio.h
+++ b/arch/mips/include/asm/mach-loongson/gpio.h
@@ -10,8 +10,8 @@
  * (at your option) any later version.
  */
 
  * (at your option) any later version.
  */
 

-#ifndef        __STLS2F_GPIO_H
-#define        __STLS2F_GPIO_H
+#ifndef __STLS2F_GPIO_H
+#define __STLS2F_GPIO_H

 
 #include <asm-generic/gpio.h>
 
 
 #include <asm-generic/gpio.h>
 

diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index 5222a007bc212a55746f9155605a836da6763442..b286534fef0899007bb0640c1e12415a73b81714 100644 (file)
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -2,8 +2,8 @@
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  *
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */


@@ -52,7 +52,7 @@ extern void mach_irq_dispatch(unsigned int pending);
 extern int mach_i8259_irq(void);
 
 /* We need this in some places... */
 extern int mach_i8259_irq(void);
 
 /* We need this in some places... */

-#define delay()        ({              \
+#define delay() ({             \

        int x;                          \
        for (x = 0; x < 100000; x++)    \
                __asm__ __volatile__(""); \
        int x;                          \
        for (x = 0; x < 100000; x++)    \
                __asm__ __volatile__(""); \


@@ -82,13 +82,13 @@ static inline void do_perfcnt_IRQ(void)
 
 #define LOONGSON_BOOT_BASE     0x1fc00000
 #define LOONGSON_BOOT_SIZE     0x00100000      /* 1M */
 
 #define LOONGSON_BOOT_BASE     0x1fc00000
 #define LOONGSON_BOOT_SIZE     0x00100000      /* 1M */

-#define LOONGSON_BOOT_TOP      (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
-#define LOONGSON_REG_BASE      0x1fe00000
-#define LOONGSON_REG_SIZE      0x00100000      /* 256Bytes + 256Bytes + ??? */
+#define LOONGSON_BOOT_TOP      (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
+#define LOONGSON_REG_BASE      0x1fe00000
+#define LOONGSON_REG_SIZE      0x00100000      /* 256Bytes + 256Bytes + ??? */

 #define LOONGSON_REG_TOP       (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
 
 #define LOONGSON_REG_TOP       (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
 

-#define LOONGSON_LIO1_BASE     0x1ff00000
-#define LOONGSON_LIO1_SIZE     0x00100000      /* 1M */
+#define LOONGSON_LIO1_BASE     0x1ff00000
+#define LOONGSON_LIO1_SIZE     0x00100000      /* 1M */

 #define LOONGSON_LIO1_TOP      (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
 
 #define LOONGSON_PCILO0_BASE   0x10000000
 #define LOONGSON_LIO1_TOP      (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
 
 #define LOONGSON_PCILO0_BASE   0x10000000


@@ -115,13 +115,13 @@ static inline void do_perfcnt_IRQ(void)
 #define LOONGSON_PCI_REG(x)    LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
 #define LOONGSON_PCIDID                LOONGSON_PCI_REG(0x00)
 #define LOONGSON_PCICMD                LOONGSON_PCI_REG(0x04)
 #define LOONGSON_PCI_REG(x)    LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
 #define LOONGSON_PCIDID                LOONGSON_PCI_REG(0x00)
 #define LOONGSON_PCICMD                LOONGSON_PCI_REG(0x04)

-#define LOONGSON_PCICLASS      LOONGSON_PCI_REG(0x08)
+#define LOONGSON_PCICLASS      LOONGSON_PCI_REG(0x08)

 #define LOONGSON_PCILTIMER     LOONGSON_PCI_REG(0x0c)
 #define LOONGSON_PCILTIMER     LOONGSON_PCI_REG(0x0c)

-#define LOONGSON_PCIBASE0      LOONGSON_PCI_REG(0x10)
-#define LOONGSON_PCIBASE1      LOONGSON_PCI_REG(0x14)
-#define LOONGSON_PCIBASE2      LOONGSON_PCI_REG(0x18)
-#define LOONGSON_PCIBASE3      LOONGSON_PCI_REG(0x1c)
-#define LOONGSON_PCIBASE4      LOONGSON_PCI_REG(0x20)
+#define LOONGSON_PCIBASE0      LOONGSON_PCI_REG(0x10)
+#define LOONGSON_PCIBASE1      LOONGSON_PCI_REG(0x14)
+#define LOONGSON_PCIBASE2      LOONGSON_PCI_REG(0x18)
+#define LOONGSON_PCIBASE3      LOONGSON_PCI_REG(0x1c)
+#define LOONGSON_PCIBASE4      LOONGSON_PCI_REG(0x20)

 #define LOONGSON_PCIEXPRBASE   LOONGSON_PCI_REG(0x30)
 #define LOONGSON_PCIINT                LOONGSON_PCI_REG(0x3c)
 
 #define LOONGSON_PCIEXPRBASE   LOONGSON_PCI_REG(0x30)
 #define LOONGSON_PCIINT                LOONGSON_PCI_REG(0x3c)
 


@@ -132,7 +132,7 @@ static inline void do_perfcnt_IRQ(void)
 #define LOONGSON_PCICMD_MABORT_CLR     0x20000000
 #define LOONGSON_PCICMD_MTABORT_CLR    0x10000000
 #define LOONGSON_PCICMD_TABORT_CLR     0x08000000
 #define LOONGSON_PCICMD_MABORT_CLR     0x20000000
 #define LOONGSON_PCICMD_MTABORT_CLR    0x10000000
 #define LOONGSON_PCICMD_TABORT_CLR     0x08000000

-#define LOONGSON_PCICMD_MPERR_CLR      0x01000000
+#define LOONGSON_PCICMD_MPERR_CLR      0x01000000

 #define LOONGSON_PCICMD_PERRRESPEN     0x00000040
 #define LOONGSON_PCICMD_ASTEPEN                0x00000080
 #define LOONGSON_PCICMD_SERREN         0x00000100
 #define LOONGSON_PCICMD_PERRRESPEN     0x00000040
 #define LOONGSON_PCICMD_ASTEPEN                0x00000080
 #define LOONGSON_PCICMD_SERREN         0x00000100


@@ -142,7 +142,7 @@ static inline void do_perfcnt_IRQ(void)
 /* Loongson h/w Configuration */
 
 #define LOONGSON_GENCFG_OFFSET         0x4
 /* Loongson h/w Configuration */
 
 #define LOONGSON_GENCFG_OFFSET         0x4

-#define LOONGSON_GENCFG        LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
+#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)

 
 #define LOONGSON_GENCFG_DEBUGMODE      0x00000001
 #define LOONGSON_GENCFG_SNOOPEN                0x00000002
 
 #define LOONGSON_GENCFG_DEBUGMODE      0x00000001
 #define LOONGSON_GENCFG_SNOOPEN                0x00000002


@@ -173,25 +173,25 @@ static inline void do_perfcnt_IRQ(void)
 
 /* GPIO Regs - r/w */
 
 
 /* GPIO Regs - r/w */
 

-#define LOONGSON_GPIODATA              LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
+#define LOONGSON_GPIODATA              LOONGSON_REG(LOONGSON_REGBASE + 0x1c)

 #define LOONGSON_GPIOIE                        LOONGSON_REG(LOONGSON_REGBASE + 0x20)
 
 /* ICU Configuration Regs - r/w */
 
 #define LOONGSON_INTEDGE               LOONGSON_REG(LOONGSON_REGBASE + 0x24)
 #define LOONGSON_GPIOIE                        LOONGSON_REG(LOONGSON_REGBASE + 0x20)
 
 /* ICU Configuration Regs - r/w */
 
 #define LOONGSON_INTEDGE               LOONGSON_REG(LOONGSON_REGBASE + 0x24)

-#define LOONGSON_INTSTEER              LOONGSON_REG(LOONGSON_REGBASE + 0x28)
+#define LOONGSON_INTSTEER              LOONGSON_REG(LOONGSON_REGBASE + 0x28)

 #define LOONGSON_INTPOL                        LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
 
 /* ICU Enable Regs - IntEn & IntISR are r/o. */
 
 #define LOONGSON_INTPOL                        LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
 
 /* ICU Enable Regs - IntEn & IntISR are r/o. */
 

-#define LOONGSON_INTENSET              LOONGSON_REG(LOONGSON_REGBASE + 0x30)
-#define LOONGSON_INTENCLR              LOONGSON_REG(LOONGSON_REGBASE + 0x34)
+#define LOONGSON_INTENSET              LOONGSON_REG(LOONGSON_REGBASE + 0x30)
+#define LOONGSON_INTENCLR              LOONGSON_REG(LOONGSON_REGBASE + 0x34)

 #define LOONGSON_INTEN                 LOONGSON_REG(LOONGSON_REGBASE + 0x38)
 #define LOONGSON_INTISR                        LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
 
 /* ICU */
 #define LOONGSON_ICU_MBOXES            0x0000000f
 #define LOONGSON_INTEN                 LOONGSON_REG(LOONGSON_REGBASE + 0x38)
 #define LOONGSON_INTISR                        LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
 
 /* ICU */
 #define LOONGSON_ICU_MBOXES            0x0000000f

-#define LOONGSON_ICU_MBOXES_SHIFT      0
+#define LOONGSON_ICU_MBOXES_SHIFT      0

 #define LOONGSON_ICU_DMARDY            0x00000010
 #define LOONGSON_ICU_DMAEMPTY          0x00000020
 #define LOONGSON_ICU_COPYRDY           0x00000040
 #define LOONGSON_ICU_DMARDY            0x00000010
 #define LOONGSON_ICU_DMAEMPTY          0x00000020
 #define LOONGSON_ICU_COPYRDY           0x00000040


@@ -212,10 +212,10 @@ static inline void do_perfcnt_IRQ(void)
 
 /* PCI prefetch window base & mask */
 
 
 /* PCI prefetch window base & mask */
 

-#define LOONGSON_MEM_WIN_BASE_L        LOONGSON_REG(LOONGSON_REGBASE + 0x40)
-#define LOONGSON_MEM_WIN_BASE_H        LOONGSON_REG(LOONGSON_REGBASE + 0x44)
-#define LOONGSON_MEM_WIN_MASK_L        LOONGSON_REG(LOONGSON_REGBASE + 0x48)
-#define LOONGSON_MEM_WIN_MASK_H        LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
+#define LOONGSON_MEM_WIN_BASE_L                LOONGSON_REG(LOONGSON_REGBASE + 0x40)
+#define LOONGSON_MEM_WIN_BASE_H                LOONGSON_REG(LOONGSON_REGBASE + 0x44)
+#define LOONGSON_MEM_WIN_MASK_L                LOONGSON_REG(LOONGSON_REGBASE + 0x48)
+#define LOONGSON_MEM_WIN_MASK_H                LOONGSON_REG(LOONGSON_REGBASE + 0x4c)

 
 /* PCI_Hit*_Sel_* */
 
 
 /* PCI_Hit*_Sel_* */
 

diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h
index 43213388c174a3609faae87ad2ac3a7e0ba7a12c..3810d5ca84ac1c592b6fca12ec7ff7cf8435305c 100644 (file)
--- a/arch/mips/include/asm/mach-loongson/machine.h
+++ b/arch/mips/include/asm/mach-loongson/machine.h
@@ -2,8 +2,8 @@
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  *
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/include/asm/mach-loongson/mem.h b/arch/mips/include/asm/mach-loongson/mem.h
index 3b23ee8647d6dd443251b4757ea2fd0780002c4a..f4a36d7dbfabd864d97df1a9e2c135cc1e4c5b63 100644 (file)
--- a/arch/mips/include/asm/mach-loongson/mem.h
+++ b/arch/mips/include/asm/mach-loongson/mem.h
@@ -2,8 +2,8 @@
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  *
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin <wuzhangjin@gmail.com>
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/include/asm/mach-loongson1/irq.h b/arch/mips/include/asm/mach-loongson1/irq.h
index da96ed42f7332b6eca19d2ccea15a5f256cc6616..96bfb1c1c73d2417e8662f0baf78dba2da6c61b1 100644 (file)
--- a/arch/mips/include/asm/mach-loongson1/irq.h
+++ b/arch/mips/include/asm/mach-loongson1/irq.h
@@ -3,8 +3,8 @@
  *
  * IRQ mappings for Loongson 1
  *
  *
  * IRQ mappings for Loongson 1
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/include/asm/mach-loongson1/loongson1.h b/arch/mips/include/asm/mach-loongson1/loongson1.h
index 4e18e88cebbfbdd2216259ff7026124fab08feea..5c437c2ba6b3067a9836a7665db7718c547673a1 100644 (file)
--- a/arch/mips/include/asm/mach-loongson1/loongson1.h
+++ b/arch/mips/include/asm/mach-loongson1/loongson1.h
@@ -3,8 +3,8 @@
  *
  * Register mappings for Loongson 1
  *
  *
  * Register mappings for Loongson 1
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/include/asm/mach-loongson1/platform.h b/arch/mips/include/asm/mach-loongson1/platform.h
index 718a1228a4f30648e219726b8f42e7e316f047c5..30c13e508fff79de7ff31dda1adafed7ebe0153b 100644 (file)
--- a/arch/mips/include/asm/mach-loongson1/platform.h
+++ b/arch/mips/include/asm/mach-loongson1/platform.h
@@ -1,8 +1,8 @@
 /*
  * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
  *
 /*
  * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/include/asm/mach-loongson1/prom.h b/arch/mips/include/asm/mach-loongson1/prom.h
index b871dc41b8d91990f0815e3f2fbd5be9e9ff6bf7..34859a4d4ac4ccafbc59bfd4beb3b696d336ce23 100644 (file)
--- a/arch/mips/include/asm/mach-loongson1/prom.h
+++ b/arch/mips/include/asm/mach-loongson1/prom.h
@@ -1,8 +1,8 @@
 /*
  * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
  *
 /*
  * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/include/asm/mach-loongson1/regs-clk.h b/arch/mips/include/asm/mach-loongson1/regs-clk.h
index a81fa3d0dc9157f4bf6c1db273a636043daa8120..fb6a3ff9318fe5ef6d38154ecd14e26c258bb5b6 100644 (file)
--- a/arch/mips/include/asm/mach-loongson1/regs-clk.h
+++ b/arch/mips/include/asm/mach-loongson1/regs-clk.h
@@ -3,8 +3,8 @@
  *
  * Loongson 1 Clock Register Definitions.
  *
  *
  * Loongson 1 Clock Register Definitions.
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/include/asm/mach-loongson1/regs-wdt.h b/arch/mips/include/asm/mach-loongson1/regs-wdt.h
index f897de68c52730780c8b64e8cb46eee8f6fdd888..6574568c208495211c5e7dafa231c1123404de97 100644 (file)
--- a/arch/mips/include/asm/mach-loongson1/regs-wdt.h
+++ b/arch/mips/include/asm/mach-loongson1/regs-wdt.h
@@ -3,8 +3,8 @@
  *
  * Loongson 1 watchdog register definitions.
  *
  *
  * Loongson 1 watchdog register definitions.
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h
index 37e3583a9fdd0c8393c76a45251069751e4f6999..de3b66a3723ee3131db1a26b467628717cf123ef 100644 (file)
--- a/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-malta/cpu-feature-overrides.h
@@ -23,8 +23,8 @@
 /* #define cpu_has_watch       ? */
 #define cpu_has_divec          1
 #define cpu_has_vce            0
 /* #define cpu_has_watch       ? */
 #define cpu_has_divec          1
 #define cpu_has_vce            0

-/* #define cpu_has_cache_cdex_p        ? */
-/* #define cpu_has_cache_cdex_s        ? */
+/* #define cpu_has_cache_cdex_p ? */
+/* #define cpu_has_cache_cdex_s ? */

 /* #define cpu_has_prefetch    ? */
 #define cpu_has_mcheck         1
 /* #define cpu_has_ejtag       ? */
 /* #define cpu_has_prefetch    ? */
 #define cpu_has_mcheck         1
 /* #define cpu_has_ejtag       ? */


@@ -50,8 +50,8 @@
 /* #define cpu_has_watch       ? */
 #define cpu_has_divec          1
 #define cpu_has_vce            0
 /* #define cpu_has_watch       ? */
 #define cpu_has_divec          1
 #define cpu_has_vce            0

-/* #define cpu_has_cache_cdex_p        ? */
-/* #define cpu_has_cache_cdex_s        ? */
+/* #define cpu_has_cache_cdex_p ? */
+/* #define cpu_has_cache_cdex_s ? */

 /* #define cpu_has_prefetch    ? */
 #define cpu_has_mcheck         1
 /* #define cpu_has_ejtag       ? */
 /* #define cpu_has_prefetch    ? */
 #define cpu_has_mcheck         1
 /* #define cpu_has_ejtag       ? */

diff --git a/arch/mips/include/asm/mach-malta/irq.h b/arch/mips/include/asm/mach-malta/irq.h
index 9b9da26683c22448d3b0a1b4a69f6a81ba585d3d..47cfe64efbb0d5fe9ee21eb26f05f7ae02c7c28c 100644 (file)
--- a/arch/mips/include/asm/mach-malta/irq.h
+++ b/arch/mips/include/asm/mach-malta/irq.h
@@ -2,7 +2,7 @@
 #define __ASM_MACH_MIPS_IRQ_H
 
 
 #define __ASM_MACH_MIPS_IRQ_H
 
 

-#define NR_IRQS        256
+#define NR_IRQS 256

 
 #include_next <irq.h>
 
 
 #include_next <irq.h>
 

diff --git a/arch/mips/include/asm/mach-malta/mach-gt64120.h b/arch/mips/include/asm/mach-malta/mach-gt64120.h
index 0f863148f3b604ee405fc74c5bf8f180da7b7af6..62a4b2889fa76b2941f52cf8460f48f2b1f425d5 100644 (file)
--- a/arch/mips/include/asm/mach-malta/mach-gt64120.h
+++ b/arch/mips/include/asm/mach-malta/mach-gt64120.h
@@ -1,6 +1,6 @@
 /*
  *  This is a direct copy of the ev96100.h file, with a global
 /*
  *  This is a direct copy of the ev96100.h file, with a global

- * search and replace.  The numbers are the same.
+ * search and replace. The numbers are the same.

  *
  *  The reason I'm duplicating this is so that the 64120/96100
  * defines won't be confusing in the source code.
  *
  *  The reason I'm duplicating this is so that the 64120/96100
  * defines won't be confusing in the source code.

diff --git a/arch/mips/include/asm/mach-pnx833x/irq-mapping.h b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h
index 6d70264557b23005fcca2d44235d0a8e1417faa4..daa85ce03ef6f5f2f08616e05dd7167e9438e810 100644 (file)
--- a/arch/mips/include/asm/mach-pnx833x/irq-mapping.h
+++ b/arch/mips/include/asm/mach-pnx833x/irq-mapping.h
@@ -42,15 +42,15 @@
 #define PNX833X_TIMER_IRQ                              (MIPS_CPU_IRQ_BASE + 7)
 
 /* Interrupts supported by PIC */
 #define PNX833X_TIMER_IRQ                              (MIPS_CPU_IRQ_BASE + 7)
 
 /* Interrupts supported by PIC */

-#define PNX833X_PIC_I2C0_INT                   (PNX833X_PIC_IRQ_BASE +  1)
-#define PNX833X_PIC_I2C1_INT                   (PNX833X_PIC_IRQ_BASE +  2)
-#define PNX833X_PIC_UART0_INT                  (PNX833X_PIC_IRQ_BASE +  3)
-#define PNX833X_PIC_UART1_INT                  (PNX833X_PIC_IRQ_BASE +  4)
-#define PNX833X_PIC_TS_IN0_DV_INT              (PNX833X_PIC_IRQ_BASE +  5)
-#define PNX833X_PIC_TS_IN0_DMA_INT             (PNX833X_PIC_IRQ_BASE +  6)
-#define PNX833X_PIC_GPIO_INT                   (PNX833X_PIC_IRQ_BASE +  7)
-#define PNX833X_PIC_AUDIO_DEC_INT              (PNX833X_PIC_IRQ_BASE +  8)
-#define PNX833X_PIC_VIDEO_DEC_INT              (PNX833X_PIC_IRQ_BASE +  9)
+#define PNX833X_PIC_I2C0_INT                   (PNX833X_PIC_IRQ_BASE +  1)
+#define PNX833X_PIC_I2C1_INT                   (PNX833X_PIC_IRQ_BASE +  2)
+#define PNX833X_PIC_UART0_INT                  (PNX833X_PIC_IRQ_BASE +  3)
+#define PNX833X_PIC_UART1_INT                  (PNX833X_PIC_IRQ_BASE +  4)
+#define PNX833X_PIC_TS_IN0_DV_INT              (PNX833X_PIC_IRQ_BASE +  5)
+#define PNX833X_PIC_TS_IN0_DMA_INT             (PNX833X_PIC_IRQ_BASE +  6)
+#define PNX833X_PIC_GPIO_INT                   (PNX833X_PIC_IRQ_BASE +  7)
+#define PNX833X_PIC_AUDIO_DEC_INT              (PNX833X_PIC_IRQ_BASE +  8)
+#define PNX833X_PIC_VIDEO_DEC_INT              (PNX833X_PIC_IRQ_BASE +  9)

 #define PNX833X_PIC_CONFIG_INT                 (PNX833X_PIC_IRQ_BASE + 10)
 #define PNX833X_PIC_AOI_INT                            (PNX833X_PIC_IRQ_BASE + 11)
 #define PNX833X_PIC_SYNC_INT                   (PNX833X_PIC_IRQ_BASE + 12)
 #define PNX833X_PIC_CONFIG_INT                 (PNX833X_PIC_IRQ_BASE + 10)
 #define PNX833X_PIC_AOI_INT                            (PNX833X_PIC_IRQ_BASE + 11)
 #define PNX833X_PIC_SYNC_INT                   (PNX833X_PIC_IRQ_BASE + 12)

diff --git a/arch/mips/include/asm/mach-pnx833x/pnx833x.h b/arch/mips/include/asm/mach-pnx833x/pnx833x.h
index 100f52870e3ce2a670e4c4e318b2f212593afe41..e6fc3a9d594a52d456b1154645491f14ca4dafee 100644 (file)
--- a/arch/mips/include/asm/mach-pnx833x/pnx833x.h
+++ b/arch/mips/include/asm/mach-pnx833x/pnx833x.h
@@ -73,7 +73,7 @@
 
 
 #define PNX833X_RESET_CONTROL          PNX833X_REG(0x8004)
 
 
 #define PNX833X_RESET_CONTROL          PNX833X_REG(0x8004)

-#define PNX833X_RESET_CONTROL_2        PNX833X_REG(0x8014)
+#define PNX833X_RESET_CONTROL_2                PNX833X_REG(0x8014)

 
 #define PNX833X_PIC_REG(offs)          PNX833X_REG(0x01000 + (offs))
 #define PNX833X_PIC_INT_PRIORITY       PNX833X_PIC_REG(0x0)
 
 #define PNX833X_PIC_REG(offs)          PNX833X_REG(0x01000 + (offs))
 #define PNX833X_PIC_INT_PRIORITY       PNX833X_PIC_REG(0x0)


@@ -82,10 +82,10 @@
 #define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT      3
 #define PNX833X_PIC_INT_REG(irq)       PNX833X_PIC_REG(0x10 + 4*(irq))
 
 #define PNX833X_PIC_INT_SRC_INT_SRC_SHIFT      3
 #define PNX833X_PIC_INT_REG(irq)       PNX833X_PIC_REG(0x10 + 4*(irq))
 

-#define PNX833X_CLOCK_CPUCP_CTL        PNX833X_REG(0x9228)
+#define PNX833X_CLOCK_CPUCP_CTL PNX833X_REG(0x9228)

 #define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET     0x00000002ul    /* bit 1 */
 #define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK 0x00000018ul    /* bits 4:3 */
 #define PNX833X_CLOCK_CPUCP_CTL_EXIT_RESET     0x00000002ul    /* bit 1 */
 #define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_MASK 0x00000018ul    /* bits 4:3 */

-#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT        3
+#define PNX833X_CLOCK_CPUCP_CTL_DIV_CLOCK_SHIFT 3

 
 #define PNX8335_CLOCK_PLL_CPU_CTL              PNX833X_REG(0x9020)
 #define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK    0x1f
 
 #define PNX8335_CLOCK_PLL_CPU_CTL              PNX833X_REG(0x9020)
 #define PNX8335_CLOCK_PLL_CPU_CTL_FREQ_MASK    0x1f


@@ -149,7 +149,7 @@
 #define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK  (1 << 14)
 #define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT 14
 
 #define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_MASK  (1 << 14)
 #define PNX833X_MIU_SEL0_SPI_MODE_ENABLE_SHIFT 14
 

-#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK        (1 << 7)
+#define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_MASK (1 << 7)

 #define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT       7
 
 #define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK   (0xF << 9)
 #define PNX833X_MIU_SEL0_BURST_MODE_ENABLE_SHIFT       7
 
 #define PNX833X_MIU_SEL0_BURST_PAGE_LEN_MASK   (0xF << 9)


@@ -160,10 +160,10 @@
 #define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK     (0xFF << 3)
 #define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT    3
 
 #define PNX833X_MIU_CONFIG_SPI_OPCODE_MASK     (0xFF << 3)
 #define PNX833X_MIU_CONFIG_SPI_OPCODE_SHIFT    3
 

-#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK        (1 << 2)
+#define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_MASK (1 << 2)

 #define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT       2
 
 #define PNX833X_MIU_CONFIG_SPI_DATA_ENABLE_SHIFT       2
 

-#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK        (1 << 1)
+#define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_MASK (1 << 1)

 #define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT       1
 
 #define PNX833X_MIU_CONFIG_SPI_SYNC_MASK       (1 << 0)
 #define PNX833X_MIU_CONFIG_SPI_ADDR_ENABLE_SHIFT       1
 
 #define PNX833X_MIU_CONFIG_SPI_SYNC_MASK       (1 << 0)

diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h
index c7077a64b9a727acb042b7ea57e7f81a1a03a223..b341108d12f117f7cc6506d7d20f65e9a095cb90 100644 (file)
--- a/arch/mips/include/asm/mach-powertv/asic.h
+++ b/arch/mips/include/asm/mach-powertv/asic.h
@@ -23,9 +23,9 @@
 #include <linux/platform_device.h>
 #include <asm/mach-powertv/asic_regs.h>
 
 #include <linux/platform_device.h>
 #include <asm/mach-powertv/asic_regs.h>
 

-#define DVR_CAPABLE     (1<<0)
-#define PCIE_CAPABLE    (1<<1)
-#define FFS_CAPABLE     (1<<2)
+#define DVR_CAPABLE    (1<<0)
+#define PCIE_CAPABLE   (1<<1)
+#define FFS_CAPABLE    (1<<2)

 #define DISPLAY_CAPABLE (1<<3)
 
 /* Platform Family types
 #define DISPLAY_CAPABLE (1<<3)
 
 /* Platform Family types


@@ -111,7 +111,7 @@ enum sys_reboot_type {
                                         * Older drivers may report as
                                         * userReboot. */
        sys_hardware_reset = 0x09,      /* HW watchdog or front-panel
                                         * Older drivers may report as
                                         * userReboot. */
        sys_hardware_reset = 0x09,      /* HW watchdog or front-panel

-                                        * reset button reset.  Older
+                                        * reset button reset.  Older

                                         * drivers may report as
                                         * userReboot. */
        sys_watchdogInterrupt = 0x0A    /* Pre-watchdog interrupt */
                                         * drivers may report as
                                         * userReboot. */
        sys_watchdogInterrupt = 0x0A    /* Pre-watchdog interrupt */

diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h
index deecb26a077ef82c60a7ea03afcca89454b74341..06712abb3e55ce797b9179b07918718827c5cea1 100644 (file)
--- a/arch/mips/include/asm/mach-powertv/asic_regs.h
+++ b/arch/mips/include/asm/mach-powertv/asic_regs.h
@@ -49,8 +49,8 @@ enum asic_type {
 #define UART1_INTEN    uart1_inten
 #define UART1_CONFIG1  uart1_config1
 #define UART1_CONFIG2  uart1_config2
 #define UART1_INTEN    uart1_inten
 #define UART1_CONFIG1  uart1_config1
 #define UART1_CONFIG2  uart1_config2

-#define UART1_DIVISORHI        uart1_divisorhi
-#define UART1_DIVISORLO        uart1_divisorlo
+#define UART1_DIVISORHI uart1_divisorhi
+#define UART1_DIVISORLO uart1_divisorlo

 #define UART1_DATA     uart1_data
 #define UART1_STATUS   uart1_status
 
 #define UART1_DATA     uart1_data
 #define UART1_STATUS   uart1_status
 

diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h
index 35371641575d3b86c85ac913095b0e6d06f8775d..f8316720a218abb37c76e9db6a39967a5077728b 100644 (file)
--- a/arch/mips/include/asm/mach-powertv/dma-coherence.h
+++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h
@@ -4,7 +4,7 @@
  * for more details.
  *
  * Version from mach-generic modified to support PowerTV port
  * for more details.
  *
  * Version from mach-generic modified to support PowerTV port

- * Portions Copyright (C) 2009  Cisco Systems, Inc.
+ * Portions Copyright (C) 2009 Cisco Systems, Inc.

  * Copyright (C) 2006  Ralf Baechle <ralf@linux-mips.org>
  *
  */
  * Copyright (C) 2006  Ralf Baechle <ralf@linux-mips.org>
  *
  */

diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h
index 4fd652ceb52afc8ebc571a3df39365f5f1f462cf..6c463be621566392f1a612dd1cf619bca3f8a70a 100644 (file)
--- a/arch/mips/include/asm/mach-powertv/interrupts.h
+++ b/arch/mips/include/asm/mach-powertv/interrupts.h
@@ -16,7 +16,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
 

-#ifndef        _ASM_MACH_POWERTV_INTERRUPTS_H_
+#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_

 #define _ASM_MACH_POWERTV_INTERRUPTS_H_
 
 /*
 #define _ASM_MACH_POWERTV_INTERRUPTS_H_
 
 /*


@@ -49,9 +49,9 @@
                                                 * glue logic inside SPARC ILC
                                                 * (see INT_SBAG_STAT, below,
                                                 * for individual interrupts) */
                                                 * glue logic inside SPARC ILC
                                                 * (see INT_SBAG_STAT, below,
                                                 * for individual interrupts) */

-#define irq_qam_b_fec          (ibase+116)     /* QAM  B FEC Interrupt */
+#define irq_qam_b_fec          (ibase+116)     /* QAM  B FEC Interrupt */

 #define irq_qam_a_fec          (ibase+115)     /* QAM A FEC Interrupt */
 #define irq_qam_a_fec          (ibase+115)     /* QAM A FEC Interrupt */

-/* 114 unused  (bit 18) */
+/* 114 unused  (bit 18) */

 #define irq_mailbox            (ibase+113)     /* Mailbox Debug Interrupt  --
                                                 * Ored by glue logic inside
                                                 * SPARC ILC (see
 #define irq_mailbox            (ibase+113)     /* Mailbox Debug Interrupt  --
                                                 * Ored by glue logic inside
                                                 * SPARC ILC (see


@@ -99,9 +99,9 @@
 #define irq_sata1              (ibase+87)      /* SATA 1 Interrupt */
 #define irq_dtcp               (ibase+86)      /* DTCP Interrupt */
 #define irq_pciexp1            (ibase+85)      /* PCI Express 1 Interrupt */
 #define irq_sata1              (ibase+87)      /* SATA 1 Interrupt */
 #define irq_dtcp               (ibase+86)      /* DTCP Interrupt */
 #define irq_pciexp1            (ibase+85)      /* PCI Express 1 Interrupt */

-/* 84 unused   (bit 20) */
-/* 83 unused   (bit 19) */
-/* 82 unused   (bit 18) */
+/* 84 unused   (bit 20) */
+/* 83 unused   (bit 19) */
+/* 82 unused   (bit 18) */

 #define irq_sata2              (ibase+81)      /* SATA2 Interrupt */
 #define irq_uart2              (ibase+80)      /* UART2 Interrupt */
 #define irq_legacy_usb         (ibase+79)      /* Legacy USB Host ISR (1.1
 #define irq_sata2              (ibase+81)      /* SATA2 Interrupt */
 #define irq_uart2              (ibase+80)      /* UART2 Interrupt */
 #define irq_legacy_usb         (ibase+79)      /* Legacy USB Host ISR (1.1


@@ -117,22 +117,22 @@
 #define irq_mod_dma            (ibase+70)      /* Modulator DMA Interrupt */
 #define irq_byte_eng1          (ibase+69)      /* Byte Engine Interrupt [1] */
 #define irq_byte_eng0          (ibase+68)      /* Byte Engine Interrupt [0] */
 #define irq_mod_dma            (ibase+70)      /* Modulator DMA Interrupt */
 #define irq_byte_eng1          (ibase+69)      /* Byte Engine Interrupt [1] */
 #define irq_byte_eng0          (ibase+68)      /* Byte Engine Interrupt [0] */

-/* 67 unused   (bit 03) */
-/* 66 unused   (bit 02) */
-/* 65 unused   (bit 01) */
-/* 64 unused   (bit 00) */
+/* 67 unused   (bit 03) */
+/* 66 unused   (bit 02) */
+/* 65 unused   (bit 01) */
+/* 64 unused   (bit 00) */

 /*------------- Register: int_stat_1 */
 /*------------- Register: int_stat_1 */

-/* 63 unused   (bit 31) */
-/* 62 unused   (bit 30) */
-/* 61 unused   (bit 29) */
-/* 60 unused   (bit 28) */
-/* 59 unused   (bit 27) */
-/* 58 unused   (bit 26) */
-/* 57 unused   (bit 25) */
-/* 56 unused   (bit 24) */
+/* 63 unused   (bit 31) */
+/* 62 unused   (bit 30) */
+/* 61 unused   (bit 29) */
+/* 60 unused   (bit 28) */
+/* 59 unused   (bit 27) */
+/* 58 unused   (bit 26) */
+/* 57 unused   (bit 25) */
+/* 56 unused   (bit 24) */

 #define irq_buf_dma_mem2mem    (ibase+55)      /* BufDMA Memory to Memory
                                                 * Interrupt */
 #define irq_buf_dma_mem2mem    (ibase+55)      /* BufDMA Memory to Memory
                                                 * Interrupt */

-#define irq_buf_dma_usbtransmit        (ibase+54)      /* BufDMA USB Transmit
+#define irq_buf_dma_usbtransmit (ibase+54)     /* BufDMA USB Transmit

                                                 * Interrupt */
 #define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit
                                                 * Interrupt */
                                                 * Interrupt */
 #define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit
                                                 * Interrupt */


@@ -140,7 +140,7 @@
                                                 * Interrupt */
 #define irq_buf_dma_usbrecv    (ibase+51)      /* BufDMA USB Receive
                                                 * Interrupt */
                                                 * Interrupt */
 #define irq_buf_dma_usbrecv    (ibase+51)      /* BufDMA USB Receive
                                                 * Interrupt */

-#define irq_buf_dma_qpskpodrecv        (ibase+50)      /* BufDMA QPSK/POD Receive
+#define irq_buf_dma_qpskpodrecv (ibase+50)     /* BufDMA QPSK/POD Receive

                                                 * Interrupt */
 #define irq_buf_dma_recv_error (ibase+49)      /* BufDMA Receive Error
                                                 * Interrupt */
                                                 * Interrupt */
 #define irq_buf_dma_recv_error (ibase+49)      /* BufDMA Receive Error
                                                 * Interrupt */


@@ -166,7 +166,7 @@
                                                 * Module */
 #define irq_gpio2              (ibase+37)      /* GP I/O IRQ 2 - From GP I/O
                                                 * Module (ABE_intN) */
                                                 * Module */
 #define irq_gpio2              (ibase+37)      /* GP I/O IRQ 2 - From GP I/O
                                                 * Module (ABE_intN) */

-#define irq_pcrcmplt1          (ibase+36)      /* PCR Capture Complete  or
+#define irq_pcrcmplt1          (ibase+36)      /* PCR Capture Complete  or

                                                 * Discontinuity 1 */
 #define irq_pcrcmplt2          (ibase+35)      /* PCR Capture Complete or
                                                 * Discontinuity 2 */
                                                 * Discontinuity 1 */
 #define irq_pcrcmplt2          (ibase+35)      /* PCR Capture Complete or
                                                 * Discontinuity 2 */


@@ -217,18 +217,18 @@
 #define irq_qpsk_hecerr                (ibase+11)      /* QPSK HEC Error Interrupt */
 #define irq_qpsk_crcerr                (ibase+10)      /* QPSK AAL-5 CRC Error
                                                 * Interrupt */
 #define irq_qpsk_hecerr                (ibase+11)      /* QPSK HEC Error Interrupt */
 #define irq_qpsk_crcerr                (ibase+10)      /* QPSK AAL-5 CRC Error
                                                 * Interrupt */

-/* 9 unused    (bit 09) */
-/* 8 unused    (bit 08) */
-#define irq_psicrcerr          (ibase+7)       /* QAM PSI CRC Error
+/* 9 unused    (bit 09) */
+/* 8 unused    (bit 08) */
+#define irq_psicrcerr          (ibase+7)       /* QAM PSI CRC Error

                                                 * Interrupt */
                                                 * Interrupt */

-#define irq_psilength_err      (ibase+6)       /* QAM PSI Length Error
+#define irq_psilength_err      (ibase+6)       /* QAM PSI Length Error

                                                 * Interrupt */
                                                 * Interrupt */

-#define irq_esfforward         (ibase+5)       /* ESF Interrupt Mark From
+#define irq_esfforward         (ibase+5)       /* ESF Interrupt Mark From

                                                 * Forward Path Reference -
                                                 * every 3ms when forward Mbits
                                                 * and forward slot control
                                                 * bytes are updated. */
                                                 * Forward Path Reference -
                                                 * every 3ms when forward Mbits
                                                 * and forward slot control
                                                 * bytes are updated. */

-#define irq_esfreverse         (ibase+4)       /* ESF Interrupt Mark from
+#define irq_esfreverse         (ibase+4)       /* ESF Interrupt Mark from

                                                 * Reverse Path Reference -
                                                 * delayed from forward mark by
                                                 * the ranging delay plus a
                                                 * Reverse Path Reference -
                                                 * delayed from forward mark by
                                                 * the ranging delay plus a


@@ -239,15 +239,15 @@
                                                 * 1.554 M upstream rates and
                                                 * every 6 ms for 256K upstream
                                                 * rate. */
                                                 * 1.554 M upstream rates and
                                                 * every 6 ms for 256K upstream
                                                 * rate. */

-#define irq_aloha_timeout      (ibase+3)       /* Slotted-Aloha timeout on
+#define irq_aloha_timeout      (ibase+3)       /* Slotted-Aloha timeout on

                                                 * Channel 1. */
                                                 * Channel 1. */

-#define irq_reservation                (ibase+2)       /* Partial (or Incremental)
+#define irq_reservation                (ibase+2)       /* Partial (or Incremental)

                                                 * Reservation Message Completed
                                                 * or Slotted aloha verify for
                                                 * channel 1. */
                                                 * Reservation Message Completed
                                                 * or Slotted aloha verify for
                                                 * channel 1. */

-#define irq_aloha3             (ibase+1)       /* Slotted-Aloha Message Verify
+#define irq_aloha3             (ibase+1)       /* Slotted-Aloha Message Verify

                                                 * Interrupt or Reservation
                                                 * increment completed for
                                                 * channel 3. */
                                                 * Interrupt or Reservation
                                                 * increment completed for
                                                 * channel 3. */

-#define irq_mpeg_d             (ibase+0)       /* MPEG Decoder Interrupt */
+#define irq_mpeg_d             (ibase+0)       /* MPEG Decoder Interrupt */

 #endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */
 #endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */

diff --git a/arch/mips/include/asm/mach-rc32434/ddr.h b/arch/mips/include/asm/mach-rc32434/ddr.h
index 291e2cf9dde0b46e8da9c5dd03e382bfd1523a74..e1cad0c7fd52e8370508784648466cb4dd87d812 100644 (file)
--- a/arch/mips/include/asm/mach-rc32434/ddr.h
+++ b/arch/mips/include/asm/mach-rc32434/ddr.h
@@ -138,4 +138,4 @@ struct ddr_ram {
 #define RC32434_DLLED_DBE_BIT          0
 #define RC32434_DLLED_DTE_BIT          1
 
 #define RC32434_DLLED_DBE_BIT          0
 #define RC32434_DLLED_DTE_BIT          1
 

-#endif  /* _ASM_RC32434_DDR_H_ */
+#endif /* _ASM_RC32434_DDR_H_ */

diff --git a/arch/mips/include/asm/mach-rc32434/dma.h b/arch/mips/include/asm/mach-rc32434/dma.h
index 5f898b5873f7c0eea0cfcf25d8b1019ade6a7645..4322191e46bf6639c273b3ed12379c73430adea5 100644 (file)
--- a/arch/mips/include/asm/mach-rc32434/dma.h
+++ b/arch/mips/include/asm/mach-rc32434/dma.h
@@ -5,7 +5,7 @@
  * DMA register definition.
  *
  * Author : ryan.holmQVist@idt.com
  * DMA register definition.
  *
  * Author : ryan.holmQVist@idt.com

- * Date   : 20011005
+ * Date          : 20011005

  */
 
 #ifndef __ASM_RC32434_DMA_H
  */
 
 #ifndef __ASM_RC32434_DMA_H


@@ -71,10 +71,10 @@ struct dma_reg {
 #define DMA_CHAN_DONE_BIT              (1 << 1)
 #define DMA_CHAN_MODE_BIT              (1 << 2)
 #define DMA_CHAN_MODE_MSK              0x0000000c
 #define DMA_CHAN_DONE_BIT              (1 << 1)
 #define DMA_CHAN_MODE_BIT              (1 << 2)
 #define DMA_CHAN_MODE_MSK              0x0000000c

-#define  DMA_CHAN_MODE_AUTO            0
-#define  DMA_CHAN_MODE_BURST           1
-#define  DMA_CHAN_MODE_XFRT            2
-#define  DMA_CHAN_MODE_RSVD            3
+#define         DMA_CHAN_MODE_AUTO             0
+#define         DMA_CHAN_MODE_BURST            1
+#define         DMA_CHAN_MODE_XFRT             2
+#define         DMA_CHAN_MODE_RSVD             3

 #define DMA_CHAN_ACT_BIT               (1 << 4)
 
 /* DMA status registers */
 #define DMA_CHAN_ACT_BIT               (1 << 4)
 
 /* DMA status registers */


@@ -100,4 +100,4 @@ struct dma_channel {
        struct dma_reg ch[DMA_CHAN_COUNT];
 };
 
        struct dma_reg ch[DMA_CHAN_COUNT];
 };
 

-#endif  /* __ASM_RC32434_DMA_H */
+#endif /* __ASM_RC32434_DMA_H */

diff --git a/arch/mips/include/asm/mach-rc32434/dma_v.h b/arch/mips/include/asm/mach-rc32434/dma_v.h
index 173a9f9146cd0263d87124889a84e1ae2a021bcf..28c54063a3451aef86bbec7bd0a166a3c94c07eb 100644 (file)
--- a/arch/mips/include/asm/mach-rc32434/dma_v.h
+++ b/arch/mips/include/asm/mach-rc32434/dma_v.h
@@ -5,7 +5,7 @@
  * DMA register definition.
  *
  * Author : ryan.holmQVist@idt.com
  * DMA register definition.
  *
  * Author : ryan.holmQVist@idt.com

- * Date   : 20011005
+ * Date          : 20011005

  */
 
 #ifndef _ASM_RC32434_DMA_V_H_
  */
 
 #ifndef _ASM_RC32434_DMA_V_H_


@@ -49,4 +49,4 @@ static inline void rc32434_chain_dma(struct dma_reg *ch, u32 dma_addr)
        __raw_writel(dma_addr, &ch->dmandptr);
 }
 
        __raw_writel(dma_addr, &ch->dmandptr);
 }
 

-#endif  /* _ASM_RC32434_DMA_V_H_ */
+#endif /* _ASM_RC32434_DMA_V_H_ */

diff --git a/arch/mips/include/asm/mach-rc32434/eth.h b/arch/mips/include/asm/mach-rc32434/eth.h
index a25cbc56173dc132e73fce07d5490704306c2cd2..c2645faadf57ff880c013c69db61871aca760031 100644 (file)
--- a/arch/mips/include/asm/mach-rc32434/eth.h
+++ b/arch/mips/include/asm/mach-rc32434/eth.h
@@ -26,8 +26,8 @@
  *
  */
 
  *
  */
 

-#ifndef        __ASM_RC32434_ETH_H
-#define        __ASM_RC32434_ETH_H
+#ifndef __ASM_RC32434_ETH_H
+#define __ASM_RC32434_ETH_H

 
 
 #define ETH0_BASE_ADDR         0x18060000
 
 
 #define ETH0_BASE_ADDR         0x18060000


@@ -217,4 +217,4 @@ struct eth_regs {
 #define ETH_TX_LE              (1 << 16)
 #define ETH_TX_CC              0x001E0000
 
 #define ETH_TX_LE              (1 << 16)
 #define ETH_TX_CC              0x001E0000
 

-#endif  /* __ASM_RC32434_ETH_H */
+#endif /* __ASM_RC32434_ETH_H */

diff --git a/arch/mips/include/asm/mach-rc32434/gpio.h b/arch/mips/include/asm/mach-rc32434/gpio.h
index 12ee8d51016010690aa6e03f3be952f77a8751c1..4dee0a34250c39bf86c450aff7a7e7efb8f6fb70 100644 (file)
--- a/arch/mips/include/asm/mach-rc32434/gpio.h
+++ b/arch/mips/include/asm/mach-rc32434/gpio.h
@@ -5,7 +5,7 @@
  * GPIO register definition.
  *
  * Author : ryan.holmQVist@idt.com
  * GPIO register definition.
  *
  * Author : ryan.holmQVist@idt.com

- * Date   : 20011005
+ * Date          : 20011005

  * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
  * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
  */
  * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
  * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
  */


@@ -26,9 +26,9 @@
 #define irq_to_gpio(irq)       (irq - (8 + 4 * 32))
 
 struct rb532_gpio_reg {
 #define irq_to_gpio(irq)       (irq - (8 + 4 * 32))
 
 struct rb532_gpio_reg {

-       u32   gpiofunc;   /* GPIO Function Register
+       u32   gpiofunc;   /* GPIO Function Register

                           * gpiofunc[x]==0 bit = gpio
                           * gpiofunc[x]==0 bit = gpio

-                          * func[x]==1  bit = altfunc
+                          * func[x]==1  bit = altfunc

                           */
        u32   gpiocfg;    /* GPIO Configuration Register
                           * gpiocfg[x]==0 bit = input
                           */
        u32   gpiocfg;    /* GPIO Configuration Register
                           * gpiocfg[x]==0 bit = input

diff --git a/arch/mips/include/asm/mach-rc32434/irq.h b/arch/mips/include/asm/mach-rc32434/irq.h
index 023a5b100ed05d617f24fb2c11fa749384c571bf..b76dec95c04e0d6566cee62938c6b4861e898713 100644 (file)
--- a/arch/mips/include/asm/mach-rc32434/irq.h
+++ b/arch/mips/include/asm/mach-rc32434/irq.h
@@ -1,7 +1,7 @@
 #ifndef __ASM_RC32434_IRQ_H
 #define __ASM_RC32434_IRQ_H
 
 #ifndef __ASM_RC32434_IRQ_H
 #define __ASM_RC32434_IRQ_H
 

-#define NR_IRQS        256
+#define NR_IRQS 256

 
 #include <asm/mach-generic/irq.h>
 #include <asm/mach-rc32434/rb.h>
 
 #include <asm/mach-generic/irq.h>
 #include <asm/mach-rc32434/rb.h>


@@ -25,12 +25,12 @@
 
 #define UART0_IRQ              (GROUP3_IRQ_BASE + 0)
 
 
 #define UART0_IRQ              (GROUP3_IRQ_BASE + 0)
 

-#define ETH0_DMA_RX_IRQ        (GROUP1_IRQ_BASE + 0)
-#define ETH0_DMA_TX_IRQ        (GROUP1_IRQ_BASE + 1)
-#define ETH0_RX_OVR_IRQ        (GROUP3_IRQ_BASE + 9)
-#define ETH0_TX_UND_IRQ        (GROUP3_IRQ_BASE + 10)
+#define ETH0_DMA_RX_IRQ                (GROUP1_IRQ_BASE + 0)
+#define ETH0_DMA_TX_IRQ                (GROUP1_IRQ_BASE + 1)
+#define ETH0_RX_OVR_IRQ                (GROUP3_IRQ_BASE + 9)
+#define ETH0_TX_UND_IRQ                (GROUP3_IRQ_BASE + 10)

 
 #define GPIO_MAPPED_IRQ_BASE   GROUP4_IRQ_BASE
 #define GPIO_MAPPED_IRQ_GROUP  4
 
 
 #define GPIO_MAPPED_IRQ_BASE   GROUP4_IRQ_BASE
 #define GPIO_MAPPED_IRQ_GROUP  4
 

-#endif  /* __ASM_RC32434_IRQ_H */
+#endif /* __ASM_RC32434_IRQ_H */

diff --git a/arch/mips/include/asm/mach-rc32434/pci.h b/arch/mips/include/asm/mach-rc32434/pci.h
index 410638f2af743428448e9cbd83395ddd48b71511..6f40d1515580b0eff73f1b5169393eb0d244bcf8 100644 (file)
--- a/arch/mips/include/asm/mach-rc32434/pci.h
+++ b/arch/mips/include/asm/mach-rc32434/pci.h
@@ -151,11 +151,11 @@ struct pci_msu {
 #define         PCI_CFGA_REG_PBA2      (0x18 >> 2)     /* use PCIPBA_ */
 #define         PCI_CFGA_REG_PBA3      (0x1c >> 2)     /* use PCIPBA_ */
 #define         PCI_CFGA_REG_SUBSYS    (0x2c >> 2)     /* use PCFGSS_ */
 #define         PCI_CFGA_REG_PBA2      (0x18 >> 2)     /* use PCIPBA_ */
 #define         PCI_CFGA_REG_PBA3      (0x1c >> 2)     /* use PCIPBA_ */
 #define         PCI_CFGA_REG_SUBSYS    (0x2c >> 2)     /* use PCFGSS_ */

-#define  PCI_CFGA_REG_3C       (0x3C >> 2)     /* use PCFG3C_ */
+#define         PCI_CFGA_REG_3C        (0x3C >> 2)     /* use PCFG3C_ */

 #define         PCI_CFGA_REG_PBBA0C    (0x44 >> 2)     /* use PCIPBAC_ */
 #define         PCI_CFGA_REG_PBBA0C    (0x44 >> 2)     /* use PCIPBAC_ */

-#define  PCI_CFGA_REG_PBA0M    (0x48 >> 2)
+#define         PCI_CFGA_REG_PBA0M     (0x48 >> 2)

 #define         PCI_CFGA_REG_PBA1C     (0x4c >> 2)     /* use PCIPBAC_ */
 #define         PCI_CFGA_REG_PBA1C     (0x4c >> 2)     /* use PCIPBAC_ */

-#define  PCI_CFGA_REG_PBA1M    (0x50 >> 2)
+#define         PCI_CFGA_REG_PBA1M     (0x50 >> 2)

 #define         PCI_CFGA_REG_PBA2C     (0x54 >> 2)     /* use PCIPBAC_ */
 #define         PCI_CFGA_REG_PBA2M     (0x58 >> 2)
 #define         PCI_CFGA_REG_PBA3C     (0x5c >> 2)     /* use PCIPBAC_ */
 #define         PCI_CFGA_REG_PBA2C     (0x54 >> 2)     /* use PCIPBAC_ */
 #define         PCI_CFGA_REG_PBA2M     (0x58 >> 2)
 #define         PCI_CFGA_REG_PBA3C     (0x5c >> 2)     /* use PCIPBAC_ */


@@ -164,9 +164,9 @@ struct pci_msu {
 #define PCI_CFGA_FUNC_BIT      8
 #define PCI_CFGA_FUNC          0x00000700
 #define PCI_CFGA_DEV_BIT       11
 #define PCI_CFGA_FUNC_BIT      8
 #define PCI_CFGA_FUNC          0x00000700
 #define PCI_CFGA_DEV_BIT       11

-#define        PCI_CFGA_DEV            0x0000f800
-#define        PCI_CFGA_DEV_INTERN     0
-#define        PCI_CFGA_BUS_BIT        16
+#define PCI_CFGA_DEV           0x0000f800
+#define PCI_CFGA_DEV_INTERN    0
+#define PCI_CFGA_BUS_BIT       16

 #define PCI CFGA_BUS           0x00ff0000
 #define PCI_CFGA_BUS_TYPE0     0
 #define PCI_CFGA_EN            (1 << 31)
 #define PCI CFGA_BUS           0x00ff0000
 #define PCI_CFGA_BUS_TYPE0     0
 #define PCI_CFGA_EN            (1 << 31)


@@ -201,13 +201,13 @@ struct pci_msu {
 #define PCI_PBAC_P             (1 << 1)
 #define PCI_PBAC_SIZE_BIT      2
 #define PCI_PBAC_SIZE          0x0000007c
 #define PCI_PBAC_P             (1 << 1)
 #define PCI_PBAC_SIZE_BIT      2
 #define PCI_PBAC_SIZE          0x0000007c

-#define        PCI_PBAC_SB             (1 << 7)
-#define        PCI_PBAC_PP             (1 << 8)
+#define PCI_PBAC_SB            (1 << 7)
+#define PCI_PBAC_PP            (1 << 8)

 #define PCI_PBAC_MR_BIT                9
 #define PCI_PBAC_MR            0x00000600
 #define         PCI_PBAC_MR_RD         0
 #define         PCI_PBAC_MR_RD_LINE    1
 #define PCI_PBAC_MR_BIT                9
 #define PCI_PBAC_MR            0x00000600
 #define         PCI_PBAC_MR_RD         0
 #define         PCI_PBAC_MR_RD_LINE    1

-#define  PCI_PBAC_MR_RD_MULT   2
+#define         PCI_PBAC_MR_RD_MULT    2

 #define PCI_PBAC_MRL           (1 << 11)
 #define PCI_PBAC_MRM           (1 << 12)
 #define PCI_PBAC_TRP           (1 << 13)
 #define PCI_PBAC_MRL           (1 << 11)
 #define PCI_PBAC_MRM           (1 << 12)
 #define PCI_PBAC_TRP           (1 << 13)


@@ -227,14 +227,14 @@ struct pci_msu {
  */
 
 #define PCI_LBAC_MSI           (1 << 0)
  */
 
 #define PCI_LBAC_MSI           (1 << 0)

-#define  PCI_LBAC_MSI_MEM      0
-#define  PCI_LBAC_MSI_IO       1
+#define         PCI_LBAC_MSI_MEM       0
+#define         PCI_LBAC_MSI_IO        1

 #define PCI_LBAC_SIZE_BIT      2
 #define PCI_LBAC_SIZE          0x0000007c
 #define PCI_LBAC_SB            (1 << 7)
 #define PCI_LBAC_RT            (1 << 8)
 #define PCI_LBAC_SIZE_BIT      2
 #define PCI_LBAC_SIZE          0x0000007c
 #define PCI_LBAC_SB            (1 << 7)
 #define PCI_LBAC_RT            (1 << 8)

-#define  PCI_LBAC_RT_NO_PREF   0
-#define  PCI_LBAC_RT_PREF      1
+#define         PCI_LBAC_RT_NO_PREF    0
+#define         PCI_LBAC_RT_PREF       1

 
 /*
  * PCI Local Base Address [0|1|2|3] Mapping Register
 
 /*
  * PCI Local Base Address [0|1|2|3] Mapping Register


@@ -279,16 +279,16 @@ struct pci_msu {
 #define PCI_DMAD_PT            0x00c00000      /* preferred transaction field */
 /* These are for reads (DMA channel 8) */
 #define PCI_DMAD_DEVCMD_MR     0               /* memory read */
 #define PCI_DMAD_PT            0x00c00000      /* preferred transaction field */
 /* These are for reads (DMA channel 8) */
 #define PCI_DMAD_DEVCMD_MR     0               /* memory read */

-#define        PCI_DMAD_DEVCMD_MRL     1               /* memory read line */
-#define        PCI_DMAD_DEVCMD_MRM     2               /* memory read multiple */
-#define        PCI_DMAD_DEVCMD_IOR     3               /* I/O read */
+#define PCI_DMAD_DEVCMD_MRL    1               /* memory read line */
+#define PCI_DMAD_DEVCMD_MRM    2               /* memory read multiple */
+#define PCI_DMAD_DEVCMD_IOR    3               /* I/O read */

 /* These are for writes (DMA channel 9) */
 #define PCI_DMAD_DEVCMD_MW     0               /* memory write */
 /* These are for writes (DMA channel 9) */
 #define PCI_DMAD_DEVCMD_MW     0               /* memory write */

-#define        PCI_DMAD_DEVCMD_MWI     1               /* memory write invalidate */
-#define        PCI_DMAD_DEVCMD_IOW     3               /* I/O write */
+#define PCI_DMAD_DEVCMD_MWI    1               /* memory write invalidate */
+#define PCI_DMAD_DEVCMD_IOW    3               /* I/O write */

 
 /* Swap byte field applies to both DMA channel 8 and 9 */
 
 /* Swap byte field applies to both DMA channel 8 and 9 */

-#define        PCI_DMAD_SB             (1 << 24)       /* swap byte field */
+#define PCI_DMAD_SB            (1 << 24)       /* swap byte field */

 
 
 /*
 
 
 /*


@@ -309,7 +309,7 @@ struct pci_msu {
 #define PCI_MSU_M1             (1 << 1)
 #define PCI_MSU_DB             (1 << 2)
 
 #define PCI_MSU_M1             (1 << 1)
 #define PCI_MSU_DB             (1 << 2)
 

-#define PCI_MSG_ADDR           0xB8088010
+#define PCI_MSG_ADDR           0xB8088010

 #define PCI0_ADDR              0xB8080000
 #define rc32434_pci ((struct pci_reg *) PCI0_ADDR)
 #define rc32434_pci_msg ((struct pci_msu *) PCI_MSG_ADDR)
 #define PCI0_ADDR              0xB8080000
 #define rc32434_pci ((struct pci_reg *) PCI0_ADDR)
 #define rc32434_pci_msg ((struct pci_msu *) PCI_MSG_ADDR)


@@ -331,9 +331,9 @@ struct pci_msu {
 #define PCILBA_SIZE_MASK       0x1F
 #define SIZE_256MB             0x1C
 #define SIZE_128MB             0x1B
 #define PCILBA_SIZE_MASK       0x1F
 #define SIZE_256MB             0x1C
 #define SIZE_128MB             0x1B

-#define SIZE_64MB               0x1A
+#define SIZE_64MB              0x1A

 #define SIZE_32MB              0x19
 #define SIZE_32MB              0x19

-#define SIZE_16MB               0x18
+#define SIZE_16MB              0x18

 #define SIZE_4MB               0x16
 #define SIZE_2MB               0x15
 #define SIZE_1MB               0x14
 #define SIZE_4MB               0x16
 #define SIZE_2MB               0x15
 #define SIZE_1MB               0x14


@@ -363,7 +363,7 @@ struct pci_msu {
 #define KORINA_CONFIG23_ADDR   0x8000005C
 #define KORINA_CONFIG24_ADDR   0x80000060
 #define KORINA_CONFIG25_ADDR   0x80000064
 #define KORINA_CONFIG23_ADDR   0x8000005C
 #define KORINA_CONFIG24_ADDR   0x80000060
 #define KORINA_CONFIG25_ADDR   0x80000064

-#define KORINA_CMD             (PCI_CFG04_CMD_IO_ENA | \
+#define KORINA_CMD             (PCI_CFG04_CMD_IO_ENA | \

                                 PCI_CFG04_CMD_MEM_ENA | \
                                 PCI_CFG04_CMD_BM_ENA | \
                                 PCI_CFG04_CMD_MW_INV | \
                                 PCI_CFG04_CMD_MEM_ENA | \
                                 PCI_CFG04_CMD_BM_ENA | \
                                 PCI_CFG04_CMD_MW_INV | \


@@ -401,8 +401,8 @@ struct pci_msu {
 #define KORINA_BAR3    0x48000008      /* Spare 128 MB Memory */
 
 #define KORINA_CNFG4   KORINA_BAR0
 #define KORINA_BAR3    0x48000008      /* Spare 128 MB Memory */
 
 #define KORINA_CNFG4   KORINA_BAR0

-#define KORINA_CNFG5    KORINA_BAR1
-#define KORINA_CNFG6   KORINA_BAR2
+#define KORINA_CNFG5   KORINA_BAR1
+#define KORINA_CNFG6   KORINA_BAR2

 #define KORINA_CNFG7   KORINA_BAR3
 
 #define KORINA_SUBSYS_VENDOR_ID 0x011d
 #define KORINA_CNFG7   KORINA_BAR3
 
 #define KORINA_SUBSYS_VENDOR_ID 0x011d


@@ -410,20 +410,20 @@ struct pci_msu {
 #define KORINA_CNFG8           0
 #define KORINA_CNFG9           0
 #define KORINA_CNFG10          0
 #define KORINA_CNFG8           0
 #define KORINA_CNFG9           0
 #define KORINA_CNFG10          0

-#define KORINA_CNFG11  ((KORINA_SUBSYS_VENDOR_ID<<16) | \
+#define KORINA_CNFG11  ((KORINA_SUBSYS_VENDOR_ID<<16) | \

                          KORINA_SUBSYSTEM_ID)
 #define KORINA_INT_LINE                1
 #define KORINA_INT_PIN         1
 #define KORINA_MIN_GNT         8
 #define KORINA_MAX_LAT         0x38
 #define KORINA_CNFG12          0
                          KORINA_SUBSYSTEM_ID)
 #define KORINA_INT_LINE                1
 #define KORINA_INT_PIN         1
 #define KORINA_MIN_GNT         8
 #define KORINA_MAX_LAT         0x38
 #define KORINA_CNFG12          0

-#define KORINA_CNFG13          0
+#define KORINA_CNFG13          0

 #define KORINA_CNFG14          0
 #define KORINA_CNFG15  ((KORINA_MAX_LAT<<24) | \
                         (KORINA_MIN_GNT<<16) | \
                         (KORINA_INT_PIN<<8)  | \
                          KORINA_INT_LINE)
 #define KORINA_CNFG14          0
 #define KORINA_CNFG15  ((KORINA_MAX_LAT<<24) | \
                         (KORINA_MIN_GNT<<16) | \
                         (KORINA_INT_PIN<<8)  | \
                          KORINA_INT_LINE)

-#define        KORINA_RETRY_LIMIT      0x80
+#define KORINA_RETRY_LIMIT     0x80

 #define KORINA_TRDY_LIMIT      0x80
 #define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
                        KORINA_TRDY_LIMIT)
 #define KORINA_TRDY_LIMIT      0x80
 #define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
                        KORINA_TRDY_LIMIT)


@@ -475,7 +475,7 @@ struct pci_msu {
 #define KORINA_PBA3M   0
 #define KORINA_CNFG24  KORINA_PBA3M
 
 #define KORINA_PBA3M   0
 #define KORINA_CNFG24  KORINA_PBA3M
 

-#define        PCITC_DTIMER_VAL        8
+#define PCITC_DTIMER_VAL       8

 #define PCITC_RTIMER_VAL       0x10
 
 #define PCITC_RTIMER_VAL       0x10
 

-#endif  /* __ASM_RC32434_PCI_H */
+#endif /* __ASM_RC32434_PCI_H */

diff --git a/arch/mips/include/asm/mach-rc32434/rb.h b/arch/mips/include/asm/mach-rc32434/rb.h
index 6dc5f8df1f3e025f22ac893d44b76a25f0da0d8e..aac8ce8902e728bcb0f47e9be33f55dc14b77779 100644 (file)
--- a/arch/mips/include/asm/mach-rc32434/rb.h
+++ b/arch/mips/include/asm/mach-rc32434/rb.h
@@ -18,7 +18,7 @@
 #include <linux/genhd.h>
 
 #define REGBASE                0x18000000
 #include <linux/genhd.h>
 
 #define REGBASE                0x18000000

-#define IDT434_REG_BASE        ((volatile void *) KSEG1ADDR(REGBASE))
+#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(REGBASE))

 #define UART0BASE      0x58000
 #define RST            (1 << 15)
 #define DEV0BASE       0x010000
 #define UART0BASE      0x58000
 #define RST            (1 << 15)
 #define DEV0BASE       0x010000


@@ -80,10 +80,10 @@ struct cf_device {
 struct mpmc_device {
        unsigned char   state;
        spinlock_t      lock;
 struct mpmc_device {
        unsigned char   state;
        spinlock_t      lock;

-       void __iomem    *base;
+       void __iomem    *base;

 };
 
 extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
 extern unsigned char get_latch_u5(void);
 
 };
 
 extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
 extern unsigned char get_latch_u5(void);
 

-#endif  /* __ASM_RC32434_RB_H */
+#endif /* __ASM_RC32434_RB_H */

diff --git a/arch/mips/include/asm/mach-rc32434/rc32434.h b/arch/mips/include/asm/mach-rc32434/rc32434.h
index fce25d4231fc8f5b8920768ce65bf8980159e5b6..02fd32b4be164e41f9966a1674d7551c830e8fb7 100644 (file)
--- a/arch/mips/include/asm/mach-rc32434/rc32434.h
+++ b/arch/mips/include/asm/mach-rc32434/rc32434.h
@@ -16,4 +16,4 @@ static inline void rc32434_sync(void)
        __asm__ volatile ("sync");
 }
 
        __asm__ volatile ("sync");
 }
 

-#endif  /* _ASM_RC32434_RC32434_H_ */
+#endif /* _ASM_RC32434_RC32434_H_ */

diff --git a/arch/mips/include/asm/mach-rc32434/timer.h b/arch/mips/include/asm/mach-rc32434/timer.h
index e49b1d57a01728ebdc348205dc5cc7fb511565e3..cda26bb9eead52015b182ee793776c21be86ff89 100644 (file)
--- a/arch/mips/include/asm/mach-rc32434/timer.h
+++ b/arch/mips/include/asm/mach-rc32434/timer.h
@@ -51,15 +51,15 @@ struct timer {
 #define RC32434_CTC_TO_BIT             1
 
 /* Real time clock registers */
 #define RC32434_CTC_TO_BIT             1
 
 /* Real time clock registers */

-#define RC32434_RTC_MSK(x)              BIT_TO_MASK(x)
-#define RC32434_RTC_CE_BIT              0
-#define RC32434_RTC_TO_BIT              1
-#define RC32434_RTC_RQE_BIT             2
+#define RC32434_RTC_MSK(x)             BIT_TO_MASK(x)
+#define RC32434_RTC_CE_BIT             0
+#define RC32434_RTC_TO_BIT             1
+#define RC32434_RTC_RQE_BIT            2

 
 /* Counter registers */
 
 /* Counter registers */

-#define RC32434_RCOUNT_BIT              0
-#define RC32434_RCOUNT_MSK              0x0000ffff
-#define RC32434_RCOMP_BIT               0
-#define RC32434_RCOMP_MSK               0x0000ffff
+#define RC32434_RCOUNT_BIT             0
+#define RC32434_RCOUNT_MSK             0x0000ffff
+#define RC32434_RCOMP_BIT              0
+#define RC32434_RCOMP_MSK              0x0000ffff

 
 

-#endif  /* __ASM_RC32434_TIMER_H */
+#endif /* __ASM_RC32434_TIMER_H */

diff --git a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
index 7f3e3f9bd23a0cb8a37d40827d7d918d017aa2fd..d9c82841903775734d6a462de251deaba1058715 100644 (file)
--- a/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-sead3/cpu-feature-overrides.h
@@ -23,8 +23,8 @@
 /* #define cpu_has_watch       ? */
 #define cpu_has_divec          1
 #define cpu_has_vce            0
 /* #define cpu_has_watch       ? */
 #define cpu_has_divec          1
 #define cpu_has_vce            0

-/* #define cpu_has_cache_cdex_p        ? */
-/* #define cpu_has_cache_cdex_s        ? */
+/* #define cpu_has_cache_cdex_p ? */
+/* #define cpu_has_cache_cdex_s ? */

 /* #define cpu_has_prefetch    ? */
 #define cpu_has_mcheck         1
 /* #define cpu_has_ejtag       ? */
 /* #define cpu_has_prefetch    ? */
 #define cpu_has_mcheck         1
 /* #define cpu_has_ejtag       ? */


@@ -53,8 +53,8 @@
 /* #define cpu_has_watch       ? */
 #define cpu_has_divec          1
 #define cpu_has_vce            0
 /* #define cpu_has_watch       ? */
 #define cpu_has_divec          1
 #define cpu_has_vce            0

-/* #define cpu_has_cache_cdex_p        ? */
-/* #define cpu_has_cache_cdex_s        ? */
+/* #define cpu_has_cache_cdex_p ? */
+/* #define cpu_has_cache_cdex_s ? */

 /* #define cpu_has_prefetch    ? */
 #define cpu_has_mcheck         1
 /* #define cpu_has_ejtag       ? */
 /* #define cpu_has_prefetch    ? */
 #define cpu_has_mcheck         1
 /* #define cpu_has_ejtag       ? */

diff --git a/arch/mips/include/asm/mach-sead3/irq.h b/arch/mips/include/asm/mach-sead3/irq.h
index 652ea4c38cdacaaaaf2adb824b87c198a9012830..5d154cfbcf4c73460b4b3b2c972072f0adaaebe6 100644 (file)
--- a/arch/mips/include/asm/mach-sead3/irq.h
+++ b/arch/mips/include/asm/mach-sead3/irq.h
@@ -1,7 +1,7 @@
 #ifndef __ASM_MACH_MIPS_IRQ_H
 #define __ASM_MACH_MIPS_IRQ_H
 
 #ifndef __ASM_MACH_MIPS_IRQ_H
 #define __ASM_MACH_MIPS_IRQ_H
 

-#define NR_IRQS        256
+#define NR_IRQS 256

 
 
 #include_next <irq.h>
 
 
 #include_next <irq.h>

diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index 176f5b32dc69346cfb0d661725e75d29dc599cc9..0a227d426b9cbf5d284e8d523eba1939fd4d9294 100644 (file)
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -21,12 +21,12 @@ extern int sb1250_m3_workaround_needed(void);
 #endif
 
 #define BCM1250_M3_WAR sb1250_m3_workaround_needed()
 #endif
 
 #define BCM1250_M3_WAR sb1250_m3_workaround_needed()

-#define SIBYTE_1956_WAR        1
+#define SIBYTE_1956_WAR 1

 
 #else
 
 #define BCM1250_M3_WAR 0
 
 #else
 
 #define BCM1250_M3_WAR 0

-#define SIBYTE_1956_WAR        0
+#define SIBYTE_1956_WAR 0

 
 #endif
 
 
 #endif
 

diff --git a/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h b/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h
index 83746b84a5ec53c3c2d36a84e3780050fcff7ad2..00fa3684ac9803b6c2559c74001ae950f3f4c2e7 100644 (file)
--- a/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h
+++ b/arch/mips/include/asm/mach-wrppmc/mach-gt64120.h
@@ -1,6 +1,6 @@
 /*
  * This is a direct copy of the ev96100.h file, with a global
 /*
  * This is a direct copy of the ev96100.h file, with a global

- * search and replace.  The numbers are the same.
+ * search and replace. The numbers are the same.

  *
  * The reason I'm duplicating this is so that the 64120/96100
  * defines won't be confusing in the source code.
  *
  * The reason I'm duplicating this is so that the 64120/96100
  * defines won't be confusing in the source code.


@@ -11,11 +11,11 @@
 /*
  * This is the CPU physical memory map of PPMC Board:
  *
 /*
  * This is the CPU physical memory map of PPMC Board:
  *

- *    0x00000000-0x03FFFFFF      - 64MB SDRAM (SCS[0]#)
- *    0x1C000000-0x1C000000      - LED (CS0)
- *    0x1C800000-0x1C800007      - UART 16550 port (CS1)
- *    0x1F000000-0x1F000000      - MailBox (CS3)
- *    0x1FC00000-0x20000000      - 4MB Flash (BOOT CS)
+ *    0x00000000-0x03FFFFFF     - 64MB SDRAM (SCS[0]#)
+ *    0x1C000000-0x1C000000     - LED (CS0)
+ *    0x1C800000-0x1C800007     - UART 16550 port (CS1)
+ *    0x1F000000-0x1F000000     - MailBox (CS3)
+ *    0x1FC00000-0x20000000     - 4MB Flash (BOOT CS)

  */
 
 #define WRPPMC_SDRAM_SCS0_BASE 0x00000000
  */
 
 #define WRPPMC_SDRAM_SCS0_BASE 0x00000000


@@ -39,8 +39,8 @@
  *
  * NOTE: We only have PCI_0 hose interface
  */
  *
  * NOTE: We only have PCI_0 hose interface
  */

-#define GT_PCI_MEM_BASE        0x13000000UL
-#define GT_PCI_MEM_SIZE        0x02000000UL
+#define GT_PCI_MEM_BASE 0x13000000UL
+#define GT_PCI_MEM_SIZE 0x02000000UL

 #define GT_PCI_IO_BASE 0x11000000UL
 #define GT_PCI_IO_SIZE 0x02000000UL
 
 #define GT_PCI_IO_BASE 0x11000000UL
 #define GT_PCI_IO_SIZE 0x02000000UL
 

diff --git a/arch/mips/include/asm/mc146818-time.h b/arch/mips/include/asm/mc146818-time.h
index 4a08dbe37db8b3662261a46c263d97cf511fa3ce..9e1ad26abdc0232482fb39e13e4e688a9487693a 100644 (file)
--- a/arch/mips/include/asm/mc146818-time.h
+++ b/arch/mips/include/asm/mc146818-time.h
@@ -26,7 +26,7 @@
  * MC146818A or Dallas DS12887 data sheet for details.
  *
  * BUG: This routine does not handle hour overflow properly; it just
  * MC146818A or Dallas DS12887 data sheet for details.
  *
  * BUG: This routine does not handle hour overflow properly; it just

- *      sets the minutes. Usually you'll only notice that after reboot!
+ *     sets the minutes. Usually you'll only notice that after reboot!

  */
 static inline int mc146818_set_rtc_mmss(unsigned long nowtime)
 {
  */
 static inline int mc146818_set_rtc_mmss(unsigned long nowtime)
 {


@@ -77,7 +77,7 @@ static inline int mc146818_set_rtc_mmss(unsigned long nowtime)
         * battery and quartz) will not reset the oscillator and will not
         * update precisely 500 ms later. You won't find this mentioned in
         * the Dallas Semiconductor data sheets, but who believes data
         * battery and quartz) will not reset the oscillator and will not
         * update precisely 500 ms later. You won't find this mentioned in
         * the Dallas Semiconductor data sheets, but who believes data

-        * sheets anyway ...                           -- Markus Kuhn
+        * sheets anyway ...                           -- Markus Kuhn

         */
        CMOS_WRITE(save_control, RTC_CONTROL);
        CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
         */
        CMOS_WRITE(save_control, RTC_CONTROL);
        CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);

diff --git a/arch/mips/include/asm/mips-boards/bonito64.h b/arch/mips/include/asm/mips-boards/bonito64.h
index d14e2adc4be5c8d26d42ec9076f690d9f4e1e0a7..b2048d1bcc1cd050ba976ab4999f6b4ebcd7d3ee 100644 (file)
--- a/arch/mips/include/asm/mips-boards/bonito64.h
+++ b/arch/mips/include/asm/mips-boards/bonito64.h
@@ -41,18 +41,18 @@ extern unsigned long _pcictrl_bonito_pcicfg;
 
 #define BONITO_BOOT_BASE               0x1fc00000
 #define BONITO_BOOT_SIZE               0x00100000
 
 #define BONITO_BOOT_BASE               0x1fc00000
 #define BONITO_BOOT_SIZE               0x00100000

-#define BONITO_BOOT_TOP                (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1)
+#define BONITO_BOOT_TOP                        (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1)

 #define BONITO_FLASH_BASE              0x1c000000
 #define BONITO_FLASH_SIZE              0x03000000
 #define BONITO_FLASH_TOP               (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1)
 #define BONITO_SOCKET_BASE             0x1f800000
 #define BONITO_SOCKET_SIZE             0x00400000
 #define BONITO_SOCKET_TOP              (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1)
 #define BONITO_FLASH_BASE              0x1c000000
 #define BONITO_FLASH_SIZE              0x03000000
 #define BONITO_FLASH_TOP               (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1)
 #define BONITO_SOCKET_BASE             0x1f800000
 #define BONITO_SOCKET_SIZE             0x00400000
 #define BONITO_SOCKET_TOP              (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1)

-#define BONITO_REG_BASE                0x1fe00000
-#define BONITO_REG_SIZE                0x00040000
+#define BONITO_REG_BASE                        0x1fe00000
+#define BONITO_REG_SIZE                        0x00040000

 #define BONITO_REG_TOP                 (BONITO_REG_BASE+BONITO_REG_SIZE-1)
 #define BONITO_REG_TOP                 (BONITO_REG_BASE+BONITO_REG_SIZE-1)

-#define BONITO_DEV_BASE                0x1ff00000
-#define BONITO_DEV_SIZE                0x00100000
+#define BONITO_DEV_BASE                        0x1ff00000
+#define BONITO_DEV_SIZE                        0x00100000

 #define BONITO_DEV_TOP                 (BONITO_DEV_BASE+BONITO_DEV_SIZE-1)
 #define BONITO_PCILO_BASE              0x10000000
 #define BONITO_PCILO_SIZE              0x0c000000
 #define BONITO_DEV_TOP                 (BONITO_DEV_BASE+BONITO_DEV_SIZE-1)
 #define BONITO_PCILO_BASE              0x10000000
 #define BONITO_PCILO_SIZE              0x0c000000


@@ -79,14 +79,14 @@ extern unsigned long _pcictrl_bonito_pcicfg;
 
 /* PCI Configuration  Registers */
 
 
 /* PCI Configuration  Registers */
 

-#define BONITO_PCI_REG(x)               BONITO(BONITO_PCICONFIGBASE + (x))
+#define BONITO_PCI_REG(x)              BONITO(BONITO_PCICONFIGBASE + (x))

 #define BONITO_PCIDID                  BONITO_PCI_REG(0x00)
 #define BONITO_PCICMD                  BONITO_PCI_REG(0x04)
 #define BONITO_PCIDID                  BONITO_PCI_REG(0x00)
 #define BONITO_PCICMD                  BONITO_PCI_REG(0x04)

-#define BONITO_PCICLASS                BONITO_PCI_REG(0x08)
+#define BONITO_PCICLASS                        BONITO_PCI_REG(0x08)

 #define BONITO_PCILTIMER               BONITO_PCI_REG(0x0c)
 #define BONITO_PCILTIMER               BONITO_PCI_REG(0x0c)

-#define BONITO_PCIBASE0                BONITO_PCI_REG(0x10)
-#define BONITO_PCIBASE1                BONITO_PCI_REG(0x14)
-#define BONITO_PCIBASE2                BONITO_PCI_REG(0x18)
+#define BONITO_PCIBASE0                        BONITO_PCI_REG(0x10)
+#define BONITO_PCIBASE1                        BONITO_PCI_REG(0x14)
+#define BONITO_PCIBASE2                        BONITO_PCI_REG(0x18)

 #define BONITO_PCIEXPRBASE             BONITO_PCI_REG(0x30)
 #define BONITO_PCIINT                  BONITO_PCI_REG(0x3c)
 
 #define BONITO_PCIEXPRBASE             BONITO_PCI_REG(0x30)
 #define BONITO_PCIINT                  BONITO_PCI_REG(0x3c)
 


@@ -95,7 +95,7 @@ extern unsigned long _pcictrl_bonito_pcicfg;
 #define BONITO_PCICMD_MABORT_CLR       0x20000000
 #define BONITO_PCICMD_MTABORT_CLR      0x10000000
 #define BONITO_PCICMD_TABORT_CLR       0x08000000
 #define BONITO_PCICMD_MABORT_CLR       0x20000000
 #define BONITO_PCICMD_MTABORT_CLR      0x10000000
 #define BONITO_PCICMD_TABORT_CLR       0x08000000

-#define BONITO_PCICMD_MPERR_CLR        0x01000000
+#define BONITO_PCICMD_MPERR_CLR                0x01000000

 #define BONITO_PCICMD_PERRRESPEN       0x00000040
 #define BONITO_PCICMD_ASTEPEN          0x00000080
 #define BONITO_PCICMD_SERREN           0x00000100
 #define BONITO_PCICMD_PERRRESPEN       0x00000040
 #define BONITO_PCICMD_ASTEPEN          0x00000080
 #define BONITO_PCICMD_SERREN           0x00000100


@@ -139,7 +139,7 @@ extern unsigned long _pcictrl_bonito_pcicfg;
 
 /* Other Bonito configuration */
 
 
 /* Other Bonito configuration */
 

-#define BONITO_BONGENCFG_OFFSET         0x4
+#define BONITO_BONGENCFG_OFFSET                0x4

 #define BONITO_BONGENCFG               BONITO(BONITO_REGBASE + BONITO_BONGENCFG_OFFSET)
 
 #define BONITO_BONGENCFG_DEBUGMODE     0x00000001
 #define BONITO_BONGENCFG               BONITO(BONITO_REGBASE + BONITO_BONGENCFG_OFFSET)
 
 #define BONITO_BONGENCFG_DEBUGMODE     0x00000001


@@ -165,7 +165,7 @@ extern unsigned long _pcictrl_bonito_pcicfg;
 
 /* 2. IO & IDE configuration */
 
 
 /* 2. IO & IDE configuration */
 

-#define BONITO_IODEVCFG                BONITO(BONITO_REGBASE + 0x08)
+#define BONITO_IODEVCFG                        BONITO(BONITO_REGBASE + 0x08)

 
 /* 3. IO & IDE configuration */
 
 
 /* 3. IO & IDE configuration */
 


@@ -181,33 +181,33 @@ extern unsigned long _pcictrl_bonito_pcicfg;
 
 /* GPIO Regs - r/w */
 
 
 /* GPIO Regs - r/w */
 

-#define BONITO_GPIODATA_OFFSET          0x1c
-#define BONITO_GPIODATA                BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET)
+#define BONITO_GPIODATA_OFFSET         0x1c
+#define BONITO_GPIODATA                        BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET)

 #define BONITO_GPIOIE                  BONITO(BONITO_REGBASE + 0x20)
 
 /* ICU Configuration Regs - r/w */
 
 #define BONITO_INTEDGE                 BONITO(BONITO_REGBASE + 0x24)
 #define BONITO_GPIOIE                  BONITO(BONITO_REGBASE + 0x20)
 
 /* ICU Configuration Regs - r/w */
 
 #define BONITO_INTEDGE                 BONITO(BONITO_REGBASE + 0x24)

-#define BONITO_INTSTEER                BONITO(BONITO_REGBASE + 0x28)
+#define BONITO_INTSTEER                        BONITO(BONITO_REGBASE + 0x28)

 #define BONITO_INTPOL                  BONITO(BONITO_REGBASE + 0x2c)
 
 /* ICU Enable Regs - IntEn & IntISR are r/o. */
 
 #define BONITO_INTPOL                  BONITO(BONITO_REGBASE + 0x2c)
 
 /* ICU Enable Regs - IntEn & IntISR are r/o. */
 

-#define BONITO_INTENSET                BONITO(BONITO_REGBASE + 0x30)
-#define BONITO_INTENCLR                BONITO(BONITO_REGBASE + 0x34)
+#define BONITO_INTENSET                        BONITO(BONITO_REGBASE + 0x30)
+#define BONITO_INTENCLR                        BONITO(BONITO_REGBASE + 0x34)

 #define BONITO_INTEN                   BONITO(BONITO_REGBASE + 0x38)
 #define BONITO_INTISR                  BONITO(BONITO_REGBASE + 0x3c)
 
 /* PCI mail boxes */
 
 #define BONITO_INTEN                   BONITO(BONITO_REGBASE + 0x38)
 #define BONITO_INTISR                  BONITO(BONITO_REGBASE + 0x3c)
 
 /* PCI mail boxes */
 

-#define BONITO_PCIMAIL0_OFFSET          0x40
-#define BONITO_PCIMAIL1_OFFSET          0x44
-#define BONITO_PCIMAIL2_OFFSET          0x48
-#define BONITO_PCIMAIL3_OFFSET          0x4c
-#define BONITO_PCIMAIL0                BONITO(BONITO_REGBASE + 0x40)
-#define BONITO_PCIMAIL1                BONITO(BONITO_REGBASE + 0x44)
-#define BONITO_PCIMAIL2                BONITO(BONITO_REGBASE + 0x48)
-#define BONITO_PCIMAIL3                BONITO(BONITO_REGBASE + 0x4c)
+#define BONITO_PCIMAIL0_OFFSET         0x40
+#define BONITO_PCIMAIL1_OFFSET         0x44
+#define BONITO_PCIMAIL2_OFFSET         0x48
+#define BONITO_PCIMAIL3_OFFSET         0x4c
+#define BONITO_PCIMAIL0                        BONITO(BONITO_REGBASE + 0x40)
+#define BONITO_PCIMAIL1                        BONITO(BONITO_REGBASE + 0x44)
+#define BONITO_PCIMAIL2                        BONITO(BONITO_REGBASE + 0x48)
+#define BONITO_PCIMAIL3                        BONITO(BONITO_REGBASE + 0x4c)

 
 
 /* 6. PCI cache */
 
 
 /* 6. PCI cache */


@@ -216,7 +216,7 @@ extern unsigned long _pcictrl_bonito_pcicfg;
 #define BONITO_PCICACHETAG             BONITO(BONITO_REGBASE + 0x54)
 
 #define BONITO_PCIBADADDR              BONITO(BONITO_REGBASE + 0x58)
 #define BONITO_PCICACHETAG             BONITO(BONITO_REGBASE + 0x54)
 
 #define BONITO_PCIBADADDR              BONITO(BONITO_REGBASE + 0x58)

-#define BONITO_PCIMSTAT                BONITO(BONITO_REGBASE + 0x5c)
+#define BONITO_PCIMSTAT                        BONITO(BONITO_REGBASE + 0x5c)

 
 
 /*
 
 
 /*


@@ -228,20 +228,20 @@ extern unsigned long _pcictrl_bonito_pcicfg;
 
 #define BONITO_CONFIGBASE              0x000
 #define BONITO_BONITOBASE              0x100
 
 #define BONITO_CONFIGBASE              0x000
 #define BONITO_BONITOBASE              0x100

-#define BONITO_LDMABASE                0x200
+#define BONITO_LDMABASE                        0x200

 #define BONITO_COPBASE                 0x300
 #define BONITO_REG_BLOCKMASK           0x300
 
 #define BONITO_COPBASE                 0x300
 #define BONITO_REG_BLOCKMASK           0x300
 

-#define BONITO_LDMACTRL                BONITO(BONITO_LDMABASE + 0x0)
-#define BONITO_LDMASTAT                BONITO(BONITO_LDMABASE + 0x0)
-#define BONITO_LDMAADDR                BONITO(BONITO_LDMABASE + 0x4)
+#define BONITO_LDMACTRL                        BONITO(BONITO_LDMABASE + 0x0)
+#define BONITO_LDMASTAT                        BONITO(BONITO_LDMABASE + 0x0)
+#define BONITO_LDMAADDR                        BONITO(BONITO_LDMABASE + 0x4)

 #define BONITO_LDMAGO                  BONITO(BONITO_LDMABASE + 0x8)
 #define BONITO_LDMAGO                  BONITO(BONITO_LDMABASE + 0x8)

-#define BONITO_LDMADATA                BONITO(BONITO_LDMABASE + 0xc)
+#define BONITO_LDMADATA                        BONITO(BONITO_LDMABASE + 0xc)

 
 #define BONITO_COPCTRL                 BONITO(BONITO_COPBASE + 0x0)
 #define BONITO_COPSTAT                 BONITO(BONITO_COPBASE + 0x0)
 
 #define BONITO_COPCTRL                 BONITO(BONITO_COPBASE + 0x0)
 #define BONITO_COPSTAT                 BONITO(BONITO_COPBASE + 0x0)

-#define BONITO_COPPADDR                BONITO(BONITO_COPBASE + 0x4)
-#define BONITO_COPDADDR                BONITO(BONITO_COPBASE + 0x8)
+#define BONITO_COPPADDR                        BONITO(BONITO_COPBASE + 0x4)
+#define BONITO_COPDADDR                        BONITO(BONITO_COPBASE + 0x8)

 #define BONITO_COPGO                   BONITO(BONITO_COPBASE + 0xc)
 
 
 #define BONITO_COPGO                   BONITO(BONITO_COPBASE + 0xc)
 
 


@@ -257,7 +257,7 @@ extern unsigned long _pcictrl_bonito_pcicfg;
 #define BONITO_IDECOPGO_DMA_SIZE_SHIFT 0
 #define BONITO_IDECOPGO_DMA_WRITE      0x00010000
 #define BONITO_IDECOPGO_DMAWCOUNT      0x000f0000
 #define BONITO_IDECOPGO_DMA_SIZE_SHIFT 0
 #define BONITO_IDECOPGO_DMA_WRITE      0x00010000
 #define BONITO_IDECOPGO_DMAWCOUNT      0x000f0000

-#define BONITO_IDECOPGO_DMAWCOUNT_SHIFT        16
+#define BONITO_IDECOPGO_DMAWCOUNT_SHIFT 16

 
 #define BONITO_IDECOPCTRL_DMA_STARTBIT 0x80000000
 #define BONITO_IDECOPCTRL_DMA_RSTBIT   0x40000000
 
 #define BONITO_IDECOPCTRL_DMA_STARTBIT 0x80000000
 #define BONITO_IDECOPCTRL_DMA_RSTBIT   0x40000000


@@ -291,11 +291,11 @@ extern unsigned long _pcictrl_bonito_pcicfg;
 #define BONITO_SDCFG_DRAMMODESET       0x00200000
 /* --- */
 #define BONITO_SDCFG_DRAMEXTREGS       0x00400000
 #define BONITO_SDCFG_DRAMMODESET       0x00200000
 /* --- */
 #define BONITO_SDCFG_DRAMEXTREGS       0x00400000

-#define BONITO_SDCFG_DRAMPARITY        0x00800000
+#define BONITO_SDCFG_DRAMPARITY                0x00800000

 /* Added by RPF 11-9-00 */
 /* Added by RPF 11-9-00 */

-#define BONITO_SDCFG_DRAMBURSTLEN      0x03000000
-#define BONITO_SDCFG_DRAMBURSTLEN_SHIFT        24
-#define BONITO_SDCFG_DRAMMODESET_DONE  0x80000000
+#define BONITO_SDCFG_DRAMBURSTLEN      0x03000000
+#define BONITO_SDCFG_DRAMBURSTLEN_SHIFT 24
+#define BONITO_SDCFG_DRAMMODESET_DONE  0x80000000

 /* --- */
 
 /* PCI Cache - pciCacheCtrl */
 /* --- */
 
 /* PCI Cache - pciCacheCtrl */


@@ -308,7 +308,7 @@ extern unsigned long _pcictrl_bonito_pcicfg;
 
 #define BONITO_PCICACHECTRL_IOBCCOH_PRES       0x00000100
 #define BONITO_PCICACHECTRL_IOBCCOH_EN 0x00000200
 
 #define BONITO_PCICACHECTRL_IOBCCOH_PRES       0x00000100
 #define BONITO_PCICACHECTRL_IOBCCOH_EN 0x00000200

-#define BONITO_PCICACHECTRL_CPUCOH_PRES        0x00000400
+#define BONITO_PCICACHECTRL_CPUCOH_PRES 0x00000400

 #define BONITO_PCICACHECTRL_CPUCOH_EN  0x00000800
 
 #define BONITO_IODEVCFG_BUFFBIT_CS0    0x00000001
 #define BONITO_PCICACHECTRL_CPUCOH_EN  0x00000800
 
 #define BONITO_IODEVCFG_BUFFBIT_CS0    0x00000001


@@ -343,18 +343,18 @@ extern unsigned long _pcictrl_bonito_pcicfg;
 
 /* gpio */
 #define BONITO_GPIO_GPIOW              0x000003ff
 
 /* gpio */
 #define BONITO_GPIO_GPIOW              0x000003ff

-#define BONITO_GPIO_GPIOW_SHIFT        0
+#define BONITO_GPIO_GPIOW_SHIFT                0

 #define BONITO_GPIO_GPIOR              0x01ff0000
 #define BONITO_GPIO_GPIOR              0x01ff0000

-#define BONITO_GPIO_GPIOR_SHIFT        16
+#define BONITO_GPIO_GPIOR_SHIFT                16

 #define BONITO_GPIO_GPINR              0xfe000000
 #define BONITO_GPIO_GPINR              0xfe000000

-#define BONITO_GPIO_GPINR_SHIFT        25
+#define BONITO_GPIO_GPINR_SHIFT                25

 #define BONITO_GPIO_IOW(N)             (1<<(BONITO_GPIO_GPIOW_SHIFT+(N)))
 #define BONITO_GPIO_IOR(N)             (1<<(BONITO_GPIO_GPIOR_SHIFT+(N)))
 #define BONITO_GPIO_INR(N)             (1<<(BONITO_GPIO_GPINR_SHIFT+(N)))
 
 /* ICU */
 #define BONITO_ICU_MBOXES              0x0000000f
 #define BONITO_GPIO_IOW(N)             (1<<(BONITO_GPIO_GPIOW_SHIFT+(N)))
 #define BONITO_GPIO_IOR(N)             (1<<(BONITO_GPIO_GPIOR_SHIFT+(N)))
 #define BONITO_GPIO_INR(N)             (1<<(BONITO_GPIO_GPINR_SHIFT+(N)))
 
 /* ICU */
 #define BONITO_ICU_MBOXES              0x0000000f

-#define BONITO_ICU_MBOXES_SHIFT        0
+#define BONITO_ICU_MBOXES_SHIFT                0

 #define BONITO_ICU_DMARDY              0x00000010
 #define BONITO_ICU_DMAEMPTY            0x00000020
 #define BONITO_ICU_COPYRDY             0x00000040
 #define BONITO_ICU_DMARDY              0x00000010
 #define BONITO_ICU_DMAEMPTY            0x00000020
 #define BONITO_ICU_COPYRDY             0x00000040


@@ -384,13 +384,13 @@ extern unsigned long _pcictrl_bonito_pcicfg;
 #define BONITO_PCIMAP_PCIMAP_2         0x00040000
 #define BONITO_PCIMAP_WIN(WIN, ADDR)   ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
 
 #define BONITO_PCIMAP_PCIMAP_2         0x00040000
 #define BONITO_PCIMAP_WIN(WIN, ADDR)   ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
 

-#define BONITO_PCIMAP_WINSIZE           (1<<26)
+#define BONITO_PCIMAP_WINSIZE          (1<<26)

 #define BONITO_PCIMAP_WINOFFSET(ADDR)  ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1))
 #define BONITO_PCIMAP_WINBASE(ADDR)    ((ADDR) << 26)
 
 /* pcimembaseCfg */
 
 #define BONITO_PCIMAP_WINOFFSET(ADDR)  ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1))
 #define BONITO_PCIMAP_WINBASE(ADDR)    ((ADDR) << 26)
 
 /* pcimembaseCfg */
 

-#define BONITO_PCIMEMBASECFG_MASK               0xf0000000
+#define BONITO_PCIMEMBASECFG_MASK              0xf0000000

 #define BONITO_PCIMEMBASECFG_MEMBASE0_MASK     0x0000001f
 #define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT       0
 #define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS    0x000003e0
 #define BONITO_PCIMEMBASECFG_MEMBASE0_MASK     0x0000001f
 #define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT       0
 #define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS    0x000003e0


@@ -406,21 +406,21 @@ extern unsigned long _pcictrl_bonito_pcicfg;
 #define BONITO_PCIMEMBASECFG_MEMBASE1_IO       0x00800000
 
 #define BONITO_PCIMEMBASECFG_ASHIFT    23
 #define BONITO_PCIMEMBASECFG_MEMBASE1_IO       0x00800000
 
 #define BONITO_PCIMEMBASECFG_ASHIFT    23

-#define BONITO_PCIMEMBASECFG_AMASK              0x007fffff
+#define BONITO_PCIMEMBASECFG_AMASK             0x007fffff

 #define BONITO_PCIMEMBASECFGSIZE(WIN, SIZE)    (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)
 #define BONITO_PCIMEMBASECFGBASE(WIN, BASE)    (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS)
 
 #define BONITO_PCIMEMBASECFG_SIZE(WIN, CFG)  (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK)
 
 
 #define BONITO_PCIMEMBASECFGSIZE(WIN, SIZE)    (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)
 #define BONITO_PCIMEMBASECFGBASE(WIN, BASE)    (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS)
 
 #define BONITO_PCIMEMBASECFG_SIZE(WIN, CFG)  (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK)
 
 

-#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)  ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
-#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)  ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
+#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)         ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
+#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)         ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)

 #define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
 
 #define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
 

-#define BONITO_PCITOPHYS(WIN, ADDR, CFG)          ( \
-                                                  (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)))) | \
-                                                  (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG)) \
-                                                )
+#define BONITO_PCITOPHYS(WIN, ADDR, CFG)         ( \
+                                                 (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)))) | \
+                                                 (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG)) \
+                                               )

 
 /* PCICmd */
 
 
 /* PCICmd */
 

diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h
index c01e286394da0c002ce3eec49f21158a0c791cdb..1465b1193b12055c9cbe9770b29cbc3357b323ea 100644 (file)
--- a/arch/mips/include/asm/mips-boards/generic.h
+++ b/arch/mips/include/asm/mips-boards/generic.h
@@ -27,39 +27,39 @@
 /*
  * Display register base.
  */
 /*
  * Display register base.
  */

-#define ASCII_DISPLAY_WORD_BASE    0x1f000410
-#define ASCII_DISPLAY_POS_BASE     0x1f000418
+#define ASCII_DISPLAY_WORD_BASE           0x1f000410
+#define ASCII_DISPLAY_POS_BASE    0x1f000418

 
 
 /*
  * Yamon Prom print address.
  */
 
 
 /*
  * Yamon Prom print address.
  */

-#define YAMON_PROM_PRINT_ADDR      0x1fc00504
+#define YAMON_PROM_PRINT_ADDR     0x1fc00504

 
 
 /*
  * Reset register.
  */
 
 
 /*
  * Reset register.
  */

-#define SOFTRES_REG       0x1f000500
-#define GORESET           0x42
+#define SOFTRES_REG      0x1f000500
+#define GORESET                  0x42

 
 /*
  * Revision register.
  */
 
 /*
  * Revision register.
  */

-#define MIPS_REVISION_REG                  0x1fc00010
-#define MIPS_REVISION_CORID_QED_RM5261     0
-#define MIPS_REVISION_CORID_CORE_LV        1
-#define MIPS_REVISION_CORID_BONITO64       2
-#define MIPS_REVISION_CORID_CORE_20K       3
-#define MIPS_REVISION_CORID_CORE_FPGA      4
-#define MIPS_REVISION_CORID_CORE_MSC       5
-#define MIPS_REVISION_CORID_CORE_EMUL      6
-#define MIPS_REVISION_CORID_CORE_FPGA2     7
-#define MIPS_REVISION_CORID_CORE_FPGAR2    8
-#define MIPS_REVISION_CORID_CORE_FPGA3     9
-#define MIPS_REVISION_CORID_CORE_24K       10
-#define MIPS_REVISION_CORID_CORE_FPGA4     11
-#define MIPS_REVISION_CORID_CORE_FPGA5     12
+#define MIPS_REVISION_REG                 0x1fc00010
+#define MIPS_REVISION_CORID_QED_RM5261    0
+#define MIPS_REVISION_CORID_CORE_LV       1
+#define MIPS_REVISION_CORID_BONITO64      2
+#define MIPS_REVISION_CORID_CORE_20K      3
+#define MIPS_REVISION_CORID_CORE_FPGA     4
+#define MIPS_REVISION_CORID_CORE_MSC      5
+#define MIPS_REVISION_CORID_CORE_EMUL     6
+#define MIPS_REVISION_CORID_CORE_FPGA2    7
+#define MIPS_REVISION_CORID_CORE_FPGAR2           8
+#define MIPS_REVISION_CORID_CORE_FPGA3    9
+#define MIPS_REVISION_CORID_CORE_24K      10
+#define MIPS_REVISION_CORID_CORE_FPGA4    11
+#define MIPS_REVISION_CORID_CORE_FPGA5    12

 
 /**** Artificial corid defines ****/
 /*
 
 /**** Artificial corid defines ****/
 /*


@@ -97,4 +97,4 @@ extern void mips_pcibios_init(void);
 #define mips_pcibios_init() do { } while (0)
 #endif
 
 #define mips_pcibios_init() do { } while (0)
 #endif
 

-#endif  /* __ASM_MIPS_BOARDS_GENERIC_H */
+#endif /* __ASM_MIPS_BOARDS_GENERIC_H */

diff --git a/arch/mips/include/asm/mips-boards/launch.h b/arch/mips/include/asm/mips-boards/launch.h
index d8ae7f95a522b0bcc221e841cd1e6a9233a3944f..653477e4074d67a01d8899d26aecc9da3c997672 100644 (file)
--- a/arch/mips/include/asm/mips-boards/launch.h
+++ b/arch/mips/include/asm/mips-boards/launch.h
@@ -16,11 +16,11 @@ struct cpulaunch {
 #else
 
 #define LOG2CPULAUNCH  5
 #else
 
 #define LOG2CPULAUNCH  5

-#define        LAUNCH_PC       0
-#define        LAUNCH_GP       4
-#define        LAUNCH_SP       8
-#define        LAUNCH_A0       12
-#define        LAUNCH_FLAGS    28
+#define LAUNCH_PC      0
+#define LAUNCH_GP      4
+#define LAUNCH_SP      8
+#define LAUNCH_A0      12
+#define LAUNCH_FLAGS   28

 
 #endif
 
 
 #endif
 

diff --git a/arch/mips/include/asm/mips-boards/malta.h b/arch/mips/include/asm/mips-boards/malta.h
index c1891578fa65893bf423a2e2e841f5dbf4c1c315..722bc889eab555dfc29d2c30dbb01642df8119bb 100644 (file)
--- a/arch/mips/include/asm/mips-boards/malta.h
+++ b/arch/mips/include/asm/mips-boards/malta.h
@@ -33,9 +33,9 @@
  * Malta I/O ports base address for the Galileo GT64120 and Algorithmics
  * Bonito system controllers.
  */
  * Malta I/O ports base address for the Galileo GT64120 and Algorithmics
  * Bonito system controllers.
  */

-#define MALTA_GT_PORT_BASE      get_gt_port_base(GT_PCI0IOLD_OFS)
-#define MALTA_BONITO_PORT_BASE  ((unsigned long)ioremap (0x1fd00000, 0x10000))
-#define MALTA_MSC_PORT_BASE     get_msc_port_base(MSC01_PCI_SC2PIOBASL)
+#define MALTA_GT_PORT_BASE     get_gt_port_base(GT_PCI0IOLD_OFS)
+#define MALTA_BONITO_PORT_BASE ((unsigned long)ioremap (0x1fd00000, 0x10000))
+#define MALTA_MSC_PORT_BASE    get_msc_port_base(MSC01_PCI_SC2PIOBASL)

 
 static inline unsigned long get_gt_port_base(unsigned long reg)
 {
 
 static inline unsigned long get_gt_port_base(unsigned long reg)
 {


@@ -77,8 +77,8 @@ static inline unsigned long get_msc_port_base(unsigned long reg)
 /*
  * Malta RTC-device indirect register access.
  */
 /*
  * Malta RTC-device indirect register access.
  */

-#define MALTA_RTC_ADR_REG       0x70
-#define MALTA_RTC_DAT_REG       0x71
+#define MALTA_RTC_ADR_REG      0x70
+#define MALTA_RTC_DAT_REG      0x71

 
 /*
  * Malta SMSC FDC37M817 Super I/O Controller register.
 
 /*
  * Malta SMSC FDC37M817 Super I/O Controller register.

diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h
index 6692448157539ee17182ada478beb65320c69f9e..e330732ddf9817211b016dc605d1f0ace87386ff 100644 (file)
--- a/arch/mips/include/asm/mips-boards/maltaint.h
+++ b/arch/mips/include/asm/mips-boards/maltaint.h
@@ -4,8 +4,8 @@
  * for more details.
  *
  * Copyright (C) 2000,2012 MIPS Technologies, Inc.  All rights reserved.
  * for more details.
  *
  * Copyright (C) 2000,2012 MIPS Technologies, Inc.  All rights reserved.

- *      Carsten Langgaard <carstenl@mips.com>
- *      Steven J. Hill <sjhill@mips.com>
+ *     Carsten Langgaard <carstenl@mips.com>
+ *     Steven J. Hill <sjhill@mips.com>

  */
 #ifndef _MIPS_MALTAINT_H
 #define _MIPS_MALTAINT_H
  */
 #ifndef _MIPS_MALTAINT_H
 #define _MIPS_MALTAINT_H


@@ -24,9 +24,9 @@
 #define MIPSCPU_INT_I8259A     MIPSCPU_INT_MB0
 #define MIPSCPU_INT_MB1                3
 #define MIPSCPU_INT_SMI                MIPSCPU_INT_MB1
 #define MIPSCPU_INT_I8259A     MIPSCPU_INT_MB0
 #define MIPSCPU_INT_MB1                3
 #define MIPSCPU_INT_SMI                MIPSCPU_INT_MB1

-#define MIPSCPU_INT_IPI0       MIPSCPU_INT_MB1 /* GIC IPI */
+#define MIPSCPU_INT_IPI0       MIPSCPU_INT_MB1 /* GIC IPI */

 #define MIPSCPU_INT_MB2                4
 #define MIPSCPU_INT_MB2                4

-#define MIPSCPU_INT_IPI1       MIPSCPU_INT_MB2 /* GIC IPI */
+#define MIPSCPU_INT_IPI1       MIPSCPU_INT_MB2 /* GIC IPI */

 #define MIPSCPU_INT_MB3                5
 #define MIPSCPU_INT_COREHI     MIPSCPU_INT_MB3
 #define MIPSCPU_INT_MB4                6
 #define MIPSCPU_INT_MB3                5
 #define MIPSCPU_INT_COREHI     MIPSCPU_INT_MB3
 #define MIPSCPU_INT_MB4                6

diff --git a/arch/mips/include/asm/mips-boards/piix4.h b/arch/mips/include/asm/mips-boards/piix4.h
index 2971d60f2e95c188fbd9987bfe0fa6752d6b33c3..a02596cf1abd418a80653b5ef36bdda6cbbb4bbd 100644 (file)
--- a/arch/mips/include/asm/mips-boards/piix4.h
+++ b/arch/mips/include/asm/mips-boards/piix4.h
@@ -53,7 +53,7 @@
 #define PIIX4_OCW2_SP          (0x6 << 5)
 #define PIIX4_OCW2_NOP         (0x2 << 5)
 
 #define PIIX4_OCW2_SP          (0x6 << 5)
 #define PIIX4_OCW2_NOP         (0x2 << 5)
 

-#define PIIX4_OCW2_SEL          (0x0 << 3)
+#define PIIX4_OCW2_SEL         (0x0 << 3)

 
 #define PIIX4_OCW2_ILS_0       0
 #define PIIX4_OCW2_ILS_1       1
 
 #define PIIX4_OCW2_ILS_0       0
 #define PIIX4_OCW2_ILS_1       1


@@ -72,9 +72,9 @@
 #define PIIX4_OCW2_ILS_14      6
 #define PIIX4_OCW2_ILS_15      7
 
 #define PIIX4_OCW2_ILS_14      6
 #define PIIX4_OCW2_ILS_15      7
 

-#define PIIX4_OCW3_SEL          (0x1 << 3)
+#define PIIX4_OCW3_SEL         (0x1 << 3)

 
 

-#define PIIX4_OCW3_IRR          0x2
-#define PIIX4_OCW3_ISR          0x3
+#define PIIX4_OCW3_IRR         0x2
+#define PIIX4_OCW3_ISR         0x3

 
 #endif /* __ASM_MIPS_BOARDS_PIIX4_H */
 
 #endif /* __ASM_MIPS_BOARDS_PIIX4_H */

diff --git a/arch/mips/include/asm/mips-boards/prom.h b/arch/mips/include/asm/mips-boards/prom.h
index a9db576a9768e0493711dd07ee39e2bdc63b6e5f..e7aed3e4ff584706e7f4a307dae5d7f1108cb28e 100644 (file)
--- a/arch/mips/include/asm/mips-boards/prom.h
+++ b/arch/mips/include/asm/mips-boards/prom.h
@@ -39,9 +39,9 @@ extern int get_ethernet_addr(char *ethernet_addr);
 /* Memory descriptor management. */
 #define PROM_MAX_PMEMBLOCKS    32
 struct prom_pmemblock {
 /* Memory descriptor management. */
 #define PROM_MAX_PMEMBLOCKS    32
 struct prom_pmemblock {

-        unsigned long base; /* Within KSEG0. */
-        unsigned int size;  /* In bytes. */
-        unsigned int type;  /* free or prom memory */
+       unsigned long base; /* Within KSEG0. */
+       unsigned int size;  /* In bytes. */
+       unsigned int type;  /* free or prom memory */

 };
 
 #endif /* !(_MIPS_PROM_H) */
 };
 
 #endif /* !(_MIPS_PROM_H) */

diff --git a/arch/mips/include/asm/mips-boards/sead3int.h b/arch/mips/include/asm/mips-boards/sead3int.h
index d634d9a807f6cdb21dce8333413abc2ebff1f34e..6b17aaf7d901cbf7f7cd4633c8e3b30a7a9945ce 100644 (file)
--- a/arch/mips/include/asm/mips-boards/sead3int.h
+++ b/arch/mips/include/asm/mips-boards/sead3int.h
@@ -4,8 +4,8 @@
  * for more details.
  *
  * Copyright (C) 2000,2012 MIPS Technologies, Inc.  All rights reserved.
  * for more details.
  *
  * Copyright (C) 2000,2012 MIPS Technologies, Inc.  All rights reserved.

- *      Douglas Leung <douglas@mips.com>
- *      Steven J. Hill <sjhill@mips.com>
+ *     Douglas Leung <douglas@mips.com>
+ *     Steven J. Hill <sjhill@mips.com>

  */
 #ifndef _MIPS_SEAD3INT_H
 #define _MIPS_SEAD3INT_H
  */
 #ifndef _MIPS_SEAD3INT_H
 #define _MIPS_SEAD3INT_H

diff --git a/arch/mips/include/asm/mips-boards/sim.h b/arch/mips/include/asm/mips-boards/sim.h
index acb7c2331d9893afe0b958b61c6b4f89f679f9f0..b112fdc9f77df63806b6a93740c97ff5771ec3da 100644 (file)
--- a/arch/mips/include/asm/mips-boards/sim.h
+++ b/arch/mips/include/asm/mips-boards/sim.h
@@ -19,18 +19,18 @@
 #ifndef _ASM_MIPS_BOARDS_SIM_H
 #define _ASM_MIPS_BOARDS_SIM_H
 
 #ifndef _ASM_MIPS_BOARDS_SIM_H
 #define _ASM_MIPS_BOARDS_SIM_H
 

-#define STATS_ON        1
-#define STATS_OFF       2
-#define STATS_CLEAR     3
-#define STATS_DUMP      4
+#define STATS_ON       1
+#define STATS_OFF      2
+#define STATS_CLEAR    3
+#define STATS_DUMP     4

 #define TRACE_ON               5
 #define TRACE_ON               5

-#define TRACE_OFF       6
+#define TRACE_OFF      6

 
 
 #define simcfg(code)                                           \
 ({                                        \
 
 
 #define simcfg(code)                                           \
 ({                                        \

-       __asm__  __volatile__( \
-        "sltiu $0,$0, %0" \
+       __asm__  __volatile__( \
+       "sltiu $0,$0, %0" \

                ::"i"(code)                                     \
                ); \
 })
                ::"i"(code)                                     \
                ); \
 })

diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h
index 5b3cb8553e9abafa3d3bb18b4628d1064b1bff12..38b7704ee376917450621baf67bf635d23524792 100644 (file)
--- a/arch/mips/include/asm/mipsmtregs.h
+++ b/arch/mips/include/asm/mipsmtregs.h
@@ -270,14 +270,14 @@ static inline void ehb(void)
 
 #define mftc0(rt,sel)                                                  \
 ({                                                                     \
 
 #define mftc0(rt,sel)                                                  \
 ({                                                                     \

-        unsigned long  __res;                                          \
+        unsigned long  __res;                                          \

                                                                        \
        __asm__ __volatile__(                                           \
        "       .set    push                                    \n"     \
        "       .set    mips32r2                                \n"     \
        "       .set    noat                                    \n"     \
                                                                        \
        __asm__ __volatile__(                                           \
        "       .set    push                                    \n"     \
        "       .set    mips32r2                                \n"     \
        "       .set    noat                                    \n"     \

-       "       # mftc0 $1, $" #rt ", " #sel "                  \n"     \
-       "       .word   0x41000800 | (" #rt " << 16) | " #sel " \n"     \
+       "       # mftc0 $1, $" #rt ", " #sel "                  \n"     \
+       "       .word   0x41000800 | (" #rt " << 16) | " #sel " \n"     \

        "       move    %0, $1                                  \n"     \
        "       .set    pop                                     \n"     \
        : "=r" (__res));                                                \
        "       move    %0, $1                                  \n"     \
        "       .set    pop                                     \n"     \
        : "=r" (__res));                                                \


@@ -334,7 +334,7 @@ do {                                                                        \
        "       .set    noat                                    \n"     \
        "       move    $1, %0                                  \n"     \
        "       # mttc0 %0," #rd ", " #sel "                    \n"     \
        "       .set    noat                                    \n"     \
        "       move    $1, %0                                  \n"     \
        "       # mttc0 %0," #rd ", " #sel "                    \n"     \

-       "       .word   0x41810000 | (" #rd " << 11) | " #sel " \n"     \
+       "       .word   0x41810000 | (" #rd " << 11) | " #sel " \n"     \

        "       .set    pop                                     \n"     \
        :                                                               \
        : "r" (v));                                                     \
        "       .set    pop                                     \n"     \
        :                                                               \
        : "r" (v));                                                     \

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 1ad3e34e18e6cf0a3d7297cdae8aadad5a0af6c8..2145162674b9798cfbddcbe4d6e8b0a6f2894b06 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -123,16 +123,16 @@
  * Status Register Values
  */
 
  * Status Register Values
  */
 

-#define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
-#define FPU_CSR_COND    0x00800000      /* $fcc0 */
-#define FPU_CSR_COND0   0x00800000      /* $fcc0 */
-#define FPU_CSR_COND1   0x02000000      /* $fcc1 */
-#define FPU_CSR_COND2   0x04000000      /* $fcc2 */
-#define FPU_CSR_COND3   0x08000000      /* $fcc3 */
-#define FPU_CSR_COND4   0x10000000      /* $fcc4 */
-#define FPU_CSR_COND5   0x20000000      /* $fcc5 */
-#define FPU_CSR_COND6   0x40000000      /* $fcc6 */
-#define FPU_CSR_COND7   0x80000000      /* $fcc7 */
+#define FPU_CSR_FLUSH  0x01000000      /* flush denormalised results to 0 */
+#define FPU_CSR_COND   0x00800000      /* $fcc0 */
+#define FPU_CSR_COND0  0x00800000      /* $fcc0 */
+#define FPU_CSR_COND1  0x02000000      /* $fcc1 */
+#define FPU_CSR_COND2  0x04000000      /* $fcc2 */
+#define FPU_CSR_COND3  0x08000000      /* $fcc3 */
+#define FPU_CSR_COND4  0x10000000      /* $fcc4 */
+#define FPU_CSR_COND5  0x20000000      /* $fcc5 */
+#define FPU_CSR_COND6  0x40000000      /* $fcc6 */
+#define FPU_CSR_COND7  0x80000000      /* $fcc7 */

 
 /*
  * Bits 18 - 20 of the FPU Status Register will be read as 0,
 
 /*
  * Bits 18 - 20 of the FPU Status Register will be read as 0,


@@ -145,34 +145,34 @@
  * E the exception enable
  * S the sticky/flag bit
 */
  * E the exception enable
  * S the sticky/flag bit
 */

-#define FPU_CSR_ALL_X   0x0003f000
-#define FPU_CSR_UNI_X   0x00020000
-#define FPU_CSR_INV_X   0x00010000
-#define FPU_CSR_DIV_X   0x00008000
-#define FPU_CSR_OVF_X   0x00004000
-#define FPU_CSR_UDF_X   0x00002000
-#define FPU_CSR_INE_X   0x00001000
-
-#define FPU_CSR_ALL_E   0x00000f80
-#define FPU_CSR_INV_E   0x00000800
-#define FPU_CSR_DIV_E   0x00000400
-#define FPU_CSR_OVF_E   0x00000200
-#define FPU_CSR_UDF_E   0x00000100
-#define FPU_CSR_INE_E   0x00000080
-
-#define FPU_CSR_ALL_S   0x0000007c
-#define FPU_CSR_INV_S   0x00000040
-#define FPU_CSR_DIV_S   0x00000020
-#define FPU_CSR_OVF_S   0x00000010
-#define FPU_CSR_UDF_S   0x00000008
-#define FPU_CSR_INE_S   0x00000004
+#define FPU_CSR_ALL_X  0x0003f000
+#define FPU_CSR_UNI_X  0x00020000
+#define FPU_CSR_INV_X  0x00010000
+#define FPU_CSR_DIV_X  0x00008000
+#define FPU_CSR_OVF_X  0x00004000
+#define FPU_CSR_UDF_X  0x00002000
+#define FPU_CSR_INE_X  0x00001000
+
+#define FPU_CSR_ALL_E  0x00000f80
+#define FPU_CSR_INV_E  0x00000800
+#define FPU_CSR_DIV_E  0x00000400
+#define FPU_CSR_OVF_E  0x00000200
+#define FPU_CSR_UDF_E  0x00000100
+#define FPU_CSR_INE_E  0x00000080
+
+#define FPU_CSR_ALL_S  0x0000007c
+#define FPU_CSR_INV_S  0x00000040
+#define FPU_CSR_DIV_S  0x00000020
+#define FPU_CSR_OVF_S  0x00000010
+#define FPU_CSR_UDF_S  0x00000008
+#define FPU_CSR_INE_S  0x00000004

 
 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
 #define FPU_CSR_RM     0x00000003
 
 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
 #define FPU_CSR_RM     0x00000003

-#define FPU_CSR_RN      0x0     /* nearest */
-#define FPU_CSR_RZ      0x1     /* towards zero */
-#define FPU_CSR_RU      0x2     /* towards +Infinity */
-#define FPU_CSR_RD      0x3     /* towards -Infinity */
+#define FPU_CSR_RN     0x0     /* nearest */
+#define FPU_CSR_RZ     0x1     /* towards zero */
+#define FPU_CSR_RU     0x2     /* towards +Infinity */
+#define FPU_CSR_RD     0x3     /* towards -Infinity */

 
 
 /*
 
 
 /*


@@ -214,15 +214,15 @@
  * Default page size for a given kernel configuration
  */
 #ifdef CONFIG_PAGE_SIZE_4KB
  * Default page size for a given kernel configuration
  */
 #ifdef CONFIG_PAGE_SIZE_4KB

-#define PM_DEFAULT_MASK        PM_4K
+#define PM_DEFAULT_MASK PM_4K

 #elif defined(CONFIG_PAGE_SIZE_8KB)
 #elif defined(CONFIG_PAGE_SIZE_8KB)

-#define PM_DEFAULT_MASK        PM_8K
+#define PM_DEFAULT_MASK PM_8K

 #elif defined(CONFIG_PAGE_SIZE_16KB)
 #elif defined(CONFIG_PAGE_SIZE_16KB)

-#define PM_DEFAULT_MASK        PM_16K
+#define PM_DEFAULT_MASK PM_16K

 #elif defined(CONFIG_PAGE_SIZE_32KB)
 #elif defined(CONFIG_PAGE_SIZE_32KB)

-#define PM_DEFAULT_MASK        PM_32K
+#define PM_DEFAULT_MASK PM_32K

 #elif defined(CONFIG_PAGE_SIZE_64KB)
 #elif defined(CONFIG_PAGE_SIZE_64KB)

-#define PM_DEFAULT_MASK        PM_64K
+#define PM_DEFAULT_MASK PM_64K

 #else
 #error Bad page size configuration!
 #endif
 #else
 #error Bad page size configuration!
 #endif


@@ -260,34 +260,34 @@
 /*
  * PageGrain bits
  */
 /*
  * PageGrain bits
  */

-#define PG_RIE         (_ULCAST_(1) <<  31)
-#define PG_XIE         (_ULCAST_(1) <<  30)
-#define PG_ELPA                (_ULCAST_(1) <<  29)
-#define PG_ESP         (_ULCAST_(1) <<  28)
+#define PG_RIE         (_ULCAST_(1) <<  31)
+#define PG_XIE         (_ULCAST_(1) <<  30)
+#define PG_ELPA                (_ULCAST_(1) <<  29)
+#define PG_ESP         (_ULCAST_(1) <<  28)

 
 /*
  * R4x00 interrupt enable / cause bits
  */
 
 /*
  * R4x00 interrupt enable / cause bits
  */

-#define IE_SW0          (_ULCAST_(1) <<  8)
-#define IE_SW1          (_ULCAST_(1) <<  9)
-#define IE_IRQ0         (_ULCAST_(1) << 10)
-#define IE_IRQ1         (_ULCAST_(1) << 11)
-#define IE_IRQ2         (_ULCAST_(1) << 12)
-#define IE_IRQ3         (_ULCAST_(1) << 13)
-#define IE_IRQ4         (_ULCAST_(1) << 14)
-#define IE_IRQ5         (_ULCAST_(1) << 15)
+#define IE_SW0         (_ULCAST_(1) <<  8)
+#define IE_SW1         (_ULCAST_(1) <<  9)
+#define IE_IRQ0                (_ULCAST_(1) << 10)
+#define IE_IRQ1                (_ULCAST_(1) << 11)
+#define IE_IRQ2                (_ULCAST_(1) << 12)
+#define IE_IRQ3                (_ULCAST_(1) << 13)
+#define IE_IRQ4                (_ULCAST_(1) << 14)
+#define IE_IRQ5                (_ULCAST_(1) << 15)

 
 /*
  * R4x00 interrupt cause bits
  */
 
 /*
  * R4x00 interrupt cause bits
  */

-#define C_SW0           (_ULCAST_(1) <<  8)
-#define C_SW1           (_ULCAST_(1) <<  9)
-#define C_IRQ0          (_ULCAST_(1) << 10)
-#define C_IRQ1          (_ULCAST_(1) << 11)
-#define C_IRQ2          (_ULCAST_(1) << 12)
-#define C_IRQ3          (_ULCAST_(1) << 13)
-#define C_IRQ4          (_ULCAST_(1) << 14)
-#define C_IRQ5          (_ULCAST_(1) << 15)
+#define C_SW0          (_ULCAST_(1) <<  8)
+#define C_SW1          (_ULCAST_(1) <<  9)
+#define C_IRQ0         (_ULCAST_(1) << 10)
+#define C_IRQ1         (_ULCAST_(1) << 11)
+#define C_IRQ2         (_ULCAST_(1) << 12)
+#define C_IRQ3         (_ULCAST_(1) << 13)
+#define C_IRQ4         (_ULCAST_(1) << 14)
+#define C_IRQ5         (_ULCAST_(1) << 15)

 
 /*
  * Bitfields in the R4xx0 cp0 status register
 
 /*
  * Bitfields in the R4xx0 cp0 status register


@@ -301,7 +301,7 @@
 #  define KSU_KERNEL           0x00000000
 #define ST0_UX                 0x00000020
 #define ST0_SX                 0x00000040
 #  define KSU_KERNEL           0x00000000
 #define ST0_UX                 0x00000020
 #define ST0_SX                 0x00000040

-#define ST0_KX                         0x00000080
+#define ST0_KX                 0x00000080

 #define ST0_DE                 0x00010000
 #define ST0_CE                 0x00020000
 
 #define ST0_DE                 0x00010000
 #define ST0_CE                 0x00020000
 


@@ -315,7 +315,7 @@
 /*
  * Bitfields in the R[23]000 cp0 status register.
  */
 /*
  * Bitfields in the R[23]000 cp0 status register.
  */

-#define ST0_IEC                 0x00000001
+#define ST0_IEC                        0x00000001

 #define ST0_KUC                        0x00000002
 #define ST0_IEP                        0x00000004
 #define ST0_KUP                        0x00000008
 #define ST0_KUC                        0x00000002
 #define ST0_IEP                        0x00000004
 #define ST0_KUP                        0x00000008


@@ -329,7 +329,7 @@
 /*
  * Bits specific to the R4640/R4650
  */
 /*
  * Bits specific to the R4640/R4650
  */

-#define ST0_UM                 (_ULCAST_(1) <<  4)
+#define ST0_UM                 (_ULCAST_(1) <<  4)

 #define ST0_IL                 (_ULCAST_(1) << 23)
 #define ST0_DL                 (_ULCAST_(1) << 24)
 
 #define ST0_IL                 (_ULCAST_(1) << 23)
 #define ST0_DL                 (_ULCAST_(1) << 24)
 


@@ -343,22 +343,22 @@
  */
 #define TX39_CONF_ICS_SHIFT    19
 #define TX39_CONF_ICS_MASK     0x00380000
  */
 #define TX39_CONF_ICS_SHIFT    19
 #define TX39_CONF_ICS_MASK     0x00380000

-#define TX39_CONF_ICS_1KB      0x00000000
-#define TX39_CONF_ICS_2KB      0x00080000
-#define TX39_CONF_ICS_4KB      0x00100000
-#define TX39_CONF_ICS_8KB      0x00180000
-#define TX39_CONF_ICS_16KB     0x00200000
+#define TX39_CONF_ICS_1KB      0x00000000
+#define TX39_CONF_ICS_2KB      0x00080000
+#define TX39_CONF_ICS_4KB      0x00100000
+#define TX39_CONF_ICS_8KB      0x00180000
+#define TX39_CONF_ICS_16KB     0x00200000

 
 #define TX39_CONF_DCS_SHIFT    16
 #define TX39_CONF_DCS_MASK     0x00070000
 
 #define TX39_CONF_DCS_SHIFT    16
 #define TX39_CONF_DCS_MASK     0x00070000

-#define TX39_CONF_DCS_1KB      0x00000000
-#define TX39_CONF_DCS_2KB      0x00010000
-#define TX39_CONF_DCS_4KB      0x00020000
-#define TX39_CONF_DCS_8KB      0x00030000
-#define TX39_CONF_DCS_16KB     0x00040000
-
-#define TX39_CONF_CWFON        0x00004000
-#define TX39_CONF_WBON         0x00002000
+#define TX39_CONF_DCS_1KB      0x00000000
+#define TX39_CONF_DCS_2KB      0x00010000
+#define TX39_CONF_DCS_4KB      0x00020000
+#define TX39_CONF_DCS_8KB      0x00030000
+#define TX39_CONF_DCS_16KB     0x00040000
+
+#define TX39_CONF_CWFON                0x00004000
+#define TX39_CONF_WBON         0x00002000

 #define TX39_CONF_RF_SHIFT     10
 #define TX39_CONF_RF_MASK      0x00000c00
 #define TX39_CONF_DOZE         0x00000200
 #define TX39_CONF_RF_SHIFT     10
 #define TX39_CONF_RF_MASK      0x00000c00
 #define TX39_CONF_DOZE         0x00000200


@@ -375,38 +375,38 @@
  * Status register bits available in all MIPS CPUs.
  */
 #define ST0_IM                 0x0000ff00
  * Status register bits available in all MIPS CPUs.
  */
 #define ST0_IM                 0x0000ff00

-#define  STATUSB_IP0           8
-#define  STATUSF_IP0           (_ULCAST_(1) <<  8)
-#define  STATUSB_IP1           9
-#define  STATUSF_IP1           (_ULCAST_(1) <<  9)
-#define  STATUSB_IP2           10
-#define  STATUSF_IP2           (_ULCAST_(1) << 10)
-#define  STATUSB_IP3           11
-#define  STATUSF_IP3           (_ULCAST_(1) << 11)
-#define  STATUSB_IP4           12
-#define  STATUSF_IP4           (_ULCAST_(1) << 12)
-#define  STATUSB_IP5           13
-#define  STATUSF_IP5           (_ULCAST_(1) << 13)
-#define  STATUSB_IP6           14
-#define  STATUSF_IP6           (_ULCAST_(1) << 14)
-#define  STATUSB_IP7           15
-#define  STATUSF_IP7           (_ULCAST_(1) << 15)
-#define  STATUSB_IP8           0
-#define  STATUSF_IP8           (_ULCAST_(1) <<  0)
-#define  STATUSB_IP9           1
-#define  STATUSF_IP9           (_ULCAST_(1) <<  1)
-#define  STATUSB_IP10          2
-#define  STATUSF_IP10          (_ULCAST_(1) <<  2)
-#define  STATUSB_IP11          3
-#define  STATUSF_IP11          (_ULCAST_(1) <<  3)
-#define  STATUSB_IP12          4
-#define  STATUSF_IP12          (_ULCAST_(1) <<  4)
-#define  STATUSB_IP13          5
-#define  STATUSF_IP13          (_ULCAST_(1) <<  5)
-#define  STATUSB_IP14          6
-#define  STATUSF_IP14          (_ULCAST_(1) <<  6)
-#define  STATUSB_IP15          7
-#define  STATUSF_IP15          (_ULCAST_(1) <<  7)
+#define         STATUSB_IP0            8
+#define         STATUSF_IP0            (_ULCAST_(1) <<  8)
+#define         STATUSB_IP1            9
+#define         STATUSF_IP1            (_ULCAST_(1) <<  9)
+#define         STATUSB_IP2            10
+#define         STATUSF_IP2            (_ULCAST_(1) << 10)
+#define         STATUSB_IP3            11
+#define         STATUSF_IP3            (_ULCAST_(1) << 11)
+#define         STATUSB_IP4            12
+#define         STATUSF_IP4            (_ULCAST_(1) << 12)
+#define         STATUSB_IP5            13
+#define         STATUSF_IP5            (_ULCAST_(1) << 13)
+#define         STATUSB_IP6            14
+#define         STATUSF_IP6            (_ULCAST_(1) << 14)
+#define         STATUSB_IP7            15
+#define         STATUSF_IP7            (_ULCAST_(1) << 15)
+#define         STATUSB_IP8            0
+#define         STATUSF_IP8            (_ULCAST_(1) <<  0)
+#define         STATUSB_IP9            1
+#define         STATUSF_IP9            (_ULCAST_(1) <<  1)
+#define         STATUSB_IP10           2
+#define         STATUSF_IP10           (_ULCAST_(1) <<  2)
+#define         STATUSB_IP11           3
+#define         STATUSF_IP11           (_ULCAST_(1) <<  3)
+#define         STATUSB_IP12           4
+#define         STATUSF_IP12           (_ULCAST_(1) <<  4)
+#define         STATUSB_IP13           5
+#define         STATUSF_IP13           (_ULCAST_(1) <<  5)
+#define         STATUSB_IP14           6
+#define         STATUSF_IP14           (_ULCAST_(1) <<  6)
+#define         STATUSB_IP15           7
+#define         STATUSF_IP15           (_ULCAST_(1) <<  7)

 #define ST0_CH                 0x00040000
 #define ST0_NMI                        0x00080000
 #define ST0_SR                 0x00100000
 #define ST0_CH                 0x00040000
 #define ST0_NMI                        0x00080000
 #define ST0_SR                 0x00100000


@@ -436,36 +436,36 @@
  *
  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
  */
  *
  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
  */

-#define  CAUSEB_EXCCODE                2
-#define  CAUSEF_EXCCODE                (_ULCAST_(31)  <<  2)
-#define  CAUSEB_IP             8
-#define  CAUSEF_IP             (_ULCAST_(255) <<  8)
-#define  CAUSEB_IP0            8
-#define  CAUSEF_IP0            (_ULCAST_(1)   <<  8)
-#define  CAUSEB_IP1            9
-#define  CAUSEF_IP1            (_ULCAST_(1)   <<  9)
-#define  CAUSEB_IP2            10
-#define  CAUSEF_IP2            (_ULCAST_(1)   << 10)
-#define  CAUSEB_IP3            11
-#define  CAUSEF_IP3            (_ULCAST_(1)   << 11)
-#define  CAUSEB_IP4            12
-#define  CAUSEF_IP4            (_ULCAST_(1)   << 12)
-#define  CAUSEB_IP5            13
-#define  CAUSEF_IP5            (_ULCAST_(1)   << 13)
-#define  CAUSEB_IP6            14
-#define  CAUSEF_IP6            (_ULCAST_(1)   << 14)
-#define  CAUSEB_IP7            15
-#define  CAUSEF_IP7            (_ULCAST_(1)   << 15)
-#define  CAUSEB_IV             23
-#define  CAUSEF_IV             (_ULCAST_(1)   << 23)
-#define  CAUSEB_PCI            26
-#define  CAUSEF_PCI            (_ULCAST_(1)   << 26)
-#define  CAUSEB_CE             28
-#define  CAUSEF_CE             (_ULCAST_(3)   << 28)
-#define  CAUSEB_TI             30
-#define  CAUSEF_TI             (_ULCAST_(1)   << 30)
-#define  CAUSEB_BD             31
-#define  CAUSEF_BD             (_ULCAST_(1)   << 31)
+#define         CAUSEB_EXCCODE         2
+#define         CAUSEF_EXCCODE         (_ULCAST_(31)  <<  2)
+#define         CAUSEB_IP              8
+#define         CAUSEF_IP              (_ULCAST_(255) <<  8)
+#define         CAUSEB_IP0             8
+#define         CAUSEF_IP0             (_ULCAST_(1)   <<  8)
+#define         CAUSEB_IP1             9
+#define         CAUSEF_IP1             (_ULCAST_(1)   <<  9)
+#define         CAUSEB_IP2             10
+#define         CAUSEF_IP2             (_ULCAST_(1)   << 10)
+#define         CAUSEB_IP3             11
+#define         CAUSEF_IP3             (_ULCAST_(1)   << 11)
+#define         CAUSEB_IP4             12
+#define         CAUSEF_IP4             (_ULCAST_(1)   << 12)
+#define         CAUSEB_IP5             13
+#define         CAUSEF_IP5             (_ULCAST_(1)   << 13)
+#define         CAUSEB_IP6             14
+#define         CAUSEF_IP6             (_ULCAST_(1)   << 14)
+#define         CAUSEB_IP7             15
+#define         CAUSEF_IP7             (_ULCAST_(1)   << 15)
+#define         CAUSEB_IV              23
+#define         CAUSEF_IV              (_ULCAST_(1)   << 23)
+#define         CAUSEB_PCI             26
+#define         CAUSEF_PCI             (_ULCAST_(1)   << 26)
+#define         CAUSEB_CE              28
+#define         CAUSEF_CE              (_ULCAST_(3)   << 28)
+#define         CAUSEB_TI              30
+#define         CAUSEF_TI              (_ULCAST_(1)   << 30)
+#define         CAUSEB_BD              31
+#define         CAUSEF_BD              (_ULCAST_(1)   << 31)

 
 /*
  * Bits in the coprocessor 0 config register.
 
 /*
  * Bits in the coprocessor 0 config register.


@@ -483,11 +483,11 @@
 #define CONF_BE                        (_ULCAST_(1) << 15)
 
 /* Bits common to various processors.  */
 #define CONF_BE                        (_ULCAST_(1) << 15)
 
 /* Bits common to various processors.  */

-#define CONF_CU                        (_ULCAST_(1) <<  3)
-#define CONF_DB                        (_ULCAST_(1) <<  4)
-#define CONF_IB                        (_ULCAST_(1) <<  5)
-#define CONF_DC                        (_ULCAST_(7) <<  6)
-#define CONF_IC                        (_ULCAST_(7) <<  9)
+#define CONF_CU                        (_ULCAST_(1) <<  3)
+#define CONF_DB                        (_ULCAST_(1) <<  4)
+#define CONF_IB                        (_ULCAST_(1) <<  5)
+#define CONF_DC                        (_ULCAST_(7) <<  6)
+#define CONF_IC                        (_ULCAST_(7) <<  9)

 #define CONF_EB                        (_ULCAST_(1) << 13)
 #define CONF_EM                        (_ULCAST_(1) << 14)
 #define CONF_SM                        (_ULCAST_(1) << 16)
 #define CONF_EB                        (_ULCAST_(1) << 13)
 #define CONF_EM                        (_ULCAST_(1) << 14)
 #define CONF_SM                        (_ULCAST_(1) << 16)


@@ -497,29 +497,29 @@
 #define CONF_EC                        (_ULCAST_(7) << 28)
 #define CONF_CM                        (_ULCAST_(1) << 31)
 
 #define CONF_EC                        (_ULCAST_(7) << 28)
 #define CONF_CM                        (_ULCAST_(1) << 31)
 

-/* Bits specific to the R4xx0.  */
+/* Bits specific to the R4xx0. */

 #define R4K_CONF_SW            (_ULCAST_(1) << 20)
 #define R4K_CONF_SS            (_ULCAST_(1) << 21)
 #define R4K_CONF_SB            (_ULCAST_(3) << 22)
 
 #define R4K_CONF_SW            (_ULCAST_(1) << 20)
 #define R4K_CONF_SS            (_ULCAST_(1) << 21)
 #define R4K_CONF_SB            (_ULCAST_(3) << 22)
 

-/* Bits specific to the R5000.  */
+/* Bits specific to the R5000. */

 #define R5K_CONF_SE            (_ULCAST_(1) << 12)
 #define R5K_CONF_SS            (_ULCAST_(3) << 20)
 
 #define R5K_CONF_SE            (_ULCAST_(1) << 12)
 #define R5K_CONF_SS            (_ULCAST_(3) << 20)
 

-/* Bits specific to the RM7000.  */
-#define RM7K_CONF_SE           (_ULCAST_(1) <<  3)
+/* Bits specific to the RM7000.         */
+#define RM7K_CONF_SE           (_ULCAST_(1) <<  3)

 #define RM7K_CONF_TE           (_ULCAST_(1) << 12)
 #define RM7K_CONF_CLK          (_ULCAST_(1) << 16)
 #define RM7K_CONF_TC           (_ULCAST_(1) << 17)
 #define RM7K_CONF_SI           (_ULCAST_(3) << 20)
 #define RM7K_CONF_SC           (_ULCAST_(1) << 31)
 
 #define RM7K_CONF_TE           (_ULCAST_(1) << 12)
 #define RM7K_CONF_CLK          (_ULCAST_(1) << 16)
 #define RM7K_CONF_TC           (_ULCAST_(1) << 17)
 #define RM7K_CONF_SI           (_ULCAST_(3) << 20)
 #define RM7K_CONF_SC           (_ULCAST_(1) << 31)
 

-/* Bits specific to the R10000.  */
-#define R10K_CONF_DN           (_ULCAST_(3) <<  3)
-#define R10K_CONF_CT           (_ULCAST_(1) <<  5)
-#define R10K_CONF_PE           (_ULCAST_(1) <<  6)
-#define R10K_CONF_PM           (_ULCAST_(3) <<  7)
-#define R10K_CONF_EC           (_ULCAST_(15)<<  9)
+/* Bits specific to the R10000.         */
+#define R10K_CONF_DN           (_ULCAST_(3) <<  3)
+#define R10K_CONF_CT           (_ULCAST_(1) <<  5)
+#define R10K_CONF_PE           (_ULCAST_(1) <<  6)
+#define R10K_CONF_PM           (_ULCAST_(3) <<  7)
+#define R10K_CONF_EC           (_ULCAST_(15)<<  9)

 #define R10K_CONF_SB           (_ULCAST_(1) << 13)
 #define R10K_CONF_SK           (_ULCAST_(1) << 14)
 #define R10K_CONF_SS           (_ULCAST_(7) << 16)
 #define R10K_CONF_SB           (_ULCAST_(1) << 13)
 #define R10K_CONF_SK           (_ULCAST_(1) << 14)
 #define R10K_CONF_SS           (_ULCAST_(7) << 16)


@@ -527,14 +527,14 @@
 #define R10K_CONF_DC           (_ULCAST_(7) << 26)
 #define R10K_CONF_IC           (_ULCAST_(7) << 29)
 
 #define R10K_CONF_DC           (_ULCAST_(7) << 26)
 #define R10K_CONF_IC           (_ULCAST_(7) << 29)
 

-/* Bits specific to the VR41xx.  */
+/* Bits specific to the VR41xx.         */

 #define VR41_CONF_CS           (_ULCAST_(1) << 12)
 #define VR41_CONF_P4K          (_ULCAST_(1) << 13)
 #define VR41_CONF_BP           (_ULCAST_(1) << 16)
 #define VR41_CONF_M16          (_ULCAST_(1) << 20)
 #define VR41_CONF_AD           (_ULCAST_(1) << 23)
 
 #define VR41_CONF_CS           (_ULCAST_(1) << 12)
 #define VR41_CONF_P4K          (_ULCAST_(1) << 13)
 #define VR41_CONF_BP           (_ULCAST_(1) << 16)
 #define VR41_CONF_M16          (_ULCAST_(1) << 20)
 #define VR41_CONF_AD           (_ULCAST_(1) << 23)
 

-/* Bits specific to the R30xx.  */
+/* Bits specific to the R30xx. */

 #define R30XX_CONF_FDM         (_ULCAST_(1) << 19)
 #define R30XX_CONF_REV         (_ULCAST_(1) << 22)
 #define R30XX_CONF_AC          (_ULCAST_(1) << 23)
 #define R30XX_CONF_FDM         (_ULCAST_(1) << 19)
 #define R30XX_CONF_REV         (_ULCAST_(1) << 22)
 #define R30XX_CONF_AC          (_ULCAST_(1) << 23)


@@ -551,8 +551,8 @@
 #define TX49_CONF_HALT         (_ULCAST_(1) << 18)
 #define TX49_CONF_CWFON                (_ULCAST_(1) << 27)
 
 #define TX49_CONF_HALT         (_ULCAST_(1) << 18)
 #define TX49_CONF_CWFON                (_ULCAST_(1) << 27)
 

-/* Bits specific to the MIPS32/64 PRA.  */
-#define MIPS_CONF_MT           (_ULCAST_(7) <<  7)
+/* Bits specific to the MIPS32/64 PRA. */
+#define MIPS_CONF_MT           (_ULCAST_(7) <<  7)

 #define MIPS_CONF_AR           (_ULCAST_(7) << 10)
 #define MIPS_CONF_AT           (_ULCAST_(3) << 13)
 #define MIPS_CONF_M            (_ULCAST_(1) << 31)
 #define MIPS_CONF_AR           (_ULCAST_(7) << 10)
 #define MIPS_CONF_AT           (_ULCAST_(3) << 13)
 #define MIPS_CONF_M            (_ULCAST_(1) << 31)


@@ -560,14 +560,14 @@
 /*
  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
  */
 /*
  * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
  */

-#define MIPS_CONF1_FP          (_ULCAST_(1) <<  0)
-#define MIPS_CONF1_EP          (_ULCAST_(1) <<  1)
-#define MIPS_CONF1_CA          (_ULCAST_(1) <<  2)
-#define MIPS_CONF1_WR          (_ULCAST_(1) <<  3)
-#define MIPS_CONF1_PC          (_ULCAST_(1) <<  4)
-#define MIPS_CONF1_MD          (_ULCAST_(1) <<  5)
-#define MIPS_CONF1_C2          (_ULCAST_(1) <<  6)
-#define MIPS_CONF1_DA          (_ULCAST_(7) <<  7)
+#define MIPS_CONF1_FP          (_ULCAST_(1) <<  0)
+#define MIPS_CONF1_EP          (_ULCAST_(1) <<  1)
+#define MIPS_CONF1_CA          (_ULCAST_(1) <<  2)
+#define MIPS_CONF1_WR          (_ULCAST_(1) <<  3)
+#define MIPS_CONF1_PC          (_ULCAST_(1) <<  4)
+#define MIPS_CONF1_MD          (_ULCAST_(1) <<  5)
+#define MIPS_CONF1_C2          (_ULCAST_(1) <<  6)
+#define MIPS_CONF1_DA          (_ULCAST_(7) <<  7)

 #define MIPS_CONF1_DL          (_ULCAST_(7) << 10)
 #define MIPS_CONF1_DS          (_ULCAST_(7) << 13)
 #define MIPS_CONF1_IA          (_ULCAST_(7) << 16)
 #define MIPS_CONF1_DL          (_ULCAST_(7) << 10)
 #define MIPS_CONF1_DS          (_ULCAST_(7) << 13)
 #define MIPS_CONF1_IA          (_ULCAST_(7) << 16)


@@ -575,22 +575,22 @@
 #define MIPS_CONF1_IS          (_ULCAST_(7) << 22)
 #define MIPS_CONF1_TLBS                (_ULCAST_(63)<< 25)
 
 #define MIPS_CONF1_IS          (_ULCAST_(7) << 22)
 #define MIPS_CONF1_TLBS                (_ULCAST_(63)<< 25)
 

-#define MIPS_CONF2_SA          (_ULCAST_(15)<<  0)
-#define MIPS_CONF2_SL          (_ULCAST_(15)<<  4)
-#define MIPS_CONF2_SS          (_ULCAST_(15)<<  8)
+#define MIPS_CONF2_SA          (_ULCAST_(15)<<  0)
+#define MIPS_CONF2_SL          (_ULCAST_(15)<<  4)
+#define MIPS_CONF2_SS          (_ULCAST_(15)<<  8)

 #define MIPS_CONF2_SU          (_ULCAST_(15)<< 12)
 #define MIPS_CONF2_TA          (_ULCAST_(15)<< 16)
 #define MIPS_CONF2_TL          (_ULCAST_(15)<< 20)
 #define MIPS_CONF2_TS          (_ULCAST_(15)<< 24)
 #define MIPS_CONF2_TU          (_ULCAST_(7) << 28)
 
 #define MIPS_CONF2_SU          (_ULCAST_(15)<< 12)
 #define MIPS_CONF2_TA          (_ULCAST_(15)<< 16)
 #define MIPS_CONF2_TL          (_ULCAST_(15)<< 20)
 #define MIPS_CONF2_TS          (_ULCAST_(15)<< 24)
 #define MIPS_CONF2_TU          (_ULCAST_(7) << 28)
 

-#define MIPS_CONF3_TL          (_ULCAST_(1) <<  0)
-#define MIPS_CONF3_SM          (_ULCAST_(1) <<  1)
-#define MIPS_CONF3_MT          (_ULCAST_(1) <<  2)
-#define MIPS_CONF3_SP          (_ULCAST_(1) <<  4)
-#define MIPS_CONF3_VINT                (_ULCAST_(1) <<  5)
-#define MIPS_CONF3_VEIC                (_ULCAST_(1) <<  6)
-#define MIPS_CONF3_LPA         (_ULCAST_(1) <<  7)
+#define MIPS_CONF3_TL          (_ULCAST_(1) <<  0)
+#define MIPS_CONF3_SM          (_ULCAST_(1) <<  1)
+#define MIPS_CONF3_MT          (_ULCAST_(1) <<  2)
+#define MIPS_CONF3_SP          (_ULCAST_(1) <<  4)
+#define MIPS_CONF3_VINT                (_ULCAST_(1) <<  5)
+#define MIPS_CONF3_VEIC                (_ULCAST_(1) <<  6)
+#define MIPS_CONF3_LPA         (_ULCAST_(1) <<  7)

 #define MIPS_CONF3_DSP         (_ULCAST_(1) << 10)
 #define MIPS_CONF3_DSP2P       (_ULCAST_(1) << 11)
 #define MIPS_CONF3_RXI         (_ULCAST_(1) << 12)
 #define MIPS_CONF3_DSP         (_ULCAST_(1) << 10)
 #define MIPS_CONF3_DSP2P       (_ULCAST_(1) << 11)
 #define MIPS_CONF3_RXI         (_ULCAST_(1) << 12)


@@ -621,7 +621,7 @@
 #ifndef __ASSEMBLY__
 
 /*
 #ifndef __ASSEMBLY__
 
 /*

- * Functions to access the R10000 performance counters.  These are basically
+ * Functions to access the R10000 performance counters.         These are basically

  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
  * performance counter number encoded into bits 1 ... 5 of the instruction.
  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
  * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
  * performance counter number encoded into bits 1 ... 5 of the instruction.
  * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware


@@ -632,13 +632,13 @@
        unsigned int __res;                                     \
        __asm__ __volatile__(                                   \
        "mfpc\t%0, %1"                                          \
        unsigned int __res;                                     \
        __asm__ __volatile__(                                   \
        "mfpc\t%0, %1"                                          \

-        : "=r" (__res)                                         \
+       : "=r" (__res)                                          \

        : "i" (counter));                                       \
                                                                \
        : "i" (counter));                                       \
                                                                \

-        __res;                                                 \
+       __res;                                                  \

 })
 
 })
 

-#define write_r10k_perf_cntr(counter,val)                       \
+#define write_r10k_perf_cntr(counter,val)                      \

 do {                                                           \
        __asm__ __volatile__(                                   \
        "mtpc\t%0, %1"                                          \
 do {                                                           \
        __asm__ __volatile__(                                   \
        "mtpc\t%0, %1"                                          \


@@ -651,13 +651,13 @@ do {                                                              \
        unsigned int __res;                                     \
        __asm__ __volatile__(                                   \
        "mfps\t%0, %1"                                          \
        unsigned int __res;                                     \
        __asm__ __volatile__(                                   \
        "mfps\t%0, %1"                                          \

-        : "=r" (__res)                                         \
+       : "=r" (__res)                                          \

        : "i" (counter));                                       \
                                                                \
        : "i" (counter));                                       \
                                                                \

-        __res;                                                 \
+       __res;                                                  \

 })
 
 })
 

-#define write_r10k_perf_cntl(counter,val)                       \
+#define write_r10k_perf_cntl(counter,val)                      \

 do {                                                           \
        __asm__ __volatile__(                                   \
        "mtps\t%0, %1"                                          \
 do {                                                           \
        __asm__ __volatile__(                                   \
        "mtps\t%0, %1"                                          \


@@ -847,20 +847,20 @@ do {                                                                      \
 #define write_c0_context(val)  __write_ulong_c0_register($4, 0, val)
 
 #define read_c0_userlocal()    __read_ulong_c0_register($4, 2)
 #define write_c0_context(val)  __write_ulong_c0_register($4, 0, val)
 
 #define read_c0_userlocal()    __read_ulong_c0_register($4, 2)

-#define write_c0_userlocal(val)        __write_ulong_c0_register($4, 2, val)
+#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)

 
 #define read_c0_pagemask()     __read_32bit_c0_register($5, 0)
 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
 
 #define read_c0_pagegrain()    __read_32bit_c0_register($5, 1)
 
 #define read_c0_pagemask()     __read_32bit_c0_register($5, 0)
 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
 
 #define read_c0_pagegrain()    __read_32bit_c0_register($5, 1)

-#define write_c0_pagegrain(val)        __write_32bit_c0_register($5, 1, val)
+#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)

 
 #define read_c0_wired()                __read_32bit_c0_register($6, 0)
 #define write_c0_wired(val)    __write_32bit_c0_register($6, 0, val)
 
 #define read_c0_info()         __read_32bit_c0_register($7, 0)
 
 
 #define read_c0_wired()                __read_32bit_c0_register($6, 0)
 #define write_c0_wired(val)    __write_32bit_c0_register($6, 0, val)
 
 #define read_c0_info()         __read_32bit_c0_register($7, 0)
 

-#define read_c0_cache()                __read_32bit_c0_register($7, 0) /* TX39xx */
+#define read_c0_cache()                __read_32bit_c0_register($7, 0) /* TX39xx */

 #define write_c0_cache(val)    __write_32bit_c0_register($7, 0, val)
 
 #define read_c0_badvaddr()     __read_ulong_c0_register($8, 0)
 #define write_c0_cache(val)    __write_32bit_c0_register($7, 0, val)
 
 #define read_c0_badvaddr()     __read_ulong_c0_register($8, 0)


@@ -975,7 +975,7 @@ do {                                                                        \
 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
 
 #define read_c0_framemask()    __read_32bit_c0_register($21, 0)
 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
 
 #define read_c0_framemask()    __read_32bit_c0_register($21, 0)

-#define write_c0_framemask(val)        __write_32bit_c0_register($21, 0, val)
+#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)

 
 #define read_c0_diag()         __read_32bit_c0_register($22, 0)
 #define write_c0_diag(val)     __write_32bit_c0_register($22, 0, val)
 
 #define read_c0_diag()         __read_32bit_c0_register($22, 0)
 #define write_c0_diag(val)     __write_32bit_c0_register($22, 0, val)


@@ -1005,27 +1005,27 @@ do {                                                                    \
  * MIPS32 / MIPS64 performance counters
  */
 #define read_c0_perfctrl0()    __read_32bit_c0_register($25, 0)
  * MIPS32 / MIPS64 performance counters
  */
 #define read_c0_perfctrl0()    __read_32bit_c0_register($25, 0)

-#define write_c0_perfctrl0(val)        __write_32bit_c0_register($25, 0, val)
+#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)

 #define read_c0_perfcntr0()    __read_32bit_c0_register($25, 1)
 #define read_c0_perfcntr0()    __read_32bit_c0_register($25, 1)

-#define write_c0_perfcntr0(val)        __write_32bit_c0_register($25, 1, val)
+#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)

 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
 #define read_c0_perfctrl1()    __read_32bit_c0_register($25, 2)
 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
 #define read_c0_perfctrl1()    __read_32bit_c0_register($25, 2)

-#define write_c0_perfctrl1(val)        __write_32bit_c0_register($25, 2, val)
+#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)

 #define read_c0_perfcntr1()    __read_32bit_c0_register($25, 3)
 #define read_c0_perfcntr1()    __read_32bit_c0_register($25, 3)

-#define write_c0_perfcntr1(val)        __write_32bit_c0_register($25, 3, val)
+#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)

 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
 #define read_c0_perfctrl2()    __read_32bit_c0_register($25, 4)
 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
 #define read_c0_perfctrl2()    __read_32bit_c0_register($25, 4)

-#define write_c0_perfctrl2(val)        __write_32bit_c0_register($25, 4, val)
+#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)

 #define read_c0_perfcntr2()    __read_32bit_c0_register($25, 5)
 #define read_c0_perfcntr2()    __read_32bit_c0_register($25, 5)

-#define write_c0_perfcntr2(val)        __write_32bit_c0_register($25, 5, val)
+#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)

 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
 #define read_c0_perfctrl3()    __read_32bit_c0_register($25, 6)
 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
 #define read_c0_perfctrl3()    __read_32bit_c0_register($25, 6)

-#define write_c0_perfctrl3(val)        __write_32bit_c0_register($25, 6, val)
+#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)

 #define read_c0_perfcntr3()    __read_32bit_c0_register($25, 7)
 #define read_c0_perfcntr3()    __read_32bit_c0_register($25, 7)

-#define write_c0_perfcntr3(val)        __write_32bit_c0_register($25, 7, val)
+#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)

 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
 
 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
 


@@ -1033,12 +1033,12 @@ do {                                                                    \
 #define write_c0_ecc(val)      __write_32bit_c0_register($26, 0, val)
 
 #define read_c0_derraddr0()    __read_ulong_c0_register($26, 1)
 #define write_c0_ecc(val)      __write_32bit_c0_register($26, 0, val)
 
 #define read_c0_derraddr0()    __read_ulong_c0_register($26, 1)

-#define write_c0_derraddr0(val)        __write_ulong_c0_register($26, 1, val)
+#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)

 
 #define read_c0_cacheerr()     __read_32bit_c0_register($27, 0)
 
 #define read_c0_derraddr1()    __read_ulong_c0_register($27, 1)
 
 #define read_c0_cacheerr()     __read_32bit_c0_register($27, 0)
 
 #define read_c0_derraddr1()    __read_ulong_c0_register($27, 1)

-#define write_c0_derraddr1(val)        __write_ulong_c0_register($27, 1, val)
+#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)

 
 #define read_c0_taglo()                __read_32bit_c0_register($28, 0)
 #define write_c0_taglo(val)    __write_32bit_c0_register($28, 0, val)
 
 #define read_c0_taglo()                __read_32bit_c0_register($28, 0)
 #define write_c0_taglo(val)    __write_32bit_c0_register($28, 0, val)


@@ -1083,9 +1083,9 @@ do {                                                                      \
 #define write_c0_cvmctl(val)   __write_64bit_c0_register($9, 7, val)
 
 #define read_c0_cvmmemctl()    __read_64bit_c0_register($11, 7)
 #define write_c0_cvmctl(val)   __write_64bit_c0_register($9, 7, val)
 
 #define read_c0_cvmmemctl()    __read_64bit_c0_register($11, 7)

-#define write_c0_cvmmemctl(val)        __write_64bit_c0_register($11, 7, val)
+#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)

 /*
 /*

- * The cacheerr registers are not standardized.  On OCTEON, they are
+ * The cacheerr registers are not standardized.         On OCTEON, they are

  * 64 bits wide.
  */
 #define read_octeon_c0_icacheerr()     __read_64bit_c0_register($27, 0)
  * 64 bits wide.
  */
 #define read_octeon_c0_icacheerr()     __read_64bit_c0_register($27, 0)


@@ -1183,7 +1183,7 @@ do {                                                                      \
        "       # wrdsp $1, %x1                                 \n"     \
        "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
        "       .set    pop                                     \n"     \
        "       # wrdsp $1, %x1                                 \n"     \
        "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
        "       .set    pop                                     \n"     \

-        :                                                              \
+       :                                                               \

        : "r" (val), "i" (mask));                                       \
 } while (0)
 
        : "r" (val), "i" (mask));                                       \
 } while (0)
 

diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 45cfa1ad86a64f1ec617df998cca6c355687f5e3..e81d719efcd18e9e226d07e8d69e29b970c89280 100644 (file)
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -77,7 +77,7 @@ extern unsigned long pgd_current[];
 #define ASID_INC       0x1
 extern unsigned long smtc_asid_mask;
 #define ASID_MASK      (smtc_asid_mask)
 #define ASID_INC       0x1
 extern unsigned long smtc_asid_mask;
 #define ASID_MASK      (smtc_asid_mask)

-#define        HW_ASID_MASK    0xff
+#define HW_ASID_MASK   0xff

 /* End SMTC/34K debug hack */
 #else /* FIXME: not correct for R6000 */
 
 /* End SMTC/34K debug hack */
 #else /* FIXME: not correct for R6000 */
 


@@ -140,7 +140,7 @@ init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 }
 
 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
 }
 
 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,

-                             struct task_struct *tsk)
+                            struct task_struct *tsk)

 {
        unsigned int cpu = smp_processor_id();
        unsigned long flags;
 {
        unsigned int cpu = smp_processor_id();
        unsigned long flags;


@@ -238,7 +238,7 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next)
        }
        /* See comments for similar code above */
        write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
        }
        /* See comments for similar code above */
        write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |

-                        cpu_asid(cpu, next));
+                        cpu_asid(cpu, next));

        ehb(); /* Make sure it propagates to TCStatus */
        evpe(mtflags);
 #else
        ehb(); /* Make sure it propagates to TCStatus */
        evpe(mtflags);
 #else

diff --git a/arch/mips/include/asm/msc01_ic.h b/arch/mips/include/asm/msc01_ic.h
index d92406ae2841747ef3ec99f3adbe6039eae83427..ff7f074d073c04852313bf1579138394523ad43a 100644 (file)
--- a/arch/mips/include/asm/msc01_ic.h
+++ b/arch/mips/include/asm/msc01_ic.h
@@ -15,45 +15,45 @@
  * Register offset addresses
  *****************************************************************************/
 
  * Register offset addresses
  *****************************************************************************/
 

-#define MSC01_IC_RST_OFS     0x00008    /* Software reset              */
-#define MSC01_IC_ENAL_OFS    0x00100    /* Int_in enable mask 31:0     */
-#define MSC01_IC_ENAH_OFS    0x00108    /* Int_in enable mask 63:32    */
-#define MSC01_IC_DISL_OFS    0x00120    /* Int_in disable mask 31:0    */
-#define MSC01_IC_DISH_OFS    0x00128    /* Int_in disable mask 63:32   */
-#define MSC01_IC_ISBL_OFS    0x00140    /* Raw int_in 31:0             */
-#define MSC01_IC_ISBH_OFS    0x00148    /* Raw int_in 63:32            */
-#define MSC01_IC_ISAL_OFS    0x00160    /* Masked int_in 31:0          */
-#define MSC01_IC_ISAH_OFS    0x00168    /* Masked int_in 63:32         */
-#define MSC01_IC_LVL_OFS     0x00180    /* Disable priority int_out    */
-#define MSC01_IC_RAMW_OFS    0x00180    /* Shadow set RAM (EI)        */
-#define MSC01_IC_OSB_OFS     0x00188    /* Raw int_out                 */
-#define MSC01_IC_OSA_OFS     0x00190    /* Masked int_out              */
-#define MSC01_IC_GENA_OFS    0x00198    /* Global HW int enable        */
-#define MSC01_IC_BASE_OFS    0x001a0    /* Base address of IC_VEC      */
-#define MSC01_IC_VEC_OFS     0x001b0    /* Active int's vector address */
-#define MSC01_IC_EOI_OFS     0x001c0    /* Enable lower level ints     */
-#define MSC01_IC_CFG_OFS     0x001c8    /* Configuration register      */
-#define MSC01_IC_TRLD_OFS    0x001d0    /* Interval timer reload val   */
-#define MSC01_IC_TVAL_OFS    0x001e0    /* Interval timer current val  */
-#define MSC01_IC_TCFG_OFS    0x001f0    /* Interval timer config       */
-#define MSC01_IC_SUP_OFS     0x00200    /* Set up int_in line 0        */
-#define MSC01_IC_ENA_OFS     0x00800    /* Int_in enable mask 63:0     */
-#define MSC01_IC_DIS_OFS     0x00820    /* Int_in disable mask 63:0    */
-#define MSC01_IC_ISB_OFS     0x00840    /* Raw int_in 63:0             */
-#define MSC01_IC_ISA_OFS     0x00860    /* Masked int_in 63:0          */
+#define MSC01_IC_RST_OFS     0x00008   /* Software reset              */
+#define MSC01_IC_ENAL_OFS    0x00100   /* Int_in enable mask 31:0     */
+#define MSC01_IC_ENAH_OFS    0x00108   /* Int_in enable mask 63:32    */
+#define MSC01_IC_DISL_OFS    0x00120   /* Int_in disable mask 31:0    */
+#define MSC01_IC_DISH_OFS    0x00128   /* Int_in disable mask 63:32   */
+#define MSC01_IC_ISBL_OFS    0x00140   /* Raw int_in 31:0             */
+#define MSC01_IC_ISBH_OFS    0x00148   /* Raw int_in 63:32            */
+#define MSC01_IC_ISAL_OFS    0x00160   /* Masked int_in 31:0          */
+#define MSC01_IC_ISAH_OFS    0x00168   /* Masked int_in 63:32         */
+#define MSC01_IC_LVL_OFS     0x00180   /* Disable priority int_out    */
+#define MSC01_IC_RAMW_OFS    0x00180   /* Shadow set RAM (EI)         */
+#define MSC01_IC_OSB_OFS     0x00188   /* Raw int_out                 */
+#define MSC01_IC_OSA_OFS     0x00190   /* Masked int_out              */
+#define MSC01_IC_GENA_OFS    0x00198   /* Global HW int enable        */
+#define MSC01_IC_BASE_OFS    0x001a0   /* Base address of IC_VEC      */
+#define MSC01_IC_VEC_OFS     0x001b0   /* Active int's vector address */
+#define MSC01_IC_EOI_OFS     0x001c0   /* Enable lower level ints     */
+#define MSC01_IC_CFG_OFS     0x001c8   /* Configuration register      */
+#define MSC01_IC_TRLD_OFS    0x001d0   /* Interval timer reload val   */
+#define MSC01_IC_TVAL_OFS    0x001e0   /* Interval timer current val  */
+#define MSC01_IC_TCFG_OFS    0x001f0   /* Interval timer config       */
+#define MSC01_IC_SUP_OFS     0x00200   /* Set up int_in line 0        */
+#define MSC01_IC_ENA_OFS     0x00800   /* Int_in enable mask 63:0     */
+#define MSC01_IC_DIS_OFS     0x00820   /* Int_in disable mask 63:0    */
+#define MSC01_IC_ISB_OFS     0x00840   /* Raw int_in 63:0             */
+#define MSC01_IC_ISA_OFS     0x00860   /* Masked int_in 63:0          */

 
 /*****************************************************************************
  * Register field encodings
  *****************************************************************************/
 
 
 /*****************************************************************************
  * Register field encodings
  *****************************************************************************/
 

-#define MSC01_IC_RST_RST_SHF      0
-#define MSC01_IC_RST_RST_MSK      0x00000001
-#define MSC01_IC_RST_RST_BIT      MSC01_IC_RST_RST_MSK
-#define MSC01_IC_LVL_LVL_SHF      0
-#define MSC01_IC_LVL_LVL_MSK      0x000000ff
-#define MSC01_IC_LVL_SPUR_SHF     16
-#define MSC01_IC_LVL_SPUR_MSK     0x00010000
-#define MSC01_IC_LVL_SPUR_BIT     MSC01_IC_LVL_SPUR_MSK
+#define MSC01_IC_RST_RST_SHF     0
+#define MSC01_IC_RST_RST_MSK     0x00000001
+#define MSC01_IC_RST_RST_BIT     MSC01_IC_RST_RST_MSK
+#define MSC01_IC_LVL_LVL_SHF     0
+#define MSC01_IC_LVL_LVL_MSK     0x000000ff
+#define MSC01_IC_LVL_SPUR_SHF    16
+#define MSC01_IC_LVL_SPUR_MSK    0x00010000
+#define MSC01_IC_LVL_SPUR_BIT    MSC01_IC_LVL_SPUR_MSK

 #define MSC01_IC_RAMW_RIPL_SHF   0
 #define MSC01_IC_RAMW_RIPL_MSK   0x0000003f
 #define MSC01_IC_RAMW_DATA_SHF   6
 #define MSC01_IC_RAMW_RIPL_SHF   0
 #define MSC01_IC_RAMW_RIPL_MSK   0x0000003f
 #define MSC01_IC_RAMW_DATA_SHF   6


@@ -63,33 +63,33 @@
 #define MSC01_IC_RAMW_READ_SHF   31
 #define MSC01_IC_RAMW_READ_MSK   0x80000000
 #define MSC01_IC_RAMW_READ_BIT   MSC01_IC_RAMW_READ_MSK
 #define MSC01_IC_RAMW_READ_SHF   31
 #define MSC01_IC_RAMW_READ_MSK   0x80000000
 #define MSC01_IC_RAMW_READ_BIT   MSC01_IC_RAMW_READ_MSK

-#define MSC01_IC_OSB_OSB_SHF      0
-#define MSC01_IC_OSB_OSB_MSK      0x000000ff
-#define MSC01_IC_OSA_OSA_SHF      0
-#define MSC01_IC_OSA_OSA_MSK      0x000000ff
-#define MSC01_IC_GENA_GENA_SHF    0
-#define MSC01_IC_GENA_GENA_MSK    0x00000001
-#define MSC01_IC_GENA_GENA_BIT    MSC01_IC_GENA_GENA_MSK
-#define MSC01_IC_CFG_DIS_SHF      0
-#define MSC01_IC_CFG_DIS_MSK      0x00000001
-#define MSC01_IC_CFG_DIS_BIT      MSC01_IC_CFG_DIS_MSK
-#define MSC01_IC_CFG_SHFT_SHF     8
-#define MSC01_IC_CFG_SHFT_MSK     0x00000f00
-#define MSC01_IC_TCFG_ENA_SHF     0
-#define MSC01_IC_TCFG_ENA_MSK     0x00000001
-#define MSC01_IC_TCFG_ENA_BIT     MSC01_IC_TCFG_ENA_MSK
-#define MSC01_IC_TCFG_INT_SHF     8
-#define MSC01_IC_TCFG_INT_MSK     0x00000100
-#define MSC01_IC_TCFG_INT_BIT     MSC01_IC_TCFG_INT_MSK
-#define MSC01_IC_TCFG_EDGE_SHF    16
-#define MSC01_IC_TCFG_EDGE_MSK    0x00010000
-#define MSC01_IC_TCFG_EDGE_BIT    MSC01_IC_TCFG_EDGE_MSK
-#define MSC01_IC_SUP_PRI_SHF      0
-#define MSC01_IC_SUP_PRI_MSK      0x00000007
-#define MSC01_IC_SUP_EDGE_SHF     8
-#define MSC01_IC_SUP_EDGE_MSK     0x00000100
-#define MSC01_IC_SUP_EDGE_BIT     MSC01_IC_SUP_EDGE_MSK
-#define MSC01_IC_SUP_STEP         8
+#define MSC01_IC_OSB_OSB_SHF     0
+#define MSC01_IC_OSB_OSB_MSK     0x000000ff
+#define MSC01_IC_OSA_OSA_SHF     0
+#define MSC01_IC_OSA_OSA_MSK     0x000000ff
+#define MSC01_IC_GENA_GENA_SHF   0
+#define MSC01_IC_GENA_GENA_MSK   0x00000001
+#define MSC01_IC_GENA_GENA_BIT   MSC01_IC_GENA_GENA_MSK
+#define MSC01_IC_CFG_DIS_SHF     0
+#define MSC01_IC_CFG_DIS_MSK     0x00000001
+#define MSC01_IC_CFG_DIS_BIT     MSC01_IC_CFG_DIS_MSK
+#define MSC01_IC_CFG_SHFT_SHF    8
+#define MSC01_IC_CFG_SHFT_MSK    0x00000f00
+#define MSC01_IC_TCFG_ENA_SHF    0
+#define MSC01_IC_TCFG_ENA_MSK    0x00000001
+#define MSC01_IC_TCFG_ENA_BIT    MSC01_IC_TCFG_ENA_MSK
+#define MSC01_IC_TCFG_INT_SHF    8
+#define MSC01_IC_TCFG_INT_MSK    0x00000100
+#define MSC01_IC_TCFG_INT_BIT    MSC01_IC_TCFG_INT_MSK
+#define MSC01_IC_TCFG_EDGE_SHF   16
+#define MSC01_IC_TCFG_EDGE_MSK   0x00010000
+#define MSC01_IC_TCFG_EDGE_BIT   MSC01_IC_TCFG_EDGE_MSK
+#define MSC01_IC_SUP_PRI_SHF     0
+#define MSC01_IC_SUP_PRI_MSK     0x00000007
+#define MSC01_IC_SUP_EDGE_SHF    8
+#define MSC01_IC_SUP_EDGE_MSK    0x00000100
+#define MSC01_IC_SUP_EDGE_BIT    MSC01_IC_SUP_EDGE_MSK
+#define MSC01_IC_SUP_STEP        8

 
 /*
  * MIPS System controller interrupt register base.
 
 /*
  * MIPS System controller interrupt register base.


@@ -100,32 +100,32 @@
  * Absolute register addresses
  *****************************************************************************/
 
  * Absolute register addresses
  *****************************************************************************/
 

-#define MSC01_IC_RST     (MSC01_IC_REG_BASE + MSC01_IC_RST_OFS)
-#define MSC01_IC_ENAL    (MSC01_IC_REG_BASE + MSC01_IC_ENAL_OFS)
-#define MSC01_IC_ENAH    (MSC01_IC_REG_BASE + MSC01_IC_ENAH_OFS)
-#define MSC01_IC_DISL    (MSC01_IC_REG_BASE + MSC01_IC_DISL_OFS)
-#define MSC01_IC_DISH    (MSC01_IC_REG_BASE + MSC01_IC_DISH_OFS)
-#define MSC01_IC_ISBL    (MSC01_IC_REG_BASE + MSC01_IC_ISBL_OFS)
-#define MSC01_IC_ISBH    (MSC01_IC_REG_BASE + MSC01_IC_ISBH_OFS)
-#define MSC01_IC_ISAL    (MSC01_IC_REG_BASE + MSC01_IC_ISAL_OFS)
-#define MSC01_IC_ISAH    (MSC01_IC_REG_BASE + MSC01_IC_ISAH_OFS)
-#define MSC01_IC_LVL     (MSC01_IC_REG_BASE + MSC01_IC_LVL_OFS)
-#define MSC01_IC_RAMW    (MSC01_IC_REG_BASE + MSC01_IC_RAMW_OFS)
-#define MSC01_IC_OSB     (MSC01_IC_REG_BASE + MSC01_IC_OSB_OFS)
-#define MSC01_IC_OSA     (MSC01_IC_REG_BASE + MSC01_IC_OSA_OFS)
-#define MSC01_IC_GENA    (MSC01_IC_REG_BASE + MSC01_IC_GENA_OFS)
-#define MSC01_IC_BASE    (MSC01_IC_REG_BASE + MSC01_IC_BASE_OFS)
-#define MSC01_IC_VEC     (MSC01_IC_REG_BASE + MSC01_IC_VEC_OFS)
-#define MSC01_IC_EOI     (MSC01_IC_REG_BASE + MSC01_IC_EOI_OFS)
-#define MSC01_IC_CFG     (MSC01_IC_REG_BASE + MSC01_IC_CFG_OFS)
-#define MSC01_IC_TRLD    (MSC01_IC_REG_BASE + MSC01_IC_TRLD_OFS)
-#define MSC01_IC_TVAL    (MSC01_IC_REG_BASE + MSC01_IC_TVAL_OFS)
-#define MSC01_IC_TCFG    (MSC01_IC_REG_BASE + MSC01_IC_TCFG_OFS)
-#define MSC01_IC_SUP     (MSC01_IC_REG_BASE + MSC01_IC_SUP_OFS)
-#define MSC01_IC_ENA     (MSC01_IC_REG_BASE + MSC01_IC_ENA_OFS)
-#define MSC01_IC_DIS     (MSC01_IC_REG_BASE + MSC01_IC_DIS_OFS)
-#define MSC01_IC_ISB     (MSC01_IC_REG_BASE + MSC01_IC_ISB_OFS)
-#define MSC01_IC_ISA     (MSC01_IC_REG_BASE + MSC01_IC_ISA_OFS)
+#define MSC01_IC_RST    (MSC01_IC_REG_BASE + MSC01_IC_RST_OFS)
+#define MSC01_IC_ENAL   (MSC01_IC_REG_BASE + MSC01_IC_ENAL_OFS)
+#define MSC01_IC_ENAH   (MSC01_IC_REG_BASE + MSC01_IC_ENAH_OFS)
+#define MSC01_IC_DISL   (MSC01_IC_REG_BASE + MSC01_IC_DISL_OFS)
+#define MSC01_IC_DISH   (MSC01_IC_REG_BASE + MSC01_IC_DISH_OFS)
+#define MSC01_IC_ISBL   (MSC01_IC_REG_BASE + MSC01_IC_ISBL_OFS)
+#define MSC01_IC_ISBH   (MSC01_IC_REG_BASE + MSC01_IC_ISBH_OFS)
+#define MSC01_IC_ISAL   (MSC01_IC_REG_BASE + MSC01_IC_ISAL_OFS)
+#define MSC01_IC_ISAH   (MSC01_IC_REG_BASE + MSC01_IC_ISAH_OFS)
+#define MSC01_IC_LVL    (MSC01_IC_REG_BASE + MSC01_IC_LVL_OFS)
+#define MSC01_IC_RAMW   (MSC01_IC_REG_BASE + MSC01_IC_RAMW_OFS)
+#define MSC01_IC_OSB    (MSC01_IC_REG_BASE + MSC01_IC_OSB_OFS)
+#define MSC01_IC_OSA    (MSC01_IC_REG_BASE + MSC01_IC_OSA_OFS)
+#define MSC01_IC_GENA   (MSC01_IC_REG_BASE + MSC01_IC_GENA_OFS)
+#define MSC01_IC_BASE   (MSC01_IC_REG_BASE + MSC01_IC_BASE_OFS)
+#define MSC01_IC_VEC    (MSC01_IC_REG_BASE + MSC01_IC_VEC_OFS)
+#define MSC01_IC_EOI    (MSC01_IC_REG_BASE + MSC01_IC_EOI_OFS)
+#define MSC01_IC_CFG    (MSC01_IC_REG_BASE + MSC01_IC_CFG_OFS)
+#define MSC01_IC_TRLD   (MSC01_IC_REG_BASE + MSC01_IC_TRLD_OFS)
+#define MSC01_IC_TVAL   (MSC01_IC_REG_BASE + MSC01_IC_TVAL_OFS)
+#define MSC01_IC_TCFG   (MSC01_IC_REG_BASE + MSC01_IC_TCFG_OFS)
+#define MSC01_IC_SUP    (MSC01_IC_REG_BASE + MSC01_IC_SUP_OFS)
+#define MSC01_IC_ENA    (MSC01_IC_REG_BASE + MSC01_IC_ENA_OFS)
+#define MSC01_IC_DIS    (MSC01_IC_REG_BASE + MSC01_IC_DIS_OFS)
+#define MSC01_IC_ISB    (MSC01_IC_REG_BASE + MSC01_IC_ISB_OFS)
+#define MSC01_IC_ISA    (MSC01_IC_REG_BASE + MSC01_IC_ISA_OFS)

 
 /*
  * Soc-it interrupts are configurable.
 
 /*
  * Soc-it interrupts are configurable.

diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h
index 42bfd5f1eeec002cda16996aa7ee4c6e83b3b29f..aef560a51a7e10eeceb5b8f1eda3283260e83f96 100644 (file)
--- a/arch/mips/include/asm/netlogic/common.h
+++ b/arch/mips/include/asm/netlogic/common.h
@@ -38,11 +38,11 @@
 /*
  * Common SMP definitions
  */
 /*
  * Common SMP definitions
  */

-#define        RESET_VEC_PHYS          0x1fc00000
-#define        RESET_DATA_PHYS         (RESET_VEC_PHYS + (1<<10))
-#define        BOOT_THREAD_MODE        0
-#define        BOOT_NMI_LOCK           4
-#define        BOOT_NMI_HANDLER        8
+#define RESET_VEC_PHYS         0x1fc00000
+#define RESET_DATA_PHYS                (RESET_VEC_PHYS + (1<<10))
+#define BOOT_THREAD_MODE       0
+#define BOOT_NMI_LOCK          4
+#define BOOT_NMI_HANDLER       8

 
 #ifndef __ASSEMBLY__
 #include <linux/cpumask.h>
 
 #ifndef __ASSEMBLY__
 #include <linux/cpumask.h>


@@ -80,7 +80,7 @@ extern unsigned int nlm_threads_per_core;
 extern cpumask_t nlm_cpumask;
 
 struct nlm_soc_info {
 extern cpumask_t nlm_cpumask;
 
 struct nlm_soc_info {

-       unsigned long coremask; /* cores enabled on the soc */
+       unsigned long coremask; /* cores enabled on the soc */

        unsigned long ebase;
        uint64_t irqmask;
        uint64_t sysbase;       /* only for XLP */
        unsigned long ebase;
        uint64_t irqmask;
        uint64_t sysbase;       /* only for XLP */


@@ -88,9 +88,9 @@ struct nlm_soc_info {
        spinlock_t piclock;
 };
 
        spinlock_t piclock;
 };
 

-#define        nlm_get_node(i)         (&nlm_nodes[i])
+#define nlm_get_node(i)                (&nlm_nodes[i])

 #ifdef CONFIG_CPU_XLR
 #ifdef CONFIG_CPU_XLR

-#define        nlm_current_node()      (&nlm_nodes[0])
+#define nlm_current_node()     (&nlm_nodes[0])

 #else
 #define nlm_current_node()     (&nlm_nodes[nlm_nodeid()])
 #endif
 #else
 #define nlm_current_node()     (&nlm_nodes[nlm_nodeid()])
 #endif

diff --git a/arch/mips/include/asm/netlogic/haldefs.h b/arch/mips/include/asm/netlogic/haldefs.h
index 72a0c788b472989fa858e69fbde96b1dc76f951d..419d8aef8569333418f68f61e88144d1e0b37285 100644 (file)
--- a/arch/mips/include/asm/netlogic/haldefs.h
+++ b/arch/mips/include/asm/netlogic/haldefs.h
@@ -48,7 +48,7 @@
  * access 64 bit addresses or data.
  *
  * We need to disable interrupts because we save just the lower 32 bits of
  * access 64 bit addresses or data.
  *
  * We need to disable interrupts because we save just the lower 32 bits of

- * registers in  interrupt handling. So if we get hit by an interrupt while
+ * registers in         interrupt handling. So if we get hit by an interrupt while

  * using the upper 32 bits of a register, we lose.
  */
 static inline uint32_t nlm_save_flags_kx(void)
  * using the upper 32 bits of a register, we lose.
  */
 static inline uint32_t nlm_save_flags_kx(void)

diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h
index 32ba6d95d47cef7768278d56d53757d7d74326d7..8ffae43107e63366e21465ed0436ccdc3b4fa7c2 100644 (file)
--- a/arch/mips/include/asm/netlogic/mips-extns.h
+++ b/arch/mips/include/asm/netlogic/mips-extns.h
@@ -49,7 +49,7 @@
  */
 #define write_c0_eimr(val)                                             \
 do {                                                                   \
  */
 #define write_c0_eimr(val)                                             \
 do {                                                                   \

-       if (sizeof(unsigned long) == 4) {                               \
+       if (sizeof(unsigned long) == 4) {                               \

                unsigned long __flags;                                  \
                                                                        \
                local_irq_save(__flags);                                \
                unsigned long __flags;                                  \
                                                                        \
                local_irq_save(__flags);                                \


@@ -208,7 +208,7 @@ do {                                                                        \
                        ".set\tmips0\n\t"                               \
                        : : "Jr" (value));                              \
        else                                                            \
                        ".set\tmips0\n\t"                               \
                        : : "Jr" (value));                              \
        else                                                            \

-               __asm__ __volatile__(                                   \
+               __asm__ __volatile__(                                   \

                        ".set\tmips32\n\t"                              \
                        "mtc2\t%z0, " #reg ", " #sel "\n\t"             \
                        ".set\tmips0\n\t"                               \
                        ".set\tmips32\n\t"                              \
                        "mtc2\t%z0, " #reg ", " #sel "\n\t"             \
                        ".set\tmips0\n\t"                               \

diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
index ca95133f1ad17bae8b3e0977f93bdcd232adbb05..790f0f1e55c6a7bcc271ce26ee509e7cf10eb40d 100644 (file)
--- a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h
@@ -178,9 +178,9 @@
 
 #define nlm_read_bridge_reg(b, r)      nlm_read_reg(b, r)
 #define nlm_write_bridge_reg(b, r, v)  nlm_write_reg(b, r, v)
 
 #define nlm_read_bridge_reg(b, r)      nlm_read_reg(b, r)
 #define nlm_write_bridge_reg(b, r, v)  nlm_write_reg(b, r, v)

-#define        nlm_get_bridge_pcibase(node)    \
+#define nlm_get_bridge_pcibase(node)   \

                        nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node))
                        nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node))

-#define        nlm_get_bridge_regbase(node)    \
+#define nlm_get_bridge_regbase(node)   \

                        (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
 
 #endif /* __ASSEMBLY__ */
                        (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
 
 #endif /* __ASSEMBLY__ */

diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
index 2c63f97546404ccd9f5431bddd7e250dcf17476d..9fac46fb791398a6e76271bb1f229fbad068779e 100644 (file)
--- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h
@@ -35,12 +35,12 @@
 #ifndef __NLM_HAL_IOMAP_H__
 #define __NLM_HAL_IOMAP_H__
 
 #ifndef __NLM_HAL_IOMAP_H__
 #define __NLM_HAL_IOMAP_H__
 

-#define XLP_DEFAULT_IO_BASE             0x18000000
+#define XLP_DEFAULT_IO_BASE            0x18000000

 #define XLP_DEFAULT_PCI_ECFG_BASE      XLP_DEFAULT_IO_BASE
 #define XLP_DEFAULT_PCI_CFG_BASE       0x1c000000
 
 #define NMI_BASE                       0xbfc00000
 #define XLP_DEFAULT_PCI_ECFG_BASE      XLP_DEFAULT_IO_BASE
 #define XLP_DEFAULT_PCI_CFG_BASE       0x1c000000
 
 #define NMI_BASE                       0xbfc00000

-#define        XLP_IO_CLK                      133333333
+#define XLP_IO_CLK                     133333333

 
 #define XLP_PCIE_CFG_SIZE              0x1000          /* 4K */
 #define XLP_PCIE_DEV_BLK_SIZE          (8 * XLP_PCIE_CFG_SIZE)
 
 #define XLP_PCIE_CFG_SIZE              0x1000          /* 4K */
 #define XLP_PCIE_DEV_BLK_SIZE          (8 * XLP_PCIE_CFG_SIZE)


@@ -96,8 +96,8 @@
 #define XLP_IO_NAND_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 7, 1)
 #define XLP_IO_SPI_OFFSET(node)                XLP_HDR_OFFSET(node, 0, 7, 2)
 /* SD flash */
 #define XLP_IO_NAND_OFFSET(node)       XLP_HDR_OFFSET(node, 0, 7, 1)
 #define XLP_IO_SPI_OFFSET(node)                XLP_HDR_OFFSET(node, 0, 7, 2)
 /* SD flash */

-#define XLP_IO_SD_OFFSET(node)          XLP_HDR_OFFSET(node, 0, 7, 3)
-#define XLP_IO_MMC_OFFSET(node, slot)   \
+#define XLP_IO_SD_OFFSET(node)         XLP_HDR_OFFSET(node, 0, 7, 3)
+#define XLP_IO_MMC_OFFSET(node, slot)  \

                ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
 
 /* PCI config header register id's */
                ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ)
 
 /* PCI config header register id's */


@@ -125,26 +125,26 @@
 #define XLP_PCI_SBB_WT_REG             0x3f
 
 /* PCI IDs for SoC device */
 #define XLP_PCI_SBB_WT_REG             0x3f
 
 /* PCI IDs for SoC device */

-#define        PCI_VENDOR_NETLOGIC             0x184e
-
-#define        PCI_DEVICE_ID_NLM_ROOT          0x1001
-#define        PCI_DEVICE_ID_NLM_ICI           0x1002
-#define        PCI_DEVICE_ID_NLM_PIC           0x1003
-#define        PCI_DEVICE_ID_NLM_PCIE          0x1004
-#define        PCI_DEVICE_ID_NLM_EHCI          0x1007
-#define        PCI_DEVICE_ID_NLM_OHCI          0x1008
-#define        PCI_DEVICE_ID_NLM_NAE           0x1009
-#define        PCI_DEVICE_ID_NLM_POE           0x100A
-#define        PCI_DEVICE_ID_NLM_FMN           0x100B
-#define        PCI_DEVICE_ID_NLM_RAID          0x100D
-#define        PCI_DEVICE_ID_NLM_SAE           0x100D
-#define        PCI_DEVICE_ID_NLM_RSA           0x100E
-#define        PCI_DEVICE_ID_NLM_CMP           0x100F
-#define        PCI_DEVICE_ID_NLM_UART          0x1010
-#define        PCI_DEVICE_ID_NLM_I2C           0x1011
-#define        PCI_DEVICE_ID_NLM_NOR           0x1015
-#define        PCI_DEVICE_ID_NLM_NAND          0x1016
-#define        PCI_DEVICE_ID_NLM_MMC           0x1018
+#define PCI_VENDOR_NETLOGIC            0x184e
+
+#define PCI_DEVICE_ID_NLM_ROOT         0x1001
+#define PCI_DEVICE_ID_NLM_ICI          0x1002
+#define PCI_DEVICE_ID_NLM_PIC          0x1003
+#define PCI_DEVICE_ID_NLM_PCIE         0x1004
+#define PCI_DEVICE_ID_NLM_EHCI         0x1007
+#define PCI_DEVICE_ID_NLM_OHCI         0x1008
+#define PCI_DEVICE_ID_NLM_NAE          0x1009
+#define PCI_DEVICE_ID_NLM_POE          0x100A
+#define PCI_DEVICE_ID_NLM_FMN          0x100B
+#define PCI_DEVICE_ID_NLM_RAID         0x100D
+#define PCI_DEVICE_ID_NLM_SAE          0x100D
+#define PCI_DEVICE_ID_NLM_RSA          0x100E
+#define PCI_DEVICE_ID_NLM_CMP          0x100F
+#define PCI_DEVICE_ID_NLM_UART         0x1010
+#define PCI_DEVICE_ID_NLM_I2C          0x1011
+#define PCI_DEVICE_ID_NLM_NOR          0x1015
+#define PCI_DEVICE_ID_NLM_NAND         0x1016
+#define PCI_DEVICE_ID_NLM_MMC          0x1018

 
 #ifndef __ASSEMBLY__
 
 
 #ifndef __ASSEMBLY__
 

diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
index 66c323d1bd7d286f18d537427905bb720a86c6a2..b559cb9f56ea78bd056b92d1faca753189608bb7 100644 (file)
--- a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h
@@ -33,42 +33,42 @@
  */
 
 #ifndef __NLM_HAL_PCIBUS_H__
  */
 
 #ifndef __NLM_HAL_PCIBUS_H__

-#define        __NLM_HAL_PCIBUS_H__
+#define __NLM_HAL_PCIBUS_H__

 
 /* PCIE Memory and IO regions */
 
 /* PCIE Memory and IO regions */

-#define        PCIE_MEM_BASE                   0xd0000000ULL
-#define        PCIE_MEM_LIMIT                  0xdfffffffULL
-#define        PCIE_IO_BASE                    0x14000000ULL
-#define        PCIE_IO_LIMIT                   0x15ffffffULL
+#define PCIE_MEM_BASE                  0xd0000000ULL
+#define PCIE_MEM_LIMIT                 0xdfffffffULL
+#define PCIE_IO_BASE                   0x14000000ULL
+#define PCIE_IO_LIMIT                  0x15ffffffULL

 
 

-#define        PCIE_BRIDGE_CMD                 0x1
-#define        PCIE_BRIDGE_MSI_CAP             0x14
-#define        PCIE_BRIDGE_MSI_ADDRL           0x15
-#define        PCIE_BRIDGE_MSI_ADDRH           0x16
-#define        PCIE_BRIDGE_MSI_DATA            0x17
+#define PCIE_BRIDGE_CMD                        0x1
+#define PCIE_BRIDGE_MSI_CAP            0x14
+#define PCIE_BRIDGE_MSI_ADDRL          0x15
+#define PCIE_BRIDGE_MSI_ADDRH          0x16
+#define PCIE_BRIDGE_MSI_DATA           0x17

 
 /* XLP Global PCIE configuration space registers */
 
 /* XLP Global PCIE configuration space registers */

-#define        PCIE_BYTE_SWAP_MEM_BASE         0x247
-#define        PCIE_BYTE_SWAP_MEM_LIM          0x248
-#define        PCIE_BYTE_SWAP_IO_BASE          0x249
-#define        PCIE_BYTE_SWAP_IO_LIM           0x24A
-#define        PCIE_MSI_STATUS                 0x25A
-#define        PCIE_MSI_EN                     0x25B
-#define        PCIE_INT_EN0                    0x261
+#define PCIE_BYTE_SWAP_MEM_BASE                0x247
+#define PCIE_BYTE_SWAP_MEM_LIM         0x248
+#define PCIE_BYTE_SWAP_IO_BASE         0x249
+#define PCIE_BYTE_SWAP_IO_LIM          0x24A
+#define PCIE_MSI_STATUS                        0x25A
+#define PCIE_MSI_EN                    0x25B
+#define PCIE_INT_EN0                   0x261

 
 /* PCIE_MSI_EN */
 
 /* PCIE_MSI_EN */

-#define        PCIE_MSI_VECTOR_INT_EN          0xFFFFFFFF
+#define PCIE_MSI_VECTOR_INT_EN         0xFFFFFFFF

 
 /* PCIE_INT_EN0 */
 
 /* PCIE_INT_EN0 */

-#define        PCIE_MSI_INT_EN                 (1 << 9)
+#define PCIE_MSI_INT_EN                        (1 << 9)

 
 #ifndef __ASSEMBLY__
 
 
 #ifndef __ASSEMBLY__
 

-#define        nlm_read_pcie_reg(b, r)         nlm_read_reg(b, r)
-#define        nlm_write_pcie_reg(b, r, v)     nlm_write_reg(b, r, v)
-#define        nlm_get_pcie_base(node, inst)   \
+#define nlm_read_pcie_reg(b, r)                nlm_read_reg(b, r)
+#define nlm_write_pcie_reg(b, r, v)    nlm_write_reg(b, r, v)
+#define nlm_get_pcie_base(node, inst)  \

                        nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst))
                        nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst))

-#define        nlm_get_pcie_regbase(node, inst)        \
+#define nlm_get_pcie_regbase(node, inst)       \

                        (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ)
 
 int xlp_pcie_link_irt(int link);
                        (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ)
 
 int xlp_pcie_link_irt(int link);

diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
index b2e53a5383ab155338f593c241a37081d85feae1..46ace0ca26d84fbc8dda1dfb51de53adf5cb149e 100644 (file)
--- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/pic.h
@@ -36,7 +36,7 @@
 #define _NLM_HAL_PIC_H
 
 /* PIC Specific registers */
 #define _NLM_HAL_PIC_H
 
 /* PIC Specific registers */

-#define PIC_CTRL                0x00
+#define PIC_CTRL               0x00

 
 /* PIC control register defines */
 #define PIC_CTRL_ITV           32 /* interrupt timeout value */
 
 /* PIC control register defines */
 #define PIC_CTRL_ITV           32 /* interrupt timeout value */


@@ -71,41 +71,41 @@
 #define PIC_IRT_DB             16 /* Destination base */
 #define PIC_IRT_DTE            0  /* Destination thread enables */
 
 #define PIC_IRT_DB             16 /* Destination base */
 #define PIC_IRT_DTE            0  /* Destination thread enables */
 

-#define PIC_BYTESWAP            0x02
-#define PIC_STATUS              0x04
+#define PIC_BYTESWAP           0x02
+#define PIC_STATUS             0x04

 #define PIC_INTR_TIMEOUT       0x06
 #define PIC_ICI0_INTR_TIMEOUT  0x08
 #define PIC_ICI1_INTR_TIMEOUT  0x0a
 #define PIC_ICI2_INTR_TIMEOUT  0x0c
 #define PIC_IPI_CTL            0x0e
 #define PIC_INTR_TIMEOUT       0x06
 #define PIC_ICI0_INTR_TIMEOUT  0x08
 #define PIC_ICI1_INTR_TIMEOUT  0x0a
 #define PIC_ICI2_INTR_TIMEOUT  0x0c
 #define PIC_IPI_CTL            0x0e

-#define PIC_INT_ACK             0x10
-#define PIC_INT_PENDING0        0x12
-#define PIC_INT_PENDING1        0x14
-#define PIC_INT_PENDING2        0x16
-
-#define PIC_WDOG0_MAXVAL        0x18
-#define PIC_WDOG0_COUNT         0x1a
-#define PIC_WDOG0_ENABLE0       0x1c
-#define PIC_WDOG0_ENABLE1       0x1e
-#define PIC_WDOG0_BEATCMD       0x20
-#define PIC_WDOG0_BEAT0         0x22
-#define PIC_WDOG0_BEAT1         0x24
-
-#define PIC_WDOG1_MAXVAL        0x26
-#define PIC_WDOG1_COUNT         0x28
-#define PIC_WDOG1_ENABLE0       0x2a
-#define PIC_WDOG1_ENABLE1       0x2c
-#define PIC_WDOG1_BEATCMD       0x2e
-#define PIC_WDOG1_BEAT0         0x30
-#define PIC_WDOG1_BEAT1         0x32
-
-#define PIC_WDOG_MAXVAL(i)      (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
-#define PIC_WDOG_COUNT(i)       (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
-#define PIC_WDOG_ENABLE0(i)     (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
-#define PIC_WDOG_ENABLE1(i)     (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
-#define PIC_WDOG_BEATCMD(i)     (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
-#define PIC_WDOG_BEAT0(i)       (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
-#define PIC_WDOG_BEAT1(i)       (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))
+#define PIC_INT_ACK            0x10
+#define PIC_INT_PENDING0       0x12
+#define PIC_INT_PENDING1       0x14
+#define PIC_INT_PENDING2       0x16
+
+#define PIC_WDOG0_MAXVAL       0x18
+#define PIC_WDOG0_COUNT                0x1a
+#define PIC_WDOG0_ENABLE0      0x1c
+#define PIC_WDOG0_ENABLE1      0x1e
+#define PIC_WDOG0_BEATCMD      0x20
+#define PIC_WDOG0_BEAT0                0x22
+#define PIC_WDOG0_BEAT1                0x24
+
+#define PIC_WDOG1_MAXVAL       0x26
+#define PIC_WDOG1_COUNT                0x28
+#define PIC_WDOG1_ENABLE0      0x2a
+#define PIC_WDOG1_ENABLE1      0x2c
+#define PIC_WDOG1_BEATCMD      0x2e
+#define PIC_WDOG1_BEAT0                0x30
+#define PIC_WDOG1_BEAT1                0x32
+
+#define PIC_WDOG_MAXVAL(i)     (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
+#define PIC_WDOG_COUNT(i)      (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
+#define PIC_WDOG_ENABLE0(i)    (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
+#define PIC_WDOG_ENABLE1(i)    (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
+#define PIC_WDOG_BEATCMD(i)    (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
+#define PIC_WDOG_BEAT0(i)      (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
+#define PIC_WDOG_BEAT1(i)      (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))

 
 #define PIC_TIMER0_MAXVAL    0x34
 #define PIC_TIMER1_MAXVAL    0x36
 
 #define PIC_TIMER0_MAXVAL    0x34
 #define PIC_TIMER1_MAXVAL    0x36


@@ -127,28 +127,28 @@
 #define PIC_TIMER7_COUNT     0x52
 #define PIC_TIMER_COUNT(i)   (PIC_TIMER0_COUNT + ((i) * 2))
 
 #define PIC_TIMER7_COUNT     0x52
 #define PIC_TIMER_COUNT(i)   (PIC_TIMER0_COUNT + ((i) * 2))
 

-#define PIC_ITE0_N0_N1          0x54
-#define PIC_ITE1_N0_N1          0x58
-#define PIC_ITE2_N0_N1          0x5c
-#define PIC_ITE3_N0_N1          0x60
-#define PIC_ITE4_N0_N1          0x64
-#define PIC_ITE5_N0_N1          0x68
-#define PIC_ITE6_N0_N1          0x6c
-#define PIC_ITE7_N0_N1          0x70
-#define PIC_ITE_N0_N1(i)        (PIC_ITE0_N0_N1 + ((i) * 4))
-
-#define PIC_ITE0_N2_N3          0x56
-#define PIC_ITE1_N2_N3          0x5a
-#define PIC_ITE2_N2_N3          0x5e
-#define PIC_ITE3_N2_N3          0x62
-#define PIC_ITE4_N2_N3          0x66
-#define PIC_ITE5_N2_N3          0x6a
-#define PIC_ITE6_N2_N3          0x6e
-#define PIC_ITE7_N2_N3          0x72
-#define PIC_ITE_N2_N3(i)        (PIC_ITE0_N2_N3 + ((i) * 4))
-
-#define PIC_IRT0                0x74
-#define PIC_IRT(i)              (PIC_IRT0 + ((i) * 2))
+#define PIC_ITE0_N0_N1         0x54
+#define PIC_ITE1_N0_N1         0x58
+#define PIC_ITE2_N0_N1         0x5c
+#define PIC_ITE3_N0_N1         0x60
+#define PIC_ITE4_N0_N1         0x64
+#define PIC_ITE5_N0_N1         0x68
+#define PIC_ITE6_N0_N1         0x6c
+#define PIC_ITE7_N0_N1         0x70
+#define PIC_ITE_N0_N1(i)       (PIC_ITE0_N0_N1 + ((i) * 4))
+
+#define PIC_ITE0_N2_N3         0x56
+#define PIC_ITE1_N2_N3         0x5a
+#define PIC_ITE2_N2_N3         0x5e
+#define PIC_ITE3_N2_N3         0x62
+#define PIC_ITE4_N2_N3         0x66
+#define PIC_ITE5_N2_N3         0x6a
+#define PIC_ITE6_N2_N3         0x6e
+#define PIC_ITE7_N2_N3         0x72
+#define PIC_ITE_N2_N3(i)       (PIC_ITE0_N2_N3 + ((i) * 4))
+
+#define PIC_IRT0               0x74
+#define PIC_IRT(i)             (PIC_IRT0 + ((i) * 2))

 
 #define TIMER_CYCLES_MAXVAL    0xffffffffffffffffULL
 
 
 #define TIMER_CYCLES_MAXVAL    0xffffffffffffffffULL
 

diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
index 258e8cc00e99f12a9c4ff2e843484220e8664344..470e52bfc061ea5ff9f57f4d966af592be92a8b8 100644 (file)
--- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/sys.h
@@ -40,89 +40,89 @@
 * @author Netlogic Microsystems
 * @brief HAL for System configuration registers
 */
 * @author Netlogic Microsystems
 * @brief HAL for System configuration registers
 */

-#define        SYS_CHIP_RESET                          0x00
-#define        SYS_POWER_ON_RESET_CFG                  0x01
-#define        SYS_EFUSE_DEVICE_CFG_STATUS0            0x02
-#define        SYS_EFUSE_DEVICE_CFG_STATUS1            0x03
-#define        SYS_EFUSE_DEVICE_CFG_STATUS2            0x04
-#define        SYS_EFUSE_DEVICE_CFG3                   0x05
-#define        SYS_EFUSE_DEVICE_CFG4                   0x06
-#define        SYS_EFUSE_DEVICE_CFG5                   0x07
-#define        SYS_EFUSE_DEVICE_CFG6                   0x08
-#define        SYS_EFUSE_DEVICE_CFG7                   0x09
-#define        SYS_PLL_CTRL                            0x0a
-#define        SYS_CPU_RESET                           0x0b
-#define        SYS_CPU_NONCOHERENT_MODE                0x0d
-#define        SYS_CORE_DFS_DIS_CTRL                   0x0e
-#define        SYS_CORE_DFS_RST_CTRL                   0x0f
-#define        SYS_CORE_DFS_BYP_CTRL                   0x10
-#define        SYS_CORE_DFS_PHA_CTRL                   0x11
-#define        SYS_CORE_DFS_DIV_INC_CTRL               0x12
-#define        SYS_CORE_DFS_DIV_DEC_CTRL               0x13
-#define        SYS_CORE_DFS_DIV_VALUE                  0x14
-#define        SYS_RESET                               0x15
-#define        SYS_DFS_DIS_CTRL                        0x16
-#define        SYS_DFS_RST_CTRL                        0x17
-#define        SYS_DFS_BYP_CTRL                        0x18
-#define        SYS_DFS_DIV_INC_CTRL                    0x19
-#define        SYS_DFS_DIV_DEC_CTRL                    0x1a
-#define        SYS_DFS_DIV_VALUE0                      0x1b
-#define        SYS_DFS_DIV_VALUE1                      0x1c
-#define        SYS_SENSE_AMP_DLY                       0x1d
-#define        SYS_SOC_SENSE_AMP_DLY                   0x1e
-#define        SYS_CTRL0                               0x1f
-#define        SYS_CTRL1                               0x20
-#define        SYS_TIMEOUT_BS1                         0x21
-#define        SYS_BYTE_SWAP                           0x22
-#define        SYS_VRM_VID                             0x23
-#define        SYS_PWR_RAM_CMD                         0x24
-#define        SYS_PWR_RAM_ADDR                        0x25
-#define        SYS_PWR_RAM_DATA0                       0x26
-#define        SYS_PWR_RAM_DATA1                       0x27
-#define        SYS_PWR_RAM_DATA2                       0x28
-#define        SYS_PWR_UCODE                           0x29
-#define        SYS_CPU0_PWR_STATUS                     0x2a
-#define        SYS_CPU1_PWR_STATUS                     0x2b
-#define        SYS_CPU2_PWR_STATUS                     0x2c
-#define        SYS_CPU3_PWR_STATUS                     0x2d
-#define        SYS_CPU4_PWR_STATUS                     0x2e
-#define        SYS_CPU5_PWR_STATUS                     0x2f
-#define        SYS_CPU6_PWR_STATUS                     0x30
-#define        SYS_CPU7_PWR_STATUS                     0x31
-#define        SYS_STATUS                              0x32
-#define        SYS_INT_POL                             0x33
-#define        SYS_INT_TYPE                            0x34
-#define        SYS_INT_STATUS                          0x35
-#define        SYS_INT_MASK0                           0x36
-#define        SYS_INT_MASK1                           0x37
-#define        SYS_UCO_S_ECC                           0x38
-#define        SYS_UCO_M_ECC                           0x39
-#define        SYS_UCO_ADDR                            0x3a
-#define        SYS_UCO_INSTR                           0x3b
-#define        SYS_MEM_BIST0                           0x3c
-#define        SYS_MEM_BIST1                           0x3d
-#define        SYS_MEM_BIST2                           0x3e
-#define        SYS_MEM_BIST3                           0x3f
-#define        SYS_MEM_BIST4                           0x40
-#define        SYS_MEM_BIST5                           0x41
-#define        SYS_MEM_BIST6                           0x42
-#define        SYS_MEM_BIST7                           0x43
-#define        SYS_MEM_BIST8                           0x44
-#define        SYS_MEM_BIST9                           0x45
-#define        SYS_MEM_BIST10                          0x46
-#define        SYS_MEM_BIST11                          0x47
-#define        SYS_MEM_BIST12                          0x48
-#define        SYS_SCRTCH0                             0x49
-#define        SYS_SCRTCH1                             0x4a
-#define        SYS_SCRTCH2                             0x4b
-#define        SYS_SCRTCH3                             0x4c
+#define SYS_CHIP_RESET                         0x00
+#define SYS_POWER_ON_RESET_CFG                 0x01
+#define SYS_EFUSE_DEVICE_CFG_STATUS0           0x02
+#define SYS_EFUSE_DEVICE_CFG_STATUS1           0x03
+#define SYS_EFUSE_DEVICE_CFG_STATUS2           0x04
+#define SYS_EFUSE_DEVICE_CFG3                  0x05
+#define SYS_EFUSE_DEVICE_CFG4                  0x06
+#define SYS_EFUSE_DEVICE_CFG5                  0x07
+#define SYS_EFUSE_DEVICE_CFG6                  0x08
+#define SYS_EFUSE_DEVICE_CFG7                  0x09
+#define SYS_PLL_CTRL                           0x0a
+#define SYS_CPU_RESET                          0x0b
+#define SYS_CPU_NONCOHERENT_MODE               0x0d
+#define SYS_CORE_DFS_DIS_CTRL                  0x0e
+#define SYS_CORE_DFS_RST_CTRL                  0x0f
+#define SYS_CORE_DFS_BYP_CTRL                  0x10
+#define SYS_CORE_DFS_PHA_CTRL                  0x11
+#define SYS_CORE_DFS_DIV_INC_CTRL              0x12
+#define SYS_CORE_DFS_DIV_DEC_CTRL              0x13
+#define SYS_CORE_DFS_DIV_VALUE                 0x14
+#define SYS_RESET                              0x15
+#define SYS_DFS_DIS_CTRL                       0x16
+#define SYS_DFS_RST_CTRL                       0x17
+#define SYS_DFS_BYP_CTRL                       0x18
+#define SYS_DFS_DIV_INC_CTRL                   0x19
+#define SYS_DFS_DIV_DEC_CTRL                   0x1a
+#define SYS_DFS_DIV_VALUE0                     0x1b
+#define SYS_DFS_DIV_VALUE1                     0x1c
+#define SYS_SENSE_AMP_DLY                      0x1d
+#define SYS_SOC_SENSE_AMP_DLY                  0x1e
+#define SYS_CTRL0                              0x1f
+#define SYS_CTRL1                              0x20
+#define SYS_TIMEOUT_BS1                                0x21
+#define SYS_BYTE_SWAP                          0x22
+#define SYS_VRM_VID                            0x23
+#define SYS_PWR_RAM_CMD                                0x24
+#define SYS_PWR_RAM_ADDR                       0x25
+#define SYS_PWR_RAM_DATA0                      0x26
+#define SYS_PWR_RAM_DATA1                      0x27
+#define SYS_PWR_RAM_DATA2                      0x28
+#define SYS_PWR_UCODE                          0x29
+#define SYS_CPU0_PWR_STATUS                    0x2a
+#define SYS_CPU1_PWR_STATUS                    0x2b
+#define SYS_CPU2_PWR_STATUS                    0x2c
+#define SYS_CPU3_PWR_STATUS                    0x2d
+#define SYS_CPU4_PWR_STATUS                    0x2e
+#define SYS_CPU5_PWR_STATUS                    0x2f
+#define SYS_CPU6_PWR_STATUS                    0x30
+#define SYS_CPU7_PWR_STATUS                    0x31
+#define SYS_STATUS                             0x32
+#define SYS_INT_POL                            0x33
+#define SYS_INT_TYPE                           0x34
+#define SYS_INT_STATUS                         0x35
+#define SYS_INT_MASK0                          0x36
+#define SYS_INT_MASK1                          0x37
+#define SYS_UCO_S_ECC                          0x38
+#define SYS_UCO_M_ECC                          0x39
+#define SYS_UCO_ADDR                           0x3a
+#define SYS_UCO_INSTR                          0x3b
+#define SYS_MEM_BIST0                          0x3c
+#define SYS_MEM_BIST1                          0x3d
+#define SYS_MEM_BIST2                          0x3e
+#define SYS_MEM_BIST3                          0x3f
+#define SYS_MEM_BIST4                          0x40
+#define SYS_MEM_BIST5                          0x41
+#define SYS_MEM_BIST6                          0x42
+#define SYS_MEM_BIST7                          0x43
+#define SYS_MEM_BIST8                          0x44
+#define SYS_MEM_BIST9                          0x45
+#define SYS_MEM_BIST10                         0x46
+#define SYS_MEM_BIST11                         0x47
+#define SYS_MEM_BIST12                         0x48
+#define SYS_SCRTCH0                            0x49
+#define SYS_SCRTCH1                            0x4a
+#define SYS_SCRTCH2                            0x4b
+#define SYS_SCRTCH3                            0x4c

 
 #ifndef __ASSEMBLY__
 
 
 #ifndef __ASSEMBLY__
 

-#define        nlm_read_sys_reg(b, r)          nlm_read_reg(b, r)
-#define        nlm_write_sys_reg(b, r, v)      nlm_write_reg(b, r, v)
-#define        nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
-#define        nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)
+#define nlm_read_sys_reg(b, r)         nlm_read_reg(b, r)
+#define nlm_write_sys_reg(b, r, v)     nlm_write_reg(b, r, v)
+#define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node))
+#define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ)

 
 #endif
 #endif
 
 #endif
 #endif

diff --git a/arch/mips/include/asm/netlogic/xlp-hal/uart.h b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
index 6a7046ca094d46ffb06e402bb5f6de2ca860cada..86d16e1e60720caedb6470debf9d0a9654dbcac6 100644 (file)
--- a/arch/mips/include/asm/netlogic/xlp-hal/uart.h
+++ b/arch/mips/include/asm/netlogic/xlp-hal/uart.h
@@ -91,8 +91,8 @@
 
 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
 
 
 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
 

-#define        nlm_read_uart_reg(b, r)         nlm_read_reg(b, r)
-#define        nlm_write_uart_reg(b, r, v)     nlm_write_reg(b, r, v)
+#define nlm_read_uart_reg(b, r)                nlm_read_reg(b, r)
+#define nlm_write_uart_reg(b, r, v)    nlm_write_reg(b, r, v)

 #define nlm_get_uart_pcibase(node, inst)       \
                nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst))
 #define nlm_get_uart_regbase(node, inst)       \
 #define nlm_get_uart_pcibase(node, inst)       \
                nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst))
 #define nlm_get_uart_regbase(node, inst)       \

diff --git a/arch/mips/include/asm/netlogic/xlr/fmn.h b/arch/mips/include/asm/netlogic/xlr/fmn.h
index 68d5167c86bbf873cd2f3b6ca4bb90e44b39bfc3..2a78929cef7385cbe4686689de05d4f1191ad249 100644 (file)
--- a/arch/mips/include/asm/netlogic/xlr/fmn.h
+++ b/arch/mips/include/asm/netlogic/xlr/fmn.h
@@ -38,108 +38,108 @@
 #include <asm/netlogic/mips-extns.h> /* for COP2 access */
 
 /* Station IDs */
 #include <asm/netlogic/mips-extns.h> /* for COP2 access */
 
 /* Station IDs */

-#define        FMN_STNID_CPU0                  0x00
-#define        FMN_STNID_CPU1                  0x08
-#define        FMN_STNID_CPU2                  0x10
-#define        FMN_STNID_CPU3                  0x18
-#define        FMN_STNID_CPU4                  0x20
-#define        FMN_STNID_CPU5                  0x28
-#define        FMN_STNID_CPU6                  0x30
-#define        FMN_STNID_CPU7                  0x38
-
-#define        FMN_STNID_XGS0_TX               64
-#define        FMN_STNID_XMAC0_00_TX           64
-#define        FMN_STNID_XMAC0_01_TX           65
-#define        FMN_STNID_XMAC0_02_TX           66
-#define        FMN_STNID_XMAC0_03_TX           67
-#define        FMN_STNID_XMAC0_04_TX           68
-#define        FMN_STNID_XMAC0_05_TX           69
-#define        FMN_STNID_XMAC0_06_TX           70
-#define        FMN_STNID_XMAC0_07_TX           71
-#define        FMN_STNID_XMAC0_08_TX           72
-#define        FMN_STNID_XMAC0_09_TX           73
-#define        FMN_STNID_XMAC0_10_TX           74
-#define        FMN_STNID_XMAC0_11_TX           75
-#define        FMN_STNID_XMAC0_12_TX           76
-#define        FMN_STNID_XMAC0_13_TX           77
-#define        FMN_STNID_XMAC0_14_TX           78
-#define        FMN_STNID_XMAC0_15_TX           79
-
-#define        FMN_STNID_XGS1_TX               80
-#define        FMN_STNID_XMAC1_00_TX           80
-#define        FMN_STNID_XMAC1_01_TX           81
-#define        FMN_STNID_XMAC1_02_TX           82
-#define        FMN_STNID_XMAC1_03_TX           83
-#define        FMN_STNID_XMAC1_04_TX           84
-#define        FMN_STNID_XMAC1_05_TX           85
-#define        FMN_STNID_XMAC1_06_TX           86
-#define        FMN_STNID_XMAC1_07_TX           87
-#define        FMN_STNID_XMAC1_08_TX           88
-#define        FMN_STNID_XMAC1_09_TX           89
-#define        FMN_STNID_XMAC1_10_TX           90
-#define        FMN_STNID_XMAC1_11_TX           91
-#define        FMN_STNID_XMAC1_12_TX           92
-#define        FMN_STNID_XMAC1_13_TX           93
-#define        FMN_STNID_XMAC1_14_TX           94
-#define        FMN_STNID_XMAC1_15_TX           95
-
-#define        FMN_STNID_GMAC                  96
-#define        FMN_STNID_GMACJFR_0             96
-#define        FMN_STNID_GMACRFR_0             97
-#define        FMN_STNID_GMACTX0               98
-#define        FMN_STNID_GMACTX1               99
-#define        FMN_STNID_GMACTX2               100
-#define        FMN_STNID_GMACTX3               101
-#define        FMN_STNID_GMACJFR_1             102
-#define        FMN_STNID_GMACRFR_1             103
-
-#define        FMN_STNID_DMA                   104
-#define        FMN_STNID_DMA_0                 104
-#define        FMN_STNID_DMA_1                 105
-#define        FMN_STNID_DMA_2                 106
-#define        FMN_STNID_DMA_3                 107
-
-#define        FMN_STNID_XGS0FR                112
-#define        FMN_STNID_XMAC0JFR              112
-#define        FMN_STNID_XMAC0RFR              113
-
-#define        FMN_STNID_XGS1FR                114
-#define        FMN_STNID_XMAC1JFR              114
-#define        FMN_STNID_XMAC1RFR              115
-#define        FMN_STNID_SEC                   120
-#define        FMN_STNID_SEC0                  120
-#define        FMN_STNID_SEC1                  121
-#define        FMN_STNID_SEC2                  122
-#define        FMN_STNID_SEC3                  123
-#define        FMN_STNID_PK0                   124
-#define        FMN_STNID_SEC_RSA               124
-#define        FMN_STNID_SEC_RSVD0             125
-#define        FMN_STNID_SEC_RSVD1             126
-#define        FMN_STNID_SEC_RSVD2             127
-
-#define        FMN_STNID_GMAC1                 80
-#define        FMN_STNID_GMAC1_FR_0            81
-#define        FMN_STNID_GMAC1_TX0             82
-#define        FMN_STNID_GMAC1_TX1             83
-#define        FMN_STNID_GMAC1_TX2             84
-#define        FMN_STNID_GMAC1_TX3             85
-#define        FMN_STNID_GMAC1_FR_1            87
-#define        FMN_STNID_GMAC0                 96
-#define        FMN_STNID_GMAC0_FR_0            97
-#define        FMN_STNID_GMAC0_TX0             98
-#define        FMN_STNID_GMAC0_TX1             99
-#define        FMN_STNID_GMAC0_TX2             100
-#define        FMN_STNID_GMAC0_TX3             101
-#define        FMN_STNID_GMAC0_FR_1            103
-#define        FMN_STNID_CMP_0                 108
-#define        FMN_STNID_CMP_1                 109
-#define        FMN_STNID_CMP_2                 110
-#define        FMN_STNID_CMP_3                 111
-#define        FMN_STNID_PCIE_0                116
-#define        FMN_STNID_PCIE_1                117
-#define        FMN_STNID_PCIE_2                118
-#define        FMN_STNID_PCIE_3                119
-#define        FMN_STNID_XLS_PK0               121
+#define FMN_STNID_CPU0                 0x00
+#define FMN_STNID_CPU1                 0x08
+#define FMN_STNID_CPU2                 0x10
+#define FMN_STNID_CPU3                 0x18
+#define FMN_STNID_CPU4                 0x20
+#define FMN_STNID_CPU5                 0x28
+#define FMN_STNID_CPU6                 0x30
+#define FMN_STNID_CPU7                 0x38
+
+#define FMN_STNID_XGS0_TX              64
+#define FMN_STNID_XMAC0_00_TX          64
+#define FMN_STNID_XMAC0_01_TX          65
+#define FMN_STNID_XMAC0_02_TX          66
+#define FMN_STNID_XMAC0_03_TX          67
+#define FMN_STNID_XMAC0_04_TX          68
+#define FMN_STNID_XMAC0_05_TX          69
+#define FMN_STNID_XMAC0_06_TX          70
+#define FMN_STNID_XMAC0_07_TX          71
+#define FMN_STNID_XMAC0_08_TX          72
+#define FMN_STNID_XMAC0_09_TX          73
+#define FMN_STNID_XMAC0_10_TX          74
+#define FMN_STNID_XMAC0_11_TX          75
+#define FMN_STNID_XMAC0_12_TX          76
+#define FMN_STNID_XMAC0_13_TX          77
+#define FMN_STNID_XMAC0_14_TX          78
+#define FMN_STNID_XMAC0_15_TX          79
+
+#define FMN_STNID_XGS1_TX              80
+#define FMN_STNID_XMAC1_00_TX          80
+#define FMN_STNID_XMAC1_01_TX          81
+#define FMN_STNID_XMAC1_02_TX          82
+#define FMN_STNID_XMAC1_03_TX          83
+#define FMN_STNID_XMAC1_04_TX          84
+#define FMN_STNID_XMAC1_05_TX          85
+#define FMN_STNID_XMAC1_06_TX          86
+#define FMN_STNID_XMAC1_07_TX          87
+#define FMN_STNID_XMAC1_08_TX          88
+#define FMN_STNID_XMAC1_09_TX          89
+#define FMN_STNID_XMAC1_10_TX          90
+#define FMN_STNID_XMAC1_11_TX          91
+#define FMN_STNID_XMAC1_12_TX          92
+#define FMN_STNID_XMAC1_13_TX          93
+#define FMN_STNID_XMAC1_14_TX          94
+#define FMN_STNID_XMAC1_15_TX          95
+
+#define FMN_STNID_GMAC                 96
+#define FMN_STNID_GMACJFR_0            96
+#define FMN_STNID_GMACRFR_0            97
+#define FMN_STNID_GMACTX0              98
+#define FMN_STNID_GMACTX1              99
+#define FMN_STNID_GMACTX2              100
+#define FMN_STNID_GMACTX3              101
+#define FMN_STNID_GMACJFR_1            102
+#define FMN_STNID_GMACRFR_1            103
+
+#define FMN_STNID_DMA                  104
+#define FMN_STNID_DMA_0                        104
+#define FMN_STNID_DMA_1                        105
+#define FMN_STNID_DMA_2                        106
+#define FMN_STNID_DMA_3                        107
+
+#define FMN_STNID_XGS0FR               112
+#define FMN_STNID_XMAC0JFR             112
+#define FMN_STNID_XMAC0RFR             113
+
+#define FMN_STNID_XGS1FR               114
+#define FMN_STNID_XMAC1JFR             114
+#define FMN_STNID_XMAC1RFR             115
+#define FMN_STNID_SEC                  120
+#define FMN_STNID_SEC0                 120
+#define FMN_STNID_SEC1                 121
+#define FMN_STNID_SEC2                 122
+#define FMN_STNID_SEC3                 123
+#define FMN_STNID_PK0                  124
+#define FMN_STNID_SEC_RSA              124
+#define FMN_STNID_SEC_RSVD0            125
+#define FMN_STNID_SEC_RSVD1            126
+#define FMN_STNID_SEC_RSVD2            127
+
+#define FMN_STNID_GMAC1                        80
+#define FMN_STNID_GMAC1_FR_0           81
+#define FMN_STNID_GMAC1_TX0            82
+#define FMN_STNID_GMAC1_TX1            83
+#define FMN_STNID_GMAC1_TX2            84
+#define FMN_STNID_GMAC1_TX3            85
+#define FMN_STNID_GMAC1_FR_1           87
+#define FMN_STNID_GMAC0                        96
+#define FMN_STNID_GMAC0_FR_0           97
+#define FMN_STNID_GMAC0_TX0            98
+#define FMN_STNID_GMAC0_TX1            99
+#define FMN_STNID_GMAC0_TX2            100
+#define FMN_STNID_GMAC0_TX3            101
+#define FMN_STNID_GMAC0_FR_1           103
+#define FMN_STNID_CMP_0                        108
+#define FMN_STNID_CMP_1                        109
+#define FMN_STNID_CMP_2                        110
+#define FMN_STNID_CMP_3                        111
+#define FMN_STNID_PCIE_0               116
+#define FMN_STNID_PCIE_1               117
+#define FMN_STNID_PCIE_2               118
+#define FMN_STNID_PCIE_3               119
+#define FMN_STNID_XLS_PK0              121

 
 #define nlm_read_c2_cc0(s)             __read_32bit_c2_register($16, s)
 #define nlm_read_c2_cc1(s)             __read_32bit_c2_register($17, s)
 
 #define nlm_read_c2_cc0(s)             __read_32bit_c2_register($16, s)
 #define nlm_read_c2_cc1(s)             __read_32bit_c2_register($17, s)


@@ -175,25 +175,25 @@
 #define nlm_write_c2_cc14(s, v)                __write_32bit_c2_register($30, s, v)
 #define nlm_write_c2_cc15(s, v)                __write_32bit_c2_register($31, s, v)
 
 #define nlm_write_c2_cc14(s, v)                __write_32bit_c2_register($30, s, v)
 #define nlm_write_c2_cc15(s, v)                __write_32bit_c2_register($31, s, v)
 

-#define        nlm_read_c2_status(sel)         __read_32bit_c2_register($2, 0)
-#define        nlm_read_c2_config()            __read_32bit_c2_register($3, 0)
-#define        nlm_write_c2_config(v)          __write_32bit_c2_register($3, 0, v)
-#define        nlm_read_c2_bucksize(b)         __read_32bit_c2_register($4, b)
-#define        nlm_write_c2_bucksize(b, v)     __write_32bit_c2_register($4, b, v)
-
-#define        nlm_read_c2_rx_msg0()           __read_64bit_c2_register($1, 0)
-#define        nlm_read_c2_rx_msg1()           __read_64bit_c2_register($1, 1)
-#define        nlm_read_c2_rx_msg2()           __read_64bit_c2_register($1, 2)
-#define        nlm_read_c2_rx_msg3()           __read_64bit_c2_register($1, 3)
-
-#define        nlm_write_c2_tx_msg0(v)         __write_64bit_c2_register($0, 0, v)
-#define        nlm_write_c2_tx_msg1(v)         __write_64bit_c2_register($0, 1, v)
-#define        nlm_write_c2_tx_msg2(v)         __write_64bit_c2_register($0, 2, v)
-#define        nlm_write_c2_tx_msg3(v)         __write_64bit_c2_register($0, 3, v)
-
-#define        FMN_STN_RX_QSIZE                256
-#define        FMN_NSTATIONS                   128
-#define        FMN_CORE_NBUCKETS               8
+#define nlm_read_c2_status(sel)                __read_32bit_c2_register($2, 0)
+#define nlm_read_c2_config()           __read_32bit_c2_register($3, 0)
+#define nlm_write_c2_config(v)         __write_32bit_c2_register($3, 0, v)
+#define nlm_read_c2_bucksize(b)                __read_32bit_c2_register($4, b)
+#define nlm_write_c2_bucksize(b, v)    __write_32bit_c2_register($4, b, v)
+
+#define nlm_read_c2_rx_msg0()          __read_64bit_c2_register($1, 0)
+#define nlm_read_c2_rx_msg1()          __read_64bit_c2_register($1, 1)
+#define nlm_read_c2_rx_msg2()          __read_64bit_c2_register($1, 2)
+#define nlm_read_c2_rx_msg3()          __read_64bit_c2_register($1, 3)
+
+#define nlm_write_c2_tx_msg0(v)                __write_64bit_c2_register($0, 0, v)
+#define nlm_write_c2_tx_msg1(v)                __write_64bit_c2_register($0, 1, v)
+#define nlm_write_c2_tx_msg2(v)                __write_64bit_c2_register($0, 2, v)
+#define nlm_write_c2_tx_msg3(v)                __write_64bit_c2_register($0, 3, v)
+
+#define FMN_STN_RX_QSIZE               256
+#define FMN_NSTATIONS                  128
+#define FMN_CORE_NBUCKETS              8

 
 static inline void nlm_msgsnd(unsigned int stid)
 {
 
 static inline void nlm_msgsnd(unsigned int stid)
 {

diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h
index 2e768f032e83198eba1652a57f2287a988f1d607..ff4533d6ee64f9f3c248950a707a8da895ab9482 100644 (file)
--- a/arch/mips/include/asm/netlogic/xlr/iomap.h
+++ b/arch/mips/include/asm/netlogic/xlr/iomap.h
@@ -35,66 +35,66 @@
 #ifndef _ASM_NLM_IOMAP_H
 #define _ASM_NLM_IOMAP_H
 
 #ifndef _ASM_NLM_IOMAP_H
 #define _ASM_NLM_IOMAP_H
 

-#define DEFAULT_NETLOGIC_IO_BASE           CKSEG1ADDR(0x1ef00000)
-#define NETLOGIC_IO_DDR2_CHN0_OFFSET       0x01000
-#define NETLOGIC_IO_DDR2_CHN1_OFFSET       0x02000
-#define NETLOGIC_IO_DDR2_CHN2_OFFSET       0x03000
-#define NETLOGIC_IO_DDR2_CHN3_OFFSET       0x04000
-#define NETLOGIC_IO_PIC_OFFSET             0x08000
-#define NETLOGIC_IO_UART_0_OFFSET          0x14000
-#define NETLOGIC_IO_UART_1_OFFSET          0x15100
+#define DEFAULT_NETLOGIC_IO_BASE          CKSEG1ADDR(0x1ef00000)
+#define NETLOGIC_IO_DDR2_CHN0_OFFSET      0x01000
+#define NETLOGIC_IO_DDR2_CHN1_OFFSET      0x02000
+#define NETLOGIC_IO_DDR2_CHN2_OFFSET      0x03000
+#define NETLOGIC_IO_DDR2_CHN3_OFFSET      0x04000
+#define NETLOGIC_IO_PIC_OFFSET            0x08000
+#define NETLOGIC_IO_UART_0_OFFSET         0x14000
+#define NETLOGIC_IO_UART_1_OFFSET         0x15100

 
 

-#define NETLOGIC_IO_SIZE                   0x1000
+#define NETLOGIC_IO_SIZE                  0x1000

 
 

-#define NETLOGIC_IO_BRIDGE_OFFSET          0x00000
+#define NETLOGIC_IO_BRIDGE_OFFSET         0x00000

 
 

-#define NETLOGIC_IO_RLD2_CHN0_OFFSET       0x05000
-#define NETLOGIC_IO_RLD2_CHN1_OFFSET       0x06000
+#define NETLOGIC_IO_RLD2_CHN0_OFFSET      0x05000
+#define NETLOGIC_IO_RLD2_CHN1_OFFSET      0x06000

 
 

-#define NETLOGIC_IO_SRAM_OFFSET            0x07000
+#define NETLOGIC_IO_SRAM_OFFSET                   0x07000

 
 

-#define NETLOGIC_IO_PCIX_OFFSET            0x09000
-#define NETLOGIC_IO_HT_OFFSET              0x0A000
+#define NETLOGIC_IO_PCIX_OFFSET                   0x09000
+#define NETLOGIC_IO_HT_OFFSET             0x0A000

 
 

-#define NETLOGIC_IO_SECURITY_OFFSET        0x0B000
+#define NETLOGIC_IO_SECURITY_OFFSET       0x0B000

 
 

-#define NETLOGIC_IO_GMAC_0_OFFSET          0x0C000
-#define NETLOGIC_IO_GMAC_1_OFFSET          0x0D000
-#define NETLOGIC_IO_GMAC_2_OFFSET          0x0E000
-#define NETLOGIC_IO_GMAC_3_OFFSET          0x0F000
+#define NETLOGIC_IO_GMAC_0_OFFSET         0x0C000
+#define NETLOGIC_IO_GMAC_1_OFFSET         0x0D000
+#define NETLOGIC_IO_GMAC_2_OFFSET         0x0E000
+#define NETLOGIC_IO_GMAC_3_OFFSET         0x0F000

 
 /* XLS devices */
 
 /* XLS devices */

-#define NETLOGIC_IO_GMAC_4_OFFSET          0x20000
-#define NETLOGIC_IO_GMAC_5_OFFSET          0x21000
-#define NETLOGIC_IO_GMAC_6_OFFSET          0x22000
-#define NETLOGIC_IO_GMAC_7_OFFSET          0x23000
+#define NETLOGIC_IO_GMAC_4_OFFSET         0x20000
+#define NETLOGIC_IO_GMAC_5_OFFSET         0x21000
+#define NETLOGIC_IO_GMAC_6_OFFSET         0x22000
+#define NETLOGIC_IO_GMAC_7_OFFSET         0x23000

 
 

-#define NETLOGIC_IO_PCIE_0_OFFSET          0x1E000
-#define NETLOGIC_IO_PCIE_1_OFFSET          0x1F000
-#define NETLOGIC_IO_SRIO_0_OFFSET          0x1E000
-#define NETLOGIC_IO_SRIO_1_OFFSET          0x1F000
+#define NETLOGIC_IO_PCIE_0_OFFSET         0x1E000
+#define NETLOGIC_IO_PCIE_1_OFFSET         0x1F000
+#define NETLOGIC_IO_SRIO_0_OFFSET         0x1E000
+#define NETLOGIC_IO_SRIO_1_OFFSET         0x1F000

 
 

-#define NETLOGIC_IO_USB_0_OFFSET           0x24000
-#define NETLOGIC_IO_USB_1_OFFSET           0x25000
+#define NETLOGIC_IO_USB_0_OFFSET          0x24000
+#define NETLOGIC_IO_USB_1_OFFSET          0x25000

 
 

-#define NETLOGIC_IO_COMP_OFFSET            0x1D000
+#define NETLOGIC_IO_COMP_OFFSET                   0x1D000

 /* end XLS devices */
 
 /* XLR devices */
 /* end XLS devices */
 
 /* XLR devices */

-#define NETLOGIC_IO_SPI4_0_OFFSET          0x10000
-#define NETLOGIC_IO_XGMAC_0_OFFSET         0x11000
-#define NETLOGIC_IO_SPI4_1_OFFSET          0x12000
-#define NETLOGIC_IO_XGMAC_1_OFFSET         0x13000
+#define NETLOGIC_IO_SPI4_0_OFFSET         0x10000
+#define NETLOGIC_IO_XGMAC_0_OFFSET        0x11000
+#define NETLOGIC_IO_SPI4_1_OFFSET         0x12000
+#define NETLOGIC_IO_XGMAC_1_OFFSET        0x13000

 /* end XLR devices */
 
 /* end XLR devices */
 

-#define NETLOGIC_IO_I2C_0_OFFSET           0x16000
-#define NETLOGIC_IO_I2C_1_OFFSET           0x17000
+#define NETLOGIC_IO_I2C_0_OFFSET          0x16000
+#define NETLOGIC_IO_I2C_1_OFFSET          0x17000

 
 

-#define NETLOGIC_IO_GPIO_OFFSET            0x18000
-#define NETLOGIC_IO_FLASH_OFFSET           0x19000
-#define NETLOGIC_IO_TB_OFFSET              0x1C000
+#define NETLOGIC_IO_GPIO_OFFSET                   0x18000
+#define NETLOGIC_IO_FLASH_OFFSET          0x19000
+#define NETLOGIC_IO_TB_OFFSET             0x1C000

 
 

-#define NETLOGIC_CPLD_OFFSET               KSEG1ADDR(0x1d840000)
+#define NETLOGIC_CPLD_OFFSET              KSEG1ADDR(0x1d840000)

 
 /*
  * Base Address (Virtual) of the PCI Config address space
 
 /*
  * Base Address (Virtual) of the PCI Config address space


@@ -102,8 +102,8 @@
  * Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes
  * ie 1<<24 = 16M
  */
  * Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes
  * ie 1<<24 = 16M
  */

-#define DEFAULT_PCI_CONFIG_BASE         0x18000000
-#define DEFAULT_HT_TYPE0_CFG_BASE       0x16000000
-#define DEFAULT_HT_TYPE1_CFG_BASE       0x17000000
+#define DEFAULT_PCI_CONFIG_BASE                0x18000000
+#define DEFAULT_HT_TYPE0_CFG_BASE      0x16000000
+#define DEFAULT_HT_TYPE1_CFG_BASE      0x17000000

 
 #endif
 
 #endif

diff --git a/arch/mips/include/asm/netlogic/xlr/msidef.h b/arch/mips/include/asm/netlogic/xlr/msidef.h
index 7e39d40be4f55cabc25b14ae8828cccf99cd8ef8..c95d18edf12fa7b1f796458fe25cd29ebb060c92 100644 (file)
--- a/arch/mips/include/asm/netlogic/xlr/msidef.h
+++ b/arch/mips/include/asm/netlogic/xlr/msidef.h
@@ -45,21 +45,21 @@
  */
 
 #define MSI_DATA_VECTOR_SHIFT          0
  */
 
 #define MSI_DATA_VECTOR_SHIFT          0

-#define  MSI_DATA_VECTOR_MASK          0x000000ff
+#define         MSI_DATA_VECTOR_MASK           0x000000ff

 #define         MSI_DATA_VECTOR(v)             (((v) << MSI_DATA_VECTOR_SHIFT) & \
                                                MSI_DATA_VECTOR_MASK)
 
 #define MSI_DATA_DELIVERY_MODE_SHIFT   8
 #define         MSI_DATA_VECTOR(v)             (((v) << MSI_DATA_VECTOR_SHIFT) & \
                                                MSI_DATA_VECTOR_MASK)
 
 #define MSI_DATA_DELIVERY_MODE_SHIFT   8

-#define  MSI_DATA_DELIVERY_FIXED       (0 << MSI_DATA_DELIVERY_MODE_SHIFT)
-#define  MSI_DATA_DELIVERY_LOWPRI      (1 << MSI_DATA_DELIVERY_MODE_SHIFT)
+#define         MSI_DATA_DELIVERY_FIXED        (0 << MSI_DATA_DELIVERY_MODE_SHIFT)
+#define         MSI_DATA_DELIVERY_LOWPRI       (1 << MSI_DATA_DELIVERY_MODE_SHIFT)

 
 #define MSI_DATA_LEVEL_SHIFT           14
 #define         MSI_DATA_LEVEL_DEASSERT        (0 << MSI_DATA_LEVEL_SHIFT)
 #define         MSI_DATA_LEVEL_ASSERT          (1 << MSI_DATA_LEVEL_SHIFT)
 
 #define MSI_DATA_TRIGGER_SHIFT         15
 
 #define MSI_DATA_LEVEL_SHIFT           14
 #define         MSI_DATA_LEVEL_DEASSERT        (0 << MSI_DATA_LEVEL_SHIFT)
 #define         MSI_DATA_LEVEL_ASSERT          (1 << MSI_DATA_LEVEL_SHIFT)
 
 #define MSI_DATA_TRIGGER_SHIFT         15

-#define  MSI_DATA_TRIGGER_EDGE         (0 << MSI_DATA_TRIGGER_SHIFT)
-#define  MSI_DATA_TRIGGER_LEVEL                (1 << MSI_DATA_TRIGGER_SHIFT)
+#define         MSI_DATA_TRIGGER_EDGE          (0 << MSI_DATA_TRIGGER_SHIFT)
+#define         MSI_DATA_TRIGGER_LEVEL         (1 << MSI_DATA_TRIGGER_SHIFT)

 
 /*
  * Shift/mask fields for msi address
 
 /*
  * Shift/mask fields for msi address


@@ -69,16 +69,16 @@
 #define MSI_ADDR_BASE_LO               0xfee00000
 
 #define MSI_ADDR_DEST_MODE_SHIFT       2
 #define MSI_ADDR_BASE_LO               0xfee00000
 
 #define MSI_ADDR_DEST_MODE_SHIFT       2

-#define  MSI_ADDR_DEST_MODE_PHYSICAL   (0 << MSI_ADDR_DEST_MODE_SHIFT)
+#define         MSI_ADDR_DEST_MODE_PHYSICAL    (0 << MSI_ADDR_DEST_MODE_SHIFT)

 #define         MSI_ADDR_DEST_MODE_LOGICAL     (1 << MSI_ADDR_DEST_MODE_SHIFT)
 
 #define MSI_ADDR_REDIRECTION_SHIFT     3
 #define         MSI_ADDR_DEST_MODE_LOGICAL     (1 << MSI_ADDR_DEST_MODE_SHIFT)
 
 #define MSI_ADDR_REDIRECTION_SHIFT     3

-#define  MSI_ADDR_REDIRECTION_CPU      (0 << MSI_ADDR_REDIRECTION_SHIFT)
-#define  MSI_ADDR_REDIRECTION_LOWPRI   (1 << MSI_ADDR_REDIRECTION_SHIFT)
+#define         MSI_ADDR_REDIRECTION_CPU       (0 << MSI_ADDR_REDIRECTION_SHIFT)
+#define         MSI_ADDR_REDIRECTION_LOWPRI    (1 << MSI_ADDR_REDIRECTION_SHIFT)

 
 #define MSI_ADDR_DEST_ID_SHIFT         12
 #define         MSI_ADDR_DEST_ID_MASK          0x00ffff0
 
 #define MSI_ADDR_DEST_ID_SHIFT         12
 #define         MSI_ADDR_DEST_ID_MASK          0x00ffff0

-#define  MSI_ADDR_DEST_ID(dest)                (((dest) << MSI_ADDR_DEST_ID_SHIFT) & \
+#define         MSI_ADDR_DEST_ID(dest)         (((dest) << MSI_ADDR_DEST_ID_SHIFT) & \

                                                 MSI_ADDR_DEST_ID_MASK)
 
 #endif /* ASM_RMI_MSIDEF_H */
                                                 MSI_ADDR_DEST_ID_MASK)
 
 #endif /* ASM_RMI_MSIDEF_H */

diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h
index 9a691b1f91baf7275dfd6282554cd0ec2a30c8d3..2f549453585e44524fb49c319f74e3fcdfd50019 100644 (file)
--- a/arch/mips/include/asm/netlogic/xlr/pic.h
+++ b/arch/mips/include/asm/netlogic/xlr/pic.h
@@ -116,7 +116,7 @@
 #define PIC_TIMER_COUNT_0_BASE         0x120
 #define PIC_TIMER_COUNT_1_BASE         0x130
 
 #define PIC_TIMER_COUNT_0_BASE         0x120
 #define PIC_TIMER_COUNT_1_BASE         0x130
 

-#define PIC_IRT_0(picintr)      (PIC_IRT_0_BASE + (picintr))
+#define PIC_IRT_0(picintr)     (PIC_IRT_0_BASE + (picintr))

 #define PIC_IRT_1(picintr)     (PIC_IRT_1_BASE + (picintr))
 
 #define PIC_TIMER_MAXVAL_0(i)  (PIC_TIMER_MAXVAL_0_BASE + (i))
 #define PIC_IRT_1(picintr)     (PIC_IRT_1_BASE + (picintr))
 
 #define PIC_TIMER_MAXVAL_0(i)  (PIC_TIMER_MAXVAL_0_BASE + (i))


@@ -130,9 +130,9 @@
  * 8-39. This leaves the IRQ 0-7 for cpu interrupts like
  * count/compare and FMN
  */
  * 8-39. This leaves the IRQ 0-7 for cpu interrupts like
  * count/compare and FMN
  */

-#define PIC_IRQ_BASE            8
-#define PIC_INTR_TO_IRQ(i)      (PIC_IRQ_BASE + (i))
-#define PIC_IRQ_TO_INTR(i)      ((i) - PIC_IRQ_BASE)
+#define PIC_IRQ_BASE           8
+#define PIC_INTR_TO_IRQ(i)     (PIC_IRQ_BASE + (i))
+#define PIC_IRQ_TO_INTR(i)     ((i) - PIC_IRQ_BASE)

 
 #define PIC_IRT_FIRST_IRQ      PIC_IRQ_BASE
 #define PIC_WD_IRQ             PIC_INTR_TO_IRQ(PIC_IRT_WD_INDEX)
 
 #define PIC_IRT_FIRST_IRQ      PIC_IRQ_BASE
 #define PIC_WD_IRQ             PIC_INTR_TO_IRQ(PIC_IRT_WD_INDEX)


@@ -168,7 +168,7 @@
 #define PIC_BRIDGE_AERR_IRQ    PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_INDEX)
 #define PIC_BRIDGE_BERR_IRQ    PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_BERR_INDEX)
 #define PIC_BRIDGE_TB_XLR_IRQ  PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLR_INDEX)
 #define PIC_BRIDGE_AERR_IRQ    PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_INDEX)
 #define PIC_BRIDGE_BERR_IRQ    PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_BERR_INDEX)
 #define PIC_BRIDGE_TB_XLR_IRQ  PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_TB_XLR_INDEX)

-#define PIC_BRIDGE_AERR_NMI_IRQ        PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_NMI_INDEX)
+#define PIC_BRIDGE_AERR_NMI_IRQ PIC_INTR_TO_IRQ(PIC_IRT_BRIDGE_AERR_NMI_INDEX)

 /* XLS defines */
 #define PIC_GMAC_4_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_GMAC4_INDEX)
 #define PIC_GMAC_5_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_GMAC5_INDEX)
 /* XLS defines */
 #define PIC_GMAC_4_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_GMAC4_INDEX)
 #define PIC_GMAC_5_IRQ         PIC_INTR_TO_IRQ(PIC_IRT_GMAC5_INDEX)

diff --git a/arch/mips/include/asm/nile4.h b/arch/mips/include/asm/nile4.h
index af0e51a9f68a879b8a139124755ff64ecf8b8702..2e2436d0e94ed17a323a1197cd145426fc001d4a 100644 (file)
--- a/arch/mips/include/asm/nile4.h
+++ b/arch/mips/include/asm/nile4.h
@@ -2,7 +2,7 @@
  *  asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions
  *
  *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
  *  asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions
  *
  *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>

- *                     Sony Software Development Center Europe (SDCE), Brussels
+ *                    Sony Software Development Center Europe (SDCE), Brussels

  *
  *  This file is based on the following documentation:
  *
  *
  *  This file is based on the following documentation:
  *


@@ -17,7 +17,7 @@
 
 
     /*
 
 
     /*

-     *  Physical Device Address Registers (PDARs)
+     * Physical Device Address Registers (PDARs)

      */
 
 #define NILE4_SDRAM0   0x0000  /* SDRAM Bank 0 [R/W] */
      */
 
 #define NILE4_SDRAM0   0x0000  /* SDRAM Bank 0 [R/W] */


@@ -37,7 +37,7 @@
 
 
     /*
 
 
     /*

-     *  CPU Interface Registers
+     * CPU Interface Registers

      */
 
 #define NILE4_CPUSTAT  0x0080  /* CPU Status [R/W] */
      */
 
 #define NILE4_CPUSTAT  0x0080  /* CPU Status [R/W] */


@@ -50,7 +50,7 @@
 
 
     /*
 
 
     /*

-     *  Memory-Interface Registers
+     * Memory-Interface Registers

      */
 
 #define NILE4_MEMCTRL  0x00C0  /* Memory Control */
      */
 
 #define NILE4_MEMCTRL  0x00C0  /* Memory Control */


@@ -59,7 +59,7 @@
 
 
     /*
 
 
     /*

-     *  PCI-Bus Registers
+     * PCI-Bus Registers

      */
 
 #define NILE4_PCICTRL  0x00E0  /* PCI Control [R/W] */
      */
 
 #define NILE4_PCICTRL  0x00E0  /* PCI Control [R/W] */


@@ -70,7 +70,7 @@
 
 
     /*
 
 
     /*

-     *  Local-Bus Registers
+     * Local-Bus Registers

      */
 
 #define NILE4_LCNFG    0x0100  /* Local Bus Configuration [R/W] */
      */
 
 #define NILE4_LCNFG    0x0100  /* Local Bus Configuration [R/W] */


@@ -88,7 +88,7 @@
 
 
     /*
 
 
     /*

-     *  DMA Registers
+     * DMA Registers

      */
 
 #define NILE4_DMACTRL0 0x0180  /* DMA Control 0 [R/W] */
      */
 
 #define NILE4_DMACTRL0 0x0180  /* DMA Control 0 [R/W] */


@@ -100,7 +100,7 @@
 
 
     /*
 
 
     /*

-     *  Timer Registers
+     * Timer Registers

      */
 
 #define NILE4_T0CTRL   0x01C0  /* SDRAM Refresh Control [R/W] */
      */
 
 #define NILE4_T0CTRL   0x01C0  /* SDRAM Refresh Control [R/W] */


@@ -114,7 +114,7 @@
 
 
     /*
 
 
     /*

-     *  PCI Configuration Space Registers
+     * PCI Configuration Space Registers

      */
 
 #define NILE4_PCI_BASE 0x0200
      */
 
 #define NILE4_PCI_BASE 0x0200


@@ -153,10 +153,10 @@
 
 
     /*
 
 
     /*

-     *  Serial-Port Registers
+     * Serial-Port Registers

      */
 
      */
 

-#define NILE4_UART_BASE        0x0300
+#define NILE4_UART_BASE 0x0300

 
 #define NILE4_UARTRBR  0x0300  /* UART Receiver Data Buffer [R] */
 #define NILE4_UARTTHR  0x0300  /* UART Transmitter Data Holding [W] */
 
 #define NILE4_UARTRBR  0x0300  /* UART Receiver Data Buffer [R] */
 #define NILE4_UARTTHR  0x0300  /* UART Transmitter Data Holding [W] */


@@ -175,7 +175,7 @@
 
 
     /*
 
 
     /*

-     *  Interrupt Lines
+     * Interrupt Lines

      */
 
 #define NILE4_INT_CPCE 0       /* CPU-Interface Parity-Error Interrupt */
      */
 
 #define NILE4_INT_CPCE 0       /* CPU-Interface Parity-Error Interrupt */


@@ -185,7 +185,7 @@
 #define NILE4_INT_UART 4       /* UART Interrupt */
 #define NILE4_INT_WDOG 5       /* Watchdog Timer Interrupt */
 #define NILE4_INT_GPT  6       /* General-Purpose Timer Interrupt */
 #define NILE4_INT_UART 4       /* UART Interrupt */
 #define NILE4_INT_WDOG 5       /* Watchdog Timer Interrupt */
 #define NILE4_INT_GPT  6       /* General-Purpose Timer Interrupt */

-#define NILE4_INT_LBRTD        7       /* Local-Bus Ready Timer Interrupt */
+#define NILE4_INT_LBRTD 7      /* Local-Bus Ready Timer Interrupt */

 #define NILE4_INT_INTA 8       /* PCI Interrupt Signal INTA# */
 #define NILE4_INT_INTB 9       /* PCI Interrupt Signal INTB# */
 #define NILE4_INT_INTC 10      /* PCI Interrupt Signal INTC# */
 #define NILE4_INT_INTA 8       /* PCI Interrupt Signal INTA# */
 #define NILE4_INT_INTB 9       /* PCI Interrupt Signal INTB# */
 #define NILE4_INT_INTC 10      /* PCI Interrupt Signal INTC# */


@@ -197,7 +197,7 @@
 
 
     /*
 
 
     /*

-     *  Nile 4 Register Access
+     * Nile 4 Register Access

      */
 
 static inline void nile4_sync(void)
      */
 
 static inline void nile4_sync(void)


@@ -247,7 +247,7 @@ static inline u8 nile4_in8(u32 offset)
 
 
     /*
 
 
     /*

-     *  Physical Device Address Registers
+     * Physical Device Address Registers

      */
 
 extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width,
      */
 
 extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width,


@@ -255,7 +255,7 @@ extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width,
 
 
     /*
 
 
     /*

-     *  PCI Master Registers
+     * PCI Master Registers

      */
 
 #define NILE4_PCICMD_IACK      0       /* PCI Interrupt Acknowledge */
      */
 
 #define NILE4_PCICMD_IACK      0       /* PCI Interrupt Acknowledge */


@@ -265,9 +265,9 @@ extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width,
 
 
     /*
 
 
     /*

-     *  PCI Address Spaces
+     * PCI Address Spaces

      *
      *

-     *  Note that these are multiplexed using PCIINIT[01]!
+     * Note that these are multiplexed using PCIINIT[01]!

      */
 
 #define NILE4_PCI_IO_BASE      0xa6000000
      */
 
 #define NILE4_PCI_IO_BASE      0xa6000000


@@ -280,7 +280,7 @@ extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr);
 
 
     /*
 
 
     /*

-     *  Interrupt Programming
+     * Interrupt Programming

      */
 
 #define NUM_I8259_INTERRUPTS   16
      */
 
 #define NUM_I8259_INTERRUPTS   16

diff --git a/arch/mips/include/asm/octeon/cvmx-address.h b/arch/mips/include/asm/octeon/cvmx-address.h
index 3c74d826e2e6265c37a271636a61b1365e947a81..e2d874e681f6d9bed7d5fecdb8fdee3241710180 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-address.h
+++ b/arch/mips/include/asm/octeon/cvmx-address.h
@@ -84,20 +84,20 @@ typedef enum {
  * Octeon-I HW never interprets this X (<39:36> reserved
  * for future expansion), software should set to 0.
  *
  * Octeon-I HW never interprets this X (<39:36> reserved
  * for future expansion), software should set to 0.
  *

- *  - 0x0 XXX0 0000 0000 to      DRAM         Cached
+ *  - 0x0 XXX0 0000 0000 to     DRAM         Cached

  *  - 0x0 XXX0 0FFF FFFF
  *
  *  - 0x0 XXX0 0FFF FFFF
  *

- *  - 0x0 XXX0 1000 0000 to      Boot Bus     Uncached  (Converted to 0x1 00X0 1000 0000
- *  - 0x0 XXX0 1FFF FFFF         + EJTAG                           to 0x1 00X0 1FFF FFFF)
+ *  - 0x0 XXX0 1000 0000 to     Boot Bus     Uncached  (Converted to 0x1 00X0 1000 0000
+ *  - 0x0 XXX0 1FFF FFFF        + EJTAG                           to 0x1 00X0 1FFF FFFF)

  *
  *

- *  - 0x0 XXX0 2000 0000 to      DRAM         Cached
+ *  - 0x0 XXX0 2000 0000 to     DRAM         Cached

  *  - 0x0 XXXF FFFF FFFF
  *
  *  - 0x0 XXXF FFFF FFFF
  *

- *  - 0x1 00X0 0000 0000 to      Boot Bus     Uncached
+ *  - 0x1 00X0 0000 0000 to     Boot Bus     Uncached

  *  - 0x1 00XF FFFF FFFF
  *
  *  - 0x1 00XF FFFF FFFF
  *

- *  - 0x1 01X0 0000 0000 to      Other NCB    Uncached
- *  - 0x1 FFXF FFFF FFFF         devices
+ *  - 0x1 01X0 0000 0000 to     Other NCB    Uncached
+ *  - 0x1 FFXF FFFF FFFF        devices

  *
  * Decode of all Octeon addresses
  */
  *
  * Decode of all Octeon addresses
  */


@@ -129,9 +129,9 @@ typedef union {
         */
        struct {
                uint64_t R:2;   /* CVMX_MIPS_SPACE_XKPHYS in this case */
         */
        struct {
                uint64_t R:2;   /* CVMX_MIPS_SPACE_XKPHYS in this case */

-               uint64_t cca:3; /* ignored by octeon */
+               uint64_t cca:3; /* ignored by octeon */

                uint64_t mbz:10;
                uint64_t mbz:10;

-               uint64_t pa:49; /* physical address */
+               uint64_t pa:49; /* physical address */

        } sxkphys;
 
        /* physical address */
        } sxkphys;
 
        /* physical address */


@@ -253,22 +253,22 @@ typedef union {
 #define CVMX_OCT_DID_ASX1 23ULL
 #define CVMX_OCT_DID_IOB 30ULL
 
 #define CVMX_OCT_DID_ASX1 23ULL
 #define CVMX_OCT_DID_IOB 30ULL
 

-#define CVMX_OCT_DID_PKT_SEND       CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL)
-#define CVMX_OCT_DID_TAG_SWTAG      CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL)
-#define CVMX_OCT_DID_TAG_TAG1       CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL)
-#define CVMX_OCT_DID_TAG_TAG2       CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL)
-#define CVMX_OCT_DID_TAG_TAG3       CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL)
+#define CVMX_OCT_DID_PKT_SEND      CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL)
+#define CVMX_OCT_DID_TAG_SWTAG     CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL)
+#define CVMX_OCT_DID_TAG_TAG1      CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL)
+#define CVMX_OCT_DID_TAG_TAG2      CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL)
+#define CVMX_OCT_DID_TAG_TAG3      CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL)

 #define CVMX_OCT_DID_TAG_NULL_RD    CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL)
 #define CVMX_OCT_DID_TAG_NULL_RD    CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL)

-#define CVMX_OCT_DID_TAG_CSR        CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL)
-#define CVMX_OCT_DID_FAU_FAI        CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL)
-#define CVMX_OCT_DID_TIM_CSR        CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL)
-#define CVMX_OCT_DID_KEY_RW         CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL)
-#define CVMX_OCT_DID_PCI_6          CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL)
-#define CVMX_OCT_DID_MIS_BOO        CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL)
-#define CVMX_OCT_DID_PCI_RML        CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL)
-#define CVMX_OCT_DID_IPD_CSR        CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL)
-#define CVMX_OCT_DID_DFA_CSR        CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL)
-#define CVMX_OCT_DID_MIS_CSR        CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL)
-#define CVMX_OCT_DID_ZIP_CSR        CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL)
+#define CVMX_OCT_DID_TAG_CSR       CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL)
+#define CVMX_OCT_DID_FAU_FAI       CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL)
+#define CVMX_OCT_DID_TIM_CSR       CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL)
+#define CVMX_OCT_DID_KEY_RW        CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL)
+#define CVMX_OCT_DID_PCI_6         CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL)
+#define CVMX_OCT_DID_MIS_BOO       CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL)
+#define CVMX_OCT_DID_PCI_RML       CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL)
+#define CVMX_OCT_DID_IPD_CSR       CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL)
+#define CVMX_OCT_DID_DFA_CSR       CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL)
+#define CVMX_OCT_DID_MIS_CSR       CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL)
+#define CVMX_OCT_DID_ZIP_CSR       CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL)

 
 #endif /* __CVMX_ADDRESS_H__ */
 
 #endif /* __CVMX_ADDRESS_H__ */

diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
index 1db1dc2724cb2c5ed74a83ae9fe8da05490e4c23..284fa8d773ba0774126b2387c15805110c961b82 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -91,11 +91,11 @@ struct cvmx_bootinfo {
 #if (CVMX_BOOTINFO_MIN_VER >= 1)
        /*
         * Several boards support compact flash on the Octeon boot
 #if (CVMX_BOOTINFO_MIN_VER >= 1)
        /*
         * Several boards support compact flash on the Octeon boot

-        * bus.  The CF memory spaces may be mapped to different
+        * bus.  The CF memory spaces may be mapped to different

         * addresses on different boards.  These are the physical
         * addresses, so care must be taken to use the correct
         * XKPHYS/KSEG0 addressing depending on the application's
         * addresses on different boards.  These are the physical
         * addresses, so care must be taken to use the correct
         * XKPHYS/KSEG0 addressing depending on the application's

-        * ABI.  These values will be 0 if CF is not present.
+        * ABI.  These values will be 0 if CF is not present.

         */
        uint64_t compact_flash_common_base_addr;
        uint64_t compact_flash_attribute_base_addr;
         */
        uint64_t compact_flash_common_base_addr;
        uint64_t compact_flash_attribute_base_addr;


@@ -131,7 +131,7 @@ struct cvmx_bootinfo {
 #define CVMX_BOOTINFO_CFG_FLAG_NO_MAGIC                        (1ull << 3)
 /* This flag is set if the TLB mappings are not contained in the
  * 0x10000000 - 0x20000000 boot bus region. */
 #define CVMX_BOOTINFO_CFG_FLAG_NO_MAGIC                        (1ull << 3)
 /* This flag is set if the TLB mappings are not contained in the
  * 0x10000000 - 0x20000000 boot bus region. */

-#define CVMX_BOOTINFO_CFG_FLAG_OVERSIZE_TLB_MAPPING     (1ull << 4)
+#define CVMX_BOOTINFO_CFG_FLAG_OVERSIZE_TLB_MAPPING    (1ull << 4)

 #define CVMX_BOOTINFO_CFG_FLAG_BREAK                   (1ull << 5)
 
 #endif /*   (CVMX_BOOTINFO_MAJ_VER == 1) */
 #define CVMX_BOOTINFO_CFG_FLAG_BREAK                   (1ull << 5)
 
 #endif /*   (CVMX_BOOTINFO_MAJ_VER == 1) */


@@ -164,9 +164,9 @@ enum cvmx_board_types_enum {
        CVMX_BOARD_TYPE_EBT5600 = 22,
        CVMX_BOARD_TYPE_EBH5201 = 23,
        CVMX_BOARD_TYPE_EBT5200 = 24,
        CVMX_BOARD_TYPE_EBT5600 = 22,
        CVMX_BOARD_TYPE_EBH5201 = 23,
        CVMX_BOARD_TYPE_EBT5200 = 24,

-       CVMX_BOARD_TYPE_CB5600  = 25,
-       CVMX_BOARD_TYPE_CB5601  = 26,
-       CVMX_BOARD_TYPE_CB5200  = 27,
+       CVMX_BOARD_TYPE_CB5600  = 25,
+       CVMX_BOARD_TYPE_CB5601  = 26,
+       CVMX_BOARD_TYPE_CB5200  = 27,

        /* Special 'generic' board type, supports many boards */
        CVMX_BOARD_TYPE_GENERIC = 28,
        CVMX_BOARD_TYPE_EBH5610 = 29,
        /* Special 'generic' board type, supports many boards */
        CVMX_BOARD_TYPE_GENERIC = 28,
        CVMX_BOARD_TYPE_EBH5610 = 29,


@@ -223,7 +223,7 @@ enum cvmx_board_types_enum {
        CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000,
 
        /*
        CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000,
 
        /*

-        * Set aside a range for customer private use.  The SDK won't
+        * Set aside a range for customer private use.  The SDK won't

         * use any numbers in this range.
         */
        CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
         * use any numbers in this range.
         */
        CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,

diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h
index 42db2be663f15a7ea68cdd3ade30083bdc0030cc..352f1dc2508bcd7cbea9866ec6528f57fb2cda9e 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-bootmem.h
+++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h
@@ -39,7 +39,7 @@
 #define CVMX_BOOTMEM_NUM_NAMED_BLOCKS 64
 
 /* minimum alignment of bootmem alloced blocks */
 #define CVMX_BOOTMEM_NUM_NAMED_BLOCKS 64
 
 /* minimum alignment of bootmem alloced blocks */

-#define CVMX_BOOTMEM_ALIGNMENT_SIZE     (16ull)
+#define CVMX_BOOTMEM_ALIGNMENT_SIZE    (16ull)

 
 /* Flags for cvmx_bootmem_phy_mem* functions */
 /* Allocate from end of block instead of beginning */
 
 /* Flags for cvmx_bootmem_phy_mem* functions */
 /* Allocate from end of block instead of beginning */


@@ -151,8 +151,8 @@ extern void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment);
  * memory cannot be allocated at the specified address.
  *
  * @size:      Size in bytes of block to allocate
  * memory cannot be allocated at the specified address.
  *
  * @size:      Size in bytes of block to allocate

- * @address:   Physical address to allocate memory at.  If this memory is not
- *                  available, the allocation fails.
+ * @address:   Physical address to allocate memory at. If this memory is not
+ *                 available, the allocation fails.

  * @alignment: Alignment required - must be power of 2
  * Returns pointer to block of memory, NULL on error
  */
  * @alignment: Alignment required - must be power of 2
  * Returns pointer to block of memory, NULL on error
  */


@@ -181,7 +181,7 @@ extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment,
  * @name:   name of block to free
  *
  * Returns 0 on failure,
  * @name:   name of block to free
  *
  * Returns 0 on failure,

- *         !0 on success
+ *        !0 on success

  */
 
 
  */
 
 


@@ -210,9 +210,9 @@ extern void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment,
  *
  * @size:     Size in bytes of block to allocate
  * @address:  Physical address to allocate memory at.  If this
  *
  * @size:     Size in bytes of block to allocate
  * @address:  Physical address to allocate memory at.  If this

- *            memory is not available, the allocation fails.
+ *           memory is not available, the allocation fails.

  * @name:     name of block - must be less than CVMX_BOOTMEM_NAME_LEN
  * @name:     name of block - must be less than CVMX_BOOTMEM_NAME_LEN

- *            bytes
+ *           bytes

  *
  * Returns a pointer to block of memory, NULL on error
  */
  *
  * Returns a pointer to block of memory, NULL on error
  */


@@ -249,7 +249,7 @@ extern int cvmx_bootmem_free_named(char *name);
  * @name:   name of block to free
  *
  * Returns pointer to named block descriptor on success
  * @name:   name of block to free
  *
  * Returns pointer to named block descriptor on success

- *         0 on failure
+ *        0 on failure

  */
 struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name);
 
  */
 struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name);
 


@@ -258,20 +258,20 @@ struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name);
  * (optional) requested address and alignment.
  *
  * @req_size: size of region to allocate.  All requests are rounded up
  * (optional) requested address and alignment.
  *
  * @req_size: size of region to allocate.  All requests are rounded up

- *            to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE bytes size
+ *           to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE bytes size

  *
  * @address_min: Minimum address that block can occupy.
  *
  * @address_max: Specifies the maximum address_min (inclusive) that
  *
  * @address_min: Minimum address that block can occupy.
  *
  * @address_max: Specifies the maximum address_min (inclusive) that

- *               the allocation can use.
+ *              the allocation can use.

  *
  * @alignment: Requested alignment of the block.  If this alignment
  *
  * @alignment: Requested alignment of the block.  If this alignment

- *             cannot be met, the allocation fails.  This must be a
- *             power of 2.  (Note: Alignment of
- *             CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and
- *             internally enforced.  Requested alignments of less than
- *             CVMX_BOOTMEM_ALIGNMENT_SIZE are set to
- *             CVMX_BOOTMEM_ALIGNMENT_SIZE.)
+ *            cannot be met, the allocation fails.  This must be a
+ *            power of 2.  (Note: Alignment of
+ *            CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and
+ *            internally enforced.  Requested alignments of less than
+ *            CVMX_BOOTMEM_ALIGNMENT_SIZE are set to
+ *            CVMX_BOOTMEM_ALIGNMENT_SIZE.)

  *
  * @flags:     Flags to control options for the allocation.
  *
  *
  * @flags:     Flags to control options for the allocation.
  *


@@ -285,21 +285,21 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min,
  * Allocates a named block of physical memory from the free list, at
  * (optional) requested address and alignment.
  *
  * Allocates a named block of physical memory from the free list, at
  * (optional) requested address and alignment.
  *

- * @param size      size of region to allocate.  All requests are rounded
- *                  up to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE
- *                  bytes size
+ * @param size     size of region to allocate.  All requests are rounded
+ *                 up to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE
+ *                 bytes size

  * @param min_addr Minimum address that block can occupy.
  * @param max_addr  Specifies the maximum address_min (inclusive) that
  * @param min_addr Minimum address that block can occupy.
  * @param max_addr  Specifies the maximum address_min (inclusive) that

- *                  the allocation can use.
+ *                 the allocation can use.

  * @param alignment Requested alignment of the block.  If this
  * @param alignment Requested alignment of the block.  If this

- *                  alignment cannot be met, the allocation fails.
- *                  This must be a power of 2.  (Note: Alignment of
- *                  CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and
- *                  internally enforced.  Requested alignments of less
- *                  than CVMX_BOOTMEM_ALIGNMENT_SIZE are set to
- *                  CVMX_BOOTMEM_ALIGNMENT_SIZE.)
- * @param name      name to assign to named block
- * @param flags     Flags to control options for the allocation.
+ *                 alignment cannot be met, the allocation fails.
+ *                 This must be a power of 2.  (Note: Alignment of
+ *                 CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and
+ *                 internally enforced.  Requested alignments of less
+ *                 than CVMX_BOOTMEM_ALIGNMENT_SIZE are set to
+ *                 CVMX_BOOTMEM_ALIGNMENT_SIZE.)
+ * @param name     name to assign to named block
+ * @param flags            Flags to control options for the allocation.

  *
  * @return physical address of block allocated, or -1 on failure
  */
  *
  * @return physical address of block allocated, or -1 on failure
  */


@@ -312,14 +312,14 @@ int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr,
  * Finds a named memory block by name.
  * Also used for finding an unused entry in the named block table.
  *
  * Finds a named memory block by name.
  * Also used for finding an unused entry in the named block table.
  *

- * @name: Name of memory block to find.  If NULL pointer given, then
- *        finds unused descriptor, if available.
+ * @name: Name of memory block to find.         If NULL pointer given, then
+ *       finds unused descriptor, if available.

  *
  * @flags: Flags to control options for the allocation.
  *
  * Returns Pointer to memory block descriptor, NULL if not found.
  *
  * @flags: Flags to control options for the allocation.
  *
  * Returns Pointer to memory block descriptor, NULL if not found.

- *         If NULL returned when name parameter is NULL, then no memory
- *         block descriptors are available.
+ *        If NULL returned when name parameter is NULL, then no memory
+ *        block descriptors are available.

  */
 struct cvmx_bootmem_named_block_desc *
 cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags);
  */
 struct cvmx_bootmem_named_block_desc *
 cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags);


@@ -331,31 +331,31 @@ cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags);
  * @flags:  flags for passing options
  *
  * Returns 0 on failure
  * @flags:  flags for passing options
  *
  * Returns 0 on failure

- *         1 on success
+ *        1 on success

  */
 int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags);
 
 /**
  */
 int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags);
 
 /**

- * Frees a block to the bootmem allocator list.  This must
+ * Frees a block to the bootmem allocator list.         This must

  * be used with care, as the size provided must match the size
  * of the block that was allocated, or the list will become
  * corrupted.
  *
  * IMPORTANT:  This is only intended to be used as part of named block
  * frees and initial population of the free memory list.
  * be used with care, as the size provided must match the size
  * of the block that was allocated, or the list will become
  * corrupted.
  *
  * IMPORTANT:  This is only intended to be used as part of named block
  * frees and initial population of the free memory list.

- *                                                      *
+ *                                                     *

  *
  * @phy_addr: physical address of block
  * @size:     size of block in bytes.
  * @flags:    flags for passing options
  *
  * Returns 1 on success,
  *
  * @phy_addr: physical address of block
  * @size:     size of block in bytes.
  * @flags:    flags for passing options
  *
  * Returns 1 on success,

- *         0 on failure
+ *        0 on failure

  */
 int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags);
 
 /**
  */
 int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags);
 
 /**

- * Locks the bootmem allocator.  This is useful in certain situations
+ * Locks the bootmem allocator.         This is useful in certain situations

  * where multiple allocations must be made without being interrupted.
  * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag.
  *
  * where multiple allocations must be made without being interrupted.
  * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag.
  *

diff --git a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
index fed91125317f07432bd20d4b76d48230127e2135..024a71b2bff91d641c22259db0c8b8451bf8b09a 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
+++ b/arch/mips/include/asm/octeon/cvmx-cmd-queue.h
@@ -244,33 +244,33 @@ static inline void __cvmx_cmd_queue_lock(cvmx_cmd_queue_id_t queue_id,
                ".set noreorder\n"
                "1:\n"
                /* Atomic add one to ticket_ptr */
                ".set noreorder\n"
                "1:\n"
                /* Atomic add one to ticket_ptr */

-               "ll     %[my_ticket], %[ticket_ptr]\n"
+               "ll     %[my_ticket], %[ticket_ptr]\n"

                /* and store the original value */
                /* and store the original value */

-               "li     %[ticket], 1\n"
+               "li     %[ticket], 1\n"

                /* in my_ticket */
                /* in my_ticket */

-               "baddu  %[ticket], %[my_ticket]\n"
-               "sc     %[ticket], %[ticket_ptr]\n"
-               "beqz   %[ticket], 1b\n"
+               "baddu  %[ticket], %[my_ticket]\n"
+               "sc     %[ticket], %[ticket_ptr]\n"
+               "beqz   %[ticket], 1b\n"

                " nop\n"
                /* Load the current now_serving ticket */
                " nop\n"
                /* Load the current now_serving ticket */

-               "lbu    %[ticket], %[now_serving]\n"
+               "lbu    %[ticket], %[now_serving]\n"

                "2:\n"
                /* Jump out if now_serving == my_ticket */
                "2:\n"
                /* Jump out if now_serving == my_ticket */

-               "beq    %[ticket], %[my_ticket], 4f\n"
+               "beq    %[ticket], %[my_ticket], 4f\n"

                /* Find out how many tickets are in front of me */
                /* Find out how many tickets are in front of me */

-               " subu   %[ticket], %[my_ticket], %[ticket]\n"
+               " subu   %[ticket], %[my_ticket], %[ticket]\n"

                /* Use tickets in front of me minus one to delay */
                "subu  %[ticket], 1\n"
                /* Delay will be ((tickets in front)-1)*32 loops */
                /* Use tickets in front of me minus one to delay */
                "subu  %[ticket], 1\n"
                /* Delay will be ((tickets in front)-1)*32 loops */

-               "cins   %[ticket], %[ticket], 5, 7\n"
+               "cins   %[ticket], %[ticket], 5, 7\n"

                "3:\n"
                /* Loop here until our ticket might be up */
                "3:\n"
                /* Loop here until our ticket might be up */

-               "bnez   %[ticket], 3b\n"
-               " subu  %[ticket], 1\n"
+               "bnez   %[ticket], 3b\n"
+               " subu  %[ticket], 1\n"

                /* Jump back up to check out ticket again */
                /* Jump back up to check out ticket again */

-               "b      2b\n"
+               "b      2b\n"

                /* Load the current now_serving ticket */
                /* Load the current now_serving ticket */

-               " lbu   %[ticket], %[now_serving]\n"
+               " lbu   %[ticket], %[now_serving]\n"

                "4:\n"
                ".set pop\n" :
                [ticket_ptr] "=m"(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]),
                "4:\n"
                ".set pop\n" :
                [ticket_ptr] "=m"(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]),


@@ -313,9 +313,9 @@ static inline __cvmx_cmd_queue_state_t
  *
  * @queue_id:  Hardware command queue to write to
  * @use_locking:
  *
  * @queue_id:  Hardware command queue to write to
  * @use_locking:

- *                  Use internal locking to ensure exclusive access for queue
- *                  updates. If you don't use this locking you must ensure
- *                  exclusivity some other way. Locking is strongly recommended.
+ *                 Use internal locking to ensure exclusive access for queue
+ *                 updates. If you don't use this locking you must ensure
+ *                 exclusivity some other way. Locking is strongly recommended.

  * @cmd_count: Number of command words to write
  * @cmds:      Array of commands to write
  *
  * @cmd_count: Number of command words to write
  * @cmds:      Array of commands to write
  *


@@ -411,9 +411,9 @@ static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write(cvmx_cmd_queue_id_t
  *
  * @queue_id: Hardware command queue to write to
  * @use_locking:
  *
  * @queue_id: Hardware command queue to write to
  * @use_locking:

- *                 Use internal locking to ensure exclusive access for queue
- *                 updates. If you don't use this locking you must ensure
- *                 exclusivity some other way. Locking is strongly recommended.
+ *                Use internal locking to ensure exclusive access for queue
+ *                updates. If you don't use this locking you must ensure
+ *                exclusivity some other way. Locking is strongly recommended.

  * @cmd1:     Command
  * @cmd2:     Command
  *
  * @cmd1:     Command
  * @cmd2:     Command
  *


@@ -510,9 +510,9 @@ static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write2(cvmx_cmd_queue_id_t
  *
  * @queue_id: Hardware command queue to write to
  * @use_locking:
  *
  * @queue_id: Hardware command queue to write to
  * @use_locking:

- *                 Use internal locking to ensure exclusive access for queue
- *                 updates. If you don't use this locking you must ensure
- *                 exclusivity some other way. Locking is strongly recommended.
+ *                Use internal locking to ensure exclusive access for queue
+ *                updates. If you don't use this locking you must ensure
+ *                exclusivity some other way. Locking is strongly recommended.

  * @cmd1:     Command
  * @cmd2:     Command
  * @cmd3:     Command
  * @cmd1:     Command
  * @cmd2:     Command
  * @cmd3:     Command

diff --git a/arch/mips/include/asm/octeon/cvmx-config.h b/arch/mips/include/asm/octeon/cvmx-config.h
index 26835d1b43b87633f0d4ebbcfa09947fd33c6112..f7dd17d0dc22d600c7f42282d42d12ed4cf3b19d 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-config.h
+++ b/arch/mips/include/asm/octeon/cvmx-config.h
@@ -31,13 +31,13 @@
 
 /* Pools in use */
 /* Packet buffers */
 
 /* Pools in use */
 /* Packet buffers */

-#define CVMX_FPA_PACKET_POOL                (0)
-#define CVMX_FPA_PACKET_POOL_SIZE           CVMX_FPA_POOL_0_SIZE
+#define CVMX_FPA_PACKET_POOL               (0)
+#define CVMX_FPA_PACKET_POOL_SIZE          CVMX_FPA_POOL_0_SIZE

 /* Work queue entrys */
 /* Work queue entrys */

-#define CVMX_FPA_WQE_POOL                   (1)
-#define CVMX_FPA_WQE_POOL_SIZE              CVMX_FPA_POOL_1_SIZE
+#define CVMX_FPA_WQE_POOL                  (1)
+#define CVMX_FPA_WQE_POOL_SIZE             CVMX_FPA_POOL_1_SIZE

 /* PKO queue command buffers */
 /* PKO queue command buffers */

-#define CVMX_FPA_OUTPUT_BUFFER_POOL         (2)
+#define CVMX_FPA_OUTPUT_BUFFER_POOL        (2)

 #define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE    CVMX_FPA_POOL_2_SIZE
 
 /*************************  FAU allocation ********************************/
 #define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE    CVMX_FPA_POOL_2_SIZE
 
 /*************************  FAU allocation ********************************/


@@ -45,7 +45,7 @@
  * in order of descending size so that all alignment constraints are
  * automatically met.  The enums are linked so that the following enum
  * continues allocating where the previous one left off, so the
  * in order of descending size so that all alignment constraints are
  * automatically met.  The enums are linked so that the following enum
  * continues allocating where the previous one left off, so the

- * numbering within each enum always starts with zero.  The macros
+ * numbering within each enum always starts with zero. The macros

  * take care of the address increment size, so the values entered
  * always increase by 1.  FAU registers are accessed with byte
  * addresses.
  * take care of the address increment size, so the values entered
  * always increase by 1.  FAU registers are accessed with byte
  * addresses.


@@ -90,9 +90,9 @@ typedef enum {
  * be taken into account.
  */
 /* Generic scratch iobdma area */
  * be taken into account.
  */
 /* Generic scratch iobdma area */

-#define CVMX_SCR_SCRATCH               (0)
+#define CVMX_SCR_SCRATCH              (0)

 /* First location available after cvmx-config.h allocated region. */
 /* First location available after cvmx-config.h allocated region. */

-#define CVMX_SCR_REG_AVAIL_BASE        (8)
+#define CVMX_SCR_REG_AVAIL_BASE               (8)

 
 /*
  * CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve
 
 /*
  * CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve


@@ -145,14 +145,14 @@ typedef enum {
  * 1: include
  */
 #define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP      0
  * 1: include
  */
 #define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP      0

-#define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP      0
-#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT    0
-#define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT    0
-#define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER         0
+#define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP      0
+#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT    0
+#define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT    0
+#define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER 0

 #define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP      0
 #define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP      0

-#define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP      0
-#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT    0
-#define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT    0
+#define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP      0
+#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT    0
+#define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT    0

 #define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL    0
 #define CVMX_HELPER_INPUT_TAG_INPUT_PORT       1
 
 #define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL    0
 #define CVMX_HELPER_INPUT_TAG_INPUT_PORT       1
 

diff --git a/arch/mips/include/asm/octeon/cvmx-fau.h b/arch/mips/include/asm/octeon/cvmx-fau.h
index a6939fc8ba188110dc2730927cb46c00856e0ca3..ef98f7fc102f27cb2a011dc1d2546dec1934dc06 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-fau.h
+++ b/arch/mips/include/asm/octeon/cvmx-fau.h
@@ -37,13 +37,13 @@
  */
 
 #define CVMX_FAU_LOAD_IO_ADDRESS    cvmx_build_io_address(0x1e, 0)
  */
 
 #define CVMX_FAU_LOAD_IO_ADDRESS    cvmx_build_io_address(0x1e, 0)

-#define CVMX_FAU_BITS_SCRADDR       63, 56
-#define CVMX_FAU_BITS_LEN           55, 48
-#define CVMX_FAU_BITS_INEVAL        35, 14
-#define CVMX_FAU_BITS_TAGWAIT       13, 13
-#define CVMX_FAU_BITS_NOADD         13, 13
-#define CVMX_FAU_BITS_SIZE          12, 11
-#define CVMX_FAU_BITS_REGISTER      10, 0
+#define CVMX_FAU_BITS_SCRADDR      63, 56
+#define CVMX_FAU_BITS_LEN          55, 48
+#define CVMX_FAU_BITS_INEVAL       35, 14
+#define CVMX_FAU_BITS_TAGWAIT      13, 13
+#define CVMX_FAU_BITS_NOADD        13, 13
+#define CVMX_FAU_BITS_SIZE         12, 11
+#define CVMX_FAU_BITS_REGISTER     10, 0

 
 typedef enum {
        CVMX_FAU_OP_SIZE_8 = 0,
 
 typedef enum {
        CVMX_FAU_OP_SIZE_8 = 0,


@@ -109,11 +109,11 @@ typedef union {
  * Builds a store I/O address for writing to the FAU
  *
  * @noadd:  0 = Store value is atomically added to the current value
  * Builds a store I/O address for writing to the FAU
  *
  * @noadd:  0 = Store value is atomically added to the current value

- *               1 = Store value is atomically written over the current value
+ *              1 = Store value is atomically written over the current value

  * @reg:    FAU atomic register to access. 0 <= reg < 2048.
  * @reg:    FAU atomic register to access. 0 <= reg < 2048.

- *               - Step by 2 for 16 bit access.
- *               - Step by 4 for 32 bit access.
- *               - Step by 8 for 64 bit access.
+ *              - Step by 2 for 16 bit access.
+ *              - Step by 4 for 32 bit access.
+ *              - Step by 8 for 64 bit access.

  * Returns Address to store for atomic update
  */
 static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg)
  * Returns Address to store for atomic update
  */
 static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg)


@@ -127,16 +127,16 @@ static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg)
  * Builds a I/O address for accessing the FAU
  *
  * @tagwait: Should the atomic add wait for the current tag switch
  * Builds a I/O address for accessing the FAU
  *
  * @tagwait: Should the atomic add wait for the current tag switch

- *                operation to complete.
- *                - 0 = Don't wait
- *                - 1 = Wait for tag switch to complete
+ *               operation to complete.
+ *               - 0 = Don't wait
+ *               - 1 = Wait for tag switch to complete

  * @reg:     FAU atomic register to access. 0 <= reg < 2048.
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.

- *                - Step by 2 for 16 bit access.
- *                - Step by 4 for 32 bit access.
- *                - Step by 8 for 64 bit access.
+ *               - Step by 2 for 16 bit access.
+ *               - Step by 4 for 32 bit access.
+ *               - Step by 8 for 64 bit access.

  * @value:   Signed value to add.
  * @value:   Signed value to add.

- *                Note: When performing 32 and 64 bit access, only the low
- *                22 bits are available.
+ *               Note: When performing 32 and 64 bit access, only the low
+ *               22 bits are available.

  * Returns Address to read from for atomic update
  */
 static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg,
  * Returns Address to read from for atomic update
  */
 static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg,


@@ -152,9 +152,9 @@ static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg,
  * Perform an atomic 64 bit add
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.
  * Perform an atomic 64 bit add
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.

- *                - Step by 8 for 64 bit access.
+ *               - Step by 8 for 64 bit access.

  * @value:   Signed value to add.
  * @value:   Signed value to add.

- *                Note: Only the low 22 bits are available.
+ *               Note: Only the low 22 bits are available.

  * Returns Value of the register before the update
  */
 static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg,
  * Returns Value of the register before the update
  */
 static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg,


@@ -167,9 +167,9 @@ static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg,
  * Perform an atomic 32 bit add
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.
  * Perform an atomic 32 bit add
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.

- *                - Step by 4 for 32 bit access.
+ *               - Step by 4 for 32 bit access.

  * @value:   Signed value to add.
  * @value:   Signed value to add.

- *                Note: Only the low 22 bits are available.
+ *               Note: Only the low 22 bits are available.

  * Returns Value of the register before the update
  */
 static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg,
  * Returns Value of the register before the update
  */
 static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg,


@@ -182,7 +182,7 @@ static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg,
  * Perform an atomic 16 bit add
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.
  * Perform an atomic 16 bit add
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.

- *                - Step by 2 for 16 bit access.
+ *               - Step by 2 for 16 bit access.

  * @value:   Signed value to add.
  * Returns Value of the register before the update
  */
  * @value:   Signed value to add.
  * Returns Value of the register before the update
  */


@@ -209,12 +209,12 @@ static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
  * completes
  *
  * @reg:    FAU atomic register to access. 0 <= reg < 2048.
  * completes
  *
  * @reg:    FAU atomic register to access. 0 <= reg < 2048.

- *               - Step by 8 for 64 bit access.
+ *              - Step by 8 for 64 bit access.

  * @value:  Signed value to add.
  * @value:  Signed value to add.

- *               Note: Only the low 22 bits are available.
+ *              Note: Only the low 22 bits are available.

  * Returns If a timeout occurs, the error bit will be set. Otherwise
  * Returns If a timeout occurs, the error bit will be set. Otherwise

- *         the value of the register before the update will be
- *         returned
+ *        the value of the register before the update will be
+ *        returned

  */
 static inline cvmx_fau_tagwait64_t
 cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value)
  */
 static inline cvmx_fau_tagwait64_t
 cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value)


@@ -233,12 +233,12 @@ cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value)
  * completes
  *
  * @reg:    FAU atomic register to access. 0 <= reg < 2048.
  * completes
  *
  * @reg:    FAU atomic register to access. 0 <= reg < 2048.

- *               - Step by 4 for 32 bit access.
+ *              - Step by 4 for 32 bit access.

  * @value:  Signed value to add.
  * @value:  Signed value to add.

- *               Note: Only the low 22 bits are available.
+ *              Note: Only the low 22 bits are available.

  * Returns If a timeout occurs, the error bit will be set. Otherwise
  * Returns If a timeout occurs, the error bit will be set. Otherwise

- *         the value of the register before the update will be
- *         returned
+ *        the value of the register before the update will be
+ *        returned

  */
 static inline cvmx_fau_tagwait32_t
 cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value)
  */
 static inline cvmx_fau_tagwait32_t
 cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value)


@@ -257,11 +257,11 @@ cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value)
  * completes
  *
  * @reg:    FAU atomic register to access. 0 <= reg < 2048.
  * completes
  *
  * @reg:    FAU atomic register to access. 0 <= reg < 2048.

- *               - Step by 2 for 16 bit access.
+ *              - Step by 2 for 16 bit access.

  * @value:  Signed value to add.
  * Returns If a timeout occurs, the error bit will be set. Otherwise
  * @value:  Signed value to add.
  * Returns If a timeout occurs, the error bit will be set. Otherwise

- *         the value of the register before the update will be
- *         returned
+ *        the value of the register before the update will be
+ *        returned

  */
 static inline cvmx_fau_tagwait16_t
 cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value)
  */
 static inline cvmx_fau_tagwait16_t
 cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value)


@@ -282,8 +282,8 @@ cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value)
  * @reg:    FAU atomic register to access. 0 <= reg < 2048.
  * @value:  Signed value to add.
  * Returns If a timeout occurs, the error bit will be set. Otherwise
  * @reg:    FAU atomic register to access. 0 <= reg < 2048.
  * @value:  Signed value to add.
  * Returns If a timeout occurs, the error bit will be set. Otherwise

- *         the value of the register before the update will be
- *         returned
+ *        the value of the register before the update will be
+ *        returned

  */
 static inline cvmx_fau_tagwait8_t
 cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
  */
 static inline cvmx_fau_tagwait8_t
 cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)


@@ -301,21 +301,21 @@ cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value)
  *
  * @scraddr: Scratch pad byte address to write to.  Must be 8 byte aligned
  * @value:   Signed value to add.
  *
  * @scraddr: Scratch pad byte address to write to.  Must be 8 byte aligned
  * @value:   Signed value to add.

- *                Note: When performing 32 and 64 bit access, only the low
- *                22 bits are available.
+ *               Note: When performing 32 and 64 bit access, only the low
+ *               22 bits are available.

  * @tagwait: Should the atomic add wait for the current tag switch
  * @tagwait: Should the atomic add wait for the current tag switch

- *                operation to complete.
- *                - 0 = Don't wait
- *                - 1 = Wait for tag switch to complete
+ *               operation to complete.
+ *               - 0 = Don't wait
+ *               - 1 = Wait for tag switch to complete

  * @size:    The size of the operation:
  * @size:    The size of the operation:

- *                - CVMX_FAU_OP_SIZE_8  (0) = 8 bits
- *                - CVMX_FAU_OP_SIZE_16 (1) = 16 bits
- *                - CVMX_FAU_OP_SIZE_32 (2) = 32 bits
- *                - CVMX_FAU_OP_SIZE_64 (3) = 64 bits
+ *               - CVMX_FAU_OP_SIZE_8  (0) = 8 bits
+ *               - CVMX_FAU_OP_SIZE_16 (1) = 16 bits
+ *               - CVMX_FAU_OP_SIZE_32 (2) = 32 bits
+ *               - CVMX_FAU_OP_SIZE_64 (3) = 64 bits

  * @reg:     FAU atomic register to access. 0 <= reg < 2048.
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.

- *                - Step by 2 for 16 bit access.
- *                - Step by 4 for 32 bit access.
- *                - Step by 8 for 64 bit access.
+ *               - Step by 2 for 16 bit access.
+ *               - Step by 4 for 32 bit access.
+ *               - Step by 8 for 64 bit access.

  * Returns Data to write using cvmx_send_single
  */
 static inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value,
  * Returns Data to write using cvmx_send_single
  */
 static inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value,


@@ -337,11 +337,11 @@ static inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value,
  * placed in the scratch memory at byte address scraddr.
  *
  * @scraddr: Scratch memory byte address to put response in.
  * placed in the scratch memory at byte address scraddr.
  *
  * @scraddr: Scratch memory byte address to put response in.

- *                Must be 8 byte aligned.
+ *               Must be 8 byte aligned.

  * @reg:     FAU atomic register to access. 0 <= reg < 2048.
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.

- *                - Step by 8 for 64 bit access.
+ *               - Step by 8 for 64 bit access.

  * @value:   Signed value to add.
  * @value:   Signed value to add.

- *                Note: Only the low 22 bits are available.
+ *               Note: Only the low 22 bits are available.

  * Returns Placed in the scratch pad register
  */
 static inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr,
  * Returns Placed in the scratch pad register
  */
 static inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr,


@@ -357,11 +357,11 @@ static inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr,
  * placed in the scratch memory at byte address scraddr.
  *
  * @scraddr: Scratch memory byte address to put response in.
  * placed in the scratch memory at byte address scraddr.
  *
  * @scraddr: Scratch memory byte address to put response in.

- *                Must be 8 byte aligned.
+ *               Must be 8 byte aligned.

  * @reg:     FAU atomic register to access. 0 <= reg < 2048.
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.

- *                - Step by 4 for 32 bit access.
+ *               - Step by 4 for 32 bit access.

  * @value:   Signed value to add.
  * @value:   Signed value to add.

- *                Note: Only the low 22 bits are available.
+ *               Note: Only the low 22 bits are available.

  * Returns Placed in the scratch pad register
  */
 static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr,
  * Returns Placed in the scratch pad register
  */
 static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr,


@@ -377,9 +377,9 @@ static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr,
  * placed in the scratch memory at byte address scraddr.
  *
  * @scraddr: Scratch memory byte address to put response in.
  * placed in the scratch memory at byte address scraddr.
  *
  * @scraddr: Scratch memory byte address to put response in.

- *                Must be 8 byte aligned.
+ *               Must be 8 byte aligned.

  * @reg:     FAU atomic register to access. 0 <= reg < 2048.
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.

- *                - Step by 2 for 16 bit access.
+ *               - Step by 2 for 16 bit access.

  * @value:   Signed value to add.
  * Returns Placed in the scratch pad register
  */
  * @value:   Signed value to add.
  * Returns Placed in the scratch pad register
  */


@@ -396,7 +396,7 @@ static inline void cvmx_fau_async_fetch_and_add16(uint64_t scraddr,
  * placed in the scratch memory at byte address scraddr.
  *
  * @scraddr: Scratch memory byte address to put response in.
  * placed in the scratch memory at byte address scraddr.
  *
  * @scraddr: Scratch memory byte address to put response in.

- *                Must be 8 byte aligned.
+ *               Must be 8 byte aligned.

  * @reg:     FAU atomic register to access. 0 <= reg < 2048.
  * @value:   Signed value to add.
  * Returns Placed in the scratch pad register
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.
  * @value:   Signed value to add.
  * Returns Placed in the scratch pad register


@@ -414,14 +414,14 @@ static inline void cvmx_fau_async_fetch_and_add8(uint64_t scraddr,
  * switch completes.
  *
  * @scraddr: Scratch memory byte address to put response in.  Must be
  * switch completes.
  *
  * @scraddr: Scratch memory byte address to put response in.  Must be

- *           8 byte aligned.  If a timeout occurs, the error bit (63)
- *           will be set. Otherwise the value of the register before
- *           the update will be returned
+ *          8 byte aligned.  If a timeout occurs, the error bit (63)
+ *          will be set. Otherwise the value of the register before
+ *          the update will be returned

  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.

- *                - Step by 8 for 64 bit access.
+ *               - Step by 8 for 64 bit access.

  * @value:   Signed value to add.
  * @value:   Signed value to add.

- *                Note: Only the low 22 bits are available.
+ *               Note: Only the low 22 bits are available.

  * Returns Placed in the scratch pad register
  */
 static inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr,
  * Returns Placed in the scratch pad register
  */
 static inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr,


@@ -437,14 +437,14 @@ static inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr,
  * switch completes.
  *
  * @scraddr: Scratch memory byte address to put response in.  Must be
  * switch completes.
  *
  * @scraddr: Scratch memory byte address to put response in.  Must be

- *           8 byte aligned.  If a timeout occurs, the error bit (63)
- *           will be set. Otherwise the value of the register before
- *           the update will be returned
+ *          8 byte aligned.  If a timeout occurs, the error bit (63)
+ *          will be set. Otherwise the value of the register before
+ *          the update will be returned

  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.

- *                - Step by 4 for 32 bit access.
+ *               - Step by 4 for 32 bit access.

  * @value:   Signed value to add.
  * @value:   Signed value to add.

- *                Note: Only the low 22 bits are available.
+ *               Note: Only the low 22 bits are available.

  * Returns Placed in the scratch pad register
  */
 static inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr,
  * Returns Placed in the scratch pad register
  */
 static inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr,


@@ -460,12 +460,12 @@ static inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr,
  * switch completes.
  *
  * @scraddr: Scratch memory byte address to put response in.  Must be
  * switch completes.
  *
  * @scraddr: Scratch memory byte address to put response in.  Must be

- *           8 byte aligned.  If a timeout occurs, the error bit (63)
- *           will be set. Otherwise the value of the register before
- *           the update will be returned
+ *          8 byte aligned.  If a timeout occurs, the error bit (63)
+ *          will be set. Otherwise the value of the register before
+ *          the update will be returned

  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.

- *                - Step by 2 for 16 bit access.
+ *               - Step by 2 for 16 bit access.

  * @value:   Signed value to add.
  *
  * Returns Placed in the scratch pad register
  * @value:   Signed value to add.
  *
  * Returns Placed in the scratch pad register


@@ -483,9 +483,9 @@ static inline void cvmx_fau_async_tagwait_fetch_and_add16(uint64_t scraddr,
  * switch completes.
  *
  * @scraddr: Scratch memory byte address to put response in.  Must be
  * switch completes.
  *
  * @scraddr: Scratch memory byte address to put response in.  Must be

- *           8 byte aligned.  If a timeout occurs, the error bit (63)
- *           will be set. Otherwise the value of the register before
- *           the update will be returned
+ *          8 byte aligned.  If a timeout occurs, the error bit (63)
+ *          will be set. Otherwise the value of the register before
+ *          the update will be returned

  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.
  * @value:   Signed value to add.
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.
  * @value:   Signed value to add.


@@ -504,7 +504,7 @@ static inline void cvmx_fau_async_tagwait_fetch_and_add8(uint64_t scraddr,
  * Perform an atomic 64 bit add
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.
  * Perform an atomic 64 bit add
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.

- *                - Step by 8 for 64 bit access.
+ *               - Step by 8 for 64 bit access.

  * @value:   Signed value to add.
  */
 static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value)
  * @value:   Signed value to add.
  */
 static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value)


@@ -516,7 +516,7 @@ static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value)
  * Perform an atomic 32 bit add
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.
  * Perform an atomic 32 bit add
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.

- *                - Step by 4 for 32 bit access.
+ *               - Step by 4 for 32 bit access.

  * @value:   Signed value to add.
  */
 static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value)
  * @value:   Signed value to add.
  */
 static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value)


@@ -528,7 +528,7 @@ static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value)
  * Perform an atomic 16 bit add
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.
  * Perform an atomic 16 bit add
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.

- *                - Step by 2 for 16 bit access.
+ *               - Step by 2 for 16 bit access.

  * @value:   Signed value to add.
  */
 static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value)
  * @value:   Signed value to add.
  */
 static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value)


@@ -551,7 +551,7 @@ static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value)
  * Perform an atomic 64 bit write
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.
  * Perform an atomic 64 bit write
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.

- *                - Step by 8 for 64 bit access.
+ *               - Step by 8 for 64 bit access.

  * @value:   Signed value to write.
  */
 static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value)
  * @value:   Signed value to write.
  */
 static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value)


@@ -563,7 +563,7 @@ static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value)
  * Perform an atomic 32 bit write
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.
  * Perform an atomic 32 bit write
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.

- *                - Step by 4 for 32 bit access.
+ *               - Step by 4 for 32 bit access.

  * @value:   Signed value to write.
  */
 static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value)
  * @value:   Signed value to write.
  */
 static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value)


@@ -575,7 +575,7 @@ static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value)
  * Perform an atomic 16 bit write
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.
  * Perform an atomic 16 bit write
  *
  * @reg:     FAU atomic register to access. 0 <= reg < 2048.

- *                - Step by 2 for 16 bit access.
+ *               - Step by 2 for 16 bit access.

  * @value:   Signed value to write.
  */
 static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value)
  * @value:   Signed value to write.
  */
 static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value)

diff --git a/arch/mips/include/asm/octeon/cvmx-fpa.h b/arch/mips/include/asm/octeon/cvmx-fpa.h
index 541a1ae02b6f7079db6e09a87baa918a8df6fa09..aa26a2ce5a0e44cb2daf3b808e736125f659edd1 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-fpa.h
+++ b/arch/mips/include/asm/octeon/cvmx-fpa.h
@@ -39,9 +39,9 @@
 #include <asm/octeon/cvmx-address.h>
 #include <asm/octeon/cvmx-fpa-defs.h>
 
 #include <asm/octeon/cvmx-address.h>
 #include <asm/octeon/cvmx-fpa-defs.h>
 

-#define CVMX_FPA_NUM_POOLS      8
+#define CVMX_FPA_NUM_POOLS     8

 #define CVMX_FPA_MIN_BLOCK_SIZE 128
 #define CVMX_FPA_MIN_BLOCK_SIZE 128

-#define CVMX_FPA_ALIGNMENT      128
+#define CVMX_FPA_ALIGNMENT     128

 
 /**
  * Structure describing the data format used for stores to the FPA.
 
 /**
  * Structure describing the data format used for stores to the FPA.


@@ -186,8 +186,8 @@ static inline void *cvmx_fpa_alloc(uint64_t pool)
 /**
  * Asynchronously get a new block from the FPA
  *
 /**
  * Asynchronously get a new block from the FPA
  *

- * @scr_addr: Local scratch address to put response in.  This is a byte address,
- *                  but must be 8 byte aligned.
+ * @scr_addr: Local scratch address to put response in.         This is a byte address,
+ *                 but must be 8 byte aligned.

  * @pool:      Pool to get the block from
  */
 static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool)
  * @pool:      Pool to get the block from
  */
 static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool)


@@ -212,7 +212,7 @@ static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool)
  * @ptr:    Block to free
  * @pool:   Pool to put it in
  * @num_cache_lines:
  * @ptr:    Block to free
  * @pool:   Pool to put it in
  * @num_cache_lines:

- *               Cache lines to invalidate
+ *              Cache lines to invalidate

  */
 static inline void cvmx_fpa_free_nosync(void *ptr, uint64_t pool,
                                        uint64_t num_cache_lines)
  */
 static inline void cvmx_fpa_free_nosync(void *ptr, uint64_t pool,
                                        uint64_t num_cache_lines)


@@ -234,7 +234,7 @@ static inline void cvmx_fpa_free_nosync(void *ptr, uint64_t pool,
  * @ptr:    Block to free
  * @pool:   Pool to put it in
  * @num_cache_lines:
  * @ptr:    Block to free
  * @pool:   Pool to put it in
  * @num_cache_lines:

- *               Cache lines to invalidate
+ *              Cache lines to invalidate

  */
 static inline void cvmx_fpa_free(void *ptr, uint64_t pool,
                                 uint64_t num_cache_lines)
  */
 static inline void cvmx_fpa_free(void *ptr, uint64_t pool,
                                 uint64_t num_cache_lines)


@@ -245,7 +245,7 @@ static inline void cvmx_fpa_free(void *ptr, uint64_t pool,
            CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool));
        /*
         * Make sure that any previous writes to memory go out before
            CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool));
        /*
         * Make sure that any previous writes to memory go out before

-        * we free this buffer.  This also serves as a barrier to
+        * we free this buffer.  This also serves as a barrier to

         * prevent GCC from reordering operations to after the
         * free.
         */
         * prevent GCC from reordering operations to after the
         * free.
         */


@@ -259,17 +259,17 @@ static inline void cvmx_fpa_free(void *ptr, uint64_t pool,
  * This can only be called once per pool. Make sure proper
  * locking enforces this.
  *
  * This can only be called once per pool. Make sure proper
  * locking enforces this.
  *

- * @pool:       Pool to initialize
- *                   0 <= pool < 8
- * @name:       Constant character string to name this pool.
- *                   String is not copied.
- * @buffer:     Pointer to the block of memory to use. This must be
- *                   accessible by all processors and external hardware.
+ * @pool:      Pool to initialize
+ *                  0 <= pool < 8
+ * @name:      Constant character string to name this pool.
+ *                  String is not copied.
+ * @buffer:    Pointer to the block of memory to use. This must be
+ *                  accessible by all processors and external hardware.

  * @block_size: Size for each block controlled by the FPA
  * @num_blocks: Number of blocks
  *
  * Returns 0 on Success,
  * @block_size: Size for each block controlled by the FPA
  * @num_blocks: Number of blocks
  *
  * Returns 0 on Success,

- *         -1 on failure
+ *        -1 on failure

  */
 extern int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer,
                               uint64_t block_size, uint64_t num_blocks);
  */
 extern int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer,
                               uint64_t block_size, uint64_t num_blocks);


@@ -282,8 +282,8 @@ extern int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer,
  *
  * @pool:   Pool to shutdown
  * Returns Zero on success
  *
  * @pool:   Pool to shutdown
  * Returns Zero on success

- *         - Positive is count of missing buffers
- *         - Negative is too many buffers or corrupted pointers
+ *        - Positive is count of missing buffers
+ *        - Negative is too many buffers or corrupted pointers

  */
 extern uint64_t cvmx_fpa_shutdown_pool(uint64_t pool);
 
  */
 extern uint64_t cvmx_fpa_shutdown_pool(uint64_t pool);
 

diff --git a/arch/mips/include/asm/octeon/cvmx-helper-board.h b/arch/mips/include/asm/octeon/cvmx-helper-board.h
index 442f508eaac9c421da95dcd714c34eb3a1027cd4..41785dd0ddd0a0923583d06b39c8ce84e1fbb347 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-helper-board.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-board.h
@@ -48,7 +48,7 @@ typedef enum {
  * Fake IPD port, the RGMII/MII interface may use different PHY, use
  * this macro to return appropriate MIX address to read the PHY.
  */
  * Fake IPD port, the RGMII/MII interface may use different PHY, use
  * this macro to return appropriate MIX address to read the PHY.
  */

-#define CVMX_HELPER_BOARD_MGMT_IPD_PORT     -10
+#define CVMX_HELPER_BOARD_MGMT_IPD_PORT            -10

 
 /**
  * cvmx_override_board_link_get(int ipd_port) is a function
 
 /**
  * cvmx_override_board_link_get(int ipd_port) is a function


@@ -86,10 +86,10 @@ extern int cvmx_helper_board_get_mii_address(int ipd_port);
  *
  * @phy_addr:  The address of the PHY to program
  * @link_flags:
  *
  * @phy_addr:  The address of the PHY to program
  * @link_flags:

- *                  Flags to control autonegotiation.  Bit 0 is autonegotiation
- *                  enable/disable to maintain backware compatibility.
+ *                 Flags to control autonegotiation.  Bit 0 is autonegotiation
+ *                 enable/disable to maintain backware compatibility.

  * @link_info: Link speed to program. If the speed is zero and autonegotiation
  * @link_info: Link speed to program. If the speed is zero and autonegotiation

- *                  is enabled, all possible negotiation speeds are advertised.
+ *                 is enabled, all possible negotiation speeds are advertised.

  *
  * Returns Zero on success, negative on failure
  */
  *
  * Returns Zero on success, negative on failure
  */


@@ -111,10 +111,10 @@ int cvmx_helper_board_link_set_phy(int phy_addr,
  * enumeration from the bootloader.
  *
  * @ipd_port: IPD input port associated with the port we want to get link
  * enumeration from the bootloader.
  *
  * @ipd_port: IPD input port associated with the port we want to get link

- *                 status for.
+ *                status for.

  *
  * Returns The ports link status. If the link isn't fully resolved, this must
  *
  * Returns The ports link status. If the link isn't fully resolved, this must

- *         return zero.
+ *        return zero.

  */
 extern cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port);
 
  */
 extern cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port);
 


@@ -134,10 +134,10 @@ extern cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port);
  *
  * @interface: Interface to probe
  * @supported_ports:
  *
  * @interface: Interface to probe
  * @supported_ports:

- *                  Number of ports Octeon supports.
+ *                 Number of ports Octeon supports.

  *
  * Returns Number of ports the actual board supports. Many times this will
  *
  * Returns Number of ports the actual board supports. Many times this will

- *         simple be "support_ports".
+ *        simple be "support_ports".

  */
 extern int __cvmx_helper_board_interface_probe(int interface,
                                               int supported_ports);
  */
 extern int __cvmx_helper_board_interface_probe(int interface,
                                               int supported_ports);

diff --git a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
index 78295ba0050f6d4a8085ade41f7797cd42932a7f..4d7a3db3a9f69fc4c0deaf3ef5039fcf0f90b09f 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-rgmii.h
@@ -98,9 +98,9 @@ extern int __cvmx_helper_rgmii_link_set(int ipd_port,
  *
  * @ipd_port: IPD/PKO port to loopback.
  * @enable_internal:
  *
  * @ipd_port: IPD/PKO port to loopback.
  * @enable_internal:

- *                 Non zero if you want internal loopback
+ *                Non zero if you want internal loopback

  * @enable_external:
  * @enable_external:

- *                 Non zero if you want external loopback
+ *                Non zero if you want external loopback

  *
  * Returns Zero on success, negative on failure.
  */
  *
  * Returns Zero on success, negative on failure.
  */

diff --git a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
index 9a9b6c103ede600bfe6576e598e1344a762f978b..4debb1c5153d692e3b983abec214ad9df23b3a79 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-sgmii.h
@@ -92,9 +92,9 @@ extern int __cvmx_helper_sgmii_link_set(int ipd_port,
  *
  * @ipd_port: IPD/PKO port to loopback.
  * @enable_internal:
  *
  * @ipd_port: IPD/PKO port to loopback.
  * @enable_internal:

- *                 Non zero if you want internal loopback
+ *                Non zero if you want internal loopback

  * @enable_external:
  * @enable_external:

- *                 Non zero if you want external loopback
+ *                Non zero if you want external loopback

  *
  * Returns Zero on success, negative on failure.
  */
  *
  * Returns Zero on success, negative on failure.
  */

diff --git a/arch/mips/include/asm/octeon/cvmx-helper-util.h b/arch/mips/include/asm/octeon/cvmx-helper-util.h
index 6a6e52fc22c1a23a702fb221e24f7d1009ed0e5a..e217aba1f5234aef1bbb62653de481539421003c 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-helper-util.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-util.h
@@ -57,11 +57,11 @@ extern int cvmx_helper_dump_packet(cvmx_wqe_t *work);
  *
  * @queue:  Input queue to setup RED on (0-7)
  * @pass_thresh:
  *
  * @queue:  Input queue to setup RED on (0-7)
  * @pass_thresh:

- *               Packets will begin slowly dropping when there are less than
- *               this many packet buffers free in FPA 0.
+ *              Packets will begin slowly dropping when there are less than
+ *              this many packet buffers free in FPA 0.

  * @drop_thresh:
  * @drop_thresh:

- *               All incomming packets will be dropped when there are less
- *               than this many free packet buffers in FPA 0.
+ *              All incomming packets will be dropped when there are less
+ *              than this many free packet buffers in FPA 0.

  * Returns Zero on success. Negative on failure
  */
 extern int cvmx_helper_setup_red_queue(int queue, int pass_thresh,
  * Returns Zero on success. Negative on failure
  */
 extern int cvmx_helper_setup_red_queue(int queue, int pass_thresh,


@@ -71,11 +71,11 @@ extern int cvmx_helper_setup_red_queue(int queue, int pass_thresh,
  * Setup Random Early Drop to automatically begin dropping packets.
  *
  * @pass_thresh:
  * Setup Random Early Drop to automatically begin dropping packets.
  *
  * @pass_thresh:

- *               Packets will begin slowly dropping when there are less than
- *               this many packet buffers free in FPA 0.
+ *              Packets will begin slowly dropping when there are less than
+ *              this many packet buffers free in FPA 0.

  * @drop_thresh:
  * @drop_thresh:

- *               All incomming packets will be dropped when there are less
- *               than this many free packet buffers in FPA 0.
+ *              All incomming packets will be dropped when there are less
+ *              than this many free packet buffers in FPA 0.

  * Returns Zero on success. Negative on failure
  */
 extern int cvmx_helper_setup_red(int pass_thresh, int drop_thresh);
  * Returns Zero on success. Negative on failure
  */
 extern int cvmx_helper_setup_red(int pass_thresh, int drop_thresh);


@@ -84,7 +84,7 @@ extern int cvmx_helper_setup_red(int pass_thresh, int drop_thresh);
  * Get the version of the CVMX libraries.
  *
  * Returns Version string. Note this buffer is allocated statically
  * Get the version of the CVMX libraries.
  *
  * Returns Version string. Note this buffer is allocated statically

- *         and will be shared by all callers.
+ *        and will be shared by all callers.

  */
 extern const char *cvmx_helper_get_version(void);
 
  */
 extern const char *cvmx_helper_get_version(void);
 

diff --git a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
index f6fbc4f45b561f5a6b9cc13a8c44c0d1993b2954..5e89ed703eaa7f85dd777443bdaef2d1026471b3 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper-xaui.h
@@ -92,9 +92,9 @@ extern int __cvmx_helper_xaui_link_set(int ipd_port,
  *
  * @ipd_port: IPD/PKO port to loopback.
  * @enable_internal:
  *
  * @ipd_port: IPD/PKO port to loopback.
  * @enable_internal:

- *                 Non zero if you want internal loopback
+ *                Non zero if you want internal loopback

  * @enable_external:
  * @enable_external:

- *                 Non zero if you want external loopback
+ *                Non zero if you want external loopback

  *
  * Returns Zero on success, negative on failure.
  */
  *
  * Returns Zero on success, negative on failure.
  */

diff --git a/arch/mips/include/asm/octeon/cvmx-helper.h b/arch/mips/include/asm/octeon/cvmx-helper.h
index 691c8142cd4fc08cecc07d3123a49c6053d67f65..5a3090dc6f2f530f810111c4d9fc206164d98a50 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-helper.h
+++ b/arch/mips/include/asm/octeon/cvmx-helper.h
@@ -93,12 +93,12 @@ extern void (*cvmx_override_ipd_port_setup) (int ipd_port);
 /**
  * This function enables the IPD and also enables the packet interfaces.
  * The packet interfaces (RGMII and SPI) must be enabled after the
 /**
  * This function enables the IPD and also enables the packet interfaces.
  * The packet interfaces (RGMII and SPI) must be enabled after the

- * IPD.  This should be called by the user program after any additional
+ * IPD.         This should be called by the user program after any additional

  * IPD configuration changes are made if CVMX_HELPER_ENABLE_IPD
  * is not set in the executive-config.h file.
  *
  * Returns 0 on success
  * IPD configuration changes are made if CVMX_HELPER_ENABLE_IPD
  * is not set in the executive-config.h file.
  *
  * Returns 0 on success

- *         -1 on failure
+ *        -1 on failure

  */
 extern int cvmx_helper_ipd_and_packet_input_enable(void);
 
  */
 extern int cvmx_helper_ipd_and_packet_input_enable(void);
 


@@ -128,7 +128,7 @@ extern int cvmx_helper_initialize_packet_io_local(void);
  * @interface: Which interface to return port count for.
  *
  * Returns Port count for interface
  * @interface: Which interface to return port count for.
  *
  * Returns Port count for interface

- *         -1 for uninitialized interface
+ *        -1 for uninitialized interface

  */
 extern int cvmx_helper_ports_on_interface(int interface);
 
  */
 extern int cvmx_helper_ports_on_interface(int interface);
 


@@ -150,7 +150,7 @@ extern int cvmx_helper_get_number_of_interfaces(void);
  * @interface: Interface to probe
  *
  * Returns Mode of the interface. Unknown or unsupported interfaces return
  * @interface: Interface to probe
  *
  * Returns Mode of the interface. Unknown or unsupported interfaces return

- *         DISABLED.
+ *        DISABLED.

  */
 extern cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int
                                                                   interface);
  */
 extern cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int
                                                                   interface);


@@ -214,9 +214,9 @@ extern int cvmx_helper_interface_enumerate(int interface);
  *
  * @ipd_port: IPD/PKO port to loopback.
  * @enable_internal:
  *
  * @ipd_port: IPD/PKO port to loopback.
  * @enable_internal:

- *                 Non zero if you want internal loopback
+ *                Non zero if you want internal loopback

  * @enable_external:
  * @enable_external:

- *                 Non zero if you want external loopback
+ *                Non zero if you want external loopback

  *
  * Returns Zero on success, negative on failure.
  */
  *
  * Returns Zero on success, negative on failure.
  */

diff --git a/arch/mips/include/asm/octeon/cvmx-ipd.h b/arch/mips/include/asm/octeon/cvmx-ipd.h
index 115a552c5c7fb94b3ceb1f90e45a59429707493b..e13490ebbb27de4ca790f0d76c57595a41e391bb 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-ipd.h
+++ b/arch/mips/include/asm/octeon/cvmx-ipd.h
@@ -38,8 +38,8 @@
 #include <asm/octeon/cvmx-ipd-defs.h>
 
 enum cvmx_ipd_mode {
 #include <asm/octeon/cvmx-ipd-defs.h>
 
 enum cvmx_ipd_mode {

-   CVMX_IPD_OPC_MODE_STT = 0LL,   /* All blocks DRAM, not cached in L2 */
-   CVMX_IPD_OPC_MODE_STF = 1LL,   /* All bloccks into  L2 */
+   CVMX_IPD_OPC_MODE_STT = 0LL,          /* All blocks DRAM, not cached in L2 */
+   CVMX_IPD_OPC_MODE_STF = 1LL,          /* All bloccks into  L2 */

    CVMX_IPD_OPC_MODE_STF1_STT = 2LL,   /* 1st block L2, rest DRAM */
    CVMX_IPD_OPC_MODE_STF2_STT = 3LL    /* 1st, 2nd blocks L2, rest DRAM */
 };
    CVMX_IPD_OPC_MODE_STF1_STT = 2LL,   /* 1st block L2, rest DRAM */
    CVMX_IPD_OPC_MODE_STF2_STT = 3LL    /* 1st, 2nd blocks L2, rest DRAM */
 };


@@ -60,17 +60,17 @@ typedef cvmx_ipd_first_next_ptr_back_t cvmx_ipd_second_next_ptr_back_t;
  *
  * @mbuff_size: Packets buffer size in 8 byte words
  * @first_mbuff_skip:
  *
  * @mbuff_size: Packets buffer size in 8 byte words
  * @first_mbuff_skip:

- *                   Number of 8 byte words to skip in the first buffer
+ *                  Number of 8 byte words to skip in the first buffer

  * @not_first_mbuff_skip:
  * @not_first_mbuff_skip:

- *                   Number of 8 byte words to skip in each following buffer
+ *                  Number of 8 byte words to skip in each following buffer

  * @first_back: Must be same as first_mbuff_skip / 128
  * @second_back:
  * @first_back: Must be same as first_mbuff_skip / 128
  * @second_back:

- *                   Must be same as not_first_mbuff_skip / 128
+ *                  Must be same as not_first_mbuff_skip / 128

  * @wqe_fpa_pool:
  * @wqe_fpa_pool:

- *                   FPA pool to get work entries from
+ *                  FPA pool to get work entries from

  * @cache_mode:
  * @back_pres_enable_flag:
  * @cache_mode:
  * @back_pres_enable_flag:

- *                   Enable or disable port back pressure
+ *                  Enable or disable port back pressure

  */
 static inline void cvmx_ipd_config(uint64_t mbuff_size,
                                   uint64_t first_mbuff_skip,
  */
 static inline void cvmx_ipd_config(uint64_t mbuff_size,
                                   uint64_t first_mbuff_skip,

diff --git a/arch/mips/include/asm/octeon/cvmx-l2c.h b/arch/mips/include/asm/octeon/cvmx-l2c.h
index 2c8ff9e33ec3856282a923a597e9edce65cf5913..11c0a8fa8eb517905cdfb4769205e3330a7626f1 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-l2c.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2c.h
@@ -33,13 +33,13 @@
 #ifndef __CVMX_L2C_H__
 #define __CVMX_L2C_H__
 
 #ifndef __CVMX_L2C_H__
 #define __CVMX_L2C_H__
 

-#define CVMX_L2_ASSOC     cvmx_l2c_get_num_assoc()   /* Deprecated macro, use function */
+#define CVMX_L2_ASSOC    cvmx_l2c_get_num_assoc()   /* Deprecated macro, use function */

 #define CVMX_L2_SET_BITS  cvmx_l2c_get_set_bits()    /* Deprecated macro, use function */
 #define CVMX_L2_SET_BITS  cvmx_l2c_get_set_bits()    /* Deprecated macro, use function */

-#define CVMX_L2_SETS      cvmx_l2c_get_num_sets()    /* Deprecated macro, use function */
+#define CVMX_L2_SETS     cvmx_l2c_get_num_sets()    /* Deprecated macro, use function */

 
 
 #define CVMX_L2C_IDX_ADDR_SHIFT 7  /* based on 128 byte cache line size */
 
 
 #define CVMX_L2C_IDX_ADDR_SHIFT 7  /* based on 128 byte cache line size */

-#define CVMX_L2C_IDX_MASK       (cvmx_l2c_get_num_sets() - 1)
+#define CVMX_L2C_IDX_MASK      (cvmx_l2c_get_num_sets() - 1)

 
 /* Defines for index aliasing computations */
 #define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits())
 
 /* Defines for index aliasing computations */
 #define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits())


@@ -67,91 +67,91 @@ union cvmx_l2c_tag {
 
   /* L2C Performance Counter events. */
 enum cvmx_l2c_event {
 
   /* L2C Performance Counter events. */
 enum cvmx_l2c_event {

-       CVMX_L2C_EVENT_CYCLES           =  0,
+       CVMX_L2C_EVENT_CYCLES           =  0,

        CVMX_L2C_EVENT_INSTRUCTION_MISS =  1,
        CVMX_L2C_EVENT_INSTRUCTION_MISS =  1,

-       CVMX_L2C_EVENT_INSTRUCTION_HIT  =  2,
-       CVMX_L2C_EVENT_DATA_MISS        =  3,
-       CVMX_L2C_EVENT_DATA_HIT         =  4,
-       CVMX_L2C_EVENT_MISS             =  5,
-       CVMX_L2C_EVENT_HIT              =  6,
-       CVMX_L2C_EVENT_VICTIM_HIT       =  7,
-       CVMX_L2C_EVENT_INDEX_CONFLICT   =  8,
-       CVMX_L2C_EVENT_TAG_PROBE        =  9,
-       CVMX_L2C_EVENT_TAG_UPDATE       = 10,
-       CVMX_L2C_EVENT_TAG_COMPLETE     = 11,
-       CVMX_L2C_EVENT_TAG_DIRTY        = 12,
-       CVMX_L2C_EVENT_DATA_STORE_NOP   = 13,
-       CVMX_L2C_EVENT_DATA_STORE_READ  = 14,
+       CVMX_L2C_EVENT_INSTRUCTION_HIT  =  2,
+       CVMX_L2C_EVENT_DATA_MISS        =  3,
+       CVMX_L2C_EVENT_DATA_HIT         =  4,
+       CVMX_L2C_EVENT_MISS             =  5,
+       CVMX_L2C_EVENT_HIT              =  6,
+       CVMX_L2C_EVENT_VICTIM_HIT       =  7,
+       CVMX_L2C_EVENT_INDEX_CONFLICT   =  8,
+       CVMX_L2C_EVENT_TAG_PROBE        =  9,
+       CVMX_L2C_EVENT_TAG_UPDATE       = 10,
+       CVMX_L2C_EVENT_TAG_COMPLETE     = 11,
+       CVMX_L2C_EVENT_TAG_DIRTY        = 12,
+       CVMX_L2C_EVENT_DATA_STORE_NOP   = 13,
+       CVMX_L2C_EVENT_DATA_STORE_READ  = 14,

        CVMX_L2C_EVENT_DATA_STORE_WRITE = 15,
        CVMX_L2C_EVENT_DATA_STORE_WRITE = 15,

-       CVMX_L2C_EVENT_FILL_DATA_VALID  = 16,
-       CVMX_L2C_EVENT_WRITE_REQUEST    = 17,
-       CVMX_L2C_EVENT_READ_REQUEST     = 18,
+       CVMX_L2C_EVENT_FILL_DATA_VALID  = 16,
+       CVMX_L2C_EVENT_WRITE_REQUEST    = 17,
+       CVMX_L2C_EVENT_READ_REQUEST     = 18,

        CVMX_L2C_EVENT_WRITE_DATA_VALID = 19,
        CVMX_L2C_EVENT_WRITE_DATA_VALID = 19,

-       CVMX_L2C_EVENT_XMC_NOP          = 20,
-       CVMX_L2C_EVENT_XMC_LDT          = 21,
-       CVMX_L2C_EVENT_XMC_LDI          = 22,
-       CVMX_L2C_EVENT_XMC_LDD          = 23,
-       CVMX_L2C_EVENT_XMC_STF          = 24,
-       CVMX_L2C_EVENT_XMC_STT          = 25,
-       CVMX_L2C_EVENT_XMC_STP          = 26,
-       CVMX_L2C_EVENT_XMC_STC          = 27,
-       CVMX_L2C_EVENT_XMC_DWB          = 28,
-       CVMX_L2C_EVENT_XMC_PL2          = 29,
-       CVMX_L2C_EVENT_XMC_PSL1         = 30,
-       CVMX_L2C_EVENT_XMC_IOBLD        = 31,
-       CVMX_L2C_EVENT_XMC_IOBST        = 32,
-       CVMX_L2C_EVENT_XMC_IOBDMA       = 33,
-       CVMX_L2C_EVENT_XMC_IOBRSP       = 34,
-       CVMX_L2C_EVENT_XMC_BUS_VALID    = 35,
-       CVMX_L2C_EVENT_XMC_MEM_DATA     = 36,
-       CVMX_L2C_EVENT_XMC_REFL_DATA    = 37,
-       CVMX_L2C_EVENT_XMC_IOBRSP_DATA  = 38,
-       CVMX_L2C_EVENT_RSC_NOP          = 39,
-       CVMX_L2C_EVENT_RSC_STDN         = 40,
-       CVMX_L2C_EVENT_RSC_FILL         = 41,
-       CVMX_L2C_EVENT_RSC_REFL         = 42,
-       CVMX_L2C_EVENT_RSC_STIN         = 43,
-       CVMX_L2C_EVENT_RSC_SCIN         = 44,
-       CVMX_L2C_EVENT_RSC_SCFL         = 45,
-       CVMX_L2C_EVENT_RSC_SCDN         = 46,
-       CVMX_L2C_EVENT_RSC_DATA_VALID   = 47,
-       CVMX_L2C_EVENT_RSC_VALID_FILL   = 48,
-       CVMX_L2C_EVENT_RSC_VALID_STRSP  = 49,
-       CVMX_L2C_EVENT_RSC_VALID_REFL   = 50,
-       CVMX_L2C_EVENT_LRF_REQ          = 51,
-       CVMX_L2C_EVENT_DT_RD_ALLOC      = 52,
-       CVMX_L2C_EVENT_DT_WR_INVAL      = 53,
+       CVMX_L2C_EVENT_XMC_NOP          = 20,
+       CVMX_L2C_EVENT_XMC_LDT          = 21,
+       CVMX_L2C_EVENT_XMC_LDI          = 22,
+       CVMX_L2C_EVENT_XMC_LDD          = 23,
+       CVMX_L2C_EVENT_XMC_STF          = 24,
+       CVMX_L2C_EVENT_XMC_STT          = 25,
+       CVMX_L2C_EVENT_XMC_STP          = 26,
+       CVMX_L2C_EVENT_XMC_STC          = 27,
+       CVMX_L2C_EVENT_XMC_DWB          = 28,
+       CVMX_L2C_EVENT_XMC_PL2          = 29,
+       CVMX_L2C_EVENT_XMC_PSL1         = 30,
+       CVMX_L2C_EVENT_XMC_IOBLD        = 31,
+       CVMX_L2C_EVENT_XMC_IOBST        = 32,
+       CVMX_L2C_EVENT_XMC_IOBDMA       = 33,
+       CVMX_L2C_EVENT_XMC_IOBRSP       = 34,
+       CVMX_L2C_EVENT_XMC_BUS_VALID    = 35,
+       CVMX_L2C_EVENT_XMC_MEM_DATA     = 36,
+       CVMX_L2C_EVENT_XMC_REFL_DATA    = 37,
+       CVMX_L2C_EVENT_XMC_IOBRSP_DATA  = 38,
+       CVMX_L2C_EVENT_RSC_NOP          = 39,
+       CVMX_L2C_EVENT_RSC_STDN         = 40,
+       CVMX_L2C_EVENT_RSC_FILL         = 41,
+       CVMX_L2C_EVENT_RSC_REFL         = 42,
+       CVMX_L2C_EVENT_RSC_STIN         = 43,
+       CVMX_L2C_EVENT_RSC_SCIN         = 44,
+       CVMX_L2C_EVENT_RSC_SCFL         = 45,
+       CVMX_L2C_EVENT_RSC_SCDN         = 46,
+       CVMX_L2C_EVENT_RSC_DATA_VALID   = 47,
+       CVMX_L2C_EVENT_RSC_VALID_FILL   = 48,
+       CVMX_L2C_EVENT_RSC_VALID_STRSP  = 49,
+       CVMX_L2C_EVENT_RSC_VALID_REFL   = 50,
+       CVMX_L2C_EVENT_LRF_REQ          = 51,
+       CVMX_L2C_EVENT_DT_RD_ALLOC      = 52,
+       CVMX_L2C_EVENT_DT_WR_INVAL      = 53,

        CVMX_L2C_EVENT_MAX
 };
 
 /* L2C Performance Counter events for Octeon2. */
 enum cvmx_l2c_tad_event {
        CVMX_L2C_EVENT_MAX
 };
 
 /* L2C Performance Counter events for Octeon2. */
 enum cvmx_l2c_tad_event {

-       CVMX_L2C_TAD_EVENT_NONE          = 0,
-       CVMX_L2C_TAD_EVENT_TAG_HIT       = 1,
-       CVMX_L2C_TAD_EVENT_TAG_MISS      = 2,
-       CVMX_L2C_TAD_EVENT_TAG_NOALLOC   = 3,
-       CVMX_L2C_TAD_EVENT_TAG_VICTIM    = 4,
-       CVMX_L2C_TAD_EVENT_SC_FAIL       = 5,
-       CVMX_L2C_TAD_EVENT_SC_PASS       = 6,
-       CVMX_L2C_TAD_EVENT_LFB_VALID     = 7,
-       CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB  = 8,
-       CVMX_L2C_TAD_EVENT_LFB_WAIT_VAB  = 9,
-       CVMX_L2C_TAD_EVENT_QUAD0_INDEX   = 128,
-       CVMX_L2C_TAD_EVENT_QUAD0_READ    = 129,
-       CVMX_L2C_TAD_EVENT_QUAD0_BANK    = 130,
-       CVMX_L2C_TAD_EVENT_QUAD0_WDAT    = 131,
-       CVMX_L2C_TAD_EVENT_QUAD1_INDEX   = 144,
-       CVMX_L2C_TAD_EVENT_QUAD1_READ    = 145,
-       CVMX_L2C_TAD_EVENT_QUAD1_BANK    = 146,
-       CVMX_L2C_TAD_EVENT_QUAD1_WDAT    = 147,
-       CVMX_L2C_TAD_EVENT_QUAD2_INDEX   = 160,
-       CVMX_L2C_TAD_EVENT_QUAD2_READ    = 161,
-       CVMX_L2C_TAD_EVENT_QUAD2_BANK    = 162,
-       CVMX_L2C_TAD_EVENT_QUAD2_WDAT    = 163,
-       CVMX_L2C_TAD_EVENT_QUAD3_INDEX   = 176,
-       CVMX_L2C_TAD_EVENT_QUAD3_READ    = 177,
-       CVMX_L2C_TAD_EVENT_QUAD3_BANK    = 178,
-       CVMX_L2C_TAD_EVENT_QUAD3_WDAT    = 179,
+       CVMX_L2C_TAD_EVENT_NONE          = 0,
+       CVMX_L2C_TAD_EVENT_TAG_HIT       = 1,
+       CVMX_L2C_TAD_EVENT_TAG_MISS      = 2,
+       CVMX_L2C_TAD_EVENT_TAG_NOALLOC   = 3,
+       CVMX_L2C_TAD_EVENT_TAG_VICTIM    = 4,
+       CVMX_L2C_TAD_EVENT_SC_FAIL       = 5,
+       CVMX_L2C_TAD_EVENT_SC_PASS       = 6,
+       CVMX_L2C_TAD_EVENT_LFB_VALID     = 7,
+       CVMX_L2C_TAD_EVENT_LFB_WAIT_LFB  = 8,
+       CVMX_L2C_TAD_EVENT_LFB_WAIT_VAB  = 9,
+       CVMX_L2C_TAD_EVENT_QUAD0_INDEX   = 128,
+       CVMX_L2C_TAD_EVENT_QUAD0_READ    = 129,
+       CVMX_L2C_TAD_EVENT_QUAD0_BANK    = 130,
+       CVMX_L2C_TAD_EVENT_QUAD0_WDAT    = 131,
+       CVMX_L2C_TAD_EVENT_QUAD1_INDEX   = 144,
+       CVMX_L2C_TAD_EVENT_QUAD1_READ    = 145,
+       CVMX_L2C_TAD_EVENT_QUAD1_BANK    = 146,
+       CVMX_L2C_TAD_EVENT_QUAD1_WDAT    = 147,
+       CVMX_L2C_TAD_EVENT_QUAD2_INDEX   = 160,
+       CVMX_L2C_TAD_EVENT_QUAD2_READ    = 161,
+       CVMX_L2C_TAD_EVENT_QUAD2_BANK    = 162,
+       CVMX_L2C_TAD_EVENT_QUAD2_WDAT    = 163,
+       CVMX_L2C_TAD_EVENT_QUAD3_INDEX   = 176,
+       CVMX_L2C_TAD_EVENT_QUAD3_READ    = 177,
+       CVMX_L2C_TAD_EVENT_QUAD3_BANK    = 178,
+       CVMX_L2C_TAD_EVENT_QUAD3_WDAT    = 179,

        CVMX_L2C_TAD_EVENT_MAX
 };
 
        CVMX_L2C_TAD_EVENT_MAX
 };
 


@@ -159,10 +159,10 @@ enum cvmx_l2c_tad_event {
  * Configure one of the four L2 Cache performance counters to capture event
  * occurrences.
  *
  * Configure one of the four L2 Cache performance counters to capture event
  * occurrences.
  *

- * @counter:        The counter to configure. Range 0..3.
- * @event:          The type of L2 Cache event occurrence to count.
+ * @counter:       The counter to configure. Range 0..3.
+ * @event:         The type of L2 Cache event occurrence to count.

  * @clear_on_read:  When asserted, any read of the performance counter
  * @clear_on_read:  When asserted, any read of the performance counter

- *                       clears the counter.
+ *                      clears the counter.

  *
  * @note The routine does not clear the counter.
  */
  *
  * @note The routine does not clear the counter.
  */


@@ -184,8 +184,8 @@ uint64_t cvmx_l2c_read_perf(uint32_t counter);
  * @core:  The core processor of interest.
  *
  * Returns    The mask specifying the partitioning. 0 bits in mask indicates
  * @core:  The core processor of interest.
  *
  * Returns    The mask specifying the partitioning. 0 bits in mask indicates

- *              the cache 'ways' that a core can evict from.
- *            -1 on error
+ *             the cache 'ways' that a core can evict from.
+ *           -1 on error

  */
 int cvmx_l2c_get_core_way_partition(uint32_t core);
 
  */
 int cvmx_l2c_get_core_way_partition(uint32_t core);
 


@@ -194,16 +194,16 @@ int cvmx_l2c_get_core_way_partition(uint32_t core);
  *
  * @core: The core that the partitioning applies to.
  * @mask: The partitioning of the ways expressed as a binary
  *
  * @core: The core that the partitioning applies to.
  * @mask: The partitioning of the ways expressed as a binary

- *             mask. A 0 bit allows the core to evict cache lines from
- *             a way, while a 1 bit blocks the core from evicting any
- *             lines from that way. There must be at least one allowed
- *             way (0 bit) in the mask.
+ *            mask. A 0 bit allows the core to evict cache lines from
+ *            a way, while a 1 bit blocks the core from evicting any
+ *            lines from that way. There must be at least one allowed
+ *            way (0 bit) in the mask.

  *
 
  * @note If any ways are blocked for all cores and the HW blocks, then
  *
 
  * @note If any ways are blocked for all cores and the HW blocks, then

- *       those ways will never have any cache lines evicted from them.
- *       All cores and the hardware blocks are free to read from all
- *       ways regardless of the partitioning.
+ *      those ways will never have any cache lines evicted from them.
+ *      All cores and the hardware blocks are free to read from all
+ *      ways regardless of the partitioning.

  */
 int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask);
 
  */
 int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask);
 


@@ -211,8 +211,8 @@ int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask);
  * Return the L2 Cache way partitioning for the hw blocks.
  *
  * Returns    The mask specifying the reserved way. 0 bits in mask indicates
  * Return the L2 Cache way partitioning for the hw blocks.
  *
  * Returns    The mask specifying the reserved way. 0 bits in mask indicates

- *              the cache 'ways' that a core can evict from.
- *            -1 on error
+ *             the cache 'ways' that a core can evict from.
+ *           -1 on error

  */
 int cvmx_l2c_get_hw_way_partition(void);
 
  */
 int cvmx_l2c_get_hw_way_partition(void);
 


@@ -220,16 +220,16 @@ int cvmx_l2c_get_hw_way_partition(void);
  * Partitions the L2 cache for the hardware blocks.
  *
  * @mask: The partitioning of the ways expressed as a binary
  * Partitions the L2 cache for the hardware blocks.
  *
  * @mask: The partitioning of the ways expressed as a binary

- *             mask. A 0 bit allows the core to evict cache lines from
- *             a way, while a 1 bit blocks the core from evicting any
- *             lines from that way. There must be at least one allowed
- *             way (0 bit) in the mask.
+ *            mask. A 0 bit allows the core to evict cache lines from
+ *            a way, while a 1 bit blocks the core from evicting any
+ *            lines from that way. There must be at least one allowed
+ *            way (0 bit) in the mask.

  *
 
  * @note If any ways are blocked for all cores and the HW blocks, then
  *
 
  * @note If any ways are blocked for all cores and the HW blocks, then

- *       those ways will never have any cache lines evicted from them.
- *       All cores and the hardware blocks are free to read from all
- *       ways regardless of the partitioning.
+ *      those ways will never have any cache lines evicted from them.
+ *      All cores and the hardware blocks are free to read from all
+ *      ways regardless of the partitioning.

  */
 int cvmx_l2c_set_hw_way_partition(uint32_t mask);
 
  */
 int cvmx_l2c_set_hw_way_partition(uint32_t mask);
 


@@ -240,7 +240,7 @@ int cvmx_l2c_set_hw_way_partition(uint32_t mask);
  * @addr:   physical address of line to lock
  *
  * Returns 0 on success,
  * @addr:   physical address of line to lock
  *
  * Returns 0 on success,

- *         1 if line not locked.
+ *        1 if line not locked.

  */
 int cvmx_l2c_lock_line(uint64_t addr);
 
  */
 int cvmx_l2c_lock_line(uint64_t addr);
 


@@ -258,7 +258,7 @@ int cvmx_l2c_lock_line(uint64_t addr);
  * @len:    Length (in bytes) of region to lock
  *
  * Returns Number of requested lines that where not locked.
  * @len:    Length (in bytes) of region to lock
  *
  * Returns Number of requested lines that where not locked.

- *         0 on success (all locked)
+ *        0 on success (all locked)

  */
 int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len);
 
  */
 int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len);
 


@@ -272,7 +272,7 @@ int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len);
  * @address: Physical address to unlock
  *
  * Returns 0: line not unlocked
  * @address: Physical address to unlock
  *
  * Returns 0: line not unlocked

- *         1: line unlocked
+ *        1: line unlocked

  */
 int cvmx_l2c_unlock_line(uint64_t address);
 
  */
 int cvmx_l2c_unlock_line(uint64_t address);
 


@@ -290,7 +290,7 @@ int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len);
  * Read the L2 controller tag for a given location in L2
  *
  * @association:
  * Read the L2 controller tag for a given location in L2
  *
  * @association:

- *               Which association to read line from
+ *              Which association to read line from

  * @index:  Which way to read from.
  *
  * Returns l2c tag structure for line requested.
  * @index:  Which way to read from.
  *
  * Returns l2c tag structure for line requested.

diff --git a/arch/mips/include/asm/octeon/cvmx-mdio.h b/arch/mips/include/asm/octeon/cvmx-mdio.h
index 6f0cd182cec8d5da1b9798cd802dfdea81dfb3da..9f6a4f32a83c5b475bfee316588b5188f2d6c00c 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-mdio.h
+++ b/arch/mips/include/asm/octeon/cvmx-mdio.h
@@ -246,21 +246,21 @@ typedef union {
 } cvmx_mdio_phy_reg_mmd_address_data_t;
 
 /* Operating request encodings. */
 } cvmx_mdio_phy_reg_mmd_address_data_t;
 
 /* Operating request encodings. */

-#define MDIO_CLAUSE_22_WRITE    0
-#define MDIO_CLAUSE_22_READ     1
+#define MDIO_CLAUSE_22_WRITE   0
+#define MDIO_CLAUSE_22_READ    1

 
 

-#define MDIO_CLAUSE_45_ADDRESS  0
-#define MDIO_CLAUSE_45_WRITE    1
+#define MDIO_CLAUSE_45_ADDRESS 0
+#define MDIO_CLAUSE_45_WRITE   1

 #define MDIO_CLAUSE_45_READ_INC 2
 #define MDIO_CLAUSE_45_READ_INC 2

-#define MDIO_CLAUSE_45_READ     3
+#define MDIO_CLAUSE_45_READ    3

 
 /* MMD identifiers, mostly for accessing devices within XENPAK modules. */
 
 /* MMD identifiers, mostly for accessing devices within XENPAK modules. */

-#define CVMX_MMD_DEVICE_PMA_PMD      1
-#define CVMX_MMD_DEVICE_WIS          2
-#define CVMX_MMD_DEVICE_PCS          3
-#define CVMX_MMD_DEVICE_PHY_XS       4
-#define CVMX_MMD_DEVICE_DTS_XS       5
-#define CVMX_MMD_DEVICE_TC           6
+#define CVMX_MMD_DEVICE_PMA_PMD             1
+#define CVMX_MMD_DEVICE_WIS         2
+#define CVMX_MMD_DEVICE_PCS         3
+#define CVMX_MMD_DEVICE_PHY_XS      4
+#define CVMX_MMD_DEVICE_DTS_XS      5
+#define CVMX_MMD_DEVICE_TC          6

 #define CVMX_MMD_DEVICE_CL22_EXT     29
 #define CVMX_MMD_DEVICE_VENDOR_1     30
 #define CVMX_MMD_DEVICE_VENDOR_2     31
 #define CVMX_MMD_DEVICE_CL22_EXT     29
 #define CVMX_MMD_DEVICE_VENDOR_1     30
 #define CVMX_MMD_DEVICE_VENDOR_2     31


@@ -291,7 +291,7 @@ static inline void __cvmx_mdio_set_clause22_mode(int bus_id)
  * registers controlling auto negotiation.
  *
  * @bus_id:   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
  * registers controlling auto negotiation.
  *
  * @bus_id:   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)

- *                 support multiple busses.
+ *                support multiple busses.

  * @phy_id:   The MII phy id
  * @location: Register location to read
  *
  * @phy_id:   The MII phy id
  * @location: Register location to read
  *


@@ -328,13 +328,13 @@ static inline int cvmx_mdio_read(int bus_id, int phy_id, int location)
  * registers controlling auto negotiation.
  *
  * @bus_id:   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
  * registers controlling auto negotiation.
  *
  * @bus_id:   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)

- *                 support multiple busses.
+ *                support multiple busses.

  * @phy_id:   The MII phy id
  * @location: Register location to write
  * @val:      Value to write
  *
  * Returns -1 on error
  * @phy_id:   The MII phy id
  * @location: Register location to write
  * @val:      Value to write
  *
  * Returns -1 on error

- *         0 on success
+ *        0 on success

  */
 static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val)
 {
  */
 static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val)
 {


@@ -370,7 +370,7 @@ static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val)
  * read PHY registers controlling auto negotiation.
  *
  * @bus_id:   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
  * read PHY registers controlling auto negotiation.
  *
  * @bus_id:   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)

- *                 support multiple busses.
+ *                support multiple busses.

  * @phy_id:   The MII phy id
  * @device:   MDIO Managable Device (MMD) id
  * @location: Register location to read
  * @phy_id:   The MII phy id
  * @device:   MDIO Managable Device (MMD) id
  * @location: Register location to read


@@ -407,7 +407,7 @@ static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device,
        } while (smi_wr.s.pending && --timeout);
        if (timeout <= 0) {
                cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "
        } while (smi_wr.s.pending && --timeout);
        if (timeout <= 0) {
                cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "

-                            "device %2d register %2d   TIME OUT(address)\n",
+                            "device %2d register %2d   TIME OUT(address)\n",

                     bus_id, phy_id, device, location);
                return -1;
        }
                     bus_id, phy_id, device, location);
                return -1;
        }


@@ -425,7 +425,7 @@ static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device,
 
        if (timeout <= 0) {
                cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "
 
        if (timeout <= 0) {
                cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "

-                            "device %2d register %2d   TIME OUT(data)\n",
+                            "device %2d register %2d   TIME OUT(data)\n",

                     bus_id, phy_id, device, location);
                return -1;
        }
                     bus_id, phy_id, device, location);
                return -1;
        }


@@ -434,7 +434,7 @@ static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device,
                return smi_rd.s.dat;
        else {
                cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "
                return smi_rd.s.dat;
        else {
                cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d "

-                            "device %2d register %2d   INVALID READ\n",
+                            "device %2d register %2d   INVALID READ\n",

                     bus_id, phy_id, device, location);
                return -1;
        }
                     bus_id, phy_id, device, location);
                return -1;
        }


@@ -445,14 +445,14 @@ static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device,
  * write PHY registers controlling auto negotiation.
  *
  * @bus_id:   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
  * write PHY registers controlling auto negotiation.
  *
  * @bus_id:   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)

- *                 support multiple busses.
+ *                support multiple busses.

  * @phy_id:   The MII phy id
  * @device:   MDIO Managable Device (MMD) id
  * @location: Register location to write
  * @val:      Value to write
  *
  * Returns -1 on error
  * @phy_id:   The MII phy id
  * @device:   MDIO Managable Device (MMD) id
  * @location: Register location to write
  * @val:      Value to write
  *
  * Returns -1 on error

- *         0 on success
+ *        0 on success

  */
 static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device,
                                     int location, int val)
  */
 static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device,
                                     int location, int val)

diff --git a/arch/mips/include/asm/octeon/cvmx-pip-defs.h b/arch/mips/include/asm/octeon/cvmx-pip-defs.h
index 05a917d6ebe54356aea6fcd761bf3d1f0292c293..e975c7d2e485cbff96be509d71686c9e78228ce1 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-pip-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-pip-defs.h
@@ -44,7 +44,7 @@ enum cvmx_pip_port_parse_mode {
         */
        CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull,
        /*
         */
        CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull,
        /*

-        * Input packets are assumed to be IP.  Results from non IP
+        * Input packets are assumed to be IP.  Results from non IP

         * packets is undefined. Pointers reference the beginning of
         * the IP header.
         */
         * packets is undefined. Pointers reference the beginning of
         * the IP header.
         */

diff --git a/arch/mips/include/asm/octeon/cvmx-pip.h b/arch/mips/include/asm/octeon/cvmx-pip.h
index 9e739a640855645382515e61bb16e80a5b13b40f..a76fe5a57a9f64e302af248194ea9288cb4590b4 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-pip.h
+++ b/arch/mips/include/asm/octeon/cvmx-pip.h
@@ -37,8 +37,8 @@
 #include <asm/octeon/cvmx-fpa.h>
 #include <asm/octeon/cvmx-pip-defs.h>
 
 #include <asm/octeon/cvmx-fpa.h>
 #include <asm/octeon/cvmx-pip-defs.h>
 

-#define CVMX_PIP_NUM_INPUT_PORTS                40
-#define CVMX_PIP_NUM_WATCHERS                   4
+#define CVMX_PIP_NUM_INPUT_PORTS               40
+#define CVMX_PIP_NUM_WATCHERS                  4

 
 /*
  * Encodes the different error and exception codes
 
 /*
  * Encodes the different error and exception codes


@@ -92,10 +92,10 @@ typedef enum {
 
 /**
  * NOTES
 
 /**
  * NOTES

- *       late collision (data received before collision)
- *            late collisions cannot be detected by the receiver
- *            they would appear as JAM bits which would appear as bad FCS
- *            or carrier extend error which is CVMX_PIP_EXTEND_ERR
+ *      late collision (data received before collision)
+ *           late collisions cannot be detected by the receiver
+ *           they would appear as JAM bits which would appear as bad FCS
+ *           or carrier extend error which is CVMX_PIP_EXTEND_ERR

  */
 typedef enum {
        /* No error */
  */
 typedef enum {
        /* No error */


@@ -122,11 +122,11 @@ typedef enum {
         * error)
         */
        CVMX_PIP_UNDER_FCS_ERR = 6ull,
         * error)
         */
        CVMX_PIP_UNDER_FCS_ERR = 6ull,

-       /* RGM     7 = FCS error */
+       /* RGM     7 = FCS error */

        CVMX_PIP_GMX_FCS_ERR = 7ull,
        /* RGM+SPI 8 = min frame error (pkt len < min frame len) */
        CVMX_PIP_UNDER_ERR = 8ull,
        CVMX_PIP_GMX_FCS_ERR = 7ull,
        /* RGM+SPI 8 = min frame error (pkt len < min frame len) */
        CVMX_PIP_UNDER_ERR = 8ull,

-       /* RGM     9 = Frame carrier extend error */
+       /* RGM     9 = Frame carrier extend error */

        CVMX_PIP_EXTEND_ERR = 9ull,
        /*
         * RGM 10 = length mismatch (len did not match len in L2
        CVMX_PIP_EXTEND_ERR = 9ull,
        /*
         * RGM 10 = length mismatch (len did not match len in L2


@@ -161,10 +161,10 @@ typedef enum {
        CVMX_PIP_PIP_L2_MAL_HDR = 18L
        /*
         * NOTES: xx = late collision (data received before collision)
        CVMX_PIP_PIP_L2_MAL_HDR = 18L
        /*
         * NOTES: xx = late collision (data received before collision)

-        *       late collisions cannot be detected by the receiver
-        *       they would appear as JAM bits which would appear as
-        *       bad FCS or carrier extend error which is
-        *       CVMX_PIP_EXTEND_ERR
+        *       late collisions cannot be detected by the receiver
+        *       they would appear as JAM bits which would appear as
+        *       bad FCS or carrier extend error which is
+        *       CVMX_PIP_EXTEND_ERR

         */
 } cvmx_pip_rcv_err_t;
 
         */
 } cvmx_pip_rcv_err_t;
 


@@ -192,13 +192,13 @@ typedef struct {
        /* Number of packets processed by PIP */
        uint32_t packets;
        /*
        /* Number of packets processed by PIP */
        uint32_t packets;
        /*

-        * Number of indentified L2 multicast packets.  Does not
+        * Number of indentified L2 multicast packets.  Does not

         * include broadcast packets.  Only includes packets whose
         * parse mode is SKIP_TO_L2
         */
        uint32_t multicast_packets;
        /*
         * include broadcast packets.  Only includes packets whose
         * parse mode is SKIP_TO_L2
         */
        uint32_t multicast_packets;
        /*

-        * Number of indentified L2 broadcast packets.  Does not
+        * Number of indentified L2 broadcast packets.  Does not

         * include multicast packets.  Only includes packets whose
         * parse mode is SKIP_TO_L2
         */
         * include multicast packets.  Only includes packets whose
         * parse mode is SKIP_TO_L2
         */


@@ -287,7 +287,7 @@ typedef union {
  * @port_num: Port number to configure
  * @port_cfg: Port hardware configuration
  * @port_tag_cfg:
  * @port_num: Port number to configure
  * @port_cfg: Port hardware configuration
  * @port_tag_cfg:

- *                 Port POW tagging configuration
+ *                Port POW tagging configuration

  */
 static inline void cvmx_pip_config_port(uint64_t port_num,
                                        union cvmx_pip_prt_cfgx port_cfg,
  */
 static inline void cvmx_pip_config_port(uint64_t port_num,
                                        union cvmx_pip_prt_cfgx port_cfg,


@@ -298,20 +298,20 @@ static inline void cvmx_pip_config_port(uint64_t port_num,
 }
 #if 0
 /**
 }
 #if 0
 /**

- * @deprecated      This function is a thin wrapper around the Pass1 version
- *                  of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for
- *                  setting the group that is incompatible with this function,
- *                  the preferred upgrade path is to use the CSR directly.
+ * @deprecated     This function is a thin wrapper around the Pass1 version
+ *                 of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for
+ *                 setting the group that is incompatible with this function,
+ *                 the preferred upgrade path is to use the CSR directly.

  *
  * Configure the global QoS packet watchers. Each watcher is
  * capable of matching a field in a packet to determine the
  * QoS queue for scheduling.
  *
  *
  * Configure the global QoS packet watchers. Each watcher is
  * capable of matching a field in a packet to determine the
  * QoS queue for scheduling.
  *

- * @watcher:    Watcher number to configure (0 - 3).
+ * @watcher:   Watcher number to configure (0 - 3).

  * @match_type: Watcher match type
  * @match_value:
  * @match_type: Watcher match type
  * @match_value:

- *                   Value the watcher will match against
- * @qos:        QoS queue for packets matching this watcher
+ *                  Value the watcher will match against
+ * @qos:       QoS queue for packets matching this watcher

  */
 static inline void cvmx_pip_config_watcher(uint64_t watcher,
                                           cvmx_pip_qos_watch_types match_type,
  */
 static inline void cvmx_pip_config_watcher(uint64_t watcher,
                                           cvmx_pip_qos_watch_types match_type,


@@ -331,7 +331,7 @@ static inline void cvmx_pip_config_watcher(uint64_t watcher,
  * Configure the VLAN priority to QoS queue mapping.
  *
  * @vlan_priority:
  * Configure the VLAN priority to QoS queue mapping.
  *
  * @vlan_priority:

- *               VLAN priority (0-7)
+ *              VLAN priority (0-7)

  * @qos:    QoS queue for packets matching this watcher
  */
 static inline void cvmx_pip_config_vlan_qos(uint64_t vlan_priority,
  * @qos:    QoS queue for packets matching this watcher
  */
 static inline void cvmx_pip_config_vlan_qos(uint64_t vlan_priority,


@@ -451,10 +451,10 @@ static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear,
  *
  * @interface: Interface to configure (0 or 1)
  * @invert_result:
  *
  * @interface: Interface to configure (0 or 1)
  * @invert_result:

- *                 Invert the result of the CRC
+ *                Invert the result of the CRC

  * @reflect:  Reflect
  * @initialization_vector:
  * @reflect:  Reflect
  * @initialization_vector:

- *                 CRC initialization vector
+ *                CRC initialization vector

  */
 static inline void cvmx_pip_config_crc(uint64_t interface,
                                       uint64_t invert_result, uint64_t reflect,
  */
 static inline void cvmx_pip_config_crc(uint64_t interface,
                                       uint64_t invert_result, uint64_t reflect,


@@ -500,13 +500,13 @@ static inline void cvmx_pip_tag_mask_clear(uint64_t mask_index)
  *
  * @mask_index: Which tag mask to modify (0..3)
  * @offset: Offset into the bitmask to set bits at. Use the GCC macro
  *
  * @mask_index: Which tag mask to modify (0..3)
  * @offset: Offset into the bitmask to set bits at. Use the GCC macro

- *          offsetof() to determine the offsets into packet headers.
- *          For example, offsetof(ethhdr, protocol) returns the offset
- *          of the ethernet protocol field.  The bitmask selects which
- *          bytes to include the the tag, with bit offset X selecting
- *          byte at offset X from the beginning of the packet data.
+ *         offsetof() to determine the offsets into packet headers.
+ *         For example, offsetof(ethhdr, protocol) returns the offset
+ *         of the ethernet protocol field.  The bitmask selects which
+ *         bytes to include the the tag, with bit offset X selecting
+ *         byte at offset X from the beginning of the packet data.

  * @len:    Number of bytes to include. Usually this is the sizeof()
  * @len:    Number of bytes to include. Usually this is the sizeof()

- *          the field.
+ *         the field.

  */
 static inline void cvmx_pip_tag_mask_set(uint64_t mask_index, uint64_t offset,
                                         uint64_t len)
  */
 static inline void cvmx_pip_tag_mask_set(uint64_t mask_index, uint64_t offset,
                                         uint64_t len)

diff --git a/arch/mips/include/asm/octeon/cvmx-pko.h b/arch/mips/include/asm/octeon/cvmx-pko.h
index c6daeedf1f8127017565e08b30d48189431bd2f6..f7d2a671884980894cbf8a22149c33ed0c08091f 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-pko.h
+++ b/arch/mips/include/asm/octeon/cvmx-pko.h
@@ -69,16 +69,16 @@
 #define CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST (1)
 
 #define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256
 #define CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST (1)
 
 #define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256

-#define CVMX_PKO_MAX_OUTPUT_QUEUES      ((OCTEON_IS_MODEL(OCTEON_CN31XX) || \
+#define CVMX_PKO_MAX_OUTPUT_QUEUES     ((OCTEON_IS_MODEL(OCTEON_CN31XX) || \

        OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || \
        OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : \
                (OCTEON_IS_MODEL(OCTEON_CN58XX) || \
                OCTEON_IS_MODEL(OCTEON_CN56XX)) ? 256 : 128)
        OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || \
        OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : \
                (OCTEON_IS_MODEL(OCTEON_CN58XX) || \
                OCTEON_IS_MODEL(OCTEON_CN56XX)) ? 256 : 128)

-#define CVMX_PKO_NUM_OUTPUT_PORTS       40
+#define CVMX_PKO_NUM_OUTPUT_PORTS      40

 /* use this for queues that are not used */
 #define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63
 /* use this for queues that are not used */
 #define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63

-#define CVMX_PKO_QUEUE_STATIC_PRIORITY  9
-#define CVMX_PKO_ILLEGAL_QUEUE  0xFFFF
+#define CVMX_PKO_QUEUE_STATIC_PRIORITY 9
+#define CVMX_PKO_ILLEGAL_QUEUE 0xFFFF

 #define CVMX_PKO_MAX_QUEUE_DEPTH 0
 
 typedef enum {
 #define CVMX_PKO_MAX_QUEUE_DEPTH 0
 
 typedef enum {


@@ -269,13 +269,13 @@ extern void cvmx_pko_shutdown(void);
 /**
  * Configure a output port and the associated queues for use.
  *
 /**
  * Configure a output port and the associated queues for use.
  *

- * @port:       Port to configure.
+ * @port:      Port to configure.

  * @base_queue: First queue number to associate with this port.
  * @num_queues: Number of queues t oassociate with this port
  * @base_queue: First queue number to associate with this port.
  * @num_queues: Number of queues t oassociate with this port

- * @priority:   Array of priority levels for each queue. Values are
- *                   allowed to be 1-8. A value of 8 get 8 times the traffic
- *                   of a value of 1. There must be num_queues elements in the
- *                   array.
+ * @priority:  Array of priority levels for each queue. Values are
+ *                  allowed to be 1-8. A value of 8 get 8 times the traffic
+ *                  of a value of 1. There must be num_queues elements in the
+ *                  array.

  */
 extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port,
                                              uint64_t base_queue,
  */
 extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port,
                                              uint64_t base_queue,


@@ -285,7 +285,7 @@ extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port,
 /**
  * Ring the packet output doorbell. This tells the packet
  * output hardware that "len" command words have been added
 /**
  * Ring the packet output doorbell. This tells the packet
  * output hardware that "len" command words have been added

- * to its pending list.  This command includes the required
+ * to its pending list.         This command includes the required

  * CVMX_SYNCWS before the doorbell ring.
  *
  * @port:   Port the packet is for
  * CVMX_SYNCWS before the doorbell ring.
  *
  * @port:   Port the packet is for


@@ -322,18 +322,18 @@ static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue,
  * The use_locking parameter allows the caller to use three
  * possible locking modes.
  * - CVMX_PKO_LOCK_NONE
  * The use_locking parameter allows the caller to use three
  * possible locking modes.
  * - CVMX_PKO_LOCK_NONE

- *      - PKO doesn't do any locking. It is the responsibility
- *          of the application to make sure that no other core
- *          is accessing the same queue at the same time.
+ *     - PKO doesn't do any locking. It is the responsibility
+ *         of the application to make sure that no other core
+ *         is accessing the same queue at the same time.

  * - CVMX_PKO_LOCK_ATOMIC_TAG
  * - CVMX_PKO_LOCK_ATOMIC_TAG

- *      - PKO performs an atomic tagswitch to insure exclusive
- *          access to the output queue. This will maintain
- *          packet ordering on output.
+ *     - PKO performs an atomic tagswitch to insure exclusive
+ *         access to the output queue. This will maintain
+ *         packet ordering on output.

  * - CVMX_PKO_LOCK_CMD_QUEUE
  * - CVMX_PKO_LOCK_CMD_QUEUE

- *      - PKO uses the common command queue locks to insure
- *          exclusive access to the output queue. This is a
- *          memory based ll/sc. This is the most portable
- *          locking mechanism.
+ *     - PKO uses the common command queue locks to insure
+ *         exclusive access to the output queue. This is a
+ *         memory based ll/sc. This is the most portable
+ *         locking mechanism.

  *
  * NOTE: If atomic locking is used, the POW entry CANNOT be
  * descheduled, as it does not contain a valid WQE pointer.
  *
  * NOTE: If atomic locking is used, the POW entry CANNOT be
  * descheduled, as it does not contain a valid WQE pointer.


@@ -341,7 +341,7 @@ static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue,
  * @port:   Port to send it on
  * @queue:  Queue to use
  * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
  * @port:   Port to send it on
  * @queue:  Queue to use
  * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or

- *               CVMX_PKO_LOCK_CMD_QUEUE
+ *              CVMX_PKO_LOCK_CMD_QUEUE

  */
 
 static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue,
  */
 
 static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue,


@@ -351,11 +351,11 @@ static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue,
                /*
                 * Must do a full switch here to handle all cases.  We
                 * use a fake WQE pointer, as the POW does not access
                /*
                 * Must do a full switch here to handle all cases.  We
                 * use a fake WQE pointer, as the POW does not access

-                * this memory.  The WQE pointer and group are only
+                * this memory.  The WQE pointer and group are only

                 * used if this work is descheduled, which is not
                 * supported by the
                 * cvmx_pko_send_packet_prepare/cvmx_pko_send_packet_finish
                 * used if this work is descheduled, which is not
                 * supported by the
                 * cvmx_pko_send_packet_prepare/cvmx_pko_send_packet_finish

-                * combination.  Note that this is a special case in
+                * combination.  Note that this is a special case in

                 * which these fake values can be used - this is not a
                 * general technique.
                 */
                 * which these fake values can be used - this is not a
                 * general technique.
                 */


@@ -377,10 +377,10 @@ static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue,
  * @port:   Port to send it on
  * @queue:  Queue to use
  * @pko_command:
  * @port:   Port to send it on
  * @queue:  Queue to use
  * @pko_command:

- *               PKO HW command word
+ *              PKO HW command word

  * @packet: Packet to send
  * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
  * @packet: Packet to send
  * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or

- *               CVMX_PKO_LOCK_CMD_QUEUE
+ *              CVMX_PKO_LOCK_CMD_QUEUE

  *
  * Returns returns CVMX_PKO_SUCCESS on success, or error code on
  * failure of output
  *
  * Returns returns CVMX_PKO_SUCCESS on success, or error code on
  * failure of output


@@ -418,12 +418,12 @@ static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(
  * @port:   Port to send it on
  * @queue:  Queue to use
  * @pko_command:
  * @port:   Port to send it on
  * @queue:  Queue to use
  * @pko_command:

- *               PKO HW command word
+ *              PKO HW command word

  * @packet: Packet to send
  * @addr: Plysical address of a work queue entry or physical address
  * @packet: Packet to send
  * @addr: Plysical address of a work queue entry or physical address

- *        to zero on complete.
+ *       to zero on complete.

  * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
  * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or

- *               CVMX_PKO_LOCK_CMD_QUEUE
+ *              CVMX_PKO_LOCK_CMD_QUEUE

  *
  * Returns returns CVMX_PKO_SUCCESS on success, or error code on
  * failure of output
  *
  * Returns returns CVMX_PKO_SUCCESS on success, or error code on
  * failure of output


@@ -588,7 +588,7 @@ static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear,
  * @port:      Port to rate limit
  * @packets_s: Maximum packet/sec
  * @burst:     Maximum number of packets to burst in a row before rate
  * @port:      Port to rate limit
  * @packets_s: Maximum packet/sec
  * @burst:     Maximum number of packets to burst in a row before rate

- *                  limiting cuts in.
+ *                 limiting cuts in.

  *
  * Returns Zero on success, negative on failure
  */
  *
  * Returns Zero on success, negative on failure
  */


@@ -601,7 +601,7 @@ extern int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst);
  * @port:   Port to rate limit
  * @bits_s: PKO rate limit in bits/sec
  * @burst:  Maximum number of bits to burst before rate
  * @port:   Port to rate limit
  * @bits_s: PKO rate limit in bits/sec
  * @burst:  Maximum number of bits to burst before rate

- *               limiting cuts in.
+ *              limiting cuts in.

  *
  * Returns Zero on success, negative on failure
  */
  *
  * Returns Zero on success, negative on failure
  */

diff --git a/arch/mips/include/asm/octeon/cvmx-pow.h b/arch/mips/include/asm/octeon/cvmx-pow.h
index 92742b241a51b80e8be2e02cfcc2e464a286e6f1..4b4d0ecfd9eb70672bffcf45ea747bf3676e33cd 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-pow.h
+++ b/arch/mips/include/asm/octeon/cvmx-pow.h
@@ -70,7 +70,7 @@ enum cvmx_pow_tag_type {
         * The work queue entry from the order - NEVER tag switch from
         * NULL to NULL
         */
         * The work queue entry from the order - NEVER tag switch from
         * NULL to NULL
         */

-       CVMX_POW_TAG_TYPE_NULL      = 2L,
+       CVMX_POW_TAG_TYPE_NULL      = 2L,

        /* A tag switch to NULL, and there is no space reserved in POW
         * - NEVER tag switch to NULL_NULL
         * - NEVER tag switch from NULL_NULL
        /* A tag switch to NULL, and there is no space reserved in POW
         * - NEVER tag switch to NULL_NULL
         * - NEVER tag switch from NULL_NULL


@@ -90,7 +90,7 @@ typedef enum {
 } cvmx_pow_wait_t;
 
 /**
 } cvmx_pow_wait_t;
 
 /**

- *  POW tag operations.  These are used in the data stored to the POW.
+ *  POW tag operations.         These are used in the data stored to the POW.

  */
 typedef enum {
        /*
  */
 typedef enum {
        /*


@@ -341,14 +341,14 @@ typedef union {
                 * lists.  The two memory-input queue lists associated
                 * with each QOS level are:
                 *
                 * lists.  The two memory-input queue lists associated
                 * with each QOS level are:
                 *

-                * - qosgrp = 0, qosgrp = 8:      QOS0
-                * - qosgrp = 1, qosgrp = 9:      QOS1
-                * - qosgrp = 2, qosgrp = 10:     QOS2
-                * - qosgrp = 3, qosgrp = 11:     QOS3
-                * - qosgrp = 4, qosgrp = 12:     QOS4
-                * - qosgrp = 5, qosgrp = 13:     QOS5
-                * - qosgrp = 6, qosgrp = 14:     QOS6
-                * - qosgrp = 7, qosgrp = 15:     QOS7
+                * - qosgrp = 0, qosgrp = 8:      QOS0
+                * - qosgrp = 1, qosgrp = 9:      QOS1
+                * - qosgrp = 2, qosgrp = 10:     QOS2
+                * - qosgrp = 3, qosgrp = 11:     QOS3
+                * - qosgrp = 4, qosgrp = 12:     QOS4
+                * - qosgrp = 5, qosgrp = 13:     QOS5
+                * - qosgrp = 6, qosgrp = 14:     QOS6
+                * - qosgrp = 7, qosgrp = 15:     QOS7

                 */
                uint64_t qosgrp:4;
                /*
                 */
                uint64_t qosgrp:4;
                /*


@@ -942,11 +942,11 @@ typedef union {
  *  operations.
  *
  *  NOTE: The following is the behavior of the pending switch bit at the PP
  *  operations.
  *
  *  NOTE: The following is the behavior of the pending switch bit at the PP

- *       for POW stores (i.e. when did<7:3> == 0xc)
- *     - did<2:0> == 0      => pending switch bit is set
- *     - did<2:0> == 1      => no affect on the pending switch bit
- *     - did<2:0> == 3      => pending switch bit is cleared
- *     - did<2:0> == 7      => no affect on the pending switch bit
+ *      for POW stores (i.e. when did<7:3> == 0xc)
+ *     - did<2:0> == 0     => pending switch bit is set
+ *     - did<2:0> == 1     => no affect on the pending switch bit
+ *     - did<2:0> == 3     => pending switch bit is cleared
+ *     - did<2:0> == 7     => no affect on the pending switch bit

  *     - did<2:0> == others => must not be used
  *     - No other loads/stores have an affect on the pending switch bit
  *     - The switch bus from POW can clear the pending switch bit
  *     - did<2:0> == others => must not be used
  *     - No other loads/stores have an affect on the pending switch bit
  *     - The switch bus from POW can clear the pending switch bit


@@ -1053,7 +1053,7 @@ static inline cvmx_wqe_t *cvmx_pow_get_current_wqp(void)
 }
 
 #ifndef CVMX_MF_CHORD
 }
 
 #ifndef CVMX_MF_CHORD

-#define CVMX_MF_CHORD(dest)         CVMX_RDHWR(dest, 30)
+#define CVMX_MF_CHORD(dest)        CVMX_RDHWR(dest, 30)

 #endif
 
 /**
 #endif
 
 /**


@@ -1097,7 +1097,7 @@ static inline void cvmx_pow_tag_sw_wait(void)
  * so the caller must ensure that there is not a pending tag switch.
  *
  * @wait:   When set, call stalls until work becomes avaiable, or times out.
  * so the caller must ensure that there is not a pending tag switch.
  *
  * @wait:   When set, call stalls until work becomes avaiable, or times out.

- *               If not set, returns immediately.
+ *              If not set, returns immediately.

  *
  * Returns Returns the WQE pointer from POW. Returns NULL if no work
  * was available.
  *
  * Returns Returns the WQE pointer from POW. Returns NULL if no work
  * was available.


@@ -1131,7 +1131,7 @@ static inline cvmx_wqe_t *cvmx_pow_work_request_sync_nocheck(cvmx_pow_wait_t
  * requesting the new work.
  *
  * @wait:   When set, call stalls until work becomes avaiable, or times out.
  * requesting the new work.
  *
  * @wait:   When set, call stalls until work becomes avaiable, or times out.

- *               If not set, returns immediately.
+ *              If not set, returns immediately.

  *
  * Returns Returns the WQE pointer from POW. Returns NULL if no work
  * was available.
  *
  * Returns Returns the WQE pointer from POW. Returns NULL if no work
  * was available.


@@ -1148,7 +1148,7 @@ static inline cvmx_wqe_t *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait)
 }
 
 /**
 }
 
 /**

- * Synchronous null_rd request.  Requests a switch out of NULL_NULL POW state.
+ * Synchronous null_rd request.         Requests a switch out of NULL_NULL POW state.

  * This function waits for any previous tag switch to complete before
  * requesting the null_rd.
  *
  * This function waits for any previous tag switch to complete before
  * requesting the null_rd.
  *


@@ -1183,11 +1183,11 @@ static inline enum cvmx_pow_tag_type cvmx_pow_work_request_null_rd(void)
  * there is not a pending tag switch.
  *
  * @scr_addr: Scratch memory address that response will be returned
  * there is not a pending tag switch.
  *
  * @scr_addr: Scratch memory address that response will be returned

- *            to, which is either a valid WQE, or a response with the
- *            invalid bit set.  Byte address, must be 8 byte aligned.
+ *           to, which is either a valid WQE, or a response with the
+ *           invalid bit set.  Byte address, must be 8 byte aligned.

  *
  * @wait: 1 to cause response to wait for work to become available (or
  *
  * @wait: 1 to cause response to wait for work to become available (or

- *        timeout), 0 to cause response to return immediately
+ *       timeout), 0 to cause response to return immediately

  */
 static inline void cvmx_pow_work_request_async_nocheck(int scr_addr,
                                                       cvmx_pow_wait_t wait)
  */
 static inline void cvmx_pow_work_request_async_nocheck(int scr_addr,
                                                       cvmx_pow_wait_t wait)


@@ -1212,11 +1212,11 @@ static inline void cvmx_pow_work_request_async_nocheck(int scr_addr,
  * tag switch to complete before requesting the new work.
  *
  * @scr_addr: Scratch memory address that response will be returned
  * tag switch to complete before requesting the new work.
  *
  * @scr_addr: Scratch memory address that response will be returned

- *            to, which is either a valid WQE, or a response with the
- *            invalid bit set.  Byte address, must be 8 byte aligned.
+ *           to, which is either a valid WQE, or a response with the
+ *           invalid bit set.  Byte address, must be 8 byte aligned.

  *
  * @wait: 1 to cause response to wait for work to become available (or
  *
  * @wait: 1 to cause response to wait for work to become available (or

- *                  timeout), 0 to cause response to return immediately
+ *                 timeout), 0 to cause response to return immediately

  */
 static inline void cvmx_pow_work_request_async(int scr_addr,
                                               cvmx_pow_wait_t wait)
  */
 static inline void cvmx_pow_work_request_async(int scr_addr,
                                               cvmx_pow_wait_t wait)


@@ -1234,7 +1234,7 @@ static inline void cvmx_pow_work_request_async(int scr_addr,
  * to wait for the response.
  *
  * @scr_addr: Scratch memory address to get result from Byte address,
  * to wait for the response.
  *
  * @scr_addr: Scratch memory address to get result from Byte address,

- *            must be 8 byte aligned.
+ *           must be 8 byte aligned.

  *
  * Returns Returns the WQE from the scratch register, or NULL if no
  * work was available.
  *
  * Returns Returns the WQE from the scratch register, or NULL if no
  * work was available.


@@ -1260,7 +1260,7 @@ static inline cvmx_wqe_t *cvmx_pow_work_response_async(int scr_addr)
  * @wqe_ptr: pointer to a work queue entry returned by the POW
  *
  * Returns 0 if pointer is valid
  * @wqe_ptr: pointer to a work queue entry returned by the POW
  *
  * Returns 0 if pointer is valid

- *         1 if invalid (no work was returned)
+ *        1 if invalid (no work was returned)

  */
 static inline uint64_t cvmx_pow_work_invalid(cvmx_wqe_t *wqe_ptr)
 {
  */
 static inline uint64_t cvmx_pow_work_invalid(cvmx_wqe_t *wqe_ptr)
 {


@@ -1314,7 +1314,7 @@ static inline void cvmx_pow_tag_sw_nocheck(uint32_t tag,
        /*
         * Note that WQE in DRAM is not updated here, as the POW does
         * not read from DRAM once the WQE is in flight.  See hardware
        /*
         * Note that WQE in DRAM is not updated here, as the POW does
         * not read from DRAM once the WQE is in flight.  See hardware

-        * manual for complete details.  It is the application's
+        * manual for complete details.  It is the application's

         * responsibility to keep track of the current tag value if
         * that is important.
         */
         * responsibility to keep track of the current tag value if
         * that is important.
         */


@@ -1361,7 +1361,7 @@ static inline void cvmx_pow_tag_sw(uint32_t tag,
        /*
         * Note that WQE in DRAM is not updated here, as the POW does
         * not read from DRAM once the WQE is in flight.  See hardware
        /*
         * Note that WQE in DRAM is not updated here, as the POW does
         * not read from DRAM once the WQE is in flight.  See hardware

-        * manual for complete details.  It is the application's
+        * manual for complete details.  It is the application's

         * responsibility to keep track of the current tag value if
         * that is important.
         */
         * responsibility to keep track of the current tag value if
         * that is important.
         */


@@ -1390,7 +1390,7 @@ static inline void cvmx_pow_tag_sw(uint32_t tag,
  * previous tag switch has completed.
  *
  * @wqp:      pointer to work queue entry to submit.  This entry is
  * previous tag switch has completed.
  *
  * @wqp:      pointer to work queue entry to submit.  This entry is

- *            updated to match the other parameters
+ *           updated to match the other parameters

  * @tag:      tag value to be assigned to work queue entry
  * @tag_type: type of tag
  * @group:    group value for the work queue entry.
  * @tag:      tag value to be assigned to work queue entry
  * @tag_type: type of tag
  * @group:    group value for the work queue entry.


@@ -1429,7 +1429,7 @@ static inline void cvmx_pow_tag_sw_full_nocheck(cvmx_wqe_t *wqp, uint32_t tag,
        /*
         * Note that WQE in DRAM is not updated here, as the POW does
         * not read from DRAM once the WQE is in flight.  See hardware
        /*
         * Note that WQE in DRAM is not updated here, as the POW does
         * not read from DRAM once the WQE is in flight.  See hardware

-        * manual for complete details.  It is the application's
+        * manual for complete details.  It is the application's

         * responsibility to keep track of the current tag value if
         * that is important.
         */
         * responsibility to keep track of the current tag value if
         * that is important.
         */


@@ -1468,10 +1468,10 @@ static inline void cvmx_pow_tag_sw_full_nocheck(cvmx_wqe_t *wqp, uint32_t tag,
  * before requesting the tag switch.
  *
  * @wqp:      pointer to work queue entry to submit.  This entry is updated
  * before requesting the tag switch.
  *
  * @wqp:      pointer to work queue entry to submit.  This entry is updated

- *            to match the other parameters
+ *           to match the other parameters

  * @tag:      tag value to be assigned to work queue entry
  * @tag_type: type of tag
  * @tag:      tag value to be assigned to work queue entry
  * @tag_type: type of tag

- * @group:      group value for the work queue entry.
+ * @group:     group value for the work queue entry.

  */
 static inline void cvmx_pow_tag_sw_full(cvmx_wqe_t *wqp, uint32_t tag,
                                        enum cvmx_pow_tag_type tag_type,
  */
 static inline void cvmx_pow_tag_sw_full(cvmx_wqe_t *wqp, uint32_t tag,
                                        enum cvmx_pow_tag_type tag_type,


@@ -1560,7 +1560,7 @@ static inline void cvmx_pow_tag_sw_null(void)
  * unrelated to the tag that the core currently holds.
  *
  * @wqp:      pointer to work queue entry to submit.  This entry is
  * unrelated to the tag that the core currently holds.
  *
  * @wqp:      pointer to work queue entry to submit.  This entry is

- *            updated to match the other parameters
+ *           updated to match the other parameters

  * @tag:      tag value to be assigned to work queue entry
  * @tag_type: type of tag
  * @qos:      Input queue to add to.
  * @tag:      tag value to be assigned to work queue entry
  * @tag_type: type of tag
  * @qos:      Input queue to add to.


@@ -1592,7 +1592,7 @@ static inline void cvmx_pow_work_submit(cvmx_wqe_t *wqp, uint32_t tag,
        ptr.sio.offset = cvmx_ptr_to_phys(wqp);
 
        /*
        ptr.sio.offset = cvmx_ptr_to_phys(wqp);
 
        /*

-        * SYNC write to memory before the work submit.  This is
+        * SYNC write to memory before the work submit.  This is

         * necessary as POW may read values from DRAM at this time.
         */
        CVMX_SYNCWS;
         * necessary as POW may read values from DRAM at this time.
         */
        CVMX_SYNCWS;


@@ -1604,11 +1604,11 @@ static inline void cvmx_pow_work_submit(cvmx_wqe_t *wqp, uint32_t tag,
  * indicates which groups each core will accept work from. There are
  * 16 groups.
  *
  * indicates which groups each core will accept work from. There are
  * 16 groups.
  *

- * @core_num:   core to apply mask to
+ * @core_num:  core to apply mask to

  * @mask:   Group mask. There are 16 groups, so only bits 0-15 are valid,
  * @mask:   Group mask. There are 16 groups, so only bits 0-15 are valid,

- *               representing groups 0-15.
- *               Each 1 bit in the mask enables the core to accept work from
- *               the corresponding group.
+ *              representing groups 0-15.
+ *              Each 1 bit in the mask enables the core to accept work from
+ *              the corresponding group.

  */
 static inline void cvmx_pow_set_group_mask(uint64_t core_num, uint64_t mask)
 {
  */
 static inline void cvmx_pow_set_group_mask(uint64_t core_num, uint64_t mask)
 {


@@ -1623,14 +1623,14 @@ static inline void cvmx_pow_set_group_mask(uint64_t core_num, uint64_t mask)
  * This function sets POW static priorities for a core. Each input queue has
  * an associated priority value.
  *
  * This function sets POW static priorities for a core. Each input queue has
  * an associated priority value.
  *

- * @core_num:   core to apply priorities to
- * @priority:   Vector of 8 priorities, one per POW Input Queue (0-7).
- *                   Highest priority is 0 and lowest is 7. A priority value
- *                   of 0xF instructs POW to skip the Input Queue when
- *                   scheduling to this specific core.
- *                   NOTE: priorities should not have gaps in values, meaning
- *                         {0,1,1,1,1,1,1,1} is a valid configuration while
- *                         {0,2,2,2,2,2,2,2} is not.
+ * @core_num:  core to apply priorities to
+ * @priority:  Vector of 8 priorities, one per POW Input Queue (0-7).
+ *                  Highest priority is 0 and lowest is 7. A priority value
+ *                  of 0xF instructs POW to skip the Input Queue when
+ *                  scheduling to this specific core.
+ *                  NOTE: priorities should not have gaps in values, meaning
+ *                        {0,1,1,1,1,1,1,1} is a valid configuration while
+ *                        {0,2,2,2,2,2,2,2} is not.

  */
 static inline void cvmx_pow_set_priority(uint64_t core_num,
                                         const uint8_t priority[])
  */
 static inline void cvmx_pow_set_priority(uint64_t core_num,
                                         const uint8_t priority[])


@@ -1708,8 +1708,8 @@ static inline void cvmx_pow_set_priority(uint64_t core_num,
  * @tag_type: New tag type
  * @group:    New group value
  * @no_sched: Control whether this work queue entry will be rescheduled.
  * @tag_type: New tag type
  * @group:    New group value
  * @no_sched: Control whether this work queue entry will be rescheduled.

- *                 - 1 : don't schedule this work
- *                 - 0 : allow this work to be scheduled.
+ *                - 1 : don't schedule this work
+ *                - 0 : allow this work to be scheduled.

  */
 static inline void cvmx_pow_tag_sw_desched_nocheck(
        uint32_t tag,
  */
 static inline void cvmx_pow_tag_sw_desched_nocheck(
        uint32_t tag,


@@ -1794,8 +1794,8 @@ static inline void cvmx_pow_tag_sw_desched_nocheck(
  * @tag_type: New tag type
  * @group:    New group value
  * @no_sched: Control whether this work queue entry will be rescheduled.
  * @tag_type: New tag type
  * @group:    New group value
  * @no_sched: Control whether this work queue entry will be rescheduled.

- *                 - 1 : don't schedule this work
- *                 - 0 : allow this work to be scheduled.
+ *                - 1 : don't schedule this work
+ *                - 0 : allow this work to be scheduled.

  */
 static inline void cvmx_pow_tag_sw_desched(uint32_t tag,
                                           enum cvmx_pow_tag_type tag_type,
  */
 static inline void cvmx_pow_tag_sw_desched(uint32_t tag,
                                           enum cvmx_pow_tag_type tag_type,


@@ -1819,8 +1819,8 @@ static inline void cvmx_pow_tag_sw_desched(uint32_t tag,
  * Descchedules the current work queue entry.
  *
  * @no_sched: no schedule flag value to be set on the work queue
  * Descchedules the current work queue entry.
  *
  * @no_sched: no schedule flag value to be set on the work queue

- *            entry.  If this is set the entry will not be
- *            rescheduled.
+ *           entry.  If this is set the entry will not be
+ *           rescheduled.

  */
 static inline void cvmx_pow_desched(uint64_t no_sched)
 {
  */
 static inline void cvmx_pow_desched(uint64_t no_sched)
 {


@@ -1863,7 +1863,7 @@ static inline void cvmx_pow_desched(uint64_t no_sched)
 *****************************************************/
 
 /*
 *****************************************************/
 
 /*

- * Number of bits of the tag used by software.  The SW bits are always
+ * Number of bits of the tag used by software. The SW bits are always

  * a contiguous block of the high starting at bit 31.  The hardware
  * bits are always the low bits.  By default, the top 8 bits of the
  * tag are reserved for software, and the low 24 are set by the IPD
  * a contiguous block of the high starting at bit 31.  The hardware
  * bits are always the low bits.  By default, the top 8 bits of the
  * tag are reserved for software, and the low 24 are set by the IPD


@@ -1890,7 +1890,7 @@ static inline void cvmx_pow_desched(uint64_t no_sched)
  * are defined here.
  */
 /* Mask for the value portion of the tag */
  * are defined here.
  */
 /* Mask for the value portion of the tag */

-#define CVMX_TAG_SUBGROUP_MASK  0xFFFF
+#define CVMX_TAG_SUBGROUP_MASK 0xFFFF

 #define CVMX_TAG_SUBGROUP_SHIFT 16
 #define CVMX_TAG_SUBGROUP_PKO  0x1
 
 #define CVMX_TAG_SUBGROUP_SHIFT 16
 #define CVMX_TAG_SUBGROUP_PKO  0x1
 


@@ -1905,12 +1905,12 @@ static inline void cvmx_pow_desched(uint64_t no_sched)
  * This function creates a 32 bit tag value from the two values provided.
  *
  * @sw_bits: The upper bits (number depends on configuration) are set
  * This function creates a 32 bit tag value from the two values provided.
  *
  * @sw_bits: The upper bits (number depends on configuration) are set

- *           to this value.  The remainder of bits are set by the
- *           hw_bits parameter.
+ *          to this value.  The remainder of bits are set by the
+ *          hw_bits parameter.

  *
  * @hw_bits: The lower bits (number depends on configuration) are set
  *
  * @hw_bits: The lower bits (number depends on configuration) are set

- *           to this value.  The remainder of bits are set by the
- *           sw_bits parameter.
+ *          to this value.  The remainder of bits are set by the
+ *          sw_bits parameter.

  *
  * Returns 32 bit value of the combined hw and sw bits.
  */
  *
  * Returns 32 bit value of the combined hw and sw bits.
  */


@@ -1957,7 +1957,7 @@ static inline uint32_t cvmx_pow_tag_get_hw_bits(uint64_t tag)
  *
  * @buffer: Buffer to store capture into
  * @buffer_size:
  *
  * @buffer: Buffer to store capture into
  * @buffer_size:

- *               The size of the supplied buffer
+ *              The size of the supplied buffer

  *
  * Returns Zero on success, negative on failure
  */
  *
  * Returns Zero on success, negative on failure
  */


@@ -1968,7 +1968,7 @@ extern int cvmx_pow_capture(void *buffer, int buffer_size);
  *
  * @buffer: POW capture from cvmx_pow_capture()
  * @buffer_size:
  *
  * @buffer: POW capture from cvmx_pow_capture()
  * @buffer_size:

- *               Size of the buffer
+ *              Size of the buffer

  */
 extern void cvmx_pow_display(void *buffer, int buffer_size);
 
  */
 extern void cvmx_pow_display(void *buffer, int buffer_size);
 

diff --git a/arch/mips/include/asm/octeon/cvmx-scratch.h b/arch/mips/include/asm/octeon/cvmx-scratch.h
index 96b70cfd624567ef0c5067d809df12dda6e1c239..8d21cc5e4e40bfa11df90d7c3a457e8f294989e2 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-scratch.h
+++ b/arch/mips/include/asm/octeon/cvmx-scratch.h
@@ -39,7 +39,7 @@
  * Note: This define must be a long, not a long long in order to
  * compile without warnings for both 32bit and 64bit.
  */
  * Note: This define must be a long, not a long long in order to
  * compile without warnings for both 32bit and 64bit.
  */

-#define CVMX_SCRATCH_BASE       (-32768l)      /* 0xffffffffffff8000 */
+#define CVMX_SCRATCH_BASE      (-32768l)       /* 0xffffffffffff8000 */

 
 /**
  * Reads an 8 bit value from the processor local scratchpad memory.
 
 /**
  * Reads an 8 bit value from the processor local scratchpad memory.

diff --git a/arch/mips/include/asm/octeon/cvmx-spi.h b/arch/mips/include/asm/octeon/cvmx-spi.h
index 3bf53b537bcfaf73ef8c975e5b96ee0c7edd96e3..d5038cc4b475a50f2581b2feed55654634450120 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-spi.h
+++ b/arch/mips/include/asm/octeon/cvmx-spi.h
@@ -84,11 +84,11 @@ static inline int cvmx_spi_is_spi_interface(int interface)
  * Initialize and start the SPI interface.
  *
  * @interface: The identifier of the packet interface to configure and
  * Initialize and start the SPI interface.
  *
  * @interface: The identifier of the packet interface to configure and

- *                  use as a SPI interface.
+ *                 use as a SPI interface.

  * @mode:      The operating mode for the SPI interface. The interface
  * @mode:      The operating mode for the SPI interface. The interface

- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
+ *                 can operate as a full duplex (both Tx and Rx data paths
+ *                 active) or as a halfplex (either the Tx data path is
+ *                 active or the Rx data path is active, but not both).

  * @timeout:   Timeout to wait for clock synchronization in seconds
  * @num_ports: Number of SPI ports to configure
  *
  * @timeout:   Timeout to wait for clock synchronization in seconds
  * @num_ports: Number of SPI ports to configure
  *


@@ -102,11 +102,11 @@ extern int cvmx_spi_start_interface(int interface, cvmx_spi_mode_t mode,
  * with its corespondant system.
  *
  * @interface: The identifier of the packet interface to configure and
  * with its corespondant system.
  *
  * @interface: The identifier of the packet interface to configure and

- *                  use as a SPI interface.
+ *                 use as a SPI interface.

  * @mode:      The operating mode for the SPI interface. The interface
  * @mode:      The operating mode for the SPI interface. The interface

- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
+ *                 can operate as a full duplex (both Tx and Rx data paths
+ *                 active) or as a halfplex (either the Tx data path is
+ *                 active or the Rx data path is active, but not both).

  * @timeout:   Timeout to wait for clock synchronization in seconds
  * Returns Zero on success, negative of failure.
  */
  * @timeout:   Timeout to wait for clock synchronization in seconds
  * Returns Zero on success, negative of failure.
  */


@@ -154,7 +154,7 @@ static inline union cvmx_gmxx_rxx_rx_inbnd cvmx_spi4000_check_speed(
 /**
  * Get current SPI4 initialization callbacks
  *
 /**
  * Get current SPI4 initialization callbacks
  *

- * @callbacks:  Pointer to the callbacks structure.to fill
+ * @callbacks: Pointer to the callbacks structure.to fill

  *
  * Returns Pointer to cvmx_spi_callbacks_t structure.
  */
  *
  * Returns Pointer to cvmx_spi_callbacks_t structure.
  */


@@ -171,11 +171,11 @@ extern void cvmx_spi_set_callbacks(cvmx_spi_callbacks_t *new_callbacks);
  * Callback to perform SPI4 reset
  *
  * @interface: The identifier of the packet interface to configure and
  * Callback to perform SPI4 reset
  *
  * @interface: The identifier of the packet interface to configure and

- *                  use as a SPI interface.
+ *                 use as a SPI interface.

  * @mode:      The operating mode for the SPI interface. The interface
  * @mode:      The operating mode for the SPI interface. The interface

- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
+ *                 can operate as a full duplex (both Tx and Rx data paths
+ *                 active) or as a halfplex (either the Tx data path is
+ *                 active or the Rx data path is active, but not both).

  *
  * Returns Zero on success, non-zero error code on failure (will cause
  * SPI initialization to abort)
  *
  * Returns Zero on success, non-zero error code on failure (will cause
  * SPI initialization to abort)


@@ -187,11 +187,11 @@ extern int cvmx_spi_reset_cb(int interface, cvmx_spi_mode_t mode);
  * detection
  *
  * @interface: The identifier of the packet interface to configure and
  * detection
  *
  * @interface: The identifier of the packet interface to configure and

- *                  use as a SPI interface.
+ *                 use as a SPI interface.

  * @mode:      The operating mode for the SPI interface. The interface
  * @mode:      The operating mode for the SPI interface. The interface

- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
+ *                 can operate as a full duplex (both Tx and Rx data paths
+ *                 active) or as a halfplex (either the Tx data path is
+ *                 active or the Rx data path is active, but not both).

  * @num_ports: Number of ports to configure on SPI
  *
  * Returns Zero on success, non-zero error code on failure (will cause
  * @num_ports: Number of ports to configure on SPI
  *
  * Returns Zero on success, non-zero error code on failure (will cause


@@ -204,11 +204,11 @@ extern int cvmx_spi_calendar_setup_cb(int interface, cvmx_spi_mode_t mode,
  * Callback to perform clock detection
  *
  * @interface: The identifier of the packet interface to configure and
  * Callback to perform clock detection
  *
  * @interface: The identifier of the packet interface to configure and

- *                  use as a SPI interface.
+ *                 use as a SPI interface.

  * @mode:      The operating mode for the SPI interface. The interface
  * @mode:      The operating mode for the SPI interface. The interface

- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
+ *                 can operate as a full duplex (both Tx and Rx data paths
+ *                 active) or as a halfplex (either the Tx data path is
+ *                 active or the Rx data path is active, but not both).

  * @timeout:   Timeout to wait for clock synchronization in seconds
  *
  * Returns Zero on success, non-zero error code on failure (will cause
  * @timeout:   Timeout to wait for clock synchronization in seconds
  *
  * Returns Zero on success, non-zero error code on failure (will cause


@@ -221,11 +221,11 @@ extern int cvmx_spi_clock_detect_cb(int interface, cvmx_spi_mode_t mode,
  * Callback to perform link training
  *
  * @interface: The identifier of the packet interface to configure and
  * Callback to perform link training
  *
  * @interface: The identifier of the packet interface to configure and

- *                  use as a SPI interface.
+ *                 use as a SPI interface.

  * @mode:      The operating mode for the SPI interface. The interface
  * @mode:      The operating mode for the SPI interface. The interface

- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
+ *                 can operate as a full duplex (both Tx and Rx data paths
+ *                 active) or as a halfplex (either the Tx data path is
+ *                 active or the Rx data path is active, but not both).

  * @timeout:   Timeout to wait for link to be trained (in seconds)
  *
  * Returns Zero on success, non-zero error code on failure (will cause
  * @timeout:   Timeout to wait for link to be trained (in seconds)
  *
  * Returns Zero on success, non-zero error code on failure (will cause


@@ -238,11 +238,11 @@ extern int cvmx_spi_training_cb(int interface, cvmx_spi_mode_t mode,
  * Callback to perform calendar data synchronization
  *
  * @interface: The identifier of the packet interface to configure and
  * Callback to perform calendar data synchronization
  *
  * @interface: The identifier of the packet interface to configure and

- *                  use as a SPI interface.
+ *                 use as a SPI interface.

  * @mode:      The operating mode for the SPI interface. The interface
  * @mode:      The operating mode for the SPI interface. The interface

- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
+ *                 can operate as a full duplex (both Tx and Rx data paths
+ *                 active) or as a halfplex (either the Tx data path is
+ *                 active or the Rx data path is active, but not both).

  * @timeout:   Timeout to wait for calendar data in seconds
  *
  * Returns Zero on success, non-zero error code on failure (will cause
  * @timeout:   Timeout to wait for calendar data in seconds
  *
  * Returns Zero on success, non-zero error code on failure (will cause


@@ -255,11 +255,11 @@ extern int cvmx_spi_calendar_sync_cb(int interface, cvmx_spi_mode_t mode,
  * Callback to handle interface up
  *
  * @interface: The identifier of the packet interface to configure and
  * Callback to handle interface up
  *
  * @interface: The identifier of the packet interface to configure and

- *                  use as a SPI interface.
+ *                 use as a SPI interface.

  * @mode:      The operating mode for the SPI interface. The interface
  * @mode:      The operating mode for the SPI interface. The interface

- *                  can operate as a full duplex (both Tx and Rx data paths
- *                  active) or as a halfplex (either the Tx data path is
- *                  active or the Rx data path is active, but not both).
+ *                 can operate as a full duplex (both Tx and Rx data paths
+ *                 active) or as a halfplex (either the Tx data path is
+ *                 active or the Rx data path is active, but not both).

  *
  * Returns Zero on success, non-zero error code on failure (will cause
  * SPI initialization to abort)
  *
  * Returns Zero on success, non-zero error code on failure (will cause
  * SPI initialization to abort)

diff --git a/arch/mips/include/asm/octeon/cvmx-spinlock.h b/arch/mips/include/asm/octeon/cvmx-spinlock.h
index a672abb1bc4f2a196c63909452ef188472e7e97c..4f09cff8b8c021d03f13f7bd0353a76e570ac3f9 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-spinlock.h
+++ b/arch/mips/include/asm/octeon/cvmx-spinlock.h
@@ -26,7 +26,7 @@
  ***********************license end**************************************/
 
 /**
  ***********************license end**************************************/
 
 /**

- * Implementation of spinlocks for Octeon CVMX.  Although similar in
+ * Implementation of spinlocks for Octeon CVMX.         Although similar in

  * function to Linux kernel spinlocks, they are not compatible.
  * Octeon CVMX spinlocks are only used to synchronize with the boot
  * monitor and other non-Linux programs running in the system.
  * function to Linux kernel spinlocks, they are not compatible.
  * Octeon CVMX spinlocks are only used to synchronize with the boot
  * monitor and other non-Linux programs running in the system.


@@ -50,8 +50,8 @@ typedef struct {
 } cvmx_spinlock_t;
 
 /* note - macros not expanded in inline ASM, so values hardcoded */
 } cvmx_spinlock_t;
 
 /* note - macros not expanded in inline ASM, so values hardcoded */

-#define  CVMX_SPINLOCK_UNLOCKED_VAL  0
-#define  CVMX_SPINLOCK_LOCKED_VAL    1
+#define         CVMX_SPINLOCK_UNLOCKED_VAL  0
+#define         CVMX_SPINLOCK_LOCKED_VAL    1

 
 #define CVMX_SPINLOCK_UNLOCKED_INITIALIZER  {CVMX_SPINLOCK_UNLOCKED_VAL}
 
 
 #define CVMX_SPINLOCK_UNLOCKED_INITIALIZER  {CVMX_SPINLOCK_UNLOCKED_VAL}
 


@@ -96,7 +96,7 @@ static inline void cvmx_spinlock_unlock(cvmx_spinlock_t *lock)
  * @lock:   pointer to lock structure
  *
  * Returns 0: lock successfully taken
  * @lock:   pointer to lock structure
  *
  * Returns 0: lock successfully taken

- *         1: lock not taken, held by someone else
+ *        1: lock not taken, held by someone else

  * These return values match the Linux semantics.
  */
 
  * These return values match the Linux semantics.
  */
 


@@ -104,16 +104,16 @@ static inline unsigned int cvmx_spinlock_trylock(cvmx_spinlock_t *lock)
 {
        unsigned int tmp;
 
 {
        unsigned int tmp;
 

-       __asm__ __volatile__(".set noreorder         \n"
+       __asm__ __volatile__(".set noreorder         \n"

                             "1: ll   %[tmp], %[val] \n"
                        /* if lock held, fail immediately */
                             "1: ll   %[tmp], %[val] \n"
                        /* if lock held, fail immediately */

-                            "   bnez %[tmp], 2f     \n"
-                            "   li   %[tmp], 1      \n"
-                            "   sc   %[tmp], %[val] \n"
-                            "   beqz %[tmp], 1b     \n"
-                            "   li   %[tmp], 0      \n"
-                            "2:                     \n"
-                            ".set reorder           \n" :
+                            "   bnez %[tmp], 2f     \n"
+                            "   li   %[tmp], 1      \n"
+                            "   sc   %[tmp], %[val] \n"
+                            "   beqz %[tmp], 1b     \n"
+                            "   li   %[tmp], 0      \n"
+                            "2:                     \n"
+                            ".set reorder           \n" :

                        [val] "+m"(lock->value), [tmp] "=&r"(tmp)
                             : : "memory");
 
                        [val] "+m"(lock->value), [tmp] "=&r"(tmp)
                             : : "memory");
 


@@ -129,14 +129,14 @@ static inline void cvmx_spinlock_lock(cvmx_spinlock_t *lock)
 {
        unsigned int tmp;
 
 {
        unsigned int tmp;
 

-       __asm__ __volatile__(".set noreorder         \n"
+       __asm__ __volatile__(".set noreorder         \n"

                             "1: ll   %[tmp], %[val]  \n"
                             "1: ll   %[tmp], %[val]  \n"

-                            "   bnez %[tmp], 1b     \n"
-                            "   li   %[tmp], 1      \n"
-                            "   sc   %[tmp], %[val] \n"
-                            "   beqz %[tmp], 1b     \n"
-                            "   nop                \n"
-                            ".set reorder           \n" :
+                            "   bnez %[tmp], 1b     \n"
+                            "   li   %[tmp], 1      \n"
+                            "   sc   %[tmp], %[val] \n"
+                            "   beqz %[tmp], 1b     \n"
+                            "   nop                \n"
+                            ".set reorder           \n" :

                        [val] "+m"(lock->value), [tmp] "=&r"(tmp)
                        : : "memory");
 
                        [val] "+m"(lock->value), [tmp] "=&r"(tmp)
                        : : "memory");
 


@@ -163,17 +163,17 @@ static inline void cvmx_spinlock_bit_lock(uint32_t *word)
        unsigned int tmp;
        unsigned int sav;
 
        unsigned int tmp;
        unsigned int sav;
 

-       __asm__ __volatile__(".set noreorder         \n"
-                            ".set noat              \n"
+       __asm__ __volatile__(".set noreorder         \n"
+                            ".set noat              \n"

                             "1: ll    %[tmp], %[val]  \n"
                             "1: ll    %[tmp], %[val]  \n"

-                            "   bbit1 %[tmp], 31, 1b    \n"
-                            "   li    $at, 1      \n"
-                            "   ins   %[tmp], $at, 31, 1  \n"
-                            "   sc    %[tmp], %[val] \n"
-                            "   beqz  %[tmp], 1b     \n"
-                            "   nop                \n"
-                            ".set at              \n"
-                            ".set reorder           \n" :
+                            "   bbit1 %[tmp], 31, 1b    \n"
+                            "   li    $at, 1      \n"
+                            "   ins   %[tmp], $at, 31, 1  \n"
+                            "   sc    %[tmp], %[val] \n"
+                            "   beqz  %[tmp], 1b     \n"
+                            "   nop                \n"
+                            ".set at              \n"
+                            ".set reorder           \n" :

                        [val] "+m"(*word), [tmp] "=&r"(tmp), [sav] "=&r"(sav)
                             : : "memory");
 
                        [val] "+m"(*word), [tmp] "=&r"(tmp), [sav] "=&r"(sav)
                             : : "memory");
 


@@ -187,7 +187,7 @@ static inline void cvmx_spinlock_bit_lock(uint32_t *word)
  *
  * @word:  word to lock bit 31 of
  * Returns 0: lock successfully taken
  *
  * @word:  word to lock bit 31 of
  * Returns 0: lock successfully taken

- *         1: lock not taken, held by someone else
+ *        1: lock not taken, held by someone else

  * These return values match the Linux semantics.
  */
 static inline unsigned int cvmx_spinlock_bit_trylock(uint32_t *word)
  * These return values match the Linux semantics.
  */
 static inline unsigned int cvmx_spinlock_bit_trylock(uint32_t *word)


@@ -198,15 +198,15 @@ static inline unsigned int cvmx_spinlock_bit_trylock(uint32_t *word)
                             ".set noat\n"
                             "1: ll    %[tmp], %[val] \n"
                        /* if lock held, fail immediately */
                             ".set noat\n"
                             "1: ll    %[tmp], %[val] \n"
                        /* if lock held, fail immediately */

-                            "   bbit1 %[tmp], 31, 2f     \n"
-                            "   li    $at, 1      \n"
-                            "   ins   %[tmp], $at, 31, 1  \n"
-                            "   sc    %[tmp], %[val] \n"
-                            "   beqz  %[tmp], 1b     \n"
-                            "   li    %[tmp], 0      \n"
-                            "2:                     \n"
-                            ".set at              \n"
-                            ".set reorder           \n" :
+                            "   bbit1 %[tmp], 31, 2f     \n"
+                            "   li    $at, 1      \n"
+                            "   ins   %[tmp], $at, 31, 1  \n"
+                            "   sc    %[tmp], %[val] \n"
+                            "   beqz  %[tmp], 1b     \n"
+                            "   li    %[tmp], 0      \n"
+                            "2:                     \n"
+                            ".set at              \n"
+                            ".set reorder           \n" :

                        [val] "+m"(*word), [tmp] "=&r"(tmp)
                        : : "memory");
 
                        [val] "+m"(*word), [tmp] "=&r"(tmp)
                        : : "memory");
 

diff --git a/arch/mips/include/asm/octeon/cvmx-sysinfo.h b/arch/mips/include/asm/octeon/cvmx-sysinfo.h
index 61dd5741afe49996509d59f6a9bd337fce99e28d..2131197422e5202a11ac4b8f6e518bbd88f48781 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-sysinfo.h
+++ b/arch/mips/include/asm/octeon/cvmx-sysinfo.h
@@ -85,7 +85,7 @@ struct cvmx_sysinfo {
        char board_serial_number[OCTEON_SERIAL_LEN];
        /*
         * Several boards support compact flash on the Octeon boot
        char board_serial_number[OCTEON_SERIAL_LEN];
        /*
         * Several boards support compact flash on the Octeon boot

-        * bus.  The CF memory spaces may be mapped to different
+        * bus.  The CF memory spaces may be mapped to different

         * addresses on different boards.  These values will be 0 if
         * CF is not present.  Note that these addresses are physical
         * addresses, and it is up to the application to use the
         * addresses on different boards.  These values will be 0 if
         * CF is not present.  Note that these addresses are physical
         * addresses, and it is up to the application to use the


@@ -123,25 +123,25 @@ extern struct cvmx_sysinfo *cvmx_sysinfo_get(void);
 
 /**
  * This function is used in non-simple executive environments (such as
 
 /**
  * This function is used in non-simple executive environments (such as

- * Linux kernel, u-boot, etc.)  to configure the minimal fields that
+ * Linux kernel, u-boot, etc.) to configure the minimal fields that

  * are required to use simple executive files directly.
  *
  * Locking (if required) must be handled outside of this
  * function
  *
  * @phy_mem_desc_ptr: Pointer to global physical memory descriptor
  * are required to use simple executive files directly.
  *
  * Locking (if required) must be handled outside of this
  * function
  *
  * @phy_mem_desc_ptr: Pointer to global physical memory descriptor

- *                   (bootmem descriptor) @board_type: Octeon board
- *                   type enumeration
+ *                  (bootmem descriptor) @board_type: Octeon board
+ *                  type enumeration

  *
  * @board_rev_major:
  *
  * @board_rev_major:

- *                   Board major revision
+ *                  Board major revision

  * @board_rev_minor:
  * @board_rev_minor:

- *                   Board minor revision
+ *                  Board minor revision

  * @cpu_clock_hz:
  * @cpu_clock_hz:

- *                   CPU clock freqency in hertz
+ *                  CPU clock freqency in hertz

  *
  * Returns 0: Failure
  *
  * Returns 0: Failure

- *         1: success
+ *        1: success

  */
 extern int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr,
                                           uint16_t board_type,
  */
 extern int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr,
                                           uint16_t board_type,

diff --git a/arch/mips/include/asm/octeon/cvmx-wqe.h b/arch/mips/include/asm/octeon/cvmx-wqe.h
index df762389e27130237838f3299220e43f92220f7e..aa0d3d0de75c5785aef9c0a6267c2f8903e9dc4f 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx-wqe.h
+++ b/arch/mips/include/asm/octeon/cvmx-wqe.h
@@ -101,23 +101,23 @@ typedef union {
                 * - 1 = Malformed L4
                 * - 2 = L4 Checksum Error: the L4 checksum value is
                 * - 3 = UDP Length Error: The UDP length field would
                 * - 1 = Malformed L4
                 * - 2 = L4 Checksum Error: the L4 checksum value is
                 * - 3 = UDP Length Error: The UDP length field would

-                *       make the UDP data longer than what remains in
-                *       the IP packet (as defined by the IP header
-                *       length field).
+                *       make the UDP data longer than what remains in
+                *       the IP packet (as defined by the IP header
+                *       length field).

                 * - 4 = Bad L4 Port: either the source or destination
                 * - 4 = Bad L4 Port: either the source or destination

-                *       TCP/UDP port is 0.
+                *       TCP/UDP port is 0.

                 * - 8 = TCP FIN Only: the packet is TCP and only the
                 * - 8 = TCP FIN Only: the packet is TCP and only the

-                *       FIN flag set.
+                *       FIN flag set.

                 * - 9 = TCP No Flags: the packet is TCP and no flags
                 * - 9 = TCP No Flags: the packet is TCP and no flags

-                *       are set.
+                *       are set.

                 * - 10 = TCP FIN RST: the packet is TCP and both FIN
                 * - 10 = TCP FIN RST: the packet is TCP and both FIN

-                *        and RST are set.
+                *        and RST are set.

                 * - 11 = TCP SYN URG: the packet is TCP and both SYN
                 * - 11 = TCP SYN URG: the packet is TCP and both SYN

-                *        and URG are set.
+                *        and URG are set.

                 * - 12 = TCP SYN RST: the packet is TCP and both SYN
                 * - 12 = TCP SYN RST: the packet is TCP and both SYN

-                *        and RST are set.
+                *        and RST are set.

                 * - 13 = TCP SYN FIN: the packet is TCP and both SYN
                 * - 13 = TCP SYN FIN: the packet is TCP and both SYN

-                *        and FIN are set.
+                *        and FIN are set.

                 */
                uint64_t L4_error:1;
                /* set if the packet is a fragment */
                 */
                uint64_t L4_error:1;
                /* set if the packet is a fragment */


@@ -127,16 +127,16 @@ typedef union {
                 * failure indicated in err_code below, decode:
                 *
                 * - 1 = Not IP: the IP version field is neither 4 nor
                 * failure indicated in err_code below, decode:
                 *
                 * - 1 = Not IP: the IP version field is neither 4 nor

-                *       6.
+                *       6.

                 * - 2 = IPv4 Header Checksum Error: the IPv4 header
                 * - 2 = IPv4 Header Checksum Error: the IPv4 header

-                *       has a checksum violation.
+                *       has a checksum violation.

                 * - 3 = IP Malformed Header: the packet is not long
                 * - 3 = IP Malformed Header: the packet is not long

-                *       enough to contain the IP header.
+                *       enough to contain the IP header.

                 * - 4 = IP Malformed: the packet is not long enough
                 *       to contain the bytes indicated by the IP
                 *       header. Pad is allowed.
                 * - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6
                 * - 4 = IP Malformed: the packet is not long enough
                 *       to contain the bytes indicated by the IP
                 *       header. Pad is allowed.
                 * - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6

-                *       Hop Count field are zero.
+                *       Hop Count field are zero.

                 * - 6 = IP Options
                 */
                uint64_t IP_exc:1;
                 * - 6 = IP Options
                 */
                uint64_t IP_exc:1;


@@ -243,46 +243,46 @@ typedef union {
                 * decode:
                 *
                 * - 1 = partial error: a packet was partially
                 * decode:
                 *
                 * - 1 = partial error: a packet was partially

-                *       received, but internal buffering / bandwidth
-                *       was not adequate to receive the entire
-                *       packet.
+                *       received, but internal buffering / bandwidth
+                *       was not adequate to receive the entire
+                *       packet.

                 * - 2 = jabber error: the RGMII packet was too large
                 * - 2 = jabber error: the RGMII packet was too large

-                *       and is truncated.
+                *       and is truncated.

                 * - 3 = overrun error: the RGMII packet is longer
                 * - 3 = overrun error: the RGMII packet is longer

-                *       than allowed and had an FCS error.
+                *       than allowed and had an FCS error.

                 * - 4 = oversize error: the RGMII packet is longer
                 * - 4 = oversize error: the RGMII packet is longer

-                *       than allowed.
+                *       than allowed.

                 * - 5 = alignment error: the RGMII packet is not an
                 * - 5 = alignment error: the RGMII packet is not an

-                *       integer number of bytes
-                *       and had an FCS error (100M and 10M only).
+                *       integer number of bytes
+                *       and had an FCS error (100M and 10M only).

                 * - 6 = fragment error: the RGMII packet is shorter
                 * - 6 = fragment error: the RGMII packet is shorter

-                *       than allowed and had an FCS error.
+                *       than allowed and had an FCS error.

                 * - 7 = GMX FCS error: the RGMII packet had an FCS
                 * - 7 = GMX FCS error: the RGMII packet had an FCS

-                *       error.
+                *       error.

                 * - 8 = undersize error: the RGMII packet is shorter
                 * - 8 = undersize error: the RGMII packet is shorter

-                *       than allowed.
+                *       than allowed.

                 * - 9 = extend error: the RGMII packet had an extend
                 * - 9 = extend error: the RGMII packet had an extend

-                *       error.
+                *       error.

                 * - 10 = length mismatch error: the RGMII packet had
                 * - 10 = length mismatch error: the RGMII packet had

-                *        a length that did not match the length field
-                *        in the L2 HDR.
+                *        a length that did not match the length field
+                *        in the L2 HDR.

                 * - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII
                 * - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII

-                *        packet had one or more data reception errors
-                *        (RXERR) or the SPI4 packet had one or more
-                *        DIP4 errors.
+                *        packet had one or more data reception errors
+                *        (RXERR) or the SPI4 packet had one or more
+                *        DIP4 errors.

                 * - 12 = RGMII skip error/SPI4 Abort Error: the RGMII
                 * - 12 = RGMII skip error/SPI4 Abort Error: the RGMII

-                *        packet was not large enough to cover the
-                *        skipped bytes or the SPI4 packet was
-                *        terminated with an About EOPS.
+                *        packet was not large enough to cover the
+                *        skipped bytes or the SPI4 packet was
+                *        terminated with an About EOPS.

                 * - 13 = RGMII nibble error/SPI4 Port NXA Error: the
                 * - 13 = RGMII nibble error/SPI4 Port NXA Error: the

-                *        RGMII packet had a studder error (data not
-                *        repeated - 10/100M only) or the SPI4 packet
-                *        was sent to an NXA.
+                *        RGMII packet had a studder error (data not
+                *        repeated - 10/100M only) or the SPI4 packet
+                *        was sent to an NXA.

                 * - 16 = FCS error: a SPI4.2 packet had an FCS error.
                 * - 17 = Skip error: a packet was not large enough to
                 * - 16 = FCS error: a SPI4.2 packet had an FCS error.
                 * - 17 = Skip error: a packet was not large enough to

-                *        cover the skipped bytes.
+                *        cover the skipped bytes.

                 * - 18 = L2 header malformed: the packet is not long
                 * - 18 = L2 header malformed: the packet is not long

-                *        enough to contain the L2.
+                *        enough to contain the L2.

                 */
 
                uint64_t rcv_error:1;
                 */
 
                uint64_t rcv_error:1;


@@ -309,7 +309,7 @@ typedef struct {
 
     /*****************************************************************
      * WORD 0
 
     /*****************************************************************
      * WORD 0

-     *  HW WRITE: the following 64 bits are filled by HW when a packet arrives
+     * HW WRITE: the following 64 bits are filled by HW when a packet arrives

      */
 
     /**
      */
 
     /**


@@ -323,14 +323,14 @@ typedef struct {
     /**
      * Next pointer used by hardware for list maintenance.
      * May be written/read by HW before the work queue
     /**
      * Next pointer used by hardware for list maintenance.
      * May be written/read by HW before the work queue

-     *           entry is scheduled to a PP
+     *          entry is scheduled to a PP

      * (Only 36 bits used in Octeon 1)
      */
        uint64_t next_ptr:40;
 
     /*****************************************************************
      * WORD 1
      * (Only 36 bits used in Octeon 1)
      */
        uint64_t next_ptr:40;
 
     /*****************************************************************
      * WORD 1

-     *  HW WRITE: the following 64 bits are filled by HW when a packet arrives
+     * HW WRITE: the following 64 bits are filled by HW when a packet arrives

      */
 
     /**
      */
 
     /**


@@ -362,8 +362,8 @@ typedef struct {
 
     /**
      * WORD 2 HW WRITE: the following 64-bits are filled in by
 
     /**
      * WORD 2 HW WRITE: the following 64-bits are filled in by

-     *   hardware when a packet arrives This indicates a variety of
-     *   status and error conditions.
+     *  hardware when a packet arrives This indicates a variety of
+     *  status and error conditions.

      */
        cvmx_pip_wqe_word2 word2;
 
      */
        cvmx_pip_wqe_word2 word2;
 


@@ -373,15 +373,15 @@ typedef struct {
        union cvmx_buf_ptr packet_ptr;
 
     /**
        union cvmx_buf_ptr packet_ptr;
 
     /**

-     *   HW WRITE: octeon will fill in a programmable amount from the
-     *             packet, up to (at most, but perhaps less) the amount
-     *             needed to fill the work queue entry to 128 bytes
+     *  HW WRITE: octeon will fill in a programmable amount from the
+     *            packet, up to (at most, but perhaps less) the amount
+     *            needed to fill the work queue entry to 128 bytes

      *
      *

-     *   If the packet is recognized to be IP, the hardware starts
-     *   (except that the IPv4 header is padded for appropriate
-     *   alignment) writing here where the IP header starts.  If the
-     *   packet is not recognized to be IP, the hardware starts
-     *   writing the beginning of the packet here.
+     *  If the packet is recognized to be IP, the hardware starts
+     *  (except that the IPv4 header is padded for appropriate
+     *  alignment) writing here where the IP header starts.  If the
+     *  packet is not recognized to be IP, the hardware starts
+     *  writing the beginning of the packet here.

      */
        uint8_t packet_data[96];
 
      */
        uint8_t packet_data[96];
 

diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
index db58beab6cb292bea83984850cc8863f54a503ae..f991e7701d3d3d4a908af18377d363e10ae6a04c 100644 (file)
--- a/arch/mips/include/asm/octeon/cvmx.h
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -76,14 +76,14 @@ enum cvmx_mips_space {
 #endif
 
 #if CVMX_ENABLE_DEBUG_PRINTS
 #endif
 
 #if CVMX_ENABLE_DEBUG_PRINTS

-#define cvmx_dprintf        printk
+#define cvmx_dprintf       printk

 #else
 #define cvmx_dprintf(...)   {}
 #endif
 
 #else
 #define cvmx_dprintf(...)   {}
 #endif
 

-#define CVMX_MAX_CORES          (16)
-#define CVMX_CACHE_LINE_SIZE    (128)  /* In bytes */
-#define CVMX_CACHE_LINE_MASK    (CVMX_CACHE_LINE_SIZE - 1)     /* In bytes */
+#define CVMX_MAX_CORES         (16)
+#define CVMX_CACHE_LINE_SIZE   (128)   /* In bytes */
+#define CVMX_CACHE_LINE_MASK   (CVMX_CACHE_LINE_SIZE - 1)      /* In bytes */

 #define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE)))
 #define CAST64(v) ((long long)(long)(v))
 #define CASTPTR(type, v) ((type *)(long)(v))
 #define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE)))
 #define CAST64(v) ((long long)(long)(v))
 #define CASTPTR(type, v) ((type *)(long)(v))


@@ -133,8 +133,8 @@ static inline uint64_t cvmx_build_io_address(uint64_t major_did,
  *
  * Example: cvmx_build_bits(39,24,value)
  * <pre>
  *
  * Example: cvmx_build_bits(39,24,value)
  * <pre>

- * 6       5       4       3       3       2       1
- * 3       5       7       9       1       3       5       7      0
+ * 6      5       4       3       3       2       1
+ * 3      5       7       9       1       3       5       7      0

  * +-------+-------+-------+-------+-------+-------+-------+------+
  * 000000000000000000000000___________value000000000000000000000000
  * </pre>
  * +-------+-------+-------+-------+-------+-------+-------+------+
  * 000000000000000000000000___________value000000000000000000000000
  * </pre>


@@ -183,7 +183,7 @@ static inline uint64_t cvmx_ptr_to_phys(void *ptr)
  * memory pointer (void *).
  *
  * @physical_address:
  * memory pointer (void *).
  *
  * @physical_address:

- *               Hardware physical address to memory
+ *              Hardware physical address to memory

  * Returns Pointer to memory
  */
 static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
  * Returns Pointer to memory
  */
 static inline void *cvmx_phys_to_ptr(uint64_t physical_address)


@@ -207,10 +207,10 @@ static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
 
 /* We have a full 64bit ABI. Writing to a 64bit address can be done with
     a simple volatile pointer */
 
 /* We have a full 64bit ABI. Writing to a 64bit address can be done with
     a simple volatile pointer */

-#define CVMX_BUILD_WRITE64(TYPE, ST)                                    \
-static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val)     \
-{                                                                       \
-    *CASTPTR(volatile TYPE##_t, addr) = val;                            \
+#define CVMX_BUILD_WRITE64(TYPE, ST)                                   \
+static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val)    \
+{                                                                      \
+    *CASTPTR(volatile TYPE##_t, addr) = val;                           \

 }
 
 
 }
 
 


@@ -221,19 +221,19 @@ static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val)     \
 
 /* We have a full 64bit ABI. Writing to a 64bit address can be done with
     a simple volatile pointer */
 
 /* We have a full 64bit ABI. Writing to a 64bit address can be done with
     a simple volatile pointer */

-#define CVMX_BUILD_READ64(TYPE, LT)                                     \
-static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr)                \
-{                                                                       \
+#define CVMX_BUILD_READ64(TYPE, LT)                                    \
+static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr)               \
+{                                                                      \

        return *CASTPTR(volatile TYPE##_t, addr);                       \
 }
 
 
 /* The following defines 8 functions for writing to a 64bit address. Each
     takes two arguments, the address and the value to write.
        return *CASTPTR(volatile TYPE##_t, addr);                       \
 }
 
 
 /* The following defines 8 functions for writing to a 64bit address. Each
     takes two arguments, the address and the value to write.

-    cvmx_write64_int64      cvmx_write64_uint64
-    cvmx_write64_int32      cvmx_write64_uint32
-    cvmx_write64_int16      cvmx_write64_uint16
-    cvmx_write64_int8       cvmx_write64_uint8 */
+    cvmx_write64_int64     cvmx_write64_uint64
+    cvmx_write64_int32     cvmx_write64_uint32
+    cvmx_write64_int16     cvmx_write64_uint16
+    cvmx_write64_int8      cvmx_write64_uint8 */

 CVMX_BUILD_WRITE64(int64, "sd");
 CVMX_BUILD_WRITE64(int32, "sw");
 CVMX_BUILD_WRITE64(int16, "sh");
 CVMX_BUILD_WRITE64(int64, "sd");
 CVMX_BUILD_WRITE64(int32, "sw");
 CVMX_BUILD_WRITE64(int16, "sh");


@@ -246,10 +246,10 @@ CVMX_BUILD_WRITE64(uint8, "sb");
 
 /* The following defines 8 functions for reading from a 64bit address. Each
     takes the address as the only argument
 
 /* The following defines 8 functions for reading from a 64bit address. Each
     takes the address as the only argument

-    cvmx_read64_int64       cvmx_read64_uint64
-    cvmx_read64_int32       cvmx_read64_uint32
-    cvmx_read64_int16       cvmx_read64_uint16
-    cvmx_read64_int8        cvmx_read64_uint8 */
+    cvmx_read64_int64      cvmx_read64_uint64
+    cvmx_read64_int32      cvmx_read64_uint32
+    cvmx_read64_int16      cvmx_read64_uint16
+    cvmx_read64_int8       cvmx_read64_uint8 */

 CVMX_BUILD_READ64(int64, "ld");
 CVMX_BUILD_READ64(int32, "lw");
 CVMX_BUILD_READ64(int16, "lh");
 CVMX_BUILD_READ64(int64, "ld");
 CVMX_BUILD_READ64(int32, "lw");
 CVMX_BUILD_READ64(int16, "lh");


@@ -389,7 +389,7 @@ static inline void cvmx_wait(uint64_t cycles)
 
 /**
  * Reads a chip global cycle counter.  This counts CPU cycles since
 
 /**
  * Reads a chip global cycle counter.  This counts CPU cycles since

- * chip reset.  The counter is 64 bit.
+ * chip reset. The counter is 64 bit.

  * This register does not exist on CN38XX pass 1 silicion
  *
  * Returns Global chip cycle count since chip reset.
  * This register does not exist on CN38XX pass 1 silicion
  *
  * Returns Global chip cycle count since chip reset.


@@ -453,7 +453,7 @@ static inline uint32_t cvmx_octeon_num_cores(void)
 
 /**
  * Read a byte of fuse data
 
 /**
  * Read a byte of fuse data

- * @byte_addr:   address to read
+ * @byte_addr:  address to read

  *
  * Returns fuse value: 0 or 1
  */
  *
  * Returns fuse value: 0 or 1
  */

diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h
index 8008da2f87794f2d4e564d891ebb93dac5a1022e..90e05a8d4b152add46184784d3e9707009deb4f6 100644 (file)
--- a/arch/mips/include/asm/octeon/octeon-feature.h
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -35,7 +35,7 @@
 #include <asm/octeon/cvmx-rnm-defs.h>
 
 enum octeon_feature {
 #include <asm/octeon/cvmx-rnm-defs.h>
 
 enum octeon_feature {

-        /* CN68XX uses port kinds for packet interface */
+       /* CN68XX uses port kinds for packet interface */

        OCTEON_FEATURE_PKND,
        /* CN68XX has different fields in word0 - word2 */
        OCTEON_FEATURE_CN68XX_WQE,
        OCTEON_FEATURE_PKND,
        /* CN68XX has different fields in word0 - word2 */
        OCTEON_FEATURE_CN68XX_WQE,


@@ -51,7 +51,7 @@ enum octeon_feature {
        OCTEON_FEATURE_DORM_CRYPTO,
        /* Does this Octeon support PCI express? */
        OCTEON_FEATURE_PCIE,
        OCTEON_FEATURE_DORM_CRYPTO,
        /* Does this Octeon support PCI express? */
        OCTEON_FEATURE_PCIE,

-        /* Does this Octeon support SRIOs */
+       /* Does this Octeon support SRIOs */

        OCTEON_FEATURE_SRIO,
        /*  Does this Octeon support Interlaken */
        OCTEON_FEATURE_ILK,
        OCTEON_FEATURE_SRIO,
        /*  Does this Octeon support Interlaken */
        OCTEON_FEATURE_ILK,


@@ -75,7 +75,7 @@ enum octeon_feature {
        /* Octeon MDIO block supports clause 45 transactions for 10
         * Gig support */
        OCTEON_FEATURE_MDIO_CLAUSE_45,
        /* Octeon MDIO block supports clause 45 transactions for 10
         * Gig support */
        OCTEON_FEATURE_MDIO_CLAUSE_45,

-        /*
+       /*

         *  CN52XX and CN56XX used a block named NPEI for PCIe
         *  access. Newer chips replaced this with SLI+DPI.
         */
         *  CN52XX and CN56XX used a block named NPEI for PCIe
         *  access. Newer chips replaced this with SLI+DPI.
         */


@@ -94,10 +94,10 @@ static inline int cvmx_fuse_read(int fuse);
  * be kept out of fast path code.
  *
  * @feature: Feature to check for. This should always be a constant so the
  * be kept out of fast path code.
  *
  * @feature: Feature to check for. This should always be a constant so the

- *                compiler can remove the switch statement through optimization.
+ *               compiler can remove the switch statement through optimization.

  *
  * Returns Non zero if the feature exists. Zero if the feature does not
  *
  * Returns Non zero if the feature exists. Zero if the feature does not

- *         exist.
+ *        exist.

  */
 static inline int octeon_has_feature(enum octeon_feature feature)
 {
  */
 static inline int octeon_has_feature(enum octeon_feature feature)
 {

diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h
index 349bb2ba840cc0260453262c9b080183ee7978f4..e2c122c6a657a69df8d821fc50bf3b1f2cb7ef6e 100644 (file)
--- a/arch/mips/include/asm/octeon/octeon-model.h
+++ b/arch/mips/include/asm/octeon/octeon-model.h
@@ -29,7 +29,7 @@
 
 /*
  * The defines below should be used with the OCTEON_IS_MODEL() macro
 
 /*
  * The defines below should be used with the OCTEON_IS_MODEL() macro

- * to determine what model of chip the software is running on.  Models
+ * to determine what model of chip the software is running on. Models

  * ending in 'XX' match multiple models (families), while specific
  * models match only that model.  If a pass (revision) is specified,
  * then only that revision will be matched.  Care should be taken when
  * ending in 'XX' match multiple models (families), while specific
  * models match only that model.  If a pass (revision) is specified,
  * then only that revision will be matched.  Care should be taken when


@@ -40,183 +40,183 @@
  * subject to change at anytime without notice.
  *
  * NOTE: only the OCTEON_IS_MODEL() macro/function and the OCTEON_CN*
  * subject to change at anytime without notice.
  *
  * NOTE: only the OCTEON_IS_MODEL() macro/function and the OCTEON_CN*

- * macros should be used outside of this file.  All other macros are
+ * macros should be used outside of this file. All other macros are

  * for internal use only, and may change without notice.
  */
 
  * for internal use only, and may change without notice.
  */
 

-#define OCTEON_FAMILY_MASK      0x00ffff00
+#define OCTEON_FAMILY_MASK     0x00ffff00

 
 /* Flag bits in top byte */
 /* Ignores revision in model checks */
 
 /* Flag bits in top byte */
 /* Ignores revision in model checks */

-#define OM_IGNORE_REVISION        0x01000000
+#define OM_IGNORE_REVISION       0x01000000

 /* Check submodels */
 /* Check submodels */

-#define OM_CHECK_SUBMODEL         0x02000000
+#define OM_CHECK_SUBMODEL        0x02000000

 /* Match all models previous than the one specified */
 #define OM_MATCH_PREVIOUS_MODELS  0x04000000
 /* Ignores the minor revison on newer parts */
 #define OM_IGNORE_MINOR_REVISION  0x08000000
 /* Match all models previous than the one specified */
 #define OM_MATCH_PREVIOUS_MODELS  0x04000000
 /* Ignores the minor revison on newer parts */
 #define OM_IGNORE_MINOR_REVISION  0x08000000

-#define OM_FLAG_MASK              0xff000000
+#define OM_FLAG_MASK             0xff000000

 
 /* Match all cn5XXX Octeon models. */
 
 /* Match all cn5XXX Octeon models. */

-#define OM_MATCH_5XXX_FAMILY_MODELS     0x20000000
+#define OM_MATCH_5XXX_FAMILY_MODELS    0x20000000

 /* Match all cn6XXX Octeon models. */
 /* Match all cn6XXX Octeon models. */

-#define OM_MATCH_6XXX_FAMILY_MODELS     0x40000000
+#define OM_MATCH_6XXX_FAMILY_MODELS    0x40000000

 /* Match all cnf7XXX Octeon models. */
 /* Match all cnf7XXX Octeon models. */

-#define OM_MATCH_F7XXX_FAMILY_MODELS    0x80000000
+#define OM_MATCH_F7XXX_FAMILY_MODELS   0x80000000

 
 /*
  * CNF7XXX models with new revision encoding
  */
 
 /*
  * CNF7XXX models with new revision encoding
  */

-#define OCTEON_CNF71XX_PASS1_0  0x000d9400
+#define OCTEON_CNF71XX_PASS1_0 0x000d9400

 
 

-#define OCTEON_CNF71XX          (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_REVISION)
-#define OCTEON_CNF71XX_PASS1_X  (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CNF71XX         (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CNF71XX_PASS1_X (OCTEON_CNF71XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)

 
 /*
  * CN6XXX models with new revision encoding
  */
 
 /*
  * CN6XXX models with new revision encoding
  */

-#define OCTEON_CN68XX_PASS1_0   0x000d9100
-#define OCTEON_CN68XX_PASS1_1   0x000d9101
-#define OCTEON_CN68XX_PASS1_2   0x000d9102
-#define OCTEON_CN68XX_PASS2_0   0x000d9108
+#define OCTEON_CN68XX_PASS1_0  0x000d9100
+#define OCTEON_CN68XX_PASS1_1  0x000d9101
+#define OCTEON_CN68XX_PASS1_2  0x000d9102
+#define OCTEON_CN68XX_PASS2_0  0x000d9108

 
 

-#define OCTEON_CN68XX           (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN68XX_PASS1_X   (OCTEON_CN68XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN68XX_PASS2_X   (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN68XX          (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN68XX_PASS1_X  (OCTEON_CN68XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN68XX_PASS2_X  (OCTEON_CN68XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)

 
 #define OCTEON_CN68XX_PASS1    OCTEON_CN68XX_PASS1_X
 #define OCTEON_CN68XX_PASS2    OCTEON_CN68XX_PASS2_X
 
 
 #define OCTEON_CN68XX_PASS1    OCTEON_CN68XX_PASS1_X
 #define OCTEON_CN68XX_PASS2    OCTEON_CN68XX_PASS2_X
 

-#define OCTEON_CN66XX_PASS1_0   0x000d9200
-#define OCTEON_CN66XX_PASS1_2   0x000d9202
+#define OCTEON_CN66XX_PASS1_0  0x000d9200
+#define OCTEON_CN66XX_PASS1_2  0x000d9202

 
 

-#define OCTEON_CN66XX           (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN66XX_PASS1_X   (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN66XX          (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN66XX_PASS1_X  (OCTEON_CN66XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)

 
 

-#define OCTEON_CN63XX_PASS1_0   0x000d9000
-#define OCTEON_CN63XX_PASS1_1   0x000d9001
-#define OCTEON_CN63XX_PASS1_2   0x000d9002
-#define OCTEON_CN63XX_PASS2_0   0x000d9008
-#define OCTEON_CN63XX_PASS2_1   0x000d9009
-#define OCTEON_CN63XX_PASS2_2   0x000d900a
+#define OCTEON_CN63XX_PASS1_0  0x000d9000
+#define OCTEON_CN63XX_PASS1_1  0x000d9001
+#define OCTEON_CN63XX_PASS1_2  0x000d9002
+#define OCTEON_CN63XX_PASS2_0  0x000d9008
+#define OCTEON_CN63XX_PASS2_1  0x000d9009
+#define OCTEON_CN63XX_PASS2_2  0x000d900a

 
 

-#define OCTEON_CN63XX           (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN63XX_PASS1_X   (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN63XX_PASS2_X   (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN63XX          (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN63XX_PASS1_X  (OCTEON_CN63XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN63XX_PASS2_X  (OCTEON_CN63XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)

 
 

-#define OCTEON_CN61XX_PASS1_0   0x000d9300
+#define OCTEON_CN61XX_PASS1_0  0x000d9300

 
 

-#define OCTEON_CN61XX           (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN61XX_PASS1_X   (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN61XX          (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN61XX_PASS1_X  (OCTEON_CN61XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)

 
 /*
  * CN5XXX models with new revision encoding
  */
 
 /*
  * CN5XXX models with new revision encoding
  */

-#define OCTEON_CN58XX_PASS1_0   0x000d0300
-#define OCTEON_CN58XX_PASS1_1   0x000d0301
-#define OCTEON_CN58XX_PASS1_2   0x000d0303
-#define OCTEON_CN58XX_PASS2_0   0x000d0308
-#define OCTEON_CN58XX_PASS2_1   0x000d0309
-#define OCTEON_CN58XX_PASS2_2   0x000d030a
-#define OCTEON_CN58XX_PASS2_3   0x000d030b
-
-#define OCTEON_CN58XX           (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN58XX_PASS1_X   (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN58XX_PASS2_X   (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN58XX_PASS1     OCTEON_CN58XX_PASS1_X
-#define OCTEON_CN58XX_PASS2     OCTEON_CN58XX_PASS2_X
-
-#define OCTEON_CN56XX_PASS1_0   0x000d0400
-#define OCTEON_CN56XX_PASS1_1   0x000d0401
-#define OCTEON_CN56XX_PASS2_0   0x000d0408
-#define OCTEON_CN56XX_PASS2_1   0x000d0409
-
-#define OCTEON_CN56XX           (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN56XX_PASS1_X   (OCTEON_CN56XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN56XX_PASS2_X   (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN56XX_PASS1     OCTEON_CN56XX_PASS1_X
-#define OCTEON_CN56XX_PASS2     OCTEON_CN56XX_PASS2_X
-
-#define OCTEON_CN57XX           OCTEON_CN56XX
-#define OCTEON_CN57XX_PASS1     OCTEON_CN56XX_PASS1
-#define OCTEON_CN57XX_PASS2     OCTEON_CN56XX_PASS2
-
-#define OCTEON_CN55XX           OCTEON_CN56XX
-#define OCTEON_CN55XX_PASS1     OCTEON_CN56XX_PASS1
-#define OCTEON_CN55XX_PASS2     OCTEON_CN56XX_PASS2
-
-#define OCTEON_CN54XX           OCTEON_CN56XX
-#define OCTEON_CN54XX_PASS1     OCTEON_CN56XX_PASS1
-#define OCTEON_CN54XX_PASS2     OCTEON_CN56XX_PASS2
-
-#define OCTEON_CN50XX_PASS1_0   0x000d0600
-
-#define OCTEON_CN50XX           (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN50XX_PASS1_X   (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN50XX_PASS1     OCTEON_CN50XX_PASS1_X
+#define OCTEON_CN58XX_PASS1_0  0x000d0300
+#define OCTEON_CN58XX_PASS1_1  0x000d0301
+#define OCTEON_CN58XX_PASS1_2  0x000d0303
+#define OCTEON_CN58XX_PASS2_0  0x000d0308
+#define OCTEON_CN58XX_PASS2_1  0x000d0309
+#define OCTEON_CN58XX_PASS2_2  0x000d030a
+#define OCTEON_CN58XX_PASS2_3  0x000d030b
+
+#define OCTEON_CN58XX          (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN58XX_PASS1_X  (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN58XX_PASS2_X  (OCTEON_CN58XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN58XX_PASS1    OCTEON_CN58XX_PASS1_X
+#define OCTEON_CN58XX_PASS2    OCTEON_CN58XX_PASS2_X
+
+#define OCTEON_CN56XX_PASS1_0  0x000d0400
+#define OCTEON_CN56XX_PASS1_1  0x000d0401
+#define OCTEON_CN56XX_PASS2_0  0x000d0408
+#define OCTEON_CN56XX_PASS2_1  0x000d0409
+
+#define OCTEON_CN56XX          (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN56XX_PASS1_X  (OCTEON_CN56XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN56XX_PASS2_X  (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN56XX_PASS1    OCTEON_CN56XX_PASS1_X
+#define OCTEON_CN56XX_PASS2    OCTEON_CN56XX_PASS2_X
+
+#define OCTEON_CN57XX          OCTEON_CN56XX
+#define OCTEON_CN57XX_PASS1    OCTEON_CN56XX_PASS1
+#define OCTEON_CN57XX_PASS2    OCTEON_CN56XX_PASS2
+
+#define OCTEON_CN55XX          OCTEON_CN56XX
+#define OCTEON_CN55XX_PASS1    OCTEON_CN56XX_PASS1
+#define OCTEON_CN55XX_PASS2    OCTEON_CN56XX_PASS2
+
+#define OCTEON_CN54XX          OCTEON_CN56XX
+#define OCTEON_CN54XX_PASS1    OCTEON_CN56XX_PASS1
+#define OCTEON_CN54XX_PASS2    OCTEON_CN56XX_PASS2
+
+#define OCTEON_CN50XX_PASS1_0  0x000d0600
+
+#define OCTEON_CN50XX          (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN50XX_PASS1_X  (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN50XX_PASS1    OCTEON_CN50XX_PASS1_X

 
 /*
  * NOTE: Octeon CN5000F model is not identifiable using the
  * OCTEON_IS_MODEL() functions, but are treated as CN50XX.
  */
 
 
 /*
  * NOTE: Octeon CN5000F model is not identifiable using the
  * OCTEON_IS_MODEL() functions, but are treated as CN50XX.
  */
 

-#define OCTEON_CN52XX_PASS1_0   0x000d0700
-#define OCTEON_CN52XX_PASS2_0   0x000d0708
+#define OCTEON_CN52XX_PASS1_0  0x000d0700
+#define OCTEON_CN52XX_PASS2_0  0x000d0708

 
 

-#define OCTEON_CN52XX           (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION)
-#define OCTEON_CN52XX_PASS1_X   (OCTEON_CN52XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN52XX_PASS2_X   (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
-#define OCTEON_CN52XX_PASS1     OCTEON_CN52XX_PASS1_X
-#define OCTEON_CN52XX_PASS2     OCTEON_CN52XX_PASS2_X
+#define OCTEON_CN52XX          (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION)
+#define OCTEON_CN52XX_PASS1_X  (OCTEON_CN52XX_PASS1_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN52XX_PASS2_X  (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_MINOR_REVISION)
+#define OCTEON_CN52XX_PASS1    OCTEON_CN52XX_PASS1_X
+#define OCTEON_CN52XX_PASS2    OCTEON_CN52XX_PASS2_X

 
 /*
  * CN3XXX models with old revision enconding
  */
 
 /*
  * CN3XXX models with old revision enconding
  */

-#define OCTEON_CN38XX_PASS1     0x000d0000
-#define OCTEON_CN38XX_PASS2     0x000d0001
-#define OCTEON_CN38XX_PASS3     0x000d0003
-#define OCTEON_CN38XX           (OCTEON_CN38XX_PASS3 | OM_IGNORE_REVISION)
+#define OCTEON_CN38XX_PASS1    0x000d0000
+#define OCTEON_CN38XX_PASS2    0x000d0001
+#define OCTEON_CN38XX_PASS3    0x000d0003
+#define OCTEON_CN38XX          (OCTEON_CN38XX_PASS3 | OM_IGNORE_REVISION)

 
 

-#define OCTEON_CN36XX           OCTEON_CN38XX
-#define OCTEON_CN36XX_PASS2     OCTEON_CN38XX_PASS2
-#define OCTEON_CN36XX_PASS3     OCTEON_CN38XX_PASS3
+#define OCTEON_CN36XX          OCTEON_CN38XX
+#define OCTEON_CN36XX_PASS2    OCTEON_CN38XX_PASS2
+#define OCTEON_CN36XX_PASS3    OCTEON_CN38XX_PASS3

 
 /* The OCTEON_CN31XX matches CN31XX models and the CN3020 */
 
 /* The OCTEON_CN31XX matches CN31XX models and the CN3020 */

-#define OCTEON_CN31XX_PASS1     0x000d0100
-#define OCTEON_CN31XX_PASS1_1   0x000d0102
-#define OCTEON_CN31XX           (OCTEON_CN31XX_PASS1 | OM_IGNORE_REVISION)
+#define OCTEON_CN31XX_PASS1    0x000d0100
+#define OCTEON_CN31XX_PASS1_1  0x000d0102
+#define OCTEON_CN31XX          (OCTEON_CN31XX_PASS1 | OM_IGNORE_REVISION)

 
 /*
  * This model is only used for internal checks, it is not a valid
  * model for the OCTEON_MODEL environment variable.  This matches the
  * CN3010 and CN3005 but NOT the CN3020.
  */
 
 /*
  * This model is only used for internal checks, it is not a valid
  * model for the OCTEON_MODEL environment variable.  This matches the
  * CN3010 and CN3005 but NOT the CN3020.
  */

-#define OCTEON_CN30XX_PASS1     0x000d0200
-#define OCTEON_CN30XX_PASS1_1   0x000d0202
-#define OCTEON_CN30XX           (OCTEON_CN30XX_PASS1 | OM_IGNORE_REVISION)
+#define OCTEON_CN30XX_PASS1    0x000d0200
+#define OCTEON_CN30XX_PASS1_1  0x000d0202
+#define OCTEON_CN30XX          (OCTEON_CN30XX_PASS1 | OM_IGNORE_REVISION)

 
 

-#define OCTEON_CN3005_PASS1     (0x000d0210 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3005_PASS1_0   (0x000d0210 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3005_PASS1_1   (0x000d0212 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3005           (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3005_PASS1    (0x000d0210 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3005_PASS1_0  (0x000d0210 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3005_PASS1_1  (0x000d0212 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3005          (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)

 
 

-#define OCTEON_CN3010_PASS1     (0x000d0200 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3010_PASS1_0   (0x000d0200 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3010_PASS1_1   (0x000d0202 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3010           (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3010_PASS1    (0x000d0200 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3010_PASS1_0  (0x000d0200 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3010_PASS1_1  (0x000d0202 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3010          (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)

 
 

-#define OCTEON_CN3020_PASS1     (0x000d0110 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3020_PASS1_0   (0x000d0110 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3020_PASS1_1   (0x000d0112 | OM_CHECK_SUBMODEL)
-#define OCTEON_CN3020           (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3020_PASS1    (0x000d0110 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3020_PASS1_0  (0x000d0110 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3020_PASS1_1  (0x000d0112 | OM_CHECK_SUBMODEL)
+#define OCTEON_CN3020          (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)

 
 /*
  * This matches the complete family of CN3xxx CPUs, and not subsequent
  * models
  */
 
 /*
  * This matches the complete family of CN3xxx CPUs, and not subsequent
  * models
  */

-#define OCTEON_CN3XXX           (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION)
-#define OCTEON_CN5XXX           (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
-#define OCTEON_CN6XXX           (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)
+#define OCTEON_CN3XXX          (OCTEON_CN58XX_PASS1_0 | OM_MATCH_PREVIOUS_MODELS | OM_IGNORE_REVISION)
+#define OCTEON_CN5XXX          (OCTEON_CN58XX_PASS1_0 | OM_MATCH_5XXX_FAMILY_MODELS)
+#define OCTEON_CN6XXX          (OCTEON_CN63XX_PASS1_0 | OM_MATCH_6XXX_FAMILY_MODELS)

 
 /* These are used to cover entire families of OCTEON processors */
 #define OCTEON_FAM_1           (OCTEON_CN3XXX)
 
 /* These are used to cover entire families of OCTEON processors */
 #define OCTEON_FAM_1           (OCTEON_CN3XXX)


@@ -243,18 +243,18 @@
  */
 
 /* Masks used for the various types of model/family/revision matching */
  */
 
 /* Masks used for the various types of model/family/revision matching */

-#define OCTEON_38XX_FAMILY_MASK      0x00ffff00
+#define OCTEON_38XX_FAMILY_MASK             0x00ffff00

 #define OCTEON_38XX_FAMILY_REV_MASK  0x00ffff0f
 #define OCTEON_38XX_FAMILY_REV_MASK  0x00ffff0f

-#define OCTEON_38XX_MODEL_MASK       0x00ffff10
+#define OCTEON_38XX_MODEL_MASK      0x00ffff10

 #define OCTEON_38XX_MODEL_REV_MASK   (OCTEON_38XX_FAMILY_REV_MASK | OCTEON_38XX_MODEL_MASK)
 
 /* CN5XXX and later use different layout of bits in the revision ID field */
 #define OCTEON_38XX_MODEL_REV_MASK   (OCTEON_38XX_FAMILY_REV_MASK | OCTEON_38XX_MODEL_MASK)
 
 /* CN5XXX and later use different layout of bits in the revision ID field */

-#define OCTEON_58XX_FAMILY_MASK      OCTEON_38XX_FAMILY_MASK
+#define OCTEON_58XX_FAMILY_MASK             OCTEON_38XX_FAMILY_MASK

 #define OCTEON_58XX_FAMILY_REV_MASK  0x00ffff3f
 #define OCTEON_58XX_FAMILY_REV_MASK  0x00ffff3f

-#define OCTEON_58XX_MODEL_MASK       0x00ffffc0
+#define OCTEON_58XX_MODEL_MASK      0x00ffffc0

 #define OCTEON_58XX_MODEL_REV_MASK   (OCTEON_58XX_FAMILY_REV_MASK | OCTEON_58XX_MODEL_MASK)
 #define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK & 0x00fffff8)
 #define OCTEON_58XX_MODEL_REV_MASK   (OCTEON_58XX_FAMILY_REV_MASK | OCTEON_58XX_MODEL_MASK)
 #define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK & 0x00fffff8)

-#define OCTEON_5XXX_MODEL_MASK       0x00ff0fc0
+#define OCTEON_5XXX_MODEL_MASK      0x00ff0fc0

 
 /* forward declarations */
 static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
 
 /* forward declarations */
 static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));


@@ -264,7 +264,7 @@ static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
 
 /* NOTE: This for internal use only! */
 #define __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model)             \
 
 /* NOTE: This for internal use only! */
 #define __OCTEON_IS_MODEL_COMPILE__(arg_model, chip_model)             \

-((((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0)  && (        \
+((((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0)  && ( \

                ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \
                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_MASK)) || \
                ((((arg_model) & (OM_FLAG_MASK)) == 0)                  \
                ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \
                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_38XX_MODEL_MASK)) || \
                ((((arg_model) & (OM_FLAG_MASK)) == 0)                  \


@@ -276,7 +276,7 @@ static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
                ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
                        && (((chip_model) & OCTEON_38XX_MODEL_MASK) < ((arg_model) & OCTEON_38XX_MODEL_MASK))) \
                )) ||                                                   \
                ((((arg_model) & (OM_MATCH_PREVIOUS_MODELS)) == OM_MATCH_PREVIOUS_MODELS) \
                        && (((chip_model) & OCTEON_38XX_MODEL_MASK) < ((arg_model) & OCTEON_38XX_MODEL_MASK))) \
                )) ||                                                   \

-       (((arg_model & OCTEON_38XX_FAMILY_MASK) >= OCTEON_CN58XX_PASS1_0)  && ( \
+       (((arg_model & OCTEON_38XX_FAMILY_MASK) >= OCTEON_CN58XX_PASS1_0)  && ( \

                ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \
                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MASK)) || \
                ((((arg_model) & (OM_FLAG_MASK)) == 0)                  \
                ((((arg_model) & (OM_FLAG_MASK)) == (OM_IGNORE_REVISION | OM_CHECK_SUBMODEL)) \
                        && __OCTEON_MATCH_MASK__((chip_model), (arg_model), OCTEON_58XX_MODEL_MASK)) || \
                ((((arg_model) & (OM_FLAG_MASK)) == 0)                  \


@@ -320,7 +320,7 @@ static inline int __octeon_is_model_runtime__(uint32_t model)
  * Use of the macro in preprocessor directives ( #if OCTEON_IS_MODEL(...) )
  * is NOT SUPPORTED, and should be replaced with CVMX_COMPILED_FOR()
  * I.e.:
  * Use of the macro in preprocessor directives ( #if OCTEON_IS_MODEL(...) )
  * is NOT SUPPORTED, and should be replaced with CVMX_COMPILED_FOR()
  * I.e.:

- *  #if OCTEON_IS_MODEL(OCTEON_CN56XX)  ->  #if CVMX_COMPILED_FOR(OCTEON_CN56XX)
+ *  #if OCTEON_IS_MODEL(OCTEON_CN56XX) ->  #if CVMX_COMPILED_FOR(OCTEON_CN56XX)

  */
 #define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x)
 #define OCTEON_IS_COMMON_BINARY() 1
  */
 #define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x)
 #define OCTEON_IS_COMMON_BINARY() 1

diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index 254e9954ed71ff3a973e44c46425263c0e05eb57..a2eed23c49a958145df685d0386bd0cadf20f539 100644 (file)
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -75,15 +75,15 @@ struct octeon_boot_descriptor {
        uint32_t argc;
        uint32_t argv[OCTEON_ARGV_MAX_ARGS];
 
        uint32_t argc;
        uint32_t argv[OCTEON_ARGV_MAX_ARGS];
 

-#define  BOOT_FLAG_INIT_CORE           (1 << 0)
-#define  OCTEON_BL_FLAG_DEBUG          (1 << 1)
-#define  OCTEON_BL_FLAG_NO_MAGIC       (1 << 2)
+#define         BOOT_FLAG_INIT_CORE            (1 << 0)
+#define         OCTEON_BL_FLAG_DEBUG           (1 << 1)
+#define         OCTEON_BL_FLAG_NO_MAGIC        (1 << 2)

        /* If set, use uart1 for console */
        /* If set, use uart1 for console */

-#define  OCTEON_BL_FLAG_CONSOLE_UART1  (1 << 3)
+#define         OCTEON_BL_FLAG_CONSOLE_UART1   (1 << 3)

        /* If set, use PCI console */
        /* If set, use PCI console */

-#define  OCTEON_BL_FLAG_CONSOLE_PCI    (1 << 4)
+#define         OCTEON_BL_FLAG_CONSOLE_PCI     (1 << 4)

        /* Call exit on break on serial port */
        /* Call exit on break on serial port */

-#define  OCTEON_BL_FLAG_BREAK          (1 << 5)
+#define         OCTEON_BL_FLAG_BREAK           (1 << 5)

 
        uint32_t flags;
        uint32_t core_mask;
 
        uint32_t flags;
        uint32_t core_mask;

diff --git a/arch/mips/include/asm/octeon/pci-octeon.h b/arch/mips/include/asm/octeon/pci-octeon.h
index c66734bd33821a1549d72eb1f7163e7fe5de108a..64ba56a028431eb89750e16731345dcf5bcb4e72 100644 (file)
--- a/arch/mips/include/asm/octeon/pci-octeon.h
+++ b/arch/mips/include/asm/octeon/pci-octeon.h
@@ -22,7 +22,7 @@
 #define CVMX_PCIE_BAR1_PHYS_SIZE (1ull << 28)
 
 /*
 #define CVMX_PCIE_BAR1_PHYS_SIZE (1ull << 28)
 
 /*

- * The RC base of BAR1.  gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2,
+ * The RC base of BAR1.         gen1 has a 39-bit BAR2, gen2 has 41-bit BAR2,

  * place BAR1 so it is the same for both.
  */
 #define CVMX_PCIE_BAR1_RC_BASE (1ull << 41)
  * place BAR1 so it is the same for both.
  */
 #define CVMX_PCIE_BAR1_RC_BASE (1ull << 41)

diff --git a/arch/mips/include/asm/paccess.h b/arch/mips/include/asm/paccess.h
index 9ce5a1e7e14ce5e965bb61af520267f70fdbdaf6..2474fc5d1751cedcf3f0caf3004d4dec4ea28be1 100644 (file)
--- a/arch/mips/include/asm/paccess.h
+++ b/arch/mips/include/asm/paccess.h
@@ -43,7 +43,7 @@ struct __large_pstruct { unsigned long buf[100]; };
        case 1: __get_dbe_asm("lb"); break;                             \
        case 2: __get_dbe_asm("lh"); break;                             \
        case 4: __get_dbe_asm("lw"); break;                             \
        case 1: __get_dbe_asm("lb"); break;                             \
        case 2: __get_dbe_asm("lh"); break;                             \
        case 4: __get_dbe_asm("lw"); break;                             \

-       case 8:  __get_dbe_asm("ld"); break;                            \
+       case 8:  __get_dbe_asm("ld"); break;                            \

        default: __get_dbe_unknown(); break;                            \
        }                                                               \
        x = (__typeof__(*(ptr))) __gu_val;                              \
        default: __get_dbe_unknown(); break;                            \
        }                                                               \
        x = (__typeof__(*(ptr))) __gu_val;                              \

diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index dbaec94046dab06348eb688887b73e2513e3b666..99fc547af9d3517257c8cc46f1deffcf3b07cff8 100644 (file)
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -31,7 +31,7 @@
 #define PAGE_SHIFT     16
 #endif
 #define PAGE_SIZE      (_AC(1,UL) << PAGE_SHIFT)
 #define PAGE_SHIFT     16
 #endif
 #define PAGE_SIZE      (_AC(1,UL) << PAGE_SHIFT)

-#define PAGE_MASK       (~(PAGE_SIZE - 1))
+#define PAGE_MASK      (~(PAGE_SIZE - 1))

 
 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
 #define HPAGE_SHIFT    (PAGE_SHIFT + PAGE_SHIFT - 3)
 
 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
 #define HPAGE_SHIFT    (PAGE_SHIFT + PAGE_SHIFT - 3)


@@ -95,11 +95,11 @@ extern void copy_user_highpage(struct page *to, struct page *from,
 #ifdef CONFIG_64BIT_PHYS_ADDR
   #ifdef CONFIG_CPU_MIPS32
     typedef struct { unsigned long pte_low, pte_high; } pte_t;
 #ifdef CONFIG_64BIT_PHYS_ADDR
   #ifdef CONFIG_CPU_MIPS32
     typedef struct { unsigned long pte_low, pte_high; } pte_t;

-    #define pte_val(x)    ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
-    #define __pte(x)      ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; })
+    #define pte_val(x)   ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
+    #define __pte(x)     ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; })

   #else
      typedef struct { unsigned long long pte; } pte_t;
   #else
      typedef struct { unsigned long long pte; } pte_t;

-     #define pte_val(x)        ((x).pte)
+     #define pte_val(x) ((x).pte)

      #define __pte(x)  ((pte_t) { (x) } )
   #endif
 #else
      #define __pte(x)  ((pte_t) { (x) } )
   #endif
 #else


@@ -191,8 +191,8 @@ typedef struct { unsigned long pgprot; } pgprot_t;
        unsigned long __pfn = (pfn);                                    \
        int __n = pfn_to_nid(__pfn);                                    \
        ((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn +         \
        unsigned long __pfn = (pfn);                                    \
        int __n = pfn_to_nid(__pfn);                                    \
        ((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn +         \

-                              NODE_DATA(__n)->node_spanned_pages)      \
-                   : 0);                                               \
+                              NODE_DATA(__n)->node_spanned_pages)      \
+                   : 0);                                               \

 })
 
 #endif
 })
 
 #endif


@@ -206,7 +206,7 @@ extern int __virt_addr_valid(const volatile void *kaddr);
 #define VM_DATA_DEFAULT_FLAGS  (VM_READ | VM_WRITE | VM_EXEC | \
                                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
 
 #define VM_DATA_DEFAULT_FLAGS  (VM_READ | VM_WRITE | VM_EXEC | \
                                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
 

-#define UNCAC_ADDR(addr)       ((addr) - PAGE_OFFSET + UNCAC_BASE +    \
+#define UNCAC_ADDR(addr)       ((addr) - PAGE_OFFSET + UNCAC_BASE +    \

                                                                PHYS_OFFSET)
 #define CAC_ADDR(addr)         ((addr) - UNCAC_BASE + PAGE_OFFSET -    \
                                                                PHYS_OFFSET)
                                                                PHYS_OFFSET)
 #define CAC_ADDR(addr)         ((addr) - UNCAC_BASE + PAGE_OFFSET -    \
                                                                PHYS_OFFSET)

diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h
index d69ea743272bfc7cac4e559b1f93b4dc6caa5ad5..e224876cc3444495193f7717d39843142420f37a 100644 (file)
--- a/arch/mips/include/asm/pci.h
+++ b/arch/mips/include/asm/pci.h
@@ -12,7 +12,7 @@
 
 /*
  * This file essentially defines the interface between board
 
 /*
  * This file essentially defines the interface between board

- * specific PCI code and MIPS common PCI code.  Should potentially put
+ * specific PCI code and MIPS common PCI code. Should potentially put

  * into include/asm/pci.h file.
  */
 
  * into include/asm/pci.h file.
  */
 


@@ -20,7 +20,7 @@
 #include <linux/of.h>
 
 /*
 #include <linux/of.h>
 
 /*

- * Each pci channel is a top-level PCI bus seem by CPU.  A machine  with
+ * Each pci channel is a top-level PCI bus seem by CPU.         A machine  with

  * multiple PCI channels may have multiple PCI host controllers or a
  * single controller supporting multiple channels.
  */
  * multiple PCI channels may have multiple PCI host controllers or a
  * single controller supporting multiple channels.
  */


@@ -99,7 +99,7 @@ extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
 struct pci_dev;
 
 /*
 struct pci_dev;
 
 /*

- * The PCI address space does equal the physical memory address space.  The
+ * The PCI address space does equal the physical memory address space. The

  * networking and block device layers use this boolean for bounce buffer
  * decisions.  This is set if any hose does not have an IOMMU.
  */
  * networking and block device layers use this boolean for bounce buffer
  * decisions.  This is set if any hose does not have an IOMMU.
  */

diff --git a/arch/mips/include/asm/pci/bridge.h b/arch/mips/include/asm/pci/bridge.h
index be44fb0266daa12eda72132b89207d47fda4eb68..af2c8a351ca70ae0ca14bc43d277ab6cea154f43 100644 (file)
--- a/arch/mips/include/asm/pci/bridge.h
+++ b/arch/mips/include/asm/pci/bridge.h
@@ -85,7 +85,7 @@ typedef volatile struct bridge_s {
 #define b_wid_llp                      b_widget.w_llp_cfg
 #define b_wid_tflush                   b_widget.w_tflush
 
 #define b_wid_llp                      b_widget.w_llp_cfg
 #define b_wid_tflush                   b_widget.w_tflush
 

-       /* bridge-specific widget configuration 0x000058-0x00007F */
+       /* bridge-specific widget configuration 0x000058-0x00007F */

        bridgereg_t         _pad_000058;
        bridgereg_t         b_wid_aux_err;              /* 0x00005C */
        bridgereg_t         _pad_000060;
        bridgereg_t         _pad_000058;
        bridgereg_t         b_wid_aux_err;              /* 0x00005C */
        bridgereg_t         _pad_000060;


@@ -167,8 +167,8 @@ typedef volatile struct bridge_s {
                bridgereg_t     __pad;                  /* 0x0002{80,,,88} */
                bridgereg_t     reg;                    /* 0x0002{84,,,8C} */
        } b_rrb_map[2];                                 /* 0x000280 */
                bridgereg_t     __pad;                  /* 0x0002{80,,,88} */
                bridgereg_t     reg;                    /* 0x0002{84,,,8C} */
        } b_rrb_map[2];                                 /* 0x000280 */

-#define        b_even_resp     b_rrb_map[0].reg                /* 0x000284 */
-#define        b_odd_resp      b_rrb_map[1].reg                /* 0x00028C */
+#define b_even_resp    b_rrb_map[0].reg                /* 0x000284 */
+#define b_odd_resp     b_rrb_map[1].reg                /* 0x00028C */

 
        bridgereg_t     _pad_000290;
        bridgereg_t     b_resp_status;                  /* 0x000294 */
 
        bridgereg_t     _pad_000290;
        bridgereg_t     b_resp_status;                  /* 0x000294 */


@@ -233,7 +233,7 @@ typedef volatile struct bridge_s {
        u8      _pad_030007[0x04fff8];                  /* 0x030008-0x07FFFF */
 
        /* External Address Translation Entry RAM 0x080000-0x0FFFFF */
        u8      _pad_030007[0x04fff8];                  /* 0x030008-0x07FFFF */
 
        /* External Address Translation Entry RAM 0x080000-0x0FFFFF */

-       bridge_ate_t    b_ext_ate_ram[0x10000];
+       bridge_ate_t    b_ext_ate_ram[0x10000];

 
        /* Reserved 0x100000-0x1FFFFF */
        char    _pad_100000[0x200000-0x100000];
 
        /* Reserved 0x100000-0x1FFFFF */
        char    _pad_100000[0x200000-0x100000];


@@ -400,7 +400,7 @@ typedef struct bridge_err_cmdword_s {
 #define BRIDGE_REV_A                   0x1
 #define BRIDGE_REV_B                   0x2
 #define BRIDGE_REV_C                   0x3
 #define BRIDGE_REV_A                   0x1
 #define BRIDGE_REV_B                   0x2
 #define BRIDGE_REV_C                   0x3

-#define        BRIDGE_REV_D                    0x4
+#define BRIDGE_REV_D                   0x4

 
 /* Bridge widget status register bits definition */
 
 
 /* Bridge widget status register bits definition */
 


@@ -691,21 +691,21 @@ typedef struct bridge_err_cmdword_s {
 #define BRIDGE_CREDIT  3
 
 /* RRB assignment register */
 #define BRIDGE_CREDIT  3
 
 /* RRB assignment register */

-#define        BRIDGE_RRB_EN   0x8     /* after shifting down */
-#define        BRIDGE_RRB_DEV  0x7     /* after shifting down */
-#define        BRIDGE_RRB_VDEV 0x4     /* after shifting down */
-#define        BRIDGE_RRB_PDEV 0x3     /* after shifting down */
+#define BRIDGE_RRB_EN  0x8     /* after shifting down */
+#define BRIDGE_RRB_DEV 0x7     /* after shifting down */
+#define BRIDGE_RRB_VDEV 0x4    /* after shifting down */
+#define BRIDGE_RRB_PDEV 0x3    /* after shifting down */

 
 /* RRB status register */
 
 /* RRB status register */

-#define        BRIDGE_RRB_VALID(r)     (0x00010000<<(r))
-#define        BRIDGE_RRB_INUSE(r)     (0x00000001<<(r))
+#define BRIDGE_RRB_VALID(r)    (0x00010000<<(r))
+#define BRIDGE_RRB_INUSE(r)    (0x00000001<<(r))

 
 /* RRB clear register */
 
 /* RRB clear register */

-#define        BRIDGE_RRB_CLEAR(r)     (0x00000001<<(r))
+#define BRIDGE_RRB_CLEAR(r)    (0x00000001<<(r))

 
 /* xbox system controller declarations */
 
 /* xbox system controller declarations */

-#define XBOX_BRIDGE_WID         8
-#define FLASH_PROM1_BASE        0xE00000 /* To read the xbox sysctlr status */
+#define XBOX_BRIDGE_WID                8
+#define FLASH_PROM1_BASE       0xE00000 /* To read the xbox sysctlr status */

 #define XBOX_RPS_EXISTS                1 << 6   /* RPS bit in status register */
 #define XBOX_RPS_FAIL          1 << 4   /* RPS status bit in register */
 
 #define XBOX_RPS_EXISTS                1 << 6   /* RPS bit in status register */
 #define XBOX_RPS_FAIL          1 << 4   /* RPS status bit in register */
 


@@ -838,7 +838,7 @@ struct bridge_controller {
        bridge_t                *base;
        nasid_t                 nasid;
        unsigned int            widget_id;
        bridge_t                *base;
        nasid_t                 nasid;
        unsigned int            widget_id;

-       unsigned int            irq_cpu;
+       unsigned int            irq_cpu;

        u64                     baddr;
        unsigned int            pci_int[8];
 };
        u64                     baddr;
        unsigned int            pci_int[8];
 };

diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h
index 5d56bb2303454e1ff3937d2acd0a99f97bba864f..b4204c179b979b5c984edb0fbf1a3181ff535bdb 100644 (file)
--- a/arch/mips/include/asm/pgtable-32.h
+++ b/arch/mips/include/asm/pgtable-32.h
@@ -47,7 +47,7 @@
 #define USER_PTRS_PER_PGD      (0x80000000UL/PGDIR_SIZE)
 #define FIRST_USER_ADDRESS     0
 
 #define USER_PTRS_PER_PGD      (0x80000000UL/PGDIR_SIZE)
 #define FIRST_USER_ADDRESS     0
 

-#define VMALLOC_START     MAP_BASE
+#define VMALLOC_START    MAP_BASE

 
 #define PKMAP_BASE             (0xfe000000UL)
 
 
 #define PKMAP_BASE             (0xfe000000UL)
 


@@ -136,7 +136,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
 #define pte_offset_kernel(dir, address)                                        \
        ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
 
 #define pte_offset_kernel(dir, address)                                        \
        ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
 

-#define pte_offset_map(dir, address)                                    \
+#define pte_offset_map(dir, address)                                   \

        ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
 #define pte_unmap(pte) ((void)(pte))
 
        ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
 #define pte_unmap(pte) ((void)(pte))
 


@@ -155,7 +155,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
 
 #define pte_to_pgoff(_pte)     ((((_pte).pte >> 1 ) & 0x07) | \
                                 (((_pte).pte >> 2 ) & 0x38) | \
 
 #define pte_to_pgoff(_pte)     ((((_pte).pte >> 1 ) & 0x07) | \
                                 (((_pte).pte >> 2 ) & 0x38) | \

-                                (((_pte).pte >> 10) <<  6 ))
+                                (((_pte).pte >> 10) <<  6 ))

 
 #define pgoff_to_pte(off)      ((pte_t) { (((off) & 0x07) << 1 ) | \
                                           (((off) & 0x38) << 2 ) | \
 
 #define pgoff_to_pte(off)      ((pte_t) { (((off) & 0x07) << 1 ) | \
                                           (((off) & 0x38) << 2 ) | \


@@ -167,14 +167,14 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
 /* Swap entries must have VALID and GLOBAL bits cleared. */
 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 #define __swp_type(x)          (((x).val >> 2) & 0x1f)
 /* Swap entries must have VALID and GLOBAL bits cleared. */
 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 #define __swp_type(x)          (((x).val >> 2) & 0x1f)

-#define __swp_offset(x)         ((x).val >> 7)
+#define __swp_offset(x)                 ((x).val >> 7)

 #define __swp_entry(type,offset)       \
 #define __swp_entry(type,offset)       \

-               ((swp_entry_t)  { ((type) << 2) | ((offset) << 7) })
+               ((swp_entry_t)  { ((type) << 2) | ((offset) << 7) })

 #else
 #define __swp_type(x)          (((x).val >> 8) & 0x1f)
 #else
 #define __swp_type(x)          (((x).val >> 8) & 0x1f)

-#define __swp_offset(x)         ((x).val >> 13)
+#define __swp_offset(x)                 ((x).val >> 13)

 #define __swp_entry(type,offset)       \
 #define __swp_entry(type,offset)       \

-               ((swp_entry_t)  { ((type) << 8) | ((offset) << 13) })
+               ((swp_entry_t)  { ((type) << 8) | ((offset) << 13) })

 #endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
 
 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
 #endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
 
 #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)


@@ -184,7 +184,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
 #define PTE_FILE_MAX_BITS      30
 
 #define pte_to_pgoff(_pte)     ((_pte).pte_high >> 2)
 #define PTE_FILE_MAX_BITS      30
 
 #define pte_to_pgoff(_pte)     ((_pte).pte_high >> 2)

-#define pgoff_to_pte(off)      ((pte_t) { _PAGE_FILE, (off) << 2 })
+#define pgoff_to_pte(off)      ((pte_t) { _PAGE_FILE, (off) << 2 })

 
 #else
 /*
 
 #else
 /*


@@ -194,7 +194,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
 
 #define pte_to_pgoff(_pte)     ((((_pte).pte >> 1) & 0x7) | \
                                 (((_pte).pte >> 2) & 0x8) | \
 
 #define pte_to_pgoff(_pte)     ((((_pte).pte >> 1) & 0x7) | \
                                 (((_pte).pte >> 2) & 0x8) | \

-                                (((_pte).pte >> 8) <<  4))
+                                (((_pte).pte >> 8) <<  4))

 
 #define pgoff_to_pte(off)      ((pte_t) { (((off) & 0x7) << 1) | \
                                           (((off) & 0x8) << 2) | \
 
 #define pgoff_to_pte(off)      ((pte_t) { (((off) & 0x7) << 1) | \
                                           (((off) & 0x8) << 2) | \


@@ -208,7 +208,7 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
 #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
 #define __swp_entry_to_pte(x)  ((pte_t) { 0, (x).val })
 #else
 #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
 #define __swp_entry_to_pte(x)  ((pte_t) { 0, (x).val })
 #else

-#define __pte_to_swp_entry(pte)        ((swp_entry_t) { pte_val(pte) })
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })

 #define __swp_entry_to_pte(x)  ((pte_t) { (x).val })
 #endif
 
 #define __swp_entry_to_pte(x)  ((pte_t) { (x).val })
 #endif
 

diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index 013d5f781263e20cf3d9e93cf14b6552c4386cc8..e1c49a96807d68bbeb61c7bd14af6273665c9a6c 100644 (file)
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -115,7 +115,7 @@
 #define PTRS_PER_PTE   ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
 
 #if PGDIR_SIZE >= TASK_SIZE64
 #define PTRS_PER_PTE   ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
 
 #if PGDIR_SIZE >= TASK_SIZE64

-#define USER_PTRS_PER_PGD       (1)
+#define USER_PTRS_PER_PGD      (1)

 #else
 #define USER_PTRS_PER_PGD      (TASK_SIZE64 / PGDIR_SIZE)
 #endif
 #else
 #define USER_PTRS_PER_PGD      (TASK_SIZE64 / PGDIR_SIZE)
 #endif


@@ -288,7 +288,7 @@ static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
 #define __swp_type(x)          (((x).val >> 32) & 0xff)
 #define __swp_offset(x)                ((x).val >> 40)
 #define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) })
 #define __swp_type(x)          (((x).val >> 32) & 0xff)
 #define __swp_offset(x)                ((x).val >> 40)
 #define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) })

-#define __pte_to_swp_entry(pte)        ((swp_entry_t) { pte_val(pte) })
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })

 #define __swp_entry_to_pte(x)  ((pte_t) { (x).val })
 
 /*
 #define __swp_entry_to_pte(x)  ((pte_t) { (x).val })
 
 /*

diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index 5a7ccc2473f897a005d54f4cdf079728bfe1407a..32aea4852fb0796045efcbc9fbd6414b67a4fe77 100644 (file)
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -21,7 +21,7 @@
  * Similar to the Alpha port, we need to keep track of the ref
  * and mod bits in software.  We have a software "yeah you can read
  * from this page" bit, and a hardware one which actually lets the
  * Similar to the Alpha port, we need to keep track of the ref
  * and mod bits in software.  We have a software "yeah you can read
  * from this page" bit, and a hardware one which actually lets the

- * process read from the page.  On the same token we have a software
+ * process read from the page. On the same token we have a software

  * writable bit and the real hardware one which actually lets the
  * process write to the page, this keeps a mod bit via the hardware
  * dirty bit.
  * writable bit and the real hardware one which actually lets the
  * process write to the page, this keeps a mod bit via the hardware
  * dirty bit.


@@ -41,9 +41,9 @@
 #define _PAGE_GLOBAL           (1 << 0)
 #define _PAGE_VALID_SHIFT      1
 #define _PAGE_VALID            (1 << _PAGE_VALID_SHIFT)
 #define _PAGE_GLOBAL           (1 << 0)
 #define _PAGE_VALID_SHIFT      1
 #define _PAGE_VALID            (1 << _PAGE_VALID_SHIFT)

-#define _PAGE_SILENT_READ      (1 << 1)  /* synonym                 */
+#define _PAGE_SILENT_READ      (1 << 1)  /* synonym                 */

 #define _PAGE_DIRTY_SHIFT      2
 #define _PAGE_DIRTY_SHIFT      2

-#define _PAGE_DIRTY            (1 << _PAGE_DIRTY_SHIFT)  /* The MIPS dirty bit      */
+#define _PAGE_DIRTY            (1 << _PAGE_DIRTY_SHIFT)  /* The MIPS dirty bit      */

 #define _PAGE_SILENT_WRITE     (1 << 2)
 #define _CACHE_SHIFT           3
 #define _CACHE_MASK            (7 << 3)
 #define _PAGE_SILENT_WRITE     (1 << 2)
 #define _CACHE_SHIFT           3
 #define _CACHE_MASK            (7 << 3)


@@ -134,7 +134,7 @@
 #define _PAGE_HUGE             (1 << _PAGE_HUGE_SHIFT)
 #else
 #define _PAGE_HUGE_SHIFT       (_PAGE_MODIFIED_SHIFT)
 #define _PAGE_HUGE             (1 << _PAGE_HUGE_SHIFT)
 #else
 #define _PAGE_HUGE_SHIFT       (_PAGE_MODIFIED_SHIFT)

-#define _PAGE_HUGE             ({BUG(); 1; })  /* Dummy value */
+#define _PAGE_HUGE             ({BUG(); 1; })  /* Dummy value */

 #endif
 
 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
 #endif
 
 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT


@@ -143,7 +143,7 @@
 #define _PAGE_SPLITTING                (1 << _PAGE_SPLITTING_SHIFT)
 #else
 #define _PAGE_SPLITTING_SHIFT  (_PAGE_HUGE_SHIFT)
 #define _PAGE_SPLITTING                (1 << _PAGE_SPLITTING_SHIFT)
 #else
 #define _PAGE_SPLITTING_SHIFT  (_PAGE_HUGE_SHIFT)

-#define _PAGE_SPLITTING                ({BUG(); 1; })  /* Dummy value */
+#define _PAGE_SPLITTING                ({BUG(); 1; })  /* Dummy value */

 #endif
 
 /* Page cannot be executed */
 #endif
 
 /* Page cannot be executed */


@@ -159,10 +159,10 @@
 
 #define _PAGE_VALID_SHIFT      (_PAGE_GLOBAL_SHIFT + 1)
 #define _PAGE_VALID            (1 << _PAGE_VALID_SHIFT)
 
 #define _PAGE_VALID_SHIFT      (_PAGE_GLOBAL_SHIFT + 1)
 #define _PAGE_VALID            (1 << _PAGE_VALID_SHIFT)

-/* synonym                 */
+/* synonym                */

 #define _PAGE_SILENT_READ      (_PAGE_VALID)
 
 #define _PAGE_SILENT_READ      (_PAGE_VALID)
 

-/* The MIPS dirty bit      */
+/* The MIPS dirty bit     */

 #define _PAGE_DIRTY_SHIFT      (_PAGE_VALID_SHIFT + 1)
 #define _PAGE_DIRTY            (1 << _PAGE_DIRTY_SHIFT)
 #define _PAGE_SILENT_WRITE     (_PAGE_DIRTY)
 #define _PAGE_DIRTY_SHIFT      (_PAGE_VALID_SHIFT + 1)
 #define _PAGE_DIRTY            (1 << _PAGE_DIRTY_SHIFT)
 #define _PAGE_SILENT_WRITE     (_PAGE_DIRTY)


@@ -175,7 +175,7 @@
 #endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */
 
 #ifndef _PFN_SHIFT
 #endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */
 
 #ifndef _PFN_SHIFT

-#define _PFN_SHIFT                  PAGE_SHIFT
+#define _PFN_SHIFT                 PAGE_SHIFT

 #endif
 #define _PFN_MASK              (~((1 << (_PFN_SHIFT)) - 1))
 
 #endif
 #define _PFN_MASK              (~((1 << (_PFN_SHIFT)) - 1))
 


@@ -230,28 +230,28 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 /* No penalty for being coherent on the SB1, so just
    use it for "noncoherent" spaces, too.  Shouldn't hurt. */
 
 /* No penalty for being coherent on the SB1, so just
    use it for "noncoherent" spaces, too.  Shouldn't hurt. */
 

-#define _CACHE_UNCACHED             (2<<_CACHE_SHIFT)
-#define _CACHE_CACHABLE_COW         (5<<_CACHE_SHIFT)
+#define _CACHE_UNCACHED                    (2<<_CACHE_SHIFT)
+#define _CACHE_CACHABLE_COW        (5<<_CACHE_SHIFT)

 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
 
 #else
 
 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
 
 #else
 

-#define _CACHE_CACHABLE_NO_WA      (0<<_CACHE_SHIFT)  /* R4600 only      */
-#define _CACHE_CACHABLE_WA         (1<<_CACHE_SHIFT)  /* R4600 only      */
-#define _CACHE_UNCACHED             (2<<_CACHE_SHIFT)  /* R4[0246]00      */
-#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* R4[0246]00      */
-#define _CACHE_CACHABLE_CE          (4<<_CACHE_SHIFT)  /* R4[04]00MC only */
-#define _CACHE_CACHABLE_COW         (5<<_CACHE_SHIFT)  /* R4[04]00MC only */
-#define _CACHE_CACHABLE_COHERENT    (5<<_CACHE_SHIFT)  /* MIPS32R2 CMP    */
-#define _CACHE_CACHABLE_CUW         (6<<_CACHE_SHIFT)  /* R4[04]00MC only */
-#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)  /* R10000 only     */
+#define _CACHE_CACHABLE_NO_WA      (0<<_CACHE_SHIFT)  /* R4600 only      */
+#define _CACHE_CACHABLE_WA         (1<<_CACHE_SHIFT)  /* R4600 only      */
+#define _CACHE_UNCACHED                    (2<<_CACHE_SHIFT)  /* R4[0246]00      */
+#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* R4[0246]00     */
+#define _CACHE_CACHABLE_CE         (4<<_CACHE_SHIFT)  /* R4[04]00MC only */
+#define _CACHE_CACHABLE_COW        (5<<_CACHE_SHIFT)  /* R4[04]00MC only */
+#define _CACHE_CACHABLE_COHERENT    (5<<_CACHE_SHIFT)  /* MIPS32R2 CMP   */
+#define _CACHE_CACHABLE_CUW        (6<<_CACHE_SHIFT)  /* R4[04]00MC only */
+#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)  /* R10000 only    */

 
 #endif
 
 #define __READABLE     (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ))
 #define __WRITEABLE    (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
 
 
 #endif
 
 #define __READABLE     (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ))
 #define __WRITEABLE    (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
 

-#define _PAGE_CHG_MASK  (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
+#define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)

 
 #endif /* _ASM_PGTABLE_BITS_H */
 
 #endif /* _ASM_PGTABLE_BITS_H */

diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index ec50d52cfb747a961a161fc98ecfb26f45f6925c..fdc62fb5630da68bb746ed3dac53b45eb5bddc37 100644 (file)
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -112,7 +112,7 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
                 * it better already be global)
                 */
                if (pte_none(*buddy)) {
                 * it better already be global)
                 */
                if (pte_none(*buddy)) {

-                       buddy->pte_low  |= _PAGE_GLOBAL;
+                       buddy->pte_low  |= _PAGE_GLOBAL;

                        buddy->pte_high |= _PAGE_GLOBAL;
                }
        }
                        buddy->pte_high |= _PAGE_GLOBAL;
                }
        }


@@ -319,7 +319,7 @@ static inline int pte_special(pte_t pte)    { return 0; }
 static inline pte_t pte_mkspecial(pte_t pte)   { return pte; }
 
 /*
 static inline pte_t pte_mkspecial(pte_t pte)   { return pte; }
 
 /*

- * Macro to make mark a page protection value as "uncacheable".  Note
+ * Macro to make mark a page protection value as "uncacheable".         Note

  * that "protection" is really a misnomer here as the protection value
  * contains the memory attribute bits, dirty bits, and various other
  * bits as well.
  * that "protection" is really a misnomer here as the protection value
  * contains the memory attribute bits, dirty bits, and various other
  * bits as well.

diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_cic_int.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_cic_int.h
index c84bcf9570b10e31f95574d1a5942b49b97863a1..ac863e2deb62e3eeac66d04adeb9ceb292b5707a 100644 (file)
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_cic_int.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_cic_int.h
@@ -43,14 +43,14 @@
  * IRQs directly forwarded to the CPU
  */
 #define MSP_MIPS_INTBASE       0
  * IRQs directly forwarded to the CPU
  */
 #define MSP_MIPS_INTBASE       0

-#define MSP_INT_SW0            0       /* IRQ for swint0,       C_SW0  */
-#define MSP_INT_SW1            1       /* IRQ for swint1,       C_SW1  */
-#define MSP_INT_MAC0           2       /* IRQ for MAC 0,        C_IRQ0 */
-#define MSP_INT_MAC1           3       /* IRQ for MAC 1,        C_IRQ1 */
-#define MSP_INT_USB            4       /* IRQ for USB,          C_IRQ2 */
-#define MSP_INT_SAR            5       /* IRQ for ADSL2+ SAR,   C_IRQ3 */
-#define MSP_INT_CIC            6       /* IRQ for CIC block,    C_IRQ4 */
-#define MSP_INT_SEC            7       /* IRQ for Sec engine,   C_IRQ5 */
+#define MSP_INT_SW0            0       /* IRQ for swint0,       C_SW0  */
+#define MSP_INT_SW1            1       /* IRQ for swint1,       C_SW1  */
+#define MSP_INT_MAC0           2       /* IRQ for MAC 0,        C_IRQ0 */
+#define MSP_INT_MAC1           3       /* IRQ for MAC 1,        C_IRQ1 */
+#define MSP_INT_USB            4       /* IRQ for USB,          C_IRQ2 */
+#define MSP_INT_SAR            5       /* IRQ for ADSL2+ SAR,   C_IRQ3 */
+#define MSP_INT_CIC            6       /* IRQ for CIC block,    C_IRQ4 */
+#define MSP_INT_SEC            7       /* IRQ for Sec engine,   C_IRQ5 */

 
 /*
  * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
 
 /*
  * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)


@@ -59,93 +59,93 @@
  */
 #define MSP_CIC_INTBASE                (MSP_MIPS_INTBASE + 8)
 #define MSP_INT_EXT0           (MSP_CIC_INTBASE + 0)
  */
 #define MSP_CIC_INTBASE                (MSP_MIPS_INTBASE + 8)
 #define MSP_INT_EXT0           (MSP_CIC_INTBASE + 0)

-                                       /* External interrupt 0         */
+                                       /* External interrupt 0         */

 #define MSP_INT_EXT1           (MSP_CIC_INTBASE + 1)
 #define MSP_INT_EXT1           (MSP_CIC_INTBASE + 1)

-                                       /* External interrupt 1         */
+                                       /* External interrupt 1         */

 #define MSP_INT_EXT2           (MSP_CIC_INTBASE + 2)
 #define MSP_INT_EXT2           (MSP_CIC_INTBASE + 2)

-                                       /* External interrupt 2         */
+                                       /* External interrupt 2         */

 #define MSP_INT_EXT3           (MSP_CIC_INTBASE + 3)
 #define MSP_INT_EXT3           (MSP_CIC_INTBASE + 3)

-                                       /* External interrupt 3         */
+                                       /* External interrupt 3         */

 #define MSP_INT_CPUIF          (MSP_CIC_INTBASE + 4)
 #define MSP_INT_CPUIF          (MSP_CIC_INTBASE + 4)

-                                       /* CPU interface interrupt      */
+                                       /* CPU interface interrupt      */

 #define MSP_INT_EXT4           (MSP_CIC_INTBASE + 5)
 #define MSP_INT_EXT4           (MSP_CIC_INTBASE + 5)

-                                       /* External interrupt 4         */
+                                       /* External interrupt 4         */

 #define MSP_INT_CIC_USB                (MSP_CIC_INTBASE + 6)
 #define MSP_INT_CIC_USB                (MSP_CIC_INTBASE + 6)

-                                       /* Cascaded IRQ for USB         */
+                                       /* Cascaded IRQ for USB         */

 #define MSP_INT_MBOX           (MSP_CIC_INTBASE + 7)
 #define MSP_INT_MBOX           (MSP_CIC_INTBASE + 7)

-                                       /* Sec engine mailbox IRQ       */
+                                       /* Sec engine mailbox IRQ       */

 #define MSP_INT_EXT5           (MSP_CIC_INTBASE + 8)
 #define MSP_INT_EXT5           (MSP_CIC_INTBASE + 8)

-                                       /* External interrupt 5         */
+                                       /* External interrupt 5         */

 #define MSP_INT_TDM            (MSP_CIC_INTBASE + 9)
 #define MSP_INT_TDM            (MSP_CIC_INTBASE + 9)

-                                       /* TDM interrupt                */
+                                       /* TDM interrupt                */

 #define MSP_INT_CIC_MAC0       (MSP_CIC_INTBASE + 10)
 #define MSP_INT_CIC_MAC0       (MSP_CIC_INTBASE + 10)

-                                       /* Cascaded IRQ for MAC 0       */
+                                       /* Cascaded IRQ for MAC 0       */

 #define MSP_INT_CIC_MAC1       (MSP_CIC_INTBASE + 11)
 #define MSP_INT_CIC_MAC1       (MSP_CIC_INTBASE + 11)

-                                       /* Cascaded IRQ for MAC 1       */
+                                       /* Cascaded IRQ for MAC 1       */

 #define MSP_INT_CIC_SEC                (MSP_CIC_INTBASE + 12)
 #define MSP_INT_CIC_SEC                (MSP_CIC_INTBASE + 12)

-                                       /* Cascaded IRQ for sec engine  */
-#define        MSP_INT_PER             (MSP_CIC_INTBASE + 13)
-                                       /* Peripheral interrupt         */
-#define        MSP_INT_TIMER0          (MSP_CIC_INTBASE + 14)
-                                       /* SLP timer 0                  */
-#define        MSP_INT_TIMER1          (MSP_CIC_INTBASE + 15)
-                                       /* SLP timer 1                  */
-#define        MSP_INT_TIMER2          (MSP_CIC_INTBASE + 16)
-                                       /* SLP timer 2                  */
-#define        MSP_INT_VPE0_TIMER      (MSP_CIC_INTBASE + 17)
-                                       /* VPE0 MIPS timer              */
+                                       /* Cascaded IRQ for sec engine  */
+#define MSP_INT_PER            (MSP_CIC_INTBASE + 13)
+                                       /* Peripheral interrupt         */
+#define MSP_INT_TIMER0         (MSP_CIC_INTBASE + 14)
+                                       /* SLP timer 0                  */
+#define MSP_INT_TIMER1         (MSP_CIC_INTBASE + 15)
+                                       /* SLP timer 1                  */
+#define MSP_INT_TIMER2         (MSP_CIC_INTBASE + 16)
+                                       /* SLP timer 2                  */
+#define MSP_INT_VPE0_TIMER     (MSP_CIC_INTBASE + 17)
+                                       /* VPE0 MIPS timer              */

 #define MSP_INT_BLKCP          (MSP_CIC_INTBASE + 18)
 #define MSP_INT_BLKCP          (MSP_CIC_INTBASE + 18)

-                                       /* Block Copy                   */
+                                       /* Block Copy                   */

 #define MSP_INT_UART0          (MSP_CIC_INTBASE + 19)
 #define MSP_INT_UART0          (MSP_CIC_INTBASE + 19)

-                                       /* UART 0                       */
+                                       /* UART 0                       */

 #define MSP_INT_PCI            (MSP_CIC_INTBASE + 20)
 #define MSP_INT_PCI            (MSP_CIC_INTBASE + 20)

-                                       /* PCI subsystem                */
+                                       /* PCI subsystem                */

 #define MSP_INT_EXT6           (MSP_CIC_INTBASE + 21)
 #define MSP_INT_EXT6           (MSP_CIC_INTBASE + 21)

-                                       /* External interrupt 5         */
+                                       /* External interrupt 5         */

 #define MSP_INT_PCI_MSI                (MSP_CIC_INTBASE + 22)
 #define MSP_INT_PCI_MSI                (MSP_CIC_INTBASE + 22)

-                                       /* PCI Message Signal           */
+                                       /* PCI Message Signal           */

 #define MSP_INT_CIC_SAR                (MSP_CIC_INTBASE + 23)
 #define MSP_INT_CIC_SAR                (MSP_CIC_INTBASE + 23)

-                                       /* Cascaded ADSL2+ SAR IRQ      */
+                                       /* Cascaded ADSL2+ SAR IRQ      */

 #define MSP_INT_DSL            (MSP_CIC_INTBASE + 24)
 #define MSP_INT_DSL            (MSP_CIC_INTBASE + 24)

-                                       /* ADSL2+ IRQ                   */
+                                       /* ADSL2+ IRQ                   */

 #define MSP_INT_CIC_ERR                (MSP_CIC_INTBASE + 25)
 #define MSP_INT_CIC_ERR                (MSP_CIC_INTBASE + 25)

-                                       /* SLP error condition          */
+                                       /* SLP error condition          */

 #define MSP_INT_VPE1_TIMER     (MSP_CIC_INTBASE + 26)
 #define MSP_INT_VPE1_TIMER     (MSP_CIC_INTBASE + 26)

-                                       /* VPE1 MIPS timer              */
+                                       /* VPE1 MIPS timer              */

 #define MSP_INT_VPE0_PC                (MSP_CIC_INTBASE + 27)
 #define MSP_INT_VPE0_PC                (MSP_CIC_INTBASE + 27)

-                                       /* VPE0 Performance counter     */
+                                       /* VPE0 Performance counter     */

 #define MSP_INT_VPE1_PC                (MSP_CIC_INTBASE + 28)
 #define MSP_INT_VPE1_PC                (MSP_CIC_INTBASE + 28)

-                                       /* VPE1 Performance counter     */
+                                       /* VPE1 Performance counter     */

 #define MSP_INT_EXT7           (MSP_CIC_INTBASE + 29)
 #define MSP_INT_EXT7           (MSP_CIC_INTBASE + 29)

-                                       /* External interrupt 5         */
+                                       /* External interrupt 5         */

 #define MSP_INT_VPE0_SW                (MSP_CIC_INTBASE + 30)
 #define MSP_INT_VPE0_SW                (MSP_CIC_INTBASE + 30)

-                                       /* VPE0 Software interrupt      */
+                                       /* VPE0 Software interrupt      */

 #define MSP_INT_VPE1_SW                (MSP_CIC_INTBASE + 31)
 #define MSP_INT_VPE1_SW                (MSP_CIC_INTBASE + 31)

-                                       /* VPE0 Software interrupt      */
+                                       /* VPE0 Software interrupt      */

 
 /*
  * IRQs cascaded on CIC PER interrupt (MSP_INT_PER)
  */
 #define MSP_PER_INTBASE                (MSP_CIC_INTBASE + 32)
 
 /*
  * IRQs cascaded on CIC PER interrupt (MSP_INT_PER)
  */
 #define MSP_PER_INTBASE                (MSP_CIC_INTBASE + 32)

-/* Reserved                                       0-1                  */
+/* Reserved                                       0-1                  */

 #define MSP_INT_UART1          (MSP_PER_INTBASE + 2)
 #define MSP_INT_UART1          (MSP_PER_INTBASE + 2)

-                                       /* UART 1                       */
-/* Reserved                                       3-5                  */
+                                       /* UART 1                       */
+/* Reserved                                       3-5                  */

 #define MSP_INT_2WIRE          (MSP_PER_INTBASE + 6)
 #define MSP_INT_2WIRE          (MSP_PER_INTBASE + 6)

-                                       /* 2-wire                       */
+                                       /* 2-wire                       */

 #define MSP_INT_TM0            (MSP_PER_INTBASE + 7)
                                        /* Peripheral timer block out 0 */
 #define MSP_INT_TM1            (MSP_PER_INTBASE + 8)
                                        /* Peripheral timer block out 1 */
 #define MSP_INT_TM0            (MSP_PER_INTBASE + 7)
                                        /* Peripheral timer block out 0 */
 #define MSP_INT_TM1            (MSP_PER_INTBASE + 8)
                                        /* Peripheral timer block out 1 */

-/* Reserved                                       9                    */
+/* Reserved                                       9                    */

 #define MSP_INT_SPRX           (MSP_PER_INTBASE + 10)
 #define MSP_INT_SPRX           (MSP_PER_INTBASE + 10)

-                                       /* SPI RX complete              */
+                                       /* SPI RX complete              */

 #define MSP_INT_SPTX           (MSP_PER_INTBASE + 11)
 #define MSP_INT_SPTX           (MSP_PER_INTBASE + 11)

-                                       /* SPI TX complete              */
+                                       /* SPI TX complete              */

 #define MSP_INT_GPIO           (MSP_PER_INTBASE + 12)
 #define MSP_INT_GPIO           (MSP_PER_INTBASE + 12)

-                                       /* GPIO                         */
+                                       /* GPIO                         */

 #define MSP_INT_PER_ERR                (MSP_PER_INTBASE + 13)
 #define MSP_INT_PER_ERR                (MSP_PER_INTBASE + 13)

-                                       /* Peripheral error             */
-/* Reserved                                       14-31                */
+                                       /* Peripheral error             */
+/* Reserved                                       14-31                */

 
 #endif /* !_MSP_CIC_INT_H */
 
 #endif /* !_MSP_CIC_INT_H */

diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_gpio_macros.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_gpio_macros.h
index 156f320c69e7c113942c273bdd84d9c446ddcfd2..daacebb047c292a04d65cdad6345a1bbedc715d4 100644 (file)
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_gpio_macros.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_gpio_macros.h
@@ -54,7 +54,7 @@ enum msp_gpio_mode {
        MSP_GPIO_UART_OUTPUT    = 0x9,  /* Only GPIO 2 or 3 */
        MSP_GPIO_PERIF_TIMERA   = 0x9,  /* Only GPIO 0 or 1 */
        MSP_GPIO_PERIF_TIMERB   = 0xa,  /* Only GPIO 0 or 1 */
        MSP_GPIO_UART_OUTPUT    = 0x9,  /* Only GPIO 2 or 3 */
        MSP_GPIO_PERIF_TIMERA   = 0x9,  /* Only GPIO 0 or 1 */
        MSP_GPIO_PERIF_TIMERB   = 0xa,  /* Only GPIO 0 or 1 */

-       MSP_GPIO_UNKNOWN        = 0xb,  /* No such GPIO or mode */
+       MSP_GPIO_UNKNOWN        = 0xb,  /* No such GPIO or mode */

 };
 
 /* -- Static Tables -- */
 };
 
 /* -- Static Tables -- */


@@ -148,7 +148,7 @@ static unsigned int MSP_GPIO_MODE_ALLOWED[] = {
        BASIC_MODE_REG_VALUE(mode, OFFSET_GPIO_NUMBER(gpio))
 #define BASIC_MODE_SHIFT(gpio) \
        BASIC_MODE_REG_SHIFT(OFFSET_GPIO_NUMBER(gpio))
        BASIC_MODE_REG_VALUE(mode, OFFSET_GPIO_NUMBER(gpio))
 #define BASIC_MODE_SHIFT(gpio) \
        BASIC_MODE_REG_SHIFT(OFFSET_GPIO_NUMBER(gpio))

-#define BASIC_MODE_FROM_REG(data, gpio)        \
+#define BASIC_MODE_FROM_REG(data, gpio) \

        BASIC_MODE_REG_FROM_REG(data, OFFSET_GPIO_NUMBER(gpio))
 
 /*
        BASIC_MODE_REG_FROM_REG(data, OFFSET_GPIO_NUMBER(gpio))
 
 /*

diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_int.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_int.h
index 1d9f0547482072ff9726e2e1f4cd9e515da8d8ba..29f8bf79d7a54916da2fc5266982aefcc745a98b 100644 (file)
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_int.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_int.h
@@ -1,7 +1,7 @@
 /*
  * Defines for the MSP interrupt handlers.
  *
 /*
  * Defines for the MSP interrupt handlers.
  *

- * Copyright (C) 2005, PMC-Sierra, Inc.  All rights reserved.
+ * Copyright (C) 2005, PMC-Sierra, Inc.         All rights reserved.

  * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
  *
  * ########################################################################
  * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
  *
  * ########################################################################


@@ -28,7 +28,7 @@
 /*
  * The PMC-Sierra MSP product line has at least two different interrupt
  * controllers, the SLP register based scheme and the CIC interrupt
 /*
  * The PMC-Sierra MSP product line has at least two different interrupt
  * controllers, the SLP register based scheme and the CIC interrupt

- * controller block mechanism.  This file distinguishes between them
+ * controller block mechanism. This file distinguishes between them

  * so that devices see a uniform interface.
  */
 
  * so that devices see a uniform interface.
  */
 

diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h
index 415606903617926d0dd8dff753ef49379c53c5b4..24948cc424618d56c2811853b42b5d3618cc249a 100644 (file)
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_pci.h
@@ -26,7 +26,7 @@
 #ifndef _MSP_PCI_H_
 #define _MSP_PCI_H_
 
 #ifndef _MSP_PCI_H_
 #define _MSP_PCI_H_
 

-#define MSP_HAS_PCI(ID)        (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220))
+#define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220))

 
 /*
  * It is convenient to program the OATRAN register so that
 
 /*
  * It is convenient to program the OATRAN register so that


@@ -96,24 +96,24 @@ enum
     config_status_command, /* 1 */
     config_class_revision, /* 2 */
     config_BIST_header_latency_cache, /* 3 */
     config_status_command, /* 1 */
     config_class_revision, /* 2 */
     config_BIST_header_latency_cache, /* 3 */

-    config_BAR0,           /* 4 */
-    config_BAR1,           /* 5 */
-    config_BAR2,           /* 6 */
-    config_not_used7,      /* 7 */
-    config_not_used8,      /* 8 */
-    config_not_used9,      /* 9 */
-    config_CIS,            /* 10 */
-    config_subsystem,      /* 11 */
-    config_not_used12,     /* 12 */
+    config_BAR0,          /* 4 */
+    config_BAR1,          /* 5 */
+    config_BAR2,          /* 6 */
+    config_not_used7,     /* 7 */
+    config_not_used8,     /* 8 */
+    config_not_used9,     /* 9 */
+    config_CIS,                   /* 10 */
+    config_subsystem,     /* 11 */
+    config_not_used12,    /* 12 */

     config_capabilities,   /* 13 */
     config_capabilities,   /* 13 */

-    config_not_used14,     /* 14 */
+    config_not_used14,    /* 14 */

     config_lat_grant_irq,  /* 15 */
     config_message_control,/* 16 */
     config_message_addr,   /* 17 */
     config_message_data,   /* 18 */
     config_lat_grant_irq,  /* 15 */
     config_message_control,/* 16 */
     config_message_addr,   /* 17 */
     config_message_data,   /* 18 */

-    config_VPD_addr,       /* 19 */
-    config_VPD_data,       /* 20 */
-    config_maxregs         /* 21 - number of registers */
+    config_VPD_addr,      /* 19 */
+    config_VPD_data,      /* 20 */
+    config_maxregs        /* 21 - number of registers */

 };
 
 struct msp_pci_regs
 };
 
 struct msp_pci_regs


@@ -132,15 +132,15 @@ struct msp_pci_regs
     pcireg hop_unused_2C; /* +0x2C */
     pcireg hop_unused_30; /* +0x30 */
     pcireg hop_unused_34; /* +0x34 */
     pcireg hop_unused_2C; /* +0x2C */
     pcireg hop_unused_30; /* +0x30 */
     pcireg hop_unused_34; /* +0x34 */

-    pcireg if_control;    /* +0x38 */
-    pcireg oatran;        /* +0x3C */
-    pcireg reset_ctl;     /* +0x40 */
-    pcireg config_addr;   /* +0x44 */
+    pcireg if_control;   /* +0x38 */
+    pcireg oatran;       /* +0x3C */
+    pcireg reset_ctl;    /* +0x40 */
+    pcireg config_addr;          /* +0x44 */

     pcireg hop_unused_48; /* +0x48 */
     pcireg msg_signaled_int_status; /* +0x4C */
     pcireg msg_signaled_int_mask;   /* +0x50 */
     pcireg hop_unused_48; /* +0x48 */
     pcireg msg_signaled_int_status; /* +0x4C */
     pcireg msg_signaled_int_mask;   /* +0x50 */

-    pcireg if_status;     /* +0x54 */
-    pcireg if_mask;       /* +0x58 */
+    pcireg if_status;    /* +0x54 */
+    pcireg if_mask;      /* +0x58 */

     pcireg hop_unused_5C; /* +0x5C */
     pcireg hop_unused_60; /* +0x60 */
     pcireg hop_unused_64; /* +0x64 */
     pcireg hop_unused_5C; /* +0x5C */
     pcireg hop_unused_60; /* +0x60 */
     pcireg hop_unused_64; /* +0x64 */


@@ -190,9 +190,9 @@ struct msp_pci_regs
 #define BPCI_IFSTATUS_PEI  (1<<30) /* Parity error as initiator */
 #define BPCI_IFSTATUS_PET  (1<<31) /* Parity error as target */
 
 #define BPCI_IFSTATUS_PEI  (1<<30) /* Parity error as initiator */
 #define BPCI_IFSTATUS_PET  (1<<31) /* Parity error as target */
 

-#define BPCI_RESETCTL_PR (1<<0)    /* True if reset asserted */
-#define BPCI_RESETCTL_RT (1<<4)    /* Release time */
-#define BPCI_RESETCTL_CT (1<<8)    /* Config time */
+#define BPCI_RESETCTL_PR (1<<0)           /* True if reset asserted */
+#define BPCI_RESETCTL_RT (1<<4)           /* Release time */
+#define BPCI_RESETCTL_CT (1<<8)           /* Config time */

 #define BPCI_RESETCTL_PE (1<<12)   /* PCI enabled */
 #define BPCI_RESETCTL_HM (1<<13)   /* PCI host mode */
 #define BPCI_RESETCTL_RI (1<<14)   /* PCI reset in */
 #define BPCI_RESETCTL_PE (1<<12)   /* PCI enabled */
 #define BPCI_RESETCTL_HM (1<<13)   /* PCI host mode */
 #define BPCI_RESETCTL_RI (1<<14)   /* PCI reset in */

diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
index 786d82daf8d60c25eaa154e2070a32340ce44a23..4d3052ab89a2d1a25e9fc84e621c7bc4cc58bba4 100644 (file)
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_prom.h
@@ -40,7 +40,7 @@
                (((revision >= 0xb0) && (revision < 0xd0)))
 #define FPGA_IS_5000(revision) \
                ((revision >= 0x80) && (revision <= 0x90))
                (((revision >= 0xb0) && (revision < 0xd0)))
 #define FPGA_IS_5000(revision) \
                ((revision >= 0x80) && (revision <= 0x90))

-#define        FPGA_IS_ZEUS(revision)          ((revision < 0x7f))
+#define FPGA_IS_ZEUS(revision)         ((revision < 0x7f))

 #define FPGA_IS_DUET(revision) \
                (((revision >= 0xa0) && (revision < 0xb0)))
 #define FPGA_IS_MSP4200(revision)      ((revision >= 0xd0))
 #define FPGA_IS_DUET(revision) \
                (((revision >= 0xa0) && (revision < 0xb0)))
 #define FPGA_IS_MSP4200(revision)      ((revision >= 0xd0))


@@ -48,7 +48,7 @@
 
 #define MACHINE_TYPE_POLO              "POLO"
 #define MACHINE_TYPE_DUET              "DUET"
 
 #define MACHINE_TYPE_POLO              "POLO"
 #define MACHINE_TYPE_DUET              "DUET"

-#define        MACHINE_TYPE_ZEUS               "ZEUS"
+#define MACHINE_TYPE_ZEUS              "ZEUS"

 #define MACHINE_TYPE_MSP2000REVB       "MSP2000REVB"
 #define MACHINE_TYPE_MSP5000           "MSP5000"
 #define MACHINE_TYPE_MSP4200           "MSP4200"
 #define MACHINE_TYPE_MSP2000REVB       "MSP2000REVB"
 #define MACHINE_TYPE_MSP5000           "MSP5000"
 #define MACHINE_TYPE_MSP4200           "MSP4200"


@@ -58,7 +58,7 @@
 
 #define MACHINE_TYPE_POLO_FPGA         "POLO-FPGA"
 #define MACHINE_TYPE_DUET_FPGA         "DUET-FPGA"
 
 #define MACHINE_TYPE_POLO_FPGA         "POLO-FPGA"
 #define MACHINE_TYPE_DUET_FPGA         "DUET-FPGA"

-#define        MACHINE_TYPE_ZEUS_FPGA          "ZEUS_FPGA"
+#define MACHINE_TYPE_ZEUS_FPGA         "ZEUS_FPGA"

 #define MACHINE_TYPE_MSP2000REVB_FPGA  "MSP2000REVB-FPGA"
 #define MACHINE_TYPE_MSP5000_FPGA      "MSP5000-FPGA"
 #define MACHINE_TYPE_MSP4200_FPGA      "MSP4200-FPGA"
 #define MACHINE_TYPE_MSP2000REVB_FPGA  "MSP2000REVB-FPGA"
 #define MACHINE_TYPE_MSP5000_FPGA      "MSP5000-FPGA"
 #define MACHINE_TYPE_MSP4200_FPGA      "MSP4200-FPGA"


@@ -95,7 +95,7 @@
 #define ENET_MII               'M'
 #define ENET_RMII              'R'
 
 #define ENET_MII               'M'
 #define ENET_RMII              'R'
 

-#define        ENETTXD_FALLING         'F'
+#define ENETTXD_FALLING                'F'

 #define ENETTXD_RISING         'R'
 
 #define PCI_HOST               'H'
 #define ENETTXD_RISING         'R'
 
 #define PCI_HOST               'H'

diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h
index 7d41474e54882af62d9d70b870a02581184ffd71..2dbc7a8cec1a4e62f46fad4e2624e699637dd779 100644 (file)
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regops.h
@@ -233,4 +233,4 @@ static inline u32 blocking_read_reg32(volatile u32 *const addr)
        : "=&r" (tmp), "=m" (*address)                          \
        : "0" (tmp), "m" (*address))
 
        : "=&r" (tmp), "=m" (*address)                          \
        : "0" (tmp), "m" (*address))
 

-#endif  /* __ASM_REGOPS_H__ */
+#endif /* __ASM_REGOPS_H__ */

diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h
index 692c1b658b92b0a7ea8e24c0329d074d9f2da447..da3a8dea228201d23ec9f5234a26fa3483402d6a 100644 (file)
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_regs.h
@@ -37,13 +37,13 @@
 
 /*
  ########################################################################
 
 /*
  ########################################################################

- #  Address space and device base definitions                           #
+ #  Address space and device base definitions                          #

  ########################################################################
  */
 
 /*
  ***************************************************************************
  ########################################################################
  */
 
 /*
  ***************************************************************************

- * System Logic and Peripherals (ELB, UART0, etc) device address space     *
+ * System Logic and Peripherals (ELB, UART0, etc) device address space    *

  ***************************************************************************
  */
 #define MSP_SLP_BASE           0x1c000000
  ***************************************************************************
  */
 #define MSP_SLP_BASE           0x1c000000


@@ -53,69 +53,69 @@
 #define MSP_RST_SIZE           0x0C    /* System reset register space  */
 
 #define MSP_WTIMER_BASE                (MSP_SLP_BASE + 0x04C)
 #define MSP_RST_SIZE           0x0C    /* System reset register space  */
 
 #define MSP_WTIMER_BASE                (MSP_SLP_BASE + 0x04C)

-                                       /* watchdog timer base          */
+                                       /* watchdog timer base          */

 #define MSP_ITIMER_BASE                (MSP_SLP_BASE + 0x054)
 #define MSP_ITIMER_BASE                (MSP_SLP_BASE + 0x054)

-                                       /* internal timer base          */
+                                       /* internal timer base          */

 #define MSP_UART0_BASE         (MSP_SLP_BASE + 0x100)
 #define MSP_UART0_BASE         (MSP_SLP_BASE + 0x100)

-                                       /* UART0 controller base        */
+                                       /* UART0 controller base        */

 #define MSP_BCPY_CTRL_BASE     (MSP_SLP_BASE + 0x120)
 #define MSP_BCPY_CTRL_BASE     (MSP_SLP_BASE + 0x120)

-                                       /* Block Copy controller base   */
+                                       /* Block Copy controller base   */

 #define MSP_BCPY_DESC_BASE     (MSP_SLP_BASE + 0x160)
 #define MSP_BCPY_DESC_BASE     (MSP_SLP_BASE + 0x160)

-                                       /* Block Copy descriptor base   */
+                                       /* Block Copy descriptor base   */

 
 /*
  ***************************************************************************
 
 /*
  ***************************************************************************

- * PCI address space                                                       *
+ * PCI address space                                                      *

  ***************************************************************************
  */
 #define MSP_PCI_BASE           0x19000000
 
 /*
  ***************************************************************************
  ***************************************************************************
  */
 #define MSP_PCI_BASE           0x19000000
 
 /*
  ***************************************************************************

- * MSbus device address space                                              *
+ * MSbus device address space                                             *

  ***************************************************************************
  */
 #define MSP_MSB_BASE           0x18000000
  ***************************************************************************
  */
 #define MSP_MSB_BASE           0x18000000

-                                       /* MSbus address start          */
+                                       /* MSbus address start          */

 #define MSP_PER_BASE           (MSP_MSB_BASE + 0x400000)
 #define MSP_PER_BASE           (MSP_MSB_BASE + 0x400000)

-                                       /* Peripheral device registers  */
+                                       /* Peripheral device registers  */

 #define MSP_MAC0_BASE          (MSP_MSB_BASE + 0x600000)
 #define MSP_MAC0_BASE          (MSP_MSB_BASE + 0x600000)

-                                       /* MAC A device registers       */
+                                       /* MAC A device registers       */

 #define MSP_MAC1_BASE          (MSP_MSB_BASE + 0x700000)
 #define MSP_MAC1_BASE          (MSP_MSB_BASE + 0x700000)

-                                       /* MAC B device registers       */
+                                       /* MAC B device registers       */

 #define MSP_MAC_SIZE           0xE0    /* MAC register space           */
 
 #define MSP_SEC_BASE           (MSP_MSB_BASE + 0x800000)
 #define MSP_MAC_SIZE           0xE0    /* MAC register space           */
 
 #define MSP_SEC_BASE           (MSP_MSB_BASE + 0x800000)

-                                       /* Security Engine registers    */
+                                       /* Security Engine registers    */

 #define MSP_MAC2_BASE          (MSP_MSB_BASE + 0x900000)
 #define MSP_MAC2_BASE          (MSP_MSB_BASE + 0x900000)

-                                       /* MAC C device registers       */
+                                       /* MAC C device registers       */

 #define MSP_ADSL2_BASE         (MSP_MSB_BASE + 0xA80000)
 #define MSP_ADSL2_BASE         (MSP_MSB_BASE + 0xA80000)

-                                       /* ADSL2 device registers       */
+                                       /* ADSL2 device registers       */

 #define MSP_USB0_BASE          (MSP_MSB_BASE + 0xB00000)
 #define MSP_USB0_BASE          (MSP_MSB_BASE + 0xB00000)

-                                       /* USB0 device registers        */
+                                       /* USB0 device registers        */

 #define MSP_USB1_BASE          (MSP_MSB_BASE + 0x300000)
                                        /* USB1 device registers        */
 #define MSP_CPUIF_BASE         (MSP_MSB_BASE + 0xC00000)
 #define MSP_USB1_BASE          (MSP_MSB_BASE + 0x300000)
                                        /* USB1 device registers        */
 #define MSP_CPUIF_BASE         (MSP_MSB_BASE + 0xC00000)

-                                       /* CPU interface registers      */
+                                       /* CPU interface registers      */

 
 /* Devices within the MSbus peripheral block */
 #define MSP_UART1_BASE         (MSP_PER_BASE + 0x030)
 
 /* Devices within the MSbus peripheral block */
 #define MSP_UART1_BASE         (MSP_PER_BASE + 0x030)

-                                       /* UART1 controller base        */
+                                       /* UART1 controller base        */

 #define MSP_SPI_BASE           (MSP_PER_BASE + 0x058)
 #define MSP_SPI_BASE           (MSP_PER_BASE + 0x058)

-                                       /* SPI/MPI control registers    */
+                                       /* SPI/MPI control registers    */

 #define MSP_TWI_BASE           (MSP_PER_BASE + 0x090)
 #define MSP_TWI_BASE           (MSP_PER_BASE + 0x090)

-                                       /* Two-wire control registers   */
+                                       /* Two-wire control registers   */

 #define MSP_PTIMER_BASE                (MSP_PER_BASE + 0x0F0)
 #define MSP_PTIMER_BASE                (MSP_PER_BASE + 0x0F0)

-                                       /* Programmable timer control   */
+                                       /* Programmable timer control   */

 
 /*
  ***************************************************************************
 
 /*
  ***************************************************************************

- * Physical Memory configuration address space                             *
+ * Physical Memory configuration address space                            *

  ***************************************************************************
  */
 #define MSP_MEM_CFG_BASE       0x17f00000
 
  ***************************************************************************
  */
 #define MSP_MEM_CFG_BASE       0x17f00000
 

-#define MSP_MEM_INDIRECT_CTL_10        0x10
+#define MSP_MEM_INDIRECT_CTL_10 0x10

 
 /*
  * Notes:
 
 /*
  * Notes:


@@ -130,10 +130,10 @@
  *  3) These constants are for physical addresses which means that they
  *     work correctly with "ioremap" and friends.  This means that device
  *     drivers will need to remap these addresses using ioremap and perhaps
  *  3) These constants are for physical addresses which means that they
  *     work correctly with "ioremap" and friends.  This means that device
  *     drivers will need to remap these addresses using ioremap and perhaps

- *     the readw/writew macros.  Or they could use the regptr() macro
+ *     the readw/writew macros.         Or they could use the regptr() macro

  *     defined below, but the readw/writew calls are the correct thing.
  *  4) The UARTs have an additional status register offset from the base
  *     defined below, but the readw/writew calls are the correct thing.
  *  4) The UARTs have an additional status register offset from the base

- *     address.  This register isn't used in the standard 8250 driver but
+ *     address.         This register isn't used in the standard 8250 driver but

  *     may be used in other software.  Consult the hardware datasheet for
  *     offset details.
  *  5) For some unknown reason the security engine (MSP_SEC_BASE) registers
  *     may be used in other software.  Consult the hardware datasheet for
  *     offset details.
  *  5) For some unknown reason the security engine (MSP_SEC_BASE) registers


@@ -163,44 +163,44 @@
 
 /*
  ***************************************************************************
 
 /*
  ***************************************************************************

- * System Logic and Peripherals (RESET, ELB, etc) registers                *
+ * System Logic and Peripherals (RESET, ELB, etc) registers               *

  ***************************************************************************
  */
 
 /* System Control register definitions */
  ***************************************************************************
  */
 
 /* System Control register definitions */

-#define        DEV_ID_REG      regptr(MSP_SLP_BASE + 0x00)
-                                       /* Device-ID                 RO */
-#define        FWR_ID_REG      regptr(MSP_SLP_BASE + 0x04)
-                                       /* Firmware-ID Register      RW */
-#define        SYS_ID_REG0     regptr(MSP_SLP_BASE + 0x08)
-                                       /* System-ID Register-0      RW */
-#define        SYS_ID_REG1     regptr(MSP_SLP_BASE + 0x0C)
-                                       /* System-ID Register-1      RW */
+#define DEV_ID_REG     regptr(MSP_SLP_BASE + 0x00)
+                                       /* Device-ID                 RO */
+#define FWR_ID_REG     regptr(MSP_SLP_BASE + 0x04)
+                                       /* Firmware-ID Register      RW */
+#define SYS_ID_REG0    regptr(MSP_SLP_BASE + 0x08)
+                                       /* System-ID Register-0      RW */
+#define SYS_ID_REG1    regptr(MSP_SLP_BASE + 0x0C)
+                                       /* System-ID Register-1      RW */

 
 /* System Reset register definitions */
 
 /* System Reset register definitions */

-#define        RST_STS_REG     regptr(MSP_SLP_BASE + 0x10)
-                                       /* System Reset Status       RO */
-#define        RST_SET_REG     regptr(MSP_SLP_BASE + 0x14)
-                                       /* System Set Reset          WO */
-#define        RST_CLR_REG     regptr(MSP_SLP_BASE + 0x18)
-                                       /* System Clear Reset        WO */
+#define RST_STS_REG    regptr(MSP_SLP_BASE + 0x10)
+                                       /* System Reset Status       RO */
+#define RST_SET_REG    regptr(MSP_SLP_BASE + 0x14)
+                                       /* System Set Reset          WO */
+#define RST_CLR_REG    regptr(MSP_SLP_BASE + 0x18)
+                                       /* System Clear Reset        WO */

 
 /* System Clock Registers */
 #define PCI_SLP_REG    regptr(MSP_SLP_BASE + 0x1C)
 
 /* System Clock Registers */
 #define PCI_SLP_REG    regptr(MSP_SLP_BASE + 0x1C)

-                                       /* PCI clock generator       RW */
+                                       /* PCI clock generator       RW */

 #define URT_SLP_REG    regptr(MSP_SLP_BASE + 0x20)
 #define URT_SLP_REG    regptr(MSP_SLP_BASE + 0x20)

-                                       /* UART clock generator      RW */
-/* reserved                  (MSP_SLP_BASE + 0x24)                     */
-/* reserved                  (MSP_SLP_BASE + 0x28)                     */
+                                       /* UART clock generator      RW */
+/* reserved                  (MSP_SLP_BASE + 0x24)                     */
+/* reserved                  (MSP_SLP_BASE + 0x28)                     */

 #define PLL1_SLP_REG   regptr(MSP_SLP_BASE + 0x2C)
 #define PLL1_SLP_REG   regptr(MSP_SLP_BASE + 0x2C)

-                                       /* PLL1 clock generator      RW */
+                                       /* PLL1 clock generator      RW */

 #define PLL0_SLP_REG   regptr(MSP_SLP_BASE + 0x30)
 #define PLL0_SLP_REG   regptr(MSP_SLP_BASE + 0x30)

-                                       /* PLL0 clock generator      RW */
+                                       /* PLL0 clock generator      RW */

 #define MIPS_SLP_REG   regptr(MSP_SLP_BASE + 0x34)
 #define MIPS_SLP_REG   regptr(MSP_SLP_BASE + 0x34)

-                                       /* MIPS clock generator      RW */
-#define        VE_SLP_REG      regptr(MSP_SLP_BASE + 0x38)
+                                       /* MIPS clock generator      RW */
+#define VE_SLP_REG     regptr(MSP_SLP_BASE + 0x38)

                                        /* Voice Eng clock generator RW */
                                        /* Voice Eng clock generator RW */

-/* reserved                  (MSP_SLP_BASE + 0x3C)                     */
+/* reserved                  (MSP_SLP_BASE + 0x3C)                     */

 #define MSB_SLP_REG    regptr(MSP_SLP_BASE + 0x40)
                                        /* MS-Bus clock generator    RW */
 #define SMAC_SLP_REG   regptr(MSP_SLP_BASE + 0x44)
 #define MSB_SLP_REG    regptr(MSP_SLP_BASE + 0x40)
                                        /* MS-Bus clock generator    RW */
 #define SMAC_SLP_REG   regptr(MSP_SLP_BASE + 0x44)


@@ -216,108 +216,108 @@
 #define SE_MBOX_REG    regptr(MSP_SLP_BASE + 0x78)
                                        /* Security Engine mailbox   RW */
 #define VE_MBOX_REG    regptr(MSP_SLP_BASE + 0x7C)
 #define SE_MBOX_REG    regptr(MSP_SLP_BASE + 0x78)
                                        /* Security Engine mailbox   RW */
 #define VE_MBOX_REG    regptr(MSP_SLP_BASE + 0x7C)

-                                       /* Voice Engine mailbox      RW */
+                                       /* Voice Engine mailbox      RW */

 
 /* ELB Controller Registers */
 #define CS0_CNFG_REG   regptr(MSP_SLP_BASE + 0x80)
 
 /* ELB Controller Registers */
 #define CS0_CNFG_REG   regptr(MSP_SLP_BASE + 0x80)

-                                       /* ELB CS0 Configuration Reg    */
+                                       /* ELB CS0 Configuration Reg    */

 #define CS0_ADDR_REG   regptr(MSP_SLP_BASE + 0x84)
 #define CS0_ADDR_REG   regptr(MSP_SLP_BASE + 0x84)

-                                       /* ELB CS0 Base Address Reg     */
+                                       /* ELB CS0 Base Address Reg     */

 #define CS0_MASK_REG   regptr(MSP_SLP_BASE + 0x88)
 #define CS0_MASK_REG   regptr(MSP_SLP_BASE + 0x88)

-                                       /* ELB CS0 Mask Register        */
+                                       /* ELB CS0 Mask Register        */

 #define CS0_ACCESS_REG regptr(MSP_SLP_BASE + 0x8C)
 #define CS0_ACCESS_REG regptr(MSP_SLP_BASE + 0x8C)

-                                       /* ELB CS0 access register      */
+                                       /* ELB CS0 access register      */

 
 #define CS1_CNFG_REG   regptr(MSP_SLP_BASE + 0x90)
 
 #define CS1_CNFG_REG   regptr(MSP_SLP_BASE + 0x90)

-                                       /* ELB CS1 Configuration Reg    */
+                                       /* ELB CS1 Configuration Reg    */

 #define CS1_ADDR_REG   regptr(MSP_SLP_BASE + 0x94)
 #define CS1_ADDR_REG   regptr(MSP_SLP_BASE + 0x94)

-                                       /* ELB CS1 Base Address Reg     */
+                                       /* ELB CS1 Base Address Reg     */

 #define CS1_MASK_REG   regptr(MSP_SLP_BASE + 0x98)
 #define CS1_MASK_REG   regptr(MSP_SLP_BASE + 0x98)

-                                       /* ELB CS1 Mask Register        */
+                                       /* ELB CS1 Mask Register        */

 #define CS1_ACCESS_REG regptr(MSP_SLP_BASE + 0x9C)
 #define CS1_ACCESS_REG regptr(MSP_SLP_BASE + 0x9C)

-                                       /* ELB CS1 access register      */
+                                       /* ELB CS1 access register      */

 
 #define CS2_CNFG_REG   regptr(MSP_SLP_BASE + 0xA0)
 
 #define CS2_CNFG_REG   regptr(MSP_SLP_BASE + 0xA0)

-                                       /* ELB CS2 Configuration Reg    */
+                                       /* ELB CS2 Configuration Reg    */

 #define CS2_ADDR_REG   regptr(MSP_SLP_BASE + 0xA4)
 #define CS2_ADDR_REG   regptr(MSP_SLP_BASE + 0xA4)

-                                       /* ELB CS2 Base Address Reg     */
+                                       /* ELB CS2 Base Address Reg     */

 #define CS2_MASK_REG   regptr(MSP_SLP_BASE + 0xA8)
 #define CS2_MASK_REG   regptr(MSP_SLP_BASE + 0xA8)

-                                       /* ELB CS2 Mask Register        */
+                                       /* ELB CS2 Mask Register        */

 #define CS2_ACCESS_REG regptr(MSP_SLP_BASE + 0xAC)
 #define CS2_ACCESS_REG regptr(MSP_SLP_BASE + 0xAC)

-                                       /* ELB CS2 access register      */
+                                       /* ELB CS2 access register      */

 
 #define CS3_CNFG_REG   regptr(MSP_SLP_BASE + 0xB0)
 
 #define CS3_CNFG_REG   regptr(MSP_SLP_BASE + 0xB0)

-                                       /* ELB CS3 Configuration Reg    */
+                                       /* ELB CS3 Configuration Reg    */

 #define CS3_ADDR_REG   regptr(MSP_SLP_BASE + 0xB4)
 #define CS3_ADDR_REG   regptr(MSP_SLP_BASE + 0xB4)

-                                       /* ELB CS3 Base Address Reg     */
+                                       /* ELB CS3 Base Address Reg     */

 #define CS3_MASK_REG   regptr(MSP_SLP_BASE + 0xB8)
 #define CS3_MASK_REG   regptr(MSP_SLP_BASE + 0xB8)

-                                       /* ELB CS3 Mask Register        */
+                                       /* ELB CS3 Mask Register        */

 #define CS3_ACCESS_REG regptr(MSP_SLP_BASE + 0xBC)
 #define CS3_ACCESS_REG regptr(MSP_SLP_BASE + 0xBC)

-                                       /* ELB CS3 access register      */
+                                       /* ELB CS3 access register      */

 
 #define CS4_CNFG_REG   regptr(MSP_SLP_BASE + 0xC0)
 
 #define CS4_CNFG_REG   regptr(MSP_SLP_BASE + 0xC0)

-                                       /* ELB CS4 Configuration Reg    */
+                                       /* ELB CS4 Configuration Reg    */

 #define CS4_ADDR_REG   regptr(MSP_SLP_BASE + 0xC4)
 #define CS4_ADDR_REG   regptr(MSP_SLP_BASE + 0xC4)

-                                       /* ELB CS4 Base Address Reg     */
+                                       /* ELB CS4 Base Address Reg     */

 #define CS4_MASK_REG   regptr(MSP_SLP_BASE + 0xC8)
 #define CS4_MASK_REG   regptr(MSP_SLP_BASE + 0xC8)

-                                       /* ELB CS4 Mask Register        */
+                                       /* ELB CS4 Mask Register        */

 #define CS4_ACCESS_REG regptr(MSP_SLP_BASE + 0xCC)
 #define CS4_ACCESS_REG regptr(MSP_SLP_BASE + 0xCC)

-                                       /* ELB CS4 access register      */
+                                       /* ELB CS4 access register      */

 
 #define CS5_CNFG_REG   regptr(MSP_SLP_BASE + 0xD0)
 
 #define CS5_CNFG_REG   regptr(MSP_SLP_BASE + 0xD0)

-                                       /* ELB CS5 Configuration Reg    */
+                                       /* ELB CS5 Configuration Reg    */

 #define CS5_ADDR_REG   regptr(MSP_SLP_BASE + 0xD4)
 #define CS5_ADDR_REG   regptr(MSP_SLP_BASE + 0xD4)

-                                       /* ELB CS5 Base Address Reg     */
+                                       /* ELB CS5 Base Address Reg     */

 #define CS5_MASK_REG   regptr(MSP_SLP_BASE + 0xD8)
 #define CS5_MASK_REG   regptr(MSP_SLP_BASE + 0xD8)

-                                       /* ELB CS5 Mask Register        */
+                                       /* ELB CS5 Mask Register        */

 #define CS5_ACCESS_REG regptr(MSP_SLP_BASE + 0xDC)
 #define CS5_ACCESS_REG regptr(MSP_SLP_BASE + 0xDC)

-                                       /* ELB CS5 access register      */
+                                       /* ELB CS5 access register      */

 
 

-/* reserved                           0xE0 - 0xE8                      */
+/* reserved                           0xE0 - 0xE8                      */

 #define ELB_1PC_EN_REG regptr(MSP_SLP_BASE + 0xEC)
 #define ELB_1PC_EN_REG regptr(MSP_SLP_BASE + 0xEC)

-                                       /* ELB single PC card detect    */
+                                       /* ELB single PC card detect    */

 
 

-/* reserved                           0xF0 - 0xF8                      */
-#define ELB_CLK_CFG_REG        regptr(MSP_SLP_BASE + 0xFC)
-                                       /* SDRAM read/ELB timing Reg    */
+/* reserved                           0xF0 - 0xF8                      */
+#define ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC)
+                                       /* SDRAM read/ELB timing Reg    */

 
 /* Extended UART status registers */
 #define UART0_STATUS_REG       regptr(MSP_UART0_BASE + 0x0c0)
 
 /* Extended UART status registers */
 #define UART0_STATUS_REG       regptr(MSP_UART0_BASE + 0x0c0)

-                                       /* UART Status Register 0       */
+                                       /* UART Status Register 0       */

 #define UART1_STATUS_REG       regptr(MSP_UART1_BASE + 0x170)
 #define UART1_STATUS_REG       regptr(MSP_UART1_BASE + 0x170)

-                                       /* UART Status Register 1       */
+                                       /* UART Status Register 1       */

 
 /* Performance monitoring registers */
 #define PERF_MON_CTRL_REG      regptr(MSP_SLP_BASE + 0x140)
 
 /* Performance monitoring registers */
 #define PERF_MON_CTRL_REG      regptr(MSP_SLP_BASE + 0x140)

-                                       /* Performance monitor control  */
+                                       /* Performance monitor control  */

 #define PERF_MON_CLR_REG       regptr(MSP_SLP_BASE + 0x144)
 #define PERF_MON_CLR_REG       regptr(MSP_SLP_BASE + 0x144)

-                                       /* Performance monitor clear    */
+                                       /* Performance monitor clear    */

 #define PERF_MON_CNTH_REG      regptr(MSP_SLP_BASE + 0x148)
 #define PERF_MON_CNTH_REG      regptr(MSP_SLP_BASE + 0x148)

-                                       /* Perf monitor counter high    */
+                                       /* Perf monitor counter high    */

 #define PERF_MON_CNTL_REG      regptr(MSP_SLP_BASE + 0x14C)
 #define PERF_MON_CNTL_REG      regptr(MSP_SLP_BASE + 0x14C)

-                                       /* Perf monitor counter low     */
+                                       /* Perf monitor counter low     */

 
 /* System control registers */
 #define SYS_CTRL_REG           regptr(MSP_SLP_BASE + 0x150)
 
 /* System control registers */
 #define SYS_CTRL_REG           regptr(MSP_SLP_BASE + 0x150)

-                                       /* System control register      */
+                                       /* System control register      */

 #define SYS_ERR1_REG           regptr(MSP_SLP_BASE + 0x154)
 #define SYS_ERR1_REG           regptr(MSP_SLP_BASE + 0x154)

-                                       /* System Error status 1        */
+                                       /* System Error status 1        */

 #define SYS_ERR2_REG           regptr(MSP_SLP_BASE + 0x158)
 #define SYS_ERR2_REG           regptr(MSP_SLP_BASE + 0x158)

-                                       /* System Error status 2        */
+                                       /* System Error status 2        */

 #define SYS_INT_CFG_REG                regptr(MSP_SLP_BASE + 0x15C)
 #define SYS_INT_CFG_REG                regptr(MSP_SLP_BASE + 0x15C)

-                                       /* System Interrupt config      */
+                                       /* System Interrupt config      */

 
 /* Voice Engine Memory configuration */
 #define VE_MEM_REG             regptr(MSP_SLP_BASE + 0x17C)
 
 /* Voice Engine Memory configuration */
 #define VE_MEM_REG             regptr(MSP_SLP_BASE + 0x17C)

-                                       /* Voice engine memory config   */
+                                       /* Voice engine memory config   */

 
 /* CPU/SLP Error Status registers */
 #define CPU_ERR1_REG           regptr(MSP_SLP_BASE + 0x180)
 
 /* CPU/SLP Error Status registers */
 #define CPU_ERR1_REG           regptr(MSP_SLP_BASE + 0x180)

-                                       /* CPU/SLP Error status 1       */
+                                       /* CPU/SLP Error status 1       */

 #define CPU_ERR2_REG           regptr(MSP_SLP_BASE + 0x184)
 #define CPU_ERR2_REG           regptr(MSP_SLP_BASE + 0x184)

-                                       /* CPU/SLP Error status 1       */
+                                       /* CPU/SLP Error status 1       */

 
 

-/* Extended GPIO registers       */
+/* Extended GPIO registers      */

 #define EXTENDED_GPIO1_REG     regptr(MSP_SLP_BASE + 0x188)
 #define EXTENDED_GPIO2_REG     regptr(MSP_SLP_BASE + 0x18c)
 #define EXTENDED_GPIO_REG      EXTENDED_GPIO1_REG
 #define EXTENDED_GPIO1_REG     regptr(MSP_SLP_BASE + 0x188)
 #define EXTENDED_GPIO2_REG     regptr(MSP_SLP_BASE + 0x18c)
 #define EXTENDED_GPIO_REG      EXTENDED_GPIO1_REG


@@ -325,182 +325,182 @@
 
 /* System Error registers */
 #define SLP_ERR_STS_REG                regptr(MSP_SLP_BASE + 0x190)
 
 /* System Error registers */
 #define SLP_ERR_STS_REG                regptr(MSP_SLP_BASE + 0x190)

-                                       /* Int status for SLP errors    */
+                                       /* Int status for SLP errors    */

 #define SLP_ERR_MSK_REG                regptr(MSP_SLP_BASE + 0x194)
 #define SLP_ERR_MSK_REG                regptr(MSP_SLP_BASE + 0x194)

-                                       /* Int mask for SLP errors      */
+                                       /* Int mask for SLP errors      */

 #define SLP_ELB_ERST_REG       regptr(MSP_SLP_BASE + 0x198)
 #define SLP_ELB_ERST_REG       regptr(MSP_SLP_BASE + 0x198)

-                                       /* External ELB reset           */
+                                       /* External ELB reset           */

 #define SLP_BOOT_STS_REG       regptr(MSP_SLP_BASE + 0x19C)
 #define SLP_BOOT_STS_REG       regptr(MSP_SLP_BASE + 0x19C)

-                                       /* Boot Status                  */
+                                       /* Boot Status                  */

 
 /* Extended ELB addressing */
 #define CS0_EXT_ADDR_REG       regptr(MSP_SLP_BASE + 0x1A0)
 
 /* Extended ELB addressing */
 #define CS0_EXT_ADDR_REG       regptr(MSP_SLP_BASE + 0x1A0)

-                                       /* CS0 Extended address         */
+                                       /* CS0 Extended address         */

 #define CS1_EXT_ADDR_REG       regptr(MSP_SLP_BASE + 0x1A4)
 #define CS1_EXT_ADDR_REG       regptr(MSP_SLP_BASE + 0x1A4)

-                                       /* CS1 Extended address         */
+                                       /* CS1 Extended address         */

 #define CS2_EXT_ADDR_REG       regptr(MSP_SLP_BASE + 0x1A8)
 #define CS2_EXT_ADDR_REG       regptr(MSP_SLP_BASE + 0x1A8)

-                                       /* CS2 Extended address         */
+                                       /* CS2 Extended address         */

 #define CS3_EXT_ADDR_REG       regptr(MSP_SLP_BASE + 0x1AC)
 #define CS3_EXT_ADDR_REG       regptr(MSP_SLP_BASE + 0x1AC)

-                                       /* CS3 Extended address         */
-/* reserved                                          0x1B0             */
+                                       /* CS3 Extended address         */
+/* reserved                                          0x1B0             */

 #define CS5_EXT_ADDR_REG       regptr(MSP_SLP_BASE + 0x1B4)
 #define CS5_EXT_ADDR_REG       regptr(MSP_SLP_BASE + 0x1B4)

-                                       /* CS5 Extended address         */
+                                       /* CS5 Extended address         */

 
 /* PLL Adjustment registers */
 #define PLL_LOCK_REG           regptr(MSP_SLP_BASE + 0x200)
 
 /* PLL Adjustment registers */
 #define PLL_LOCK_REG           regptr(MSP_SLP_BASE + 0x200)

-                                       /* PLL0 lock status             */
+                                       /* PLL0 lock status             */

 #define PLL_ARST_REG           regptr(MSP_SLP_BASE + 0x204)
 #define PLL_ARST_REG           regptr(MSP_SLP_BASE + 0x204)

-                                       /* PLL Analog reset status      */
+                                       /* PLL Analog reset status      */

 #define PLL0_ADJ_REG           regptr(MSP_SLP_BASE + 0x208)
 #define PLL0_ADJ_REG           regptr(MSP_SLP_BASE + 0x208)

-                                       /* PLL0 Adjustment value        */
+                                       /* PLL0 Adjustment value        */

 #define PLL1_ADJ_REG           regptr(MSP_SLP_BASE + 0x20C)
 #define PLL1_ADJ_REG           regptr(MSP_SLP_BASE + 0x20C)

-                                       /* PLL1 Adjustment value        */
+                                       /* PLL1 Adjustment value        */

 
 /*
  ***************************************************************************
 
 /*
  ***************************************************************************

- * Peripheral Register definitions                                         *
+ * Peripheral Register definitions                                        *

  ***************************************************************************
  */
 
 /* Peripheral status */
 #define PER_CTRL_REG           regptr(MSP_PER_BASE + 0x50)
  ***************************************************************************
  */
 
 /* Peripheral status */
 #define PER_CTRL_REG           regptr(MSP_PER_BASE + 0x50)

-                                       /* Peripheral control register  */
+                                       /* Peripheral control register  */

 #define PER_STS_REG            regptr(MSP_PER_BASE + 0x54)
 #define PER_STS_REG            regptr(MSP_PER_BASE + 0x54)

-                                       /* Peripheral status register   */
+                                       /* Peripheral status register   */

 
 /* SPI/MPI Registers */
 #define SMPI_TX_SZ_REG         regptr(MSP_PER_BASE + 0x58)
 
 /* SPI/MPI Registers */
 #define SMPI_TX_SZ_REG         regptr(MSP_PER_BASE + 0x58)

-                                       /* SPI/MPI Tx Size register     */
+                                       /* SPI/MPI Tx Size register     */

 #define SMPI_RX_SZ_REG         regptr(MSP_PER_BASE + 0x5C)
 #define SMPI_RX_SZ_REG         regptr(MSP_PER_BASE + 0x5C)

-                                       /* SPI/MPI Rx Size register     */
+                                       /* SPI/MPI Rx Size register     */

 #define SMPI_CTL_REG           regptr(MSP_PER_BASE + 0x60)
 #define SMPI_CTL_REG           regptr(MSP_PER_BASE + 0x60)

-                                       /* SPI/MPI Control register     */
+                                       /* SPI/MPI Control register     */

 #define SMPI_MS_REG            regptr(MSP_PER_BASE + 0x64)
 #define SMPI_MS_REG            regptr(MSP_PER_BASE + 0x64)

-                                       /* SPI/MPI Chip Select reg      */
+                                       /* SPI/MPI Chip Select reg      */

 #define SMPI_CORE_DATA_REG     regptr(MSP_PER_BASE + 0xC0)
 #define SMPI_CORE_DATA_REG     regptr(MSP_PER_BASE + 0xC0)

-                                       /* SPI/MPI Core Data reg        */
+                                       /* SPI/MPI Core Data reg        */

 #define SMPI_CORE_CTRL_REG     regptr(MSP_PER_BASE + 0xC4)
 #define SMPI_CORE_CTRL_REG     regptr(MSP_PER_BASE + 0xC4)

-                                       /* SPI/MPI Core Control reg     */
+                                       /* SPI/MPI Core Control reg     */

 #define SMPI_CORE_STAT_REG     regptr(MSP_PER_BASE + 0xC8)
 #define SMPI_CORE_STAT_REG     regptr(MSP_PER_BASE + 0xC8)

-                                       /* SPI/MPI Core Status reg      */
+                                       /* SPI/MPI Core Status reg      */

 #define SMPI_CORE_SSEL_REG     regptr(MSP_PER_BASE + 0xCC)
 #define SMPI_CORE_SSEL_REG     regptr(MSP_PER_BASE + 0xCC)

-                                       /* SPI/MPI Core Ssel reg        */
+                                       /* SPI/MPI Core Ssel reg        */

 #define SMPI_FIFO_REG          regptr(MSP_PER_BASE + 0xD0)
 #define SMPI_FIFO_REG          regptr(MSP_PER_BASE + 0xD0)

-                                       /* SPI/MPI Data FIFO reg        */
+                                       /* SPI/MPI Data FIFO reg        */

 
 

-/* Peripheral Block Error Registers           */
+/* Peripheral Block Error Registers          */

 #define PER_ERR_STS_REG                regptr(MSP_PER_BASE + 0x70)
 #define PER_ERR_STS_REG                regptr(MSP_PER_BASE + 0x70)

-                                       /* Error Bit Status Register    */
+                                       /* Error Bit Status Register    */

 #define PER_ERR_MSK_REG                regptr(MSP_PER_BASE + 0x74)
 #define PER_ERR_MSK_REG                regptr(MSP_PER_BASE + 0x74)

-                                       /* Error Bit Mask Register      */
+                                       /* Error Bit Mask Register      */

 #define PER_HDR1_REG           regptr(MSP_PER_BASE + 0x78)
 #define PER_HDR1_REG           regptr(MSP_PER_BASE + 0x78)

-                                       /* Error Header 1 Register      */
+                                       /* Error Header 1 Register      */

 #define PER_HDR2_REG           regptr(MSP_PER_BASE + 0x7C)
 #define PER_HDR2_REG           regptr(MSP_PER_BASE + 0x7C)

-                                       /* Error Header 2 Register      */
+                                       /* Error Header 2 Register      */

 
 

-/* Peripheral Block Interrupt Registers       */
+/* Peripheral Block Interrupt Registers              */

 #define PER_INT_STS_REG                regptr(MSP_PER_BASE + 0x80)
 #define PER_INT_STS_REG                regptr(MSP_PER_BASE + 0x80)

-                                       /* Interrupt status register    */
+                                       /* Interrupt status register    */

 #define PER_INT_MSK_REG                regptr(MSP_PER_BASE + 0x84)
 #define PER_INT_MSK_REG                regptr(MSP_PER_BASE + 0x84)

-                                       /* Interrupt Mask Register      */
+                                       /* Interrupt Mask Register      */

 #define GPIO_INT_STS_REG       regptr(MSP_PER_BASE + 0x88)
 #define GPIO_INT_STS_REG       regptr(MSP_PER_BASE + 0x88)

-                                       /* GPIO interrupt status reg    */
+                                       /* GPIO interrupt status reg    */

 #define GPIO_INT_MSK_REG       regptr(MSP_PER_BASE + 0x8C)
 #define GPIO_INT_MSK_REG       regptr(MSP_PER_BASE + 0x8C)

-                                       /* GPIO interrupt MASK Reg      */
+                                       /* GPIO interrupt MASK Reg      */

 
 

-/* POLO GPIO registers                        */
+/* POLO GPIO registers                       */

 #define POLO_GPIO_DAT1_REG     regptr(MSP_PER_BASE + 0x0E0)
 #define POLO_GPIO_DAT1_REG     regptr(MSP_PER_BASE + 0x0E0)

-                                       /* Polo GPIO[8:0]  data reg     */
+                                       /* Polo GPIO[8:0]  data reg     */

 #define POLO_GPIO_CFG1_REG     regptr(MSP_PER_BASE + 0x0E4)
 #define POLO_GPIO_CFG1_REG     regptr(MSP_PER_BASE + 0x0E4)

-                                       /* Polo GPIO[7:0]  config reg   */
+                                       /* Polo GPIO[7:0]  config reg   */

 #define POLO_GPIO_CFG2_REG     regptr(MSP_PER_BASE + 0x0E8)
 #define POLO_GPIO_CFG2_REG     regptr(MSP_PER_BASE + 0x0E8)

-                                       /* Polo GPIO[15:8] config reg   */
+                                       /* Polo GPIO[15:8] config reg   */

 #define POLO_GPIO_OD1_REG      regptr(MSP_PER_BASE + 0x0EC)
                                        /* Polo GPIO[31:0] output drive */
 #define POLO_GPIO_CFG3_REG     regptr(MSP_PER_BASE + 0x170)
 #define POLO_GPIO_OD1_REG      regptr(MSP_PER_BASE + 0x0EC)
                                        /* Polo GPIO[31:0] output drive */
 #define POLO_GPIO_CFG3_REG     regptr(MSP_PER_BASE + 0x170)

-                                       /* Polo GPIO[23:16] config reg  */
+                                       /* Polo GPIO[23:16] config reg  */

 #define POLO_GPIO_DAT2_REG     regptr(MSP_PER_BASE + 0x174)
 #define POLO_GPIO_DAT2_REG     regptr(MSP_PER_BASE + 0x174)

-                                       /* Polo GPIO[15:9]  data reg    */
+                                       /* Polo GPIO[15:9]  data reg    */

 #define POLO_GPIO_DAT3_REG     regptr(MSP_PER_BASE + 0x178)
 #define POLO_GPIO_DAT3_REG     regptr(MSP_PER_BASE + 0x178)

-                                       /* Polo GPIO[23:16]  data reg   */
+                                       /* Polo GPIO[23:16]  data reg   */

 #define POLO_GPIO_DAT4_REG     regptr(MSP_PER_BASE + 0x17C)
 #define POLO_GPIO_DAT4_REG     regptr(MSP_PER_BASE + 0x17C)

-                                       /* Polo GPIO[31:24]  data reg   */
+                                       /* Polo GPIO[31:24]  data reg   */

 #define POLO_GPIO_DAT5_REG     regptr(MSP_PER_BASE + 0x180)
 #define POLO_GPIO_DAT5_REG     regptr(MSP_PER_BASE + 0x180)

-                                       /* Polo GPIO[39:32]  data reg   */
+                                       /* Polo GPIO[39:32]  data reg   */

 #define POLO_GPIO_DAT6_REG     regptr(MSP_PER_BASE + 0x184)
 #define POLO_GPIO_DAT6_REG     regptr(MSP_PER_BASE + 0x184)

-                                       /* Polo GPIO[47:40]  data reg   */
+                                       /* Polo GPIO[47:40]  data reg   */

 #define POLO_GPIO_DAT7_REG     regptr(MSP_PER_BASE + 0x188)
 #define POLO_GPIO_DAT7_REG     regptr(MSP_PER_BASE + 0x188)

-                                       /* Polo GPIO[54:48]  data reg   */
+                                       /* Polo GPIO[54:48]  data reg   */

 #define POLO_GPIO_CFG4_REG     regptr(MSP_PER_BASE + 0x18C)
 #define POLO_GPIO_CFG4_REG     regptr(MSP_PER_BASE + 0x18C)

-                                       /* Polo GPIO[31:24] config reg  */
+                                       /* Polo GPIO[31:24] config reg  */

 #define POLO_GPIO_CFG5_REG     regptr(MSP_PER_BASE + 0x190)
 #define POLO_GPIO_CFG5_REG     regptr(MSP_PER_BASE + 0x190)

-                                       /* Polo GPIO[39:32] config reg  */
+                                       /* Polo GPIO[39:32] config reg  */

 #define POLO_GPIO_CFG6_REG     regptr(MSP_PER_BASE + 0x194)
 #define POLO_GPIO_CFG6_REG     regptr(MSP_PER_BASE + 0x194)

-                                       /* Polo GPIO[47:40] config reg  */
+                                       /* Polo GPIO[47:40] config reg  */

 #define POLO_GPIO_CFG7_REG     regptr(MSP_PER_BASE + 0x198)
 #define POLO_GPIO_CFG7_REG     regptr(MSP_PER_BASE + 0x198)

-                                       /* Polo GPIO[54:48] config reg  */
+                                       /* Polo GPIO[54:48] config reg  */

 #define POLO_GPIO_OD2_REG      regptr(MSP_PER_BASE + 0x19C)
                                        /* Polo GPIO[54:32] output drive */
 
 #define POLO_GPIO_OD2_REG      regptr(MSP_PER_BASE + 0x19C)
                                        /* Polo GPIO[54:32] output drive */
 

-/* Generic GPIO registers                     */
+/* Generic GPIO registers                    */

 #define GPIO_DATA1_REG         regptr(MSP_PER_BASE + 0x170)
 #define GPIO_DATA1_REG         regptr(MSP_PER_BASE + 0x170)

-                                       /* GPIO[1:0] data register      */
+                                       /* GPIO[1:0] data register      */

 #define GPIO_DATA2_REG         regptr(MSP_PER_BASE + 0x174)
 #define GPIO_DATA2_REG         regptr(MSP_PER_BASE + 0x174)

-                                       /* GPIO[5:2] data register      */
+                                       /* GPIO[5:2] data register      */

 #define GPIO_DATA3_REG         regptr(MSP_PER_BASE + 0x178)
 #define GPIO_DATA3_REG         regptr(MSP_PER_BASE + 0x178)

-                                       /* GPIO[9:6] data register      */
+                                       /* GPIO[9:6] data register      */

 #define GPIO_DATA4_REG         regptr(MSP_PER_BASE + 0x17C)
 #define GPIO_DATA4_REG         regptr(MSP_PER_BASE + 0x17C)

-                                       /* GPIO[15:10] data register    */
+                                       /* GPIO[15:10] data register    */

 #define GPIO_CFG1_REG          regptr(MSP_PER_BASE + 0x180)
 #define GPIO_CFG1_REG          regptr(MSP_PER_BASE + 0x180)

-                                       /* GPIO[1:0] config register    */
+                                       /* GPIO[1:0] config register    */

 #define GPIO_CFG2_REG          regptr(MSP_PER_BASE + 0x184)
 #define GPIO_CFG2_REG          regptr(MSP_PER_BASE + 0x184)

-                                       /* GPIO[5:2] config register    */
+                                       /* GPIO[5:2] config register    */

 #define GPIO_CFG3_REG          regptr(MSP_PER_BASE + 0x188)
 #define GPIO_CFG3_REG          regptr(MSP_PER_BASE + 0x188)

-                                       /* GPIO[9:6] config register    */
+                                       /* GPIO[9:6] config register    */

 #define GPIO_CFG4_REG          regptr(MSP_PER_BASE + 0x18C)
 #define GPIO_CFG4_REG          regptr(MSP_PER_BASE + 0x18C)

-                                       /* GPIO[15:10] config register  */
+                                       /* GPIO[15:10] config register  */

 #define GPIO_OD_REG            regptr(MSP_PER_BASE + 0x190)
 #define GPIO_OD_REG            regptr(MSP_PER_BASE + 0x190)

-                                       /* GPIO[15:0] output drive      */
+                                       /* GPIO[15:0] output drive      */

 
 /*
  ***************************************************************************
 
 /*
  ***************************************************************************

- * CPU Interface register definitions                                      *
+ * CPU Interface register definitions                                     *

  ***************************************************************************
  */
 #define PCI_FLUSH_REG          regptr(MSP_CPUIF_BASE + 0x00)
                                        /* PCI-SDRAM queue flush trigger */
 #define OCP_ERR1_REG           regptr(MSP_CPUIF_BASE + 0x04)
  ***************************************************************************
  */
 #define PCI_FLUSH_REG          regptr(MSP_CPUIF_BASE + 0x00)
                                        /* PCI-SDRAM queue flush trigger */
 #define OCP_ERR1_REG           regptr(MSP_CPUIF_BASE + 0x04)

-                                       /* OCP Error Attribute 1        */
+                                       /* OCP Error Attribute 1        */

 #define OCP_ERR2_REG           regptr(MSP_CPUIF_BASE + 0x08)
 #define OCP_ERR2_REG           regptr(MSP_CPUIF_BASE + 0x08)

-                                       /* OCP Error Attribute 2        */
+                                       /* OCP Error Attribute 2        */

 #define OCP_STS_REG            regptr(MSP_CPUIF_BASE + 0x0C)
 #define OCP_STS_REG            regptr(MSP_CPUIF_BASE + 0x0C)

-                                       /* OCP Error Status             */
+                                       /* OCP Error Status             */

 #define CPUIF_PM_REG           regptr(MSP_CPUIF_BASE + 0x10)
 #define CPUIF_PM_REG           regptr(MSP_CPUIF_BASE + 0x10)

-                                       /* CPU policy configuration     */
+                                       /* CPU policy configuration     */

 #define CPUIF_CFG_REG          regptr(MSP_CPUIF_BASE + 0x10)
 #define CPUIF_CFG_REG          regptr(MSP_CPUIF_BASE + 0x10)

-                                       /* Misc configuration options   */
+                                       /* Misc configuration options   */

 
 /* Central Interrupt Controller Registers */
 #define MSP_CIC_BASE           (MSP_CPUIF_BASE + 0x8000)
 
 /* Central Interrupt Controller Registers */
 #define MSP_CIC_BASE           (MSP_CPUIF_BASE + 0x8000)

-                                       /* Central Interrupt registers  */
+                                       /* Central Interrupt registers  */

 #define CIC_EXT_CFG_REG                regptr(MSP_CIC_BASE + 0x00)
 #define CIC_EXT_CFG_REG                regptr(MSP_CIC_BASE + 0x00)

-                                       /* External interrupt config    */
+                                       /* External interrupt config    */

 #define CIC_STS_REG            regptr(MSP_CIC_BASE + 0x04)
 #define CIC_STS_REG            regptr(MSP_CIC_BASE + 0x04)

-                                       /* CIC Interrupt Status         */
+                                       /* CIC Interrupt Status         */

 #define CIC_VPE0_MSK_REG       regptr(MSP_CIC_BASE + 0x08)
 #define CIC_VPE0_MSK_REG       regptr(MSP_CIC_BASE + 0x08)

-                                       /* VPE0 Interrupt Mask          */
+                                       /* VPE0 Interrupt Mask          */

 #define CIC_VPE1_MSK_REG       regptr(MSP_CIC_BASE + 0x0C)
 #define CIC_VPE1_MSK_REG       regptr(MSP_CIC_BASE + 0x0C)

-                                       /* VPE1 Interrupt Mask          */
+                                       /* VPE1 Interrupt Mask          */

 #define CIC_TC0_MSK_REG                regptr(MSP_CIC_BASE + 0x10)
 #define CIC_TC0_MSK_REG                regptr(MSP_CIC_BASE + 0x10)

-                                       /* Thread Context 0 Int Mask    */
+                                       /* Thread Context 0 Int Mask    */

 #define CIC_TC1_MSK_REG                regptr(MSP_CIC_BASE + 0x14)
 #define CIC_TC1_MSK_REG                regptr(MSP_CIC_BASE + 0x14)

-                                       /* Thread Context 1 Int Mask    */
+                                       /* Thread Context 1 Int Mask    */

 #define CIC_TC2_MSK_REG                regptr(MSP_CIC_BASE + 0x18)
 #define CIC_TC2_MSK_REG                regptr(MSP_CIC_BASE + 0x18)

-                                       /* Thread Context 2 Int Mask    */
+                                       /* Thread Context 2 Int Mask    */

 #define CIC_TC3_MSK_REG                regptr(MSP_CIC_BASE + 0x18)
 #define CIC_TC3_MSK_REG                regptr(MSP_CIC_BASE + 0x18)

-                                       /* Thread Context 3 Int Mask    */
+                                       /* Thread Context 3 Int Mask    */

 #define CIC_TC4_MSK_REG                regptr(MSP_CIC_BASE + 0x18)
 #define CIC_TC4_MSK_REG                regptr(MSP_CIC_BASE + 0x18)

-                                       /* Thread Context 4 Int Mask    */
+                                       /* Thread Context 4 Int Mask    */

 #define CIC_PCIMSI_STS_REG     regptr(MSP_CIC_BASE + 0x18)
 #define CIC_PCIMSI_MSK_REG     regptr(MSP_CIC_BASE + 0x18)
 #define CIC_PCIFLSH_REG                regptr(MSP_CIC_BASE + 0x18)
 #define CIC_PCIMSI_STS_REG     regptr(MSP_CIC_BASE + 0x18)
 #define CIC_PCIMSI_MSK_REG     regptr(MSP_CIC_BASE + 0x18)
 #define CIC_PCIFLSH_REG                regptr(MSP_CIC_BASE + 0x18)


@@ -509,7 +509,7 @@
 
 /*
  ***************************************************************************
 
 /*
  ***************************************************************************

- * Memory controller registers                                             *
+ * Memory controller registers                                            *

  ***************************************************************************
  */
 #define MEM_CFG1_REG           regptr(MSP_MEM_CFG_BASE + 0x00)
  ***************************************************************************
  */
 #define MEM_CFG1_REG           regptr(MSP_MEM_CFG_BASE + 0x00)


@@ -519,7 +519,7 @@
 
 /*
  ***************************************************************************
 
 /*
  ***************************************************************************

- * PCI controller registers                                                *
+ * PCI controller registers                                               *

  ***************************************************************************
  */
 #define PCI_BASE_REG           regptr(MSP_PCI_BASE + 0x00)
  ***************************************************************************
  */
 #define PCI_BASE_REG           regptr(MSP_PCI_BASE + 0x00)


@@ -528,25 +528,25 @@
 
 /*
  ########################################################################
 
 /*
  ########################################################################

- #  Register content & macro definitions                                #
+ #  Register content & macro definitions                               #

  ########################################################################
  */
 
 /*
  ***************************************************************************
  ########################################################################
  */
 
 /*
  ***************************************************************************

- * DEV_ID defines                                                          *
+ * DEV_ID defines                                                         *

  ***************************************************************************
  */
  ***************************************************************************
  */

-#define DEV_ID_PCI_DIS         (1 << 26)       /* Set if PCI disabled */
-#define DEV_ID_PCI_HOST                (1 << 20)       /* Set if PCI host */
-#define DEV_ID_SINGLE_PC       (1 << 19)       /* Set if single PC Card */
-#define DEV_ID_FAMILY          (0xff << 8)     /* family ID code */
-#define POLO_ZEUS_SUB_FAMILY   (0x7  << 16)    /* sub family for Polo/Zeus */
+#define DEV_ID_PCI_DIS         (1 << 26)       /* Set if PCI disabled */
+#define DEV_ID_PCI_HOST                (1 << 20)       /* Set if PCI host */
+#define DEV_ID_SINGLE_PC       (1 << 19)       /* Set if single PC Card */
+#define DEV_ID_FAMILY          (0xff << 8)     /* family ID code */
+#define POLO_ZEUS_SUB_FAMILY   (0x7  << 16)    /* sub family for Polo/Zeus */

 
 

-#define MSPFPGA_ID             (0x00  << 8)    /* you are on your own here */
+#define MSPFPGA_ID             (0x00  << 8)    /* you are on your own here */

 #define MSP5000_ID             (0x50  << 8)
 #define MSP5000_ID             (0x50  << 8)

-#define MSP4F00_ID             (0x4f  << 8)    /* FPGA version of MSP4200 */
-#define MSP4E00_ID             (0x4f  << 8)    /* FPGA version of MSP7120 */
+#define MSP4F00_ID             (0x4f  << 8)    /* FPGA version of MSP4200 */
+#define MSP4E00_ID             (0x4f  << 8)    /* FPGA version of MSP7120 */

 #define MSP4200_ID             (0x42  << 8)
 #define MSP4000_ID             (0x40  << 8)
 #define MSP2XXX_ID             (0x20  << 8)
 #define MSP4200_ID             (0x42  << 8)
 #define MSP4000_ID             (0x40  << 8)
 #define MSP2XXX_ID             (0x20  << 8)


@@ -563,27 +563,27 @@
 
 /*
  ***************************************************************************
 
 /*
  ***************************************************************************

- * RESET defines                                                           *
+ * RESET defines                                                          *

  ***************************************************************************
  */
  ***************************************************************************
  */

-#define MSP_GR_RST             (0x01 << 0)     /* Global reset bit     */
-#define MSP_MR_RST             (0x01 << 1)     /* MIPS reset bit       */
-#define MSP_PD_RST             (0x01 << 2)     /* PVC DMA reset bit    */
-#define MSP_PP_RST             (0x01 << 3)     /* PVC reset bit        */
-/* reserved                                                             */
-#define MSP_EA_RST             (0x01 << 6)     /* Mac A reset bit      */
-#define MSP_EB_RST             (0x01 << 7)     /* Mac B reset bit      */
-#define MSP_SE_RST             (0x01 << 8)     /* Security Eng reset bit */
-#define MSP_PB_RST             (0x01 << 9)     /* Per block reset bit  */
-#define MSP_EC_RST             (0x01 << 10)    /* Mac C reset bit      */
-#define MSP_TW_RST             (0x01 << 11)    /* TWI reset bit        */
-#define MSP_SPI_RST            (0x01 << 12)    /* SPI/MPI reset bit    */
-#define MSP_U1_RST             (0x01 << 13)    /* UART1 reset bit      */
-#define MSP_U0_RST             (0x01 << 14)    /* UART0 reset bit      */
+#define MSP_GR_RST             (0x01 << 0)     /* Global reset bit     */
+#define MSP_MR_RST             (0x01 << 1)     /* MIPS reset bit       */
+#define MSP_PD_RST             (0x01 << 2)     /* PVC DMA reset bit    */
+#define MSP_PP_RST             (0x01 << 3)     /* PVC reset bit        */
+/* reserved                                                            */
+#define MSP_EA_RST             (0x01 << 6)     /* Mac A reset bit      */
+#define MSP_EB_RST             (0x01 << 7)     /* Mac B reset bit      */
+#define MSP_SE_RST             (0x01 << 8)     /* Security Eng reset bit */
+#define MSP_PB_RST             (0x01 << 9)     /* Per block reset bit  */
+#define MSP_EC_RST             (0x01 << 10)    /* Mac C reset bit      */
+#define MSP_TW_RST             (0x01 << 11)    /* TWI reset bit        */
+#define MSP_SPI_RST            (0x01 << 12)    /* SPI/MPI reset bit    */
+#define MSP_U1_RST             (0x01 << 13)    /* UART1 reset bit      */
+#define MSP_U0_RST             (0x01 << 14)    /* UART0 reset bit      */

 
 /*
  ***************************************************************************
 
 /*
  ***************************************************************************

- * UART defines                                                            *
+ * UART defines                                                                   *

  ***************************************************************************
  */
 #define MSP_BASE_BAUD          25000000
  ***************************************************************************
  */
 #define MSP_BASE_BAUD          25000000


@@ -591,15 +591,15 @@
 
 /*
  ***************************************************************************
 
 /*
  ***************************************************************************

- * ELB defines                                                             *
+ * ELB defines                                                            *

  ***************************************************************************
  */
  ***************************************************************************
  */

-#define PCCARD_32              0x02    /* Set if is PCCARD 32 (Cardbus) */
-#define SINGLE_PCCARD          0x01    /* Set to enable single PC card */
+#define PCCARD_32              0x02    /* Set if is PCCARD 32 (Cardbus) */
+#define SINGLE_PCCARD          0x01    /* Set to enable single PC card */

 
 /*
  ***************************************************************************
 
 /*
  ***************************************************************************

- * CIC defines                                                             *
+ * CIC defines                                                            *

  ***************************************************************************
  */
 
  ***************************************************************************
  */
 


@@ -625,7 +625,7 @@
 
 /*
  ***************************************************************************
 
 /*
  ***************************************************************************

- * Memory Controller defines                                               *
+ * Memory Controller defines                                              *

  ***************************************************************************
  */
 
  ***************************************************************************
  */
 


@@ -644,17 +644,17 @@
 
 /*
  ***************************************************************************
 
 /*
  ***************************************************************************

- * SPI/MPI Mode                                                            *
+ * SPI/MPI Mode                                                                   *

  ***************************************************************************
  */
 #define SPI_MPI_RX_BUSY                0x00008000      /* SPI/MPI Receive Busy */
  ***************************************************************************
  */
 #define SPI_MPI_RX_BUSY                0x00008000      /* SPI/MPI Receive Busy */

-#define SPI_MPI_FIFO_EMPTY     0x00004000      /* SPI/MPI Fifo Empty   */
+#define SPI_MPI_FIFO_EMPTY     0x00004000      /* SPI/MPI Fifo Empty   */

 #define SPI_MPI_TX_BUSY                0x00002000      /* SPI/MPI Transmit Busy */
 #define SPI_MPI_TX_BUSY                0x00002000      /* SPI/MPI Transmit Busy */

-#define SPI_MPI_FIFO_FULL      0x00001000      /* SPI/MPU FIFO full    */
+#define SPI_MPI_FIFO_FULL      0x00001000      /* SPI/MPU FIFO full    */

 
 /*
  ***************************************************************************
 
 /*
  ***************************************************************************

- * SPI/MPI Control Register                                                *
+ * SPI/MPI Control Register                                               *

  ***************************************************************************
  */
 #define SPI_MPI_RX_START       0x00000004      /* Start receive command */
  ***************************************************************************
  */
 #define SPI_MPI_RX_START       0x00000004      /* Start receive command */

diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_slp_int.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_slp_int.h
index 96d4c8ce8c8340eeb3c3c0f23d9e6576be3b5503..51a66dcc429d94a0c209a3f2da4e1ea18c4ccf99 100644 (file)
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_slp_int.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_slp_int.h
@@ -27,9 +27,9 @@
 
 /*
  * The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded
 
 /*
  * The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded

- * hierarchical system.  The first level are the direct MIPS interrupts
+ * hierarchical system.         The first level are the direct MIPS interrupts

  * and are assigned the interrupt range 0-7.  The second level is the SLM
  * and are assigned the interrupt range 0-7.  The second level is the SLM

- * interrupt controller and is assigned the range 8-39.  The third level
+ * interrupt controller and is assigned the range 8-39.         The third level

  * comprises the Peripherial block, the PCI block, the PCI MSI block and
  * the SLP.  The PCI interrupts and the SLP errors are handled by the
  * relevant subsystems so the core interrupt code needs only concern
  * comprises the Peripherial block, the PCI block, the PCI MSI block and
  * the SLP.  The PCI interrupts and the SLP errors are handled by the
  * relevant subsystems so the core interrupt code needs only concern


@@ -41,11 +41,11 @@
  * IRQs directly connected to CPU
  */
 #define MSP_MIPS_INTBASE       0
  * IRQs directly connected to CPU
  */
 #define MSP_MIPS_INTBASE       0

-#define MSP_INT_SW0            0  /* IRQ for swint0,         C_SW0  */
-#define MSP_INT_SW1            1  /* IRQ for swint1,         C_SW1  */
-#define MSP_INT_MAC0           2  /* IRQ for MAC 0,          C_IRQ0 */
-#define MSP_INT_MAC1           3  /* IRQ for MAC 1,          C_IRQ1 */
-#define MSP_INT_C_IRQ2         4  /* Wired off,              C_IRQ2 */
+#define MSP_INT_SW0            0  /* IRQ for swint0,         C_SW0  */
+#define MSP_INT_SW1            1  /* IRQ for swint1,         C_SW1  */
+#define MSP_INT_MAC0           2  /* IRQ for MAC 0,          C_IRQ0 */
+#define MSP_INT_MAC1           3  /* IRQ for MAC 1,          C_IRQ1 */
+#define MSP_INT_C_IRQ2         4  /* Wired off,              C_IRQ2 */

 #define MSP_INT_VE             5  /* IRQ for Voice Engine,   C_IRQ3 */
 #define MSP_INT_SLP            6  /* IRQ for SLM block,      C_IRQ4 */
 #define MSP_INT_TIMER          7  /* IRQ for the MIPS timer, C_IRQ5 */
 #define MSP_INT_VE             5  /* IRQ for Voice Engine,   C_IRQ3 */
 #define MSP_INT_SLP            6  /* IRQ for SLM block,      C_IRQ4 */
 #define MSP_INT_TIMER          7  /* IRQ for the MIPS timer, C_IRQ5 */


@@ -57,85 +57,85 @@
  */
 #define MSP_SLP_INTBASE                (MSP_MIPS_INTBASE + 8)
 #define MSP_INT_EXT0           (MSP_SLP_INTBASE + 0)
  */
 #define MSP_SLP_INTBASE                (MSP_MIPS_INTBASE + 8)
 #define MSP_INT_EXT0           (MSP_SLP_INTBASE + 0)

-                                       /* External interrupt 0         */
+                                       /* External interrupt 0         */

 #define MSP_INT_EXT1           (MSP_SLP_INTBASE + 1)
 #define MSP_INT_EXT1           (MSP_SLP_INTBASE + 1)

-                                       /* External interrupt 1         */
+                                       /* External interrupt 1         */

 #define MSP_INT_EXT2           (MSP_SLP_INTBASE + 2)
 #define MSP_INT_EXT2           (MSP_SLP_INTBASE + 2)

-                                       /* External interrupt 2         */
+                                       /* External interrupt 2         */

 #define MSP_INT_EXT3           (MSP_SLP_INTBASE + 3)
 #define MSP_INT_EXT3           (MSP_SLP_INTBASE + 3)

-                                       /* External interrupt 3         */
-/* Reserved                                       4-7                  */
+                                       /* External interrupt 3         */
+/* Reserved                                       4-7                  */

 
 /*
  *************************************************************************
  * DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER *
 
 /*
  *************************************************************************
  * DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER *

- * Some MSP produces have this interrupt labelled as Voice and some are  *
- * SEC mbox ...                                                          *
+ * Some MSP produces have this interrupt labelled as Voice and some are         *
+ * SEC mbox ...                                                                 *

  *************************************************************************
  */
 #define MSP_INT_SLP_VE         (MSP_SLP_INTBASE + 8)
                                        /* Cascaded IRQ for Voice Engine*/
 #define MSP_INT_SLP_TDM                (MSP_SLP_INTBASE + 9)
  *************************************************************************
  */
 #define MSP_INT_SLP_VE         (MSP_SLP_INTBASE + 8)
                                        /* Cascaded IRQ for Voice Engine*/
 #define MSP_INT_SLP_TDM                (MSP_SLP_INTBASE + 9)

-                                       /* TDM interrupt                */
+                                       /* TDM interrupt                */

 #define MSP_INT_SLP_MAC0       (MSP_SLP_INTBASE + 10)
 #define MSP_INT_SLP_MAC0       (MSP_SLP_INTBASE + 10)

-                                       /* Cascaded IRQ for MAC 0       */
+                                       /* Cascaded IRQ for MAC 0       */

 #define MSP_INT_SLP_MAC1       (MSP_SLP_INTBASE + 11)
 #define MSP_INT_SLP_MAC1       (MSP_SLP_INTBASE + 11)

-                                       /* Cascaded IRQ for MAC 1       */
+                                       /* Cascaded IRQ for MAC 1       */

 #define MSP_INT_SEC            (MSP_SLP_INTBASE + 12)
 #define MSP_INT_SEC            (MSP_SLP_INTBASE + 12)

-                                       /* IRQ for security engine      */
-#define        MSP_INT_PER             (MSP_SLP_INTBASE + 13)
-                                       /* Peripheral interrupt         */
-#define        MSP_INT_TIMER0          (MSP_SLP_INTBASE + 14)
-                                       /* SLP timer 0                  */
-#define        MSP_INT_TIMER1          (MSP_SLP_INTBASE + 15)
-                                       /* SLP timer 1                  */
-#define        MSP_INT_TIMER2          (MSP_SLP_INTBASE + 16)
-                                       /* SLP timer 2                  */
-#define        MSP_INT_SLP_TIMER       (MSP_SLP_INTBASE + 17)
-                                       /* Cascaded MIPS timer          */
+                                       /* IRQ for security engine      */
+#define MSP_INT_PER            (MSP_SLP_INTBASE + 13)
+                                       /* Peripheral interrupt         */
+#define MSP_INT_TIMER0         (MSP_SLP_INTBASE + 14)
+                                       /* SLP timer 0                  */
+#define MSP_INT_TIMER1         (MSP_SLP_INTBASE + 15)
+                                       /* SLP timer 1                  */
+#define MSP_INT_TIMER2         (MSP_SLP_INTBASE + 16)
+                                       /* SLP timer 2                  */
+#define MSP_INT_SLP_TIMER      (MSP_SLP_INTBASE + 17)
+                                       /* Cascaded MIPS timer          */

 #define MSP_INT_BLKCP          (MSP_SLP_INTBASE + 18)
 #define MSP_INT_BLKCP          (MSP_SLP_INTBASE + 18)

-                                       /* Block Copy                   */
+                                       /* Block Copy                   */

 #define MSP_INT_UART0          (MSP_SLP_INTBASE + 19)
 #define MSP_INT_UART0          (MSP_SLP_INTBASE + 19)

-                                       /* UART 0                       */
+                                       /* UART 0                       */

 #define MSP_INT_PCI            (MSP_SLP_INTBASE + 20)
 #define MSP_INT_PCI            (MSP_SLP_INTBASE + 20)

-                                       /* PCI subsystem                */
+                                       /* PCI subsystem                */

 #define MSP_INT_PCI_DBELL      (MSP_SLP_INTBASE + 21)
 #define MSP_INT_PCI_DBELL      (MSP_SLP_INTBASE + 21)

-                                       /* PCI doorbell                 */
+                                       /* PCI doorbell                 */

 #define MSP_INT_PCI_MSI                (MSP_SLP_INTBASE + 22)
 #define MSP_INT_PCI_MSI                (MSP_SLP_INTBASE + 22)

-                                       /* PCI Message Signal           */
+                                       /* PCI Message Signal           */

 #define MSP_INT_PCI_BC0                (MSP_SLP_INTBASE + 23)
 #define MSP_INT_PCI_BC0                (MSP_SLP_INTBASE + 23)

-                                       /* PCI Block Copy 0             */
+                                       /* PCI Block Copy 0             */

 #define MSP_INT_PCI_BC1                (MSP_SLP_INTBASE + 24)
 #define MSP_INT_PCI_BC1                (MSP_SLP_INTBASE + 24)

-                                       /* PCI Block Copy 1             */
+                                       /* PCI Block Copy 1             */

 #define MSP_INT_SLP_ERR                (MSP_SLP_INTBASE + 25)
 #define MSP_INT_SLP_ERR                (MSP_SLP_INTBASE + 25)

-                                       /* SLP error condition          */
+                                       /* SLP error condition          */

 #define MSP_INT_MAC2           (MSP_SLP_INTBASE + 26)
 #define MSP_INT_MAC2           (MSP_SLP_INTBASE + 26)

-                                       /* IRQ for MAC2                 */
-/* Reserved                                       26-31                */
+                                       /* IRQ for MAC2                 */
+/* Reserved                                       26-31                */

 
 /*
  * IRQs cascaded on SLP PER interrupt (MSP_INT_PER)
  */
 #define MSP_PER_INTBASE                (MSP_SLP_INTBASE + 32)
 
 /*
  * IRQs cascaded on SLP PER interrupt (MSP_INT_PER)
  */
 #define MSP_PER_INTBASE                (MSP_SLP_INTBASE + 32)

-/* Reserved                                       0-1                  */
+/* Reserved                                       0-1                  */

 #define MSP_INT_UART1          (MSP_PER_INTBASE + 2)
 #define MSP_INT_UART1          (MSP_PER_INTBASE + 2)

-                                       /* UART 1                       */
-/* Reserved                                       3-5                  */
+                                       /* UART 1                       */
+/* Reserved                                       3-5                  */

 #define MSP_INT_2WIRE          (MSP_PER_INTBASE + 6)
 #define MSP_INT_2WIRE          (MSP_PER_INTBASE + 6)

-                                       /* 2-wire                       */
+                                       /* 2-wire                       */

 #define MSP_INT_TM0            (MSP_PER_INTBASE + 7)
                                        /* Peripheral timer block out 0 */
 #define MSP_INT_TM1            (MSP_PER_INTBASE + 8)
                                        /* Peripheral timer block out 1 */
 #define MSP_INT_TM0            (MSP_PER_INTBASE + 7)
                                        /* Peripheral timer block out 0 */
 #define MSP_INT_TM1            (MSP_PER_INTBASE + 8)
                                        /* Peripheral timer block out 1 */

-/* Reserved                                       9                    */
+/* Reserved                                       9                    */

 #define MSP_INT_SPRX           (MSP_PER_INTBASE + 10)
 #define MSP_INT_SPRX           (MSP_PER_INTBASE + 10)

-                                       /* SPI RX complete              */
+                                       /* SPI RX complete              */

 #define MSP_INT_SPTX           (MSP_PER_INTBASE + 11)
 #define MSP_INT_SPTX           (MSP_PER_INTBASE + 11)

-                                       /* SPI TX complete              */
+                                       /* SPI TX complete              */

 #define MSP_INT_GPIO           (MSP_PER_INTBASE + 12)
 #define MSP_INT_GPIO           (MSP_PER_INTBASE + 12)

-                                       /* GPIO                         */
+                                       /* GPIO                         */

 #define MSP_INT_PER_ERR                (MSP_PER_INTBASE + 13)
 #define MSP_INT_PER_ERR                (MSP_PER_INTBASE + 13)

-                                       /* Peripheral error             */
-/* Reserved                                       14-31                */
+                                       /* Peripheral error             */
+/* Reserved                                       14-31                */

 
 #endif /* !_MSP_SLP_INT_H */
 
 #endif /* !_MSP_SLP_INT_H */

diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h
index 4c9348df9df22cdad9812b832ff948c853d270e8..aa45e6a07126686834722959daaccdc4afe6a0c1 100644 (file)
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/msp_usb.h
@@ -40,7 +40,7 @@
 #define MSP_USB0_HS_END                (MSP_USB0_BASE + 0x401FF)
 
 /* Register spaces for USB host 1 */
 #define MSP_USB0_HS_END                (MSP_USB0_BASE + 0x401FF)
 
 /* Register spaces for USB host 1 */

-#define        MSP_USB1_MAB_START      (MSP_USB1_BASE + 0x0)
+#define MSP_USB1_MAB_START     (MSP_USB1_BASE + 0x0)

 #define MSP_USB1_MAB_END       (MSP_USB1_BASE + 0x17)
 #define MSP_USB1_ID_START      (MSP_USB1_BASE + 0x40000)
 #define MSP_USB1_ID_END                (MSP_USB1_BASE + 0x4008f)
 #define MSP_USB1_MAB_END       (MSP_USB1_BASE + 0x17)
 #define MSP_USB1_ID_START      (MSP_USB1_BASE + 0x40000)
 #define MSP_USB1_ID_END                (MSP_USB1_BASE + 0x4008f)

diff --git a/arch/mips/include/asm/pmc-sierra/msp71xx/war.h b/arch/mips/include/asm/pmc-sierra/msp71xx/war.h
index c74eb1657f5f51c52f4549cbcfc09cbcc9668c99..a60bf9dd14aeceeb89be9c8dd6a57e1c557f187a 100644 (file)
--- a/arch/mips/include/asm/pmc-sierra/msp71xx/war.h
+++ b/arch/mips/include/asm/pmc-sierra/msp71xx/war.h
@@ -21,9 +21,9 @@
 #define R10000_LLSC_WAR                        0
 #if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
        defined(CONFIG_PMC_MSP7120_FPGA)
 #define R10000_LLSC_WAR                        0
 #if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
        defined(CONFIG_PMC_MSP7120_FPGA)

-#define MIPS34K_MISSED_ITLB_WAR         1
+#define MIPS34K_MISSED_ITLB_WAR                1

 #else
 #else

-#define MIPS34K_MISSED_ITLB_WAR         0
+#define MIPS34K_MISSED_ITLB_WAR                0

 #endif
 
 #endif /* __ASM_MIPS_PMC_SIERRA_WAR_H */
 #endif
 
 #endif /* __ASM_MIPS_PMC_SIERRA_WAR_H */

diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index bd98b503f04c68fe070366aaa9d1a9d4606c9796..2a5fa7abb346b8633ddda81ff40766c0e2e47aef 100644 (file)
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -112,8 +112,8 @@ struct mips_fpu_struct {
 typedef __u32 dspreg_t;
 
 struct mips_dsp_state {
 typedef __u32 dspreg_t;
 
 struct mips_dsp_state {

-       dspreg_t        dspr[NUM_DSP_REGS];
-       unsigned int    dspcontrol;
+       dspreg_t        dspr[NUM_DSP_REGS];
+       unsigned int    dspcontrol;

 };
 
 #define INIT_CPUMASK { \
 };
 
 #define INIT_CPUMASK { \


@@ -137,46 +137,46 @@ union mips_watch_reg_state {
 
 struct octeon_cop2_state {
        /* DMFC2 rt, 0x0201 */
 
 struct octeon_cop2_state {
        /* DMFC2 rt, 0x0201 */

-       unsigned long   cop2_crc_iv;
+       unsigned long   cop2_crc_iv;

        /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
        /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */

-       unsigned long   cop2_crc_length;
+       unsigned long   cop2_crc_length;

        /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
        /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */

-       unsigned long   cop2_crc_poly;
+       unsigned long   cop2_crc_poly;

        /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
        /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */

-       unsigned long   cop2_llm_dat[2];
+       unsigned long   cop2_llm_dat[2];

        /* DMFC2 rt, 0x0084 */
        /* DMFC2 rt, 0x0084 */

-       unsigned long   cop2_3des_iv;
+       unsigned long   cop2_3des_iv;

        /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
        /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */

-       unsigned long   cop2_3des_key[3];
+       unsigned long   cop2_3des_key[3];

        /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
        /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */

-       unsigned long   cop2_3des_result;
+       unsigned long   cop2_3des_result;

        /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
        /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */

-       unsigned long   cop2_aes_inp0;
+       unsigned long   cop2_aes_inp0;

        /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
        /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */

-       unsigned long   cop2_aes_iv[2];
+       unsigned long   cop2_aes_iv[2];

        /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
         * rt, 0x0107 */
        /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
         * rt, 0x0107 */

-       unsigned long   cop2_aes_key[4];
+       unsigned long   cop2_aes_key[4];

        /* DMFC2 rt, 0x0110 */
        /* DMFC2 rt, 0x0110 */

-       unsigned long   cop2_aes_keylen;
+       unsigned long   cop2_aes_keylen;

        /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
        /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */

-       unsigned long   cop2_aes_result[2];
+       unsigned long   cop2_aes_result[2];

        /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
         * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
         * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
         * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
         * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
        /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
         * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
         * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
         * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
         * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */

-       unsigned long   cop2_hsh_datw[15];
+       unsigned long   cop2_hsh_datw[15];

        /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
         * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
         * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
        /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
         * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
         * 0x0256; DMFC2 rt, 0x0257 - Pass2 */

-       unsigned long   cop2_hsh_ivw[8];
+       unsigned long   cop2_hsh_ivw[8];

        /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
        /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */

-       unsigned long   cop2_gfm_mult[2];
+       unsigned long   cop2_gfm_mult[2];

        /* DMFC2 rt, 0x025E - Pass2 */
        /* DMFC2 rt, 0x025E - Pass2 */

-       unsigned long   cop2_gfm_poly;
+       unsigned long   cop2_gfm_poly;

        /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
        /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */

-       unsigned long   cop2_gfm_result[2];
+       unsigned long   cop2_gfm_result[2];

 };
 #define INIT_OCTEON_COP2 {0,}
 
 };
 #define INIT_OCTEON_COP2 {0,}
 


@@ -249,9 +249,9 @@ struct thread_struct {
 #endif /* CONFIG_CPU_CAVIUM_OCTEON */
 
 #define INIT_THREAD  {                                         \
 #endif /* CONFIG_CPU_CAVIUM_OCTEON */
 
 #define INIT_THREAD  {                                         \

-        /*                                                     \
-         * Saved main processor registers                      \
-         */                                                    \
+       /*                                                      \
+        * Saved main processor registers                       \
+        */                                                     \

        .reg16                  = 0,                            \
        .reg17                  = 0,                            \
        .reg18                  = 0,                            \
        .reg16                  = 0,                            \
        .reg17                  = 0,                            \
        .reg18                  = 0,                            \


@@ -332,7 +332,7 @@ unsigned long get_wchan(struct task_struct *p);
  * aborts compilation on some CPUs.  It's simply not possible to unwind
  * some CPU's stackframes.
  *
  * aborts compilation on some CPUs.  It's simply not possible to unwind
  * some CPU's stackframes.
  *

- * __builtin_return_address works only for non-leaf functions.  We avoid the
+ * __builtin_return_address works only for non-leaf functions. We avoid the

  * overhead of a function call by forcing the compiler to save the return
  * address register on the stack.
  */
  * overhead of a function call by forcing the compiler to save the return
  * address register on the stack.
  */

diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index 54ea47da59a120ba4350666eab4381b5776a7e47..a0b2650516ac9a2837a362f4c5768ce609767216 100644 (file)
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -22,10 +22,10 @@
  * for indexed cache operations.  Two issues here:
  *
  *  - The MIPS32 and MIPS64 specs permit an implementation to directly derive
  * for indexed cache operations.  Two issues here:
  *
  *  - The MIPS32 and MIPS64 specs permit an implementation to directly derive

- *    the index bits from the virtual address.  This breaks with tradition
- *    set by the R4000.  To keep unpleasant surprises from happening we pick
+ *    the index bits from the virtual address. This breaks with tradition
+ *    set by the R4000.         To keep unpleasant surprises from happening we pick

  *    an address in KSEG0 / CKSEG0.
  *    an address in KSEG0 / CKSEG0.

- *  - We need a properly sign extended address for 64-bit code.  To get away
+ *  - We need a properly sign extended address for 64-bit code.         To get away

  *    without ifdefs we let the compiler do it by a type cast.
  */
 #define INDEX_BASE     CKSEG0
  *    without ifdefs we let the compiler do it by a type cast.
  */
 #define INDEX_BASE     CKSEG0


@@ -347,7 +347,7 @@ static inline void blast_##pfx##cache##lsize(void)                  \
        unsigned long end = start + current_cpu_data.desc.waysize;      \
        unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit;     \
        unsigned long ws_end = current_cpu_data.desc.ways <<            \
        unsigned long end = start + current_cpu_data.desc.waysize;      \
        unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit;     \
        unsigned long ws_end = current_cpu_data.desc.ways <<            \

-                              current_cpu_data.desc.waybit;            \
+                              current_cpu_data.desc.waybit;            \

        unsigned long ws, addr;                                         \
                                                                        \
        __##pfx##flush_prologue                                         \
        unsigned long ws, addr;                                         \
                                                                        \
        __##pfx##flush_prologue                                         \


@@ -359,7 +359,7 @@ static inline void blast_##pfx##cache##lsize(void)                  \
        __##pfx##flush_epilogue                                         \
 }                                                                      \
                                                                        \
        __##pfx##flush_epilogue                                         \
 }                                                                      \
                                                                        \

-static inline void blast_##pfx##cache##lsize##_page(unsigned long page)        \
+static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \

 {                                                                      \
        unsigned long start = page;                                     \
        unsigned long end = page + PAGE_SIZE;                           \
 {                                                                      \
        unsigned long start = page;                                     \
        unsigned long end = page + PAGE_SIZE;                           \


@@ -381,7 +381,7 @@ static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page)
        unsigned long end = start + PAGE_SIZE;                          \
        unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit;     \
        unsigned long ws_end = current_cpu_data.desc.ways <<            \
        unsigned long end = start + PAGE_SIZE;                          \
        unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit;     \
        unsigned long ws_end = current_cpu_data.desc.ways <<            \

-                              current_cpu_data.desc.waybit;            \
+                              current_cpu_data.desc.waybit;            \

        unsigned long ws, addr;                                         \
                                                                        \
        __##pfx##flush_prologue                                         \
        unsigned long ws, addr;                                         \
                                                                        \
        __##pfx##flush_prologue                                         \

diff --git a/arch/mips/include/asm/regdef.h b/arch/mips/include/asm/regdef.h
index 785a5189b374df50babf8b719a72e29c2c633823..3c687df1d5150656bda1a18a485b7b8c9ee5cfb0 100644 (file)
--- a/arch/mips/include/asm/regdef.h
+++ b/arch/mips/include/asm/regdef.h
@@ -19,44 +19,44 @@
 /*
  * Symbolic register names for 32 bit ABI
  */
 /*
  * Symbolic register names for 32 bit ABI
  */

-#define zero    $0      /* wired zero */
-#define AT      $1      /* assembler temp  - uppercase because of ".set at" */
-#define v0      $2      /* return value */
-#define v1      $3
-#define a0      $4      /* argument registers */
-#define a1      $5
-#define a2      $6
-#define a3      $7
-#define t0      $8      /* caller saved */
-#define t1      $9
-#define t2      $10
-#define t3      $11
-#define t4      $12
+#define zero   $0      /* wired zero */
+#define AT     $1      /* assembler temp  - uppercase because of ".set at" */
+#define v0     $2      /* return value */
+#define v1     $3
+#define a0     $4      /* argument registers */
+#define a1     $5
+#define a2     $6
+#define a3     $7
+#define t0     $8      /* caller saved */
+#define t1     $9
+#define t2     $10
+#define t3     $11
+#define t4     $12

 #define ta0    $12
 #define ta0    $12

-#define t5      $13
+#define t5     $13

 #define ta1    $13
 #define ta1    $13

-#define t6      $14
+#define t6     $14

 #define ta2    $14
 #define ta2    $14

-#define t7      $15
+#define t7     $15

 #define ta3    $15
 #define ta3    $15

-#define s0      $16     /* callee saved */
-#define s1      $17
-#define s2      $18
-#define s3      $19
-#define s4      $20
-#define s5      $21
-#define s6      $22
-#define s7      $23
-#define t8      $24     /* caller saved */
-#define t9      $25
-#define jp      $25     /* PIC jump register */
-#define k0      $26     /* kernel scratch */
-#define k1      $27
-#define gp      $28     /* global pointer */
-#define sp      $29     /* stack pointer */
-#define fp      $30     /* frame pointer */
+#define s0     $16     /* callee saved */
+#define s1     $17
+#define s2     $18
+#define s3     $19
+#define s4     $20
+#define s5     $21
+#define s6     $22
+#define s7     $23
+#define t8     $24     /* caller saved */
+#define t9     $25
+#define jp     $25     /* PIC jump register */
+#define k0     $26     /* kernel scratch */
+#define k1     $27
+#define gp     $28     /* global pointer */
+#define sp     $29     /* stack pointer */
+#define fp     $30     /* frame pointer */

 #define s8     $30     /* same like fp! */
 #define s8     $30     /* same like fp! */

-#define ra      $31     /* return address */
+#define ra     $31     /* return address */

 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 

diff --git a/arch/mips/include/asm/rtlx.h b/arch/mips/include/asm/rtlx.h
index 4ca3063ed2ce9330cd3c87ef3b1da6fb001927d5..90985b61dbd9a2c83cbf7acaa43d253521525c91 100644 (file)
--- a/arch/mips/include/asm/rtlx.h
+++ b/arch/mips/include/asm/rtlx.h
@@ -38,7 +38,7 @@ enum rtlx_state {
 #define RTLX_BUFFER_SIZE 2048
 
 /* each channel supports read and write.
 #define RTLX_BUFFER_SIZE 2048
 
 /* each channel supports read and write.

-   linux (vpe0) reads lx_buffer  and writes rt_buffer
+   linux (vpe0) reads lx_buffer         and writes rt_buffer

    SP (vpe1) reads rt_buffer and writes lx_buffer
 */
 struct rtlx_channel {
    SP (vpe1) reads rt_buffer and writes lx_buffer
 */
 struct rtlx_channel {

diff --git a/arch/mips/include/asm/seccomp.h b/arch/mips/include/asm/seccomp.h
index ae6306ebdcad51f86d30e77bf2ce0a282235e3a7..f29c75cf83c67889c870634992f201728d9314f8 100644 (file)
--- a/arch/mips/include/asm/seccomp.h
+++ b/arch/mips/include/asm/seccomp.h
@@ -10,7 +10,7 @@
 /*
  * Kludge alert:
  *
 /*
  * Kludge alert:
  *

- * The generic seccomp code currently allows only a single compat ABI.  Until
+ * The generic seccomp code currently allows only a single compat ABI. Until

  * this is fixed we priorize O32 as the compat ABI over N32.
  */
 #ifdef CONFIG_MIPS32_O32
  * this is fixed we priorize O32 as the compat ABI over N32.
  */
 #ifdef CONFIG_MIPS32_O32

diff --git a/arch/mips/include/asm/sgi/gio.h b/arch/mips/include/asm/sgi/gio.h
index 889cf028c95d4b2e3e4c39918c01a19bcb2462a3..24be2b425be84129669cc6ef05f08bae1bfc841f 100644 (file)
--- a/arch/mips/include/asm/sgi/gio.h
+++ b/arch/mips/include/asm/sgi/gio.h
@@ -18,18 +18,18 @@
  * three physical connectors, but only two slots, GFX and EXP0.
  *
  * There is 10MB of GIO address space for GIO64 slot devices
  * three physical connectors, but only two slots, GFX and EXP0.
  *
  * There is 10MB of GIO address space for GIO64 slot devices

- * slot#   slot type address range            size
+ * slot#   slot type address range           size

  * -----   --------- ----------------------- -----
  * -----   --------- ----------------------- -----

- *   0     GFX       0x1f000000 - 0x1f3fffff   4MB
- *   1     EXP0      0x1f400000 - 0x1f5fffff   2MB
- *   2     EXP1      0x1f600000 - 0x1f9fffff   4MB
+ *   0    GFX       0x1f000000 - 0x1f3fffff   4MB
+ *   1    EXP0      0x1f400000 - 0x1f5fffff   2MB
+ *   2    EXP1      0x1f600000 - 0x1f9fffff   4MB

  *
  * There are un-slotted devices, HPC, I/O and misc devices, which are grouped
  * into the HPC address space.
  *
  * There are un-slotted devices, HPC, I/O and misc devices, which are grouped
  * into the HPC address space.

- *   -     MISC      0x1fb00000 - 0x1fbfffff   1MB
+ *   -    MISC      0x1fb00000 - 0x1fbfffff   1MB

  *
  * Following space is reserved and unused
  *
  * Following space is reserved and unused

- *   -     RESERVED  0x18000000 - 0x1effffff 112MB
+ *   -    RESERVED  0x18000000 - 0x1effffff 112MB

  *
  * GIO bus IDs
  *
  *
  * GIO bus IDs
  *


@@ -39,10 +39,10 @@
  * the slot undefined.
  *
  * 32-bit IDs are divided into
  * the slot undefined.
  *
  * 32-bit IDs are divided into

- *     bits 0:6        the product ID; ranges from 0x00 to 0x7F.
+ *     bits 0:6        the product ID; ranges from 0x00 to 0x7F.

  *     bit 7           0=GIO Product ID is 8 bits wide
  *                     1=GIO Product ID is 32 bits wide.
  *     bit 7           0=GIO Product ID is 8 bits wide
  *                     1=GIO Product ID is 32 bits wide.

- *     bits 8:15       manufacturer version for the product.
+ *     bits 8:15       manufacturer version for the product.

  *     bit 16          0=GIO32 and GIO32-bis, 1=GIO64.
  *     bit 17          0=no ROM present
  *                     1=ROM present on this board AND next three words
  *     bit 16          0=GIO32 and GIO32-bis, 1=GIO64.
  *     bit 17          0=no ROM present
  *                     1=ROM present on this board AND next three words

diff --git a/arch/mips/include/asm/sgi/hpc3.h b/arch/mips/include/asm/sgi/hpc3.h
index c4729f53191921183ee8e701184a0a5fff6a064f..59920b3459420192b3f34185bc4293b763293418 100644 (file)
--- a/arch/mips/include/asm/sgi/hpc3.h
+++ b/arch/mips/include/asm/sgi/hpc3.h
@@ -65,39 +65,39 @@ struct hpc3_scsiregs {
        u32 _unused0[0x1000/4 - 2];     /* padding */
        volatile u32 bcd;       /* byte count info */
 #define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */
        u32 _unused0[0x1000/4 - 2];     /* padding */
        volatile u32 bcd;       /* byte count info */
 #define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */

-#define HPC3_SBCD_XIE     0x00004000 /* Send IRQ when done with cur buf */
-#define HPC3_SBCD_EOX     0x00008000 /* Indicates this is last buf in chain */
+#define HPC3_SBCD_XIE    0x00004000 /* Send IRQ when done with cur buf */
+#define HPC3_SBCD_EOX    0x00008000 /* Indicates this is last buf in chain */

 
        volatile u32 ctrl;    /* control register */
 
        volatile u32 ctrl;    /* control register */

-#define HPC3_SCTRL_IRQ    0x01 /* IRQ asserted, either dma done or parity */
+#define HPC3_SCTRL_IRQ   0x01 /* IRQ asserted, either dma done or parity */

 #define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
 #define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */

-#define HPC3_SCTRL_DIR    0x04 /* DMA direction, 1=dev2mem 0=mem2dev */
+#define HPC3_SCTRL_DIR   0x04 /* DMA direction, 1=dev2mem 0=mem2dev */

 #define HPC3_SCTRL_FLUSH  0x08 /* Tells HPC3 to flush scsi fifos */
 #define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */
 #define HPC3_SCTRL_AMASK  0x20 /* DMA active inhibits PIO */
 #define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
 #define HPC3_SCTRL_FLUSH  0x08 /* Tells HPC3 to flush scsi fifos */
 #define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */
 #define HPC3_SCTRL_AMASK  0x20 /* DMA active inhibits PIO */
 #define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */

-#define HPC3_SCTRL_PERR   0x80 /* Bad parity on HPC3 iface to scsi controller */
+#define HPC3_SCTRL_PERR          0x80 /* Bad parity on HPC3 iface to scsi controller */

 
        volatile u32 gfptr;     /* current GIO fifo ptr */
        volatile u32 dfptr;     /* current device fifo ptr */
        volatile u32 dconfig;   /* DMA configuration register */
 #define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */
 
        volatile u32 gfptr;     /* current GIO fifo ptr */
        volatile u32 dfptr;     /* current device fifo ptr */
        volatile u32 dconfig;   /* DMA configuration register */
 #define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */

-#define HPC3_SDCFG_D1   0x00006 /* Cycles to spend in D1 state */
-#define HPC3_SDCFG_D2   0x00038 /* Cycles to spend in D2 state */
-#define HPC3_SDCFG_D3   0x001c0 /* Cycles to spend in D3 state */
+#define HPC3_SDCFG_D1  0x00006 /* Cycles to spend in D1 state */
+#define HPC3_SDCFG_D2  0x00038 /* Cycles to spend in D2 state */
+#define HPC3_SDCFG_D3  0x001c0 /* Cycles to spend in D3 state */

 #define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */
 #define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */

-#define HPC3_SDCFG_HW   0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
+#define HPC3_SDCFG_HW  0x01000 /* Enable 16-bit halfword DMA accesses to scsi */

 #define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */
 #define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */
 #define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */
 #define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */
 
        volatile u32 pconfig;   /* PIO configuration register */
 #define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */
 #define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */
 #define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */
 #define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */
 
        volatile u32 pconfig;   /* PIO configuration register */

-#define HPC3_SPCFG_P3   0x0003 /* Cycles to spend in P3 state */
-#define HPC3_SPCFG_P2W  0x001c /* Cycles to spend in P2 state for writes */
-#define HPC3_SPCFG_P2R  0x01e0 /* Cycles to spend in P2 state for reads */
-#define HPC3_SPCFG_P1   0x0e00 /* Cycles to spend in P1 state */
-#define HPC3_SPCFG_HW   0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
+#define HPC3_SPCFG_P3  0x0003 /* Cycles to spend in P3 state */
+#define HPC3_SPCFG_P2W 0x001c /* Cycles to spend in P2 state for writes */
+#define HPC3_SPCFG_P2R 0x01e0 /* Cycles to spend in P2 state for reads */
+#define HPC3_SPCFG_P1  0x0e00 /* Cycles to spend in P1 state */
+#define HPC3_SPCFG_HW  0x1000 /* Enable 16-bit halfword PIO accesses to scsi */

 #define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */
 #define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
 #define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */
 #define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */
 #define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
 #define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */


@@ -108,13 +108,13 @@ struct hpc3_scsiregs {
 /* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */
 struct hpc3_ethregs {
        /* Receiver registers. */
 /* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */
 struct hpc3_ethregs {
        /* Receiver registers. */

-       volatile u32 rx_cbptr;   /* current dma buffer ptr, diagnostic use only */
-       volatile u32 rx_ndptr;   /* next dma descriptor ptr */
+       volatile u32 rx_cbptr;   /* current dma buffer ptr, diagnostic use only */
+       volatile u32 rx_ndptr;   /* next dma descriptor ptr */

        u32 _unused0[0x1000/4 - 2];     /* padding */
        volatile u32 rx_bcd;    /* byte count info */
 #define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */
        u32 _unused0[0x1000/4 - 2];     /* padding */
        volatile u32 rx_bcd;    /* byte count info */
 #define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */

-#define HPC3_ERXBCD_XIE     0x20000000 /* HPC3 interrupts cpu at end of this buf */
-#define HPC3_ERXBCD_EOX     0x80000000 /* flags this as end of descriptor chain */
+#define HPC3_ERXBCD_XIE            0x20000000 /* HPC3 interrupts cpu at end of this buf */
+#define HPC3_ERXBCD_EOX            0x80000000 /* flags this as end of descriptor chain */

 
        volatile u32 rx_ctrl;   /* control register */
 #define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */
 
        volatile u32 rx_ctrl;   /* control register */
 #define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */


@@ -131,23 +131,23 @@ struct hpc3_ethregs {
        volatile u32 reset;     /* reset register */
 #define HPC3_ERST_CRESET 0x1   /* Reset dma channel and external controller */
 #define HPC3_ERST_CLRIRQ 0x2   /* Clear channel interrupt */
        volatile u32 reset;     /* reset register */
 #define HPC3_ERST_CRESET 0x1   /* Reset dma channel and external controller */
 #define HPC3_ERST_CLRIRQ 0x2   /* Clear channel interrupt */

-#define HPC3_ERST_LBACK  0x4   /* Enable diagnostic loopback mode of Seeq8003 */
+#define HPC3_ERST_LBACK         0x4    /* Enable diagnostic loopback mode of Seeq8003 */

 
 

-       volatile u32 dconfig;    /* DMA configuration register */
-#define HPC3_EDCFG_D1    0x0000f /* Cycles to spend in D1 state for PIO */
-#define HPC3_EDCFG_D2    0x000f0 /* Cycles to spend in D2 state for PIO */
-#define HPC3_EDCFG_D3    0x00f00 /* Cycles to spend in D3 state for PIO */
+       volatile u32 dconfig;    /* DMA configuration register */
+#define HPC3_EDCFG_D1   0x0000f /* Cycles to spend in D1 state for PIO */
+#define HPC3_EDCFG_D2   0x000f0 /* Cycles to spend in D2 state for PIO */
+#define HPC3_EDCFG_D3   0x00f00 /* Cycles to spend in D3 state for PIO */

 #define HPC3_EDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
 #define HPC3_EDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
 #define HPC3_EDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
 #define HPC3_EDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */

-#define HPC3_EDCFG_FEOP  0x04000 /* Bad packet marker timeout enable */
-#define HPC3_EDCFG_FIRQ  0x08000 /* Another bad packet timeout enable */
-#define HPC3_EDCFG_PTO   0x30000 /* Programmed timeout value for above two */
+#define HPC3_EDCFG_FEOP         0x04000 /* Bad packet marker timeout enable */
+#define HPC3_EDCFG_FIRQ         0x08000 /* Another bad packet timeout enable */
+#define HPC3_EDCFG_PTO  0x30000 /* Programmed timeout value for above two */

 
 

-       volatile u32 pconfig;   /* PIO configuration register */
-#define HPC3_EPCFG_P1    0x000f /* Cycles to spend in P1 state for PIO */
-#define HPC3_EPCFG_P2    0x00f0 /* Cycles to spend in P2 state for PIO */
-#define HPC3_EPCFG_P3    0x0f00 /* Cycles to spend in P3 state for PIO */
-#define HPC3_EPCFG_TST   0x1000 /* Diagnistic ram test feature bit */
+       volatile u32 pconfig;   /* PIO configuration register */
+#define HPC3_EPCFG_P1   0x000f /* Cycles to spend in P1 state for PIO */
+#define HPC3_EPCFG_P2   0x00f0 /* Cycles to spend in P2 state for PIO */
+#define HPC3_EPCFG_P3   0x0f00 /* Cycles to spend in P3 state for PIO */
+#define HPC3_EPCFG_TST  0x1000 /* Diagnistic ram test feature bit */

 
        u32 _unused2[0x1000/4 - 8];     /* padding */
 
 
        u32 _unused2[0x1000/4 - 8];     /* padding */
 


@@ -158,9 +158,9 @@ struct hpc3_ethregs {
        volatile u32 tx_bcd;            /* byte count info */
 #define HPC3_ETXBCD_BCNTMSK 0x00003fff /* bytes to be read from memory */
 #define HPC3_ETXBCD_ESAMP   0x10000000 /* if set, too late to add descriptor */
        volatile u32 tx_bcd;            /* byte count info */
 #define HPC3_ETXBCD_BCNTMSK 0x00003fff /* bytes to be read from memory */
 #define HPC3_ETXBCD_ESAMP   0x10000000 /* if set, too late to add descriptor */

-#define HPC3_ETXBCD_XIE     0x20000000 /* Interrupt cpu at end of cur desc */
-#define HPC3_ETXBCD_EOP     0x40000000 /* Last byte of cur buf is end of packet */
-#define HPC3_ETXBCD_EOX     0x80000000 /* This buf is the end of desc chain */
+#define HPC3_ETXBCD_XIE            0x20000000  /* Interrupt cpu at end of cur desc */
+#define HPC3_ETXBCD_EOP            0x40000000  /* Last byte of cur buf is end of packet */
+#define HPC3_ETXBCD_EOX            0x80000000  /* This buf is the end of desc chain */

 
        volatile u32 tx_ctrl;           /* control register */
 #define HPC3_ETXCTRL_STAT30 0x0000000f /* Rdonly copy of seeq tx stat reg */
 
        volatile u32 tx_ctrl;           /* control register */
 #define HPC3_ETXCTRL_STAT30 0x0000000f /* Rdonly copy of seeq tx stat reg */


@@ -215,10 +215,10 @@ struct hpc3_regs {
 
        volatile u32 istat1;            /* Irq status, only bits <9:5> reliable. */
        volatile u32 bestat;            /* Bus error interrupt status reg. */
 
        volatile u32 istat1;            /* Irq status, only bits <9:5> reliable. */
        volatile u32 bestat;            /* Bus error interrupt status reg. */

-#define HPC3_BESTAT_BLMASK     0x000ff /* Bus lane where bad parity occurred */
-#define HPC3_BESTAT_CTYPE      0x00100 /* Bus cycle type, 0=PIO 1=DMA */
+#define HPC3_BESTAT_BLMASK     0x000ff /* Bus lane where bad parity occurred */
+#define HPC3_BESTAT_CTYPE      0x00100 /* Bus cycle type, 0=PIO 1=DMA */

 #define HPC3_BESTAT_PIDSHIFT   9
 #define HPC3_BESTAT_PIDSHIFT   9

-#define HPC3_BESTAT_PIDMASK    0x3f700 /* DMA channel parity identifier */
+#define HPC3_BESTAT_PIDMASK    0x3f700 /* DMA channel parity identifier */

 
        u32 _unused1[0x14000/4 - 5];    /* padding */
 
 
        u32 _unused1[0x14000/4 - 5];    /* padding */
 


@@ -259,7 +259,7 @@ struct hpc3_regs {
 #define HPC3_DMACFG_RTIME              0x00200000
        /* 5 bit burst count for DMA device */
 #define HPC3_DMACFG_BURST_MASK         0x07c00000
 #define HPC3_DMACFG_RTIME              0x00200000
        /* 5 bit burst count for DMA device */
 #define HPC3_DMACFG_BURST_MASK         0x07c00000

-#define HPC3_DMACFG_BURST_SHIFT        22
+#define HPC3_DMACFG_BURST_SHIFT 22

        /* Use live pbus_dreq unsynchronized signal */
 #define HPC3_DMACFG_DRQLIVE            0x08000000
        volatile u32 pbus_piocfg[16][64];
        /* Use live pbus_dreq unsynchronized signal */
 #define HPC3_DMACFG_DRQLIVE            0x08000000
        volatile u32 pbus_piocfg[16][64];


@@ -288,20 +288,20 @@ struct hpc3_regs {
 
        /* PBUS PROM control regs. */
        volatile u32 pbus_promwe;       /* PROM write enable register */
 
        /* PBUS PROM control regs. */
        volatile u32 pbus_promwe;       /* PROM write enable register */

-#define HPC3_PROM_WENAB        0x1     /* Enable writes to the PROM */
+#define HPC3_PROM_WENAB 0x1    /* Enable writes to the PROM */

 
        u32 _unused5[0x0800/4 - 1];
        volatile u32 pbus_promswap;     /* Chip select swap reg */
 #define HPC3_PROM_SWAP 0x1     /* invert GIO addr bit to select prom0 or prom1 */
 
        u32 _unused6[0x0800/4 - 1];
 
        u32 _unused5[0x0800/4 - 1];
        volatile u32 pbus_promswap;     /* Chip select swap reg */
 #define HPC3_PROM_SWAP 0x1     /* invert GIO addr bit to select prom0 or prom1 */
 
        u32 _unused6[0x0800/4 - 1];

-       volatile u32 pbus_gout; /* PROM general purpose output reg */
+       volatile u32 pbus_gout; /* PROM general purpose output reg */

 #define HPC3_PROM_STAT 0x1     /* General purpose status bit in gout */
 
        u32 _unused7[0x1000/4 - 1];
        volatile u32 rtcregs[14];       /* Dallas clock registers */
        u32 _unused8[50];
 #define HPC3_PROM_STAT 0x1     /* General purpose status bit in gout */
 
        u32 _unused7[0x1000/4 - 1];
        volatile u32 rtcregs[14];       /* Dallas clock registers */
        u32 _unused8[50];

-       volatile u32 bbram[8192-50-14]; /* Battery backed ram */
+       volatile u32 bbram[8192-50-14]; /* Battery backed ram */

 };
 
 /*
 };
 
 /*

diff --git a/arch/mips/include/asm/sgi/ioc.h b/arch/mips/include/asm/sgi/ioc.h
index 380347b648e2fdda38239a6a1152e73ba876bdc4..53c6b1ca6860755556f6ef43757e665410cc5bf3 100644 (file)
--- a/arch/mips/include/asm/sgi/ioc.h
+++ b/arch/mips/include/asm/sgi/ioc.h
@@ -138,7 +138,7 @@ struct sgioc_regs {
        u8 _sysid[3];
        volatile u8 sysid;
 #define SGIOC_SYSID_FULLHOUSE  0x01
        u8 _sysid[3];
        volatile u8 sysid;
 #define SGIOC_SYSID_FULLHOUSE  0x01

-#define SGIOC_SYSID_BOARDREV(x)        (((x) & 0x1e) >> 1)
+#define SGIOC_SYSID_BOARDREV(x) (((x) & 0x1e) >> 1)

 #define SGIOC_SYSID_CHIPREV(x) (((x) & 0xe0) >> 5)
        u32 _unused2;
        u8 _read[3];
 #define SGIOC_SYSID_CHIPREV(x) (((x) & 0xe0) >> 5)
        u32 _unused2;
        u8 _read[3];


@@ -150,7 +150,7 @@ struct sgioc_regs {
 #define SGIOC_DMASEL_ISDNB     0x01    /* enable isdn B */
 #define SGIOC_DMASEL_ISDNA     0x02    /* enable isdn A */
 #define SGIOC_DMASEL_PPORT     0x04    /* use parallel DMA */
 #define SGIOC_DMASEL_ISDNB     0x01    /* enable isdn B */
 #define SGIOC_DMASEL_ISDNA     0x02    /* enable isdn A */
 #define SGIOC_DMASEL_PPORT     0x04    /* use parallel DMA */

-#define SGIOC_DMASEL_SCLK667MHZ        0x10    /* use 6.67MHZ serial clock */
+#define SGIOC_DMASEL_SCLK667MHZ 0x10   /* use 6.67MHZ serial clock */

 #define SGIOC_DMASEL_SCLKEXT   0x20    /* use external serial clock */
        u32 _unused4;
        u8 _reset[3];
 #define SGIOC_DMASEL_SCLKEXT   0x20    /* use external serial clock */
        u32 _unused4;
        u8 _reset[3];

diff --git a/arch/mips/include/asm/sgi/ip22.h b/arch/mips/include/asm/sgi/ip22.h
index c0501f91719b93a6a82db3fa082243eb500b9ffe..8db1a3588cf274584462c673e963ba9cf8b95f4c 100644 (file)
--- a/arch/mips/include/asm/sgi/ip22.h
+++ b/arch/mips/include/asm/sgi/ip22.h
@@ -38,8 +38,8 @@
 
 #define SGI_SOFT_0_IRQ SGINT_CPU + 0
 #define SGI_SOFT_1_IRQ SGINT_CPU + 1
 
 #define SGI_SOFT_0_IRQ SGINT_CPU + 0
 #define SGI_SOFT_1_IRQ SGINT_CPU + 1

-#define SGI_LOCAL_0_IRQ        SGINT_CPU + 2
-#define SGI_LOCAL_1_IRQ        SGINT_CPU + 3
+#define SGI_LOCAL_0_IRQ SGINT_CPU + 2
+#define SGI_LOCAL_1_IRQ SGINT_CPU + 3

 #define SGI_8254_0_IRQ SGINT_CPU + 4
 #define SGI_8254_1_IRQ SGINT_CPU + 5
 #define SGI_BUSERR_IRQ SGINT_CPU + 6
 #define SGI_8254_0_IRQ SGINT_CPU + 4
 #define SGI_8254_1_IRQ SGINT_CPU + 5
 #define SGI_BUSERR_IRQ SGINT_CPU + 6


@@ -51,7 +51,7 @@
 #define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2        /* 2nd onboard WD93 */
 #define SGI_ENET_IRQ   SGINT_LOCAL0 + 3        /* onboard ethernet */
 #define SGI_MCDMA_IRQ  SGINT_LOCAL0 + 4        /* MC DMA done */
 #define SGI_WD93_1_IRQ SGINT_LOCAL0 + 2        /* 2nd onboard WD93 */
 #define SGI_ENET_IRQ   SGINT_LOCAL0 + 3        /* onboard ethernet */
 #define SGI_MCDMA_IRQ  SGINT_LOCAL0 + 4        /* MC DMA done */

-#define SGI_PARPORT_IRQ        SGINT_LOCAL0 + 5        /* Parallel port */
+#define SGI_PARPORT_IRQ SGINT_LOCAL0 + 5       /* Parallel port */

 #define SGI_GIO_1_IRQ  SGINT_LOCAL0 + 6        /* GE / GIO-1 / 2nd-HPC */
 #define SGI_MAP_0_IRQ  SGINT_LOCAL0 + 7        /* Mappable interrupt 0 */
 
 #define SGI_GIO_1_IRQ  SGINT_LOCAL0 + 6        /* GE / GIO-1 / 2nd-HPC */
 #define SGI_MAP_0_IRQ  SGINT_LOCAL0 + 7        /* Mappable interrupt 0 */
 

diff --git a/arch/mips/include/asm/sgi/mc.h b/arch/mips/include/asm/sgi/mc.h
index 1576c2394de807608abee5caf6fba3b97f761fce..3a070cec97e7d7be66f21cdb6a1b43c437ed632b 100644 (file)
--- a/arch/mips/include/asm/sgi/mc.h
+++ b/arch/mips/include/asm/sgi/mc.h
@@ -29,10 +29,10 @@ struct sgimc_regs {
 #define SGIMC_CCTRL0_IENAB     0x00002000 /* Allow interrupts from MC */
 #define SGIMC_CCTRL0_ESNOOP    0x00004000 /* Snooping I/O enable */
 #define SGIMC_CCTRL0_EPROMWR   0x00008000 /* Prom writes from cpu enable */
 #define SGIMC_CCTRL0_IENAB     0x00002000 /* Allow interrupts from MC */
 #define SGIMC_CCTRL0_ESNOOP    0x00004000 /* Snooping I/O enable */
 #define SGIMC_CCTRL0_EPROMWR   0x00008000 /* Prom writes from cpu enable */

-#define SGIMC_CCTRL0_WRESETPMEM        0x00010000 /* Perform warm reset, preserves mem */
+#define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */

 #define SGIMC_CCTRL0_LENDIAN   0x00020000 /* Put MC in little-endian mode */
 #define SGIMC_CCTRL0_LENDIAN   0x00020000 /* Put MC in little-endian mode */

-#define SGIMC_CCTRL0_WRESETDMEM        0x00040000 /* Warm reset, destroys mem contents */
-#define SGIMC_CCTRL0_CMEMBADPAR        0x02000000 /* Generate bad perr from cpu to mem */
+#define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */
+#define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */

 #define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */
 #define SGIMC_CCTRL0_GIOBTOB   0x08000000 /* Allow GIO back to back writes */
        u32 _unused1;
 #define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */
 #define SGIMC_CCTRL0_GIOBTOB   0x08000000 /* Allow GIO back to back writes */
        u32 _unused1;


@@ -40,13 +40,13 @@ struct sgimc_regs {
 #define SGIMC_CCTRL1_EGIOTIMEO 0x00000010 /* GIO bus timeout enable */
 #define SGIMC_CCTRL1_FIXEDEHPC 0x00001000 /* Fixed HPC endianness */
 #define SGIMC_CCTRL1_LITTLEHPC 0x00002000 /* Little endian HPC */
 #define SGIMC_CCTRL1_EGIOTIMEO 0x00000010 /* GIO bus timeout enable */
 #define SGIMC_CCTRL1_FIXEDEHPC 0x00001000 /* Fixed HPC endianness */
 #define SGIMC_CCTRL1_LITTLEHPC 0x00002000 /* Little endian HPC */

-#define SGIMC_CCTRL1_FIXEDEEXP0        0x00004000 /* Fixed EXP0 endianness */
-#define SGIMC_CCTRL1_LITTLEEXP0        0x00008000 /* Little endian EXP0 */
-#define SGIMC_CCTRL1_FIXEDEEXP1        0x00010000 /* Fixed EXP1 endianness */
-#define SGIMC_CCTRL1_LITTLEEXP1        0x00020000 /* Little endian EXP1 */
+#define SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */
+#define SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */
+#define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */
+#define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */

 
        u32 _unused2;
 
        u32 _unused2;

-       volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */
+       volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */

 
        u32 _unused3;
        volatile u32 systemid;  /* MC system ID register, readonly */
 
        u32 _unused3;
        volatile u32 systemid;  /* MC system ID register, readonly */


@@ -81,11 +81,11 @@ struct sgimc_regs {
 #define SGIMC_GIOPAR_RTIMEGFX  0x00000040 /* GFX device has realtime attr */
 #define SGIMC_GIOPAR_RTIMEEXP0 0x00000080 /* EXP(slot0) has realtime attr */
 #define SGIMC_GIOPAR_RTIMEEXP1 0x00000100 /* EXP(slot1) has realtime attr */
 #define SGIMC_GIOPAR_RTIMEGFX  0x00000040 /* GFX device has realtime attr */
 #define SGIMC_GIOPAR_RTIMEEXP0 0x00000080 /* EXP(slot0) has realtime attr */
 #define SGIMC_GIOPAR_RTIMEEXP1 0x00000100 /* EXP(slot1) has realtime attr */

-#define SGIMC_GIOPAR_MASTEREISA        0x00000200 /* EISA bus can act as bus master */
+#define SGIMC_GIOPAR_MASTEREISA 0x00000200 /* EISA bus can act as bus master */

 #define SGIMC_GIOPAR_ONEBUS    0x00000400 /* Exists one GIO64 pipelined bus */
 #define SGIMC_GIOPAR_MASTERGFX 0x00000800 /* GFX can act as a bus master */
 #define SGIMC_GIOPAR_ONEBUS    0x00000400 /* Exists one GIO64 pipelined bus */
 #define SGIMC_GIOPAR_MASTERGFX 0x00000800 /* GFX can act as a bus master */

-#define SGIMC_GIOPAR_MASTEREXP0        0x00001000 /* EXP(slot0) can bus master */
-#define SGIMC_GIOPAR_MASTEREXP1        0x00002000 /* EXP(slot1) can bus master */
+#define SGIMC_GIOPAR_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */
+#define SGIMC_GIOPAR_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */

 #define SGIMC_GIOPAR_PLINEEXP0 0x00004000 /* EXP(slot0) has pipeline attr */
 #define SGIMC_GIOPAR_PLINEEXP1 0x00008000 /* EXP(slot1) has pipeline attr */
 
 #define SGIMC_GIOPAR_PLINEEXP0 0x00004000 /* EXP(slot0) has pipeline attr */
 #define SGIMC_GIOPAR_PLINEEXP1 0x00008000 /* EXP(slot1) has pipeline attr */
 


@@ -107,9 +107,9 @@ struct sgimc_regs {
 #define SGIMC_MCONFIG_SBANKS   0x00004000 /* Number of subbanks */
 
        u32 _unused13;
 #define SGIMC_MCONFIG_SBANKS   0x00004000 /* Number of subbanks */
 
        u32 _unused13;

-       volatile u32 cmacc;        /* Mem access config for CPU */
+       volatile u32 cmacc;        /* Mem access config for CPU */

        u32 _unused14;
        u32 _unused14;

-       volatile u32 gmacc;        /* Mem access config for GIO */
+       volatile u32 gmacc;        /* Mem access config for GIO */

 
        /* This define applies to both cmacc and gmacc registers above. */
 #define SGIMC_MACC_ALIASBIG    0x20000000 /* 512MB home for alias */
 
        /* This define applies to both cmacc and gmacc registers above. */
 #define SGIMC_MACC_ALIASBIG    0x20000000 /* 512MB home for alias */

diff --git a/arch/mips/include/asm/sgi/pi1.h b/arch/mips/include/asm/sgi/pi1.h
index c9506915dc5c0d924611b47fe9592574e855071f..96b1a0771ec3e339d5b027ce84c5095214259e0e 100644 (file)
--- a/arch/mips/include/asm/sgi/pi1.h
+++ b/arch/mips/include/asm/sgi/pi1.h
@@ -28,16 +28,16 @@ struct pi1_regs {
 #define PI1_STAT_BUSY          0x80
        u8 _dmactrl[3];
        volatile u8 dmactrl;
 #define PI1_STAT_BUSY          0x80
        u8 _dmactrl[3];
        volatile u8 dmactrl;

-#define PI1_DMACTRL_FIFO_EMPTY 0x01    /* fifo empty R/O */
-#define PI1_DMACTRL_ABORT      0x02    /* reset DMA and internal fifo W/O */
-#define PI1_DMACTRL_STDMODE    0x00    /* bits 2-3 */
-#define PI1_DMACTRL_SGIMODE    0x04    /* bits 2-3 */
-#define PI1_DMACTRL_RICOHMODE  0x08    /* bits 2-3 */
-#define PI1_DMACTRL_HPMODE     0x0c    /* bits 2-3 */
-#define PI1_DMACTRL_BLKMODE    0x10    /* block mode */
-#define PI1_DMACTRL_FIFO_CLEAR 0x20    /* clear fifo W/O */
-#define PI1_DMACTRL_READ       0x40    /* read */
-#define PI1_DMACTRL_RUN                0x80    /* pedal to the metal */
+#define PI1_DMACTRL_FIFO_EMPTY 0x01    /* fifo empty R/O */
+#define PI1_DMACTRL_ABORT      0x02    /* reset DMA and internal fifo W/O */
+#define PI1_DMACTRL_STDMODE    0x00    /* bits 2-3 */
+#define PI1_DMACTRL_SGIMODE    0x04    /* bits 2-3 */
+#define PI1_DMACTRL_RICOHMODE  0x08    /* bits 2-3 */
+#define PI1_DMACTRL_HPMODE     0x0c    /* bits 2-3 */
+#define PI1_DMACTRL_BLKMODE    0x10    /* block mode */
+#define PI1_DMACTRL_FIFO_CLEAR 0x20    /* clear fifo W/O */
+#define PI1_DMACTRL_READ       0x40    /* read */
+#define PI1_DMACTRL_RUN                0x80    /* pedal to the metal */

        u8 _intstat[3];
        volatile u8 intstat;
 #define PI1_INTSTAT_ACK                0x04
        u8 _intstat[3];
        volatile u8 intstat;
 #define PI1_INTSTAT_ACK                0x04

diff --git a/arch/mips/include/asm/sgialib.h b/arch/mips/include/asm/sgialib.h
index f5811576945733edac776ae853405a228b2194c7..753275accd1892142151169ed8ca722e41742d14 100644 (file)
--- a/arch/mips/include/asm/sgialib.h
+++ b/arch/mips/include/asm/sgialib.h
@@ -37,7 +37,7 @@ extern char prom_getchar(void);
  * in chain is CURR is NULL.
  */
 extern struct linux_mdesc *prom_getmdesc(struct linux_mdesc *curr);
  * in chain is CURR is NULL.
  */
 extern struct linux_mdesc *prom_getmdesc(struct linux_mdesc *curr);

-#define PROM_NULL_MDESC   ((struct linux_mdesc *) 0)
+#define PROM_NULL_MDESC          ((struct linux_mdesc *) 0)

 
 /* Called by prom_init to setup the physical memory pmemblock
  * array.
 
 /* Called by prom_init to setup the physical memory pmemblock
  * array.

diff --git a/arch/mips/include/asm/sgiarcs.h b/arch/mips/include/asm/sgiarcs.h
index 3dce7c788b3e579679c045a937b2f4128cd5f59f..26ddfff28c8e27cd53629e840502a771a9d0c6a5 100644 (file)
--- a/arch/mips/include/asm/sgiarcs.h
+++ b/arch/mips/include/asm/sgiarcs.h
@@ -16,33 +16,33 @@
 #include <asm/fw/arc/types.h>
 
 /* Various ARCS error codes. */
 #include <asm/fw/arc/types.h>
 
 /* Various ARCS error codes. */

-#define PROM_ESUCCESS                   0x00
-#define PROM_E2BIG                      0x01
-#define PROM_EACCESS                    0x02
-#define PROM_EAGAIN                     0x03
-#define PROM_EBADF                      0x04
-#define PROM_EBUSY                      0x05
-#define PROM_EFAULT                     0x06
-#define PROM_EINVAL                     0x07
-#define PROM_EIO                        0x08
-#define PROM_EISDIR                     0x09
-#define PROM_EMFILE                     0x0a
-#define PROM_EMLINK                     0x0b
-#define PROM_ENAMETOOLONG               0x0c
-#define PROM_ENODEV                     0x0d
-#define PROM_ENOENT                     0x0e
-#define PROM_ENOEXEC                    0x0f
-#define PROM_ENOMEM                     0x10
-#define PROM_ENOSPC                     0x11
-#define PROM_ENOTDIR                    0x12
-#define PROM_ENOTTY                     0x13
-#define PROM_ENXIO                      0x14
-#define PROM_EROFS                      0x15
+#define PROM_ESUCCESS                  0x00
+#define PROM_E2BIG                     0x01
+#define PROM_EACCESS                   0x02
+#define PROM_EAGAIN                    0x03
+#define PROM_EBADF                     0x04
+#define PROM_EBUSY                     0x05
+#define PROM_EFAULT                    0x06
+#define PROM_EINVAL                    0x07
+#define PROM_EIO                       0x08
+#define PROM_EISDIR                    0x09
+#define PROM_EMFILE                    0x0a
+#define PROM_EMLINK                    0x0b
+#define PROM_ENAMETOOLONG              0x0c
+#define PROM_ENODEV                    0x0d
+#define PROM_ENOENT                    0x0e
+#define PROM_ENOEXEC                   0x0f
+#define PROM_ENOMEM                    0x10
+#define PROM_ENOSPC                    0x11
+#define PROM_ENOTDIR                   0x12
+#define PROM_ENOTTY                    0x13
+#define PROM_ENXIO                     0x14
+#define PROM_EROFS                     0x15

 /* SGI ARCS specific errno's. */
 /* SGI ARCS specific errno's. */

-#define PROM_EADDRNOTAVAIL              0x1f
-#define PROM_ETIMEDOUT                  0x20
-#define PROM_ECONNABORTED               0x21
-#define PROM_ENOCONNECT                 0x22
+#define PROM_EADDRNOTAVAIL             0x1f
+#define PROM_ETIMEDOUT                 0x20
+#define PROM_ECONNABORTED              0x21
+#define PROM_ENOCONNECT                        0x22

 
 /* Device classes, types, and identifiers for prom
  * device inventory queries.
 
 /* Device classes, types, and identifiers for prom
  * device inventory queries.


@@ -77,14 +77,14 @@ enum linux_identifier {
 
 /* A prom device tree component. */
 struct linux_component {
 
 /* A prom device tree component. */
 struct linux_component {

-       enum linux_devclass     class;  /* node class */
-       enum linux_devtypes     type;   /* node type */
-       enum linux_identifier   iflags; /* node flags */
-       USHORT                  vers;   /* node version */
-       USHORT                  rev;    /* node revision */
-       ULONG                   key;    /* completely magic */
-       ULONG                   amask;  /* XXX affinity mask??? */
-       ULONG                   cdsize; /* size of configuration data */
+       enum linux_devclass     class;  /* node class */
+       enum linux_devtypes     type;   /* node type */
+       enum linux_identifier   iflags; /* node flags */
+       USHORT                  vers;   /* node version */
+       USHORT                  rev;    /* node revision */
+       ULONG                   key;    /* completely magic */
+       ULONG                   amask;  /* XXX affinity mask??? */
+       ULONG                   cdsize; /* size of configuration data */

        ULONG                   ilen;   /* length of string identifier */
        _PULONG                 iname;  /* string identifier */
 };
        ULONG                   ilen;   /* length of string identifier */
        _PULONG                 iname;  /* string identifier */
 };


@@ -177,13 +177,13 @@ struct linux_finfo {
        struct linux_bigint   end;
        struct linux_bigint   cur;
        enum linux_devtypes   dtype;
        struct linux_bigint   end;
        struct linux_bigint   cur;
        enum linux_devtypes   dtype;

-       unsigned long         namelen;
-       unsigned char         attr;
-       char                  name[32]; /* XXX imperical, should be define */
+       unsigned long         namelen;
+       unsigned char         attr;
+       char                  name[32]; /* XXX imperical, should be define */

 };
 
 /* This describes the vector containing function pointers to the ARC
 };
 
 /* This describes the vector containing function pointers to the ARC

-   firmware functions.  */
+   firmware functions. */

 struct linux_romvec {
        LONG    load;                   /* Load an executable image. */
        LONG    invoke;                 /* Invoke a standalong image. */
 struct linux_romvec {
        LONG    load;                   /* Load an executable image. */
        LONG    invoke;                 /* Invoke a standalong image. */


@@ -244,7 +244,7 @@ struct linux_romvec {
  */
 typedef struct _SYSTEM_PARAMETER_BLOCK {
        ULONG                   magic;          /* magic cookie */
  */
 typedef struct _SYSTEM_PARAMETER_BLOCK {
        ULONG                   magic;          /* magic cookie */

-#define PROMBLOCK_MAGIC      0x53435241
+#define PROMBLOCK_MAGIC             0x53435241

 
        ULONG                   len;            /* length of parm block */
        USHORT                  ver;            /* ARCS firmware version */
 
        ULONG                   len;            /* length of parm block */
        USHORT                  ver;            /* ARCS firmware version */


@@ -294,16 +294,16 @@ struct linux_cdata {
 };
 
 /* Common SGI ARCS firmware file descriptors. */
 };
 
 /* Common SGI ARCS firmware file descriptors. */

-#define SGIPROM_STDIN     0
-#define SGIPROM_STDOUT    1
+#define SGIPROM_STDIN    0
+#define SGIPROM_STDOUT   1

 
 /* Common SGI ARCS firmware file types. */
 
 /* Common SGI ARCS firmware file types. */

-#define SGIPROM_ROFILE    0x01  /* read-only file */
-#define SGIPROM_HFILE     0x02  /* hidden file */
-#define SGIPROM_SFILE     0x04  /* System file */
-#define SGIPROM_AFILE     0x08  /* Archive file */
-#define SGIPROM_DFILE     0x10  /* Directory file */
-#define SGIPROM_DELFILE   0x20  /* Deleted file */
+#define SGIPROM_ROFILE   0x01  /* read-only file */
+#define SGIPROM_HFILE    0x02  /* hidden file */
+#define SGIPROM_SFILE    0x04  /* System file */
+#define SGIPROM_AFILE    0x08  /* Archive file */
+#define SGIPROM_DFILE    0x10  /* Directory file */
+#define SGIPROM_DELFILE          0x20  /* Deleted file */

 
 /* SGI ARCS boot record information. */
 struct sgi_partition {
 
 /* SGI ARCS boot record information. */
 struct sgi_partition {


@@ -318,7 +318,7 @@ struct sgi_partition {
        unsigned char tsect0, tsect1, tsect2, tsect3;
 };
 
        unsigned char tsect0, tsect1, tsect2, tsect3;
 };
 

-#define SGIBBLOCK_MAGIC   0xaa55
+#define SGIBBLOCK_MAGIC          0xaa55

 #define SGIBBLOCK_MAXPART 0x0004
 
 struct sgi_bootblock {
 #define SGIBBLOCK_MAXPART 0x0004
 
 struct sgi_bootblock {


@@ -332,34 +332,34 @@ struct sgi_bparm_block {
        unsigned short bytes_sect;    /* bytes per sector */
        unsigned char  sect_clust;    /* sectors per cluster */
        unsigned short sect_resv;     /* reserved sectors */
        unsigned short bytes_sect;    /* bytes per sector */
        unsigned char  sect_clust;    /* sectors per cluster */
        unsigned short sect_resv;     /* reserved sectors */

-       unsigned char  nfats;         /* # of allocation tables */
+       unsigned char  nfats;         /* # of allocation tables */

        unsigned short nroot_dirents; /* # of root directory entries */
        unsigned short sect_volume;   /* sectors in volume */
        unsigned char  media_type;    /* media descriptor */
        unsigned short sect_fat;      /* sectors per allocation table */
        unsigned short sect_track;    /* sectors per track */
        unsigned short nroot_dirents; /* # of root directory entries */
        unsigned short sect_volume;   /* sectors in volume */
        unsigned char  media_type;    /* media descriptor */
        unsigned short sect_fat;      /* sectors per allocation table */
        unsigned short sect_track;    /* sectors per track */

-       unsigned short nheads;        /* # of heads */
-       unsigned short nhsects;       /* # of hidden sectors */
+       unsigned short nheads;        /* # of heads */
+       unsigned short nhsects;       /* # of hidden sectors */

 };
 
 struct sgi_bsector {
 };
 
 struct sgi_bsector {

-       unsigned char   jmpinfo[3];
-       unsigned char   manuf_name[8];
+       unsigned char   jmpinfo[3];
+       unsigned char   manuf_name[8];

        struct sgi_bparm_block info;
 };
 
 /* Debugging block used with SGI symmon symbolic debugger. */
        struct sgi_bparm_block info;
 };
 
 /* Debugging block used with SGI symmon symbolic debugger. */

-#define SMB_DEBUG_MAGIC   0xfeeddead
+#define SMB_DEBUG_MAGIC          0xfeeddead

 struct linux_smonblock {
 struct linux_smonblock {

-       unsigned long   magic;
-       void            (*handler)(void);  /* Breakpoint routine. */
-       unsigned long   dtable_base;       /* Base addr of dbg table. */
-       int             (*printf)(const char *fmt, ...);
-       unsigned long   btable_base;       /* Breakpoint table. */
-       unsigned long   mpflushreqs;       /* SMP cache flush request list. */
-       unsigned long   ntab;              /* Name table. */
-       unsigned long   stab;              /* Symbol table. */
-       int             smax;              /* Max # of symbols. */
+       unsigned long   magic;
+       void            (*handler)(void);  /* Breakpoint routine. */
+       unsigned long   dtable_base;       /* Base addr of dbg table. */
+       int             (*printf)(const char *fmt, ...);
+       unsigned long   btable_base;       /* Breakpoint table. */
+       unsigned long   mpflushreqs;       /* SMP cache flush request list. */
+       unsigned long   ntab;              /* Name table. */
+       unsigned long   stab;              /* Symbol table. */
+       int             smax;              /* Max # of symbols. */

 };
 
 /*
 };
 
 /*


@@ -369,7 +369,7 @@ struct linux_smonblock {
 #if defined(CONFIG_64BIT) && defined(CONFIG_FW_ARC32)
 
 #define __arc_clobbers                                                 \
 #if defined(CONFIG_64BIT) && defined(CONFIG_FW_ARC32)
 
 #define __arc_clobbers                                                 \

-       "$2", "$3" /* ... */, "$8", "$9", "$10", "$11",                         \
+       "$2", "$3" /* ... */, "$8", "$9", "$10", "$11",                         \

        "$12", "$13", "$14", "$15", "$16", "$24", "$25", "$31"
 
 #define ARC_CALL0(dest)                                                        \
        "$12", "$13", "$14", "$15", "$16", "$24", "$25", "$31"
 
 #define ARC_CALL0(dest)                                                        \


@@ -447,7 +447,7 @@ struct linux_smonblock {
        "daddu\t$29, 32\n\t"                                            \
        "move\t%0, $2"                                                  \
        : "=r" (__res), "=r" (__vec)                                    \
        "daddu\t$29, 32\n\t"                                            \
        "move\t%0, $2"                                                  \
        : "=r" (__res), "=r" (__vec)                                    \

-       : "1" (__vec), "r" (__a1), "r" (__a2), "r" (__a3),              \
+       : "1" (__vec), "r" (__a1), "r" (__a2), "r" (__a3),              \

          "r" (__a4)                                                    \
        : __arc_clobbers);                                              \
        __res;                                                          \
          "r" (__a4)                                                    \
        : __arc_clobbers);                                              \
        __res;                                                          \


@@ -468,8 +468,8 @@ struct linux_smonblock {
        "daddu\t$29, 32\n\t"                                            \
        "move\t%0, $2"                                                  \
        : "=r" (__res), "=r" (__vec)                                    \
        "daddu\t$29, 32\n\t"                                            \
        "move\t%0, $2"                                                  \
        : "=r" (__res), "=r" (__vec)                                    \

-       : "1" (__vec),                                                  \
-         "r" (__a1), "r" (__a2), "r" (__a3), "r" (__a4),               \
+       : "1" (__vec),                                                  \
+         "r" (__a1), "r" (__a2), "r" (__a3), "r" (__a4),               \

          "r" (__a5)                                                    \
        : __arc_clobbers);                                              \
        __res;                                                          \
          "r" (__a5)                                                    \
        : __arc_clobbers);                                              \
        __res;                                                          \


@@ -512,7 +512,7 @@ struct linux_smonblock {
        long __a1 = (long) (a1);                                        \
        long __a2 = (long) (a2);                                        \
        long __a3 = (long) (a3);                                        \
        long __a1 = (long) (a1);                                        \
        long __a2 = (long) (a2);                                        \
        long __a3 = (long) (a3);                                        \

-       long (*__vec)(long, long, long) = (void *) romvec->dest;        \
+       long (*__vec)(long, long, long) = (void *) romvec->dest;        \

                                                                        \
        __res = __vec(__a1, __a2, __a3);                                \
        __res;                                                          \
                                                                        \
        __res = __vec(__a1, __a2, __a3);                                \
        __res;                                                          \

diff --git a/arch/mips/include/asm/shmparam.h b/arch/mips/include/asm/shmparam.h
index 09290720751cb2cb1187db63c5a8d20dc1c6a331..324d04042bdfec8d9a78e83c7af9f39b3dac143c 100644 (file)
--- a/arch/mips/include/asm/shmparam.h
+++ b/arch/mips/include/asm/shmparam.h
@@ -8,6 +8,6 @@
 
 #define __ARCH_FORCE_SHMLBA    1
 
 
 #define __ARCH_FORCE_SHMLBA    1
 

-#define        SHMLBA 0x40000                  /* attach addr a multiple of this */
+#define SHMLBA 0x40000                 /* attach addr a multiple of this */

 
 #endif /* _ASM_SHMPARAM_H */
 
 #endif /* _ASM_SHMPARAM_H */

diff --git a/arch/mips/include/asm/sibyte/bcm1480_int.h b/arch/mips/include/asm/sibyte/bcm1480_int.h
index fffb224d2297d59834598b8f5701965dd85a9b46..6b82ed3c2359e6e1bd041aeba0823a628db4a48c 100644 (file)
--- a/arch/mips/include/asm/sibyte/bcm1480_int.h
+++ b/arch/mips/include/asm/sibyte/bcm1480_int.h
@@ -60,253 +60,253 @@
  * Interrupt sources (Table 22)
  */
 
  * Interrupt sources (Table 22)
  */
 

-#define K_BCM1480_INT_SOURCES               128
+#define K_BCM1480_INT_SOURCES              128

 
 #define _BCM1480_INT_HIGH(k)   (k)
 #define _BCM1480_INT_LOW(k)    ((k)+64)
 
 
 #define _BCM1480_INT_HIGH(k)   (k)
 #define _BCM1480_INT_LOW(k)    ((k)+64)
 

-#define K_BCM1480_INT_ADDR_TRAP             _BCM1480_INT_HIGH(1)
-#define K_BCM1480_INT_GPIO_0                _BCM1480_INT_HIGH(4)
-#define K_BCM1480_INT_GPIO_1                _BCM1480_INT_HIGH(5)
-#define K_BCM1480_INT_GPIO_2                _BCM1480_INT_HIGH(6)
-#define K_BCM1480_INT_GPIO_3                _BCM1480_INT_HIGH(7)
-#define K_BCM1480_INT_PCI_INTA              _BCM1480_INT_HIGH(8)
-#define K_BCM1480_INT_PCI_INTB              _BCM1480_INT_HIGH(9)
-#define K_BCM1480_INT_PCI_INTC              _BCM1480_INT_HIGH(10)
-#define K_BCM1480_INT_PCI_INTD              _BCM1480_INT_HIGH(11)
-#define K_BCM1480_INT_CYCLE_CP0             _BCM1480_INT_HIGH(12)
-#define K_BCM1480_INT_CYCLE_CP1             _BCM1480_INT_HIGH(13)
-#define K_BCM1480_INT_CYCLE_CP2             _BCM1480_INT_HIGH(14)
-#define K_BCM1480_INT_CYCLE_CP3             _BCM1480_INT_HIGH(15)
-#define K_BCM1480_INT_TIMER_0               _BCM1480_INT_HIGH(20)
-#define K_BCM1480_INT_TIMER_1               _BCM1480_INT_HIGH(21)
-#define K_BCM1480_INT_TIMER_2               _BCM1480_INT_HIGH(22)
-#define K_BCM1480_INT_TIMER_3               _BCM1480_INT_HIGH(23)
-#define K_BCM1480_INT_DM_CH_0               _BCM1480_INT_HIGH(28)
-#define K_BCM1480_INT_DM_CH_1               _BCM1480_INT_HIGH(29)
-#define K_BCM1480_INT_DM_CH_2               _BCM1480_INT_HIGH(30)
-#define K_BCM1480_INT_DM_CH_3               _BCM1480_INT_HIGH(31)
-#define K_BCM1480_INT_MAC_0                 _BCM1480_INT_HIGH(36)
-#define K_BCM1480_INT_MAC_0_CH1             _BCM1480_INT_HIGH(37)
-#define K_BCM1480_INT_MAC_1                 _BCM1480_INT_HIGH(38)
-#define K_BCM1480_INT_MAC_1_CH1             _BCM1480_INT_HIGH(39)
-#define K_BCM1480_INT_MAC_2                 _BCM1480_INT_HIGH(40)
-#define K_BCM1480_INT_MAC_2_CH1             _BCM1480_INT_HIGH(41)
-#define K_BCM1480_INT_MAC_3                 _BCM1480_INT_HIGH(42)
-#define K_BCM1480_INT_MAC_3_CH1             _BCM1480_INT_HIGH(43)
-#define K_BCM1480_INT_PMI_LOW               _BCM1480_INT_HIGH(52)
-#define K_BCM1480_INT_PMI_HIGH              _BCM1480_INT_HIGH(53)
-#define K_BCM1480_INT_PMO_LOW               _BCM1480_INT_HIGH(54)
-#define K_BCM1480_INT_PMO_HIGH              _BCM1480_INT_HIGH(55)
-#define K_BCM1480_INT_MBOX_0_0              _BCM1480_INT_HIGH(56)
-#define K_BCM1480_INT_MBOX_0_1              _BCM1480_INT_HIGH(57)
-#define K_BCM1480_INT_MBOX_0_2              _BCM1480_INT_HIGH(58)
-#define K_BCM1480_INT_MBOX_0_3              _BCM1480_INT_HIGH(59)
-#define K_BCM1480_INT_MBOX_1_0              _BCM1480_INT_HIGH(60)
-#define K_BCM1480_INT_MBOX_1_1              _BCM1480_INT_HIGH(61)
-#define K_BCM1480_INT_MBOX_1_2              _BCM1480_INT_HIGH(62)
-#define K_BCM1480_INT_MBOX_1_3              _BCM1480_INT_HIGH(63)
+#define K_BCM1480_INT_ADDR_TRAP                    _BCM1480_INT_HIGH(1)
+#define K_BCM1480_INT_GPIO_0               _BCM1480_INT_HIGH(4)
+#define K_BCM1480_INT_GPIO_1               _BCM1480_INT_HIGH(5)
+#define K_BCM1480_INT_GPIO_2               _BCM1480_INT_HIGH(6)
+#define K_BCM1480_INT_GPIO_3               _BCM1480_INT_HIGH(7)
+#define K_BCM1480_INT_PCI_INTA             _BCM1480_INT_HIGH(8)
+#define K_BCM1480_INT_PCI_INTB             _BCM1480_INT_HIGH(9)
+#define K_BCM1480_INT_PCI_INTC             _BCM1480_INT_HIGH(10)
+#define K_BCM1480_INT_PCI_INTD             _BCM1480_INT_HIGH(11)
+#define K_BCM1480_INT_CYCLE_CP0                    _BCM1480_INT_HIGH(12)
+#define K_BCM1480_INT_CYCLE_CP1                    _BCM1480_INT_HIGH(13)
+#define K_BCM1480_INT_CYCLE_CP2                    _BCM1480_INT_HIGH(14)
+#define K_BCM1480_INT_CYCLE_CP3                    _BCM1480_INT_HIGH(15)
+#define K_BCM1480_INT_TIMER_0              _BCM1480_INT_HIGH(20)
+#define K_BCM1480_INT_TIMER_1              _BCM1480_INT_HIGH(21)
+#define K_BCM1480_INT_TIMER_2              _BCM1480_INT_HIGH(22)
+#define K_BCM1480_INT_TIMER_3              _BCM1480_INT_HIGH(23)
+#define K_BCM1480_INT_DM_CH_0              _BCM1480_INT_HIGH(28)
+#define K_BCM1480_INT_DM_CH_1              _BCM1480_INT_HIGH(29)
+#define K_BCM1480_INT_DM_CH_2              _BCM1480_INT_HIGH(30)
+#define K_BCM1480_INT_DM_CH_3              _BCM1480_INT_HIGH(31)
+#define K_BCM1480_INT_MAC_0                _BCM1480_INT_HIGH(36)
+#define K_BCM1480_INT_MAC_0_CH1                    _BCM1480_INT_HIGH(37)
+#define K_BCM1480_INT_MAC_1                _BCM1480_INT_HIGH(38)
+#define K_BCM1480_INT_MAC_1_CH1                    _BCM1480_INT_HIGH(39)
+#define K_BCM1480_INT_MAC_2                _BCM1480_INT_HIGH(40)
+#define K_BCM1480_INT_MAC_2_CH1                    _BCM1480_INT_HIGH(41)
+#define K_BCM1480_INT_MAC_3                _BCM1480_INT_HIGH(42)
+#define K_BCM1480_INT_MAC_3_CH1                    _BCM1480_INT_HIGH(43)
+#define K_BCM1480_INT_PMI_LOW              _BCM1480_INT_HIGH(52)
+#define K_BCM1480_INT_PMI_HIGH             _BCM1480_INT_HIGH(53)
+#define K_BCM1480_INT_PMO_LOW              _BCM1480_INT_HIGH(54)
+#define K_BCM1480_INT_PMO_HIGH             _BCM1480_INT_HIGH(55)
+#define K_BCM1480_INT_MBOX_0_0             _BCM1480_INT_HIGH(56)
+#define K_BCM1480_INT_MBOX_0_1             _BCM1480_INT_HIGH(57)
+#define K_BCM1480_INT_MBOX_0_2             _BCM1480_INT_HIGH(58)
+#define K_BCM1480_INT_MBOX_0_3             _BCM1480_INT_HIGH(59)
+#define K_BCM1480_INT_MBOX_1_0             _BCM1480_INT_HIGH(60)
+#define K_BCM1480_INT_MBOX_1_1             _BCM1480_INT_HIGH(61)
+#define K_BCM1480_INT_MBOX_1_2             _BCM1480_INT_HIGH(62)
+#define K_BCM1480_INT_MBOX_1_3             _BCM1480_INT_HIGH(63)

 
 

-#define K_BCM1480_INT_BAD_ECC               _BCM1480_INT_LOW(1)
-#define K_BCM1480_INT_COR_ECC               _BCM1480_INT_LOW(2)
-#define K_BCM1480_INT_IO_BUS                _BCM1480_INT_LOW(3)
-#define K_BCM1480_INT_PERF_CNT              _BCM1480_INT_LOW(4)
-#define K_BCM1480_INT_SW_PERF_CNT           _BCM1480_INT_LOW(5)
-#define K_BCM1480_INT_TRACE_FREEZE          _BCM1480_INT_LOW(6)
-#define K_BCM1480_INT_SW_TRACE_FREEZE       _BCM1480_INT_LOW(7)
-#define K_BCM1480_INT_WATCHDOG_TIMER_0      _BCM1480_INT_LOW(8)
-#define K_BCM1480_INT_WATCHDOG_TIMER_1      _BCM1480_INT_LOW(9)
-#define K_BCM1480_INT_WATCHDOG_TIMER_2      _BCM1480_INT_LOW(10)
-#define K_BCM1480_INT_WATCHDOG_TIMER_3      _BCM1480_INT_LOW(11)
-#define K_BCM1480_INT_PCI_ERROR             _BCM1480_INT_LOW(16)
-#define K_BCM1480_INT_PCI_RESET             _BCM1480_INT_LOW(17)
-#define K_BCM1480_INT_NODE_CONTROLLER       _BCM1480_INT_LOW(18)
-#define K_BCM1480_INT_HOST_BRIDGE           _BCM1480_INT_LOW(19)
-#define K_BCM1480_INT_PORT_0_FATAL          _BCM1480_INT_LOW(20)
-#define K_BCM1480_INT_PORT_0_NONFATAL       _BCM1480_INT_LOW(21)
-#define K_BCM1480_INT_PORT_1_FATAL          _BCM1480_INT_LOW(22)
-#define K_BCM1480_INT_PORT_1_NONFATAL       _BCM1480_INT_LOW(23)
-#define K_BCM1480_INT_PORT_2_FATAL          _BCM1480_INT_LOW(24)
-#define K_BCM1480_INT_PORT_2_NONFATAL       _BCM1480_INT_LOW(25)
-#define K_BCM1480_INT_LDT_SMI               _BCM1480_INT_LOW(32)
-#define K_BCM1480_INT_LDT_NMI               _BCM1480_INT_LOW(33)
-#define K_BCM1480_INT_LDT_INIT              _BCM1480_INT_LOW(34)
-#define K_BCM1480_INT_LDT_STARTUP           _BCM1480_INT_LOW(35)
-#define K_BCM1480_INT_LDT_EXT               _BCM1480_INT_LOW(36)
-#define K_BCM1480_INT_SMB_0                 _BCM1480_INT_LOW(40)
-#define K_BCM1480_INT_SMB_1                 _BCM1480_INT_LOW(41)
-#define K_BCM1480_INT_PCMCIA                _BCM1480_INT_LOW(42)
-#define K_BCM1480_INT_UART_0                _BCM1480_INT_LOW(44)
-#define K_BCM1480_INT_UART_1                _BCM1480_INT_LOW(45)
-#define K_BCM1480_INT_UART_2                _BCM1480_INT_LOW(46)
-#define K_BCM1480_INT_UART_3                _BCM1480_INT_LOW(47)
-#define K_BCM1480_INT_GPIO_4                _BCM1480_INT_LOW(52)
-#define K_BCM1480_INT_GPIO_5                _BCM1480_INT_LOW(53)
-#define K_BCM1480_INT_GPIO_6                _BCM1480_INT_LOW(54)
-#define K_BCM1480_INT_GPIO_7                _BCM1480_INT_LOW(55)
-#define K_BCM1480_INT_GPIO_8                _BCM1480_INT_LOW(56)
-#define K_BCM1480_INT_GPIO_9                _BCM1480_INT_LOW(57)
-#define K_BCM1480_INT_GPIO_10               _BCM1480_INT_LOW(58)
-#define K_BCM1480_INT_GPIO_11               _BCM1480_INT_LOW(59)
-#define K_BCM1480_INT_GPIO_12               _BCM1480_INT_LOW(60)
-#define K_BCM1480_INT_GPIO_13               _BCM1480_INT_LOW(61)
-#define K_BCM1480_INT_GPIO_14               _BCM1480_INT_LOW(62)
-#define K_BCM1480_INT_GPIO_15               _BCM1480_INT_LOW(63)
+#define K_BCM1480_INT_BAD_ECC              _BCM1480_INT_LOW(1)
+#define K_BCM1480_INT_COR_ECC              _BCM1480_INT_LOW(2)
+#define K_BCM1480_INT_IO_BUS               _BCM1480_INT_LOW(3)
+#define K_BCM1480_INT_PERF_CNT             _BCM1480_INT_LOW(4)
+#define K_BCM1480_INT_SW_PERF_CNT          _BCM1480_INT_LOW(5)
+#define K_BCM1480_INT_TRACE_FREEZE         _BCM1480_INT_LOW(6)
+#define K_BCM1480_INT_SW_TRACE_FREEZE      _BCM1480_INT_LOW(7)
+#define K_BCM1480_INT_WATCHDOG_TIMER_0     _BCM1480_INT_LOW(8)
+#define K_BCM1480_INT_WATCHDOG_TIMER_1     _BCM1480_INT_LOW(9)
+#define K_BCM1480_INT_WATCHDOG_TIMER_2     _BCM1480_INT_LOW(10)
+#define K_BCM1480_INT_WATCHDOG_TIMER_3     _BCM1480_INT_LOW(11)
+#define K_BCM1480_INT_PCI_ERROR                    _BCM1480_INT_LOW(16)
+#define K_BCM1480_INT_PCI_RESET                    _BCM1480_INT_LOW(17)
+#define K_BCM1480_INT_NODE_CONTROLLER      _BCM1480_INT_LOW(18)
+#define K_BCM1480_INT_HOST_BRIDGE          _BCM1480_INT_LOW(19)
+#define K_BCM1480_INT_PORT_0_FATAL         _BCM1480_INT_LOW(20)
+#define K_BCM1480_INT_PORT_0_NONFATAL      _BCM1480_INT_LOW(21)
+#define K_BCM1480_INT_PORT_1_FATAL         _BCM1480_INT_LOW(22)
+#define K_BCM1480_INT_PORT_1_NONFATAL      _BCM1480_INT_LOW(23)
+#define K_BCM1480_INT_PORT_2_FATAL         _BCM1480_INT_LOW(24)
+#define K_BCM1480_INT_PORT_2_NONFATAL      _BCM1480_INT_LOW(25)
+#define K_BCM1480_INT_LDT_SMI              _BCM1480_INT_LOW(32)
+#define K_BCM1480_INT_LDT_NMI              _BCM1480_INT_LOW(33)
+#define K_BCM1480_INT_LDT_INIT             _BCM1480_INT_LOW(34)
+#define K_BCM1480_INT_LDT_STARTUP          _BCM1480_INT_LOW(35)
+#define K_BCM1480_INT_LDT_EXT              _BCM1480_INT_LOW(36)
+#define K_BCM1480_INT_SMB_0                _BCM1480_INT_LOW(40)
+#define K_BCM1480_INT_SMB_1                _BCM1480_INT_LOW(41)
+#define K_BCM1480_INT_PCMCIA               _BCM1480_INT_LOW(42)
+#define K_BCM1480_INT_UART_0               _BCM1480_INT_LOW(44)
+#define K_BCM1480_INT_UART_1               _BCM1480_INT_LOW(45)
+#define K_BCM1480_INT_UART_2               _BCM1480_INT_LOW(46)
+#define K_BCM1480_INT_UART_3               _BCM1480_INT_LOW(47)
+#define K_BCM1480_INT_GPIO_4               _BCM1480_INT_LOW(52)
+#define K_BCM1480_INT_GPIO_5               _BCM1480_INT_LOW(53)
+#define K_BCM1480_INT_GPIO_6               _BCM1480_INT_LOW(54)
+#define K_BCM1480_INT_GPIO_7               _BCM1480_INT_LOW(55)
+#define K_BCM1480_INT_GPIO_8               _BCM1480_INT_LOW(56)
+#define K_BCM1480_INT_GPIO_9               _BCM1480_INT_LOW(57)
+#define K_BCM1480_INT_GPIO_10              _BCM1480_INT_LOW(58)
+#define K_BCM1480_INT_GPIO_11              _BCM1480_INT_LOW(59)
+#define K_BCM1480_INT_GPIO_12              _BCM1480_INT_LOW(60)
+#define K_BCM1480_INT_GPIO_13              _BCM1480_INT_LOW(61)
+#define K_BCM1480_INT_GPIO_14              _BCM1480_INT_LOW(62)
+#define K_BCM1480_INT_GPIO_15              _BCM1480_INT_LOW(63)

 
 /*
  * Mask values for each interrupt
  */
 
 
 /*
  * Mask values for each interrupt
  */
 

-#define _BCM1480_INT_MASK(w, n)              _SB_MAKEMASK(w, ((n) & 0x3F))
-#define _BCM1480_INT_MASK1(n)               _SB_MAKEMASK1(((n) & 0x3F))
-#define _BCM1480_INT_OFFSET(n)              (((n) & 0x40) << 6)
+#define _BCM1480_INT_MASK(w, n)                     _SB_MAKEMASK(w, ((n) & 0x3F))
+#define _BCM1480_INT_MASK1(n)              _SB_MAKEMASK1(((n) & 0x3F))
+#define _BCM1480_INT_OFFSET(n)             (((n) & 0x40) << 6)

 
 

-#define M_BCM1480_INT_CASCADE               _BCM1480_INT_MASK1(_BCM1480_INT_HIGH(0))
+#define M_BCM1480_INT_CASCADE              _BCM1480_INT_MASK1(_BCM1480_INT_HIGH(0))

 
 

-#define M_BCM1480_INT_ADDR_TRAP             _BCM1480_INT_MASK1(K_BCM1480_INT_ADDR_TRAP)
-#define M_BCM1480_INT_GPIO_0                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_0)
-#define M_BCM1480_INT_GPIO_1                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_1)
-#define M_BCM1480_INT_GPIO_2                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_2)
-#define M_BCM1480_INT_GPIO_3                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_3)
-#define M_BCM1480_INT_PCI_INTA              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTA)
-#define M_BCM1480_INT_PCI_INTB              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTB)
-#define M_BCM1480_INT_PCI_INTC              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTC)
-#define M_BCM1480_INT_PCI_INTD              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTD)
-#define M_BCM1480_INT_CYCLE_CP0             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP0)
-#define M_BCM1480_INT_CYCLE_CP1             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP1)
-#define M_BCM1480_INT_CYCLE_CP2             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP2)
-#define M_BCM1480_INT_CYCLE_CP3             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP3)
-#define M_BCM1480_INT_TIMER_0               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_0)
-#define M_BCM1480_INT_TIMER_1               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_1)
-#define M_BCM1480_INT_TIMER_2               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_2)
-#define M_BCM1480_INT_TIMER_3               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_3)
-#define M_BCM1480_INT_DM_CH_0               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_0)
-#define M_BCM1480_INT_DM_CH_1               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_1)
-#define M_BCM1480_INT_DM_CH_2               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_2)
-#define M_BCM1480_INT_DM_CH_3               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_3)
-#define M_BCM1480_INT_MAC_0                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0)
-#define M_BCM1480_INT_MAC_0_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0_CH1)
-#define M_BCM1480_INT_MAC_1                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1)
-#define M_BCM1480_INT_MAC_1_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1_CH1)
-#define M_BCM1480_INT_MAC_2                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2)
-#define M_BCM1480_INT_MAC_2_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2_CH1)
-#define M_BCM1480_INT_MAC_3                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3)
-#define M_BCM1480_INT_MAC_3_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3_CH1)
-#define M_BCM1480_INT_PMI_LOW               _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_LOW)
-#define M_BCM1480_INT_PMI_HIGH              _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH)
-#define M_BCM1480_INT_PMO_LOW               _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW)
-#define M_BCM1480_INT_PMO_HIGH              _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH)
-#define M_BCM1480_INT_MBOX_ALL              _BCM1480_INT_MASK(8, K_BCM1480_INT_MBOX_0_0)
-#define M_BCM1480_INT_MBOX_0_0              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0)
-#define M_BCM1480_INT_MBOX_0_1              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1)
-#define M_BCM1480_INT_MBOX_0_2              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2)
-#define M_BCM1480_INT_MBOX_0_3              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_3)
-#define M_BCM1480_INT_MBOX_1_0              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_0)
-#define M_BCM1480_INT_MBOX_1_1              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_1)
-#define M_BCM1480_INT_MBOX_1_2              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_2)
-#define M_BCM1480_INT_MBOX_1_3              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_3)
-#define M_BCM1480_INT_BAD_ECC               _BCM1480_INT_MASK1(K_BCM1480_INT_BAD_ECC)
-#define M_BCM1480_INT_COR_ECC               _BCM1480_INT_MASK1(K_BCM1480_INT_COR_ECC)
-#define M_BCM1480_INT_IO_BUS                _BCM1480_INT_MASK1(K_BCM1480_INT_IO_BUS)
-#define M_BCM1480_INT_PERF_CNT              _BCM1480_INT_MASK1(K_BCM1480_INT_PERF_CNT)
-#define M_BCM1480_INT_SW_PERF_CNT           _BCM1480_INT_MASK1(K_BCM1480_INT_SW_PERF_CNT)
-#define M_BCM1480_INT_TRACE_FREEZE          _BCM1480_INT_MASK1(K_BCM1480_INT_TRACE_FREEZE)
-#define M_BCM1480_INT_SW_TRACE_FREEZE       _BCM1480_INT_MASK1(K_BCM1480_INT_SW_TRACE_FREEZE)
-#define M_BCM1480_INT_WATCHDOG_TIMER_0      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_0)
-#define M_BCM1480_INT_WATCHDOG_TIMER_1      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_1)
-#define M_BCM1480_INT_WATCHDOG_TIMER_2      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_2)
-#define M_BCM1480_INT_WATCHDOG_TIMER_3      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_3)
-#define M_BCM1480_INT_PCI_ERROR             _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_ERROR)
-#define M_BCM1480_INT_PCI_RESET             _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_RESET)
-#define M_BCM1480_INT_NODE_CONTROLLER       _BCM1480_INT_MASK1(K_BCM1480_INT_NODE_CONTROLLER)
-#define M_BCM1480_INT_HOST_BRIDGE           _BCM1480_INT_MASK1(K_BCM1480_INT_HOST_BRIDGE)
-#define M_BCM1480_INT_PORT_0_FATAL          _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_FATAL)
-#define M_BCM1480_INT_PORT_0_NONFATAL       _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_NONFATAL)
-#define M_BCM1480_INT_PORT_1_FATAL          _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_FATAL)
-#define M_BCM1480_INT_PORT_1_NONFATAL       _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_NONFATAL)
-#define M_BCM1480_INT_PORT_2_FATAL          _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_FATAL)
-#define M_BCM1480_INT_PORT_2_NONFATAL       _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_NONFATAL)
-#define M_BCM1480_INT_LDT_SMI               _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_SMI)
-#define M_BCM1480_INT_LDT_NMI               _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_NMI)
-#define M_BCM1480_INT_LDT_INIT              _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_INIT)
-#define M_BCM1480_INT_LDT_STARTUP           _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_STARTUP)
-#define M_BCM1480_INT_LDT_EXT               _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_EXT)
-#define M_BCM1480_INT_SMB_0                 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_0)
-#define M_BCM1480_INT_SMB_1                 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_1)
-#define M_BCM1480_INT_PCMCIA                _BCM1480_INT_MASK1(K_BCM1480_INT_PCMCIA)
-#define M_BCM1480_INT_UART_0                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_0)
-#define M_BCM1480_INT_UART_1                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_1)
-#define M_BCM1480_INT_UART_2                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_2)
-#define M_BCM1480_INT_UART_3                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_3)
-#define M_BCM1480_INT_GPIO_4                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_4)
-#define M_BCM1480_INT_GPIO_5                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_5)
-#define M_BCM1480_INT_GPIO_6                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_6)
-#define M_BCM1480_INT_GPIO_7                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_7)
-#define M_BCM1480_INT_GPIO_8                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_8)
-#define M_BCM1480_INT_GPIO_9                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_9)
-#define M_BCM1480_INT_GPIO_10               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_10)
-#define M_BCM1480_INT_GPIO_11               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_11)
-#define M_BCM1480_INT_GPIO_12               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_12)
-#define M_BCM1480_INT_GPIO_13               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_13)
-#define M_BCM1480_INT_GPIO_14               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_14)
-#define M_BCM1480_INT_GPIO_15               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_15)
+#define M_BCM1480_INT_ADDR_TRAP                    _BCM1480_INT_MASK1(K_BCM1480_INT_ADDR_TRAP)
+#define M_BCM1480_INT_GPIO_0               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_0)
+#define M_BCM1480_INT_GPIO_1               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_1)
+#define M_BCM1480_INT_GPIO_2               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_2)
+#define M_BCM1480_INT_GPIO_3               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_3)
+#define M_BCM1480_INT_PCI_INTA             _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTA)
+#define M_BCM1480_INT_PCI_INTB             _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTB)
+#define M_BCM1480_INT_PCI_INTC             _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTC)
+#define M_BCM1480_INT_PCI_INTD             _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTD)
+#define M_BCM1480_INT_CYCLE_CP0                    _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP0)
+#define M_BCM1480_INT_CYCLE_CP1                    _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP1)
+#define M_BCM1480_INT_CYCLE_CP2                    _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP2)
+#define M_BCM1480_INT_CYCLE_CP3                    _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP3)
+#define M_BCM1480_INT_TIMER_0              _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_0)
+#define M_BCM1480_INT_TIMER_1              _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_1)
+#define M_BCM1480_INT_TIMER_2              _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_2)
+#define M_BCM1480_INT_TIMER_3              _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_3)
+#define M_BCM1480_INT_DM_CH_0              _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_0)
+#define M_BCM1480_INT_DM_CH_1              _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_1)
+#define M_BCM1480_INT_DM_CH_2              _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_2)
+#define M_BCM1480_INT_DM_CH_3              _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_3)
+#define M_BCM1480_INT_MAC_0                _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0)
+#define M_BCM1480_INT_MAC_0_CH1                    _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0_CH1)
+#define M_BCM1480_INT_MAC_1                _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1)
+#define M_BCM1480_INT_MAC_1_CH1                    _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1_CH1)
+#define M_BCM1480_INT_MAC_2                _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2)
+#define M_BCM1480_INT_MAC_2_CH1                    _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2_CH1)
+#define M_BCM1480_INT_MAC_3                _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3)
+#define M_BCM1480_INT_MAC_3_CH1                    _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3_CH1)
+#define M_BCM1480_INT_PMI_LOW              _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_LOW)
+#define M_BCM1480_INT_PMI_HIGH             _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH)
+#define M_BCM1480_INT_PMO_LOW              _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW)
+#define M_BCM1480_INT_PMO_HIGH             _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH)
+#define M_BCM1480_INT_MBOX_ALL             _BCM1480_INT_MASK(8, K_BCM1480_INT_MBOX_0_0)
+#define M_BCM1480_INT_MBOX_0_0             _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0)
+#define M_BCM1480_INT_MBOX_0_1             _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1)
+#define M_BCM1480_INT_MBOX_0_2             _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2)
+#define M_BCM1480_INT_MBOX_0_3             _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_3)
+#define M_BCM1480_INT_MBOX_1_0             _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_0)
+#define M_BCM1480_INT_MBOX_1_1             _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_1)
+#define M_BCM1480_INT_MBOX_1_2             _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_2)
+#define M_BCM1480_INT_MBOX_1_3             _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_3)
+#define M_BCM1480_INT_BAD_ECC              _BCM1480_INT_MASK1(K_BCM1480_INT_BAD_ECC)
+#define M_BCM1480_INT_COR_ECC              _BCM1480_INT_MASK1(K_BCM1480_INT_COR_ECC)
+#define M_BCM1480_INT_IO_BUS               _BCM1480_INT_MASK1(K_BCM1480_INT_IO_BUS)
+#define M_BCM1480_INT_PERF_CNT             _BCM1480_INT_MASK1(K_BCM1480_INT_PERF_CNT)
+#define M_BCM1480_INT_SW_PERF_CNT          _BCM1480_INT_MASK1(K_BCM1480_INT_SW_PERF_CNT)
+#define M_BCM1480_INT_TRACE_FREEZE         _BCM1480_INT_MASK1(K_BCM1480_INT_TRACE_FREEZE)
+#define M_BCM1480_INT_SW_TRACE_FREEZE      _BCM1480_INT_MASK1(K_BCM1480_INT_SW_TRACE_FREEZE)
+#define M_BCM1480_INT_WATCHDOG_TIMER_0     _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_0)
+#define M_BCM1480_INT_WATCHDOG_TIMER_1     _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_1)
+#define M_BCM1480_INT_WATCHDOG_TIMER_2     _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_2)
+#define M_BCM1480_INT_WATCHDOG_TIMER_3     _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_3)
+#define M_BCM1480_INT_PCI_ERROR                    _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_ERROR)
+#define M_BCM1480_INT_PCI_RESET                    _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_RESET)
+#define M_BCM1480_INT_NODE_CONTROLLER      _BCM1480_INT_MASK1(K_BCM1480_INT_NODE_CONTROLLER)
+#define M_BCM1480_INT_HOST_BRIDGE          _BCM1480_INT_MASK1(K_BCM1480_INT_HOST_BRIDGE)
+#define M_BCM1480_INT_PORT_0_FATAL         _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_FATAL)
+#define M_BCM1480_INT_PORT_0_NONFATAL      _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_NONFATAL)
+#define M_BCM1480_INT_PORT_1_FATAL         _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_FATAL)
+#define M_BCM1480_INT_PORT_1_NONFATAL      _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_NONFATAL)
+#define M_BCM1480_INT_PORT_2_FATAL         _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_FATAL)
+#define M_BCM1480_INT_PORT_2_NONFATAL      _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_NONFATAL)
+#define M_BCM1480_INT_LDT_SMI              _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_SMI)
+#define M_BCM1480_INT_LDT_NMI              _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_NMI)
+#define M_BCM1480_INT_LDT_INIT             _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_INIT)
+#define M_BCM1480_INT_LDT_STARTUP          _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_STARTUP)
+#define M_BCM1480_INT_LDT_EXT              _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_EXT)
+#define M_BCM1480_INT_SMB_0                _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_0)
+#define M_BCM1480_INT_SMB_1                _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_1)
+#define M_BCM1480_INT_PCMCIA               _BCM1480_INT_MASK1(K_BCM1480_INT_PCMCIA)
+#define M_BCM1480_INT_UART_0               _BCM1480_INT_MASK1(K_BCM1480_INT_UART_0)
+#define M_BCM1480_INT_UART_1               _BCM1480_INT_MASK1(K_BCM1480_INT_UART_1)
+#define M_BCM1480_INT_UART_2               _BCM1480_INT_MASK1(K_BCM1480_INT_UART_2)
+#define M_BCM1480_INT_UART_3               _BCM1480_INT_MASK1(K_BCM1480_INT_UART_3)
+#define M_BCM1480_INT_GPIO_4               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_4)
+#define M_BCM1480_INT_GPIO_5               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_5)
+#define M_BCM1480_INT_GPIO_6               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_6)
+#define M_BCM1480_INT_GPIO_7               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_7)
+#define M_BCM1480_INT_GPIO_8               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_8)
+#define M_BCM1480_INT_GPIO_9               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_9)
+#define M_BCM1480_INT_GPIO_10              _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_10)
+#define M_BCM1480_INT_GPIO_11              _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_11)
+#define M_BCM1480_INT_GPIO_12              _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_12)
+#define M_BCM1480_INT_GPIO_13              _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_13)
+#define M_BCM1480_INT_GPIO_14              _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_14)
+#define M_BCM1480_INT_GPIO_15              _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_15)

 
 /*
  * Interrupt mappings (Table 18)
  */
 
 
 /*
  * Interrupt mappings (Table 18)
  */
 

-#define K_BCM1480_INT_MAP_I0    0              /* interrupt pins on processor */
-#define K_BCM1480_INT_MAP_I1    1
-#define K_BCM1480_INT_MAP_I2    2
-#define K_BCM1480_INT_MAP_I3    3
-#define K_BCM1480_INT_MAP_I4    4
-#define K_BCM1480_INT_MAP_I5    5
-#define K_BCM1480_INT_MAP_NMI   6              /* nonmaskable */
-#define K_BCM1480_INT_MAP_DINT  7              /* debug interrupt */
+#define K_BCM1480_INT_MAP_I0   0               /* interrupt pins on processor */
+#define K_BCM1480_INT_MAP_I1   1
+#define K_BCM1480_INT_MAP_I2   2
+#define K_BCM1480_INT_MAP_I3   3
+#define K_BCM1480_INT_MAP_I4   4
+#define K_BCM1480_INT_MAP_I5   5
+#define K_BCM1480_INT_MAP_NMI  6               /* nonmaskable */
+#define K_BCM1480_INT_MAP_DINT 7               /* debug interrupt */

 
 /*
  * Interrupt LDT Set Register (Table 19)
  */
 
 
 /*
  * Interrupt LDT Set Register (Table 19)
  */
 

-#define S_BCM1480_INT_HT_INTMSG             0
-#define M_BCM1480_INT_HT_INTMSG             _SB_MAKEMASK(3, S_BCM1480_INT_HT_INTMSG)
-#define V_BCM1480_INT_HT_INTMSG(x)          _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTMSG)
-#define G_BCM1480_INT_HT_INTMSG(x)          _SB_GETVALUE(x, S_BCM1480_INT_HT_INTMSG, M_BCM1480_INT_HT_INTMSG)
+#define S_BCM1480_INT_HT_INTMSG                    0
+#define M_BCM1480_INT_HT_INTMSG                    _SB_MAKEMASK(3, S_BCM1480_INT_HT_INTMSG)
+#define V_BCM1480_INT_HT_INTMSG(x)         _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTMSG)
+#define G_BCM1480_INT_HT_INTMSG(x)         _SB_GETVALUE(x, S_BCM1480_INT_HT_INTMSG, M_BCM1480_INT_HT_INTMSG)

 
 

-#define K_BCM1480_INT_HT_INTMSG_FIXED       0
+#define K_BCM1480_INT_HT_INTMSG_FIXED      0

 #define K_BCM1480_INT_HT_INTMSG_ARBITRATED  1
 #define K_BCM1480_INT_HT_INTMSG_ARBITRATED  1

-#define K_BCM1480_INT_HT_INTMSG_SMI         2
-#define K_BCM1480_INT_HT_INTMSG_NMI         3
-#define K_BCM1480_INT_HT_INTMSG_INIT        4
-#define K_BCM1480_INT_HT_INTMSG_STARTUP     5
-#define K_BCM1480_INT_HT_INTMSG_EXTINT      6
+#define K_BCM1480_INT_HT_INTMSG_SMI        2
+#define K_BCM1480_INT_HT_INTMSG_NMI        3
+#define K_BCM1480_INT_HT_INTMSG_INIT       4
+#define K_BCM1480_INT_HT_INTMSG_STARTUP            5
+#define K_BCM1480_INT_HT_INTMSG_EXTINT     6

 #define K_BCM1480_INT_HT_INTMSG_RESERVED    7
 
 #define K_BCM1480_INT_HT_INTMSG_RESERVED    7
 

-#define M_BCM1480_INT_HT_TRIGGERMODE        _SB_MAKEMASK1(3)
-#define V_BCM1480_INT_HT_EDGETRIGGER        0
-#define V_BCM1480_INT_HT_LEVELTRIGGER       M_BCM1480_INT_HT_TRIGGERMODE
+#define M_BCM1480_INT_HT_TRIGGERMODE       _SB_MAKEMASK1(3)
+#define V_BCM1480_INT_HT_EDGETRIGGER       0
+#define V_BCM1480_INT_HT_LEVELTRIGGER      M_BCM1480_INT_HT_TRIGGERMODE

 
 

-#define M_BCM1480_INT_HT_DESTMODE           _SB_MAKEMASK1(4)
-#define V_BCM1480_INT_HT_PHYSICALDEST       0
-#define V_BCM1480_INT_HT_LOGICALDEST        M_BCM1480_INT_HT_DESTMODE
+#define M_BCM1480_INT_HT_DESTMODE          _SB_MAKEMASK1(4)
+#define V_BCM1480_INT_HT_PHYSICALDEST      0
+#define V_BCM1480_INT_HT_LOGICALDEST       M_BCM1480_INT_HT_DESTMODE

 
 

-#define S_BCM1480_INT_HT_INTDEST            5
-#define M_BCM1480_INT_HT_INTDEST            _SB_MAKEMASK(8, S_BCM1480_INT_HT_INTDEST)
-#define V_BCM1480_INT_HT_INTDEST(x)         _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTDEST)
-#define G_BCM1480_INT_HT_INTDEST(x)         _SB_GETVALUE(x, S_BCM1480_INT_HT_INTDEST, M_BCM1480_INT_HT_INTDEST)
+#define S_BCM1480_INT_HT_INTDEST           5
+#define M_BCM1480_INT_HT_INTDEST           _SB_MAKEMASK(8, S_BCM1480_INT_HT_INTDEST)
+#define V_BCM1480_INT_HT_INTDEST(x)        _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTDEST)
+#define G_BCM1480_INT_HT_INTDEST(x)        _SB_GETVALUE(x, S_BCM1480_INT_HT_INTDEST, M_BCM1480_INT_HT_INTDEST)

 
 

-#define S_BCM1480_INT_HT_VECTOR             13
-#define M_BCM1480_INT_HT_VECTOR             _SB_MAKEMASK(8, S_BCM1480_INT_HT_VECTOR)
-#define V_BCM1480_INT_HT_VECTOR(x)          _SB_MAKEVALUE(x, S_BCM1480_INT_HT_VECTOR)
-#define G_BCM1480_INT_HT_VECTOR(x)          _SB_GETVALUE(x, S_BCM1480_INT_HT_VECTOR, M_BCM1480_INT_HT_VECTOR)
+#define S_BCM1480_INT_HT_VECTOR                    13
+#define M_BCM1480_INT_HT_VECTOR                    _SB_MAKEMASK(8, S_BCM1480_INT_HT_VECTOR)
+#define V_BCM1480_INT_HT_VECTOR(x)         _SB_MAKEVALUE(x, S_BCM1480_INT_HT_VECTOR)
+#define G_BCM1480_INT_HT_VECTOR(x)         _SB_GETVALUE(x, S_BCM1480_INT_HT_VECTOR, M_BCM1480_INT_HT_VECTOR)

 
 /*
  * Vector prefix (Table 4-7)
  */
 
 #define M_BCM1480_HTVECT_RAISE_INTLDT_HIGH  0x00
 
 /*
  * Vector prefix (Table 4-7)
  */
 
 #define M_BCM1480_HTVECT_RAISE_INTLDT_HIGH  0x00

-#define M_BCM1480_HTVECT_RAISE_MBOX_0       0x40
+#define M_BCM1480_HTVECT_RAISE_MBOX_0      0x40

 #define M_BCM1480_HTVECT_RAISE_INTLDT_LO    0x80
 #define M_BCM1480_HTVECT_RAISE_INTLDT_LO    0x80

-#define M_BCM1480_HTVECT_RAISE_MBOX_1       0xC0
+#define M_BCM1480_HTVECT_RAISE_MBOX_1      0xC0

 
 #endif /* _BCM1480_INT_H */
 
 #endif /* _BCM1480_INT_H */

diff --git a/arch/mips/include/asm/sibyte/bcm1480_l2c.h b/arch/mips/include/asm/sibyte/bcm1480_l2c.h
index 725d38cb9d1c7b7d6f3103ae439234db957879ee..910e5c7e1b08cede3963514910f0d3dafeb5b3de 100644 (file)
--- a/arch/mips/include/asm/sibyte/bcm1480_l2c.h
+++ b/arch/mips/include/asm/sibyte/bcm1480_l2c.h
@@ -39,120 +39,120 @@
  * Format of level 2 cache management address (Table 55)
  */
 
  * Format of level 2 cache management address (Table 55)
  */
 

-#define S_BCM1480_L2C_MGMT_INDEX            5
-#define M_BCM1480_L2C_MGMT_INDEX            _SB_MAKEMASK(12, S_BCM1480_L2C_MGMT_INDEX)
-#define V_BCM1480_L2C_MGMT_INDEX(x)         _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_INDEX)
-#define G_BCM1480_L2C_MGMT_INDEX(x)         _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_INDEX, M_BCM1480_L2C_MGMT_INDEX)
+#define S_BCM1480_L2C_MGMT_INDEX           5
+#define M_BCM1480_L2C_MGMT_INDEX           _SB_MAKEMASK(12, S_BCM1480_L2C_MGMT_INDEX)
+#define V_BCM1480_L2C_MGMT_INDEX(x)        _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_INDEX)
+#define G_BCM1480_L2C_MGMT_INDEX(x)        _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_INDEX, M_BCM1480_L2C_MGMT_INDEX)

 
 

-#define S_BCM1480_L2C_MGMT_WAY              17
-#define M_BCM1480_L2C_MGMT_WAY              _SB_MAKEMASK(3, S_BCM1480_L2C_MGMT_WAY)
-#define V_BCM1480_L2C_MGMT_WAY(x)           _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_WAY)
-#define G_BCM1480_L2C_MGMT_WAY(x)           _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_WAY, M_BCM1480_L2C_MGMT_WAY)
+#define S_BCM1480_L2C_MGMT_WAY             17
+#define M_BCM1480_L2C_MGMT_WAY             _SB_MAKEMASK(3, S_BCM1480_L2C_MGMT_WAY)
+#define V_BCM1480_L2C_MGMT_WAY(x)          _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_WAY)
+#define G_BCM1480_L2C_MGMT_WAY(x)          _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_WAY, M_BCM1480_L2C_MGMT_WAY)

 
 

-#define M_BCM1480_L2C_MGMT_DIRTY            _SB_MAKEMASK1(20)
-#define M_BCM1480_L2C_MGMT_VALID            _SB_MAKEMASK1(21)
+#define M_BCM1480_L2C_MGMT_DIRTY           _SB_MAKEMASK1(20)
+#define M_BCM1480_L2C_MGMT_VALID           _SB_MAKEMASK1(21)

 
 

-#define S_BCM1480_L2C_MGMT_ECC_DIAG         22
-#define M_BCM1480_L2C_MGMT_ECC_DIAG         _SB_MAKEMASK(2, S_BCM1480_L2C_MGMT_ECC_DIAG)
-#define V_BCM1480_L2C_MGMT_ECC_DIAG(x)      _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG)
-#define G_BCM1480_L2C_MGMT_ECC_DIAG(x)      _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG, M_BCM1480_L2C_MGMT_ECC_DIAG)
+#define S_BCM1480_L2C_MGMT_ECC_DIAG        22
+#define M_BCM1480_L2C_MGMT_ECC_DIAG        _SB_MAKEMASK(2, S_BCM1480_L2C_MGMT_ECC_DIAG)
+#define V_BCM1480_L2C_MGMT_ECC_DIAG(x)     _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG)
+#define G_BCM1480_L2C_MGMT_ECC_DIAG(x)     _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG, M_BCM1480_L2C_MGMT_ECC_DIAG)

 
 

-#define A_BCM1480_L2C_MGMT_TAG_BASE         0x00D0000000
+#define A_BCM1480_L2C_MGMT_TAG_BASE        0x00D0000000

 
 

-#define BCM1480_L2C_ENTRIES_PER_WAY         4096
-#define BCM1480_L2C_NUM_WAYS                8
+#define BCM1480_L2C_ENTRIES_PER_WAY        4096
+#define BCM1480_L2C_NUM_WAYS               8

 
 
 /*
  * Level 2 Cache Tag register (Table 59)
  */
 
 
 
 /*
  * Level 2 Cache Tag register (Table 59)
  */
 

-#define S_BCM1480_L2C_TAG_MBZ               0
-#define M_BCM1480_L2C_TAG_MBZ               _SB_MAKEMASK(5, S_BCM1480_L2C_TAG_MBZ)
+#define S_BCM1480_L2C_TAG_MBZ              0
+#define M_BCM1480_L2C_TAG_MBZ              _SB_MAKEMASK(5, S_BCM1480_L2C_TAG_MBZ)

 
 

-#define S_BCM1480_L2C_TAG_INDEX             5
-#define M_BCM1480_L2C_TAG_INDEX             _SB_MAKEMASK(12, S_BCM1480_L2C_TAG_INDEX)
-#define V_BCM1480_L2C_TAG_INDEX(x)          _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_INDEX)
-#define G_BCM1480_L2C_TAG_INDEX(x)          _SB_GETVALUE(x, S_BCM1480_L2C_TAG_INDEX, M_BCM1480_L2C_TAG_INDEX)
+#define S_BCM1480_L2C_TAG_INDEX                    5
+#define M_BCM1480_L2C_TAG_INDEX                    _SB_MAKEMASK(12, S_BCM1480_L2C_TAG_INDEX)
+#define V_BCM1480_L2C_TAG_INDEX(x)         _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_INDEX)
+#define G_BCM1480_L2C_TAG_INDEX(x)         _SB_GETVALUE(x, S_BCM1480_L2C_TAG_INDEX, M_BCM1480_L2C_TAG_INDEX)

 
 /* Note that index bit 16 is also tag bit 40 */
 
 /* Note that index bit 16 is also tag bit 40 */

-#define S_BCM1480_L2C_TAG_TAG               17
-#define M_BCM1480_L2C_TAG_TAG               _SB_MAKEMASK(23, S_BCM1480_L2C_TAG_TAG)
-#define V_BCM1480_L2C_TAG_TAG(x)            _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_TAG)
-#define G_BCM1480_L2C_TAG_TAG(x)            _SB_GETVALUE(x, S_BCM1480_L2C_TAG_TAG, M_BCM1480_L2C_TAG_TAG)
+#define S_BCM1480_L2C_TAG_TAG              17
+#define M_BCM1480_L2C_TAG_TAG              _SB_MAKEMASK(23, S_BCM1480_L2C_TAG_TAG)
+#define V_BCM1480_L2C_TAG_TAG(x)           _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_TAG)
+#define G_BCM1480_L2C_TAG_TAG(x)           _SB_GETVALUE(x, S_BCM1480_L2C_TAG_TAG, M_BCM1480_L2C_TAG_TAG)

 
 

-#define S_BCM1480_L2C_TAG_ECC               40
-#define M_BCM1480_L2C_TAG_ECC               _SB_MAKEMASK(6, S_BCM1480_L2C_TAG_ECC)
-#define V_BCM1480_L2C_TAG_ECC(x)            _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_ECC)
-#define G_BCM1480_L2C_TAG_ECC(x)            _SB_GETVALUE(x, S_BCM1480_L2C_TAG_ECC, M_BCM1480_L2C_TAG_ECC)
+#define S_BCM1480_L2C_TAG_ECC              40
+#define M_BCM1480_L2C_TAG_ECC              _SB_MAKEMASK(6, S_BCM1480_L2C_TAG_ECC)
+#define V_BCM1480_L2C_TAG_ECC(x)           _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_ECC)
+#define G_BCM1480_L2C_TAG_ECC(x)           _SB_GETVALUE(x, S_BCM1480_L2C_TAG_ECC, M_BCM1480_L2C_TAG_ECC)

 
 

-#define S_BCM1480_L2C_TAG_WAY               46
-#define M_BCM1480_L2C_TAG_WAY               _SB_MAKEMASK(3, S_BCM1480_L2C_TAG_WAY)
-#define V_BCM1480_L2C_TAG_WAY(x)            _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_WAY)
-#define G_BCM1480_L2C_TAG_WAY(x)            _SB_GETVALUE(x, S_BCM1480_L2C_TAG_WAY, M_BCM1480_L2C_TAG_WAY)
+#define S_BCM1480_L2C_TAG_WAY              46
+#define M_BCM1480_L2C_TAG_WAY              _SB_MAKEMASK(3, S_BCM1480_L2C_TAG_WAY)
+#define V_BCM1480_L2C_TAG_WAY(x)           _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_WAY)
+#define G_BCM1480_L2C_TAG_WAY(x)           _SB_GETVALUE(x, S_BCM1480_L2C_TAG_WAY, M_BCM1480_L2C_TAG_WAY)

 
 

-#define M_BCM1480_L2C_TAG_DIRTY             _SB_MAKEMASK1(49)
-#define M_BCM1480_L2C_TAG_VALID             _SB_MAKEMASK1(50)
+#define M_BCM1480_L2C_TAG_DIRTY                    _SB_MAKEMASK1(49)
+#define M_BCM1480_L2C_TAG_VALID                    _SB_MAKEMASK1(50)

 
 

-#define S_BCM1480_L2C_DATA_ECC              51
-#define M_BCM1480_L2C_DATA_ECC              _SB_MAKEMASK(10, S_BCM1480_L2C_DATA_ECC)
-#define V_BCM1480_L2C_DATA_ECC(x)           _SB_MAKEVALUE(x, S_BCM1480_L2C_DATA_ECC)
-#define G_BCM1480_L2C_DATA_ECC(x)           _SB_GETVALUE(x, S_BCM1480_L2C_DATA_ECC, M_BCM1480_L2C_DATA_ECC)
+#define S_BCM1480_L2C_DATA_ECC             51
+#define M_BCM1480_L2C_DATA_ECC             _SB_MAKEMASK(10, S_BCM1480_L2C_DATA_ECC)
+#define V_BCM1480_L2C_DATA_ECC(x)          _SB_MAKEVALUE(x, S_BCM1480_L2C_DATA_ECC)
+#define G_BCM1480_L2C_DATA_ECC(x)          _SB_GETVALUE(x, S_BCM1480_L2C_DATA_ECC, M_BCM1480_L2C_DATA_ECC)

 
 
 /*
  * L2 Misc0 Value Register (Table 60)
  */
 
 
 
 /*
  * L2 Misc0 Value Register (Table 60)
  */
 

-#define S_BCM1480_L2C_MISC0_WAY_REMOTE      0
-#define M_BCM1480_L2C_MISC0_WAY_REMOTE      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_REMOTE)
+#define S_BCM1480_L2C_MISC0_WAY_REMOTE     0
+#define M_BCM1480_L2C_MISC0_WAY_REMOTE     _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_REMOTE)

 #define G_BCM1480_L2C_MISC0_WAY_REMOTE(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_REMOTE, M_BCM1480_L2C_MISC0_WAY_REMOTE)
 
 #define G_BCM1480_L2C_MISC0_WAY_REMOTE(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_REMOTE, M_BCM1480_L2C_MISC0_WAY_REMOTE)
 

-#define S_BCM1480_L2C_MISC0_WAY_LOCAL       8
-#define M_BCM1480_L2C_MISC0_WAY_LOCAL       _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_LOCAL)
+#define S_BCM1480_L2C_MISC0_WAY_LOCAL      8
+#define M_BCM1480_L2C_MISC0_WAY_LOCAL      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_LOCAL)

 #define G_BCM1480_L2C_MISC0_WAY_LOCAL(x)    _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_LOCAL, M_BCM1480_L2C_MISC0_WAY_LOCAL)
 
 #define G_BCM1480_L2C_MISC0_WAY_LOCAL(x)    _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_LOCAL, M_BCM1480_L2C_MISC0_WAY_LOCAL)
 

-#define S_BCM1480_L2C_MISC0_WAY_ENABLE      16
-#define M_BCM1480_L2C_MISC0_WAY_ENABLE      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_ENABLE)
+#define S_BCM1480_L2C_MISC0_WAY_ENABLE     16
+#define M_BCM1480_L2C_MISC0_WAY_ENABLE     _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_ENABLE)

 #define G_BCM1480_L2C_MISC0_WAY_ENABLE(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_ENABLE, M_BCM1480_L2C_MISC0_WAY_ENABLE)
 
 #define S_BCM1480_L2C_MISC0_CACHE_DISABLE   24
 #define M_BCM1480_L2C_MISC0_CACHE_DISABLE   _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_DISABLE)
 #define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_DISABLE, M_BCM1480_L2C_MISC0_CACHE_DISABLE)
 
 #define G_BCM1480_L2C_MISC0_WAY_ENABLE(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_ENABLE, M_BCM1480_L2C_MISC0_WAY_ENABLE)
 
 #define S_BCM1480_L2C_MISC0_CACHE_DISABLE   24
 #define M_BCM1480_L2C_MISC0_CACHE_DISABLE   _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_DISABLE)
 #define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_DISABLE, M_BCM1480_L2C_MISC0_CACHE_DISABLE)
 

-#define S_BCM1480_L2C_MISC0_CACHE_QUAD      26
-#define M_BCM1480_L2C_MISC0_CACHE_QUAD      _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_QUAD)
+#define S_BCM1480_L2C_MISC0_CACHE_QUAD     26
+#define M_BCM1480_L2C_MISC0_CACHE_QUAD     _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_QUAD)

 #define G_BCM1480_L2C_MISC0_CACHE_QUAD(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_QUAD, M_BCM1480_L2C_MISC0_CACHE_QUAD)
 
 #define G_BCM1480_L2C_MISC0_CACHE_QUAD(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_QUAD, M_BCM1480_L2C_MISC0_CACHE_QUAD)
 

-#define S_BCM1480_L2C_MISC0_MC_PRIORITY      30
-#define M_BCM1480_L2C_MISC0_MC_PRIORITY      _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY)
+#define S_BCM1480_L2C_MISC0_MC_PRIORITY             30
+#define M_BCM1480_L2C_MISC0_MC_PRIORITY             _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY)

 
 

-#define S_BCM1480_L2C_MISC0_ECC_CLEANUP      31
-#define M_BCM1480_L2C_MISC0_ECC_CLEANUP      _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_ECC_CLEANUP)
+#define S_BCM1480_L2C_MISC0_ECC_CLEANUP             31
+#define M_BCM1480_L2C_MISC0_ECC_CLEANUP             _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_ECC_CLEANUP)

 
 
 /*
  * L2 Misc1 Value Register (Table 60)
  */
 
 
 
 /*
  * L2 Misc1 Value Register (Table 60)
  */
 

-#define S_BCM1480_L2C_MISC1_WAY_AGENT_0      0
-#define M_BCM1480_L2C_MISC1_WAY_AGENT_0      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_0)
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_0             0
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_0             _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_0)

 #define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_0, M_BCM1480_L2C_MISC1_WAY_AGENT_0)
 
 #define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_0, M_BCM1480_L2C_MISC1_WAY_AGENT_0)
 

-#define S_BCM1480_L2C_MISC1_WAY_AGENT_1      8
-#define M_BCM1480_L2C_MISC1_WAY_AGENT_1      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_1)
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_1             8
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_1             _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_1)

 #define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_1, M_BCM1480_L2C_MISC1_WAY_AGENT_1)
 
 #define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_1, M_BCM1480_L2C_MISC1_WAY_AGENT_1)
 

-#define S_BCM1480_L2C_MISC1_WAY_AGENT_2      16
-#define M_BCM1480_L2C_MISC1_WAY_AGENT_2      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_2)
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_2             16
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_2             _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_2)

 #define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_2, M_BCM1480_L2C_MISC1_WAY_AGENT_2)
 
 #define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_2, M_BCM1480_L2C_MISC1_WAY_AGENT_2)
 

-#define S_BCM1480_L2C_MISC1_WAY_AGENT_3      24
-#define M_BCM1480_L2C_MISC1_WAY_AGENT_3      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_3)
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_3             24
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_3             _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_3)

 #define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_3, M_BCM1480_L2C_MISC1_WAY_AGENT_3)
 
 #define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_3, M_BCM1480_L2C_MISC1_WAY_AGENT_3)
 

-#define S_BCM1480_L2C_MISC1_WAY_AGENT_4      32
-#define M_BCM1480_L2C_MISC1_WAY_AGENT_4      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_4)
+#define S_BCM1480_L2C_MISC1_WAY_AGENT_4             32
+#define M_BCM1480_L2C_MISC1_WAY_AGENT_4             _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_4)

 #define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_4, M_BCM1480_L2C_MISC1_WAY_AGENT_4)
 
 
 #define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_4, M_BCM1480_L2C_MISC1_WAY_AGENT_4)
 
 


@@ -160,16 +160,16 @@
  * L2 Misc2 Value Register (Table 60)
  */
 
  * L2 Misc2 Value Register (Table 60)
  */
 

-#define S_BCM1480_L2C_MISC2_WAY_AGENT_8      0
-#define M_BCM1480_L2C_MISC2_WAY_AGENT_8      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_8)
+#define S_BCM1480_L2C_MISC2_WAY_AGENT_8             0
+#define M_BCM1480_L2C_MISC2_WAY_AGENT_8             _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_8)

 #define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_8, M_BCM1480_L2C_MISC2_WAY_AGENT_8)
 
 #define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_8, M_BCM1480_L2C_MISC2_WAY_AGENT_8)
 

-#define S_BCM1480_L2C_MISC2_WAY_AGENT_9      8
-#define M_BCM1480_L2C_MISC2_WAY_AGENT_9      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_9)
+#define S_BCM1480_L2C_MISC2_WAY_AGENT_9             8
+#define M_BCM1480_L2C_MISC2_WAY_AGENT_9             _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_9)

 #define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_9, M_BCM1480_L2C_MISC2_WAY_AGENT_9)
 
 #define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_9, M_BCM1480_L2C_MISC2_WAY_AGENT_9)
 

-#define S_BCM1480_L2C_MISC2_WAY_AGENT_A      16
-#define M_BCM1480_L2C_MISC2_WAY_AGENT_A      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_A)
+#define S_BCM1480_L2C_MISC2_WAY_AGENT_A             16
+#define M_BCM1480_L2C_MISC2_WAY_AGENT_A             _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_A)

 #define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_A, M_BCM1480_L2C_MISC2_WAY_AGENT_A)
 
 
 #define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_A, M_BCM1480_L2C_MISC2_WAY_AGENT_A)
 
 

diff --git a/arch/mips/include/asm/sibyte/bcm1480_mc.h b/arch/mips/include/asm/sibyte/bcm1480_mc.h
index 4307a758e3bf336c0d73c679917fd834376df610..86908fdb403253cfd3ce11310bc0b80c53654b09 100644 (file)
--- a/arch/mips/include/asm/sibyte/bcm1480_mc.h
+++ b/arch/mips/include/asm/sibyte/bcm1480_mc.h
@@ -1,7 +1,7 @@
 /*  *********************************************************************
     *  BCM1280/BCM1480 Board Support Package
     *
 /*  *********************************************************************
     *  BCM1280/BCM1480 Board Support Package
     *

-    *  Memory Controller constants              File: bcm1480_mc.h
+    *  Memory Controller constants             File: bcm1480_mc.h

     *
     *  This module contains constants and macros useful for
     *  programming the memory controller.
     *
     *  This module contains constants and macros useful for
     *  programming the memory controller.


@@ -39,33 +39,33 @@
  * Memory Channel Configuration Register (Table 81)
  */
 
  * Memory Channel Configuration Register (Table 81)
  */
 

-#define S_BCM1480_MC_INTLV0                 0
-#define M_BCM1480_MC_INTLV0                 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0)
-#define V_BCM1480_MC_INTLV0(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0)
-#define G_BCM1480_MC_INTLV0(x)              _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0)
-#define V_BCM1480_MC_INTLV0_DEFAULT         V_BCM1480_MC_INTLV0(0)
-
-#define S_BCM1480_MC_INTLV1                 8
-#define M_BCM1480_MC_INTLV1                 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1)
-#define V_BCM1480_MC_INTLV1(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1)
-#define G_BCM1480_MC_INTLV1(x)              _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1)
-#define V_BCM1480_MC_INTLV1_DEFAULT         V_BCM1480_MC_INTLV1(0)
-
-#define S_BCM1480_MC_INTLV2                 16
-#define M_BCM1480_MC_INTLV2                 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV2)
-#define V_BCM1480_MC_INTLV2(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV2)
-#define G_BCM1480_MC_INTLV2(x)              _SB_GETVALUE(x, S_BCM1480_MC_INTLV2, M_BCM1480_MC_INTLV2)
-#define V_BCM1480_MC_INTLV2_DEFAULT         V_BCM1480_MC_INTLV2(0)
-
-#define S_BCM1480_MC_CS_MODE                32
-#define M_BCM1480_MC_CS_MODE                _SB_MAKEMASK(8, S_BCM1480_MC_CS_MODE)
-#define V_BCM1480_MC_CS_MODE(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_CS_MODE)
-#define G_BCM1480_MC_CS_MODE(x)             _SB_GETVALUE(x, S_BCM1480_MC_CS_MODE, M_BCM1480_MC_CS_MODE)
-#define V_BCM1480_MC_CS_MODE_DEFAULT        V_BCM1480_MC_CS_MODE(0)
-
-#define V_BCM1480_MC_CONFIG_DEFAULT         (V_BCM1480_MC_INTLV0_DEFAULT  | \
-                                     V_BCM1480_MC_INTLV1_DEFAULT  | \
-                                     V_BCM1480_MC_INTLV2_DEFAULT  | \
+#define S_BCM1480_MC_INTLV0                0
+#define M_BCM1480_MC_INTLV0                _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0)
+#define V_BCM1480_MC_INTLV0(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0)
+#define G_BCM1480_MC_INTLV0(x)             _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0)
+#define V_BCM1480_MC_INTLV0_DEFAULT        V_BCM1480_MC_INTLV0(0)
+
+#define S_BCM1480_MC_INTLV1                8
+#define M_BCM1480_MC_INTLV1                _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1)
+#define V_BCM1480_MC_INTLV1(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1)
+#define G_BCM1480_MC_INTLV1(x)             _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1)
+#define V_BCM1480_MC_INTLV1_DEFAULT        V_BCM1480_MC_INTLV1(0)
+
+#define S_BCM1480_MC_INTLV2                16
+#define M_BCM1480_MC_INTLV2                _SB_MAKEMASK(6, S_BCM1480_MC_INTLV2)
+#define V_BCM1480_MC_INTLV2(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV2)
+#define G_BCM1480_MC_INTLV2(x)             _SB_GETVALUE(x, S_BCM1480_MC_INTLV2, M_BCM1480_MC_INTLV2)
+#define V_BCM1480_MC_INTLV2_DEFAULT        V_BCM1480_MC_INTLV2(0)
+
+#define S_BCM1480_MC_CS_MODE               32
+#define M_BCM1480_MC_CS_MODE               _SB_MAKEMASK(8, S_BCM1480_MC_CS_MODE)
+#define V_BCM1480_MC_CS_MODE(x)                    _SB_MAKEVALUE(x, S_BCM1480_MC_CS_MODE)
+#define G_BCM1480_MC_CS_MODE(x)                    _SB_GETVALUE(x, S_BCM1480_MC_CS_MODE, M_BCM1480_MC_CS_MODE)
+#define V_BCM1480_MC_CS_MODE_DEFAULT       V_BCM1480_MC_CS_MODE(0)
+
+#define V_BCM1480_MC_CONFIG_DEFAULT        (V_BCM1480_MC_INTLV0_DEFAULT  | \
+                                    V_BCM1480_MC_INTLV1_DEFAULT  | \
+                                    V_BCM1480_MC_INTLV2_DEFAULT  | \

                                     V_BCM1480_MC_CS_MODE_DEFAULT)
 
 #define K_BCM1480_MC_CS01_MODE             0x03
                                     V_BCM1480_MC_CS_MODE_DEFAULT)
 
 #define K_BCM1480_MC_CS01_MODE             0x03


@@ -80,254 +80,254 @@
  * Chip Select Start Address Register (Table 82)
  */
 
  * Chip Select Start Address Register (Table 82)
  */
 

-#define S_BCM1480_MC_CS0_START              0
-#define M_BCM1480_MC_CS0_START              _SB_MAKEMASK(12, S_BCM1480_MC_CS0_START)
-#define V_BCM1480_MC_CS0_START(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_START)
-#define G_BCM1480_MC_CS0_START(x)           _SB_GETVALUE(x, S_BCM1480_MC_CS0_START, M_BCM1480_MC_CS0_START)
+#define S_BCM1480_MC_CS0_START             0
+#define M_BCM1480_MC_CS0_START             _SB_MAKEMASK(12, S_BCM1480_MC_CS0_START)
+#define V_BCM1480_MC_CS0_START(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_START)
+#define G_BCM1480_MC_CS0_START(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS0_START, M_BCM1480_MC_CS0_START)

 
 

-#define S_BCM1480_MC_CS1_START              16
-#define M_BCM1480_MC_CS1_START              _SB_MAKEMASK(12, S_BCM1480_MC_CS1_START)
-#define V_BCM1480_MC_CS1_START(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_START)
-#define G_BCM1480_MC_CS1_START(x)           _SB_GETVALUE(x, S_BCM1480_MC_CS1_START, M_BCM1480_MC_CS1_START)
+#define S_BCM1480_MC_CS1_START             16
+#define M_BCM1480_MC_CS1_START             _SB_MAKEMASK(12, S_BCM1480_MC_CS1_START)
+#define V_BCM1480_MC_CS1_START(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_START)
+#define G_BCM1480_MC_CS1_START(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS1_START, M_BCM1480_MC_CS1_START)

 
 

-#define S_BCM1480_MC_CS2_START              32
-#define M_BCM1480_MC_CS2_START              _SB_MAKEMASK(12, S_BCM1480_MC_CS2_START)
-#define V_BCM1480_MC_CS2_START(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_START)
-#define G_BCM1480_MC_CS2_START(x)           _SB_GETVALUE(x, S_BCM1480_MC_CS2_START, M_BCM1480_MC_CS2_START)
+#define S_BCM1480_MC_CS2_START             32
+#define M_BCM1480_MC_CS2_START             _SB_MAKEMASK(12, S_BCM1480_MC_CS2_START)
+#define V_BCM1480_MC_CS2_START(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_START)
+#define G_BCM1480_MC_CS2_START(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS2_START, M_BCM1480_MC_CS2_START)

 
 

-#define S_BCM1480_MC_CS3_START              48
-#define M_BCM1480_MC_CS3_START              _SB_MAKEMASK(12, S_BCM1480_MC_CS3_START)
-#define V_BCM1480_MC_CS3_START(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_START)
-#define G_BCM1480_MC_CS3_START(x)           _SB_GETVALUE(x, S_BCM1480_MC_CS3_START, M_BCM1480_MC_CS3_START)
+#define S_BCM1480_MC_CS3_START             48
+#define M_BCM1480_MC_CS3_START             _SB_MAKEMASK(12, S_BCM1480_MC_CS3_START)
+#define V_BCM1480_MC_CS3_START(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_START)
+#define G_BCM1480_MC_CS3_START(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS3_START, M_BCM1480_MC_CS3_START)

 
 /*
  * Chip Select End Address Register (Table 83)
  */
 
 
 /*
  * Chip Select End Address Register (Table 83)
  */
 

-#define S_BCM1480_MC_CS0_END                0
-#define M_BCM1480_MC_CS0_END                _SB_MAKEMASK(12, S_BCM1480_MC_CS0_END)
-#define V_BCM1480_MC_CS0_END(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_END)
-#define G_BCM1480_MC_CS0_END(x)             _SB_GETVALUE(x, S_BCM1480_MC_CS0_END, M_BCM1480_MC_CS0_END)
+#define S_BCM1480_MC_CS0_END               0
+#define M_BCM1480_MC_CS0_END               _SB_MAKEMASK(12, S_BCM1480_MC_CS0_END)
+#define V_BCM1480_MC_CS0_END(x)                    _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_END)
+#define G_BCM1480_MC_CS0_END(x)                    _SB_GETVALUE(x, S_BCM1480_MC_CS0_END, M_BCM1480_MC_CS0_END)

 
 

-#define S_BCM1480_MC_CS1_END                16
-#define M_BCM1480_MC_CS1_END                _SB_MAKEMASK(12, S_BCM1480_MC_CS1_END)
-#define V_BCM1480_MC_CS1_END(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_END)
-#define G_BCM1480_MC_CS1_END(x)             _SB_GETVALUE(x, S_BCM1480_MC_CS1_END, M_BCM1480_MC_CS1_END)
+#define S_BCM1480_MC_CS1_END               16
+#define M_BCM1480_MC_CS1_END               _SB_MAKEMASK(12, S_BCM1480_MC_CS1_END)
+#define V_BCM1480_MC_CS1_END(x)                    _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_END)
+#define G_BCM1480_MC_CS1_END(x)                    _SB_GETVALUE(x, S_BCM1480_MC_CS1_END, M_BCM1480_MC_CS1_END)

 
 

-#define S_BCM1480_MC_CS2_END                32
-#define M_BCM1480_MC_CS2_END                _SB_MAKEMASK(12, S_BCM1480_MC_CS2_END)
-#define V_BCM1480_MC_CS2_END(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_END)
-#define G_BCM1480_MC_CS2_END(x)             _SB_GETVALUE(x, S_BCM1480_MC_CS2_END, M_BCM1480_MC_CS2_END)
+#define S_BCM1480_MC_CS2_END               32
+#define M_BCM1480_MC_CS2_END               _SB_MAKEMASK(12, S_BCM1480_MC_CS2_END)
+#define V_BCM1480_MC_CS2_END(x)                    _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_END)
+#define G_BCM1480_MC_CS2_END(x)                    _SB_GETVALUE(x, S_BCM1480_MC_CS2_END, M_BCM1480_MC_CS2_END)

 
 

-#define S_BCM1480_MC_CS3_END                48
-#define M_BCM1480_MC_CS3_END                _SB_MAKEMASK(12, S_BCM1480_MC_CS3_END)
-#define V_BCM1480_MC_CS3_END(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_END)
-#define G_BCM1480_MC_CS3_END(x)             _SB_GETVALUE(x, S_BCM1480_MC_CS3_END, M_BCM1480_MC_CS3_END)
+#define S_BCM1480_MC_CS3_END               48
+#define M_BCM1480_MC_CS3_END               _SB_MAKEMASK(12, S_BCM1480_MC_CS3_END)
+#define V_BCM1480_MC_CS3_END(x)                    _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_END)
+#define G_BCM1480_MC_CS3_END(x)                    _SB_GETVALUE(x, S_BCM1480_MC_CS3_END, M_BCM1480_MC_CS3_END)

 
 /*
  * Row Address Bit Select Register 0 (Table 84)
  */
 
 
 /*
  * Row Address Bit Select Register 0 (Table 84)
  */
 

-#define S_BCM1480_MC_ROW00                  0
-#define M_BCM1480_MC_ROW00                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW00)
-#define V_BCM1480_MC_ROW00(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW00)
-#define G_BCM1480_MC_ROW00(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW00, M_BCM1480_MC_ROW00)
-
-#define S_BCM1480_MC_ROW01                  8
-#define M_BCM1480_MC_ROW01                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW01)
-#define V_BCM1480_MC_ROW01(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW01)
-#define G_BCM1480_MC_ROW01(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW01, M_BCM1480_MC_ROW01)
-
-#define S_BCM1480_MC_ROW02                  16
-#define M_BCM1480_MC_ROW02                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW02)
-#define V_BCM1480_MC_ROW02(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW02)
-#define G_BCM1480_MC_ROW02(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW02, M_BCM1480_MC_ROW02)
-
-#define S_BCM1480_MC_ROW03                  24
-#define M_BCM1480_MC_ROW03                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW03)
-#define V_BCM1480_MC_ROW03(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW03)
-#define G_BCM1480_MC_ROW03(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW03, M_BCM1480_MC_ROW03)
-
-#define S_BCM1480_MC_ROW04                  32
-#define M_BCM1480_MC_ROW04                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW04)
-#define V_BCM1480_MC_ROW04(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW04)
-#define G_BCM1480_MC_ROW04(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW04, M_BCM1480_MC_ROW04)
-
-#define S_BCM1480_MC_ROW05                  40
-#define M_BCM1480_MC_ROW05                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW05)
-#define V_BCM1480_MC_ROW05(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW05)
-#define G_BCM1480_MC_ROW05(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW05, M_BCM1480_MC_ROW05)
-
-#define S_BCM1480_MC_ROW06                  48
-#define M_BCM1480_MC_ROW06                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW06)
-#define V_BCM1480_MC_ROW06(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW06)
-#define G_BCM1480_MC_ROW06(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW06, M_BCM1480_MC_ROW06)
-
-#define S_BCM1480_MC_ROW07                  56
-#define M_BCM1480_MC_ROW07                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW07)
-#define V_BCM1480_MC_ROW07(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW07)
-#define G_BCM1480_MC_ROW07(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW07, M_BCM1480_MC_ROW07)
+#define S_BCM1480_MC_ROW00                 0
+#define M_BCM1480_MC_ROW00                 _SB_MAKEMASK(6, S_BCM1480_MC_ROW00)
+#define V_BCM1480_MC_ROW00(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_ROW00)
+#define G_BCM1480_MC_ROW00(x)              _SB_GETVALUE(x, S_BCM1480_MC_ROW00, M_BCM1480_MC_ROW00)
+
+#define S_BCM1480_MC_ROW01                 8
+#define M_BCM1480_MC_ROW01                 _SB_MAKEMASK(6, S_BCM1480_MC_ROW01)
+#define V_BCM1480_MC_ROW01(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_ROW01)
+#define G_BCM1480_MC_ROW01(x)              _SB_GETVALUE(x, S_BCM1480_MC_ROW01, M_BCM1480_MC_ROW01)
+
+#define S_BCM1480_MC_ROW02                 16
+#define M_BCM1480_MC_ROW02                 _SB_MAKEMASK(6, S_BCM1480_MC_ROW02)
+#define V_BCM1480_MC_ROW02(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_ROW02)
+#define G_BCM1480_MC_ROW02(x)              _SB_GETVALUE(x, S_BCM1480_MC_ROW02, M_BCM1480_MC_ROW02)
+
+#define S_BCM1480_MC_ROW03                 24
+#define M_BCM1480_MC_ROW03                 _SB_MAKEMASK(6, S_BCM1480_MC_ROW03)
+#define V_BCM1480_MC_ROW03(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_ROW03)
+#define G_BCM1480_MC_ROW03(x)              _SB_GETVALUE(x, S_BCM1480_MC_ROW03, M_BCM1480_MC_ROW03)
+
+#define S_BCM1480_MC_ROW04                 32
+#define M_BCM1480_MC_ROW04                 _SB_MAKEMASK(6, S_BCM1480_MC_ROW04)
+#define V_BCM1480_MC_ROW04(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_ROW04)
+#define G_BCM1480_MC_ROW04(x)              _SB_GETVALUE(x, S_BCM1480_MC_ROW04, M_BCM1480_MC_ROW04)
+
+#define S_BCM1480_MC_ROW05                 40
+#define M_BCM1480_MC_ROW05                 _SB_MAKEMASK(6, S_BCM1480_MC_ROW05)
+#define V_BCM1480_MC_ROW05(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_ROW05)
+#define G_BCM1480_MC_ROW05(x)              _SB_GETVALUE(x, S_BCM1480_MC_ROW05, M_BCM1480_MC_ROW05)
+
+#define S_BCM1480_MC_ROW06                 48
+#define M_BCM1480_MC_ROW06                 _SB_MAKEMASK(6, S_BCM1480_MC_ROW06)
+#define V_BCM1480_MC_ROW06(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_ROW06)
+#define G_BCM1480_MC_ROW06(x)              _SB_GETVALUE(x, S_BCM1480_MC_ROW06, M_BCM1480_MC_ROW06)
+
+#define S_BCM1480_MC_ROW07                 56
+#define M_BCM1480_MC_ROW07                 _SB_MAKEMASK(6, S_BCM1480_MC_ROW07)
+#define V_BCM1480_MC_ROW07(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_ROW07)
+#define G_BCM1480_MC_ROW07(x)              _SB_GETVALUE(x, S_BCM1480_MC_ROW07, M_BCM1480_MC_ROW07)

 
 /*
  * Row Address Bit Select Register 1 (Table 85)
  */
 
 
 /*
  * Row Address Bit Select Register 1 (Table 85)
  */
 

-#define S_BCM1480_MC_ROW08                  0
-#define M_BCM1480_MC_ROW08                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW08)
-#define V_BCM1480_MC_ROW08(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW08)
-#define G_BCM1480_MC_ROW08(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW08, M_BCM1480_MC_ROW08)
+#define S_BCM1480_MC_ROW08                 0
+#define M_BCM1480_MC_ROW08                 _SB_MAKEMASK(6, S_BCM1480_MC_ROW08)
+#define V_BCM1480_MC_ROW08(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_ROW08)
+#define G_BCM1480_MC_ROW08(x)              _SB_GETVALUE(x, S_BCM1480_MC_ROW08, M_BCM1480_MC_ROW08)

 
 

-#define S_BCM1480_MC_ROW09                  8
-#define M_BCM1480_MC_ROW09                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW09)
-#define V_BCM1480_MC_ROW09(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW09)
-#define G_BCM1480_MC_ROW09(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW09, M_BCM1480_MC_ROW09)
+#define S_BCM1480_MC_ROW09                 8
+#define M_BCM1480_MC_ROW09                 _SB_MAKEMASK(6, S_BCM1480_MC_ROW09)
+#define V_BCM1480_MC_ROW09(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_ROW09)
+#define G_BCM1480_MC_ROW09(x)              _SB_GETVALUE(x, S_BCM1480_MC_ROW09, M_BCM1480_MC_ROW09)

 
 

-#define S_BCM1480_MC_ROW10                  16
-#define M_BCM1480_MC_ROW10                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW10)
-#define V_BCM1480_MC_ROW10(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW10)
-#define G_BCM1480_MC_ROW10(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW10, M_BCM1480_MC_ROW10)
+#define S_BCM1480_MC_ROW10                 16
+#define M_BCM1480_MC_ROW10                 _SB_MAKEMASK(6, S_BCM1480_MC_ROW10)
+#define V_BCM1480_MC_ROW10(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_ROW10)
+#define G_BCM1480_MC_ROW10(x)              _SB_GETVALUE(x, S_BCM1480_MC_ROW10, M_BCM1480_MC_ROW10)

 
 

-#define S_BCM1480_MC_ROW11                  24
-#define M_BCM1480_MC_ROW11                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW11)
-#define V_BCM1480_MC_ROW11(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW11)
-#define G_BCM1480_MC_ROW11(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW11, M_BCM1480_MC_ROW11)
+#define S_BCM1480_MC_ROW11                 24
+#define M_BCM1480_MC_ROW11                 _SB_MAKEMASK(6, S_BCM1480_MC_ROW11)
+#define V_BCM1480_MC_ROW11(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_ROW11)
+#define G_BCM1480_MC_ROW11(x)              _SB_GETVALUE(x, S_BCM1480_MC_ROW11, M_BCM1480_MC_ROW11)

 
 

-#define S_BCM1480_MC_ROW12                  32
-#define M_BCM1480_MC_ROW12                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW12)
-#define V_BCM1480_MC_ROW12(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW12)
-#define G_BCM1480_MC_ROW12(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW12, M_BCM1480_MC_ROW12)
+#define S_BCM1480_MC_ROW12                 32
+#define M_BCM1480_MC_ROW12                 _SB_MAKEMASK(6, S_BCM1480_MC_ROW12)
+#define V_BCM1480_MC_ROW12(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_ROW12)
+#define G_BCM1480_MC_ROW12(x)              _SB_GETVALUE(x, S_BCM1480_MC_ROW12, M_BCM1480_MC_ROW12)

 
 

-#define S_BCM1480_MC_ROW13                  40
-#define M_BCM1480_MC_ROW13                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW13)
-#define V_BCM1480_MC_ROW13(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW13)
-#define G_BCM1480_MC_ROW13(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW13, M_BCM1480_MC_ROW13)
+#define S_BCM1480_MC_ROW13                 40
+#define M_BCM1480_MC_ROW13                 _SB_MAKEMASK(6, S_BCM1480_MC_ROW13)
+#define V_BCM1480_MC_ROW13(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_ROW13)
+#define G_BCM1480_MC_ROW13(x)              _SB_GETVALUE(x, S_BCM1480_MC_ROW13, M_BCM1480_MC_ROW13)

 
 

-#define S_BCM1480_MC_ROW14                  48
-#define M_BCM1480_MC_ROW14                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW14)
-#define V_BCM1480_MC_ROW14(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW14)
-#define G_BCM1480_MC_ROW14(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW14, M_BCM1480_MC_ROW14)
+#define S_BCM1480_MC_ROW14                 48
+#define M_BCM1480_MC_ROW14                 _SB_MAKEMASK(6, S_BCM1480_MC_ROW14)
+#define V_BCM1480_MC_ROW14(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_ROW14)
+#define G_BCM1480_MC_ROW14(x)              _SB_GETVALUE(x, S_BCM1480_MC_ROW14, M_BCM1480_MC_ROW14)

 
 

-#define K_BCM1480_MC_ROWX_BIT_SPACING              8
+#define K_BCM1480_MC_ROWX_BIT_SPACING      8

 
 /*
  * Column Address Bit Select Register 0 (Table 86)
  */
 
 
 /*
  * Column Address Bit Select Register 0 (Table 86)
  */
 

-#define S_BCM1480_MC_COL00                  0
-#define M_BCM1480_MC_COL00                  _SB_MAKEMASK(6, S_BCM1480_MC_COL00)
-#define V_BCM1480_MC_COL00(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL00)
-#define G_BCM1480_MC_COL00(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL00, M_BCM1480_MC_COL00)
-
-#define S_BCM1480_MC_COL01                  8
-#define M_BCM1480_MC_COL01                  _SB_MAKEMASK(6, S_BCM1480_MC_COL01)
-#define V_BCM1480_MC_COL01(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL01)
-#define G_BCM1480_MC_COL01(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL01, M_BCM1480_MC_COL01)
-
-#define S_BCM1480_MC_COL02                  16
-#define M_BCM1480_MC_COL02                  _SB_MAKEMASK(6, S_BCM1480_MC_COL02)
-#define V_BCM1480_MC_COL02(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL02)
-#define G_BCM1480_MC_COL02(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL02, M_BCM1480_MC_COL02)
-
-#define S_BCM1480_MC_COL03                  24
-#define M_BCM1480_MC_COL03                  _SB_MAKEMASK(6, S_BCM1480_MC_COL03)
-#define V_BCM1480_MC_COL03(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL03)
-#define G_BCM1480_MC_COL03(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL03, M_BCM1480_MC_COL03)
-
-#define S_BCM1480_MC_COL04                  32
-#define M_BCM1480_MC_COL04                  _SB_MAKEMASK(6, S_BCM1480_MC_COL04)
-#define V_BCM1480_MC_COL04(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL04)
-#define G_BCM1480_MC_COL04(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL04, M_BCM1480_MC_COL04)
-
-#define S_BCM1480_MC_COL05                  40
-#define M_BCM1480_MC_COL05                  _SB_MAKEMASK(6, S_BCM1480_MC_COL05)
-#define V_BCM1480_MC_COL05(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL05)
-#define G_BCM1480_MC_COL05(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL05, M_BCM1480_MC_COL05)
-
-#define S_BCM1480_MC_COL06                  48
-#define M_BCM1480_MC_COL06                  _SB_MAKEMASK(6, S_BCM1480_MC_COL06)
-#define V_BCM1480_MC_COL06(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL06)
-#define G_BCM1480_MC_COL06(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL06, M_BCM1480_MC_COL06)
-
-#define S_BCM1480_MC_COL07                  56
-#define M_BCM1480_MC_COL07                  _SB_MAKEMASK(6, S_BCM1480_MC_COL07)
-#define V_BCM1480_MC_COL07(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL07)
-#define G_BCM1480_MC_COL07(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL07, M_BCM1480_MC_COL07)
+#define S_BCM1480_MC_COL00                 0
+#define M_BCM1480_MC_COL00                 _SB_MAKEMASK(6, S_BCM1480_MC_COL00)
+#define V_BCM1480_MC_COL00(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_COL00)
+#define G_BCM1480_MC_COL00(x)              _SB_GETVALUE(x, S_BCM1480_MC_COL00, M_BCM1480_MC_COL00)
+
+#define S_BCM1480_MC_COL01                 8
+#define M_BCM1480_MC_COL01                 _SB_MAKEMASK(6, S_BCM1480_MC_COL01)
+#define V_BCM1480_MC_COL01(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_COL01)
+#define G_BCM1480_MC_COL01(x)              _SB_GETVALUE(x, S_BCM1480_MC_COL01, M_BCM1480_MC_COL01)
+
+#define S_BCM1480_MC_COL02                 16
+#define M_BCM1480_MC_COL02                 _SB_MAKEMASK(6, S_BCM1480_MC_COL02)
+#define V_BCM1480_MC_COL02(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_COL02)
+#define G_BCM1480_MC_COL02(x)              _SB_GETVALUE(x, S_BCM1480_MC_COL02, M_BCM1480_MC_COL02)
+
+#define S_BCM1480_MC_COL03                 24
+#define M_BCM1480_MC_COL03                 _SB_MAKEMASK(6, S_BCM1480_MC_COL03)
+#define V_BCM1480_MC_COL03(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_COL03)
+#define G_BCM1480_MC_COL03(x)              _SB_GETVALUE(x, S_BCM1480_MC_COL03, M_BCM1480_MC_COL03)
+
+#define S_BCM1480_MC_COL04                 32
+#define M_BCM1480_MC_COL04                 _SB_MAKEMASK(6, S_BCM1480_MC_COL04)
+#define V_BCM1480_MC_COL04(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_COL04)
+#define G_BCM1480_MC_COL04(x)              _SB_GETVALUE(x, S_BCM1480_MC_COL04, M_BCM1480_MC_COL04)
+
+#define S_BCM1480_MC_COL05                 40
+#define M_BCM1480_MC_COL05                 _SB_MAKEMASK(6, S_BCM1480_MC_COL05)
+#define V_BCM1480_MC_COL05(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_COL05)
+#define G_BCM1480_MC_COL05(x)              _SB_GETVALUE(x, S_BCM1480_MC_COL05, M_BCM1480_MC_COL05)
+
+#define S_BCM1480_MC_COL06                 48
+#define M_BCM1480_MC_COL06                 _SB_MAKEMASK(6, S_BCM1480_MC_COL06)
+#define V_BCM1480_MC_COL06(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_COL06)
+#define G_BCM1480_MC_COL06(x)              _SB_GETVALUE(x, S_BCM1480_MC_COL06, M_BCM1480_MC_COL06)
+
+#define S_BCM1480_MC_COL07                 56
+#define M_BCM1480_MC_COL07                 _SB_MAKEMASK(6, S_BCM1480_MC_COL07)
+#define V_BCM1480_MC_COL07(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_COL07)
+#define G_BCM1480_MC_COL07(x)              _SB_GETVALUE(x, S_BCM1480_MC_COL07, M_BCM1480_MC_COL07)

 
 /*
  * Column Address Bit Select Register 1 (Table 87)
  */
 
 
 /*
  * Column Address Bit Select Register 1 (Table 87)
  */
 

-#define S_BCM1480_MC_COL08                  0
-#define M_BCM1480_MC_COL08                  _SB_MAKEMASK(6, S_BCM1480_MC_COL08)
-#define V_BCM1480_MC_COL08(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL08)
-#define G_BCM1480_MC_COL08(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL08, M_BCM1480_MC_COL08)
+#define S_BCM1480_MC_COL08                 0
+#define M_BCM1480_MC_COL08                 _SB_MAKEMASK(6, S_BCM1480_MC_COL08)
+#define V_BCM1480_MC_COL08(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_COL08)
+#define G_BCM1480_MC_COL08(x)              _SB_GETVALUE(x, S_BCM1480_MC_COL08, M_BCM1480_MC_COL08)

 
 

-#define S_BCM1480_MC_COL09                  8
-#define M_BCM1480_MC_COL09                  _SB_MAKEMASK(6, S_BCM1480_MC_COL09)
-#define V_BCM1480_MC_COL09(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL09)
-#define G_BCM1480_MC_COL09(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL09, M_BCM1480_MC_COL09)
+#define S_BCM1480_MC_COL09                 8
+#define M_BCM1480_MC_COL09                 _SB_MAKEMASK(6, S_BCM1480_MC_COL09)
+#define V_BCM1480_MC_COL09(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_COL09)
+#define G_BCM1480_MC_COL09(x)              _SB_GETVALUE(x, S_BCM1480_MC_COL09, M_BCM1480_MC_COL09)

 
 

-#define S_BCM1480_MC_COL10                  16   /* not a valid position, must be prog as 0 */
+#define S_BCM1480_MC_COL10                 16   /* not a valid position, must be prog as 0 */

 
 

-#define S_BCM1480_MC_COL11                  24
-#define M_BCM1480_MC_COL11                  _SB_MAKEMASK(6, S_BCM1480_MC_COL11)
-#define V_BCM1480_MC_COL11(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL11)
-#define G_BCM1480_MC_COL11(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL11, M_BCM1480_MC_COL11)
+#define S_BCM1480_MC_COL11                 24
+#define M_BCM1480_MC_COL11                 _SB_MAKEMASK(6, S_BCM1480_MC_COL11)
+#define V_BCM1480_MC_COL11(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_COL11)
+#define G_BCM1480_MC_COL11(x)              _SB_GETVALUE(x, S_BCM1480_MC_COL11, M_BCM1480_MC_COL11)

 
 

-#define S_BCM1480_MC_COL12                  32
-#define M_BCM1480_MC_COL12                  _SB_MAKEMASK(6, S_BCM1480_MC_COL12)
-#define V_BCM1480_MC_COL12(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL12)
-#define G_BCM1480_MC_COL12(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL12, M_BCM1480_MC_COL12)
+#define S_BCM1480_MC_COL12                 32
+#define M_BCM1480_MC_COL12                 _SB_MAKEMASK(6, S_BCM1480_MC_COL12)
+#define V_BCM1480_MC_COL12(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_COL12)
+#define G_BCM1480_MC_COL12(x)              _SB_GETVALUE(x, S_BCM1480_MC_COL12, M_BCM1480_MC_COL12)

 
 

-#define S_BCM1480_MC_COL13                  40
-#define M_BCM1480_MC_COL13                  _SB_MAKEMASK(6, S_BCM1480_MC_COL13)
-#define V_BCM1480_MC_COL13(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL13)
-#define G_BCM1480_MC_COL13(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL13, M_BCM1480_MC_COL13)
+#define S_BCM1480_MC_COL13                 40
+#define M_BCM1480_MC_COL13                 _SB_MAKEMASK(6, S_BCM1480_MC_COL13)
+#define V_BCM1480_MC_COL13(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_COL13)
+#define G_BCM1480_MC_COL13(x)              _SB_GETVALUE(x, S_BCM1480_MC_COL13, M_BCM1480_MC_COL13)

 
 

-#define S_BCM1480_MC_COL14                  48
-#define M_BCM1480_MC_COL14                  _SB_MAKEMASK(6, S_BCM1480_MC_COL14)
-#define V_BCM1480_MC_COL14(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL14)
-#define G_BCM1480_MC_COL14(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL14, M_BCM1480_MC_COL14)
+#define S_BCM1480_MC_COL14                 48
+#define M_BCM1480_MC_COL14                 _SB_MAKEMASK(6, S_BCM1480_MC_COL14)
+#define V_BCM1480_MC_COL14(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_COL14)
+#define G_BCM1480_MC_COL14(x)              _SB_GETVALUE(x, S_BCM1480_MC_COL14, M_BCM1480_MC_COL14)

 
 

-#define K_BCM1480_MC_COLX_BIT_SPACING              8
+#define K_BCM1480_MC_COLX_BIT_SPACING      8

 
 /*
  * CS0 and CS1 Bank Address Bit Select Register (Table 88)
  */
 
 
 /*
  * CS0 and CS1 Bank Address Bit Select Register (Table 88)
  */
 

-#define S_BCM1480_MC_CS01_BANK0             0
-#define M_BCM1480_MC_CS01_BANK0             _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK0)
-#define V_BCM1480_MC_CS01_BANK0(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK0)
-#define G_BCM1480_MC_CS01_BANK0(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK0, M_BCM1480_MC_CS01_BANK0)
+#define S_BCM1480_MC_CS01_BANK0                    0
+#define M_BCM1480_MC_CS01_BANK0                    _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK0)
+#define V_BCM1480_MC_CS01_BANK0(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK0)
+#define G_BCM1480_MC_CS01_BANK0(x)         _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK0, M_BCM1480_MC_CS01_BANK0)

 
 

-#define S_BCM1480_MC_CS01_BANK1             8
-#define M_BCM1480_MC_CS01_BANK1             _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK1)
-#define V_BCM1480_MC_CS01_BANK1(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK1)
-#define G_BCM1480_MC_CS01_BANK1(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK1, M_BCM1480_MC_CS01_BANK1)
+#define S_BCM1480_MC_CS01_BANK1                    8
+#define M_BCM1480_MC_CS01_BANK1                    _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK1)
+#define V_BCM1480_MC_CS01_BANK1(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK1)
+#define G_BCM1480_MC_CS01_BANK1(x)         _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK1, M_BCM1480_MC_CS01_BANK1)

 
 

-#define S_BCM1480_MC_CS01_BANK2             16
-#define M_BCM1480_MC_CS01_BANK2             _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK2)
-#define V_BCM1480_MC_CS01_BANK2(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK2)
-#define G_BCM1480_MC_CS01_BANK2(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK2, M_BCM1480_MC_CS01_BANK2)
+#define S_BCM1480_MC_CS01_BANK2                    16
+#define M_BCM1480_MC_CS01_BANK2                    _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK2)
+#define V_BCM1480_MC_CS01_BANK2(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK2)
+#define G_BCM1480_MC_CS01_BANK2(x)         _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK2, M_BCM1480_MC_CS01_BANK2)

 
 /*
  * CS2 and CS3 Bank Address Bit Select Register (Table 89)
  */
 
 
 /*
  * CS2 and CS3 Bank Address Bit Select Register (Table 89)
  */
 

-#define S_BCM1480_MC_CS23_BANK0             0
-#define M_BCM1480_MC_CS23_BANK0             _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK0)
-#define V_BCM1480_MC_CS23_BANK0(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK0)
-#define G_BCM1480_MC_CS23_BANK0(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK0, M_BCM1480_MC_CS23_BANK0)
+#define S_BCM1480_MC_CS23_BANK0                    0
+#define M_BCM1480_MC_CS23_BANK0                    _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK0)
+#define V_BCM1480_MC_CS23_BANK0(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK0)
+#define G_BCM1480_MC_CS23_BANK0(x)         _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK0, M_BCM1480_MC_CS23_BANK0)

 
 

-#define S_BCM1480_MC_CS23_BANK1             8
-#define M_BCM1480_MC_CS23_BANK1             _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK1)
-#define V_BCM1480_MC_CS23_BANK1(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK1)
-#define G_BCM1480_MC_CS23_BANK1(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK1, M_BCM1480_MC_CS23_BANK1)
+#define S_BCM1480_MC_CS23_BANK1                    8
+#define M_BCM1480_MC_CS23_BANK1                    _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK1)
+#define V_BCM1480_MC_CS23_BANK1(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK1)
+#define G_BCM1480_MC_CS23_BANK1(x)         _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK1, M_BCM1480_MC_CS23_BANK1)

 
 

-#define S_BCM1480_MC_CS23_BANK2             16
-#define M_BCM1480_MC_CS23_BANK2             _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK2)
-#define V_BCM1480_MC_CS23_BANK2(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK2)
-#define G_BCM1480_MC_CS23_BANK2(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK2, M_BCM1480_MC_CS23_BANK2)
+#define S_BCM1480_MC_CS23_BANK2                    16
+#define M_BCM1480_MC_CS23_BANK2                    _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK2)
+#define V_BCM1480_MC_CS23_BANK2(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK2)
+#define G_BCM1480_MC_CS23_BANK2(x)         _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK2, M_BCM1480_MC_CS23_BANK2)

 
 #define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING  8
 
 
 #define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING  8
 


@@ -335,19 +335,19 @@
  * DRAM Command Register (Table 90)
  */
 
  * DRAM Command Register (Table 90)
  */
 

-#define S_BCM1480_MC_COMMAND                0
-#define M_BCM1480_MC_COMMAND                _SB_MAKEMASK(4, S_BCM1480_MC_COMMAND)
-#define V_BCM1480_MC_COMMAND(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_COMMAND)
-#define G_BCM1480_MC_COMMAND(x)             _SB_GETVALUE(x, S_BCM1480_MC_COMMAND, M_BCM1480_MC_COMMAND)
+#define S_BCM1480_MC_COMMAND               0
+#define M_BCM1480_MC_COMMAND               _SB_MAKEMASK(4, S_BCM1480_MC_COMMAND)
+#define V_BCM1480_MC_COMMAND(x)                    _SB_MAKEVALUE(x, S_BCM1480_MC_COMMAND)
+#define G_BCM1480_MC_COMMAND(x)                    _SB_GETVALUE(x, S_BCM1480_MC_COMMAND, M_BCM1480_MC_COMMAND)

 
 

-#define K_BCM1480_MC_COMMAND_EMRS           0
-#define K_BCM1480_MC_COMMAND_MRS            1
-#define K_BCM1480_MC_COMMAND_PRE            2
-#define K_BCM1480_MC_COMMAND_AR             3
-#define K_BCM1480_MC_COMMAND_SETRFSH        4
-#define K_BCM1480_MC_COMMAND_CLRRFSH        5
-#define K_BCM1480_MC_COMMAND_SETPWRDN       6
-#define K_BCM1480_MC_COMMAND_CLRPWRDN       7
+#define K_BCM1480_MC_COMMAND_EMRS          0
+#define K_BCM1480_MC_COMMAND_MRS           1
+#define K_BCM1480_MC_COMMAND_PRE           2
+#define K_BCM1480_MC_COMMAND_AR                    3
+#define K_BCM1480_MC_COMMAND_SETRFSH       4
+#define K_BCM1480_MC_COMMAND_CLRRFSH       5
+#define K_BCM1480_MC_COMMAND_SETPWRDN      6
+#define K_BCM1480_MC_COMMAND_CLRPWRDN      7

 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 #define K_BCM1480_MC_COMMAND_EMRS2         8
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 #define K_BCM1480_MC_COMMAND_EMRS2         8


@@ -356,61 +356,61 @@
 #define K_BCM1480_MC_COMMAND_DISABLE_MCLK   11
 #endif
 
 #define K_BCM1480_MC_COMMAND_DISABLE_MCLK   11
 #endif
 

-#define V_BCM1480_MC_COMMAND_EMRS           V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS)
-#define V_BCM1480_MC_COMMAND_MRS            V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_MRS)
-#define V_BCM1480_MC_COMMAND_PRE            V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_PRE)
-#define V_BCM1480_MC_COMMAND_AR             V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_AR)
-#define V_BCM1480_MC_COMMAND_SETRFSH        V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETRFSH)
-#define V_BCM1480_MC_COMMAND_CLRRFSH        V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRRFSH)
-#define V_BCM1480_MC_COMMAND_SETPWRDN       V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETPWRDN)
-#define V_BCM1480_MC_COMMAND_CLRPWRDN       V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRPWRDN)
+#define V_BCM1480_MC_COMMAND_EMRS          V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS)
+#define V_BCM1480_MC_COMMAND_MRS           V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_MRS)
+#define V_BCM1480_MC_COMMAND_PRE           V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_PRE)
+#define V_BCM1480_MC_COMMAND_AR                    V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_AR)
+#define V_BCM1480_MC_COMMAND_SETRFSH       V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETRFSH)
+#define V_BCM1480_MC_COMMAND_CLRRFSH       V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRRFSH)
+#define V_BCM1480_MC_COMMAND_SETPWRDN      V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETPWRDN)
+#define V_BCM1480_MC_COMMAND_CLRPWRDN      V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRPWRDN)

 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)

-#define V_BCM1480_MC_COMMAND_EMRS2          V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS2)
-#define V_BCM1480_MC_COMMAND_EMRS3          V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS3)
+#define V_BCM1480_MC_COMMAND_EMRS2         V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS2)
+#define V_BCM1480_MC_COMMAND_EMRS3         V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS3)

 #define V_BCM1480_MC_COMMAND_ENABLE_MCLK    V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_ENABLE_MCLK)
 #define V_BCM1480_MC_COMMAND_DISABLE_MCLK   V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_DISABLE_MCLK)
 #endif
 
 #define S_BCM1480_MC_CS0                   4
 #define V_BCM1480_MC_COMMAND_ENABLE_MCLK    V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_ENABLE_MCLK)
 #define V_BCM1480_MC_COMMAND_DISABLE_MCLK   V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_DISABLE_MCLK)
 #endif
 
 #define S_BCM1480_MC_CS0                   4

-#define M_BCM1480_MC_CS0                    _SB_MAKEMASK1(4)
-#define M_BCM1480_MC_CS1                    _SB_MAKEMASK1(5)
-#define M_BCM1480_MC_CS2                    _SB_MAKEMASK1(6)
-#define M_BCM1480_MC_CS3                    _SB_MAKEMASK1(7)
-#define M_BCM1480_MC_CS4                    _SB_MAKEMASK1(8)
-#define M_BCM1480_MC_CS5                    _SB_MAKEMASK1(9)
-#define M_BCM1480_MC_CS6                    _SB_MAKEMASK1(10)
-#define M_BCM1480_MC_CS7                    _SB_MAKEMASK1(11)
+#define M_BCM1480_MC_CS0                   _SB_MAKEMASK1(4)
+#define M_BCM1480_MC_CS1                   _SB_MAKEMASK1(5)
+#define M_BCM1480_MC_CS2                   _SB_MAKEMASK1(6)
+#define M_BCM1480_MC_CS3                   _SB_MAKEMASK1(7)
+#define M_BCM1480_MC_CS4                   _SB_MAKEMASK1(8)
+#define M_BCM1480_MC_CS5                   _SB_MAKEMASK1(9)
+#define M_BCM1480_MC_CS6                   _SB_MAKEMASK1(10)
+#define M_BCM1480_MC_CS7                   _SB_MAKEMASK1(11)

 
 

-#define M_BCM1480_MC_CS                  _SB_MAKEMASK(8, S_BCM1480_MC_CS0)
-#define V_BCM1480_MC_CS(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_CS0)
-#define G_BCM1480_MC_CS(x)               _SB_GETVALUE(x, S_BCM1480_MC_CS0, M_BCM1480_MC_CS0)
+#define M_BCM1480_MC_CS                         _SB_MAKEMASK(8, S_BCM1480_MC_CS0)
+#define V_BCM1480_MC_CS(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_CS0)
+#define G_BCM1480_MC_CS(x)              _SB_GETVALUE(x, S_BCM1480_MC_CS0, M_BCM1480_MC_CS0)

 
 

-#define M_BCM1480_MC_CMD_ACTIVE             _SB_MAKEMASK1(16)
+#define M_BCM1480_MC_CMD_ACTIVE                    _SB_MAKEMASK1(16)

 
 /*
  * DRAM Mode Register (Table 91)
  */
 
 
 /*
  * DRAM Mode Register (Table 91)
  */
 

-#define S_BCM1480_MC_EMODE                  0
-#define M_BCM1480_MC_EMODE                  _SB_MAKEMASK(15, S_BCM1480_MC_EMODE)
-#define V_BCM1480_MC_EMODE(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_EMODE)
-#define G_BCM1480_MC_EMODE(x)               _SB_GETVALUE(x, S_BCM1480_MC_EMODE, M_BCM1480_MC_EMODE)
-#define V_BCM1480_MC_EMODE_DEFAULT          V_BCM1480_MC_EMODE(0)
+#define S_BCM1480_MC_EMODE                 0
+#define M_BCM1480_MC_EMODE                 _SB_MAKEMASK(15, S_BCM1480_MC_EMODE)
+#define V_BCM1480_MC_EMODE(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_EMODE)
+#define G_BCM1480_MC_EMODE(x)              _SB_GETVALUE(x, S_BCM1480_MC_EMODE, M_BCM1480_MC_EMODE)
+#define V_BCM1480_MC_EMODE_DEFAULT         V_BCM1480_MC_EMODE(0)

 
 

-#define S_BCM1480_MC_MODE                   16
-#define M_BCM1480_MC_MODE                   _SB_MAKEMASK(15, S_BCM1480_MC_MODE)
-#define V_BCM1480_MC_MODE(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_MODE)
-#define G_BCM1480_MC_MODE(x)                _SB_GETVALUE(x, S_BCM1480_MC_MODE, M_BCM1480_MC_MODE)
-#define V_BCM1480_MC_MODE_DEFAULT           V_BCM1480_MC_MODE(0)
+#define S_BCM1480_MC_MODE                  16
+#define M_BCM1480_MC_MODE                  _SB_MAKEMASK(15, S_BCM1480_MC_MODE)
+#define V_BCM1480_MC_MODE(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_MODE)
+#define G_BCM1480_MC_MODE(x)               _SB_GETVALUE(x, S_BCM1480_MC_MODE, M_BCM1480_MC_MODE)
+#define V_BCM1480_MC_MODE_DEFAULT          V_BCM1480_MC_MODE(0)

 
 

-#define S_BCM1480_MC_DRAM_TYPE              32
-#define M_BCM1480_MC_DRAM_TYPE              _SB_MAKEMASK(4, S_BCM1480_MC_DRAM_TYPE)
-#define V_BCM1480_MC_DRAM_TYPE(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_DRAM_TYPE)
-#define G_BCM1480_MC_DRAM_TYPE(x)           _SB_GETVALUE(x, S_BCM1480_MC_DRAM_TYPE, M_BCM1480_MC_DRAM_TYPE)
+#define S_BCM1480_MC_DRAM_TYPE             32
+#define M_BCM1480_MC_DRAM_TYPE             _SB_MAKEMASK(4, S_BCM1480_MC_DRAM_TYPE)
+#define V_BCM1480_MC_DRAM_TYPE(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_DRAM_TYPE)
+#define G_BCM1480_MC_DRAM_TYPE(x)          _SB_GETVALUE(x, S_BCM1480_MC_DRAM_TYPE, M_BCM1480_MC_DRAM_TYPE)

 
 

-#define K_BCM1480_MC_DRAM_TYPE_JEDEC        0
-#define K_BCM1480_MC_DRAM_TYPE_FCRAM        1
+#define K_BCM1480_MC_DRAM_TYPE_JEDEC       0
+#define K_BCM1480_MC_DRAM_TYPE_FCRAM       1

 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 #define K_BCM1480_MC_DRAM_TYPE_DDR2        2
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 #define K_BCM1480_MC_DRAM_TYPE_DDR2        2


@@ -418,27 +418,27 @@
 
 #define K_BCM1480_MC_DRAM_TYPE_DDR2_PASS1   0
 
 
 #define K_BCM1480_MC_DRAM_TYPE_DDR2_PASS1   0
 

-#define V_BCM1480_MC_DRAM_TYPE_JEDEC        V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC)
-#define V_BCM1480_MC_DRAM_TYPE_FCRAM        V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM)
+#define V_BCM1480_MC_DRAM_TYPE_JEDEC       V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC)
+#define V_BCM1480_MC_DRAM_TYPE_FCRAM       V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM)

 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 #define V_BCM1480_MC_DRAM_TYPE_DDR2        V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_DDR2)
 #endif
 
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 #define V_BCM1480_MC_DRAM_TYPE_DDR2        V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_DDR2)
 #endif
 

-#define M_BCM1480_MC_GANGED                 _SB_MAKEMASK1(36)
-#define M_BCM1480_MC_BY9_INTF               _SB_MAKEMASK1(37)
-#define M_BCM1480_MC_FORCE_ECC64            _SB_MAKEMASK1(38)
-#define M_BCM1480_MC_ECC_DISABLE            _SB_MAKEMASK1(39)
+#define M_BCM1480_MC_GANGED                _SB_MAKEMASK1(36)
+#define M_BCM1480_MC_BY9_INTF              _SB_MAKEMASK1(37)
+#define M_BCM1480_MC_FORCE_ECC64           _SB_MAKEMASK1(38)
+#define M_BCM1480_MC_ECC_DISABLE           _SB_MAKEMASK1(39)

 
 

-#define S_BCM1480_MC_PG_POLICY              40
-#define M_BCM1480_MC_PG_POLICY              _SB_MAKEMASK(2, S_BCM1480_MC_PG_POLICY)
-#define V_BCM1480_MC_PG_POLICY(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_PG_POLICY)
-#define G_BCM1480_MC_PG_POLICY(x)           _SB_GETVALUE(x, S_BCM1480_MC_PG_POLICY, M_BCM1480_MC_PG_POLICY)
+#define S_BCM1480_MC_PG_POLICY             40
+#define M_BCM1480_MC_PG_POLICY             _SB_MAKEMASK(2, S_BCM1480_MC_PG_POLICY)
+#define V_BCM1480_MC_PG_POLICY(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_PG_POLICY)
+#define G_BCM1480_MC_PG_POLICY(x)          _SB_GETVALUE(x, S_BCM1480_MC_PG_POLICY, M_BCM1480_MC_PG_POLICY)

 
 

-#define K_BCM1480_MC_PG_POLICY_CLOSED       0
+#define K_BCM1480_MC_PG_POLICY_CLOSED      0

 #define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1
 
 #define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1
 

-#define V_BCM1480_MC_PG_POLICY_CLOSED       V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CLOSED)
+#define V_BCM1480_MC_PG_POLICY_CLOSED      V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CLOSED)

 #define V_BCM1480_MC_PG_POLICY_CAS_TIME_CHK V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK)
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 #define V_BCM1480_MC_PG_POLICY_CAS_TIME_CHK V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK)
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)


@@ -447,32 +447,32 @@
 #endif
 
 #define V_BCM1480_MC_DRAMMODE_DEFAULT  V_BCM1480_MC_EMODE_DEFAULT | V_BCM1480_MC_MODE_DEFAULT | V_BCM1480_MC_DRAM_TYPE_JEDEC | \
 #endif
 
 #define V_BCM1480_MC_DRAMMODE_DEFAULT  V_BCM1480_MC_EMODE_DEFAULT | V_BCM1480_MC_MODE_DEFAULT | V_BCM1480_MC_DRAM_TYPE_JEDEC | \

-                                V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK)
+                               V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK)

 
 /*
  * Memory Clock Configuration Register (Table 92)
  */
 
 
 /*
  * Memory Clock Configuration Register (Table 92)
  */
 

-#define S_BCM1480_MC_CLK_RATIO              0
-#define M_BCM1480_MC_CLK_RATIO              _SB_MAKEMASK(6, S_BCM1480_MC_CLK_RATIO)
-#define V_BCM1480_MC_CLK_RATIO(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_CLK_RATIO)
-#define G_BCM1480_MC_CLK_RATIO(x)           _SB_GETVALUE(x, S_BCM1480_MC_CLK_RATIO, M_BCM1480_MC_CLK_RATIO)
+#define S_BCM1480_MC_CLK_RATIO             0
+#define M_BCM1480_MC_CLK_RATIO             _SB_MAKEMASK(6, S_BCM1480_MC_CLK_RATIO)
+#define V_BCM1480_MC_CLK_RATIO(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CLK_RATIO)
+#define G_BCM1480_MC_CLK_RATIO(x)          _SB_GETVALUE(x, S_BCM1480_MC_CLK_RATIO, M_BCM1480_MC_CLK_RATIO)

 
 

-#define V_BCM1480_MC_CLK_RATIO_DEFAULT      V_BCM1480_MC_CLK_RATIO(10)
+#define V_BCM1480_MC_CLK_RATIO_DEFAULT     V_BCM1480_MC_CLK_RATIO(10)

 
 

-#define S_BCM1480_MC_REF_RATE               8
-#define M_BCM1480_MC_REF_RATE               _SB_MAKEMASK(8, S_BCM1480_MC_REF_RATE)
-#define V_BCM1480_MC_REF_RATE(x)            _SB_MAKEVALUE(x, S_BCM1480_MC_REF_RATE)
-#define G_BCM1480_MC_REF_RATE(x)            _SB_GETVALUE(x, S_BCM1480_MC_REF_RATE, M_BCM1480_MC_REF_RATE)
+#define S_BCM1480_MC_REF_RATE              8
+#define M_BCM1480_MC_REF_RATE              _SB_MAKEMASK(8, S_BCM1480_MC_REF_RATE)
+#define V_BCM1480_MC_REF_RATE(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_REF_RATE)
+#define G_BCM1480_MC_REF_RATE(x)           _SB_GETVALUE(x, S_BCM1480_MC_REF_RATE, M_BCM1480_MC_REF_RATE)

 
 

-#define K_BCM1480_MC_REF_RATE_100MHz        0x31
-#define K_BCM1480_MC_REF_RATE_200MHz        0x62
-#define K_BCM1480_MC_REF_RATE_400MHz        0xC4
+#define K_BCM1480_MC_REF_RATE_100MHz       0x31
+#define K_BCM1480_MC_REF_RATE_200MHz       0x62
+#define K_BCM1480_MC_REF_RATE_400MHz       0xC4

 
 

-#define V_BCM1480_MC_REF_RATE_100MHz        V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_100MHz)
-#define V_BCM1480_MC_REF_RATE_200MHz        V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_200MHz)
-#define V_BCM1480_MC_REF_RATE_400MHz        V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_400MHz)
-#define V_BCM1480_MC_REF_RATE_DEFAULT       V_BCM1480_MC_REF_RATE_400MHz
+#define V_BCM1480_MC_REF_RATE_100MHz       V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_100MHz)
+#define V_BCM1480_MC_REF_RATE_200MHz       V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_200MHz)
+#define V_BCM1480_MC_REF_RATE_400MHz       V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_400MHz)
+#define V_BCM1480_MC_REF_RATE_DEFAULT      V_BCM1480_MC_REF_RATE_400MHz

 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 #define M_BCM1480_MC_AUTO_REF_DIS          _SB_MAKEMASK1(16)
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 #define M_BCM1480_MC_AUTO_REF_DIS          _SB_MAKEMASK1(16)


@@ -518,19 +518,19 @@
 
 #define M_BCM1480_MC_CS_ODD_ODT_EN         _SB_MAKEMASK1(32)
 
 
 #define M_BCM1480_MC_CS_ODD_ODT_EN         _SB_MAKEMASK1(32)
 

-#define S_BCM1480_MC_ODT0                  0
+#define S_BCM1480_MC_ODT0                  0

 #define M_BCM1480_MC_ODT0                  _SB_MAKEMASK(8, S_BCM1480_MC_ODT0)
 #define V_BCM1480_MC_ODT0(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ODT0)
 
 #define M_BCM1480_MC_ODT0                  _SB_MAKEMASK(8, S_BCM1480_MC_ODT0)
 #define V_BCM1480_MC_ODT0(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ODT0)
 

-#define S_BCM1480_MC_ODT2                  8
+#define S_BCM1480_MC_ODT2                  8

 #define M_BCM1480_MC_ODT2                  _SB_MAKEMASK(8, S_BCM1480_MC_ODT2)
 #define V_BCM1480_MC_ODT2(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ODT2)
 
 #define M_BCM1480_MC_ODT2                  _SB_MAKEMASK(8, S_BCM1480_MC_ODT2)
 #define V_BCM1480_MC_ODT2(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ODT2)
 

-#define S_BCM1480_MC_ODT4                  16
+#define S_BCM1480_MC_ODT4                  16

 #define M_BCM1480_MC_ODT4                  _SB_MAKEMASK(8, S_BCM1480_MC_ODT4)
 #define V_BCM1480_MC_ODT4(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ODT4)
 
 #define M_BCM1480_MC_ODT4                  _SB_MAKEMASK(8, S_BCM1480_MC_ODT4)
 #define V_BCM1480_MC_ODT4(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ODT4)
 

-#define S_BCM1480_MC_ODT6                  24
+#define S_BCM1480_MC_ODT6                  24

 #define M_BCM1480_MC_ODT6                  _SB_MAKEMASK(8, S_BCM1480_MC_ODT6)
 #define V_BCM1480_MC_ODT6(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ODT6)
 #endif
 #define M_BCM1480_MC_ODT6                  _SB_MAKEMASK(8, S_BCM1480_MC_ODT6)
 #define V_BCM1480_MC_ODT6(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ODT6)
 #endif


@@ -539,139 +539,139 @@
  * Memory DLL Configuration Register (Table 93)
  */
 
  * Memory DLL Configuration Register (Table 93)
  */
 

-#define S_BCM1480_MC_ADDR_COARSE_ADJ         0
-#define M_BCM1480_MC_ADDR_COARSE_ADJ         _SB_MAKEMASK(6, S_BCM1480_MC_ADDR_COARSE_ADJ)
-#define V_BCM1480_MC_ADDR_COARSE_ADJ(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ)
-#define G_BCM1480_MC_ADDR_COARSE_ADJ(x)      _SB_GETVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ, M_BCM1480_MC_ADDR_COARSE_ADJ)
+#define S_BCM1480_MC_ADDR_COARSE_ADJ        0
+#define M_BCM1480_MC_ADDR_COARSE_ADJ        _SB_MAKEMASK(6, S_BCM1480_MC_ADDR_COARSE_ADJ)
+#define V_BCM1480_MC_ADDR_COARSE_ADJ(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ)
+#define G_BCM1480_MC_ADDR_COARSE_ADJ(x)             _SB_GETVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ, M_BCM1480_MC_ADDR_COARSE_ADJ)

 #define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0)
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 #define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0)
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)

-#define S_BCM1480_MC_ADDR_FREQ_RANGE           8
-#define M_BCM1480_MC_ADDR_FREQ_RANGE           _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FREQ_RANGE)
-#define V_BCM1480_MC_ADDR_FREQ_RANGE(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE)
-#define G_BCM1480_MC_ADDR_FREQ_RANGE(x)        _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE, M_BCM1480_MC_ADDR_FREQ_RANGE)
-#define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT   V_BCM1480_MC_ADDR_FREQ_RANGE(0x4)
+#define S_BCM1480_MC_ADDR_FREQ_RANGE           8
+#define M_BCM1480_MC_ADDR_FREQ_RANGE           _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FREQ_RANGE)
+#define V_BCM1480_MC_ADDR_FREQ_RANGE(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE)
+#define G_BCM1480_MC_ADDR_FREQ_RANGE(x)                _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE, M_BCM1480_MC_ADDR_FREQ_RANGE)
+#define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT   V_BCM1480_MC_ADDR_FREQ_RANGE(0x4)

 #endif
 
 #endif
 

-#define S_BCM1480_MC_ADDR_FINE_ADJ          8
-#define M_BCM1480_MC_ADDR_FINE_ADJ          _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FINE_ADJ)
-#define V_BCM1480_MC_ADDR_FINE_ADJ(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ)
-#define G_BCM1480_MC_ADDR_FINE_ADJ(x)       _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ, M_BCM1480_MC_ADDR_FINE_ADJ)
+#define S_BCM1480_MC_ADDR_FINE_ADJ         8
+#define M_BCM1480_MC_ADDR_FINE_ADJ         _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FINE_ADJ)
+#define V_BCM1480_MC_ADDR_FINE_ADJ(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ)
+#define G_BCM1480_MC_ADDR_FINE_ADJ(x)      _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ, M_BCM1480_MC_ADDR_FINE_ADJ)

 #define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT  V_BCM1480_MC_ADDR_FINE_ADJ(0x8)
 
 #define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT  V_BCM1480_MC_ADDR_FINE_ADJ(0x8)
 

-#define S_BCM1480_MC_DQI_COARSE_ADJ         16
-#define M_BCM1480_MC_DQI_COARSE_ADJ         _SB_MAKEMASK(6, S_BCM1480_MC_DQI_COARSE_ADJ)
-#define V_BCM1480_MC_DQI_COARSE_ADJ(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ)
-#define G_BCM1480_MC_DQI_COARSE_ADJ(x)      _SB_GETVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ, M_BCM1480_MC_DQI_COARSE_ADJ)
+#define S_BCM1480_MC_DQI_COARSE_ADJ        16
+#define M_BCM1480_MC_DQI_COARSE_ADJ        _SB_MAKEMASK(6, S_BCM1480_MC_DQI_COARSE_ADJ)
+#define V_BCM1480_MC_DQI_COARSE_ADJ(x)     _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ)
+#define G_BCM1480_MC_DQI_COARSE_ADJ(x)     _SB_GETVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ, M_BCM1480_MC_DQI_COARSE_ADJ)

 #define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0)
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 #define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0)
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)

-#define S_BCM1480_MC_DQI_FREQ_RANGE            24
-#define M_BCM1480_MC_DQI_FREQ_RANGE            _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FREQ_RANGE)
-#define V_BCM1480_MC_DQI_FREQ_RANGE(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE)
-#define G_BCM1480_MC_DQI_FREQ_RANGE(x)         _SB_GETVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE, M_BCM1480_MC_DQI_FREQ_RANGE)
-#define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT    V_BCM1480_MC_DQI_FREQ_RANGE(0x4)
+#define S_BCM1480_MC_DQI_FREQ_RANGE            24
+#define M_BCM1480_MC_DQI_FREQ_RANGE            _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FREQ_RANGE)
+#define V_BCM1480_MC_DQI_FREQ_RANGE(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE)
+#define G_BCM1480_MC_DQI_FREQ_RANGE(x)         _SB_GETVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE, M_BCM1480_MC_DQI_FREQ_RANGE)
+#define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT    V_BCM1480_MC_DQI_FREQ_RANGE(0x4)

 #endif
 
 #endif
 

-#define S_BCM1480_MC_DQI_FINE_ADJ           24
-#define M_BCM1480_MC_DQI_FINE_ADJ           _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FINE_ADJ)
-#define V_BCM1480_MC_DQI_FINE_ADJ(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ)
-#define G_BCM1480_MC_DQI_FINE_ADJ(x)        _SB_GETVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ, M_BCM1480_MC_DQI_FINE_ADJ)
+#define S_BCM1480_MC_DQI_FINE_ADJ          24
+#define M_BCM1480_MC_DQI_FINE_ADJ          _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FINE_ADJ)
+#define V_BCM1480_MC_DQI_FINE_ADJ(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ)
+#define G_BCM1480_MC_DQI_FINE_ADJ(x)       _SB_GETVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ, M_BCM1480_MC_DQI_FINE_ADJ)

 #define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT   V_BCM1480_MC_DQI_FINE_ADJ(0x8)
 
 #define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT   V_BCM1480_MC_DQI_FINE_ADJ(0x8)
 

-#define S_BCM1480_MC_DQO_COARSE_ADJ         32
-#define M_BCM1480_MC_DQO_COARSE_ADJ         _SB_MAKEMASK(6, S_BCM1480_MC_DQO_COARSE_ADJ)
-#define V_BCM1480_MC_DQO_COARSE_ADJ(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ)
-#define G_BCM1480_MC_DQO_COARSE_ADJ(x)      _SB_GETVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ, M_BCM1480_MC_DQO_COARSE_ADJ)
+#define S_BCM1480_MC_DQO_COARSE_ADJ        32
+#define M_BCM1480_MC_DQO_COARSE_ADJ        _SB_MAKEMASK(6, S_BCM1480_MC_DQO_COARSE_ADJ)
+#define V_BCM1480_MC_DQO_COARSE_ADJ(x)     _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ)
+#define G_BCM1480_MC_DQO_COARSE_ADJ(x)     _SB_GETVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ, M_BCM1480_MC_DQO_COARSE_ADJ)

 #define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0)
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 #define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0)
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)

-#define S_BCM1480_MC_DQO_FREQ_RANGE            40
-#define M_BCM1480_MC_DQO_FREQ_RANGE            _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FREQ_RANGE)
-#define V_BCM1480_MC_DQO_FREQ_RANGE(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE)
-#define G_BCM1480_MC_DQO_FREQ_RANGE(x)         _SB_GETVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE, M_BCM1480_MC_DQO_FREQ_RANGE)
-#define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT    V_BCM1480_MC_DQO_FREQ_RANGE(0x4)
+#define S_BCM1480_MC_DQO_FREQ_RANGE            40
+#define M_BCM1480_MC_DQO_FREQ_RANGE            _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FREQ_RANGE)
+#define V_BCM1480_MC_DQO_FREQ_RANGE(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE)
+#define G_BCM1480_MC_DQO_FREQ_RANGE(x)         _SB_GETVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE, M_BCM1480_MC_DQO_FREQ_RANGE)
+#define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT    V_BCM1480_MC_DQO_FREQ_RANGE(0x4)

 #endif
 
 #endif
 

-#define S_BCM1480_MC_DQO_FINE_ADJ           40
-#define M_BCM1480_MC_DQO_FINE_ADJ           _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FINE_ADJ)
-#define V_BCM1480_MC_DQO_FINE_ADJ(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ)
-#define G_BCM1480_MC_DQO_FINE_ADJ(x)        _SB_GETVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ, M_BCM1480_MC_DQO_FINE_ADJ)
+#define S_BCM1480_MC_DQO_FINE_ADJ          40
+#define M_BCM1480_MC_DQO_FINE_ADJ          _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FINE_ADJ)
+#define V_BCM1480_MC_DQO_FINE_ADJ(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ)
+#define G_BCM1480_MC_DQO_FINE_ADJ(x)       _SB_GETVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ, M_BCM1480_MC_DQO_FINE_ADJ)

 #define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT   V_BCM1480_MC_DQO_FINE_ADJ(0x8)
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 #define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT   V_BCM1480_MC_DQO_FINE_ADJ(0x8)
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)

-#define S_BCM1480_MC_DLL_PDSEL            44
-#define M_BCM1480_MC_DLL_PDSEL            _SB_MAKEMASK(2, S_BCM1480_MC_DLL_PDSEL)
-#define V_BCM1480_MC_DLL_PDSEL(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_PDSEL)
-#define G_BCM1480_MC_DLL_PDSEL(x)         _SB_GETVALUE(x, S_BCM1480_MC_DLL_PDSEL, M_BCM1480_MC_DLL_PDSEL)
-#define V_BCM1480_MC_DLL_DEFAULT_PDSEL    V_BCM1480_MC_DLL_PDSEL(0x0)
-
-#define        M_BCM1480_MC_DLL_REGBYPASS        _SB_MAKEMASK1(46)
-#define        M_BCM1480_MC_DQO_SHIFT            _SB_MAKEMASK1(47)
+#define S_BCM1480_MC_DLL_PDSEL           44
+#define M_BCM1480_MC_DLL_PDSEL           _SB_MAKEMASK(2, S_BCM1480_MC_DLL_PDSEL)
+#define V_BCM1480_MC_DLL_PDSEL(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_PDSEL)
+#define G_BCM1480_MC_DLL_PDSEL(x)        _SB_GETVALUE(x, S_BCM1480_MC_DLL_PDSEL, M_BCM1480_MC_DLL_PDSEL)
+#define V_BCM1480_MC_DLL_DEFAULT_PDSEL   V_BCM1480_MC_DLL_PDSEL(0x0)
+
+#define M_BCM1480_MC_DLL_REGBYPASS       _SB_MAKEMASK1(46)
+#define M_BCM1480_MC_DQO_SHIFT           _SB_MAKEMASK1(47)

 #endif
 
 #endif
 

-#define S_BCM1480_MC_DLL_DEFAULT           48
-#define M_BCM1480_MC_DLL_DEFAULT           _SB_MAKEMASK(6, S_BCM1480_MC_DLL_DEFAULT)
-#define V_BCM1480_MC_DLL_DEFAULT(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_DEFAULT)
-#define G_BCM1480_MC_DLL_DEFAULT(x)        _SB_GETVALUE(x, S_BCM1480_MC_DLL_DEFAULT, M_BCM1480_MC_DLL_DEFAULT)
+#define S_BCM1480_MC_DLL_DEFAULT          48
+#define M_BCM1480_MC_DLL_DEFAULT          _SB_MAKEMASK(6, S_BCM1480_MC_DLL_DEFAULT)
+#define V_BCM1480_MC_DLL_DEFAULT(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_DEFAULT)
+#define G_BCM1480_MC_DLL_DEFAULT(x)       _SB_GETVALUE(x, S_BCM1480_MC_DLL_DEFAULT, M_BCM1480_MC_DLL_DEFAULT)

 #define V_BCM1480_MC_DLL_DEFAULT_DEFAULT   V_BCM1480_MC_DLL_DEFAULT(0x10)
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 #define S_BCM1480_MC_DLL_REGCTRL         54
 #define V_BCM1480_MC_DLL_DEFAULT_DEFAULT   V_BCM1480_MC_DLL_DEFAULT(0x10)
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 #define S_BCM1480_MC_DLL_REGCTRL         54

-#define M_BCM1480_MC_DLL_REGCTRL                 _SB_MAKEMASK(2, S_BCM1480_MC_DLL_REGCTRL)
-#define V_BCM1480_MC_DLL_REGCTRL(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_REGCTRL)
-#define G_BCM1480_MC_DLL_REGCTRL(x)       _SB_GETVALUE(x, S_BCM1480_MC_DLL_REGCTRL, M_BCM1480_MC_DLL_REGCTRL)
+#define M_BCM1480_MC_DLL_REGCTRL         _SB_MAKEMASK(2, S_BCM1480_MC_DLL_REGCTRL)
+#define V_BCM1480_MC_DLL_REGCTRL(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_REGCTRL)
+#define G_BCM1480_MC_DLL_REGCTRL(x)      _SB_GETVALUE(x, S_BCM1480_MC_DLL_REGCTRL, M_BCM1480_MC_DLL_REGCTRL)

 #define V_BCM1480_MC_DLL_DEFAULT_REGCTRL  V_BCM1480_MC_DLL_REGCTRL(0x0)
 #endif
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 #define V_BCM1480_MC_DLL_DEFAULT_REGCTRL  V_BCM1480_MC_DLL_REGCTRL(0x0)
 #endif
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)

-#define S_BCM1480_MC_DLL_FREQ_RANGE            56
-#define M_BCM1480_MC_DLL_FREQ_RANGE            _SB_MAKEMASK(4, S_BCM1480_MC_DLL_FREQ_RANGE)
-#define V_BCM1480_MC_DLL_FREQ_RANGE(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE)
-#define G_BCM1480_MC_DLL_FREQ_RANGE(x)         _SB_GETVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE, M_BCM1480_MC_DLL_FREQ_RANGE)
-#define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT    V_BCM1480_MC_DLL_FREQ_RANGE(0x4)
+#define S_BCM1480_MC_DLL_FREQ_RANGE            56
+#define M_BCM1480_MC_DLL_FREQ_RANGE            _SB_MAKEMASK(4, S_BCM1480_MC_DLL_FREQ_RANGE)
+#define V_BCM1480_MC_DLL_FREQ_RANGE(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE)
+#define G_BCM1480_MC_DLL_FREQ_RANGE(x)         _SB_GETVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE, M_BCM1480_MC_DLL_FREQ_RANGE)
+#define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT    V_BCM1480_MC_DLL_FREQ_RANGE(0x4)

 #endif
 
 #endif
 

-#define S_BCM1480_MC_DLL_STEP_SIZE          56
-#define M_BCM1480_MC_DLL_STEP_SIZE          _SB_MAKEMASK(4, S_BCM1480_MC_DLL_STEP_SIZE)
-#define V_BCM1480_MC_DLL_STEP_SIZE(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE)
-#define G_BCM1480_MC_DLL_STEP_SIZE(x)       _SB_GETVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE, M_BCM1480_MC_DLL_STEP_SIZE)
+#define S_BCM1480_MC_DLL_STEP_SIZE         56
+#define M_BCM1480_MC_DLL_STEP_SIZE         _SB_MAKEMASK(4, S_BCM1480_MC_DLL_STEP_SIZE)
+#define V_BCM1480_MC_DLL_STEP_SIZE(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE)
+#define G_BCM1480_MC_DLL_STEP_SIZE(x)      _SB_GETVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE, M_BCM1480_MC_DLL_STEP_SIZE)

 #define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT  V_BCM1480_MC_DLL_STEP_SIZE(0x8)
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 #define S_BCM1480_MC_DLL_BGCTRL          60
 #define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT  V_BCM1480_MC_DLL_STEP_SIZE(0x8)
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 #define S_BCM1480_MC_DLL_BGCTRL          60

-#define M_BCM1480_MC_DLL_BGCTRL          _SB_MAKEMASK(2, S_BCM1480_MC_DLL_BGCTRL)
-#define V_BCM1480_MC_DLL_BGCTRL(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_BGCTRL)
-#define G_BCM1480_MC_DLL_BGCTRL(x)       _SB_GETVALUE(x, S_BCM1480_MC_DLL_BGCTRL, M_BCM1480_MC_DLL_BGCTRL)
-#define V_BCM1480_MC_DLL_DEFAULT_BGCTRL  V_BCM1480_MC_DLL_BGCTRL(0x0)
+#define M_BCM1480_MC_DLL_BGCTRL                  _SB_MAKEMASK(2, S_BCM1480_MC_DLL_BGCTRL)
+#define V_BCM1480_MC_DLL_BGCTRL(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_BGCTRL)
+#define G_BCM1480_MC_DLL_BGCTRL(x)      _SB_GETVALUE(x, S_BCM1480_MC_DLL_BGCTRL, M_BCM1480_MC_DLL_BGCTRL)
+#define V_BCM1480_MC_DLL_DEFAULT_BGCTRL         V_BCM1480_MC_DLL_BGCTRL(0x0)

 #endif
 
 #endif
 

-#define        M_BCM1480_MC_DLL_BYPASS             _SB_MAKEMASK1(63)
+#define M_BCM1480_MC_DLL_BYPASS                    _SB_MAKEMASK1(63)

 
 /*
  * Memory Drive Configuration Register (Table 94)
  */
 
 
 /*
  * Memory Drive Configuration Register (Table 94)
  */
 

-#define S_BCM1480_MC_RTT_BYP_PULLDOWN       0
-#define M_BCM1480_MC_RTT_BYP_PULLDOWN       _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLDOWN)
+#define S_BCM1480_MC_RTT_BYP_PULLDOWN      0
+#define M_BCM1480_MC_RTT_BYP_PULLDOWN      _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLDOWN)

 #define V_BCM1480_MC_RTT_BYP_PULLDOWN(x)    _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN)
 #define G_BCM1480_MC_RTT_BYP_PULLDOWN(x)    _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN, M_BCM1480_MC_RTT_BYP_PULLDOWN)
 
 #define V_BCM1480_MC_RTT_BYP_PULLDOWN(x)    _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN)
 #define G_BCM1480_MC_RTT_BYP_PULLDOWN(x)    _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN, M_BCM1480_MC_RTT_BYP_PULLDOWN)
 

-#define S_BCM1480_MC_RTT_BYP_PULLUP         6
-#define M_BCM1480_MC_RTT_BYP_PULLUP         _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLUP)
-#define V_BCM1480_MC_RTT_BYP_PULLUP(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP)
-#define G_BCM1480_MC_RTT_BYP_PULLUP(x)      _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP, M_BCM1480_MC_RTT_BYP_PULLUP)
+#define S_BCM1480_MC_RTT_BYP_PULLUP        6
+#define M_BCM1480_MC_RTT_BYP_PULLUP        _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLUP)
+#define V_BCM1480_MC_RTT_BYP_PULLUP(x)     _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP)
+#define G_BCM1480_MC_RTT_BYP_PULLUP(x)     _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP, M_BCM1480_MC_RTT_BYP_PULLUP)

 
 

-#define M_BCM1480_MC_RTT_BYPASS             _SB_MAKEMASK1(8)
-#define M_BCM1480_MC_RTT_COMP_MOV_AVG       _SB_MAKEMASK1(9)
+#define M_BCM1480_MC_RTT_BYPASS                    _SB_MAKEMASK1(8)
+#define M_BCM1480_MC_RTT_COMP_MOV_AVG      _SB_MAKEMASK1(9)

 
 #define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN    10
 #define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN    _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
 #define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
 #define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN, M_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
 
 
 #define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN    10
 #define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN    _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
 #define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
 #define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN, M_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
 

-#define S_BCM1480_MC_PVT_BYP_C1_PULLUP      15
-#define M_BCM1480_MC_PVT_BYP_C1_PULLUP      _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLUP)
+#define S_BCM1480_MC_PVT_BYP_C1_PULLUP     15
+#define M_BCM1480_MC_PVT_BYP_C1_PULLUP     _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLUP)

 #define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x)   _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP)
 #define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x)   _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP, M_BCM1480_MC_PVT_BYP_C1_PULLUP)
 
 #define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x)   _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP)
 #define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x)   _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP, M_BCM1480_MC_PVT_BYP_C1_PULLUP)
 


@@ -680,153 +680,153 @@
 #define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
 #define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN, M_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
 
 #define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
 #define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN, M_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
 

-#define S_BCM1480_MC_PVT_BYP_C2_PULLUP      25
-#define M_BCM1480_MC_PVT_BYP_C2_PULLUP      _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLUP)
+#define S_BCM1480_MC_PVT_BYP_C2_PULLUP     25
+#define M_BCM1480_MC_PVT_BYP_C2_PULLUP     _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLUP)

 #define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x)   _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP)
 #define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x)   _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP, M_BCM1480_MC_PVT_BYP_C2_PULLUP)
 
 #define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x)   _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP)
 #define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x)   _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP, M_BCM1480_MC_PVT_BYP_C2_PULLUP)
 

-#define M_BCM1480_MC_PVT_BYPASS             _SB_MAKEMASK1(30)
-#define M_BCM1480_MC_PVT_COMP_MOV_AVG       _SB_MAKEMASK1(31)
+#define M_BCM1480_MC_PVT_BYPASS                    _SB_MAKEMASK1(30)
+#define M_BCM1480_MC_PVT_COMP_MOV_AVG      _SB_MAKEMASK1(31)

 
 

-#define M_BCM1480_MC_CLK_CLASS              _SB_MAKEMASK1(34)
-#define M_BCM1480_MC_DATA_CLASS             _SB_MAKEMASK1(35)
-#define M_BCM1480_MC_ADDR_CLASS             _SB_MAKEMASK1(36)
+#define M_BCM1480_MC_CLK_CLASS             _SB_MAKEMASK1(34)
+#define M_BCM1480_MC_DATA_CLASS                    _SB_MAKEMASK1(35)
+#define M_BCM1480_MC_ADDR_CLASS                    _SB_MAKEMASK1(36)

 
 

-#define M_BCM1480_MC_DQ_ODT_75              _SB_MAKEMASK1(37)
-#define M_BCM1480_MC_DQ_ODT_150             _SB_MAKEMASK1(38)
-#define M_BCM1480_MC_DQS_ODT_75             _SB_MAKEMASK1(39)
-#define M_BCM1480_MC_DQS_ODT_150            _SB_MAKEMASK1(40)
-#define M_BCM1480_MC_DQS_DIFF               _SB_MAKEMASK1(41)
+#define M_BCM1480_MC_DQ_ODT_75             _SB_MAKEMASK1(37)
+#define M_BCM1480_MC_DQ_ODT_150                    _SB_MAKEMASK1(38)
+#define M_BCM1480_MC_DQS_ODT_75                    _SB_MAKEMASK1(39)
+#define M_BCM1480_MC_DQS_ODT_150           _SB_MAKEMASK1(40)
+#define M_BCM1480_MC_DQS_DIFF              _SB_MAKEMASK1(41)

 
 /*
  * ECC Test Data Register (Table 95)
  */
 
 
 /*
  * ECC Test Data Register (Table 95)
  */
 

-#define S_BCM1480_MC_DATA_INVERT            0
-#define M_DATA_ECC_INVERT           _SB_MAKEMASK(64, S_BCM1480_MC_ECC_INVERT)
+#define S_BCM1480_MC_DATA_INVERT           0
+#define M_DATA_ECC_INVERT          _SB_MAKEMASK(64, S_BCM1480_MC_ECC_INVERT)

 
 /*
  * ECC Test ECC Register (Table 96)
  */
 
 
 /*
  * ECC Test ECC Register (Table 96)
  */
 

-#define S_BCM1480_MC_ECC_INVERT             0
-#define M_BCM1480_MC_ECC_INVERT             _SB_MAKEMASK(8, S_BCM1480_MC_ECC_INVERT)
+#define S_BCM1480_MC_ECC_INVERT                    0
+#define M_BCM1480_MC_ECC_INVERT                    _SB_MAKEMASK(8, S_BCM1480_MC_ECC_INVERT)

 
 /*
  * SDRAM Timing Register  (Table 97)
  */
 
 
 /*
  * SDRAM Timing Register  (Table 97)
  */
 

-#define S_BCM1480_MC_tRCD                   0
-#define M_BCM1480_MC_tRCD                   _SB_MAKEMASK(4, S_BCM1480_MC_tRCD)
-#define V_BCM1480_MC_tRCD(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRCD)
-#define G_BCM1480_MC_tRCD(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRCD, M_BCM1480_MC_tRCD)
-#define K_BCM1480_MC_tRCD_DEFAULT           3
-#define V_BCM1480_MC_tRCD_DEFAULT           V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT)
-
-#define S_BCM1480_MC_tCL                    4
-#define M_BCM1480_MC_tCL                    _SB_MAKEMASK(4, S_BCM1480_MC_tCL)
-#define V_BCM1480_MC_tCL(x)                 _SB_MAKEVALUE(x, S_BCM1480_MC_tCL)
-#define G_BCM1480_MC_tCL(x)                 _SB_GETVALUE(x, S_BCM1480_MC_tCL, M_BCM1480_MC_tCL)
-#define K_BCM1480_MC_tCL_DEFAULT            2
-#define V_BCM1480_MC_tCL_DEFAULT            V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT)
-
-#define M_BCM1480_MC_tCrDh                  _SB_MAKEMASK1(8)
-
-#define S_BCM1480_MC_tWR                    9
-#define M_BCM1480_MC_tWR                    _SB_MAKEMASK(3, S_BCM1480_MC_tWR)
-#define V_BCM1480_MC_tWR(x)                 _SB_MAKEVALUE(x, S_BCM1480_MC_tWR)
-#define G_BCM1480_MC_tWR(x)                 _SB_GETVALUE(x, S_BCM1480_MC_tWR, M_BCM1480_MC_tWR)
-#define K_BCM1480_MC_tWR_DEFAULT            2
-#define V_BCM1480_MC_tWR_DEFAULT            V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT)
-
-#define S_BCM1480_MC_tCwD                   12
-#define M_BCM1480_MC_tCwD                   _SB_MAKEMASK(4, S_BCM1480_MC_tCwD)
-#define V_BCM1480_MC_tCwD(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tCwD)
-#define G_BCM1480_MC_tCwD(x)                _SB_GETVALUE(x, S_BCM1480_MC_tCwD, M_BCM1480_MC_tCwD)
-#define K_BCM1480_MC_tCwD_DEFAULT           1
-#define V_BCM1480_MC_tCwD_DEFAULT           V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT)
-
-#define S_BCM1480_MC_tRP                    16
-#define M_BCM1480_MC_tRP                    _SB_MAKEMASK(4, S_BCM1480_MC_tRP)
-#define V_BCM1480_MC_tRP(x)                 _SB_MAKEVALUE(x, S_BCM1480_MC_tRP)
-#define G_BCM1480_MC_tRP(x)                 _SB_GETVALUE(x, S_BCM1480_MC_tRP, M_BCM1480_MC_tRP)
-#define K_BCM1480_MC_tRP_DEFAULT            4
-#define V_BCM1480_MC_tRP_DEFAULT            V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT)
-
-#define S_BCM1480_MC_tRRD                   20
-#define M_BCM1480_MC_tRRD                   _SB_MAKEMASK(4, S_BCM1480_MC_tRRD)
-#define V_BCM1480_MC_tRRD(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRRD)
-#define G_BCM1480_MC_tRRD(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRRD, M_BCM1480_MC_tRRD)
-#define K_BCM1480_MC_tRRD_DEFAULT           2
-#define V_BCM1480_MC_tRRD_DEFAULT           V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT)
-
-#define S_BCM1480_MC_tRCw                   24
-#define M_BCM1480_MC_tRCw                   _SB_MAKEMASK(5, S_BCM1480_MC_tRCw)
-#define V_BCM1480_MC_tRCw(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRCw)
-#define G_BCM1480_MC_tRCw(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRCw, M_BCM1480_MC_tRCw)
-#define K_BCM1480_MC_tRCw_DEFAULT           10
-#define V_BCM1480_MC_tRCw_DEFAULT           V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT)
-
-#define S_BCM1480_MC_tRCr                   32
-#define M_BCM1480_MC_tRCr                   _SB_MAKEMASK(5, S_BCM1480_MC_tRCr)
-#define V_BCM1480_MC_tRCr(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRCr)
-#define G_BCM1480_MC_tRCr(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRCr, M_BCM1480_MC_tRCr)
-#define K_BCM1480_MC_tRCr_DEFAULT           9
-#define V_BCM1480_MC_tRCr_DEFAULT           V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT)
+#define S_BCM1480_MC_tRCD                  0
+#define M_BCM1480_MC_tRCD                  _SB_MAKEMASK(4, S_BCM1480_MC_tRCD)
+#define V_BCM1480_MC_tRCD(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tRCD)
+#define G_BCM1480_MC_tRCD(x)               _SB_GETVALUE(x, S_BCM1480_MC_tRCD, M_BCM1480_MC_tRCD)
+#define K_BCM1480_MC_tRCD_DEFAULT          3
+#define V_BCM1480_MC_tRCD_DEFAULT          V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT)
+
+#define S_BCM1480_MC_tCL                   4
+#define M_BCM1480_MC_tCL                   _SB_MAKEMASK(4, S_BCM1480_MC_tCL)
+#define V_BCM1480_MC_tCL(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tCL)
+#define G_BCM1480_MC_tCL(x)                _SB_GETVALUE(x, S_BCM1480_MC_tCL, M_BCM1480_MC_tCL)
+#define K_BCM1480_MC_tCL_DEFAULT           2
+#define V_BCM1480_MC_tCL_DEFAULT           V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT)
+
+#define M_BCM1480_MC_tCrDh                 _SB_MAKEMASK1(8)
+
+#define S_BCM1480_MC_tWR                   9
+#define M_BCM1480_MC_tWR                   _SB_MAKEMASK(3, S_BCM1480_MC_tWR)
+#define V_BCM1480_MC_tWR(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tWR)
+#define G_BCM1480_MC_tWR(x)                _SB_GETVALUE(x, S_BCM1480_MC_tWR, M_BCM1480_MC_tWR)
+#define K_BCM1480_MC_tWR_DEFAULT           2
+#define V_BCM1480_MC_tWR_DEFAULT           V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT)
+
+#define S_BCM1480_MC_tCwD                  12
+#define M_BCM1480_MC_tCwD                  _SB_MAKEMASK(4, S_BCM1480_MC_tCwD)
+#define V_BCM1480_MC_tCwD(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tCwD)
+#define G_BCM1480_MC_tCwD(x)               _SB_GETVALUE(x, S_BCM1480_MC_tCwD, M_BCM1480_MC_tCwD)
+#define K_BCM1480_MC_tCwD_DEFAULT          1
+#define V_BCM1480_MC_tCwD_DEFAULT          V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT)
+
+#define S_BCM1480_MC_tRP                   16
+#define M_BCM1480_MC_tRP                   _SB_MAKEMASK(4, S_BCM1480_MC_tRP)
+#define V_BCM1480_MC_tRP(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRP)
+#define G_BCM1480_MC_tRP(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRP, M_BCM1480_MC_tRP)
+#define K_BCM1480_MC_tRP_DEFAULT           4
+#define V_BCM1480_MC_tRP_DEFAULT           V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT)
+
+#define S_BCM1480_MC_tRRD                  20
+#define M_BCM1480_MC_tRRD                  _SB_MAKEMASK(4, S_BCM1480_MC_tRRD)
+#define V_BCM1480_MC_tRRD(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tRRD)
+#define G_BCM1480_MC_tRRD(x)               _SB_GETVALUE(x, S_BCM1480_MC_tRRD, M_BCM1480_MC_tRRD)
+#define K_BCM1480_MC_tRRD_DEFAULT          2
+#define V_BCM1480_MC_tRRD_DEFAULT          V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT)
+
+#define S_BCM1480_MC_tRCw                  24
+#define M_BCM1480_MC_tRCw                  _SB_MAKEMASK(5, S_BCM1480_MC_tRCw)
+#define V_BCM1480_MC_tRCw(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tRCw)
+#define G_BCM1480_MC_tRCw(x)               _SB_GETVALUE(x, S_BCM1480_MC_tRCw, M_BCM1480_MC_tRCw)
+#define K_BCM1480_MC_tRCw_DEFAULT          10
+#define V_BCM1480_MC_tRCw_DEFAULT          V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT)
+
+#define S_BCM1480_MC_tRCr                  32
+#define M_BCM1480_MC_tRCr                  _SB_MAKEMASK(5, S_BCM1480_MC_tRCr)
+#define V_BCM1480_MC_tRCr(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tRCr)
+#define G_BCM1480_MC_tRCr(x)               _SB_GETVALUE(x, S_BCM1480_MC_tRCr, M_BCM1480_MC_tRCr)
+#define K_BCM1480_MC_tRCr_DEFAULT          9
+#define V_BCM1480_MC_tRCr_DEFAULT          V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT)

 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)

-#define S_BCM1480_MC_tFAW                   40
-#define M_BCM1480_MC_tFAW                   _SB_MAKEMASK(6, S_BCM1480_MC_tFAW)
-#define V_BCM1480_MC_tFAW(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tFAW)
-#define G_BCM1480_MC_tFAW(x)                _SB_GETVALUE(x, S_BCM1480_MC_tFAW, M_BCM1480_MC_tFAW)
-#define K_BCM1480_MC_tFAW_DEFAULT           0
-#define V_BCM1480_MC_tFAW_DEFAULT           V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT)
+#define S_BCM1480_MC_tFAW                  40
+#define M_BCM1480_MC_tFAW                  _SB_MAKEMASK(6, S_BCM1480_MC_tFAW)
+#define V_BCM1480_MC_tFAW(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tFAW)
+#define G_BCM1480_MC_tFAW(x)               _SB_GETVALUE(x, S_BCM1480_MC_tFAW, M_BCM1480_MC_tFAW)
+#define K_BCM1480_MC_tFAW_DEFAULT          0
+#define V_BCM1480_MC_tFAW_DEFAULT          V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT)

 #endif
 
 #endif
 

-#define S_BCM1480_MC_tRFC                   48
-#define M_BCM1480_MC_tRFC                   _SB_MAKEMASK(7, S_BCM1480_MC_tRFC)
-#define V_BCM1480_MC_tRFC(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRFC)
-#define G_BCM1480_MC_tRFC(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRFC, M_BCM1480_MC_tRFC)
-#define K_BCM1480_MC_tRFC_DEFAULT           12
-#define V_BCM1480_MC_tRFC_DEFAULT           V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT)
-
-#define S_BCM1480_MC_tFIFO                  56
-#define M_BCM1480_MC_tFIFO                  _SB_MAKEMASK(2, S_BCM1480_MC_tFIFO)
-#define V_BCM1480_MC_tFIFO(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tFIFO)
-#define G_BCM1480_MC_tFIFO(x)               _SB_GETVALUE(x, S_BCM1480_MC_tFIFO, M_BCM1480_MC_tFIFO)
-#define K_BCM1480_MC_tFIFO_DEFAULT          0
-#define V_BCM1480_MC_tFIFO_DEFAULT          V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT)
-
-#define S_BCM1480_MC_tW2R                  58
-#define M_BCM1480_MC_tW2R                  _SB_MAKEMASK(2, S_BCM1480_MC_tW2R)
-#define V_BCM1480_MC_tW2R(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tW2R)
-#define G_BCM1480_MC_tW2R(x)               _SB_GETVALUE(x, S_BCM1480_MC_tW2R, M_BCM1480_MC_tW2R)
-#define K_BCM1480_MC_tW2R_DEFAULT          1
-#define V_BCM1480_MC_tW2R_DEFAULT          V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT)
-
-#define S_BCM1480_MC_tR2W                  60
-#define M_BCM1480_MC_tR2W                  _SB_MAKEMASK(2, S_BCM1480_MC_tR2W)
-#define V_BCM1480_MC_tR2W(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tR2W)
-#define G_BCM1480_MC_tR2W(x)               _SB_GETVALUE(x, S_BCM1480_MC_tR2W, M_BCM1480_MC_tR2W)
-#define K_BCM1480_MC_tR2W_DEFAULT          0
-#define V_BCM1480_MC_tR2W_DEFAULT          V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT)
+#define S_BCM1480_MC_tRFC                  48
+#define M_BCM1480_MC_tRFC                  _SB_MAKEMASK(7, S_BCM1480_MC_tRFC)
+#define V_BCM1480_MC_tRFC(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tRFC)
+#define G_BCM1480_MC_tRFC(x)               _SB_GETVALUE(x, S_BCM1480_MC_tRFC, M_BCM1480_MC_tRFC)
+#define K_BCM1480_MC_tRFC_DEFAULT          12
+#define V_BCM1480_MC_tRFC_DEFAULT          V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT)
+
+#define S_BCM1480_MC_tFIFO                 56
+#define M_BCM1480_MC_tFIFO                 _SB_MAKEMASK(2, S_BCM1480_MC_tFIFO)
+#define V_BCM1480_MC_tFIFO(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_tFIFO)
+#define G_BCM1480_MC_tFIFO(x)              _SB_GETVALUE(x, S_BCM1480_MC_tFIFO, M_BCM1480_MC_tFIFO)
+#define K_BCM1480_MC_tFIFO_DEFAULT         0
+#define V_BCM1480_MC_tFIFO_DEFAULT         V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT)
+
+#define S_BCM1480_MC_tW2R                 58
+#define M_BCM1480_MC_tW2R                 _SB_MAKEMASK(2, S_BCM1480_MC_tW2R)
+#define V_BCM1480_MC_tW2R(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_tW2R)
+#define G_BCM1480_MC_tW2R(x)              _SB_GETVALUE(x, S_BCM1480_MC_tW2R, M_BCM1480_MC_tW2R)
+#define K_BCM1480_MC_tW2R_DEFAULT         1
+#define V_BCM1480_MC_tW2R_DEFAULT         V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT)
+
+#define S_BCM1480_MC_tR2W                 60
+#define M_BCM1480_MC_tR2W                 _SB_MAKEMASK(2, S_BCM1480_MC_tR2W)
+#define V_BCM1480_MC_tR2W(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_tR2W)
+#define G_BCM1480_MC_tR2W(x)              _SB_GETVALUE(x, S_BCM1480_MC_tR2W, M_BCM1480_MC_tR2W)
+#define K_BCM1480_MC_tR2W_DEFAULT         0
+#define V_BCM1480_MC_tR2W_DEFAULT         V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT)

 
 #define M_BCM1480_MC_tR2R                  _SB_MAKEMASK1(62)
 
 
 #define M_BCM1480_MC_tR2R                  _SB_MAKEMASK1(62)
 

-#define V_BCM1480_MC_TIMING_DEFAULT         (M_BCM1480_MC_tR2R | \
-                                     V_BCM1480_MC_tFIFO_DEFAULT | \
-                                     V_BCM1480_MC_tR2W_DEFAULT | \
-                                     V_BCM1480_MC_tW2R_DEFAULT | \
-                                     V_BCM1480_MC_tRFC_DEFAULT | \
-                                     V_BCM1480_MC_tRCr_DEFAULT | \
-                                     V_BCM1480_MC_tRCw_DEFAULT | \
-                                     V_BCM1480_MC_tRRD_DEFAULT | \
-                                     V_BCM1480_MC_tRP_DEFAULT | \
-                                     V_BCM1480_MC_tCwD_DEFAULT | \
-                                     V_BCM1480_MC_tWR_DEFAULT | \
-                                     M_BCM1480_MC_tCrDh | \
-                                     V_BCM1480_MC_tCL_DEFAULT | \
-                                     V_BCM1480_MC_tRCD_DEFAULT)
+#define V_BCM1480_MC_TIMING_DEFAULT        (M_BCM1480_MC_tR2R | \
+                                    V_BCM1480_MC_tFIFO_DEFAULT | \
+                                    V_BCM1480_MC_tR2W_DEFAULT | \
+                                    V_BCM1480_MC_tW2R_DEFAULT | \
+                                    V_BCM1480_MC_tRFC_DEFAULT | \
+                                    V_BCM1480_MC_tRCr_DEFAULT | \
+                                    V_BCM1480_MC_tRCw_DEFAULT | \
+                                    V_BCM1480_MC_tRRD_DEFAULT | \
+                                    V_BCM1480_MC_tRP_DEFAULT | \
+                                    V_BCM1480_MC_tCwD_DEFAULT | \
+                                    V_BCM1480_MC_tWR_DEFAULT | \
+                                    M_BCM1480_MC_tCrDh | \
+                                    V_BCM1480_MC_tCL_DEFAULT | \
+                                    V_BCM1480_MC_tRCD_DEFAULT)

 
 /*
  * SDRAM Timing Register 2
 
 /*
  * SDRAM Timing Register 2


@@ -834,33 +834,33 @@
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 

-#define S_BCM1480_MC_tAL                   0
-#define M_BCM1480_MC_tAL                   _SB_MAKEMASK(4, S_BCM1480_MC_tAL)
-#define V_BCM1480_MC_tAL(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tAL)
-#define G_BCM1480_MC_tAL(x)                _SB_GETVALUE(x, S_BCM1480_MC_tAL, M_BCM1480_MC_tAL)
-#define K_BCM1480_MC_tAL_DEFAULT           0
-#define V_BCM1480_MC_tAL_DEFAULT           V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT)
-
-#define S_BCM1480_MC_tRTP                   4
-#define M_BCM1480_MC_tRTP                   _SB_MAKEMASK(3, S_BCM1480_MC_tRTP)
-#define V_BCM1480_MC_tRTP(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRTP)
-#define G_BCM1480_MC_tRTP(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRTP, M_BCM1480_MC_tRTP)
-#define K_BCM1480_MC_tRTP_DEFAULT           2
-#define V_BCM1480_MC_tRTP_DEFAULT           V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT)
-
-#define S_BCM1480_MC_tW2W                   8
-#define M_BCM1480_MC_tW2W                   _SB_MAKEMASK(2, S_BCM1480_MC_tW2W)
-#define V_BCM1480_MC_tW2W(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tW2W)
-#define G_BCM1480_MC_tW2W(x)                _SB_GETVALUE(x, S_BCM1480_MC_tW2W, M_BCM1480_MC_tW2W)
-#define K_BCM1480_MC_tW2W_DEFAULT           0
-#define V_BCM1480_MC_tW2W_DEFAULT           V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT)
-
-#define S_BCM1480_MC_tRAP                   12
-#define M_BCM1480_MC_tRAP                  _SB_MAKEMASK(4, S_BCM1480_MC_tRAP)
-#define V_BCM1480_MC_tRAP(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRAP)
-#define G_BCM1480_MC_tRAP(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRAP, M_BCM1480_MC_tRAP)
-#define K_BCM1480_MC_tRAP_DEFAULT           0
-#define V_BCM1480_MC_tRAP_DEFAULT           V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT)
+#define S_BCM1480_MC_tAL                  0
+#define M_BCM1480_MC_tAL                  _SB_MAKEMASK(4, S_BCM1480_MC_tAL)
+#define V_BCM1480_MC_tAL(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tAL)
+#define G_BCM1480_MC_tAL(x)               _SB_GETVALUE(x, S_BCM1480_MC_tAL, M_BCM1480_MC_tAL)
+#define K_BCM1480_MC_tAL_DEFAULT          0
+#define V_BCM1480_MC_tAL_DEFAULT          V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT)
+
+#define S_BCM1480_MC_tRTP                  4
+#define M_BCM1480_MC_tRTP                  _SB_MAKEMASK(3, S_BCM1480_MC_tRTP)
+#define V_BCM1480_MC_tRTP(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tRTP)
+#define G_BCM1480_MC_tRTP(x)               _SB_GETVALUE(x, S_BCM1480_MC_tRTP, M_BCM1480_MC_tRTP)
+#define K_BCM1480_MC_tRTP_DEFAULT          2
+#define V_BCM1480_MC_tRTP_DEFAULT          V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT)
+
+#define S_BCM1480_MC_tW2W                  8
+#define M_BCM1480_MC_tW2W                  _SB_MAKEMASK(2, S_BCM1480_MC_tW2W)
+#define V_BCM1480_MC_tW2W(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tW2W)
+#define G_BCM1480_MC_tW2W(x)               _SB_GETVALUE(x, S_BCM1480_MC_tW2W, M_BCM1480_MC_tW2W)
+#define K_BCM1480_MC_tW2W_DEFAULT          0
+#define V_BCM1480_MC_tW2W_DEFAULT          V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT)
+
+#define S_BCM1480_MC_tRAP                  12
+#define M_BCM1480_MC_tRAP                 _SB_MAKEMASK(4, S_BCM1480_MC_tRAP)
+#define V_BCM1480_MC_tRAP(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tRAP)
+#define G_BCM1480_MC_tRAP(x)               _SB_GETVALUE(x, S_BCM1480_MC_tRAP, M_BCM1480_MC_tRAP)
+#define K_BCM1480_MC_tRAP_DEFAULT          0
+#define V_BCM1480_MC_tRAP_DEFAULT          V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT)

 
 #endif
 
 
 #endif
 


@@ -874,111 +874,111 @@
  * Global Configuration Register (Table 99)
  */
 
  * Global Configuration Register (Table 99)
  */
 

-#define S_BCM1480_MC_BLK_SET_MARK           8
-#define M_BCM1480_MC_BLK_SET_MARK           _SB_MAKEMASK(4, S_BCM1480_MC_BLK_SET_MARK)
-#define V_BCM1480_MC_BLK_SET_MARK(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_SET_MARK)
-#define G_BCM1480_MC_BLK_SET_MARK(x)        _SB_GETVALUE(x, S_BCM1480_MC_BLK_SET_MARK, M_BCM1480_MC_BLK_SET_MARK)
+#define S_BCM1480_MC_BLK_SET_MARK          8
+#define M_BCM1480_MC_BLK_SET_MARK          _SB_MAKEMASK(4, S_BCM1480_MC_BLK_SET_MARK)
+#define V_BCM1480_MC_BLK_SET_MARK(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_SET_MARK)
+#define G_BCM1480_MC_BLK_SET_MARK(x)       _SB_GETVALUE(x, S_BCM1480_MC_BLK_SET_MARK, M_BCM1480_MC_BLK_SET_MARK)

 
 

-#define S_BCM1480_MC_BLK_CLR_MARK           12
-#define M_BCM1480_MC_BLK_CLR_MARK           _SB_MAKEMASK(4, S_BCM1480_MC_BLK_CLR_MARK)
-#define V_BCM1480_MC_BLK_CLR_MARK(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_CLR_MARK)
-#define G_BCM1480_MC_BLK_CLR_MARK(x)        _SB_GETVALUE(x, S_BCM1480_MC_BLK_CLR_MARK, M_BCM1480_MC_BLK_CLR_MARK)
+#define S_BCM1480_MC_BLK_CLR_MARK          12
+#define M_BCM1480_MC_BLK_CLR_MARK          _SB_MAKEMASK(4, S_BCM1480_MC_BLK_CLR_MARK)
+#define V_BCM1480_MC_BLK_CLR_MARK(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_CLR_MARK)
+#define G_BCM1480_MC_BLK_CLR_MARK(x)       _SB_GETVALUE(x, S_BCM1480_MC_BLK_CLR_MARK, M_BCM1480_MC_BLK_CLR_MARK)

 
 

-#define M_BCM1480_MC_PKT_PRIORITY           _SB_MAKEMASK1(16)
+#define M_BCM1480_MC_PKT_PRIORITY          _SB_MAKEMASK1(16)

 
 

-#define S_BCM1480_MC_MAX_AGE                20
-#define M_BCM1480_MC_MAX_AGE                _SB_MAKEMASK(4, S_BCM1480_MC_MAX_AGE)
-#define V_BCM1480_MC_MAX_AGE(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_MAX_AGE)
-#define G_BCM1480_MC_MAX_AGE(x)             _SB_GETVALUE(x, S_BCM1480_MC_MAX_AGE, M_BCM1480_MC_MAX_AGE)
+#define S_BCM1480_MC_MAX_AGE               20
+#define M_BCM1480_MC_MAX_AGE               _SB_MAKEMASK(4, S_BCM1480_MC_MAX_AGE)
+#define V_BCM1480_MC_MAX_AGE(x)                    _SB_MAKEVALUE(x, S_BCM1480_MC_MAX_AGE)
+#define G_BCM1480_MC_MAX_AGE(x)                    _SB_GETVALUE(x, S_BCM1480_MC_MAX_AGE, M_BCM1480_MC_MAX_AGE)

 
 

-#define M_BCM1480_MC_BERR_DISABLE           _SB_MAKEMASK1(29)
-#define M_BCM1480_MC_FORCE_SEQ              _SB_MAKEMASK1(30)
-#define M_BCM1480_MC_VGEN                   _SB_MAKEMASK1(32)
+#define M_BCM1480_MC_BERR_DISABLE          _SB_MAKEMASK1(29)
+#define M_BCM1480_MC_FORCE_SEQ             _SB_MAKEMASK1(30)
+#define M_BCM1480_MC_VGEN                  _SB_MAKEMASK1(32)

 
 

-#define S_BCM1480_MC_SLEW                   33
-#define M_BCM1480_MC_SLEW                   _SB_MAKEMASK(2, S_BCM1480_MC_SLEW)
-#define V_BCM1480_MC_SLEW(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_SLEW)
-#define G_BCM1480_MC_SLEW(x)                _SB_GETVALUE(x, S_BCM1480_MC_SLEW, M_BCM1480_MC_SLEW)
+#define S_BCM1480_MC_SLEW                  33
+#define M_BCM1480_MC_SLEW                  _SB_MAKEMASK(2, S_BCM1480_MC_SLEW)
+#define V_BCM1480_MC_SLEW(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_SLEW)
+#define G_BCM1480_MC_SLEW(x)               _SB_GETVALUE(x, S_BCM1480_MC_SLEW, M_BCM1480_MC_SLEW)

 
 

-#define M_BCM1480_MC_SSTL_VOLTAGE           _SB_MAKEMASK1(35)
+#define M_BCM1480_MC_SSTL_VOLTAGE          _SB_MAKEMASK1(35)

 
 /*
  * Global Channel Interleave Register (Table 100)
  */
 
 
 /*
  * Global Channel Interleave Register (Table 100)
  */
 

-#define S_BCM1480_MC_INTLV0                 0
-#define M_BCM1480_MC_INTLV0                 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0)
-#define V_BCM1480_MC_INTLV0(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0)
-#define G_BCM1480_MC_INTLV0(x)              _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0)
-
-#define S_BCM1480_MC_INTLV1                 8
-#define M_BCM1480_MC_INTLV1                 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1)
-#define V_BCM1480_MC_INTLV1(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1)
-#define G_BCM1480_MC_INTLV1(x)              _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1)
-
-#define S_BCM1480_MC_INTLV_MODE             16
-#define M_BCM1480_MC_INTLV_MODE             _SB_MAKEMASK(3, S_BCM1480_MC_INTLV_MODE)
-#define V_BCM1480_MC_INTLV_MODE(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV_MODE)
-#define G_BCM1480_MC_INTLV_MODE(x)          _SB_GETVALUE(x, S_BCM1480_MC_INTLV_MODE, M_BCM1480_MC_INTLV_MODE)
-
-#define K_BCM1480_MC_INTLV_MODE_NONE        0x0
-#define K_BCM1480_MC_INTLV_MODE_01          0x1
-#define K_BCM1480_MC_INTLV_MODE_23          0x2
-#define K_BCM1480_MC_INTLV_MODE_01_23       0x3
-#define K_BCM1480_MC_INTLV_MODE_0123        0x4
-
-#define V_BCM1480_MC_INTLV_MODE_NONE        V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_NONE)
-#define V_BCM1480_MC_INTLV_MODE_01          V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01)
-#define V_BCM1480_MC_INTLV_MODE_23          V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_23)
-#define V_BCM1480_MC_INTLV_MODE_01_23       V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01_23)
-#define V_BCM1480_MC_INTLV_MODE_0123        V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_0123)
+#define S_BCM1480_MC_INTLV0                0
+#define M_BCM1480_MC_INTLV0                _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0)
+#define V_BCM1480_MC_INTLV0(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0)
+#define G_BCM1480_MC_INTLV0(x)             _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0)
+
+#define S_BCM1480_MC_INTLV1                8
+#define M_BCM1480_MC_INTLV1                _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1)
+#define V_BCM1480_MC_INTLV1(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1)
+#define G_BCM1480_MC_INTLV1(x)             _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1)
+
+#define S_BCM1480_MC_INTLV_MODE                    16
+#define M_BCM1480_MC_INTLV_MODE                    _SB_MAKEMASK(3, S_BCM1480_MC_INTLV_MODE)
+#define V_BCM1480_MC_INTLV_MODE(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV_MODE)
+#define G_BCM1480_MC_INTLV_MODE(x)         _SB_GETVALUE(x, S_BCM1480_MC_INTLV_MODE, M_BCM1480_MC_INTLV_MODE)
+
+#define K_BCM1480_MC_INTLV_MODE_NONE       0x0
+#define K_BCM1480_MC_INTLV_MODE_01         0x1
+#define K_BCM1480_MC_INTLV_MODE_23         0x2
+#define K_BCM1480_MC_INTLV_MODE_01_23      0x3
+#define K_BCM1480_MC_INTLV_MODE_0123       0x4
+
+#define V_BCM1480_MC_INTLV_MODE_NONE       V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_NONE)
+#define V_BCM1480_MC_INTLV_MODE_01         V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01)
+#define V_BCM1480_MC_INTLV_MODE_23         V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_23)
+#define V_BCM1480_MC_INTLV_MODE_01_23      V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01_23)
+#define V_BCM1480_MC_INTLV_MODE_0123       V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_0123)

 
 /*
  * ECC Status Register
  */
 
 
 /*
  * ECC Status Register
  */
 

-#define S_BCM1480_MC_ECC_ERR_ADDR           0
-#define M_BCM1480_MC_ECC_ERR_ADDR           _SB_MAKEMASK(37, S_BCM1480_MC_ECC_ERR_ADDR)
-#define V_BCM1480_MC_ECC_ERR_ADDR(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR)
-#define G_BCM1480_MC_ECC_ERR_ADDR(x)        _SB_GETVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR, M_BCM1480_MC_ECC_ERR_ADDR)
+#define S_BCM1480_MC_ECC_ERR_ADDR          0
+#define M_BCM1480_MC_ECC_ERR_ADDR          _SB_MAKEMASK(37, S_BCM1480_MC_ECC_ERR_ADDR)
+#define V_BCM1480_MC_ECC_ERR_ADDR(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR)
+#define G_BCM1480_MC_ECC_ERR_ADDR(x)       _SB_GETVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR, M_BCM1480_MC_ECC_ERR_ADDR)

 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)

-#define M_BCM1480_MC_ECC_ERR_RMW            _SB_MAKEMASK1(60)
+#define M_BCM1480_MC_ECC_ERR_RMW           _SB_MAKEMASK1(60)

 #endif
 
 #endif
 

-#define M_BCM1480_MC_ECC_MULT_ERR_DET       _SB_MAKEMASK1(61)
-#define M_BCM1480_MC_ECC_UERR_DET           _SB_MAKEMASK1(62)
-#define M_BCM1480_MC_ECC_CERR_DET           _SB_MAKEMASK1(63)
+#define M_BCM1480_MC_ECC_MULT_ERR_DET      _SB_MAKEMASK1(61)
+#define M_BCM1480_MC_ECC_UERR_DET          _SB_MAKEMASK1(62)
+#define M_BCM1480_MC_ECC_CERR_DET          _SB_MAKEMASK1(63)

 
 /*
  * Global ECC Address Register (Table 102)
  */
 
 
 /*
  * Global ECC Address Register (Table 102)
  */
 

-#define S_BCM1480_MC_ECC_CORR_ADDR          0
-#define M_BCM1480_MC_ECC_CORR_ADDR          _SB_MAKEMASK(37, S_BCM1480_MC_ECC_CORR_ADDR)
-#define V_BCM1480_MC_ECC_CORR_ADDR(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR)
-#define G_BCM1480_MC_ECC_CORR_ADDR(x)       _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR, M_BCM1480_MC_ECC_CORR_ADDR)
+#define S_BCM1480_MC_ECC_CORR_ADDR         0
+#define M_BCM1480_MC_ECC_CORR_ADDR         _SB_MAKEMASK(37, S_BCM1480_MC_ECC_CORR_ADDR)
+#define V_BCM1480_MC_ECC_CORR_ADDR(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR)
+#define G_BCM1480_MC_ECC_CORR_ADDR(x)      _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR, M_BCM1480_MC_ECC_CORR_ADDR)

 
 /*
  * Global ECC Correction Register (Table 103)
  */
 
 
 /*
  * Global ECC Correction Register (Table 103)
  */
 

-#define S_BCM1480_MC_ECC_CORRECT            0
-#define M_BCM1480_MC_ECC_CORRECT            _SB_MAKEMASK(64, S_BCM1480_MC_ECC_CORRECT)
-#define V_BCM1480_MC_ECC_CORRECT(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORRECT)
-#define G_BCM1480_MC_ECC_CORRECT(x)         _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORRECT, M_BCM1480_MC_ECC_CORRECT)
+#define S_BCM1480_MC_ECC_CORRECT           0
+#define M_BCM1480_MC_ECC_CORRECT           _SB_MAKEMASK(64, S_BCM1480_MC_ECC_CORRECT)
+#define V_BCM1480_MC_ECC_CORRECT(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORRECT)
+#define G_BCM1480_MC_ECC_CORRECT(x)        _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORRECT, M_BCM1480_MC_ECC_CORRECT)

 
 /*
  * Global ECC Performance Counters Control Register (Table 104)
  */
 
 
 /*
  * Global ECC Performance Counters Control Register (Table 104)
  */
 

-#define S_BCM1480_MC_CHANNEL_SELECT         0
-#define M_BCM1480_MC_CHANNEL_SELECT         _SB_MAKEMASK(4, S_BCM1480_MC_CHANNEL_SELECT)
-#define V_BCM1480_MC_CHANNEL_SELECT(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_CHANNEL_SELECT)
-#define G_BCM1480_MC_CHANNEL_SELECT(x)      _SB_GETVALUE(x, S_BCM1480_MC_CHANNEL_SELECT, M_BCM1480_MC_CHANNEL_SELECT)
-#define K_BCM1480_MC_CHANNEL_SELECT_0       0x1
-#define K_BCM1480_MC_CHANNEL_SELECT_1       0x2
-#define K_BCM1480_MC_CHANNEL_SELECT_2       0x4
-#define K_BCM1480_MC_CHANNEL_SELECT_3       0x8
+#define S_BCM1480_MC_CHANNEL_SELECT        0
+#define M_BCM1480_MC_CHANNEL_SELECT        _SB_MAKEMASK(4, S_BCM1480_MC_CHANNEL_SELECT)
+#define V_BCM1480_MC_CHANNEL_SELECT(x)     _SB_MAKEVALUE(x, S_BCM1480_MC_CHANNEL_SELECT)
+#define G_BCM1480_MC_CHANNEL_SELECT(x)     _SB_GETVALUE(x, S_BCM1480_MC_CHANNEL_SELECT, M_BCM1480_MC_CHANNEL_SELECT)
+#define K_BCM1480_MC_CHANNEL_SELECT_0      0x1
+#define K_BCM1480_MC_CHANNEL_SELECT_1      0x2
+#define K_BCM1480_MC_CHANNEL_SELECT_2      0x4
+#define K_BCM1480_MC_CHANNEL_SELECT_3      0x8

 
 #endif /* _BCM1480_MC_H */
 
 #endif /* _BCM1480_MC_H */

diff --git a/arch/mips/include/asm/sibyte/bcm1480_regs.h b/arch/mips/include/asm/sibyte/bcm1480_regs.h
index 84d168ddfebb05f7f82cbb553a97df5f53084da5..ec0dacf6f0cb58616612155f160b9eede2d6d0ca 100644 (file)
--- a/arch/mips/include/asm/sibyte/bcm1480_regs.h
+++ b/arch/mips/include/asm/sibyte/bcm1480_regs.h
@@ -1,7 +1,7 @@
 /*  *********************************************************************
     *  BCM1255/BCM1280/BCM1455/BCM1480 Board Support Package
     *
 /*  *********************************************************************
     *  BCM1255/BCM1280/BCM1455/BCM1480 Board Support Package
     *

-    *  Register Definitions                     File: bcm1480_regs.h
+    *  Register Definitions                    File: bcm1480_regs.h

     *
     *  This module contains the addresses of the on-chip peripherals
     *  on the BCM1280 and BCM1480.
     *
     *  This module contains the addresses of the on-chip peripherals
     *  on the BCM1280 and BCM1480.


@@ -80,48 +80,48 @@
     * Memory Controller Registers (Section 6)
     ********************************************************************* */
 
     * Memory Controller Registers (Section 6)
     ********************************************************************* */
 

-#define A_BCM1480_MC_BASE_0                 0x0010050000
-#define A_BCM1480_MC_BASE_1                 0x0010051000
-#define A_BCM1480_MC_BASE_2                 0x0010052000
-#define A_BCM1480_MC_BASE_3                 0x0010053000
-#define BCM1480_MC_REGISTER_SPACING         0x1000
+#define A_BCM1480_MC_BASE_0                0x0010050000
+#define A_BCM1480_MC_BASE_1                0x0010051000
+#define A_BCM1480_MC_BASE_2                0x0010052000
+#define A_BCM1480_MC_BASE_3                0x0010053000
+#define BCM1480_MC_REGISTER_SPACING        0x1000

 
 

-#define A_BCM1480_MC_BASE(ctlid)            (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING)
+#define A_BCM1480_MC_BASE(ctlid)           (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING)

 #define A_BCM1480_MC_REGISTER(ctlid, reg)    (A_BCM1480_MC_BASE(ctlid)+(reg))
 
 #define A_BCM1480_MC_REGISTER(ctlid, reg)    (A_BCM1480_MC_BASE(ctlid)+(reg))
 

-#define R_BCM1480_MC_CONFIG                 0x0000000100
-#define R_BCM1480_MC_CS_START               0x0000000120
-#define R_BCM1480_MC_CS_END                 0x0000000140
-#define S_BCM1480_MC_CS_STARTEND            24
-
-#define R_BCM1480_MC_CS01_ROW0              0x0000000180
-#define R_BCM1480_MC_CS01_ROW1              0x00000001A0
-#define R_BCM1480_MC_CS23_ROW0              0x0000000200
-#define R_BCM1480_MC_CS23_ROW1              0x0000000220
-#define R_BCM1480_MC_CS01_COL0              0x0000000280
-#define R_BCM1480_MC_CS01_COL1              0x00000002A0
-#define R_BCM1480_MC_CS23_COL0              0x0000000300
-#define R_BCM1480_MC_CS23_COL1              0x0000000320
-
-#define R_BCM1480_MC_CSX_BASE               0x0000000180
-#define R_BCM1480_MC_CSX_ROW0               0x0000000000   /* relative to CSX_BASE */
-#define R_BCM1480_MC_CSX_ROW1               0x0000000020   /* relative to CSX_BASE */
-#define R_BCM1480_MC_CSX_COL0               0x0000000100   /* relative to CSX_BASE */
-#define R_BCM1480_MC_CSX_COL1               0x0000000120   /* relative to CSX_BASE */
-#define BCM1480_MC_CSX_SPACING              0x0000000080   /* CS23 relative to CS01 */
-
-#define R_BCM1480_MC_CS01_BA                0x0000000380
-#define R_BCM1480_MC_CS23_BA                0x00000003A0
-#define R_BCM1480_MC_DRAMCMD                0x0000000400
-#define R_BCM1480_MC_DRAMMODE               0x0000000420
-#define R_BCM1480_MC_CLOCK_CFG              0x0000000440
-#define R_BCM1480_MC_MCLK_CFG               R_BCM1480_MC_CLOCK_CFG
-#define R_BCM1480_MC_TEST_DATA              0x0000000480
-#define R_BCM1480_MC_TEST_ECC               0x00000004A0
-#define R_BCM1480_MC_TIMING1                0x00000004C0
-#define R_BCM1480_MC_TIMING2                0x00000004E0
-#define R_BCM1480_MC_DLL_CFG                0x0000000500
-#define R_BCM1480_MC_DRIVE_CFG              0x0000000520
+#define R_BCM1480_MC_CONFIG                0x0000000100
+#define R_BCM1480_MC_CS_START              0x0000000120
+#define R_BCM1480_MC_CS_END                0x0000000140
+#define S_BCM1480_MC_CS_STARTEND           24
+
+#define R_BCM1480_MC_CS01_ROW0             0x0000000180
+#define R_BCM1480_MC_CS01_ROW1             0x00000001A0
+#define R_BCM1480_MC_CS23_ROW0             0x0000000200
+#define R_BCM1480_MC_CS23_ROW1             0x0000000220
+#define R_BCM1480_MC_CS01_COL0             0x0000000280
+#define R_BCM1480_MC_CS01_COL1             0x00000002A0
+#define R_BCM1480_MC_CS23_COL0             0x0000000300
+#define R_BCM1480_MC_CS23_COL1             0x0000000320
+
+#define R_BCM1480_MC_CSX_BASE              0x0000000180
+#define R_BCM1480_MC_CSX_ROW0              0x0000000000   /* relative to CSX_BASE */
+#define R_BCM1480_MC_CSX_ROW1              0x0000000020   /* relative to CSX_BASE */
+#define R_BCM1480_MC_CSX_COL0              0x0000000100   /* relative to CSX_BASE */
+#define R_BCM1480_MC_CSX_COL1              0x0000000120   /* relative to CSX_BASE */
+#define BCM1480_MC_CSX_SPACING             0x0000000080   /* CS23 relative to CS01 */
+
+#define R_BCM1480_MC_CS01_BA               0x0000000380
+#define R_BCM1480_MC_CS23_BA               0x00000003A0
+#define R_BCM1480_MC_DRAMCMD               0x0000000400
+#define R_BCM1480_MC_DRAMMODE              0x0000000420
+#define R_BCM1480_MC_CLOCK_CFG             0x0000000440
+#define R_BCM1480_MC_MCLK_CFG              R_BCM1480_MC_CLOCK_CFG
+#define R_BCM1480_MC_TEST_DATA             0x0000000480
+#define R_BCM1480_MC_TEST_ECC              0x00000004A0
+#define R_BCM1480_MC_TIMING1               0x00000004C0
+#define R_BCM1480_MC_TIMING2               0x00000004E0
+#define R_BCM1480_MC_DLL_CFG               0x0000000500
+#define R_BCM1480_MC_DRIVE_CFG             0x0000000520

 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 #define R_BCM1480_MC_ODT                   0x0000000460
 
 #if SIBYTE_HDR_FEATURE(1480, PASS2)
 #define R_BCM1480_MC_ODT                   0x0000000460


@@ -129,55 +129,55 @@
 #endif
 
 /* Global registers (single instance) */
 #endif
 
 /* Global registers (single instance) */

-#define A_BCM1480_MC_GLB_CONFIG             0x0010054100
-#define A_BCM1480_MC_GLB_INTLV              0x0010054120
-#define A_BCM1480_MC_GLB_ECC_STATUS         0x0010054140
-#define A_BCM1480_MC_GLB_ECC_ADDR           0x0010054160
-#define A_BCM1480_MC_GLB_ECC_CORRECT        0x0010054180
+#define A_BCM1480_MC_GLB_CONFIG                    0x0010054100
+#define A_BCM1480_MC_GLB_INTLV             0x0010054120
+#define A_BCM1480_MC_GLB_ECC_STATUS        0x0010054140
+#define A_BCM1480_MC_GLB_ECC_ADDR          0x0010054160
+#define A_BCM1480_MC_GLB_ECC_CORRECT       0x0010054180

 #define A_BCM1480_MC_GLB_PERF_CNT_CONTROL   0x00100541A0
 
 /*  *********************************************************************
     * L2 Cache Control Registers (Section 5)
     ********************************************************************* */
 
 #define A_BCM1480_MC_GLB_PERF_CNT_CONTROL   0x00100541A0
 
 /*  *********************************************************************
     * L2 Cache Control Registers (Section 5)
     ********************************************************************* */
 

-#define A_BCM1480_L2_BASE                   0x0010040000
+#define A_BCM1480_L2_BASE                  0x0010040000

 
 

-#define A_BCM1480_L2_READ_TAG               0x0010040018
-#define A_BCM1480_L2_ECC_TAG                0x0010040038
-#define A_BCM1480_L2_MISC0_VALUE            0x0010040058
-#define A_BCM1480_L2_MISC1_VALUE            0x0010040078
-#define A_BCM1480_L2_MISC2_VALUE            0x0010040098
-#define A_BCM1480_L2_MISC_CONFIG            0x0010040040       /* x040 */
-#define A_BCM1480_L2_CACHE_DISABLE          0x0010040060       /* x060 */
+#define A_BCM1480_L2_READ_TAG              0x0010040018
+#define A_BCM1480_L2_ECC_TAG               0x0010040038
+#define A_BCM1480_L2_MISC0_VALUE           0x0010040058
+#define A_BCM1480_L2_MISC1_VALUE           0x0010040078
+#define A_BCM1480_L2_MISC2_VALUE           0x0010040098
+#define A_BCM1480_L2_MISC_CONFIG           0x0010040040        /* x040 */
+#define A_BCM1480_L2_CACHE_DISABLE         0x0010040060        /* x060 */

 #define A_BCM1480_L2_MAKECACHEDISABLE(x)    (A_BCM1480_L2_CACHE_DISABLE | (((x)&0xF) << 12))
 #define A_BCM1480_L2_MAKECACHEDISABLE(x)    (A_BCM1480_L2_CACHE_DISABLE | (((x)&0xF) << 12))

-#define A_BCM1480_L2_WAY_ENABLE_3_0         0x0010040080       /* x080 */
-#define A_BCM1480_L2_WAY_ENABLE_7_4         0x00100400A0       /* x0A0 */
+#define A_BCM1480_L2_WAY_ENABLE_3_0        0x0010040080        /* x080 */
+#define A_BCM1480_L2_WAY_ENABLE_7_4        0x00100400A0        /* x0A0 */

 #define A_BCM1480_L2_MAKE_WAY_ENABLE_LO(x)  (A_BCM1480_L2_WAY_ENABLE_3_0 | (((x)&0xF) << 12))
 #define A_BCM1480_L2_MAKE_WAY_ENABLE_HI(x)  (A_BCM1480_L2_WAY_ENABLE_7_4 | (((x)&0xF) << 12))
 #define A_BCM1480_L2_MAKE_WAY_DISABLE_LO(x)  (A_BCM1480_L2_WAY_ENABLE_3_0 | (((~x)&0xF) << 12))
 #define A_BCM1480_L2_MAKE_WAY_DISABLE_HI(x)  (A_BCM1480_L2_WAY_ENABLE_7_4 | (((~x)&0xF) << 12))
 #define A_BCM1480_L2_MAKE_WAY_ENABLE_LO(x)  (A_BCM1480_L2_WAY_ENABLE_3_0 | (((x)&0xF) << 12))
 #define A_BCM1480_L2_MAKE_WAY_ENABLE_HI(x)  (A_BCM1480_L2_WAY_ENABLE_7_4 | (((x)&0xF) << 12))
 #define A_BCM1480_L2_MAKE_WAY_DISABLE_LO(x)  (A_BCM1480_L2_WAY_ENABLE_3_0 | (((~x)&0xF) << 12))
 #define A_BCM1480_L2_MAKE_WAY_DISABLE_HI(x)  (A_BCM1480_L2_WAY_ENABLE_7_4 | (((~x)&0xF) << 12))

-#define A_BCM1480_L2_WAY_LOCAL_3_0          0x0010040100       /* x100 */
-#define A_BCM1480_L2_WAY_LOCAL_7_4          0x0010040120       /* x120 */
-#define A_BCM1480_L2_WAY_REMOTE_3_0         0x0010040140       /* x140 */
-#define A_BCM1480_L2_WAY_REMOTE_7_4         0x0010040160       /* x160 */
-#define A_BCM1480_L2_WAY_AGENT_3_0          0x00100400C0       /* xxC0 */
-#define A_BCM1480_L2_WAY_AGENT_7_4          0x00100400E0       /* xxE0 */
+#define A_BCM1480_L2_WAY_LOCAL_3_0         0x0010040100        /* x100 */
+#define A_BCM1480_L2_WAY_LOCAL_7_4         0x0010040120        /* x120 */
+#define A_BCM1480_L2_WAY_REMOTE_3_0        0x0010040140        /* x140 */
+#define A_BCM1480_L2_WAY_REMOTE_7_4        0x0010040160        /* x160 */
+#define A_BCM1480_L2_WAY_AGENT_3_0         0x00100400C0        /* xxC0 */
+#define A_BCM1480_L2_WAY_AGENT_7_4         0x00100400E0        /* xxE0 */

 #define A_BCM1480_L2_WAY_ENABLE(A, banks)   (A | (((~(banks))&0x0F) << 8))
 #define A_BCM1480_L2_WAY_ENABLE(A, banks)   (A | (((~(banks))&0x0F) << 8))

-#define A_BCM1480_L2_BANK_BASE              0x00D0300000
-#define A_BCM1480_L2_BANK_ADDRESS(b)        (A_BCM1480_L2_BANK_BASE | (((b)&0x7)<<17))
-#define A_BCM1480_L2_MGMT_TAG_BASE          0x00D0000000
+#define A_BCM1480_L2_BANK_BASE             0x00D0300000
+#define A_BCM1480_L2_BANK_ADDRESS(b)       (A_BCM1480_L2_BANK_BASE | (((b)&0x7)<<17))
+#define A_BCM1480_L2_MGMT_TAG_BASE         0x00D0000000

 
 
 /*  *********************************************************************
     * PCI-X Interface Registers (Section 7)
     ********************************************************************* */
 
 
 
 /*  *********************************************************************
     * PCI-X Interface Registers (Section 7)
     ********************************************************************* */
 

-#define A_BCM1480_PCI_BASE                  0x0010061400
+#define A_BCM1480_PCI_BASE                 0x0010061400

 
 

-#define A_BCM1480_PCI_RESET                 0x0010061400
-#define A_BCM1480_PCI_DLL                   0x0010061500
+#define A_BCM1480_PCI_RESET                0x0010061400
+#define A_BCM1480_PCI_DLL                  0x0010061500

 
 

-#define A_BCM1480_PCI_TYPE00_HEADER         0x002E000000
+#define A_BCM1480_PCI_TYPE00_HEADER        0x002E000000

 
 /*  *********************************************************************
     * Ethernet MAC Registers (Section 11) and DMA Registers (Section 10.6)
 
 /*  *********************************************************************
     * Ethernet MAC Registers (Section 11) and DMA Registers (Section 10.6)


@@ -185,19 +185,19 @@
 
 /* No register changes with Rev.C BCM1250, but one additional MAC */
 
 
 /* No register changes with Rev.C BCM1250, but one additional MAC */
 

-#define A_BCM1480_MAC_BASE_2        0x0010066000
+#define A_BCM1480_MAC_BASE_2       0x0010066000

 
 #ifndef A_MAC_BASE_2
 
 #ifndef A_MAC_BASE_2

-#define A_MAC_BASE_2                A_BCM1480_MAC_BASE_2
+#define A_MAC_BASE_2               A_BCM1480_MAC_BASE_2

 #endif
 
 #endif
 

-#define A_BCM1480_MAC_BASE_3        0x0010067000
-#define A_MAC_BASE_3                A_BCM1480_MAC_BASE_3
+#define A_BCM1480_MAC_BASE_3       0x0010067000
+#define A_MAC_BASE_3               A_BCM1480_MAC_BASE_3

 
 

-#define R_BCM1480_MAC_DMA_OODPKTLOST        0x00000038
+#define R_BCM1480_MAC_DMA_OODPKTLOST       0x00000038

 
 #ifndef R_MAC_DMA_OODPKTLOST
 
 #ifndef R_MAC_DMA_OODPKTLOST

-#define R_MAC_DMA_OODPKTLOST        R_BCM1480_MAC_DMA_OODPKTLOST
+#define R_MAC_DMA_OODPKTLOST       R_BCM1480_MAC_DMA_OODPKTLOST

 #endif
 
 
 #endif
 
 


@@ -208,18 +208,18 @@
 /* No significant differences from BCM1250, two DUARTs */
 
 /*  Conventions, per user manual:
 /* No significant differences from BCM1250, two DUARTs */
 
 /*  Conventions, per user manual:

- *     DUART    generic, channels A,B,C,D
- *     DUART0   implementing channels A,B
- *     DUART1   inplementing channels C,D
+ *     DUART   generic, channels A,B,C,D
+ *     DUART0  implementing channels A,B
+ *     DUART1  inplementing channels C,D

  */
 
  */
 

-#define BCM1480_DUART_NUM_PORTS           4
+#define BCM1480_DUART_NUM_PORTS                  4

 
 

-#define A_BCM1480_DUART0                    0x0010060000
-#define A_BCM1480_DUART1                    0x0010060400
-#define A_BCM1480_DUART(chan)               ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1)
+#define A_BCM1480_DUART0                   0x0010060000
+#define A_BCM1480_DUART1                   0x0010060400
+#define A_BCM1480_DUART(chan)              ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1)

 
 

-#define BCM1480_DUART_CHANREG_SPACING       0x100
+#define BCM1480_DUART_CHANREG_SPACING      0x100

 #define A_BCM1480_DUART_CHANREG(chan, reg)                             \
        (A_BCM1480_DUART(chan) +                                        \
         BCM1480_DUART_CHANREG_SPACING * (((chan) & 1) + 1) + (reg))
 #define A_BCM1480_DUART_CHANREG(chan, reg)                             \
        (A_BCM1480_DUART(chan) +                                        \
         BCM1480_DUART_CHANREG_SPACING * (((chan) & 1) + 1) + (reg))


@@ -249,43 +249,43 @@
  * These constants are the absolute addresses.
  */
 
  * These constants are the absolute addresses.
  */
 

-#define A_BCM1480_DUART_MODE_REG_1_C        0x0010060400
-#define A_BCM1480_DUART_MODE_REG_2_C        0x0010060410
-#define A_BCM1480_DUART_STATUS_C            0x0010060420
-#define A_BCM1480_DUART_CLK_SEL_C           0x0010060430
-#define A_BCM1480_DUART_FULL_CTL_C          0x0010060440
-#define A_BCM1480_DUART_CMD_C               0x0010060450
-#define A_BCM1480_DUART_RX_HOLD_C           0x0010060460
-#define A_BCM1480_DUART_TX_HOLD_C           0x0010060470
-#define A_BCM1480_DUART_OPCR_C              0x0010060480
-#define A_BCM1480_DUART_AUX_CTRL_C          0x0010060490
-
-#define A_BCM1480_DUART_MODE_REG_1_D        0x0010060500
-#define A_BCM1480_DUART_MODE_REG_2_D        0x0010060510
-#define A_BCM1480_DUART_STATUS_D            0x0010060520
-#define A_BCM1480_DUART_CLK_SEL_D           0x0010060530
-#define A_BCM1480_DUART_FULL_CTL_D          0x0010060540
-#define A_BCM1480_DUART_CMD_D               0x0010060550
-#define A_BCM1480_DUART_RX_HOLD_D           0x0010060560
-#define A_BCM1480_DUART_TX_HOLD_D           0x0010060570
-#define A_BCM1480_DUART_OPCR_D              0x0010060580
-#define A_BCM1480_DUART_AUX_CTRL_D          0x0010060590
-
-#define A_BCM1480_DUART_INPORT_CHNG_CD      0x0010060600
-#define A_BCM1480_DUART_AUX_CTRL_CD         0x0010060610
-#define A_BCM1480_DUART_ISR_C               0x0010060620
-#define A_BCM1480_DUART_IMR_C               0x0010060630
-#define A_BCM1480_DUART_ISR_D               0x0010060640
-#define A_BCM1480_DUART_IMR_D               0x0010060650
-#define A_BCM1480_DUART_OUT_PORT_CD         0x0010060660
-#define A_BCM1480_DUART_OPCR_CD             0x0010060670
-#define A_BCM1480_DUART_IN_PORT_CD          0x0010060680
-#define A_BCM1480_DUART_ISR_CD              0x0010060690
-#define A_BCM1480_DUART_IMR_CD              0x00100606A0
-#define A_BCM1480_DUART_SET_OPR_CD          0x00100606B0
-#define A_BCM1480_DUART_CLEAR_OPR_CD        0x00100606C0
-#define A_BCM1480_DUART_INPORT_CHNG_C       0x00100606D0
-#define A_BCM1480_DUART_INPORT_CHNG_D       0x00100606E0
+#define A_BCM1480_DUART_MODE_REG_1_C       0x0010060400
+#define A_BCM1480_DUART_MODE_REG_2_C       0x0010060410
+#define A_BCM1480_DUART_STATUS_C           0x0010060420
+#define A_BCM1480_DUART_CLK_SEL_C          0x0010060430
+#define A_BCM1480_DUART_FULL_CTL_C         0x0010060440
+#define A_BCM1480_DUART_CMD_C              0x0010060450
+#define A_BCM1480_DUART_RX_HOLD_C          0x0010060460
+#define A_BCM1480_DUART_TX_HOLD_C          0x0010060470
+#define A_BCM1480_DUART_OPCR_C             0x0010060480
+#define A_BCM1480_DUART_AUX_CTRL_C         0x0010060490
+
+#define A_BCM1480_DUART_MODE_REG_1_D       0x0010060500
+#define A_BCM1480_DUART_MODE_REG_2_D       0x0010060510
+#define A_BCM1480_DUART_STATUS_D           0x0010060520
+#define A_BCM1480_DUART_CLK_SEL_D          0x0010060530
+#define A_BCM1480_DUART_FULL_CTL_D         0x0010060540
+#define A_BCM1480_DUART_CMD_D              0x0010060550
+#define A_BCM1480_DUART_RX_HOLD_D          0x0010060560
+#define A_BCM1480_DUART_TX_HOLD_D          0x0010060570
+#define A_BCM1480_DUART_OPCR_D             0x0010060580
+#define A_BCM1480_DUART_AUX_CTRL_D         0x0010060590
+
+#define A_BCM1480_DUART_INPORT_CHNG_CD     0x0010060600
+#define A_BCM1480_DUART_AUX_CTRL_CD        0x0010060610
+#define A_BCM1480_DUART_ISR_C              0x0010060620
+#define A_BCM1480_DUART_IMR_C              0x0010060630
+#define A_BCM1480_DUART_ISR_D              0x0010060640
+#define A_BCM1480_DUART_IMR_D              0x0010060650
+#define A_BCM1480_DUART_OUT_PORT_CD        0x0010060660
+#define A_BCM1480_DUART_OPCR_CD                    0x0010060670
+#define A_BCM1480_DUART_IN_PORT_CD         0x0010060680
+#define A_BCM1480_DUART_ISR_CD             0x0010060690
+#define A_BCM1480_DUART_IMR_CD             0x00100606A0
+#define A_BCM1480_DUART_SET_OPR_CD         0x00100606B0
+#define A_BCM1480_DUART_CLEAR_OPR_CD       0x00100606C0
+#define A_BCM1480_DUART_INPORT_CHNG_C      0x00100606D0
+#define A_BCM1480_DUART_INPORT_CHNG_D      0x00100606E0

 
 
 /*  *********************************************************************
 
 
 /*  *********************************************************************


@@ -301,8 +301,8 @@
 
 /* One additional GPIO register, placed _before_ the BCM1250's GPIO block base */
 
 
 /* One additional GPIO register, placed _before_ the BCM1250's GPIO block base */
 

-#define A_BCM1480_GPIO_INT_ADD_TYPE         0x0010061A78
-#define R_BCM1480_GPIO_INT_ADD_TYPE         (-8)
+#define A_BCM1480_GPIO_INT_ADD_TYPE        0x0010061A78
+#define R_BCM1480_GPIO_INT_ADD_TYPE        (-8)

 
 #define A_GPIO_INT_ADD_TYPE    A_BCM1480_GPIO_INT_ADD_TYPE
 #define R_GPIO_INT_ADD_TYPE    R_BCM1480_GPIO_INT_ADD_TYPE
 
 #define A_GPIO_INT_ADD_TYPE    A_BCM1480_GPIO_INT_ADD_TYPE
 #define R_GPIO_INT_ADD_TYPE    R_BCM1480_GPIO_INT_ADD_TYPE


@@ -321,30 +321,30 @@
 
 /* Watchdog timers */
 
 
 /* Watchdog timers */
 

-#define A_BCM1480_SCD_WDOG_2                0x0010022050
-#define A_BCM1480_SCD_WDOG_3                0x0010022150
+#define A_BCM1480_SCD_WDOG_2               0x0010022050
+#define A_BCM1480_SCD_WDOG_3               0x0010022150

 
 

-#define BCM1480_SCD_NUM_WDOGS               4
+#define BCM1480_SCD_NUM_WDOGS              4

 
 

-#define A_BCM1480_SCD_WDOG_BASE(w)       (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100)
+#define A_BCM1480_SCD_WDOG_BASE(w)      (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100)

 #define A_BCM1480_SCD_WDOG_REGISTER(w, r) (A_BCM1480_SCD_WDOG_BASE(w) + (r))
 
 #define A_BCM1480_SCD_WDOG_REGISTER(w, r) (A_BCM1480_SCD_WDOG_BASE(w) + (r))
 

-#define A_BCM1480_SCD_WDOG_INIT_2       0x0010022050
-#define A_BCM1480_SCD_WDOG_CNT_2        0x0010022058
-#define A_BCM1480_SCD_WDOG_CFG_2        0x0010022060
+#define A_BCM1480_SCD_WDOG_INIT_2      0x0010022050
+#define A_BCM1480_SCD_WDOG_CNT_2       0x0010022058
+#define A_BCM1480_SCD_WDOG_CFG_2       0x0010022060

 
 

-#define A_BCM1480_SCD_WDOG_INIT_3       0x0010022150
-#define A_BCM1480_SCD_WDOG_CNT_3        0x0010022158
-#define A_BCM1480_SCD_WDOG_CFG_3        0x0010022160
+#define A_BCM1480_SCD_WDOG_INIT_3      0x0010022150
+#define A_BCM1480_SCD_WDOG_CNT_3       0x0010022158
+#define A_BCM1480_SCD_WDOG_CFG_3       0x0010022160

 
 /* BCM1480 has two additional compare registers */
 
 #define A_BCM1480_SCD_ZBBUS_CYCLE_COUNT                A_SCD_ZBBUS_CYCLE_COUNT
 
 /* BCM1480 has two additional compare registers */
 
 #define A_BCM1480_SCD_ZBBUS_CYCLE_COUNT                A_SCD_ZBBUS_CYCLE_COUNT

-#define A_BCM1480_SCD_ZBBUS_CYCLE_CP_BASE       0x0010020C00
-#define A_BCM1480_SCD_ZBBUS_CYCLE_CP0           A_SCD_ZBBUS_CYCLE_CP0
-#define A_BCM1480_SCD_ZBBUS_CYCLE_CP1           A_SCD_ZBBUS_CYCLE_CP1
-#define A_BCM1480_SCD_ZBBUS_CYCLE_CP2           0x0010020C10
-#define A_BCM1480_SCD_ZBBUS_CYCLE_CP3           0x0010020C18
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP_BASE      0x0010020C00
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP0          A_SCD_ZBBUS_CYCLE_CP0
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP1          A_SCD_ZBBUS_CYCLE_CP1
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP2          0x0010020C10
+#define A_BCM1480_SCD_ZBBUS_CYCLE_CP3          0x0010020C18

 
 /*  *********************************************************************
     * System Control Registers (Section 4.2)
 
 /*  *********************************************************************
     * System Control Registers (Section 4.2)


@@ -352,7 +352,7 @@
 
 /* Scratch register in different place */
 
 
 /* Scratch register in different place */
 

-#define A_BCM1480_SCD_SCRATCH          0x100200A0
+#define A_BCM1480_SCD_SCRATCH          0x100200A0

 
 /*  *********************************************************************
     * System Address Trap Registers (Section 4.9)
 
 /*  *********************************************************************
     * System Address Trap Registers (Section 4.9)


@@ -364,68 +364,68 @@
     * System Interrupt Mapper Registers (Sections 4.3-4.5)
     ********************************************************************* */
 
     * System Interrupt Mapper Registers (Sections 4.3-4.5)
     ********************************************************************* */
 

-#define A_BCM1480_IMR_CPU0_BASE             0x0010020000
-#define A_BCM1480_IMR_CPU1_BASE             0x0010022000
-#define A_BCM1480_IMR_CPU2_BASE             0x0010024000
-#define A_BCM1480_IMR_CPU3_BASE             0x0010026000
-#define BCM1480_IMR_REGISTER_SPACING        0x2000
+#define A_BCM1480_IMR_CPU0_BASE                    0x0010020000
+#define A_BCM1480_IMR_CPU1_BASE                    0x0010022000
+#define A_BCM1480_IMR_CPU2_BASE                    0x0010024000
+#define A_BCM1480_IMR_CPU3_BASE                    0x0010026000
+#define BCM1480_IMR_REGISTER_SPACING       0x2000

 #define BCM1480_IMR_REGISTER_SPACING_SHIFT  13
 
 #define BCM1480_IMR_REGISTER_SPACING_SHIFT  13
 

-#define A_BCM1480_IMR_MAPPER(cpu)       (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING)
+#define A_BCM1480_IMR_MAPPER(cpu)      (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING)

 #define A_BCM1480_IMR_REGISTER(cpu, reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg))
 
 /* Most IMR registers are 128 bits, implemented as non-contiguous
    64-bit registers high (_H) and low (_L) */
 #define A_BCM1480_IMR_REGISTER(cpu, reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg))
 
 /* Most IMR registers are 128 bits, implemented as non-contiguous
    64-bit registers high (_H) and low (_L) */

-#define BCM1480_IMR_HL_SPACING                  0x1000
+#define BCM1480_IMR_HL_SPACING                 0x1000

 
 

-#define R_BCM1480_IMR_INTERRUPT_DIAG_H          0x0010
-#define R_BCM1480_IMR_LDT_INTERRUPT_H           0x0018
-#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_H       0x0020
-#define R_BCM1480_IMR_INTERRUPT_MASK_H          0x0028
-#define R_BCM1480_IMR_INTERRUPT_TRACE_H         0x0038
+#define R_BCM1480_IMR_INTERRUPT_DIAG_H         0x0010
+#define R_BCM1480_IMR_LDT_INTERRUPT_H          0x0018
+#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_H      0x0020
+#define R_BCM1480_IMR_INTERRUPT_MASK_H         0x0028
+#define R_BCM1480_IMR_INTERRUPT_TRACE_H                0x0038

 #define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_H 0x0040
 #define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_H 0x0040

-#define R_BCM1480_IMR_LDT_INTERRUPT_SET         0x0048
-#define R_BCM1480_IMR_MAILBOX_0_CPU             0x00C0
-#define R_BCM1480_IMR_MAILBOX_0_SET_CPU         0x00C8
-#define R_BCM1480_IMR_MAILBOX_0_CLR_CPU         0x00D0
-#define R_BCM1480_IMR_MAILBOX_1_CPU             0x00E0
-#define R_BCM1480_IMR_MAILBOX_1_SET_CPU         0x00E8
-#define R_BCM1480_IMR_MAILBOX_1_CLR_CPU         0x00F0
-#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H   0x0100
-#define BCM1480_IMR_INTERRUPT_STATUS_COUNT      8
-#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_H      0x0200
-#define BCM1480_IMR_INTERRUPT_MAP_COUNT         64
-
-#define R_BCM1480_IMR_INTERRUPT_DIAG_L          0x1010
-#define R_BCM1480_IMR_LDT_INTERRUPT_L           0x1018
-#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_L       0x1020
-#define R_BCM1480_IMR_INTERRUPT_MASK_L          0x1028
-#define R_BCM1480_IMR_INTERRUPT_TRACE_L         0x1038
+#define R_BCM1480_IMR_LDT_INTERRUPT_SET                0x0048
+#define R_BCM1480_IMR_MAILBOX_0_CPU            0x00C0
+#define R_BCM1480_IMR_MAILBOX_0_SET_CPU                0x00C8
+#define R_BCM1480_IMR_MAILBOX_0_CLR_CPU                0x00D0
+#define R_BCM1480_IMR_MAILBOX_1_CPU            0x00E0
+#define R_BCM1480_IMR_MAILBOX_1_SET_CPU                0x00E8
+#define R_BCM1480_IMR_MAILBOX_1_CLR_CPU                0x00F0
+#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H  0x0100
+#define BCM1480_IMR_INTERRUPT_STATUS_COUNT     8
+#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_H     0x0200
+#define BCM1480_IMR_INTERRUPT_MAP_COUNT                64
+
+#define R_BCM1480_IMR_INTERRUPT_DIAG_L         0x1010
+#define R_BCM1480_IMR_LDT_INTERRUPT_L          0x1018
+#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_L      0x1020
+#define R_BCM1480_IMR_INTERRUPT_MASK_L         0x1028
+#define R_BCM1480_IMR_INTERRUPT_TRACE_L                0x1038

 #define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_L 0x1040
 #define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_L 0x1040

-#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L   0x1100
-#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_L      0x1200
+#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L  0x1100
+#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_L     0x1200

 
 

-#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE   0x0010028000
-#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU1_BASE   0x0010028100
-#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU2_BASE   0x0010028200
-#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU3_BASE   0x0010028300
-#define BCM1480_IMR_ALIAS_MAILBOX_SPACING       0100
+#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE  0x0010028000
+#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU1_BASE  0x0010028100
+#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU2_BASE  0x0010028200
+#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU3_BASE  0x0010028300
+#define BCM1480_IMR_ALIAS_MAILBOX_SPACING      0100

 
 #define A_BCM1480_IMR_ALIAS_MAILBOX(cpu)     (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \
 
 #define A_BCM1480_IMR_ALIAS_MAILBOX(cpu)     (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \

-                                        (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING)
+                                       (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING)

 #define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu, reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg))
 
 #define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu, reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg))
 

-#define R_BCM1480_IMR_ALIAS_MAILBOX_0           0x0000         /* 0x0x0 */
-#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET       0x0008         /* 0x0x8 */
+#define R_BCM1480_IMR_ALIAS_MAILBOX_0          0x0000          /* 0x0x0 */
+#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET      0x0008          /* 0x0x8 */

 
 /*
  * these macros work together to build the address of a mailbox
  * register, e.g., A_BCM1480_MAILBOX_REGISTER(0,R_BCM1480_IMR_MAILBOX_SET,2)
  * for mbox_0_set_cpu2 returns 0x00100240C8
  */
 
 /*
  * these macros work together to build the address of a mailbox
  * register, e.g., A_BCM1480_MAILBOX_REGISTER(0,R_BCM1480_IMR_MAILBOX_SET,2)
  * for mbox_0_set_cpu2 returns 0x00100240C8
  */

-#define R_BCM1480_IMR_MAILBOX_CPU         0x00
-#define R_BCM1480_IMR_MAILBOX_SET         0x08
-#define R_BCM1480_IMR_MAILBOX_CLR         0x10
+#define R_BCM1480_IMR_MAILBOX_CPU        0x00
+#define R_BCM1480_IMR_MAILBOX_SET        0x08
+#define R_BCM1480_IMR_MAILBOX_CLR        0x10

 #define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20
 #define A_BCM1480_MAILBOX_REGISTER(num, reg, cpu) \
     (A_BCM1480_IMR_CPU0_BASE + \
 #define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20
 #define A_BCM1480_MAILBOX_REGISTER(num, reg, cpu) \
     (A_BCM1480_IMR_CPU0_BASE + \


@@ -440,22 +440,22 @@
 /* BCM1480 has four more performance counter registers, and two control
    registers. */
 
 /* BCM1480 has four more performance counter registers, and two control
    registers. */
 

-#define A_BCM1480_SCD_PERF_CNT_BASE         0x00100204C0
+#define A_BCM1480_SCD_PERF_CNT_BASE        0x00100204C0

 
 

-#define A_BCM1480_SCD_PERF_CNT_CFG0         0x00100204C0
-#define A_BCM1480_SCD_PERF_CNT_CFG_0        A_BCM1480_SCD_PERF_CNT_CFG0
-#define A_BCM1480_SCD_PERF_CNT_CFG1         0x00100204C8
-#define A_BCM1480_SCD_PERF_CNT_CFG_1        A_BCM1480_SCD_PERF_CNT_CFG1
+#define A_BCM1480_SCD_PERF_CNT_CFG0        0x00100204C0
+#define A_BCM1480_SCD_PERF_CNT_CFG_0       A_BCM1480_SCD_PERF_CNT_CFG0
+#define A_BCM1480_SCD_PERF_CNT_CFG1        0x00100204C8
+#define A_BCM1480_SCD_PERF_CNT_CFG_1       A_BCM1480_SCD_PERF_CNT_CFG1

 
 

-#define A_BCM1480_SCD_PERF_CNT_0            A_SCD_PERF_CNT_0
-#define A_BCM1480_SCD_PERF_CNT_1            A_SCD_PERF_CNT_1
-#define A_BCM1480_SCD_PERF_CNT_2            A_SCD_PERF_CNT_2
-#define A_BCM1480_SCD_PERF_CNT_3            A_SCD_PERF_CNT_3
+#define A_BCM1480_SCD_PERF_CNT_0           A_SCD_PERF_CNT_0
+#define A_BCM1480_SCD_PERF_CNT_1           A_SCD_PERF_CNT_1
+#define A_BCM1480_SCD_PERF_CNT_2           A_SCD_PERF_CNT_2
+#define A_BCM1480_SCD_PERF_CNT_3           A_SCD_PERF_CNT_3

 
 

-#define A_BCM1480_SCD_PERF_CNT_4            0x00100204F0
-#define A_BCM1480_SCD_PERF_CNT_5            0x00100204F8
-#define A_BCM1480_SCD_PERF_CNT_6            0x0010020500
-#define A_BCM1480_SCD_PERF_CNT_7            0x0010020508
+#define A_BCM1480_SCD_PERF_CNT_4           0x00100204F0
+#define A_BCM1480_SCD_PERF_CNT_5           0x00100204F8
+#define A_BCM1480_SCD_PERF_CNT_6           0x0010020500
+#define A_BCM1480_SCD_PERF_CNT_7           0x0010020508

 
 #define BCM1480_SCD_NUM_PERF_CNT 8
 #define BCM1480_SCD_PERF_CNT_SPACING 8
 
 #define BCM1480_SCD_NUM_PERF_CNT 8
 #define BCM1480_SCD_PERF_CNT_SPACING 8


@@ -468,7 +468,7 @@
 
 /* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */
 
 
 /* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */
 

-#define A_BCM1480_BUS_ERR_STATUS_DEBUG      0x00100208D8
+#define A_BCM1480_BUS_ERR_STATUS_DEBUG     0x00100208D8

 
 /*  *********************************************************************
     * System Debug Controller Registers (Section 19)
 
 /*  *********************************************************************
     * System Debug Controller Registers (Section 19)


@@ -497,46 +497,46 @@
 #define BCM1480_HT_PORT_SPACING                   0x800
 #define A_BCM1480_HT_PORT_HEADER(x)       (A_BCM1480_HT_PORT0_HEADER + ((x)*BCM1480_HT_PORT_SPACING))
 
 #define BCM1480_HT_PORT_SPACING                   0x800
 #define A_BCM1480_HT_PORT_HEADER(x)       (A_BCM1480_HT_PORT0_HEADER + ((x)*BCM1480_HT_PORT_SPACING))
 

-#define A_BCM1480_HT_PORT0_HEADER          0x00FE000000
-#define A_BCM1480_HT_PORT1_HEADER          0x00FE000800
-#define A_BCM1480_HT_PORT2_HEADER          0x00FE001000
-#define A_BCM1480_HT_TYPE00_HEADER         0x00FE002000
+#define A_BCM1480_HT_PORT0_HEADER         0x00FE000000
+#define A_BCM1480_HT_PORT1_HEADER         0x00FE000800
+#define A_BCM1480_HT_PORT2_HEADER         0x00FE001000
+#define A_BCM1480_HT_TYPE00_HEADER        0x00FE002000

 
 
 /*  *********************************************************************
     * Node Controller Registers (Section 9)
     ********************************************************************* */
 
 
 
 /*  *********************************************************************
     * Node Controller Registers (Section 9)
     ********************************************************************* */
 

-#define A_BCM1480_NC_BASE                   0x00DFBD0000
+#define A_BCM1480_NC_BASE                  0x00DFBD0000

 
 

-#define A_BCM1480_NC_RLD_FIELD              0x00DFBD0000
-#define A_BCM1480_NC_RLD_TRIGGER            0x00DFBD0020
-#define A_BCM1480_NC_RLD_BAD_ERROR          0x00DFBD0040
-#define A_BCM1480_NC_RLD_COR_ERROR          0x00DFBD0060
-#define A_BCM1480_NC_RLD_ECC_STATUS         0x00DFBD0080
-#define A_BCM1480_NC_RLD_WAY_ENABLE         0x00DFBD00A0
-#define A_BCM1480_NC_RLD_RANDOM_LFSR        0x00DFBD00C0
+#define A_BCM1480_NC_RLD_FIELD             0x00DFBD0000
+#define A_BCM1480_NC_RLD_TRIGGER           0x00DFBD0020
+#define A_BCM1480_NC_RLD_BAD_ERROR         0x00DFBD0040
+#define A_BCM1480_NC_RLD_COR_ERROR         0x00DFBD0060
+#define A_BCM1480_NC_RLD_ECC_STATUS        0x00DFBD0080
+#define A_BCM1480_NC_RLD_WAY_ENABLE        0x00DFBD00A0
+#define A_BCM1480_NC_RLD_RANDOM_LFSR       0x00DFBD00C0

 
 

-#define A_BCM1480_NC_INTERRUPT_STATUS       0x00DFBD00E0
-#define A_BCM1480_NC_INTERRUPT_ENABLE       0x00DFBD0100
-#define A_BCM1480_NC_TIMEOUT_COUNTER        0x00DFBD0120
+#define A_BCM1480_NC_INTERRUPT_STATUS      0x00DFBD00E0
+#define A_BCM1480_NC_INTERRUPT_ENABLE      0x00DFBD0100
+#define A_BCM1480_NC_TIMEOUT_COUNTER       0x00DFBD0120

 #define A_BCM1480_NC_TIMEOUT_COUNTER_SEL    0x00DFBD0140
 
 #define A_BCM1480_NC_TIMEOUT_COUNTER_SEL    0x00DFBD0140
 

-#define A_BCM1480_NC_CREDIT_STATUS_REG0     0x00DFBD0200
-#define A_BCM1480_NC_CREDIT_STATUS_REG1     0x00DFBD0220
-#define A_BCM1480_NC_CREDIT_STATUS_REG2     0x00DFBD0240
-#define A_BCM1480_NC_CREDIT_STATUS_REG3     0x00DFBD0260
-#define A_BCM1480_NC_CREDIT_STATUS_REG4     0x00DFBD0280
-#define A_BCM1480_NC_CREDIT_STATUS_REG5     0x00DFBD02A0
-#define A_BCM1480_NC_CREDIT_STATUS_REG6     0x00DFBD02C0
-#define A_BCM1480_NC_CREDIT_STATUS_REG7     0x00DFBD02E0
-#define A_BCM1480_NC_CREDIT_STATUS_REG8     0x00DFBD0300
-#define A_BCM1480_NC_CREDIT_STATUS_REG9     0x00DFBD0320
+#define A_BCM1480_NC_CREDIT_STATUS_REG0            0x00DFBD0200
+#define A_BCM1480_NC_CREDIT_STATUS_REG1            0x00DFBD0220
+#define A_BCM1480_NC_CREDIT_STATUS_REG2            0x00DFBD0240
+#define A_BCM1480_NC_CREDIT_STATUS_REG3            0x00DFBD0260
+#define A_BCM1480_NC_CREDIT_STATUS_REG4            0x00DFBD0280
+#define A_BCM1480_NC_CREDIT_STATUS_REG5            0x00DFBD02A0
+#define A_BCM1480_NC_CREDIT_STATUS_REG6            0x00DFBD02C0
+#define A_BCM1480_NC_CREDIT_STATUS_REG7            0x00DFBD02E0
+#define A_BCM1480_NC_CREDIT_STATUS_REG8            0x00DFBD0300
+#define A_BCM1480_NC_CREDIT_STATUS_REG9            0x00DFBD0320

 #define A_BCM1480_NC_CREDIT_STATUS_REG10    0x00DFBE0000
 #define A_BCM1480_NC_CREDIT_STATUS_REG11    0x00DFBE0020
 #define A_BCM1480_NC_CREDIT_STATUS_REG12    0x00DFBE0040
 
 #define A_BCM1480_NC_CREDIT_STATUS_REG10    0x00DFBE0000
 #define A_BCM1480_NC_CREDIT_STATUS_REG11    0x00DFBE0020
 #define A_BCM1480_NC_CREDIT_STATUS_REG12    0x00DFBE0040
 

-#define A_BCM1480_NC_SR_TIMEOUT_COUNTER     0x00DFBE0060
+#define A_BCM1480_NC_SR_TIMEOUT_COUNTER            0x00DFBE0060

 #define A_BCM1480_NC_SR_TIMEOUT_COUNTER_SEL 0x00DFBE0080
 
 
 #define A_BCM1480_NC_SR_TIMEOUT_COUNTER_SEL 0x00DFBE0080
 
 


@@ -544,43 +544,43 @@
     * H&R Block Configuration Registers (Section 12.4)
     ********************************************************************* */
 
     * H&R Block Configuration Registers (Section 12.4)
     ********************************************************************* */
 

-#define A_BCM1480_HR_BASE_0                 0x00DF820000
-#define A_BCM1480_HR_BASE_1                 0x00DF8A0000
-#define A_BCM1480_HR_BASE_2                 0x00DF920000
-#define BCM1480_HR_REGISTER_SPACING         0x80000
+#define A_BCM1480_HR_BASE_0                0x00DF820000
+#define A_BCM1480_HR_BASE_1                0x00DF8A0000
+#define A_BCM1480_HR_BASE_2                0x00DF920000
+#define BCM1480_HR_REGISTER_SPACING        0x80000

 
 

-#define A_BCM1480_HR_BASE(idx)              (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING))
-#define A_BCM1480_HR_REGISTER(idx, reg)      (A_BCM1480_HR_BASE(idx) + (reg))
+#define A_BCM1480_HR_BASE(idx)             (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING))
+#define A_BCM1480_HR_REGISTER(idx, reg)             (A_BCM1480_HR_BASE(idx) + (reg))

 
 

-#define R_BCM1480_HR_CFG                    0x0000000000
+#define R_BCM1480_HR_CFG                   0x0000000000

 
 #define R_BCM1480_HR_MAPPING               0x0000010010
 
 
 #define R_BCM1480_HR_MAPPING               0x0000010010
 

-#define BCM1480_HR_RULE_SPACING             0x0000000010
-#define BCM1480_HR_NUM_RULES                16
-#define BCM1480_HR_OP_OFFSET                0x0000000100
-#define BCM1480_HR_TYPE_OFFSET              0x0000000108
-#define R_BCM1480_HR_RULE_OP(idx)           (BCM1480_HR_OP_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))
-#define R_BCM1480_HR_RULE_TYPE(idx)         (BCM1480_HR_TYPE_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))
+#define BCM1480_HR_RULE_SPACING                    0x0000000010
+#define BCM1480_HR_NUM_RULES               16
+#define BCM1480_HR_OP_OFFSET               0x0000000100
+#define BCM1480_HR_TYPE_OFFSET             0x0000000108
+#define R_BCM1480_HR_RULE_OP(idx)          (BCM1480_HR_OP_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))
+#define R_BCM1480_HR_RULE_TYPE(idx)        (BCM1480_HR_TYPE_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))

 
 

-#define BCM1480_HR_LEAF_SPACING             0x0000000010
-#define BCM1480_HR_NUM_LEAVES               10
-#define BCM1480_HR_LEAF_OFFSET              0x0000000300
-#define R_BCM1480_HR_HA_LEAF0(idx)          (BCM1480_HR_LEAF_OFFSET + ((idx)*BCM1480_HR_LEAF_SPACING))
+#define BCM1480_HR_LEAF_SPACING                    0x0000000010
+#define BCM1480_HR_NUM_LEAVES              10
+#define BCM1480_HR_LEAF_OFFSET             0x0000000300
+#define R_BCM1480_HR_HA_LEAF0(idx)         (BCM1480_HR_LEAF_OFFSET + ((idx)*BCM1480_HR_LEAF_SPACING))

 
 

-#define R_BCM1480_HR_EX_LEAF0               0x00000003A0
+#define R_BCM1480_HR_EX_LEAF0              0x00000003A0

 
 

-#define BCM1480_HR_PATH_SPACING             0x0000000010
-#define BCM1480_HR_NUM_PATHS                16
-#define BCM1480_HR_PATH_OFFSET              0x0000000600
-#define R_BCM1480_HR_PATH(idx)              (BCM1480_HR_PATH_OFFSET + ((idx)*BCM1480_HR_PATH_SPACING))
+#define BCM1480_HR_PATH_SPACING                    0x0000000010
+#define BCM1480_HR_NUM_PATHS               16
+#define BCM1480_HR_PATH_OFFSET             0x0000000600
+#define R_BCM1480_HR_PATH(idx)             (BCM1480_HR_PATH_OFFSET + ((idx)*BCM1480_HR_PATH_SPACING))

 
 

-#define R_BCM1480_HR_PATH_DEFAULT           0x0000000700
+#define R_BCM1480_HR_PATH_DEFAULT          0x0000000700

 
 

-#define BCM1480_HR_ROUTE_SPACING            8
-#define BCM1480_HR_NUM_ROUTES               512
-#define BCM1480_HR_ROUTE_OFFSET             0x0000001000
-#define R_BCM1480_HR_RT_WORD(idx)           (BCM1480_HR_ROUTE_OFFSET + ((idx)*BCM1480_HR_ROUTE_SPACING))
+#define BCM1480_HR_ROUTE_SPACING           8
+#define BCM1480_HR_NUM_ROUTES              512
+#define BCM1480_HR_ROUTE_OFFSET                    0x0000001000
+#define R_BCM1480_HR_RT_WORD(idx)          (BCM1480_HR_ROUTE_OFFSET + ((idx)*BCM1480_HR_ROUTE_SPACING))

 
 
 /* checked to here - ehs */
 
 
 /* checked to here - ehs */


@@ -588,55 +588,55 @@
     * Packet Manager DMA Registers (Section 12.5)
     ********************************************************************* */
 
     * Packet Manager DMA Registers (Section 12.5)
     ********************************************************************* */
 

-#define A_BCM1480_PM_BASE                   0x0010056000
+#define A_BCM1480_PM_BASE                  0x0010056000

 
 

-#define A_BCM1480_PMI_LCL_0                 0x0010058000
-#define A_BCM1480_PMO_LCL_0                 0x001005C000
-#define A_BCM1480_PMI_OFFSET_0              (A_BCM1480_PMI_LCL_0 - A_BCM1480_PM_BASE)
-#define A_BCM1480_PMO_OFFSET_0              (A_BCM1480_PMO_LCL_0 - A_BCM1480_PM_BASE)
+#define A_BCM1480_PMI_LCL_0                0x0010058000
+#define A_BCM1480_PMO_LCL_0                0x001005C000
+#define A_BCM1480_PMI_OFFSET_0             (A_BCM1480_PMI_LCL_0 - A_BCM1480_PM_BASE)
+#define A_BCM1480_PMO_OFFSET_0             (A_BCM1480_PMO_LCL_0 - A_BCM1480_PM_BASE)

 
 

-#define BCM1480_PM_LCL_REGISTER_SPACING     0x100
-#define BCM1480_PM_NUM_CHANNELS             32
+#define BCM1480_PM_LCL_REGISTER_SPACING            0x100
+#define BCM1480_PM_NUM_CHANNELS                    32

 
 

-#define A_BCM1480_PMI_LCL_BASE(idx)             (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
-#define A_BCM1480_PMI_LCL_REGISTER(idx, reg)     (A_BCM1480_PMI_LCL_BASE(idx) + (reg))
-#define A_BCM1480_PMO_LCL_BASE(idx)             (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
-#define A_BCM1480_PMO_LCL_REGISTER(idx, reg)     (A_BCM1480_PMO_LCL_BASE(idx) + (reg))
+#define A_BCM1480_PMI_LCL_BASE(idx)            (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
+#define A_BCM1480_PMI_LCL_REGISTER(idx, reg)    (A_BCM1480_PMI_LCL_BASE(idx) + (reg))
+#define A_BCM1480_PMO_LCL_BASE(idx)            (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
+#define A_BCM1480_PMO_LCL_REGISTER(idx, reg)    (A_BCM1480_PMO_LCL_BASE(idx) + (reg))

 
 

-#define BCM1480_PM_INT_PACKING              8
-#define BCM1480_PM_INT_FUNCTION_SPACING     0x40
-#define BCM1480_PM_INT_NUM_FUNCTIONS        3
+#define BCM1480_PM_INT_PACKING             8
+#define BCM1480_PM_INT_FUNCTION_SPACING            0x40
+#define BCM1480_PM_INT_NUM_FUNCTIONS       3

 
 /*
  * DMA channel registers relative to A_BCM1480_PMI_LCL_BASE(n) and A_BCM1480_PMO_LCL_BASE(n)
  */
 
 
 /*
  * DMA channel registers relative to A_BCM1480_PMI_LCL_BASE(n) and A_BCM1480_PMO_LCL_BASE(n)
  */
 

-#define R_BCM1480_PM_BASE_SIZE              0x0000000000
-#define R_BCM1480_PM_CNT                    0x0000000008
-#define R_BCM1480_PM_PFCNT                  0x0000000010
-#define R_BCM1480_PM_LAST                   0x0000000018
-#define R_BCM1480_PM_PFINDX                 0x0000000020
-#define R_BCM1480_PM_INT_WMK                0x0000000028
-#define R_BCM1480_PM_CONFIG0                0x0000000030
-#define R_BCM1480_PM_LOCALDEBUG             0x0000000078
-#define R_BCM1480_PM_CACHEABILITY           0x0000000080   /* PMI only */
-#define R_BCM1480_PM_INT_CNFG               0x0000000088
-#define R_BCM1480_PM_DESC_MERGE_TIMER       0x0000000090
-#define R_BCM1480_PM_LOCALDEBUG_PIB         0x00000000F8   /* PMI only */
-#define R_BCM1480_PM_LOCALDEBUG_POB         0x00000000F8   /* PMO only */
+#define R_BCM1480_PM_BASE_SIZE             0x0000000000
+#define R_BCM1480_PM_CNT                   0x0000000008
+#define R_BCM1480_PM_PFCNT                 0x0000000010
+#define R_BCM1480_PM_LAST                  0x0000000018
+#define R_BCM1480_PM_PFINDX                0x0000000020
+#define R_BCM1480_PM_INT_WMK               0x0000000028
+#define R_BCM1480_PM_CONFIG0               0x0000000030
+#define R_BCM1480_PM_LOCALDEBUG                    0x0000000078
+#define R_BCM1480_PM_CACHEABILITY          0x0000000080   /* PMI only */
+#define R_BCM1480_PM_INT_CNFG              0x0000000088
+#define R_BCM1480_PM_DESC_MERGE_TIMER      0x0000000090
+#define R_BCM1480_PM_LOCALDEBUG_PIB        0x00000000F8   /* PMI only */
+#define R_BCM1480_PM_LOCALDEBUG_POB        0x00000000F8   /* PMO only */

 
 /*
  * Global Registers (Not Channelized)
  */
 
 
 /*
  * Global Registers (Not Channelized)
  */
 

-#define A_BCM1480_PMI_GLB_0                 0x0010056000
-#define A_BCM1480_PMO_GLB_0                 0x0010057000
+#define A_BCM1480_PMI_GLB_0                0x0010056000
+#define A_BCM1480_PMO_GLB_0                0x0010057000

 
 /*
  * PM to TX Mapping Register relative to A_BCM1480_PMI_GLB_0 and A_BCM1480_PMO_GLB_0
  */
 
 
 /*
  * PM to TX Mapping Register relative to A_BCM1480_PMI_GLB_0 and A_BCM1480_PMO_GLB_0
  */
 

-#define R_BCM1480_PM_PMO_MAPPING            0x00000008C8   /* PMO only */
+#define R_BCM1480_PM_PMO_MAPPING           0x00000008C8   /* PMO only */

 
 #define A_BCM1480_PM_PMO_MAPPING       (A_BCM1480_PMO_GLB_0 + R_BCM1480_PM_PMO_MAPPING)
 
 
 #define A_BCM1480_PM_PMO_MAPPING       (A_BCM1480_PMO_GLB_0 + R_BCM1480_PM_PMO_MAPPING)
 


@@ -645,32 +645,32 @@
  */
 
 
  */
 
 

-#define A_BCM1480_PMI_INT_0                 0x0010056800
-#define A_BCM1480_PMI_INT(q)                (A_BCM1480_PMI_INT_0 + ((q>>8)<<8))
-#define A_BCM1480_PMI_INT_OFFSET_0          (A_BCM1480_PMI_INT_0 - A_BCM1480_PM_BASE)
-#define A_BCM1480_PMO_INT_0                 0x0010057800
-#define A_BCM1480_PMO_INT(q)                (A_BCM1480_PMO_INT_0 + ((q>>8)<<8))
-#define A_BCM1480_PMO_INT_OFFSET_0          (A_BCM1480_PMO_INT_0 - A_BCM1480_PM_BASE)
+#define A_BCM1480_PMI_INT_0                0x0010056800
+#define A_BCM1480_PMI_INT(q)               (A_BCM1480_PMI_INT_0 + ((q>>8)<<8))
+#define A_BCM1480_PMI_INT_OFFSET_0         (A_BCM1480_PMI_INT_0 - A_BCM1480_PM_BASE)
+#define A_BCM1480_PMO_INT_0                0x0010057800
+#define A_BCM1480_PMO_INT(q)               (A_BCM1480_PMO_INT_0 + ((q>>8)<<8))
+#define A_BCM1480_PMO_INT_OFFSET_0         (A_BCM1480_PMO_INT_0 - A_BCM1480_PM_BASE)

 
 /*
  * Interrupt registers relative to A_BCM1480_PMI_INT_0 and A_BCM1480_PMO_INT_0
  */
 
 
 /*
  * Interrupt registers relative to A_BCM1480_PMI_INT_0 and A_BCM1480_PMO_INT_0
  */
 

-#define R_BCM1480_PM_INT_ST                 0x0000000000
-#define R_BCM1480_PM_INT_MSK                0x0000000040
-#define R_BCM1480_PM_INT_CLR                0x0000000080
-#define R_BCM1480_PM_MRGD_INT               0x00000000C0
+#define R_BCM1480_PM_INT_ST                0x0000000000
+#define R_BCM1480_PM_INT_MSK               0x0000000040
+#define R_BCM1480_PM_INT_CLR               0x0000000080
+#define R_BCM1480_PM_MRGD_INT              0x00000000C0

 
 /*
  * Debug registers (global)
  */
 
 #define A_BCM1480_PM_GLOBALDEBUGMODE_PMI    0x0010056000
 
 /*
  * Debug registers (global)
  */
 
 #define A_BCM1480_PM_GLOBALDEBUGMODE_PMI    0x0010056000

-#define A_BCM1480_PM_GLOBALDEBUG_PID        0x00100567F8
-#define A_BCM1480_PM_GLOBALDEBUG_PIB        0x0010056FF8
+#define A_BCM1480_PM_GLOBALDEBUG_PID       0x00100567F8
+#define A_BCM1480_PM_GLOBALDEBUG_PIB       0x0010056FF8

 #define A_BCM1480_PM_GLOBALDEBUGMODE_PMO    0x0010057000
 #define A_BCM1480_PM_GLOBALDEBUGMODE_PMO    0x0010057000

-#define A_BCM1480_PM_GLOBALDEBUG_POD        0x00100577F8
-#define A_BCM1480_PM_GLOBALDEBUG_POB        0x0010057FF8
+#define A_BCM1480_PM_GLOBALDEBUG_POD       0x00100577F8
+#define A_BCM1480_PM_GLOBALDEBUG_POB       0x0010057FF8

 
 /*  *********************************************************************
     *  Switch performance counters
 
 /*  *********************************************************************
     *  Switch performance counters


@@ -715,16 +715,16 @@
     *  High-Speed Port Registers (Section 13)
     ********************************************************************* */
 
     *  High-Speed Port Registers (Section 13)
     ********************************************************************* */
 

-#define A_BCM1480_HSP_BASE_0                0x00DF810000
-#define A_BCM1480_HSP_BASE_1                0x00DF890000
-#define A_BCM1480_HSP_BASE_2                0x00DF910000
-#define BCM1480_HSP_REGISTER_SPACING        0x80000
+#define A_BCM1480_HSP_BASE_0               0x00DF810000
+#define A_BCM1480_HSP_BASE_1               0x00DF890000
+#define A_BCM1480_HSP_BASE_2               0x00DF910000
+#define BCM1480_HSP_REGISTER_SPACING       0x80000

 
 

-#define A_BCM1480_HSP_BASE(idx)             (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING))
+#define A_BCM1480_HSP_BASE(idx)                    (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING))

 #define A_BCM1480_HSP_REGISTER(idx, reg)     (A_BCM1480_HSP_BASE(idx) + (reg))
 
 #define A_BCM1480_HSP_REGISTER(idx, reg)     (A_BCM1480_HSP_BASE(idx) + (reg))
 

-#define R_BCM1480_HSP_RX_SPI4_CFG_0           0x0000000000
-#define R_BCM1480_HSP_RX_SPI4_CFG_1           0x0000000008
+#define R_BCM1480_HSP_RX_SPI4_CFG_0          0x0000000000
+#define R_BCM1480_HSP_RX_SPI4_CFG_1          0x0000000008

 #define R_BCM1480_HSP_RX_SPI4_DESKEW_OVERRIDE 0x0000000010
 #define R_BCM1480_HSP_RX_SPI4_DESKEW_DATAPATH 0x0000000018
 #define R_BCM1480_HSP_RX_SPI4_PORT_INT_EN     0x0000000020
 #define R_BCM1480_HSP_RX_SPI4_DESKEW_OVERRIDE 0x0000000010
 #define R_BCM1480_HSP_RX_SPI4_DESKEW_DATAPATH 0x0000000018
 #define R_BCM1480_HSP_RX_SPI4_PORT_INT_EN     0x0000000020


@@ -733,34 +733,34 @@
 #define R_BCM1480_HSP_RX_SPI4_CALENDAR_0      0x0000000200
 #define R_BCM1480_HSP_RX_SPI4_CALENDAR_1      0x0000000208
 
 #define R_BCM1480_HSP_RX_SPI4_CALENDAR_0      0x0000000200
 #define R_BCM1480_HSP_RX_SPI4_CALENDAR_1      0x0000000208
 

-#define R_BCM1480_HSP_RX_PLL_CNFG             0x0000000800
-#define R_BCM1480_HSP_RX_CALIBRATION          0x0000000808
-#define R_BCM1480_HSP_RX_TEST                 0x0000000810
-#define R_BCM1480_HSP_RX_DIAG_DETAILS         0x0000000818
-#define R_BCM1480_HSP_RX_DIAG_CRC_0           0x0000000820
-#define R_BCM1480_HSP_RX_DIAG_CRC_1           0x0000000828
-#define R_BCM1480_HSP_RX_DIAG_HTCMD           0x0000000830
-#define R_BCM1480_HSP_RX_DIAG_PKTCTL          0x0000000838
+#define R_BCM1480_HSP_RX_PLL_CNFG            0x0000000800
+#define R_BCM1480_HSP_RX_CALIBRATION         0x0000000808
+#define R_BCM1480_HSP_RX_TEST                0x0000000810
+#define R_BCM1480_HSP_RX_DIAG_DETAILS        0x0000000818
+#define R_BCM1480_HSP_RX_DIAG_CRC_0          0x0000000820
+#define R_BCM1480_HSP_RX_DIAG_CRC_1          0x0000000828
+#define R_BCM1480_HSP_RX_DIAG_HTCMD          0x0000000830
+#define R_BCM1480_HSP_RX_DIAG_PKTCTL         0x0000000838

 
 #define R_BCM1480_HSP_RX_VIS_FLCTRL_COUNTER   0x0000000870
 
 
 #define R_BCM1480_HSP_RX_VIS_FLCTRL_COUNTER   0x0000000870
 

-#define R_BCM1480_HSP_RX_PKT_RAMALLOC_0       0x0000020020
-#define R_BCM1480_HSP_RX_PKT_RAMALLOC_1       0x0000020028
-#define R_BCM1480_HSP_RX_PKT_RAMALLOC_2       0x0000020030
-#define R_BCM1480_HSP_RX_PKT_RAMALLOC_3       0x0000020038
-#define R_BCM1480_HSP_RX_PKT_RAMALLOC_4       0x0000020040
-#define R_BCM1480_HSP_RX_PKT_RAMALLOC_5       0x0000020048
-#define R_BCM1480_HSP_RX_PKT_RAMALLOC_6       0x0000020050
-#define R_BCM1480_HSP_RX_PKT_RAMALLOC_7       0x0000020058
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_0              0x0000020020
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_1              0x0000020028
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_2              0x0000020030
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_3              0x0000020038
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_4              0x0000020040
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_5              0x0000020048
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_6              0x0000020050
+#define R_BCM1480_HSP_RX_PKT_RAMALLOC_7              0x0000020058

 #define R_BCM1480_HSP_RX_PKT_RAMALLOC(idx)    (R_BCM1480_HSP_RX_PKT_RAMALLOC_0 + 8*(idx))
 
 /* XXX Following registers were shuffled.  Renamed/renumbered per errata. */
 #define R_BCM1480_HSP_RX_PKT_RAMALLOC(idx)    (R_BCM1480_HSP_RX_PKT_RAMALLOC_0 + 8*(idx))
 
 /* XXX Following registers were shuffled.  Renamed/renumbered per errata. */

-#define R_BCM1480_HSP_RX_HT_RAMALLOC_0      0x0000020078
-#define R_BCM1480_HSP_RX_HT_RAMALLOC_1      0x0000020080
-#define R_BCM1480_HSP_RX_HT_RAMALLOC_2      0x0000020088
-#define R_BCM1480_HSP_RX_HT_RAMALLOC_3      0x0000020090
-#define R_BCM1480_HSP_RX_HT_RAMALLOC_4      0x0000020098
-#define R_BCM1480_HSP_RX_HT_RAMALLOC_5      0x00000200A0
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_0     0x0000020078
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_1     0x0000020080
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_2     0x0000020088
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_3     0x0000020090
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_4     0x0000020098
+#define R_BCM1480_HSP_RX_HT_RAMALLOC_5     0x00000200A0

 
 #define R_BCM1480_HSP_RX_SPI_WATERMARK_0      0x00000200B0
 #define R_BCM1480_HSP_RX_SPI_WATERMARK_1      0x00000200B8
 
 #define R_BCM1480_HSP_RX_SPI_WATERMARK_0      0x00000200B0
 #define R_BCM1480_HSP_RX_SPI_WATERMARK_1      0x00000200B8


@@ -772,30 +772,30 @@
 #define R_BCM1480_HSP_RX_SPI_WATERMARK_7      0x00000200E8
 #define R_BCM1480_HSP_RX_SPI_WATERMARK(idx)   (R_BCM1480_HSP_RX_SPI_WATERMARK_0 + 8*(idx))
 
 #define R_BCM1480_HSP_RX_SPI_WATERMARK_7      0x00000200E8
 #define R_BCM1480_HSP_RX_SPI_WATERMARK(idx)   (R_BCM1480_HSP_RX_SPI_WATERMARK_0 + 8*(idx))
 

-#define R_BCM1480_HSP_RX_VIS_CMDQ_0           0x00000200F0
-#define R_BCM1480_HSP_RX_VIS_CMDQ_1           0x00000200F8
-#define R_BCM1480_HSP_RX_VIS_CMDQ_2           0x0000020100
-#define R_BCM1480_HSP_RX_RAM_READCTL          0x0000020108
-#define R_BCM1480_HSP_RX_RAM_READWINDOW       0x0000020110
-#define R_BCM1480_HSP_RX_RF_READCTL           0x0000020118
-#define R_BCM1480_HSP_RX_RF_READWINDOW        0x0000020120
+#define R_BCM1480_HSP_RX_VIS_CMDQ_0          0x00000200F0
+#define R_BCM1480_HSP_RX_VIS_CMDQ_1          0x00000200F8
+#define R_BCM1480_HSP_RX_VIS_CMDQ_2          0x0000020100
+#define R_BCM1480_HSP_RX_RAM_READCTL         0x0000020108
+#define R_BCM1480_HSP_RX_RAM_READWINDOW              0x0000020110
+#define R_BCM1480_HSP_RX_RF_READCTL          0x0000020118
+#define R_BCM1480_HSP_RX_RF_READWINDOW       0x0000020120

 
 

-#define R_BCM1480_HSP_TX_SPI4_CFG_0           0x0000040000
-#define R_BCM1480_HSP_TX_SPI4_CFG_1           0x0000040008
+#define R_BCM1480_HSP_TX_SPI4_CFG_0          0x0000040000
+#define R_BCM1480_HSP_TX_SPI4_CFG_1          0x0000040008

 #define R_BCM1480_HSP_TX_SPI4_TRAINING_FMT    0x0000040010
 
 #define R_BCM1480_HSP_TX_SPI4_TRAINING_FMT    0x0000040010
 

-#define R_BCM1480_HSP_TX_PKT_RAMALLOC_0       0x0000040020
-#define R_BCM1480_HSP_TX_PKT_RAMALLOC_1       0x0000040028
-#define R_BCM1480_HSP_TX_PKT_RAMALLOC_2       0x0000040030
-#define R_BCM1480_HSP_TX_PKT_RAMALLOC_3       0x0000040038
-#define R_BCM1480_HSP_TX_PKT_RAMALLOC_4       0x0000040040
-#define R_BCM1480_HSP_TX_PKT_RAMALLOC_5       0x0000040048
-#define R_BCM1480_HSP_TX_PKT_RAMALLOC_6       0x0000040050
-#define R_BCM1480_HSP_TX_PKT_RAMALLOC_7       0x0000040058
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_0              0x0000040020
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_1              0x0000040028
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_2              0x0000040030
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_3              0x0000040038
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_4              0x0000040040
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_5              0x0000040048
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_6              0x0000040050
+#define R_BCM1480_HSP_TX_PKT_RAMALLOC_7              0x0000040058

 #define R_BCM1480_HSP_TX_PKT_RAMALLOC(idx)    (R_BCM1480_HSP_TX_PKT_RAMALLOC_0 + 8*(idx))
 #define R_BCM1480_HSP_TX_PKT_RAMALLOC(idx)    (R_BCM1480_HSP_TX_PKT_RAMALLOC_0 + 8*(idx))

-#define R_BCM1480_HSP_TX_NPC_RAMALLOC         0x0000040078
-#define R_BCM1480_HSP_TX_RSP_RAMALLOC         0x0000040080
-#define R_BCM1480_HSP_TX_PC_RAMALLOC          0x0000040088
+#define R_BCM1480_HSP_TX_NPC_RAMALLOC        0x0000040078
+#define R_BCM1480_HSP_TX_RSP_RAMALLOC        0x0000040080
+#define R_BCM1480_HSP_TX_PC_RAMALLOC         0x0000040088

 #define R_BCM1480_HSP_TX_HTCC_RAMALLOC_0      0x0000040090
 #define R_BCM1480_HSP_TX_HTCC_RAMALLOC_1      0x0000040098
 #define R_BCM1480_HSP_TX_HTCC_RAMALLOC_2      0x00000400A0
 #define R_BCM1480_HSP_TX_HTCC_RAMALLOC_0      0x0000040090
 #define R_BCM1480_HSP_TX_HTCC_RAMALLOC_1      0x0000040098
 #define R_BCM1480_HSP_TX_HTCC_RAMALLOC_2      0x00000400A0


@@ -805,37 +805,37 @@
 #define R_BCM1480_HSP_TX_PKT_RXPHITCNT_2      0x00000400C0
 #define R_BCM1480_HSP_TX_PKT_RXPHITCNT_3      0x00000400C8
 #define R_BCM1480_HSP_TX_PKT_RXPHITCNT(idx)   (R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 + 8*(idx))
 #define R_BCM1480_HSP_TX_PKT_RXPHITCNT_2      0x00000400C0
 #define R_BCM1480_HSP_TX_PKT_RXPHITCNT_3      0x00000400C8
 #define R_BCM1480_HSP_TX_PKT_RXPHITCNT(idx)   (R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 + 8*(idx))

-#define R_BCM1480_HSP_TX_HTIO_RXPHITCNT       0x00000400D0
-#define R_BCM1480_HSP_TX_HTCC_RXPHITCNT       0x00000400D8
+#define R_BCM1480_HSP_TX_HTIO_RXPHITCNT              0x00000400D0
+#define R_BCM1480_HSP_TX_HTCC_RXPHITCNT              0x00000400D8

 
 #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_0      0x00000400E0
 #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_1      0x00000400E8
 #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_2      0x00000400F0
 #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_3      0x00000400F8
 #define R_BCM1480_HSP_TX_PKT_TXPHITCNT(idx)   (R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 + 8*(idx))
 
 #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_0      0x00000400E0
 #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_1      0x00000400E8
 #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_2      0x00000400F0
 #define R_BCM1480_HSP_TX_PKT_TXPHITCNT_3      0x00000400F8
 #define R_BCM1480_HSP_TX_PKT_TXPHITCNT(idx)   (R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 + 8*(idx))

-#define R_BCM1480_HSP_TX_HTIO_TXPHITCNT       0x0000040100
-#define R_BCM1480_HSP_TX_HTCC_TXPHITCNT       0x0000040108
+#define R_BCM1480_HSP_TX_HTIO_TXPHITCNT              0x0000040100
+#define R_BCM1480_HSP_TX_HTCC_TXPHITCNT              0x0000040108

 
 #define R_BCM1480_HSP_TX_SPI4_CALENDAR_0      0x0000040200
 #define R_BCM1480_HSP_TX_SPI4_CALENDAR_1      0x0000040208
 
 
 #define R_BCM1480_HSP_TX_SPI4_CALENDAR_0      0x0000040200
 #define R_BCM1480_HSP_TX_SPI4_CALENDAR_1      0x0000040208
 

-#define R_BCM1480_HSP_TX_PLL_CNFG             0x0000040800
-#define R_BCM1480_HSP_TX_CALIBRATION          0x0000040808
-#define R_BCM1480_HSP_TX_TEST                 0x0000040810
+#define R_BCM1480_HSP_TX_PLL_CNFG            0x0000040800
+#define R_BCM1480_HSP_TX_CALIBRATION         0x0000040808
+#define R_BCM1480_HSP_TX_TEST                0x0000040810

 
 

-#define R_BCM1480_HSP_TX_VIS_CMDQ_0           0x0000040840
-#define R_BCM1480_HSP_TX_VIS_CMDQ_1           0x0000040848
-#define R_BCM1480_HSP_TX_VIS_CMDQ_2           0x0000040850
-#define R_BCM1480_HSP_TX_RAM_READCTL          0x0000040860
-#define R_BCM1480_HSP_TX_RAM_READWINDOW       0x0000040868
-#define R_BCM1480_HSP_TX_RF_READCTL           0x0000040870
-#define R_BCM1480_HSP_TX_RF_READWINDOW        0x0000040878
+#define R_BCM1480_HSP_TX_VIS_CMDQ_0          0x0000040840
+#define R_BCM1480_HSP_TX_VIS_CMDQ_1          0x0000040848
+#define R_BCM1480_HSP_TX_VIS_CMDQ_2          0x0000040850
+#define R_BCM1480_HSP_TX_RAM_READCTL         0x0000040860
+#define R_BCM1480_HSP_TX_RAM_READWINDOW              0x0000040868
+#define R_BCM1480_HSP_TX_RF_READCTL          0x0000040870
+#define R_BCM1480_HSP_TX_RF_READWINDOW       0x0000040878

 
 #define R_BCM1480_HSP_TX_SPI4_PORT_INT_STATUS 0x0000040880
 #define R_BCM1480_HSP_TX_SPI4_PORT_INT_EN     0x0000040888
 
 #define R_BCM1480_HSP_TX_NEXT_ADDR_BASE 0x000040400
 
 #define R_BCM1480_HSP_TX_SPI4_PORT_INT_STATUS 0x0000040880
 #define R_BCM1480_HSP_TX_SPI4_PORT_INT_EN     0x0000040888
 
 #define R_BCM1480_HSP_TX_NEXT_ADDR_BASE 0x000040400

-#define R_BCM1480_HSP_TX_NEXT_ADDR_REGISTER(x)  (R_BCM1480_HSP_TX_NEXT_ADDR_BASE+ 8*(x))
+#define R_BCM1480_HSP_TX_NEXT_ADDR_REGISTER(x) (R_BCM1480_HSP_TX_NEXT_ADDR_BASE+ 8*(x))

 
 
 
 
 
 


@@ -843,60 +843,60 @@
     *  Physical Address Map (Table 10 and Figure 7)
     ********************************************************************* */
 
     *  Physical Address Map (Table 10 and Figure 7)
     ********************************************************************* */
 

-#define A_BCM1480_PHYS_MEMORY_0                 _SB_MAKE64(0x0000000000)
-#define A_BCM1480_PHYS_MEMORY_SIZE              _SB_MAKE64((256*1024*1024))
-#define A_BCM1480_PHYS_SYSTEM_CTL               _SB_MAKE64(0x0010000000)
-#define A_BCM1480_PHYS_IO_SYSTEM                _SB_MAKE64(0x0010060000)
-#define A_BCM1480_PHYS_GENBUS                   _SB_MAKE64(0x0010090000)
-#define A_BCM1480_PHYS_GENBUS_END               _SB_MAKE64(0x0028000000)
-#define A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES     _SB_MAKE64(0x0028000000)
-#define A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES     _SB_MAKE64(0x0029000000)
-#define A_BCM1480_PHYS_PCI_IO_MATCH_BYTES       _SB_MAKE64(0x002C000000)
-#define A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES      _SB_MAKE64(0x002E000000)
-#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES     _SB_MAKE64(0x002F000000)
-#define A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES      _SB_MAKE64(0x0030000000)
-#define A_BCM1480_PHYS_HT_MEM_MATCH_BYTES       _SB_MAKE64(0x0040000000)
-#define A_BCM1480_PHYS_HT_MEM_MATCH_BITS        _SB_MAKE64(0x0060000000)
-#define A_BCM1480_PHYS_MEMORY_1                 _SB_MAKE64(0x0080000000)
-#define A_BCM1480_PHYS_MEMORY_2                 _SB_MAKE64(0x0090000000)
-#define A_BCM1480_PHYS_PCI_MISC_MATCH_BITS      _SB_MAKE64(0x00A8000000)
-#define A_BCM1480_PHYS_PCI_IACK_MATCH_BITS      _SB_MAKE64(0x00A9000000)
-#define A_BCM1480_PHYS_PCI_IO_MATCH_BITS        _SB_MAKE64(0x00AC000000)
-#define A_BCM1480_PHYS_PCI_CFG_MATCH_BITS       _SB_MAKE64(0x00AE000000)
-#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS      _SB_MAKE64(0x00AF000000)
-#define A_BCM1480_PHYS_PCI_MEM_MATCH_BITS       _SB_MAKE64(0x00B0000000)
-#define A_BCM1480_PHYS_MEMORY_3                 _SB_MAKE64(0x00C0000000)
-#define A_BCM1480_PHYS_L2_CACHE_TEST            _SB_MAKE64(0x00D0000000)
-#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES   _SB_MAKE64(0x00D8000000)
-#define A_BCM1480_PHYS_HT_IO_MATCH_BYTES        _SB_MAKE64(0x00DC000000)
-#define A_BCM1480_PHYS_HT_CFG_MATCH_BYTES       _SB_MAKE64(0x00DE000000)
-#define A_BCM1480_PHYS_HS_SUBSYS                _SB_MAKE64(0x00DF000000)
-#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS    _SB_MAKE64(0x00F8000000)
-#define A_BCM1480_PHYS_HT_IO_MATCH_BITS         _SB_MAKE64(0x00FC000000)
-#define A_BCM1480_PHYS_HT_CFG_MATCH_BITS        _SB_MAKE64(0x00FE000000)
-#define A_BCM1480_PHYS_MEMORY_EXP               _SB_MAKE64(0x0100000000)
-#define A_BCM1480_PHYS_MEMORY_EXP_SIZE          _SB_MAKE64((508*1024*1024*1024))
-#define A_BCM1480_PHYS_PCI_UPPER                _SB_MAKE64(0x1000000000)
-#define A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES     _SB_MAKE64(0x2000000000)
-#define A_BCM1480_PHYS_HT_UPPER_MATCH_BITS      _SB_MAKE64(0x3000000000)
-#define A_BCM1480_PHYS_HT_NODE_ALIAS            _SB_MAKE64(0x4000000000)
-#define A_BCM1480_PHYS_HT_FULLACCESS            _SB_MAKE64(0xF000000000)
+#define A_BCM1480_PHYS_MEMORY_0                        _SB_MAKE64(0x0000000000)
+#define A_BCM1480_PHYS_MEMORY_SIZE             _SB_MAKE64((256*1024*1024))
+#define A_BCM1480_PHYS_SYSTEM_CTL              _SB_MAKE64(0x0010000000)
+#define A_BCM1480_PHYS_IO_SYSTEM               _SB_MAKE64(0x0010060000)
+#define A_BCM1480_PHYS_GENBUS                  _SB_MAKE64(0x0010090000)
+#define A_BCM1480_PHYS_GENBUS_END              _SB_MAKE64(0x0028000000)
+#define A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES    _SB_MAKE64(0x0028000000)
+#define A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES    _SB_MAKE64(0x0029000000)
+#define A_BCM1480_PHYS_PCI_IO_MATCH_BYTES      _SB_MAKE64(0x002C000000)
+#define A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES     _SB_MAKE64(0x002E000000)
+#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES    _SB_MAKE64(0x002F000000)
+#define A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES     _SB_MAKE64(0x0030000000)
+#define A_BCM1480_PHYS_HT_MEM_MATCH_BYTES      _SB_MAKE64(0x0040000000)
+#define A_BCM1480_PHYS_HT_MEM_MATCH_BITS       _SB_MAKE64(0x0060000000)
+#define A_BCM1480_PHYS_MEMORY_1                        _SB_MAKE64(0x0080000000)
+#define A_BCM1480_PHYS_MEMORY_2                        _SB_MAKE64(0x0090000000)
+#define A_BCM1480_PHYS_PCI_MISC_MATCH_BITS     _SB_MAKE64(0x00A8000000)
+#define A_BCM1480_PHYS_PCI_IACK_MATCH_BITS     _SB_MAKE64(0x00A9000000)
+#define A_BCM1480_PHYS_PCI_IO_MATCH_BITS       _SB_MAKE64(0x00AC000000)
+#define A_BCM1480_PHYS_PCI_CFG_MATCH_BITS      _SB_MAKE64(0x00AE000000)
+#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS     _SB_MAKE64(0x00AF000000)
+#define A_BCM1480_PHYS_PCI_MEM_MATCH_BITS      _SB_MAKE64(0x00B0000000)
+#define A_BCM1480_PHYS_MEMORY_3                        _SB_MAKE64(0x00C0000000)
+#define A_BCM1480_PHYS_L2_CACHE_TEST           _SB_MAKE64(0x00D0000000)
+#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES  _SB_MAKE64(0x00D8000000)
+#define A_BCM1480_PHYS_HT_IO_MATCH_BYTES       _SB_MAKE64(0x00DC000000)
+#define A_BCM1480_PHYS_HT_CFG_MATCH_BYTES      _SB_MAKE64(0x00DE000000)
+#define A_BCM1480_PHYS_HS_SUBSYS               _SB_MAKE64(0x00DF000000)
+#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS   _SB_MAKE64(0x00F8000000)
+#define A_BCM1480_PHYS_HT_IO_MATCH_BITS                _SB_MAKE64(0x00FC000000)
+#define A_BCM1480_PHYS_HT_CFG_MATCH_BITS       _SB_MAKE64(0x00FE000000)
+#define A_BCM1480_PHYS_MEMORY_EXP              _SB_MAKE64(0x0100000000)
+#define A_BCM1480_PHYS_MEMORY_EXP_SIZE         _SB_MAKE64((508*1024*1024*1024))
+#define A_BCM1480_PHYS_PCI_UPPER               _SB_MAKE64(0x1000000000)
+#define A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES    _SB_MAKE64(0x2000000000)
+#define A_BCM1480_PHYS_HT_UPPER_MATCH_BITS     _SB_MAKE64(0x3000000000)
+#define A_BCM1480_PHYS_HT_NODE_ALIAS           _SB_MAKE64(0x4000000000)
+#define A_BCM1480_PHYS_HT_FULLACCESS           _SB_MAKE64(0xF000000000)

 
 
 /*  *********************************************************************
     *  L2 Cache as RAM (Table 54)
     ********************************************************************* */
 
 
 
 /*  *********************************************************************
     *  L2 Cache as RAM (Table 54)
     ********************************************************************* */
 

-#define A_BCM1480_PHYS_L2CACHE_WAY_SIZE         _SB_MAKE64(0x0000020000)
-#define BCM1480_PHYS_L2CACHE_NUM_WAYS           8
-#define A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE       _SB_MAKE64(0x0000100000)
-#define A_BCM1480_PHYS_L2CACHE_WAY0             _SB_MAKE64(0x00D0300000)
-#define A_BCM1480_PHYS_L2CACHE_WAY1             _SB_MAKE64(0x00D0320000)
-#define A_BCM1480_PHYS_L2CACHE_WAY2             _SB_MAKE64(0x00D0340000)
-#define A_BCM1480_PHYS_L2CACHE_WAY3             _SB_MAKE64(0x00D0360000)
-#define A_BCM1480_PHYS_L2CACHE_WAY4             _SB_MAKE64(0x00D0380000)
-#define A_BCM1480_PHYS_L2CACHE_WAY5             _SB_MAKE64(0x00D03A0000)
-#define A_BCM1480_PHYS_L2CACHE_WAY6             _SB_MAKE64(0x00D03C0000)
-#define A_BCM1480_PHYS_L2CACHE_WAY7             _SB_MAKE64(0x00D03E0000)
+#define A_BCM1480_PHYS_L2CACHE_WAY_SIZE                _SB_MAKE64(0x0000020000)
+#define BCM1480_PHYS_L2CACHE_NUM_WAYS          8
+#define A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE      _SB_MAKE64(0x0000100000)
+#define A_BCM1480_PHYS_L2CACHE_WAY0            _SB_MAKE64(0x00D0300000)
+#define A_BCM1480_PHYS_L2CACHE_WAY1            _SB_MAKE64(0x00D0320000)
+#define A_BCM1480_PHYS_L2CACHE_WAY2            _SB_MAKE64(0x00D0340000)
+#define A_BCM1480_PHYS_L2CACHE_WAY3            _SB_MAKE64(0x00D0360000)
+#define A_BCM1480_PHYS_L2CACHE_WAY4            _SB_MAKE64(0x00D0380000)
+#define A_BCM1480_PHYS_L2CACHE_WAY5            _SB_MAKE64(0x00D03A0000)
+#define A_BCM1480_PHYS_L2CACHE_WAY6            _SB_MAKE64(0x00D03C0000)
+#define A_BCM1480_PHYS_L2CACHE_WAY7            _SB_MAKE64(0x00D03E0000)

 
 #endif /* _BCM1480_REGS_H */
 
 #endif /* _BCM1480_REGS_H */

diff --git a/arch/mips/include/asm/sibyte/bcm1480_scd.h b/arch/mips/include/asm/sibyte/bcm1480_scd.h
index 2af3706b964860be7ef32602ab98f821994e9b5b..8a1e2b05a626f1838c985d4ab7da4e04ba15a093 100644 (file)
--- a/arch/mips/include/asm/sibyte/bcm1480_scd.h
+++ b/arch/mips/include/asm/sibyte/bcm1480_scd.h
@@ -1,7 +1,7 @@
 /*  *********************************************************************
     *  BCM1280/BCM1400 Board Support Package
     *
 /*  *********************************************************************
     *  BCM1280/BCM1400 Board Support Package
     *

-    *  SCD Constants and Macros                     File: bcm1480_scd.h
+    *  SCD Constants and Macros                            File: bcm1480_scd.h

     *
     *  This module contains constants and macros useful for
     *  manipulating the System Control and Debug module.
     *
     *  This module contains constants and macros useful for
     *  manipulating the System Control and Debug module.


@@ -74,11 +74,11 @@
  * New part definitions
  */
 
  * New part definitions
  */
 

-#define K_SYS_PART_BCM1480          0x1406
-#define K_SYS_PART_BCM1280          0x1206
-#define K_SYS_PART_BCM1455          0x1407
-#define K_SYS_PART_BCM1255          0x1257
-#define K_SYS_PART_BCM1158          0x1156
+#define K_SYS_PART_BCM1480         0x1406
+#define K_SYS_PART_BCM1280         0x1206
+#define K_SYS_PART_BCM1455         0x1407
+#define K_SYS_PART_BCM1255         0x1257
+#define K_SYS_PART_BCM1158         0x1156

 
 /*
  * Manufacturing Information Register (Table 14)
 
 /*
  * Manufacturing Information Register (Table 14)


@@ -91,73 +91,73 @@
  * Entire register is different from 1250, all new constants below
  */
 
  * Entire register is different from 1250, all new constants below
  */
 

-#define M_BCM1480_SYS_RESERVED0             _SB_MAKEMASK1(0)
-#define M_BCM1480_SYS_HT_MINRSTCNT          _SB_MAKEMASK1(1)
-#define M_BCM1480_SYS_RESERVED2             _SB_MAKEMASK1(2)
-#define M_BCM1480_SYS_RESERVED3             _SB_MAKEMASK1(3)
-#define M_BCM1480_SYS_RESERVED4             _SB_MAKEMASK1(4)
-#define M_BCM1480_SYS_IOB_DIV               _SB_MAKEMASK1(5)
-
-#define S_BCM1480_SYS_PLL_DIV               _SB_MAKE64(6)
-#define M_BCM1480_SYS_PLL_DIV               _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV)
-#define V_BCM1480_SYS_PLL_DIV(x)            _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV)
-#define G_BCM1480_SYS_PLL_DIV(x)            _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV)
-
-#define S_BCM1480_SYS_SW_DIV                _SB_MAKE64(11)
-#define M_BCM1480_SYS_SW_DIV                _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV)
-#define V_BCM1480_SYS_SW_DIV(x)             _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV)
-#define G_BCM1480_SYS_SW_DIV(x)             _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV)
-
-#define M_BCM1480_SYS_PCMCIA_ENABLE         _SB_MAKEMASK1(16)
-#define M_BCM1480_SYS_DUART1_ENABLE         _SB_MAKEMASK1(17)
-
-#define S_BCM1480_SYS_BOOT_MODE             _SB_MAKE64(18)
-#define M_BCM1480_SYS_BOOT_MODE             _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE)
-#define V_BCM1480_SYS_BOOT_MODE(x)          _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE)
-#define G_BCM1480_SYS_BOOT_MODE(x)          _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE)
-#define K_BCM1480_SYS_BOOT_MODE_ROM32       0
-#define K_BCM1480_SYS_BOOT_MODE_ROM8        1
+#define M_BCM1480_SYS_RESERVED0                    _SB_MAKEMASK1(0)
+#define M_BCM1480_SYS_HT_MINRSTCNT         _SB_MAKEMASK1(1)
+#define M_BCM1480_SYS_RESERVED2                    _SB_MAKEMASK1(2)
+#define M_BCM1480_SYS_RESERVED3                    _SB_MAKEMASK1(3)
+#define M_BCM1480_SYS_RESERVED4                    _SB_MAKEMASK1(4)
+#define M_BCM1480_SYS_IOB_DIV              _SB_MAKEMASK1(5)
+
+#define S_BCM1480_SYS_PLL_DIV              _SB_MAKE64(6)
+#define M_BCM1480_SYS_PLL_DIV              _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV)
+#define V_BCM1480_SYS_PLL_DIV(x)           _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV)
+#define G_BCM1480_SYS_PLL_DIV(x)           _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV)
+
+#define S_BCM1480_SYS_SW_DIV               _SB_MAKE64(11)
+#define M_BCM1480_SYS_SW_DIV               _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV)
+#define V_BCM1480_SYS_SW_DIV(x)                    _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV)
+#define G_BCM1480_SYS_SW_DIV(x)                    _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV)
+
+#define M_BCM1480_SYS_PCMCIA_ENABLE        _SB_MAKEMASK1(16)
+#define M_BCM1480_SYS_DUART1_ENABLE        _SB_MAKEMASK1(17)
+
+#define S_BCM1480_SYS_BOOT_MODE                    _SB_MAKE64(18)
+#define M_BCM1480_SYS_BOOT_MODE                    _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE)
+#define V_BCM1480_SYS_BOOT_MODE(x)         _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE)
+#define G_BCM1480_SYS_BOOT_MODE(x)         _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE)
+#define K_BCM1480_SYS_BOOT_MODE_ROM32      0
+#define K_BCM1480_SYS_BOOT_MODE_ROM8       1

 #define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2
 #define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG   3
 #define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2
 #define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG   3

-#define M_BCM1480_SYS_BOOT_MODE_SMBUS       _SB_MAKEMASK1(19)
-
-#define M_BCM1480_SYS_PCI_HOST              _SB_MAKEMASK1(20)
-#define M_BCM1480_SYS_PCI_ARBITER           _SB_MAKEMASK1(21)
-#define M_BCM1480_SYS_BIG_ENDIAN            _SB_MAKEMASK1(22)
-#define M_BCM1480_SYS_GENCLK_EN             _SB_MAKEMASK1(23)
-#define M_BCM1480_SYS_GEN_PARITY_EN         _SB_MAKEMASK1(24)
-#define M_BCM1480_SYS_RESERVED25            _SB_MAKEMASK1(25)
-
-#define S_BCM1480_SYS_CONFIG                26
-#define M_BCM1480_SYS_CONFIG                _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG)
-#define V_BCM1480_SYS_CONFIG(x)             _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG)
-#define G_BCM1480_SYS_CONFIG(x)             _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG)
-
-#define M_BCM1480_SYS_RESERVED32            _SB_MAKEMASK(32, 15)
-
-#define S_BCM1480_SYS_NODEID                47
-#define M_BCM1480_SYS_NODEID                _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID)
-#define V_BCM1480_SYS_NODEID(x)             _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID)
-#define G_BCM1480_SYS_NODEID(x)             _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID)
-
-#define M_BCM1480_SYS_CCNUMA_EN             _SB_MAKEMASK1(51)
-#define M_BCM1480_SYS_CPU_RESET_0           _SB_MAKEMASK1(52)
-#define M_BCM1480_SYS_CPU_RESET_1           _SB_MAKEMASK1(53)
-#define M_BCM1480_SYS_CPU_RESET_2           _SB_MAKEMASK1(54)
-#define M_BCM1480_SYS_CPU_RESET_3           _SB_MAKEMASK1(55)
-#define S_BCM1480_SYS_DISABLECPU0           56
-#define M_BCM1480_SYS_DISABLECPU0           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0)
-#define S_BCM1480_SYS_DISABLECPU1           57
-#define M_BCM1480_SYS_DISABLECPU1           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1)
-#define S_BCM1480_SYS_DISABLECPU2           58
-#define M_BCM1480_SYS_DISABLECPU2           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2)
-#define S_BCM1480_SYS_DISABLECPU3           59
-#define M_BCM1480_SYS_DISABLECPU3           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3)
-
-#define M_BCM1480_SYS_SB_SOFTRES            _SB_MAKEMASK1(60)
-#define M_BCM1480_SYS_EXT_RESET             _SB_MAKEMASK1(61)
-#define M_BCM1480_SYS_SYSTEM_RESET          _SB_MAKEMASK1(62)
-#define M_BCM1480_SYS_SW_FLAG               _SB_MAKEMASK1(63)
+#define M_BCM1480_SYS_BOOT_MODE_SMBUS      _SB_MAKEMASK1(19)
+
+#define M_BCM1480_SYS_PCI_HOST             _SB_MAKEMASK1(20)
+#define M_BCM1480_SYS_PCI_ARBITER          _SB_MAKEMASK1(21)
+#define M_BCM1480_SYS_BIG_ENDIAN           _SB_MAKEMASK1(22)
+#define M_BCM1480_SYS_GENCLK_EN                    _SB_MAKEMASK1(23)
+#define M_BCM1480_SYS_GEN_PARITY_EN        _SB_MAKEMASK1(24)
+#define M_BCM1480_SYS_RESERVED25           _SB_MAKEMASK1(25)
+
+#define S_BCM1480_SYS_CONFIG               26
+#define M_BCM1480_SYS_CONFIG               _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG)
+#define V_BCM1480_SYS_CONFIG(x)                    _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG)
+#define G_BCM1480_SYS_CONFIG(x)                    _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG)
+
+#define M_BCM1480_SYS_RESERVED32           _SB_MAKEMASK(32, 15)
+
+#define S_BCM1480_SYS_NODEID               47
+#define M_BCM1480_SYS_NODEID               _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID)
+#define V_BCM1480_SYS_NODEID(x)                    _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID)
+#define G_BCM1480_SYS_NODEID(x)                    _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID)
+
+#define M_BCM1480_SYS_CCNUMA_EN                    _SB_MAKEMASK1(51)
+#define M_BCM1480_SYS_CPU_RESET_0          _SB_MAKEMASK1(52)
+#define M_BCM1480_SYS_CPU_RESET_1          _SB_MAKEMASK1(53)
+#define M_BCM1480_SYS_CPU_RESET_2          _SB_MAKEMASK1(54)
+#define M_BCM1480_SYS_CPU_RESET_3          _SB_MAKEMASK1(55)
+#define S_BCM1480_SYS_DISABLECPU0          56
+#define M_BCM1480_SYS_DISABLECPU0          _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0)
+#define S_BCM1480_SYS_DISABLECPU1          57
+#define M_BCM1480_SYS_DISABLECPU1          _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1)
+#define S_BCM1480_SYS_DISABLECPU2          58
+#define M_BCM1480_SYS_DISABLECPU2          _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2)
+#define S_BCM1480_SYS_DISABLECPU3          59
+#define M_BCM1480_SYS_DISABLECPU3          _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3)
+
+#define M_BCM1480_SYS_SB_SOFTRES           _SB_MAKEMASK1(60)
+#define M_BCM1480_SYS_EXT_RESET                    _SB_MAKEMASK1(61)
+#define M_BCM1480_SYS_SYSTEM_RESET         _SB_MAKEMASK1(62)
+#define M_BCM1480_SYS_SW_FLAG              _SB_MAKEMASK1(63)

 
 /*
  * Scratch Register (Table 16)
 
 /*
  * Scratch Register (Table 16)


@@ -193,23 +193,23 @@
  * Registers: SCD_WDOG_CFG_x
  */
 
  * Registers: SCD_WDOG_CFG_x
  */
 

-#define M_BCM1480_SCD_WDOG_ENABLE           _SB_MAKEMASK1(0)
+#define M_BCM1480_SCD_WDOG_ENABLE          _SB_MAKEMASK1(0)

 
 

-#define S_BCM1480_SCD_WDOG_RESET_TYPE       2
-#define M_BCM1480_SCD_WDOG_RESET_TYPE       _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE)
+#define S_BCM1480_SCD_WDOG_RESET_TYPE      2
+#define M_BCM1480_SCD_WDOG_RESET_TYPE      _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE)

 #define V_BCM1480_SCD_WDOG_RESET_TYPE(x)    _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE)
 #define G_BCM1480_SCD_WDOG_RESET_TYPE(x)    _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE)
 
 #define V_BCM1480_SCD_WDOG_RESET_TYPE(x)    _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE)
 #define G_BCM1480_SCD_WDOG_RESET_TYPE(x)    _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE)
 

-#define K_BCM1480_SCD_WDOG_RESET_FULL       0  /* actually, (x & 1) == 0  */
-#define K_BCM1480_SCD_WDOG_RESET_SOFT       1
-#define K_BCM1480_SCD_WDOG_RESET_CPU0       3
-#define K_BCM1480_SCD_WDOG_RESET_CPU1       5
-#define K_BCM1480_SCD_WDOG_RESET_CPU2       9
-#define K_BCM1480_SCD_WDOG_RESET_CPU3       17
+#define K_BCM1480_SCD_WDOG_RESET_FULL      0   /* actually, (x & 1) == 0  */
+#define K_BCM1480_SCD_WDOG_RESET_SOFT      1
+#define K_BCM1480_SCD_WDOG_RESET_CPU0      3
+#define K_BCM1480_SCD_WDOG_RESET_CPU1      5
+#define K_BCM1480_SCD_WDOG_RESET_CPU2      9
+#define K_BCM1480_SCD_WDOG_RESET_CPU3      17

 #define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS   31
 
 
 #define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS   31
 
 

-#define M_BCM1480_SCD_WDOG_HAS_RESET        _SB_MAKEMASK1(8)
+#define M_BCM1480_SCD_WDOG_HAS_RESET       _SB_MAKEMASK1(8)

 
 /*
  * General Timer Initial Count Registers (Table 26)
 
 /*
  * General Timer Initial Count Registers (Table 26)


@@ -243,32 +243,32 @@
  * The clear/enable bits are in different locations on the 1250 and 1480.
  */
 
  * The clear/enable bits are in different locations on the 1250 and 1480.
  */
 

-#define S_SPC_CFG_SRC4              32
-#define M_SPC_CFG_SRC4              _SB_MAKEMASK(8, S_SPC_CFG_SRC4)
-#define V_SPC_CFG_SRC4(x)           _SB_MAKEVALUE(x, S_SPC_CFG_SRC4)
-#define G_SPC_CFG_SRC4(x)           _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4)
+#define S_SPC_CFG_SRC4             32
+#define M_SPC_CFG_SRC4             _SB_MAKEMASK(8, S_SPC_CFG_SRC4)
+#define V_SPC_CFG_SRC4(x)          _SB_MAKEVALUE(x, S_SPC_CFG_SRC4)
+#define G_SPC_CFG_SRC4(x)          _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4)

 
 

-#define S_SPC_CFG_SRC5              40
-#define M_SPC_CFG_SRC5              _SB_MAKEMASK(8, S_SPC_CFG_SRC5)
-#define V_SPC_CFG_SRC5(x)           _SB_MAKEVALUE(x, S_SPC_CFG_SRC5)
-#define G_SPC_CFG_SRC5(x)           _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5)
+#define S_SPC_CFG_SRC5             40
+#define M_SPC_CFG_SRC5             _SB_MAKEMASK(8, S_SPC_CFG_SRC5)
+#define V_SPC_CFG_SRC5(x)          _SB_MAKEVALUE(x, S_SPC_CFG_SRC5)
+#define G_SPC_CFG_SRC5(x)          _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5)

 
 

-#define S_SPC_CFG_SRC6              48
-#define M_SPC_CFG_SRC6              _SB_MAKEMASK(8, S_SPC_CFG_SRC6)
-#define V_SPC_CFG_SRC6(x)           _SB_MAKEVALUE(x, S_SPC_CFG_SRC6)
-#define G_SPC_CFG_SRC6(x)           _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6)
+#define S_SPC_CFG_SRC6             48
+#define M_SPC_CFG_SRC6             _SB_MAKEMASK(8, S_SPC_CFG_SRC6)
+#define V_SPC_CFG_SRC6(x)          _SB_MAKEVALUE(x, S_SPC_CFG_SRC6)
+#define G_SPC_CFG_SRC6(x)          _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6)

 
 

-#define S_SPC_CFG_SRC7              56
-#define M_SPC_CFG_SRC7              _SB_MAKEMASK(8, S_SPC_CFG_SRC7)
-#define V_SPC_CFG_SRC7(x)           _SB_MAKEVALUE(x, S_SPC_CFG_SRC7)
-#define G_SPC_CFG_SRC7(x)           _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7)
+#define S_SPC_CFG_SRC7             56
+#define M_SPC_CFG_SRC7             _SB_MAKEMASK(8, S_SPC_CFG_SRC7)
+#define V_SPC_CFG_SRC7(x)          _SB_MAKEVALUE(x, S_SPC_CFG_SRC7)
+#define G_SPC_CFG_SRC7(x)          _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7)

 
 /*
  * System Performance Counter Control Register (Table 32)
  * Register: PERF_CNT_CFG_1
  * BCM1480 specific
  */
 
 /*
  * System Performance Counter Control Register (Table 32)
  * Register: PERF_CNT_CFG_1
  * BCM1480 specific
  */

-#define M_BCM1480_SPC_CFG_CLEAR     _SB_MAKEMASK1(0)
+#define M_BCM1480_SPC_CFG_CLEAR            _SB_MAKEMASK1(0)

 #define M_BCM1480_SPC_CFG_ENABLE    _SB_MAKEMASK1(1)
 #if SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_SPC_CFG_CLEAR                        M_BCM1480_SPC_CFG_CLEAR
 #define M_BCM1480_SPC_CFG_ENABLE    _SB_MAKEMASK1(1)
 #if SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_SPC_CFG_CLEAR                        M_BCM1480_SPC_CFG_CLEAR


@@ -280,12 +280,12 @@
  * Registers: PERF_CNT_x
  */
 
  * Registers: PERF_CNT_x
  */
 

-#define S_BCM1480_SPC_CNT_COUNT             0
-#define M_BCM1480_SPC_CNT_COUNT             _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT)
-#define V_BCM1480_SPC_CNT_COUNT(x)          _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT)
-#define G_BCM1480_SPC_CNT_COUNT(x)          _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT)
+#define S_BCM1480_SPC_CNT_COUNT                    0
+#define M_BCM1480_SPC_CNT_COUNT                    _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT)
+#define V_BCM1480_SPC_CNT_COUNT(x)         _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT)
+#define G_BCM1480_SPC_CNT_COUNT(x)         _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT)

 
 

-#define M_BCM1480_SPC_CNT_OFLOW             _SB_MAKEMASK1(40)
+#define M_BCM1480_SPC_CNT_OFLOW                    _SB_MAKEMASK1(40)

 
 
 /*
 
 
 /*


@@ -325,45 +325,45 @@
 #define M_BCM1480_ATRAP_INDEX            _SB_MAKEMASK(4, 0)
 #define M_BCM1480_ATRAP_ADDRESS                  _SB_MAKEMASK(40, 0)
 
 #define M_BCM1480_ATRAP_INDEX            _SB_MAKEMASK(4, 0)
 #define M_BCM1480_ATRAP_ADDRESS                  _SB_MAKEMASK(40, 0)
 

-#define S_BCM1480_ATRAP_CFG_CNT            0
-#define M_BCM1480_ATRAP_CFG_CNT            _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT)
-#define V_BCM1480_ATRAP_CFG_CNT(x)         _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT)
-#define G_BCM1480_ATRAP_CFG_CNT(x)         _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT)
+#define S_BCM1480_ATRAP_CFG_CNT                   0
+#define M_BCM1480_ATRAP_CFG_CNT                   _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT)
+#define V_BCM1480_ATRAP_CFG_CNT(x)        _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT)
+#define G_BCM1480_ATRAP_CFG_CNT(x)        _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT)

 
 #define M_BCM1480_ATRAP_CFG_WRITE         _SB_MAKEMASK1(3)
 
 #define M_BCM1480_ATRAP_CFG_WRITE         _SB_MAKEMASK1(3)

-#define M_BCM1480_ATRAP_CFG_ALL                   _SB_MAKEMASK1(4)
-#define M_BCM1480_ATRAP_CFG_INV                   _SB_MAKEMASK1(5)
+#define M_BCM1480_ATRAP_CFG_ALL                   _SB_MAKEMASK1(4)
+#define M_BCM1480_ATRAP_CFG_INV                   _SB_MAKEMASK1(5)

 #define M_BCM1480_ATRAP_CFG_USESRC        _SB_MAKEMASK1(6)
 #define M_BCM1480_ATRAP_CFG_SRCINV        _SB_MAKEMASK1(7)
 
 #define M_BCM1480_ATRAP_CFG_USESRC        _SB_MAKEMASK1(6)
 #define M_BCM1480_ATRAP_CFG_SRCINV        _SB_MAKEMASK1(7)
 

-#define S_BCM1480_ATRAP_CFG_AGENTID     8
-#define M_BCM1480_ATRAP_CFG_AGENTID     _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID)
-#define V_BCM1480_ATRAP_CFG_AGENTID(x)  _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID)
-#define G_BCM1480_ATRAP_CFG_AGENTID(x)  _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID)
+#define S_BCM1480_ATRAP_CFG_AGENTID    8
+#define M_BCM1480_ATRAP_CFG_AGENTID    _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID)
+#define V_BCM1480_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID)
+#define G_BCM1480_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID)

 
 
 
 

-#define K_BCM1480_BUS_AGENT_CPU0            0
-#define K_BCM1480_BUS_AGENT_CPU1            1
-#define K_BCM1480_BUS_AGENT_NC              2
-#define K_BCM1480_BUS_AGENT_IOB             3
-#define K_BCM1480_BUS_AGENT_SCD             4
-#define K_BCM1480_BUS_AGENT_L2C             6
-#define K_BCM1480_BUS_AGENT_MC              7
-#define K_BCM1480_BUS_AGENT_CPU2            8
-#define K_BCM1480_BUS_AGENT_CPU3            9
-#define K_BCM1480_BUS_AGENT_PM              10
+#define K_BCM1480_BUS_AGENT_CPU0           0
+#define K_BCM1480_BUS_AGENT_CPU1           1
+#define K_BCM1480_BUS_AGENT_NC             2
+#define K_BCM1480_BUS_AGENT_IOB                    3
+#define K_BCM1480_BUS_AGENT_SCD                    4
+#define K_BCM1480_BUS_AGENT_L2C                    6
+#define K_BCM1480_BUS_AGENT_MC             7
+#define K_BCM1480_BUS_AGENT_CPU2           8
+#define K_BCM1480_BUS_AGENT_CPU3           9
+#define K_BCM1480_BUS_AGENT_PM             10

 
 

-#define S_BCM1480_ATRAP_CFG_CATTR           12
-#define M_BCM1480_ATRAP_CFG_CATTR           _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR)
-#define V_BCM1480_ATRAP_CFG_CATTR(x)        _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR)
-#define G_BCM1480_ATRAP_CFG_CATTR(x)        _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR)
+#define S_BCM1480_ATRAP_CFG_CATTR          12
+#define M_BCM1480_ATRAP_CFG_CATTR          _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR)
+#define V_BCM1480_ATRAP_CFG_CATTR(x)       _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR)
+#define G_BCM1480_ATRAP_CFG_CATTR(x)       _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR)

 
 #define K_BCM1480_ATRAP_CFG_CATTR_IGNORE    0
 
 #define K_BCM1480_ATRAP_CFG_CATTR_IGNORE    0

-#define K_BCM1480_ATRAP_CFG_CATTR_UNC       1
+#define K_BCM1480_ATRAP_CFG_CATTR_UNC      1

 #define K_BCM1480_ATRAP_CFG_CATTR_NONCOH    2
 #define K_BCM1480_ATRAP_CFG_CATTR_COHERENT  3
 
 #define K_BCM1480_ATRAP_CFG_CATTR_NONCOH    2
 #define K_BCM1480_ATRAP_CFG_CATTR_COHERENT  3
 

-#define M_BCM1480_ATRAP_CFG_CATTRINV        _SB_MAKEMASK1(14)
+#define M_BCM1480_ATRAP_CFG_CATTRINV       _SB_MAKEMASK1(14)

 
 
 /*
 
 
 /*


@@ -381,10 +381,10 @@
 
 #define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN    _SB_MAKEMASK1(25)
 
 
 #define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN    _SB_MAKEMASK1(25)
 

-#define S_BCM1480_SCD_TRSEQ_SWFUNC          26
-#define M_BCM1480_SCD_TRSEQ_SWFUNC          _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC)
-#define V_BCM1480_SCD_TRSEQ_SWFUNC(x)       _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC)
-#define G_BCM1480_SCD_TRSEQ_SWFUNC(x)       _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC)
+#define S_BCM1480_SCD_TRSEQ_SWFUNC         26
+#define M_BCM1480_SCD_TRSEQ_SWFUNC         _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC)
+#define V_BCM1480_SCD_TRSEQ_SWFUNC(x)      _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC)
+#define G_BCM1480_SCD_TRSEQ_SWFUNC(x)      _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC)

 
 /*
  * Trace Control Register (Table 49)
 
 /*
  * Trace Control Register (Table 49)


@@ -394,13 +394,13 @@
  * are defined below.
  */
 
  * are defined below.
  */
 

-#define S_BCM1480_SCD_TRACE_CFG_MODE        16
-#define M_BCM1480_SCD_TRACE_CFG_MODE        _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE)
-#define V_BCM1480_SCD_TRACE_CFG_MODE(x)     _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE)
-#define G_BCM1480_SCD_TRACE_CFG_MODE(x)     _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE)
+#define S_BCM1480_SCD_TRACE_CFG_MODE       16
+#define M_BCM1480_SCD_TRACE_CFG_MODE       _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE)
+#define V_BCM1480_SCD_TRACE_CFG_MODE(x)            _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE)
+#define G_BCM1480_SCD_TRACE_CFG_MODE(x)            _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE)

 
 #define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS  0
 
 #define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS  0

-#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT        1
+#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1

 #define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID   2
 
 #endif /* _BCM1480_SCD_H */
 #define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID   2
 
 #endif /* _BCM1480_SCD_H */

diff --git a/arch/mips/include/asm/sibyte/bigsur.h b/arch/mips/include/asm/sibyte/bigsur.h
index 2d1a26d3436adcd2bddaaff4583030f1dbcc8391..ae29dae41554ce3d7db8130bfa901cac1a5167fa 100644 (file)
--- a/arch/mips/include/asm/sibyte/bigsur.h
+++ b/arch/mips/include/asm/sibyte/bigsur.h
@@ -24,25 +24,25 @@
 #ifdef CONFIG_SIBYTE_BIGSUR
 #define SIBYTE_BOARD_NAME "BCM91x80A/B (BigSur)"
 #define SIBYTE_HAVE_PCMCIA 1
 #ifdef CONFIG_SIBYTE_BIGSUR
 #define SIBYTE_BOARD_NAME "BCM91x80A/B (BigSur)"
 #define SIBYTE_HAVE_PCMCIA 1

-#define SIBYTE_HAVE_IDE    1
+#define SIBYTE_HAVE_IDE           1

 #endif
 
 /* Generic bus chip selects */
 #endif
 
 /* Generic bus chip selects */

-#define LEDS_CS         3
-#define LEDS_PHYS       0x100a0000
+#define LEDS_CS                3
+#define LEDS_PHYS      0x100a0000

 
 #ifdef SIBYTE_HAVE_IDE
 
 #ifdef SIBYTE_HAVE_IDE

-#define IDE_CS          4
-#define IDE_PHYS        0x100b0000
-#define K_GPIO_GB_IDE   4
-#define K_INT_GB_IDE    (K_INT_GPIO_0 + K_GPIO_GB_IDE)
+#define IDE_CS         4
+#define IDE_PHYS       0x100b0000
+#define K_GPIO_GB_IDE  4
+#define K_INT_GB_IDE   (K_INT_GPIO_0 + K_GPIO_GB_IDE)

 #endif
 
 #ifdef SIBYTE_HAVE_PCMCIA
 #endif
 
 #ifdef SIBYTE_HAVE_PCMCIA

-#define PCMCIA_CS       6
-#define PCMCIA_PHYS     0x11000000
+#define PCMCIA_CS      6
+#define PCMCIA_PHYS    0x11000000

 #define K_GPIO_PC_READY 9
 #define K_GPIO_PC_READY 9

-#define K_INT_PC_READY  (K_INT_GPIO_0 + K_GPIO_PC_READY)
+#define K_INT_PC_READY (K_INT_GPIO_0 + K_GPIO_PC_READY)

 #endif
 
 #endif /* __ASM_SIBYTE_BIGSUR_H */
 #endif
 
 #endif /* __ASM_SIBYTE_BIGSUR_H */

diff --git a/arch/mips/include/asm/sibyte/carmel.h b/arch/mips/include/asm/sibyte/carmel.h
index 11cad71323e8ae04aef80a31d9a6126ba207882b..793edba73aa4df24d45989ed8dffc1b29d0b1553 100644 (file)
--- a/arch/mips/include/asm/sibyte/carmel.h
+++ b/arch/mips/include/asm/sibyte/carmel.h
@@ -23,35 +23,35 @@
 
 #define SIBYTE_BOARD_NAME "Carmel"
 
 
 #define SIBYTE_BOARD_NAME "Carmel"
 

-#define GPIO_PHY_INTERRUPT      2
-#define GPIO_NONMASKABLE_INT    3
-#define GPIO_CF_INSERTED        6
-#define GPIO_MONTEREY_RESET     7
-#define GPIO_QUADUART_INT       8
-#define GPIO_CF_INT             9
-#define GPIO_FPGA_CCLK          10
-#define GPIO_FPGA_DOUT          11
-#define GPIO_FPGA_DIN           12
-#define GPIO_FPGA_PGM           13
-#define GPIO_FPGA_DONE          14
-#define GPIO_FPGA_INIT          15
+#define GPIO_PHY_INTERRUPT     2
+#define GPIO_NONMASKABLE_INT   3
+#define GPIO_CF_INSERTED       6
+#define GPIO_MONTEREY_RESET    7
+#define GPIO_QUADUART_INT      8
+#define GPIO_CF_INT            9
+#define GPIO_FPGA_CCLK         10
+#define GPIO_FPGA_DOUT         11
+#define GPIO_FPGA_DIN          12
+#define GPIO_FPGA_PGM          13
+#define GPIO_FPGA_DONE         14
+#define GPIO_FPGA_INIT         15

 
 

-#define LEDS_CS                 2
-#define LEDS_PHYS               0x100C0000
-#define MLEDS_CS                3
-#define MLEDS_PHYS              0x100A0000
-#define UART_CS                 4
-#define UART_PHYS               0x100D0000
-#define ARAVALI_CS              5
-#define ARAVALI_PHYS            0x11000000
-#define IDE_CS                  6
-#define IDE_PHYS                0x100B0000
-#define ARAVALI2_CS             7
-#define ARAVALI2_PHYS           0x100E0000
+#define LEDS_CS                        2
+#define LEDS_PHYS              0x100C0000
+#define MLEDS_CS               3
+#define MLEDS_PHYS             0x100A0000
+#define UART_CS                        4
+#define UART_PHYS              0x100D0000
+#define ARAVALI_CS             5
+#define ARAVALI_PHYS           0x11000000
+#define IDE_CS                 6
+#define IDE_PHYS               0x100B0000
+#define ARAVALI2_CS            7
+#define ARAVALI2_PHYS          0x100E0000

 
 #if defined(CONFIG_SIBYTE_CARMEL)
 
 #if defined(CONFIG_SIBYTE_CARMEL)

-#define K_GPIO_GB_IDE   9
-#define K_INT_GB_IDE    (K_INT_GPIO_0 + K_GPIO_GB_IDE)
+#define K_GPIO_GB_IDE  9
+#define K_INT_GB_IDE   (K_INT_GPIO_0 + K_GPIO_GB_IDE)

 #endif
 
 
 #endif
 
 

diff --git a/arch/mips/include/asm/sibyte/sb1250.h b/arch/mips/include/asm/sibyte/sb1250.h
index 80c1a052662a623693f19e5799817399699efd6e..d45dff9753d30979be0ee563bf038a74b09351d6 100644 (file)
--- a/arch/mips/include/asm/sibyte/sb1250.h
+++ b/arch/mips/include/asm/sibyte/sb1250.h
@@ -27,8 +27,8 @@
 
 #define SB1250_NR_IRQS 64
 
 
 #define SB1250_NR_IRQS 64
 

-#define BCM1480_NR_IRQS                 128
-#define BCM1480_NR_IRQS_HALF            64
+#define BCM1480_NR_IRQS                        128
+#define BCM1480_NR_IRQS_HALF           64

 
 #define SB1250_DUART_MINOR_BASE                64
 
 
 #define SB1250_DUART_MINOR_BASE                64
 

diff --git a/arch/mips/include/asm/sibyte/sb1250_defs.h b/arch/mips/include/asm/sibyte/sb1250_defs.h
index 09365f9111fa74244b0e45cc0a1601d385711a8b..4364eb8d22abbb82c7b949bc7703b90335f89efa 100644 (file)
--- a/arch/mips/include/asm/sibyte/sb1250_defs.h
+++ b/arch/mips/include/asm/sibyte/sb1250_defs.h
@@ -51,15 +51,15 @@
     *
     *  Use like:
     *
     *
     *  Use like:
     *

-    *    #define SIBYTE_HDR_FEATURES   SIBYTE_HDR_FMASK_112x_PASS1
+    *   #define SIBYTE_HDR_FEATURES    SIBYTE_HDR_FMASK_112x_PASS1

     *
     *          Generate defines only for that revision of chip.
     *
     *
     *          Generate defines only for that revision of chip.
     *

-    *    #if SIBYTE_HDR_FEATURE(chip,pass)
+    *   #if SIBYTE_HDR_FEATURE(chip,pass)

     *
     *          True if header features for that revision or later of
     *
     *          True if header features for that revision or later of

-    *          that particular chip type are enabled in SIBYTE_HDR_FEATURES.
-    *          (Use this to bracket #defines for features present in a given
+    *          that particular chip type are enabled in SIBYTE_HDR_FEATURES.
+    *          (Use this to bracket #defines for features present in a given

     *          revision and later.)
     *
     *          Note that there is no implied ordering between chip types.
     *          revision and later.)
     *
     *          Note that there is no implied ordering between chip types.


@@ -69,12 +69,12 @@
     *          SIBYTE_HDR_FEATURE(112x, PASS1) is OK, but
     *          SIBYTE_HDR_FEATURE(1120, pass1) is not (for two reasons).
     *
     *          SIBYTE_HDR_FEATURE(112x, PASS1) is OK, but
     *          SIBYTE_HDR_FEATURE(1120, pass1) is not (for two reasons).
     *

-    *    #if SIBYTE_HDR_FEATURE_UP_TO(chip,pass)
+    *   #if SIBYTE_HDR_FEATURE_UP_TO(chip,pass)

     *
     *          Same as SIBYTE_HDR_FEATURE, but true for the named revision
     *          and earlier revisions of the named chip type.
     *
     *
     *          Same as SIBYTE_HDR_FEATURE, but true for the named revision
     *          and earlier revisions of the named chip type.
     *

-    *    #if SIBYTE_HDR_FEATURE_EXACT(chip,pass)
+    *   #if SIBYTE_HDR_FEATURE_EXACT(chip,pass)

     *
     *          Same as SIBYTE_HDR_FEATURE, but only true for the named
     *          revision of the named chip type.  (Note that this CANNOT
     *
     *          Same as SIBYTE_HDR_FEATURE, but only true for the named
     *          revision of the named chip type.  (Note that this CANNOT


@@ -82,7 +82,7 @@
     *          particular chip/revision.  It will be true any time this
     *          chip/revision is included in SIBYTE_HDR_FEATURES.)
     *
     *          particular chip/revision.  It will be true any time this
     *          chip/revision is included in SIBYTE_HDR_FEATURES.)
     *

-    *    #if SIBYTE_HDR_FEATURE_CHIP(chip)
+    *   #if SIBYTE_HDR_FEATURE_CHIP(chip)

     *
     *          True if header features for (any revision of) that chip type
     *          are enabled in SIBYTE_HDR_FEATURES.  (Use this to bracket
     *
     *          True if header features for (any revision of) that chip type
     *          are enabled in SIBYTE_HDR_FEATURES.  (Use this to bracket


@@ -95,47 +95,47 @@
     *  ordering, so be careful when adding support for new minor revs.
     ********************************************************************* */
 
     *  ordering, so be careful when adding support for new minor revs.
     ********************************************************************* */
 

-#define        SIBYTE_HDR_FMASK_1250_ALL               0x000000ff
-#define        SIBYTE_HDR_FMASK_1250_PASS1             0x00000001
-#define        SIBYTE_HDR_FMASK_1250_PASS2             0x00000002
-#define        SIBYTE_HDR_FMASK_1250_PASS3             0x00000004
+#define SIBYTE_HDR_FMASK_1250_ALL              0x000000ff
+#define SIBYTE_HDR_FMASK_1250_PASS1            0x00000001
+#define SIBYTE_HDR_FMASK_1250_PASS2            0x00000002
+#define SIBYTE_HDR_FMASK_1250_PASS3            0x00000004

 
 

-#define        SIBYTE_HDR_FMASK_112x_ALL               0x00000f00
-#define        SIBYTE_HDR_FMASK_112x_PASS1             0x00000100
+#define SIBYTE_HDR_FMASK_112x_ALL              0x00000f00
+#define SIBYTE_HDR_FMASK_112x_PASS1            0x00000100

 
 #define SIBYTE_HDR_FMASK_1480_ALL              0x0000f000
 #define SIBYTE_HDR_FMASK_1480_PASS1            0x00001000
 #define SIBYTE_HDR_FMASK_1480_PASS2            0x00002000
 
 
 #define SIBYTE_HDR_FMASK_1480_ALL              0x0000f000
 #define SIBYTE_HDR_FMASK_1480_PASS1            0x00001000
 #define SIBYTE_HDR_FMASK_1480_PASS2            0x00002000
 

-/* Bit mask for chip/revision.  (use _ALL for all revisions of a chip).  */
-#define        SIBYTE_HDR_FMASK(chip, pass)                                    \
+/* Bit mask for chip/revision. (use _ALL for all revisions of a chip).  */
+#define SIBYTE_HDR_FMASK(chip, pass)                                   \

     (SIBYTE_HDR_FMASK_ ## chip ## _ ## pass)
     (SIBYTE_HDR_FMASK_ ## chip ## _ ## pass)

-#define        SIBYTE_HDR_FMASK_ALLREVS(chip)                                  \
+#define SIBYTE_HDR_FMASK_ALLREVS(chip)                                 \

     (SIBYTE_HDR_FMASK_ ## chip ## _ALL)
 
 /* Default constant value for all chips, all revisions */
     (SIBYTE_HDR_FMASK_ ## chip ## _ALL)
 
 /* Default constant value for all chips, all revisions */

-#define        SIBYTE_HDR_FMASK_ALL                                            \
+#define SIBYTE_HDR_FMASK_ALL                                           \

     (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL             \
      | SIBYTE_HDR_FMASK_1480_ALL)
 
 /* This one is used for the "original" BCM1250/BCM112x chips.  We use this
    to weed out constants and macros that do not exist on later chips like
     (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL             \
      | SIBYTE_HDR_FMASK_1480_ALL)
 
 /* This one is used for the "original" BCM1250/BCM112x chips.  We use this
    to weed out constants and macros that do not exist on later chips like

-   the BCM1480  */
+   the BCM1480 */

 #define SIBYTE_HDR_FMASK_1250_112x_ALL                                 \
     (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL)
 #define SIBYTE_HDR_FMASK_1250_112x SIBYTE_HDR_FMASK_1250_112x_ALL
 
 #ifndef SIBYTE_HDR_FEATURES
 #define SIBYTE_HDR_FMASK_1250_112x_ALL                                 \
     (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL)
 #define SIBYTE_HDR_FMASK_1250_112x SIBYTE_HDR_FMASK_1250_112x_ALL
 
 #ifndef SIBYTE_HDR_FEATURES

-#define        SIBYTE_HDR_FEATURES                     SIBYTE_HDR_FMASK_ALL
+#define SIBYTE_HDR_FEATURES                    SIBYTE_HDR_FMASK_ALL

 #endif
 
 
 /* Bit mask for revisions of chip exclusively before the named revision.  */
 #endif
 
 
 /* Bit mask for revisions of chip exclusively before the named revision.  */

-#define        SIBYTE_HDR_FMASK_BEFORE(chip, pass)                             \
+#define SIBYTE_HDR_FMASK_BEFORE(chip, pass)                            \

     ((SIBYTE_HDR_FMASK(chip, pass) - 1) & SIBYTE_HDR_FMASK_ALLREVS(chip))
 
     ((SIBYTE_HDR_FMASK(chip, pass) - 1) & SIBYTE_HDR_FMASK_ALLREVS(chip))
 

-/* Bit mask for revisions of chip exclusively after the named revision.  */
-#define        SIBYTE_HDR_FMASK_AFTER(chip, pass)                              \
+/* Bit mask for revisions of chip exclusively after the named revision.         */
+#define SIBYTE_HDR_FMASK_AFTER(chip, pass)                             \

     (~(SIBYTE_HDR_FMASK(chip, pass)                                    \
      | (SIBYTE_HDR_FMASK(chip, pass) - 1)) & SIBYTE_HDR_FMASK_ALLREVS(chip))
 
     (~(SIBYTE_HDR_FMASK(chip, pass)                                    \
      | (SIBYTE_HDR_FMASK(chip, pass) - 1)) & SIBYTE_HDR_FMASK_ALLREVS(chip))
 


@@ -168,38 +168,38 @@
 /*  *********************************************************************
     *  Naming schemes for constants in these files:
     *
 /*  *********************************************************************
     *  Naming schemes for constants in these files:
     *

-    *  M_xxx           MASK constant (identifies bits in a register).
-    *                  For multi-bit fields, all bits in the field will
-    *                  be set.
+    *  M_xxx          MASK constant (identifies bits in a register).
+    *                 For multi-bit fields, all bits in the field will
+    *                 be set.

     *
     *

-    *  K_xxx           "Code" constant (value for data in a multi-bit
-    *                  field).  The value is right justified.
+    *  K_xxx          "Code" constant (value for data in a multi-bit
+    *                 field).  The value is right justified.

     *
     *

-    *  V_xxx           "Value" constant.  This is the same as the
-    *                  corresponding "K_xxx" constant, except it is
-    *                  shifted to the correct position in the register.
+    *  V_xxx          "Value" constant.  This is the same as the
+    *                 corresponding "K_xxx" constant, except it is
+    *                 shifted to the correct position in the register.

     *
     *

-    *  S_xxx           SHIFT constant.  This is the number of bits that
-    *                  a field value (code) needs to be shifted
-    *                  (towards the left) to put the value in the right
-    *                  position for the register.
+    *  S_xxx          SHIFT constant.  This is the number of bits that
+    *                 a field value (code) needs to be shifted
+    *                 (towards the left) to put the value in the right
+    *                 position for the register.

     *
     *

-    *  A_xxx           ADDRESS constant.  This will be a physical
-    *                  address.  Use the PHYS_TO_K1 macro to generate
-    *                  a K1SEG address.
+    *  A_xxx          ADDRESS constant.  This will be a physical
+    *                 address.  Use the PHYS_TO_K1 macro to generate
+    *                 a K1SEG address.

     *
     *

-    *  R_xxx           RELATIVE offset constant.  This is an offset from
-    *                  an A_xxx constant (usually the first register in
-    *                  a group).
+    *  R_xxx          RELATIVE offset constant.  This is an offset from
+    *                 an A_xxx constant (usually the first register in
+    *                 a group).

     *
     *

-    *  G_xxx(X)        GET value.  This macro obtains a multi-bit field
-    *                  from a register, masks it, and shifts it to
-    *                  the bottom of the register (retrieving a K_xxx
-    *                  value, for example).
+    *  G_xxx(X)               GET value.  This macro obtains a multi-bit field
+    *                 from a register, masks it, and shifts it to
+    *                 the bottom of the register (retrieving a K_xxx
+    *                 value, for example).

     *
     *

-    *  V_xxx(X)        VALUE.  This macro computes the value of a
-    *                  K_xxx constant shifted to the correct position
-    *                  in the register.
+    *  V_xxx(X)               VALUE.  This macro computes the value of a
+    *                 K_xxx constant shifted to the correct position
+    *                 in the register.

     ********************************************************************* */
 
 
     ********************************************************************* */
 
 

diff --git a/arch/mips/include/asm/sibyte/sb1250_dma.h b/arch/mips/include/asm/sibyte/sb1250_dma.h
index 6c44dfb528780ad1c5dd9d5c3f94742a4d3bb215..ea81713b78d63830b157bffb28d561f3d752ff28 100644 (file)
--- a/arch/mips/include/asm/sibyte/sb1250_dma.h
+++ b/arch/mips/include/asm/sibyte/sb1250_dma.h
@@ -51,15 +51,15 @@
  */
 
 
  */
 
 

-#define M_DMA_DROP                  _SB_MAKEMASK1(0)
+#define M_DMA_DROP                 _SB_MAKEMASK1(0)

 
 

-#define M_DMA_CHAIN_SEL             _SB_MAKEMASK1(1)
-#define M_DMA_RESERVED1             _SB_MAKEMASK1(2)
+#define M_DMA_CHAIN_SEL                    _SB_MAKEMASK1(1)
+#define M_DMA_RESERVED1                    _SB_MAKEMASK1(2)

 
 #define S_DMA_DESC_TYPE                    _SB_MAKE64(1)
 #define M_DMA_DESC_TYPE                    _SB_MAKEMASK(2, S_DMA_DESC_TYPE)
 
 #define S_DMA_DESC_TYPE                    _SB_MAKE64(1)
 #define M_DMA_DESC_TYPE                    _SB_MAKEMASK(2, S_DMA_DESC_TYPE)

-#define V_DMA_DESC_TYPE(x)          _SB_MAKEVALUE(x, S_DMA_DESC_TYPE)
-#define G_DMA_DESC_TYPE(x)          _SB_GETVALUE(x, S_DMA_DESC_TYPE, M_DMA_DESC_TYPE)
+#define V_DMA_DESC_TYPE(x)         _SB_MAKEVALUE(x, S_DMA_DESC_TYPE)
+#define G_DMA_DESC_TYPE(x)         _SB_GETVALUE(x, S_DMA_DESC_TYPE, M_DMA_DESC_TYPE)

 
 #define K_DMA_DESC_TYPE_RING_AL                0
 #define K_DMA_DESC_TYPE_CHAIN_AL       1
 
 #define K_DMA_DESC_TYPE_RING_AL                0
 #define K_DMA_DESC_TYPE_CHAIN_AL       1


@@ -69,31 +69,31 @@
 #define K_DMA_DESC_TYPE_RING_UAL_RMW   3
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 #define K_DMA_DESC_TYPE_RING_UAL_RMW   3
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 

-#define M_DMA_EOP_INT_EN            _SB_MAKEMASK1(3)
-#define M_DMA_HWM_INT_EN            _SB_MAKEMASK1(4)
-#define M_DMA_LWM_INT_EN            _SB_MAKEMASK1(5)
-#define M_DMA_TBX_EN                _SB_MAKEMASK1(6)
-#define M_DMA_TDX_EN                _SB_MAKEMASK1(7)
+#define M_DMA_EOP_INT_EN           _SB_MAKEMASK1(3)
+#define M_DMA_HWM_INT_EN           _SB_MAKEMASK1(4)
+#define M_DMA_LWM_INT_EN           _SB_MAKEMASK1(5)
+#define M_DMA_TBX_EN               _SB_MAKEMASK1(6)
+#define M_DMA_TDX_EN               _SB_MAKEMASK1(7)

 
 

-#define S_DMA_INT_PKTCNT            _SB_MAKE64(8)
-#define M_DMA_INT_PKTCNT            _SB_MAKEMASK(8, S_DMA_INT_PKTCNT)
-#define V_DMA_INT_PKTCNT(x)         _SB_MAKEVALUE(x, S_DMA_INT_PKTCNT)
-#define G_DMA_INT_PKTCNT(x)         _SB_GETVALUE(x, S_DMA_INT_PKTCNT, M_DMA_INT_PKTCNT)
+#define S_DMA_INT_PKTCNT           _SB_MAKE64(8)
+#define M_DMA_INT_PKTCNT           _SB_MAKEMASK(8, S_DMA_INT_PKTCNT)
+#define V_DMA_INT_PKTCNT(x)        _SB_MAKEVALUE(x, S_DMA_INT_PKTCNT)
+#define G_DMA_INT_PKTCNT(x)        _SB_GETVALUE(x, S_DMA_INT_PKTCNT, M_DMA_INT_PKTCNT)

 
 

-#define S_DMA_RINGSZ                _SB_MAKE64(16)
-#define M_DMA_RINGSZ                _SB_MAKEMASK(16, S_DMA_RINGSZ)
-#define V_DMA_RINGSZ(x)             _SB_MAKEVALUE(x, S_DMA_RINGSZ)
-#define G_DMA_RINGSZ(x)             _SB_GETVALUE(x, S_DMA_RINGSZ, M_DMA_RINGSZ)
+#define S_DMA_RINGSZ               _SB_MAKE64(16)
+#define M_DMA_RINGSZ               _SB_MAKEMASK(16, S_DMA_RINGSZ)
+#define V_DMA_RINGSZ(x)                    _SB_MAKEVALUE(x, S_DMA_RINGSZ)
+#define G_DMA_RINGSZ(x)                    _SB_GETVALUE(x, S_DMA_RINGSZ, M_DMA_RINGSZ)

 
 

-#define S_DMA_HIGH_WATERMARK        _SB_MAKE64(32)
-#define M_DMA_HIGH_WATERMARK        _SB_MAKEMASK(16, S_DMA_HIGH_WATERMARK)
-#define V_DMA_HIGH_WATERMARK(x)     _SB_MAKEVALUE(x, S_DMA_HIGH_WATERMARK)
-#define G_DMA_HIGH_WATERMARK(x)     _SB_GETVALUE(x, S_DMA_HIGH_WATERMARK, M_DMA_HIGH_WATERMARK)
+#define S_DMA_HIGH_WATERMARK       _SB_MAKE64(32)
+#define M_DMA_HIGH_WATERMARK       _SB_MAKEMASK(16, S_DMA_HIGH_WATERMARK)
+#define V_DMA_HIGH_WATERMARK(x)            _SB_MAKEVALUE(x, S_DMA_HIGH_WATERMARK)
+#define G_DMA_HIGH_WATERMARK(x)            _SB_GETVALUE(x, S_DMA_HIGH_WATERMARK, M_DMA_HIGH_WATERMARK)

 
 

-#define S_DMA_LOW_WATERMARK         _SB_MAKE64(48)
-#define M_DMA_LOW_WATERMARK         _SB_MAKEMASK(16, S_DMA_LOW_WATERMARK)
-#define V_DMA_LOW_WATERMARK(x)      _SB_MAKEVALUE(x, S_DMA_LOW_WATERMARK)
-#define G_DMA_LOW_WATERMARK(x)      _SB_GETVALUE(x, S_DMA_LOW_WATERMARK, M_DMA_LOW_WATERMARK)
+#define S_DMA_LOW_WATERMARK        _SB_MAKE64(48)
+#define M_DMA_LOW_WATERMARK        _SB_MAKEMASK(16, S_DMA_LOW_WATERMARK)
+#define V_DMA_LOW_WATERMARK(x)     _SB_MAKEVALUE(x, S_DMA_LOW_WATERMARK)
+#define G_DMA_LOW_WATERMARK(x)     _SB_GETVALUE(x, S_DMA_LOW_WATERMARK, M_DMA_LOW_WATERMARK)

 
 /*
  * Ethernet and Serial DMA Configuration Register 1 (Table 7-5)
 
 /*
  * Ethernet and Serial DMA Configuration Register 1 (Table 7-5)


@@ -103,11 +103,11 @@
  * Registers: DMA_CONFIG1_SER_x_TX
  */
 
  * Registers: DMA_CONFIG1_SER_x_TX
  */
 

-#define M_DMA_HDR_CF_EN             _SB_MAKEMASK1(0)
-#define M_DMA_ASIC_XFR_EN           _SB_MAKEMASK1(1)
-#define M_DMA_PRE_ADDR_EN           _SB_MAKEMASK1(2)
-#define M_DMA_FLOW_CTL_EN           _SB_MAKEMASK1(3)
-#define M_DMA_NO_DSCR_UPDT          _SB_MAKEMASK1(4)
+#define M_DMA_HDR_CF_EN                    _SB_MAKEMASK1(0)
+#define M_DMA_ASIC_XFR_EN          _SB_MAKEMASK1(1)
+#define M_DMA_PRE_ADDR_EN          _SB_MAKEMASK1(2)
+#define M_DMA_FLOW_CTL_EN          _SB_MAKEMASK1(3)
+#define M_DMA_NO_DSCR_UPDT         _SB_MAKEMASK1(4)

 #define M_DMA_L2CA                 _SB_MAKEMASK1(5)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_DMA_L2CA                 _SB_MAKEMASK1(5)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)


@@ -116,37 +116,37 @@
 #define M_DMA_TX_FC_PAUSE_EN       _SB_MAKEMASK1(7)
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 #define M_DMA_TX_FC_PAUSE_EN       _SB_MAKEMASK1(7)
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 

-#define M_DMA_MBZ1                  _SB_MAKEMASK(6, 15)
+#define M_DMA_MBZ1                 _SB_MAKEMASK(6, 15)

 
 

-#define S_DMA_HDR_SIZE              _SB_MAKE64(21)
-#define M_DMA_HDR_SIZE              _SB_MAKEMASK(9, S_DMA_HDR_SIZE)
-#define V_DMA_HDR_SIZE(x)           _SB_MAKEVALUE(x, S_DMA_HDR_SIZE)
-#define G_DMA_HDR_SIZE(x)           _SB_GETVALUE(x, S_DMA_HDR_SIZE, M_DMA_HDR_SIZE)
+#define S_DMA_HDR_SIZE             _SB_MAKE64(21)
+#define M_DMA_HDR_SIZE             _SB_MAKEMASK(9, S_DMA_HDR_SIZE)
+#define V_DMA_HDR_SIZE(x)          _SB_MAKEVALUE(x, S_DMA_HDR_SIZE)
+#define G_DMA_HDR_SIZE(x)          _SB_GETVALUE(x, S_DMA_HDR_SIZE, M_DMA_HDR_SIZE)

 
 

-#define M_DMA_MBZ2                  _SB_MAKEMASK(5, 32)
+#define M_DMA_MBZ2                 _SB_MAKEMASK(5, 32)

 
 

-#define S_DMA_ASICXFR_SIZE          _SB_MAKE64(37)
-#define M_DMA_ASICXFR_SIZE          _SB_MAKEMASK(9, S_DMA_ASICXFR_SIZE)
-#define V_DMA_ASICXFR_SIZE(x)       _SB_MAKEVALUE(x, S_DMA_ASICXFR_SIZE)
-#define G_DMA_ASICXFR_SIZE(x)       _SB_GETVALUE(x, S_DMA_ASICXFR_SIZE, M_DMA_ASICXFR_SIZE)
+#define S_DMA_ASICXFR_SIZE         _SB_MAKE64(37)
+#define M_DMA_ASICXFR_SIZE         _SB_MAKEMASK(9, S_DMA_ASICXFR_SIZE)
+#define V_DMA_ASICXFR_SIZE(x)      _SB_MAKEVALUE(x, S_DMA_ASICXFR_SIZE)
+#define G_DMA_ASICXFR_SIZE(x)      _SB_GETVALUE(x, S_DMA_ASICXFR_SIZE, M_DMA_ASICXFR_SIZE)

 
 

-#define S_DMA_INT_TIMEOUT           _SB_MAKE64(48)
-#define M_DMA_INT_TIMEOUT           _SB_MAKEMASK(16, S_DMA_INT_TIMEOUT)
-#define V_DMA_INT_TIMEOUT(x)        _SB_MAKEVALUE(x, S_DMA_INT_TIMEOUT)
-#define G_DMA_INT_TIMEOUT(x)        _SB_GETVALUE(x, S_DMA_INT_TIMEOUT, M_DMA_INT_TIMEOUT)
+#define S_DMA_INT_TIMEOUT          _SB_MAKE64(48)
+#define M_DMA_INT_TIMEOUT          _SB_MAKEMASK(16, S_DMA_INT_TIMEOUT)
+#define V_DMA_INT_TIMEOUT(x)       _SB_MAKEVALUE(x, S_DMA_INT_TIMEOUT)
+#define G_DMA_INT_TIMEOUT(x)       _SB_GETVALUE(x, S_DMA_INT_TIMEOUT, M_DMA_INT_TIMEOUT)

 
 /*
  * Ethernet and Serial DMA Descriptor base address (Table 7-6)
  */
 
 
 /*
  * Ethernet and Serial DMA Descriptor base address (Table 7-6)
  */
 

-#define M_DMA_DSCRBASE_MBZ          _SB_MAKEMASK(4, 0)
+#define M_DMA_DSCRBASE_MBZ         _SB_MAKEMASK(4, 0)

 
 
 /*
  * ASIC Mode Base Address (Table 7-7)
  */
 
 
 
 /*
  * ASIC Mode Base Address (Table 7-7)
  */
 

-#define M_DMA_ASIC_BASE_MBZ         _SB_MAKEMASK(20, 0)
+#define M_DMA_ASIC_BASE_MBZ        _SB_MAKEMASK(20, 0)

 
 /*
  * DMA Descriptor Count Registers (Table 7-8)
 
 /*
  * DMA Descriptor Count Registers (Table 7-8)


@@ -159,10 +159,10 @@
  * Current Descriptor Address Register (Table 7-11)
  */
 
  * Current Descriptor Address Register (Table 7-11)
  */
 

-#define S_DMA_CURDSCR_ADDR          _SB_MAKE64(0)
-#define M_DMA_CURDSCR_ADDR          _SB_MAKEMASK(40, S_DMA_CURDSCR_ADDR)
-#define S_DMA_CURDSCR_COUNT         _SB_MAKE64(40)
-#define M_DMA_CURDSCR_COUNT         _SB_MAKEMASK(16, S_DMA_CURDSCR_COUNT)
+#define S_DMA_CURDSCR_ADDR         _SB_MAKE64(0)
+#define M_DMA_CURDSCR_ADDR         _SB_MAKEMASK(40, S_DMA_CURDSCR_ADDR)
+#define S_DMA_CURDSCR_COUNT        _SB_MAKE64(40)
+#define M_DMA_CURDSCR_COUNT        _SB_MAKEMASK(16, S_DMA_CURDSCR_COUNT)

 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_DMA_TX_CH_PAUSE_ON       _SB_MAKEMASK1(56)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_DMA_TX_CH_PAUSE_ON       _SB_MAKEMASK1(56)


@@ -172,13 +172,13 @@
  * Receive Packet Drop Registers
  */
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
  * Receive Packet Drop Registers
  */
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)

-#define S_DMA_OODLOST_RX           _SB_MAKE64(0)
-#define M_DMA_OODLOST_RX           _SB_MAKEMASK(16, S_DMA_OODLOST_RX)
-#define G_DMA_OODLOST_RX(x)        _SB_GETVALUE(x, S_DMA_OODLOST_RX, M_DMA_OODLOST_RX)
+#define S_DMA_OODLOST_RX          _SB_MAKE64(0)
+#define M_DMA_OODLOST_RX          _SB_MAKEMASK(16, S_DMA_OODLOST_RX)
+#define G_DMA_OODLOST_RX(x)       _SB_GETVALUE(x, S_DMA_OODLOST_RX, M_DMA_OODLOST_RX)

 
 

-#define S_DMA_EOP_COUNT_RX         _SB_MAKE64(16)
-#define M_DMA_EOP_COUNT_RX         _SB_MAKEMASK(8, S_DMA_EOP_COUNT_RX)
-#define G_DMA_EOP_COUNT_RX(x)      _SB_GETVALUE(x, S_DMA_EOP_COUNT_RX, M_DMA_EOP_COUNT_RX)
+#define S_DMA_EOP_COUNT_RX        _SB_MAKE64(16)
+#define M_DMA_EOP_COUNT_RX        _SB_MAKEMASK(8, S_DMA_EOP_COUNT_RX)
+#define G_DMA_EOP_COUNT_RX(x)     _SB_GETVALUE(x, S_DMA_EOP_COUNT_RX, M_DMA_EOP_COUNT_RX)

 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 /*  *********************************************************************
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 /*  *********************************************************************


@@ -189,26 +189,26 @@
  * Descriptor doubleword "A"  (Table 7-12)
  */
 
  * Descriptor doubleword "A"  (Table 7-12)
  */
 

-#define S_DMA_DSCRA_OFFSET          _SB_MAKE64(0)
-#define M_DMA_DSCRA_OFFSET          _SB_MAKEMASK(5, S_DMA_DSCRA_OFFSET)
-#define V_DMA_DSCRA_OFFSET(x)       _SB_MAKEVALUE(x, S_DMA_DSCRA_OFFSET)
-#define G_DMA_DSCRA_OFFSET(x)       _SB_GETVALUE(x, S_DMA_DSCRA_OFFSET, M_DMA_DSCRA_OFFSET)
+#define S_DMA_DSCRA_OFFSET         _SB_MAKE64(0)
+#define M_DMA_DSCRA_OFFSET         _SB_MAKEMASK(5, S_DMA_DSCRA_OFFSET)
+#define V_DMA_DSCRA_OFFSET(x)      _SB_MAKEVALUE(x, S_DMA_DSCRA_OFFSET)
+#define G_DMA_DSCRA_OFFSET(x)      _SB_GETVALUE(x, S_DMA_DSCRA_OFFSET, M_DMA_DSCRA_OFFSET)

 
 /* Note: Don't shift the address over, just mask it with the mask below */
 
 /* Note: Don't shift the address over, just mask it with the mask below */

-#define S_DMA_DSCRA_A_ADDR          _SB_MAKE64(5)
-#define M_DMA_DSCRA_A_ADDR          _SB_MAKEMASK(35, S_DMA_DSCRA_A_ADDR)
+#define S_DMA_DSCRA_A_ADDR         _SB_MAKE64(5)
+#define M_DMA_DSCRA_A_ADDR         _SB_MAKEMASK(35, S_DMA_DSCRA_A_ADDR)

 
 #define M_DMA_DSCRA_A_ADDR_OFFSET   (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 
 #define M_DMA_DSCRA_A_ADDR_OFFSET   (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)

-#define S_DMA_DSCRA_A_ADDR_UA        _SB_MAKE64(0)
-#define M_DMA_DSCRA_A_ADDR_UA        _SB_MAKEMASK(40, S_DMA_DSCRA_A_ADDR_UA)
+#define S_DMA_DSCRA_A_ADDR_UA       _SB_MAKE64(0)
+#define M_DMA_DSCRA_A_ADDR_UA       _SB_MAKEMASK(40, S_DMA_DSCRA_A_ADDR_UA)

 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 

-#define S_DMA_DSCRA_A_SIZE          _SB_MAKE64(40)
-#define M_DMA_DSCRA_A_SIZE          _SB_MAKEMASK(9, S_DMA_DSCRA_A_SIZE)
-#define V_DMA_DSCRA_A_SIZE(x)       _SB_MAKEVALUE(x, S_DMA_DSCRA_A_SIZE)
-#define G_DMA_DSCRA_A_SIZE(x)       _SB_GETVALUE(x, S_DMA_DSCRA_A_SIZE, M_DMA_DSCRA_A_SIZE)
+#define S_DMA_DSCRA_A_SIZE         _SB_MAKE64(40)
+#define M_DMA_DSCRA_A_SIZE         _SB_MAKEMASK(9, S_DMA_DSCRA_A_SIZE)
+#define V_DMA_DSCRA_A_SIZE(x)      _SB_MAKEVALUE(x, S_DMA_DSCRA_A_SIZE)
+#define G_DMA_DSCRA_A_SIZE(x)      _SB_GETVALUE(x, S_DMA_DSCRA_A_SIZE, M_DMA_DSCRA_A_SIZE)

 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_DMA_DSCRA_DSCR_CNT       _SB_MAKE64(40)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_DMA_DSCRA_DSCR_CNT       _SB_MAKE64(40)


@@ -216,43 +216,43 @@
 #define G_DMA_DSCRA_DSCR_CNT(x)            _SB_GETVALUE(x, S_DMA_DSCRA_DSCR_CNT, M_DMA_DSCRA_DSCR_CNT)
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 #define G_DMA_DSCRA_DSCR_CNT(x)            _SB_GETVALUE(x, S_DMA_DSCRA_DSCR_CNT, M_DMA_DSCRA_DSCR_CNT)
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 

-#define M_DMA_DSCRA_INTERRUPT       _SB_MAKEMASK1(49)
+#define M_DMA_DSCRA_INTERRUPT      _SB_MAKEMASK1(49)

 #define M_DMA_DSCRA_OFFSETB        _SB_MAKEMASK1(50)
 
 #define M_DMA_DSCRA_OFFSETB        _SB_MAKEMASK1(50)
 

-#define S_DMA_DSCRA_STATUS          _SB_MAKE64(51)
-#define M_DMA_DSCRA_STATUS          _SB_MAKEMASK(13, S_DMA_DSCRA_STATUS)
-#define V_DMA_DSCRA_STATUS(x)       _SB_MAKEVALUE(x, S_DMA_DSCRA_STATUS)
-#define G_DMA_DSCRA_STATUS(x)       _SB_GETVALUE(x, S_DMA_DSCRA_STATUS, M_DMA_DSCRA_STATUS)
+#define S_DMA_DSCRA_STATUS         _SB_MAKE64(51)
+#define M_DMA_DSCRA_STATUS         _SB_MAKEMASK(13, S_DMA_DSCRA_STATUS)
+#define V_DMA_DSCRA_STATUS(x)      _SB_MAKEVALUE(x, S_DMA_DSCRA_STATUS)
+#define G_DMA_DSCRA_STATUS(x)      _SB_GETVALUE(x, S_DMA_DSCRA_STATUS, M_DMA_DSCRA_STATUS)

 
 /*
  * Descriptor doubleword "B"  (Table 7-13)
  */
 
 
 
 /*
  * Descriptor doubleword "B"  (Table 7-13)
  */
 
 

-#define S_DMA_DSCRB_OPTIONS         _SB_MAKE64(0)
-#define M_DMA_DSCRB_OPTIONS         _SB_MAKEMASK(4, S_DMA_DSCRB_OPTIONS)
-#define V_DMA_DSCRB_OPTIONS(x)      _SB_MAKEVALUE(x, S_DMA_DSCRB_OPTIONS)
-#define G_DMA_DSCRB_OPTIONS(x)      _SB_GETVALUE(x, S_DMA_DSCRB_OPTIONS, M_DMA_DSCRB_OPTIONS)
+#define S_DMA_DSCRB_OPTIONS        _SB_MAKE64(0)
+#define M_DMA_DSCRB_OPTIONS        _SB_MAKEMASK(4, S_DMA_DSCRB_OPTIONS)
+#define V_DMA_DSCRB_OPTIONS(x)     _SB_MAKEVALUE(x, S_DMA_DSCRB_OPTIONS)
+#define G_DMA_DSCRB_OPTIONS(x)     _SB_GETVALUE(x, S_DMA_DSCRB_OPTIONS, M_DMA_DSCRB_OPTIONS)

 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)

-#define S_DMA_DSCRB_A_SIZE        _SB_MAKE64(8)
-#define M_DMA_DSCRB_A_SIZE        _SB_MAKEMASK(14, S_DMA_DSCRB_A_SIZE)
-#define V_DMA_DSCRB_A_SIZE(x)     _SB_MAKEVALUE(x, S_DMA_DSCRB_A_SIZE)
-#define G_DMA_DSCRB_A_SIZE(x)     _SB_GETVALUE(x, S_DMA_DSCRB_A_SIZE, M_DMA_DSCRB_A_SIZE)
+#define S_DMA_DSCRB_A_SIZE       _SB_MAKE64(8)
+#define M_DMA_DSCRB_A_SIZE       _SB_MAKEMASK(14, S_DMA_DSCRB_A_SIZE)
+#define V_DMA_DSCRB_A_SIZE(x)    _SB_MAKEVALUE(x, S_DMA_DSCRB_A_SIZE)
+#define G_DMA_DSCRB_A_SIZE(x)    _SB_GETVALUE(x, S_DMA_DSCRB_A_SIZE, M_DMA_DSCRB_A_SIZE)

 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 

-#define R_DMA_DSCRB_ADDR            _SB_MAKE64(0x10)
+#define R_DMA_DSCRB_ADDR           _SB_MAKE64(0x10)

 
 /* Note: Don't shift the address over, just mask it with the mask below */
 
 /* Note: Don't shift the address over, just mask it with the mask below */

-#define S_DMA_DSCRB_B_ADDR          _SB_MAKE64(5)
-#define M_DMA_DSCRB_B_ADDR          _SB_MAKEMASK(35, S_DMA_DSCRB_B_ADDR)
+#define S_DMA_DSCRB_B_ADDR         _SB_MAKE64(5)
+#define M_DMA_DSCRB_B_ADDR         _SB_MAKEMASK(35, S_DMA_DSCRB_B_ADDR)

 
 

-#define S_DMA_DSCRB_B_SIZE          _SB_MAKE64(40)
-#define M_DMA_DSCRB_B_SIZE          _SB_MAKEMASK(9, S_DMA_DSCRB_B_SIZE)
-#define V_DMA_DSCRB_B_SIZE(x)       _SB_MAKEVALUE(x, S_DMA_DSCRB_B_SIZE)
-#define G_DMA_DSCRB_B_SIZE(x)       _SB_GETVALUE(x, S_DMA_DSCRB_B_SIZE, M_DMA_DSCRB_B_SIZE)
+#define S_DMA_DSCRB_B_SIZE         _SB_MAKE64(40)
+#define M_DMA_DSCRB_B_SIZE         _SB_MAKEMASK(9, S_DMA_DSCRB_B_SIZE)
+#define V_DMA_DSCRB_B_SIZE(x)      _SB_MAKEVALUE(x, S_DMA_DSCRB_B_SIZE)
+#define G_DMA_DSCRB_B_SIZE(x)      _SB_GETVALUE(x, S_DMA_DSCRB_B_SIZE, M_DMA_DSCRB_B_SIZE)

 
 

-#define M_DMA_DSCRB_B_VALID         _SB_MAKEMASK1(49)
+#define M_DMA_DSCRB_B_VALID        _SB_MAKEMASK1(49)

 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKE64(48)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define S_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKE64(48)


@@ -261,24 +261,24 @@
 #define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB, M_DMA_DSCRB_PKT_SIZE_MSB)
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 #define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB, M_DMA_DSCRB_PKT_SIZE_MSB)
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 

-#define S_DMA_DSCRB_PKT_SIZE        _SB_MAKE64(50)
-#define M_DMA_DSCRB_PKT_SIZE        _SB_MAKEMASK(14, S_DMA_DSCRB_PKT_SIZE)
-#define V_DMA_DSCRB_PKT_SIZE(x)     _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE)
-#define G_DMA_DSCRB_PKT_SIZE(x)     _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE, M_DMA_DSCRB_PKT_SIZE)
+#define S_DMA_DSCRB_PKT_SIZE       _SB_MAKE64(50)
+#define M_DMA_DSCRB_PKT_SIZE       _SB_MAKEMASK(14, S_DMA_DSCRB_PKT_SIZE)
+#define V_DMA_DSCRB_PKT_SIZE(x)            _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE)
+#define G_DMA_DSCRB_PKT_SIZE(x)            _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE, M_DMA_DSCRB_PKT_SIZE)

 
 /*
  * from pass2 some bits in dscr_b are also used for rx status
  */
 
 /*
  * from pass2 some bits in dscr_b are also used for rx status
  */

-#define S_DMA_DSCRB_STATUS          _SB_MAKE64(0)
-#define M_DMA_DSCRB_STATUS          _SB_MAKEMASK(1, S_DMA_DSCRB_STATUS)
-#define V_DMA_DSCRB_STATUS(x)       _SB_MAKEVALUE(x, S_DMA_DSCRB_STATUS)
-#define G_DMA_DSCRB_STATUS(x)       _SB_GETVALUE(x, S_DMA_DSCRB_STATUS, M_DMA_DSCRB_STATUS)
+#define S_DMA_DSCRB_STATUS         _SB_MAKE64(0)
+#define M_DMA_DSCRB_STATUS         _SB_MAKEMASK(1, S_DMA_DSCRB_STATUS)
+#define V_DMA_DSCRB_STATUS(x)      _SB_MAKEVALUE(x, S_DMA_DSCRB_STATUS)
+#define G_DMA_DSCRB_STATUS(x)      _SB_GETVALUE(x, S_DMA_DSCRB_STATUS, M_DMA_DSCRB_STATUS)

 
 /*
  * Ethernet Descriptor Status Bits (Table 7-15)
  */
 
 
 /*
  * Ethernet Descriptor Status Bits (Table 7-15)
  */
 

-#define M_DMA_ETHRX_BADIP4CS        _SB_MAKEMASK1(51)
+#define M_DMA_ETHRX_BADIP4CS       _SB_MAKEMASK1(51)

 #define M_DMA_ETHRX_DSCRERR        _SB_MAKEMASK1(52)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_DMA_ETHRX_DSCRERR        _SB_MAKEMASK1(52)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)


@@ -292,70 +292,70 @@
 #define M_DMA_ETH_CRC_FLAG     _SB_MAKEMASK1(2)
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 #define M_DMA_ETH_CRC_FLAG     _SB_MAKEMASK1(2)
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 

-#define S_DMA_ETHRX_RXCH            53
-#define M_DMA_ETHRX_RXCH            _SB_MAKEMASK(2, S_DMA_ETHRX_RXCH)
-#define V_DMA_ETHRX_RXCH(x)         _SB_MAKEVALUE(x, S_DMA_ETHRX_RXCH)
-#define G_DMA_ETHRX_RXCH(x)         _SB_GETVALUE(x, S_DMA_ETHRX_RXCH, M_DMA_ETHRX_RXCH)
+#define S_DMA_ETHRX_RXCH           53
+#define M_DMA_ETHRX_RXCH           _SB_MAKEMASK(2, S_DMA_ETHRX_RXCH)
+#define V_DMA_ETHRX_RXCH(x)        _SB_MAKEVALUE(x, S_DMA_ETHRX_RXCH)
+#define G_DMA_ETHRX_RXCH(x)        _SB_GETVALUE(x, S_DMA_ETHRX_RXCH, M_DMA_ETHRX_RXCH)

 
 

-#define S_DMA_ETHRX_PKTTYPE         55
-#define M_DMA_ETHRX_PKTTYPE         _SB_MAKEMASK(3, S_DMA_ETHRX_PKTTYPE)
-#define V_DMA_ETHRX_PKTTYPE(x)      _SB_MAKEVALUE(x, S_DMA_ETHRX_PKTTYPE)
-#define G_DMA_ETHRX_PKTTYPE(x)      _SB_GETVALUE(x, S_DMA_ETHRX_PKTTYPE, M_DMA_ETHRX_PKTTYPE)
+#define S_DMA_ETHRX_PKTTYPE        55
+#define M_DMA_ETHRX_PKTTYPE        _SB_MAKEMASK(3, S_DMA_ETHRX_PKTTYPE)
+#define V_DMA_ETHRX_PKTTYPE(x)     _SB_MAKEVALUE(x, S_DMA_ETHRX_PKTTYPE)
+#define G_DMA_ETHRX_PKTTYPE(x)     _SB_GETVALUE(x, S_DMA_ETHRX_PKTTYPE, M_DMA_ETHRX_PKTTYPE)

 
 #define K_DMA_ETHRX_PKTTYPE_IPV4    0
 #define K_DMA_ETHRX_PKTTYPE_ARPV4   1
 
 #define K_DMA_ETHRX_PKTTYPE_IPV4    0
 #define K_DMA_ETHRX_PKTTYPE_ARPV4   1

-#define K_DMA_ETHRX_PKTTYPE_802     2
+#define K_DMA_ETHRX_PKTTYPE_802            2

 #define K_DMA_ETHRX_PKTTYPE_OTHER   3
 #define K_DMA_ETHRX_PKTTYPE_USER0   4
 #define K_DMA_ETHRX_PKTTYPE_USER1   5
 #define K_DMA_ETHRX_PKTTYPE_USER2   6
 #define K_DMA_ETHRX_PKTTYPE_USER3   7
 
 #define K_DMA_ETHRX_PKTTYPE_OTHER   3
 #define K_DMA_ETHRX_PKTTYPE_USER0   4
 #define K_DMA_ETHRX_PKTTYPE_USER1   5
 #define K_DMA_ETHRX_PKTTYPE_USER2   6
 #define K_DMA_ETHRX_PKTTYPE_USER3   7
 

-#define M_DMA_ETHRX_MATCH_HASH      _SB_MAKEMASK1(58)
-#define M_DMA_ETHRX_MATCH_EXACT     _SB_MAKEMASK1(59)
-#define M_DMA_ETHRX_BCAST           _SB_MAKEMASK1(60)
-#define M_DMA_ETHRX_MCAST           _SB_MAKEMASK1(61)
-#define M_DMA_ETHRX_BAD                    _SB_MAKEMASK1(62)
-#define M_DMA_ETHRX_SOP             _SB_MAKEMASK1(63)
+#define M_DMA_ETHRX_MATCH_HASH     _SB_MAKEMASK1(58)
+#define M_DMA_ETHRX_MATCH_EXACT            _SB_MAKEMASK1(59)
+#define M_DMA_ETHRX_BCAST          _SB_MAKEMASK1(60)
+#define M_DMA_ETHRX_MCAST          _SB_MAKEMASK1(61)
+#define M_DMA_ETHRX_BAD                    _SB_MAKEMASK1(62)
+#define M_DMA_ETHRX_SOP                    _SB_MAKEMASK1(63)

 
 /*
  * Ethernet Transmit Status Bits (Table 7-16)
  */
 
 
 /*
  * Ethernet Transmit Status Bits (Table 7-16)
  */
 

-#define M_DMA_ETHTX_SOP                    _SB_MAKEMASK1(63)
+#define M_DMA_ETHTX_SOP                    _SB_MAKEMASK1(63)

 
 /*
  * Ethernet Transmit Options (Table 7-17)
  */
 
 
 /*
  * Ethernet Transmit Options (Table 7-17)
  */
 

-#define K_DMA_ETHTX_NOTSOP          _SB_MAKE64(0x00)
-#define K_DMA_ETHTX_APPENDCRC       _SB_MAKE64(0x01)
-#define K_DMA_ETHTX_REPLACECRC      _SB_MAKE64(0x02)
+#define K_DMA_ETHTX_NOTSOP         _SB_MAKE64(0x00)
+#define K_DMA_ETHTX_APPENDCRC      _SB_MAKE64(0x01)
+#define K_DMA_ETHTX_REPLACECRC     _SB_MAKE64(0x02)

 #define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03)
 #define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04)
 #define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05)
 #define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6)
 #define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03)
 #define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04)
 #define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05)
 #define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6)

-#define K_DMA_ETHTX_NOMODS          _SB_MAKE64(0x07)
-#define K_DMA_ETHTX_RESERVED1       _SB_MAKE64(0x08)
+#define K_DMA_ETHTX_NOMODS         _SB_MAKE64(0x07)
+#define K_DMA_ETHTX_RESERVED1      _SB_MAKE64(0x08)

 #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09)
 #define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A)
 #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B)
 #define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C)
 #define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D)
 #define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E)
 #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09)
 #define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A)
 #define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B)
 #define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C)
 #define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D)
 #define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E)

-#define K_DMA_ETHTX_RESERVED2       _SB_MAKE64(0x0F)
+#define K_DMA_ETHTX_RESERVED2      _SB_MAKE64(0x0F)

 
 /*
  * Serial Receive Options (Table 7-18)
  */
 
 /*
  * Serial Receive Options (Table 7-18)
  */

-#define M_DMA_SERRX_CRC_ERROR       _SB_MAKEMASK1(56)
-#define M_DMA_SERRX_ABORT           _SB_MAKEMASK1(57)
-#define M_DMA_SERRX_OCTET_ERROR     _SB_MAKEMASK1(58)
+#define M_DMA_SERRX_CRC_ERROR      _SB_MAKEMASK1(56)
+#define M_DMA_SERRX_ABORT          _SB_MAKEMASK1(57)
+#define M_DMA_SERRX_OCTET_ERROR            _SB_MAKEMASK1(58)

 #define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59)
 #define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60)
 #define M_DMA_SERRX_OVERRUN_ERROR   _SB_MAKEMASK1(61)
 #define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59)
 #define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60)
 #define M_DMA_SERRX_OVERRUN_ERROR   _SB_MAKEMASK1(61)

-#define M_DMA_SERRX_GOOD            _SB_MAKEMASK1(62)
-#define M_DMA_SERRX_SOP             _SB_MAKEMASK1(63)
+#define M_DMA_SERRX_GOOD           _SB_MAKEMASK1(62)
+#define M_DMA_SERRX_SOP                    _SB_MAKEMASK1(63)

 
 /*
  * Serial Transmit Status Bits (Table 7-20)
 
 /*
  * Serial Transmit Status Bits (Table 7-20)


@@ -367,10 +367,10 @@
  * Serial Transmit Options (Table 7-21)
  */
 
  * Serial Transmit Options (Table 7-21)
  */
 

-#define K_DMA_SERTX_RESERVED        _SB_MAKEMASK1(0)
-#define K_DMA_SERTX_APPENDCRC       _SB_MAKEMASK1(1)
-#define K_DMA_SERTX_APPENDPAD       _SB_MAKEMASK1(2)
-#define K_DMA_SERTX_ABORT           _SB_MAKEMASK1(3)
+#define K_DMA_SERTX_RESERVED       _SB_MAKEMASK1(0)
+#define K_DMA_SERTX_APPENDCRC      _SB_MAKEMASK1(1)
+#define K_DMA_SERTX_APPENDPAD      _SB_MAKEMASK1(2)
+#define K_DMA_SERTX_ABORT          _SB_MAKEMASK1(3)

 
 
 /*  *********************************************************************
 
 
 /*  *********************************************************************


@@ -385,19 +385,19 @@
  * Register: DM_DSCR_BASE_3
  */
 
  * Register: DM_DSCR_BASE_3
  */
 

-#define M_DM_DSCR_BASE_MBZ          _SB_MAKEMASK(4, 0)
+#define M_DM_DSCR_BASE_MBZ         _SB_MAKEMASK(4, 0)

 
 /*  Note: Just mask the base address and then OR it in. */
 
 /*  Note: Just mask the base address and then OR it in. */

-#define S_DM_DSCR_BASE_ADDR         _SB_MAKE64(4)
-#define M_DM_DSCR_BASE_ADDR         _SB_MAKEMASK(36, S_DM_DSCR_BASE_ADDR)
+#define S_DM_DSCR_BASE_ADDR        _SB_MAKE64(4)
+#define M_DM_DSCR_BASE_ADDR        _SB_MAKEMASK(36, S_DM_DSCR_BASE_ADDR)

 
 

-#define S_DM_DSCR_BASE_RINGSZ       _SB_MAKE64(40)
-#define M_DM_DSCR_BASE_RINGSZ       _SB_MAKEMASK(16, S_DM_DSCR_BASE_RINGSZ)
+#define S_DM_DSCR_BASE_RINGSZ      _SB_MAKE64(40)
+#define M_DM_DSCR_BASE_RINGSZ      _SB_MAKEMASK(16, S_DM_DSCR_BASE_RINGSZ)

 #define V_DM_DSCR_BASE_RINGSZ(x)    _SB_MAKEVALUE(x, S_DM_DSCR_BASE_RINGSZ)
 #define G_DM_DSCR_BASE_RINGSZ(x)    _SB_GETVALUE(x, S_DM_DSCR_BASE_RINGSZ, M_DM_DSCR_BASE_RINGSZ)
 
 #define V_DM_DSCR_BASE_RINGSZ(x)    _SB_MAKEVALUE(x, S_DM_DSCR_BASE_RINGSZ)
 #define G_DM_DSCR_BASE_RINGSZ(x)    _SB_GETVALUE(x, S_DM_DSCR_BASE_RINGSZ, M_DM_DSCR_BASE_RINGSZ)
 

-#define S_DM_DSCR_BASE_PRIORITY     _SB_MAKE64(56)
-#define M_DM_DSCR_BASE_PRIORITY     _SB_MAKEMASK(3, S_DM_DSCR_BASE_PRIORITY)
+#define S_DM_DSCR_BASE_PRIORITY            _SB_MAKE64(56)
+#define M_DM_DSCR_BASE_PRIORITY            _SB_MAKEMASK(3, S_DM_DSCR_BASE_PRIORITY)

 #define V_DM_DSCR_BASE_PRIORITY(x)  _SB_MAKEVALUE(x, S_DM_DSCR_BASE_PRIORITY)
 #define G_DM_DSCR_BASE_PRIORITY(x)  _SB_GETVALUE(x, S_DM_DSCR_BASE_PRIORITY, M_DM_DSCR_BASE_PRIORITY)
 
 #define V_DM_DSCR_BASE_PRIORITY(x)  _SB_MAKEVALUE(x, S_DM_DSCR_BASE_PRIORITY)
 #define G_DM_DSCR_BASE_PRIORITY(x)  _SB_GETVALUE(x, S_DM_DSCR_BASE_PRIORITY, M_DM_DSCR_BASE_PRIORITY)
 


@@ -407,12 +407,12 @@
 #define K_DM_DSCR_BASE_PRIORITY_8   3
 #define K_DM_DSCR_BASE_PRIORITY_16  4
 
 #define K_DM_DSCR_BASE_PRIORITY_8   3
 #define K_DM_DSCR_BASE_PRIORITY_16  4
 

-#define M_DM_DSCR_BASE_ACTIVE       _SB_MAKEMASK1(59)
+#define M_DM_DSCR_BASE_ACTIVE      _SB_MAKEMASK1(59)

 #define M_DM_DSCR_BASE_INTERRUPT    _SB_MAKEMASK1(60)
 #define M_DM_DSCR_BASE_INTERRUPT    _SB_MAKEMASK1(60)

-#define M_DM_DSCR_BASE_RESET        _SB_MAKEMASK1(61)  /* write register */
-#define M_DM_DSCR_BASE_ERROR        _SB_MAKEMASK1(61)  /* read register */
-#define M_DM_DSCR_BASE_ABORT        _SB_MAKEMASK1(62)
-#define M_DM_DSCR_BASE_ENABL        _SB_MAKEMASK1(63)
+#define M_DM_DSCR_BASE_RESET       _SB_MAKEMASK1(61)   /* write register */
+#define M_DM_DSCR_BASE_ERROR       _SB_MAKEMASK1(61)   /* read register */
+#define M_DM_DSCR_BASE_ABORT       _SB_MAKEMASK1(62)
+#define M_DM_DSCR_BASE_ENABL       _SB_MAKEMASK1(63)

 
 /*
  * Data Mover Descriptor Count Register (Table 7-25)
 
 /*
  * Data Mover Descriptor Count Register (Table 7-25)


@@ -428,14 +428,14 @@
  * Register: DM_CUR_DSCR_ADDR_3
  */
 
  * Register: DM_CUR_DSCR_ADDR_3
  */
 

-#define S_DM_CUR_DSCR_DSCR_ADDR     _SB_MAKE64(0)
-#define M_DM_CUR_DSCR_DSCR_ADDR     _SB_MAKEMASK(40, S_DM_CUR_DSCR_DSCR_ADDR)
+#define S_DM_CUR_DSCR_DSCR_ADDR            _SB_MAKE64(0)
+#define M_DM_CUR_DSCR_DSCR_ADDR            _SB_MAKEMASK(40, S_DM_CUR_DSCR_DSCR_ADDR)

 
 #define S_DM_CUR_DSCR_DSCR_COUNT    _SB_MAKE64(48)
 #define M_DM_CUR_DSCR_DSCR_COUNT    _SB_MAKEMASK(16, S_DM_CUR_DSCR_DSCR_COUNT)
 #define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT)
 #define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT,\
 
 #define S_DM_CUR_DSCR_DSCR_COUNT    _SB_MAKE64(48)
 #define M_DM_CUR_DSCR_DSCR_COUNT    _SB_MAKEMASK(16, S_DM_CUR_DSCR_DSCR_COUNT)
 #define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT)
 #define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT,\

-                                     M_DM_CUR_DSCR_DSCR_COUNT)
+                                    M_DM_CUR_DSCR_DSCR_COUNT)

 
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)


@@ -450,15 +450,15 @@
 #define M_DM_PARTIAL_CRC_PARTIAL      _SB_MAKEMASK(32, S_DM_PARTIAL_CRC_PARTIAL)
 #define V_DM_PARTIAL_CRC_PARTIAL(r)   _SB_MAKEVALUE(r, S_DM_PARTIAL_CRC_PARTIAL)
 #define G_DM_PARTIAL_CRC_PARTIAL(r)   _SB_GETVALUE(r, S_DM_PARTIAL_CRC_PARTIAL,\
 #define M_DM_PARTIAL_CRC_PARTIAL      _SB_MAKEMASK(32, S_DM_PARTIAL_CRC_PARTIAL)
 #define V_DM_PARTIAL_CRC_PARTIAL(r)   _SB_MAKEVALUE(r, S_DM_PARTIAL_CRC_PARTIAL)
 #define G_DM_PARTIAL_CRC_PARTIAL(r)   _SB_GETVALUE(r, S_DM_PARTIAL_CRC_PARTIAL,\

-                                       M_DM_PARTIAL_CRC_PARTIAL)
+                                      M_DM_PARTIAL_CRC_PARTIAL)

 
 #define S_DM_PARTIAL_TCPCS_PARTIAL    _SB_MAKE64(32)
 #define M_DM_PARTIAL_TCPCS_PARTIAL    _SB_MAKEMASK(16, S_DM_PARTIAL_TCPCS_PARTIAL)
 #define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL)
 #define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL,\
 
 #define S_DM_PARTIAL_TCPCS_PARTIAL    _SB_MAKE64(32)
 #define M_DM_PARTIAL_TCPCS_PARTIAL    _SB_MAKEMASK(16, S_DM_PARTIAL_TCPCS_PARTIAL)
 #define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL)
 #define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL,\

-                                       M_DM_PARTIAL_TCPCS_PARTIAL)
+                                      M_DM_PARTIAL_TCPCS_PARTIAL)

 
 

-#define M_DM_PARTIAL_ODD_BYTE         _SB_MAKEMASK1(48)
+#define M_DM_PARTIAL_ODD_BYTE        _SB_MAKEMASK1(48)

 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 


@@ -468,17 +468,17 @@
  * Register: CRC_DEF_0
  * Register: CRC_DEF_1
  */
  * Register: CRC_DEF_0
  * Register: CRC_DEF_1
  */

-#define S_CRC_DEF_CRC_INIT            _SB_MAKE64(0)
-#define M_CRC_DEF_CRC_INIT            _SB_MAKEMASK(32, S_CRC_DEF_CRC_INIT)
-#define V_CRC_DEF_CRC_INIT(r)         _SB_MAKEVALUE(r, S_CRC_DEF_CRC_INIT)
-#define G_CRC_DEF_CRC_INIT(r)         _SB_GETVALUE(r, S_CRC_DEF_CRC_INIT,\
-                                       M_CRC_DEF_CRC_INIT)
-
-#define S_CRC_DEF_CRC_POLY            _SB_MAKE64(32)
-#define M_CRC_DEF_CRC_POLY            _SB_MAKEMASK(32, S_CRC_DEF_CRC_POLY)
-#define V_CRC_DEF_CRC_POLY(r)         _SB_MAKEVALUE(r, S_CRC_DEF_CRC_POLY)
-#define G_CRC_DEF_CRC_POLY(r)         _SB_GETVALUE(r, S_CRC_DEF_CRC_POLY,\
-                                       M_CRC_DEF_CRC_POLY)
+#define S_CRC_DEF_CRC_INIT           _SB_MAKE64(0)
+#define M_CRC_DEF_CRC_INIT           _SB_MAKEMASK(32, S_CRC_DEF_CRC_INIT)
+#define V_CRC_DEF_CRC_INIT(r)        _SB_MAKEVALUE(r, S_CRC_DEF_CRC_INIT)
+#define G_CRC_DEF_CRC_INIT(r)        _SB_GETVALUE(r, S_CRC_DEF_CRC_INIT,\
+                                      M_CRC_DEF_CRC_INIT)
+
+#define S_CRC_DEF_CRC_POLY           _SB_MAKE64(32)
+#define M_CRC_DEF_CRC_POLY           _SB_MAKEMASK(32, S_CRC_DEF_CRC_POLY)
+#define V_CRC_DEF_CRC_POLY(r)        _SB_MAKEVALUE(r, S_CRC_DEF_CRC_POLY)
+#define G_CRC_DEF_CRC_POLY(r)        _SB_GETVALUE(r, S_CRC_DEF_CRC_POLY,\
+                                      M_CRC_DEF_CRC_POLY)

 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 


@@ -488,50 +488,50 @@
  * Register: CTCP_DEF_0
  * Register: CTCP_DEF_1
  */
  * Register: CTCP_DEF_0
  * Register: CTCP_DEF_1
  */

-#define S_CTCP_DEF_CRC_TXOR           _SB_MAKE64(0)
-#define M_CTCP_DEF_CRC_TXOR           _SB_MAKEMASK(32, S_CTCP_DEF_CRC_TXOR)
-#define V_CTCP_DEF_CRC_TXOR(r)        _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_TXOR)
-#define G_CTCP_DEF_CRC_TXOR(r)        _SB_GETVALUE(r, S_CTCP_DEF_CRC_TXOR,\
-                                       M_CTCP_DEF_CRC_TXOR)
-
-#define S_CTCP_DEF_TCPCS_INIT         _SB_MAKE64(32)
-#define M_CTCP_DEF_TCPCS_INIT         _SB_MAKEMASK(16, S_CTCP_DEF_TCPCS_INIT)
+#define S_CTCP_DEF_CRC_TXOR          _SB_MAKE64(0)
+#define M_CTCP_DEF_CRC_TXOR          _SB_MAKEMASK(32, S_CTCP_DEF_CRC_TXOR)
+#define V_CTCP_DEF_CRC_TXOR(r)       _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_TXOR)
+#define G_CTCP_DEF_CRC_TXOR(r)       _SB_GETVALUE(r, S_CTCP_DEF_CRC_TXOR,\
+                                      M_CTCP_DEF_CRC_TXOR)
+
+#define S_CTCP_DEF_TCPCS_INIT        _SB_MAKE64(32)
+#define M_CTCP_DEF_TCPCS_INIT        _SB_MAKEMASK(16, S_CTCP_DEF_TCPCS_INIT)

 #define V_CTCP_DEF_TCPCS_INIT(r)      _SB_MAKEVALUE(r, S_CTCP_DEF_TCPCS_INIT)
 #define G_CTCP_DEF_TCPCS_INIT(r)      _SB_GETVALUE(r, S_CTCP_DEF_TCPCS_INIT,\
 #define V_CTCP_DEF_TCPCS_INIT(r)      _SB_MAKEVALUE(r, S_CTCP_DEF_TCPCS_INIT)
 #define G_CTCP_DEF_TCPCS_INIT(r)      _SB_GETVALUE(r, S_CTCP_DEF_TCPCS_INIT,\

-                                       M_CTCP_DEF_TCPCS_INIT)
+                                      M_CTCP_DEF_TCPCS_INIT)

 
 

-#define S_CTCP_DEF_CRC_WIDTH          _SB_MAKE64(48)
-#define M_CTCP_DEF_CRC_WIDTH          _SB_MAKEMASK(2, S_CTCP_DEF_CRC_WIDTH)
-#define V_CTCP_DEF_CRC_WIDTH(r)       _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_WIDTH)
-#define G_CTCP_DEF_CRC_WIDTH(r)       _SB_GETVALUE(r, S_CTCP_DEF_CRC_WIDTH,\
-                                       M_CTCP_DEF_CRC_WIDTH)
+#define S_CTCP_DEF_CRC_WIDTH         _SB_MAKE64(48)
+#define M_CTCP_DEF_CRC_WIDTH         _SB_MAKEMASK(2, S_CTCP_DEF_CRC_WIDTH)
+#define V_CTCP_DEF_CRC_WIDTH(r)              _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_WIDTH)
+#define G_CTCP_DEF_CRC_WIDTH(r)              _SB_GETVALUE(r, S_CTCP_DEF_CRC_WIDTH,\
+                                      M_CTCP_DEF_CRC_WIDTH)

 
 

-#define K_CTCP_DEF_CRC_WIDTH_4        0
-#define K_CTCP_DEF_CRC_WIDTH_2        1
-#define K_CTCP_DEF_CRC_WIDTH_1        2
+#define K_CTCP_DEF_CRC_WIDTH_4       0
+#define K_CTCP_DEF_CRC_WIDTH_2       1
+#define K_CTCP_DEF_CRC_WIDTH_1       2

 
 #define M_CTCP_DEF_CRC_BIT_ORDER      _SB_MAKEMASK1(50)
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 
 /*
 
 #define M_CTCP_DEF_CRC_BIT_ORDER      _SB_MAKEMASK1(50)
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 
 /*

- * Data Mover Descriptor Doubleword "A"  (Table 7-26)
+ * Data Mover Descriptor Doubleword "A"         (Table 7-26)

  */
 
  */
 

-#define S_DM_DSCRA_DST_ADDR         _SB_MAKE64(0)
-#define M_DM_DSCRA_DST_ADDR         _SB_MAKEMASK(40, S_DM_DSCRA_DST_ADDR)
+#define S_DM_DSCRA_DST_ADDR        _SB_MAKE64(0)
+#define M_DM_DSCRA_DST_ADDR        _SB_MAKEMASK(40, S_DM_DSCRA_DST_ADDR)

 
 

-#define M_DM_DSCRA_UN_DEST          _SB_MAKEMASK1(40)
-#define M_DM_DSCRA_UN_SRC           _SB_MAKEMASK1(41)
-#define M_DM_DSCRA_INTERRUPT        _SB_MAKEMASK1(42)
+#define M_DM_DSCRA_UN_DEST         _SB_MAKEMASK1(40)
+#define M_DM_DSCRA_UN_SRC          _SB_MAKEMASK1(41)
+#define M_DM_DSCRA_INTERRUPT       _SB_MAKEMASK1(42)

 #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
 #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)

-#define M_DM_DSCRA_THROTTLE         _SB_MAKEMASK1(43)
+#define M_DM_DSCRA_THROTTLE        _SB_MAKEMASK1(43)

 #endif /* up to 1250 PASS1 */
 
 #endif /* up to 1250 PASS1 */
 

-#define S_DM_DSCRA_DIR_DEST         _SB_MAKE64(44)
-#define M_DM_DSCRA_DIR_DEST         _SB_MAKEMASK(2, S_DM_DSCRA_DIR_DEST)
-#define V_DM_DSCRA_DIR_DEST(x)      _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_DEST)
-#define G_DM_DSCRA_DIR_DEST(x)      _SB_GETVALUE(x, S_DM_DSCRA_DIR_DEST, M_DM_DSCRA_DIR_DEST)
+#define S_DM_DSCRA_DIR_DEST        _SB_MAKE64(44)
+#define M_DM_DSCRA_DIR_DEST        _SB_MAKEMASK(2, S_DM_DSCRA_DIR_DEST)
+#define V_DM_DSCRA_DIR_DEST(x)     _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_DEST)
+#define G_DM_DSCRA_DIR_DEST(x)     _SB_GETVALUE(x, S_DM_DSCRA_DIR_DEST, M_DM_DSCRA_DIR_DEST)

 
 #define K_DM_DSCRA_DIR_DEST_INCR    0
 #define K_DM_DSCRA_DIR_DEST_DECR    1
 
 #define K_DM_DSCRA_DIR_DEST_INCR    0
 #define K_DM_DSCRA_DIR_DEST_DECR    1


@@ -541,24 +541,24 @@
 #define V_DM_DSCRA_DIR_DEST_DECR    _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR, S_DM_DSCRA_DIR_DEST)
 #define V_DM_DSCRA_DIR_DEST_CONST   _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST, S_DM_DSCRA_DIR_DEST)
 
 #define V_DM_DSCRA_DIR_DEST_DECR    _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR, S_DM_DSCRA_DIR_DEST)
 #define V_DM_DSCRA_DIR_DEST_CONST   _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST, S_DM_DSCRA_DIR_DEST)
 

-#define S_DM_DSCRA_DIR_SRC          _SB_MAKE64(46)
-#define M_DM_DSCRA_DIR_SRC          _SB_MAKEMASK(2, S_DM_DSCRA_DIR_SRC)
-#define V_DM_DSCRA_DIR_SRC(x)       _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_SRC)
-#define G_DM_DSCRA_DIR_SRC(x)       _SB_GETVALUE(x, S_DM_DSCRA_DIR_SRC, M_DM_DSCRA_DIR_SRC)
+#define S_DM_DSCRA_DIR_SRC         _SB_MAKE64(46)
+#define M_DM_DSCRA_DIR_SRC         _SB_MAKEMASK(2, S_DM_DSCRA_DIR_SRC)
+#define V_DM_DSCRA_DIR_SRC(x)      _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_SRC)
+#define G_DM_DSCRA_DIR_SRC(x)      _SB_GETVALUE(x, S_DM_DSCRA_DIR_SRC, M_DM_DSCRA_DIR_SRC)

 
 

-#define K_DM_DSCRA_DIR_SRC_INCR     0
-#define K_DM_DSCRA_DIR_SRC_DECR     1
+#define K_DM_DSCRA_DIR_SRC_INCR            0
+#define K_DM_DSCRA_DIR_SRC_DECR            1

 #define K_DM_DSCRA_DIR_SRC_CONST    2
 
 #define K_DM_DSCRA_DIR_SRC_CONST    2
 

-#define V_DM_DSCRA_DIR_SRC_INCR     _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR, S_DM_DSCRA_DIR_SRC)
-#define V_DM_DSCRA_DIR_SRC_DECR     _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR, S_DM_DSCRA_DIR_SRC)
+#define V_DM_DSCRA_DIR_SRC_INCR            _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR, S_DM_DSCRA_DIR_SRC)
+#define V_DM_DSCRA_DIR_SRC_DECR            _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR, S_DM_DSCRA_DIR_SRC)

 #define V_DM_DSCRA_DIR_SRC_CONST    _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST, S_DM_DSCRA_DIR_SRC)
 
 
 #define V_DM_DSCRA_DIR_SRC_CONST    _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST, S_DM_DSCRA_DIR_SRC)
 
 

-#define M_DM_DSCRA_ZERO_MEM         _SB_MAKEMASK1(48)
-#define M_DM_DSCRA_PREFETCH         _SB_MAKEMASK1(49)
-#define M_DM_DSCRA_L2C_DEST         _SB_MAKEMASK1(50)
-#define M_DM_DSCRA_L2C_SRC          _SB_MAKEMASK1(51)
+#define M_DM_DSCRA_ZERO_MEM        _SB_MAKEMASK1(48)
+#define M_DM_DSCRA_PREFETCH        _SB_MAKEMASK1(49)
+#define M_DM_DSCRA_L2C_DEST        _SB_MAKEMASK1(50)
+#define M_DM_DSCRA_L2C_SRC         _SB_MAKEMASK1(51)

 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_DM_DSCRA_RD_BKOFF        _SB_MAKEMASK1(52)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_DM_DSCRA_RD_BKOFF        _SB_MAKEMASK1(52)


@@ -566,27 +566,27 @@
 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)

-#define M_DM_DSCRA_TCPCS_EN         _SB_MAKEMASK1(54)
-#define M_DM_DSCRA_TCPCS_RES        _SB_MAKEMASK1(55)
-#define M_DM_DSCRA_TCPCS_AP         _SB_MAKEMASK1(56)
-#define M_DM_DSCRA_CRC_EN           _SB_MAKEMASK1(57)
-#define M_DM_DSCRA_CRC_RES          _SB_MAKEMASK1(58)
-#define M_DM_DSCRA_CRC_AP           _SB_MAKEMASK1(59)
-#define M_DM_DSCRA_CRC_DFN          _SB_MAKEMASK1(60)
-#define M_DM_DSCRA_CRC_XBIT         _SB_MAKEMASK1(61)
+#define M_DM_DSCRA_TCPCS_EN        _SB_MAKEMASK1(54)
+#define M_DM_DSCRA_TCPCS_RES       _SB_MAKEMASK1(55)
+#define M_DM_DSCRA_TCPCS_AP        _SB_MAKEMASK1(56)
+#define M_DM_DSCRA_CRC_EN          _SB_MAKEMASK1(57)
+#define M_DM_DSCRA_CRC_RES         _SB_MAKEMASK1(58)
+#define M_DM_DSCRA_CRC_AP          _SB_MAKEMASK1(59)
+#define M_DM_DSCRA_CRC_DFN         _SB_MAKEMASK1(60)
+#define M_DM_DSCRA_CRC_XBIT        _SB_MAKEMASK1(61)

 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 

-#define M_DM_DSCRA_RESERVED2        _SB_MAKEMASK(3, 61)
+#define M_DM_DSCRA_RESERVED2       _SB_MAKEMASK(3, 61)

 
 /*
 
 /*

- * Data Mover Descriptor Doubleword "B"  (Table 7-25)
+ * Data Mover Descriptor Doubleword "B"         (Table 7-25)

  */
 
  */
 

-#define S_DM_DSCRB_SRC_ADDR         _SB_MAKE64(0)
-#define M_DM_DSCRB_SRC_ADDR         _SB_MAKEMASK(40, S_DM_DSCRB_SRC_ADDR)
+#define S_DM_DSCRB_SRC_ADDR        _SB_MAKE64(0)
+#define M_DM_DSCRB_SRC_ADDR        _SB_MAKEMASK(40, S_DM_DSCRB_SRC_ADDR)

 
 

-#define S_DM_DSCRB_SRC_LENGTH       _SB_MAKE64(40)
-#define M_DM_DSCRB_SRC_LENGTH       _SB_MAKEMASK(20, S_DM_DSCRB_SRC_LENGTH)
+#define S_DM_DSCRB_SRC_LENGTH      _SB_MAKE64(40)
+#define M_DM_DSCRB_SRC_LENGTH      _SB_MAKEMASK(20, S_DM_DSCRB_SRC_LENGTH)

 #define V_DM_DSCRB_SRC_LENGTH(x)    _SB_MAKEVALUE(x, S_DM_DSCRB_SRC_LENGTH)
 #define G_DM_DSCRB_SRC_LENGTH(x)    _SB_GETVALUE(x, S_DM_DSCRB_SRC_LENGTH, M_DM_DSCRB_SRC_LENGTH)
 
 #define V_DM_DSCRB_SRC_LENGTH(x)    _SB_MAKEVALUE(x, S_DM_DSCRB_SRC_LENGTH)
 #define G_DM_DSCRB_SRC_LENGTH(x)    _SB_GETVALUE(x, S_DM_DSCRB_SRC_LENGTH, M_DM_DSCRB_SRC_LENGTH)
 

diff --git a/arch/mips/include/asm/sibyte/sb1250_genbus.h b/arch/mips/include/asm/sibyte/sb1250_genbus.h
index a96ded17bdc9e34dcf4804919d727b818feeb013..04c009c36937dc0d5aa4612b96f3b9c6bc27c235 100644 (file)
--- a/arch/mips/include/asm/sibyte/sb1250_genbus.h
+++ b/arch/mips/include/asm/sibyte/sb1250_genbus.h
@@ -1,7 +1,7 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
     *
 /*  *********************************************************************
     *  SB1250 Board Support Package
     *

-    *  Generic Bus Constants                     File: sb1250_genbus.h
+    *  Generic Bus Constants                    File: sb1250_genbus.h

     *
     *  This module contains constants and macros useful for
     *  manipulating the SB1250's Generic Bus interface
     *
     *  This module contains constants and macros useful for
     *  manipulating the SB1250's Generic Bus interface


@@ -40,10 +40,10 @@
  * Generic Bus Region Configuration Registers (Table 11-4)
  */
 
  * Generic Bus Region Configuration Registers (Table 11-4)
  */
 

-#define S_IO_RDY_ACTIVE         0
+#define S_IO_RDY_ACTIVE                0

 #define M_IO_RDY_ACTIVE                _SB_MAKEMASK1(S_IO_RDY_ACTIVE)
 
 #define M_IO_RDY_ACTIVE                _SB_MAKEMASK1(S_IO_RDY_ACTIVE)
 

-#define S_IO_ENA_RDY            1
+#define S_IO_ENA_RDY           1

 #define M_IO_ENA_RDY           _SB_MAKEMASK1(S_IO_ENA_RDY)
 
 #define S_IO_WIDTH_SEL         2
 #define M_IO_ENA_RDY           _SB_MAKEMASK1(S_IO_ENA_RDY)
 
 #define S_IO_WIDTH_SEL         2


@@ -52,7 +52,7 @@
 #define K_IO_WIDTH_SEL_2       1
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
     || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define K_IO_WIDTH_SEL_2       1
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
     || SIBYTE_HDR_FEATURE_CHIP(1480)

-#define K_IO_WIDTH_SEL_1L       2
+#define K_IO_WIDTH_SEL_1L      2

 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 #define K_IO_WIDTH_SEL_4       3
 #define V_IO_WIDTH_SEL(x)      _SB_MAKEVALUE(x, S_IO_WIDTH_SEL)
 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 #define K_IO_WIDTH_SEL_4       3
 #define V_IO_WIDTH_SEL(x)      _SB_MAKEVALUE(x, S_IO_WIDTH_SEL)


@@ -111,7 +111,7 @@
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
     || SIBYTE_HDR_FEATURE_CHIP(1480)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
     || SIBYTE_HDR_FEATURE_CHIP(1480)

-#define M_IO_EARLY_CS          _SB_MAKEMASK1(3)
+#define M_IO_EARLY_CS          _SB_MAKEMASK1(3)

 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 #define S_IO_ALE_TO_CS         4
 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 #define S_IO_ALE_TO_CS         4


@@ -121,10 +121,10 @@
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
     || SIBYTE_HDR_FEATURE_CHIP(1480)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
     || SIBYTE_HDR_FEATURE_CHIP(1480)

-#define S_IO_BURST_WIDTH           _SB_MAKE64(6)
-#define M_IO_BURST_WIDTH           _SB_MAKEMASK(2, S_IO_BURST_WIDTH)
-#define V_IO_BURST_WIDTH(x)        _SB_MAKEVALUE(x, S_IO_BURST_WIDTH)
-#define G_IO_BURST_WIDTH(x)        _SB_GETVALUE(x, S_IO_BURST_WIDTH, M_IO_BURST_WIDTH)
+#define S_IO_BURST_WIDTH          _SB_MAKE64(6)
+#define M_IO_BURST_WIDTH          _SB_MAKEMASK(2, S_IO_BURST_WIDTH)
+#define V_IO_BURST_WIDTH(x)       _SB_MAKEVALUE(x, S_IO_BURST_WIDTH)
+#define G_IO_BURST_WIDTH(x)       _SB_GETVALUE(x, S_IO_BURST_WIDTH, M_IO_BURST_WIDTH)

 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 #define S_IO_CS_WIDTH          8
 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 #define S_IO_CS_WIDTH          8


@@ -149,7 +149,7 @@
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
     || SIBYTE_HDR_FEATURE_CHIP(1480)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
     || SIBYTE_HDR_FEATURE_CHIP(1480)

-#define M_IO_RDY_SYNC          _SB_MAKEMASK1(3)
+#define M_IO_RDY_SYNC          _SB_MAKEMASK1(3)

 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 #define S_IO_WRITE_WIDTH       4
 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 #define S_IO_WRITE_WIDTH       4


@@ -191,7 +191,7 @@
 #define M_IO_ILL_ADDR_INT      _SB_MAKEMASK1(11)
 #define M_IO_MULT_CS_INT       _SB_MAKEMASK1(12)
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_IO_ILL_ADDR_INT      _SB_MAKEMASK1(11)
 #define M_IO_MULT_CS_INT       _SB_MAKEMASK1(12)
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)

-#define M_IO_COH_ERR           _SB_MAKEMASK1(14)
+#define M_IO_COH_ERR           _SB_MAKEMASK1(14)

 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 
 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 


@@ -370,8 +370,8 @@
 
 #define S_GPIO_INTR_TYPEX(n)   (((n)/2)*2)
 #define M_GPIO_INTR_TYPEX(n)   _SB_MAKEMASK(2, S_GPIO_INTR_TYPEX(n))
 
 #define S_GPIO_INTR_TYPEX(n)   (((n)/2)*2)
 #define M_GPIO_INTR_TYPEX(n)   _SB_MAKEMASK(2, S_GPIO_INTR_TYPEX(n))

-#define V_GPIO_INTR_TYPEX(n, x)        _SB_MAKEVALUE(x, S_GPIO_INTR_TYPEX(n))
-#define G_GPIO_INTR_TYPEX(n, x)        _SB_GETVALUE(x, S_GPIO_INTR_TYPEX(n), M_GPIO_INTR_TYPEX(n))
+#define V_GPIO_INTR_TYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPEX(n))
+#define G_GPIO_INTR_TYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_TYPEX(n), M_GPIO_INTR_TYPEX(n))

 
 #define S_GPIO_INTR_TYPE0      0
 #define M_GPIO_INTR_TYPE0      _SB_MAKEMASK(2, S_GPIO_INTR_TYPE0)
 
 #define S_GPIO_INTR_TYPE0      0
 #define M_GPIO_INTR_TYPE0      _SB_MAKEMASK(2, S_GPIO_INTR_TYPE0)

diff --git a/arch/mips/include/asm/sibyte/sb1250_int.h b/arch/mips/include/asm/sibyte/sb1250_int.h
index dbea73ddd2feb92d5457d79d678546dec3da7499..36afcb2766c662c9a253cf2d37ab2e6b9e4a0704 100644 (file)
--- a/arch/mips/include/asm/sibyte/sb1250_int.h
+++ b/arch/mips/include/asm/sibyte/sb1250_int.h
@@ -45,71 +45,71 @@
  * First, the interrupt numbers.
  */
 
  * First, the interrupt numbers.
  */
 

-#define K_INT_SOURCES               64
-
-#define K_INT_WATCHDOG_TIMER_0      0
-#define K_INT_WATCHDOG_TIMER_1      1
-#define K_INT_TIMER_0               2
-#define K_INT_TIMER_1               3
-#define K_INT_TIMER_2               4
-#define K_INT_TIMER_3               5
-#define K_INT_SMB_0                 6
-#define K_INT_SMB_1                 7
-#define K_INT_UART_0                8
-#define K_INT_UART_1                9
-#define K_INT_SER_0                 10
-#define K_INT_SER_1                 11
-#define K_INT_PCMCIA                12
-#define K_INT_ADDR_TRAP             13
-#define K_INT_PERF_CNT              14
-#define K_INT_TRACE_FREEZE          15
-#define K_INT_BAD_ECC               16
-#define K_INT_COR_ECC               17
-#define K_INT_IO_BUS                18
-#define K_INT_MAC_0                 19
-#define K_INT_MAC_1                 20
-#define K_INT_MAC_2                 21
-#define K_INT_DM_CH_0               22
-#define K_INT_DM_CH_1               23
-#define K_INT_DM_CH_2               24
-#define K_INT_DM_CH_3               25
-#define K_INT_MBOX_0                26
-#define K_INT_MBOX_1                27
-#define K_INT_MBOX_2                28
-#define K_INT_MBOX_3                29
+#define K_INT_SOURCES              64
+
+#define K_INT_WATCHDOG_TIMER_0     0
+#define K_INT_WATCHDOG_TIMER_1     1
+#define K_INT_TIMER_0              2
+#define K_INT_TIMER_1              3
+#define K_INT_TIMER_2              4
+#define K_INT_TIMER_3              5
+#define K_INT_SMB_0                6
+#define K_INT_SMB_1                7
+#define K_INT_UART_0               8
+#define K_INT_UART_1               9
+#define K_INT_SER_0                10
+#define K_INT_SER_1                11
+#define K_INT_PCMCIA               12
+#define K_INT_ADDR_TRAP                    13
+#define K_INT_PERF_CNT             14
+#define K_INT_TRACE_FREEZE         15
+#define K_INT_BAD_ECC              16
+#define K_INT_COR_ECC              17
+#define K_INT_IO_BUS               18
+#define K_INT_MAC_0                19
+#define K_INT_MAC_1                20
+#define K_INT_MAC_2                21
+#define K_INT_DM_CH_0              22
+#define K_INT_DM_CH_1              23
+#define K_INT_DM_CH_2              24
+#define K_INT_DM_CH_3              25
+#define K_INT_MBOX_0               26
+#define K_INT_MBOX_1               27
+#define K_INT_MBOX_2               28
+#define K_INT_MBOX_3               29

 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define K_INT_CYCLE_CP0_INT        30
 #define K_INT_CYCLE_CP1_INT        31
 #endif /* 1250 PASS2 || 112x PASS1 */
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define K_INT_CYCLE_CP0_INT        30
 #define K_INT_CYCLE_CP1_INT        31
 #endif /* 1250 PASS2 || 112x PASS1 */

-#define K_INT_GPIO_0                32
-#define K_INT_GPIO_1                33
-#define K_INT_GPIO_2                34
-#define K_INT_GPIO_3                35
-#define K_INT_GPIO_4                36
-#define K_INT_GPIO_5                37
-#define K_INT_GPIO_6                38
-#define K_INT_GPIO_7                39
-#define K_INT_GPIO_8                40
-#define K_INT_GPIO_9                41
-#define K_INT_GPIO_10               42
-#define K_INT_GPIO_11               43
-#define K_INT_GPIO_12               44
-#define K_INT_GPIO_13               45
-#define K_INT_GPIO_14               46
-#define K_INT_GPIO_15               47
-#define K_INT_LDT_FATAL             48
-#define K_INT_LDT_NONFATAL          49
-#define K_INT_LDT_SMI               50
-#define K_INT_LDT_NMI               51
-#define K_INT_LDT_INIT              52
-#define K_INT_LDT_STARTUP           53
-#define K_INT_LDT_EXT               54
-#define K_INT_PCI_ERROR             55
-#define K_INT_PCI_INTA              56
-#define K_INT_PCI_INTB              57
-#define K_INT_PCI_INTC              58
-#define K_INT_PCI_INTD              59
-#define K_INT_SPARE_2               60
+#define K_INT_GPIO_0               32
+#define K_INT_GPIO_1               33
+#define K_INT_GPIO_2               34
+#define K_INT_GPIO_3               35
+#define K_INT_GPIO_4               36
+#define K_INT_GPIO_5               37
+#define K_INT_GPIO_6               38
+#define K_INT_GPIO_7               39
+#define K_INT_GPIO_8               40
+#define K_INT_GPIO_9               41
+#define K_INT_GPIO_10              42
+#define K_INT_GPIO_11              43
+#define K_INT_GPIO_12              44
+#define K_INT_GPIO_13              45
+#define K_INT_GPIO_14              46
+#define K_INT_GPIO_15              47
+#define K_INT_LDT_FATAL                    48
+#define K_INT_LDT_NONFATAL         49
+#define K_INT_LDT_SMI              50
+#define K_INT_LDT_NMI              51
+#define K_INT_LDT_INIT             52
+#define K_INT_LDT_STARTUP          53
+#define K_INT_LDT_EXT              54
+#define K_INT_PCI_ERROR                    55
+#define K_INT_PCI_INTA             56
+#define K_INT_PCI_INTB             57
+#define K_INT_PCI_INTC             58
+#define K_INT_PCI_INTD             59
+#define K_INT_SPARE_2              60

 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define K_INT_MAC_0_CH1                    61
 #define K_INT_MAC_1_CH1                    62
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define K_INT_MAC_0_CH1                    61
 #define K_INT_MAC_1_CH1                    62


@@ -120,70 +120,70 @@
  * Mask values for each interrupt
  */
 
  * Mask values for each interrupt
  */
 

-#define M_INT_WATCHDOG_TIMER_0      _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0)
-#define M_INT_WATCHDOG_TIMER_1      _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1)
-#define M_INT_TIMER_0               _SB_MAKEMASK1(K_INT_TIMER_0)
-#define M_INT_TIMER_1               _SB_MAKEMASK1(K_INT_TIMER_1)
-#define M_INT_TIMER_2               _SB_MAKEMASK1(K_INT_TIMER_2)
-#define M_INT_TIMER_3               _SB_MAKEMASK1(K_INT_TIMER_3)
-#define M_INT_SMB_0                 _SB_MAKEMASK1(K_INT_SMB_0)
-#define M_INT_SMB_1                 _SB_MAKEMASK1(K_INT_SMB_1)
-#define M_INT_UART_0                _SB_MAKEMASK1(K_INT_UART_0)
-#define M_INT_UART_1                _SB_MAKEMASK1(K_INT_UART_1)
-#define M_INT_SER_0                 _SB_MAKEMASK1(K_INT_SER_0)
-#define M_INT_SER_1                 _SB_MAKEMASK1(K_INT_SER_1)
-#define M_INT_PCMCIA                _SB_MAKEMASK1(K_INT_PCMCIA)
-#define M_INT_ADDR_TRAP             _SB_MAKEMASK1(K_INT_ADDR_TRAP)
-#define M_INT_PERF_CNT              _SB_MAKEMASK1(K_INT_PERF_CNT)
-#define M_INT_TRACE_FREEZE          _SB_MAKEMASK1(K_INT_TRACE_FREEZE)
-#define M_INT_BAD_ECC               _SB_MAKEMASK1(K_INT_BAD_ECC)
-#define M_INT_COR_ECC               _SB_MAKEMASK1(K_INT_COR_ECC)
-#define M_INT_IO_BUS                _SB_MAKEMASK1(K_INT_IO_BUS)
-#define M_INT_MAC_0                 _SB_MAKEMASK1(K_INT_MAC_0)
-#define M_INT_MAC_1                 _SB_MAKEMASK1(K_INT_MAC_1)
-#define M_INT_MAC_2                 _SB_MAKEMASK1(K_INT_MAC_2)
-#define M_INT_DM_CH_0               _SB_MAKEMASK1(K_INT_DM_CH_0)
-#define M_INT_DM_CH_1               _SB_MAKEMASK1(K_INT_DM_CH_1)
-#define M_INT_DM_CH_2               _SB_MAKEMASK1(K_INT_DM_CH_2)
-#define M_INT_DM_CH_3               _SB_MAKEMASK1(K_INT_DM_CH_3)
-#define M_INT_MBOX_0                _SB_MAKEMASK1(K_INT_MBOX_0)
-#define M_INT_MBOX_1                _SB_MAKEMASK1(K_INT_MBOX_1)
-#define M_INT_MBOX_2                _SB_MAKEMASK1(K_INT_MBOX_2)
-#define M_INT_MBOX_3                _SB_MAKEMASK1(K_INT_MBOX_3)
-#define M_INT_MBOX_ALL              _SB_MAKEMASK(4, K_INT_MBOX_0)
+#define M_INT_WATCHDOG_TIMER_0     _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0)
+#define M_INT_WATCHDOG_TIMER_1     _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1)
+#define M_INT_TIMER_0              _SB_MAKEMASK1(K_INT_TIMER_0)
+#define M_INT_TIMER_1              _SB_MAKEMASK1(K_INT_TIMER_1)
+#define M_INT_TIMER_2              _SB_MAKEMASK1(K_INT_TIMER_2)
+#define M_INT_TIMER_3              _SB_MAKEMASK1(K_INT_TIMER_3)
+#define M_INT_SMB_0                _SB_MAKEMASK1(K_INT_SMB_0)
+#define M_INT_SMB_1                _SB_MAKEMASK1(K_INT_SMB_1)
+#define M_INT_UART_0               _SB_MAKEMASK1(K_INT_UART_0)
+#define M_INT_UART_1               _SB_MAKEMASK1(K_INT_UART_1)
+#define M_INT_SER_0                _SB_MAKEMASK1(K_INT_SER_0)
+#define M_INT_SER_1                _SB_MAKEMASK1(K_INT_SER_1)
+#define M_INT_PCMCIA               _SB_MAKEMASK1(K_INT_PCMCIA)
+#define M_INT_ADDR_TRAP                    _SB_MAKEMASK1(K_INT_ADDR_TRAP)
+#define M_INT_PERF_CNT             _SB_MAKEMASK1(K_INT_PERF_CNT)
+#define M_INT_TRACE_FREEZE         _SB_MAKEMASK1(K_INT_TRACE_FREEZE)
+#define M_INT_BAD_ECC              _SB_MAKEMASK1(K_INT_BAD_ECC)
+#define M_INT_COR_ECC              _SB_MAKEMASK1(K_INT_COR_ECC)
+#define M_INT_IO_BUS               _SB_MAKEMASK1(K_INT_IO_BUS)
+#define M_INT_MAC_0                _SB_MAKEMASK1(K_INT_MAC_0)
+#define M_INT_MAC_1                _SB_MAKEMASK1(K_INT_MAC_1)
+#define M_INT_MAC_2                _SB_MAKEMASK1(K_INT_MAC_2)
+#define M_INT_DM_CH_0              _SB_MAKEMASK1(K_INT_DM_CH_0)
+#define M_INT_DM_CH_1              _SB_MAKEMASK1(K_INT_DM_CH_1)
+#define M_INT_DM_CH_2              _SB_MAKEMASK1(K_INT_DM_CH_2)
+#define M_INT_DM_CH_3              _SB_MAKEMASK1(K_INT_DM_CH_3)
+#define M_INT_MBOX_0               _SB_MAKEMASK1(K_INT_MBOX_0)
+#define M_INT_MBOX_1               _SB_MAKEMASK1(K_INT_MBOX_1)
+#define M_INT_MBOX_2               _SB_MAKEMASK1(K_INT_MBOX_2)
+#define M_INT_MBOX_3               _SB_MAKEMASK1(K_INT_MBOX_3)
+#define M_INT_MBOX_ALL             _SB_MAKEMASK(4, K_INT_MBOX_0)

 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define M_INT_CYCLE_CP0_INT        _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
 #define M_INT_CYCLE_CP1_INT        _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
 #endif /* 1250 PASS2 || 112x PASS1 */
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define M_INT_CYCLE_CP0_INT        _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
 #define M_INT_CYCLE_CP1_INT        _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
 #endif /* 1250 PASS2 || 112x PASS1 */

-#define M_INT_GPIO_0                _SB_MAKEMASK1(K_INT_GPIO_0)
-#define M_INT_GPIO_1                _SB_MAKEMASK1(K_INT_GPIO_1)
-#define M_INT_GPIO_2                _SB_MAKEMASK1(K_INT_GPIO_2)
-#define M_INT_GPIO_3                _SB_MAKEMASK1(K_INT_GPIO_3)
-#define M_INT_GPIO_4                _SB_MAKEMASK1(K_INT_GPIO_4)
-#define M_INT_GPIO_5                _SB_MAKEMASK1(K_INT_GPIO_5)
-#define M_INT_GPIO_6                _SB_MAKEMASK1(K_INT_GPIO_6)
-#define M_INT_GPIO_7                _SB_MAKEMASK1(K_INT_GPIO_7)
-#define M_INT_GPIO_8                _SB_MAKEMASK1(K_INT_GPIO_8)
-#define M_INT_GPIO_9                _SB_MAKEMASK1(K_INT_GPIO_9)
-#define M_INT_GPIO_10               _SB_MAKEMASK1(K_INT_GPIO_10)
-#define M_INT_GPIO_11               _SB_MAKEMASK1(K_INT_GPIO_11)
-#define M_INT_GPIO_12               _SB_MAKEMASK1(K_INT_GPIO_12)
-#define M_INT_GPIO_13               _SB_MAKEMASK1(K_INT_GPIO_13)
-#define M_INT_GPIO_14               _SB_MAKEMASK1(K_INT_GPIO_14)
-#define M_INT_GPIO_15               _SB_MAKEMASK1(K_INT_GPIO_15)
-#define M_INT_LDT_FATAL             _SB_MAKEMASK1(K_INT_LDT_FATAL)
-#define M_INT_LDT_NONFATAL          _SB_MAKEMASK1(K_INT_LDT_NONFATAL)
-#define M_INT_LDT_SMI               _SB_MAKEMASK1(K_INT_LDT_SMI)
-#define M_INT_LDT_NMI               _SB_MAKEMASK1(K_INT_LDT_NMI)
-#define M_INT_LDT_INIT              _SB_MAKEMASK1(K_INT_LDT_INIT)
-#define M_INT_LDT_STARTUP           _SB_MAKEMASK1(K_INT_LDT_STARTUP)
-#define M_INT_LDT_EXT               _SB_MAKEMASK1(K_INT_LDT_EXT)
-#define M_INT_PCI_ERROR             _SB_MAKEMASK1(K_INT_PCI_ERROR)
-#define M_INT_PCI_INTA              _SB_MAKEMASK1(K_INT_PCI_INTA)
-#define M_INT_PCI_INTB              _SB_MAKEMASK1(K_INT_PCI_INTB)
-#define M_INT_PCI_INTC              _SB_MAKEMASK1(K_INT_PCI_INTC)
-#define M_INT_PCI_INTD              _SB_MAKEMASK1(K_INT_PCI_INTD)
-#define M_INT_SPARE_2               _SB_MAKEMASK1(K_INT_SPARE_2)
+#define M_INT_GPIO_0               _SB_MAKEMASK1(K_INT_GPIO_0)
+#define M_INT_GPIO_1               _SB_MAKEMASK1(K_INT_GPIO_1)
+#define M_INT_GPIO_2               _SB_MAKEMASK1(K_INT_GPIO_2)
+#define M_INT_GPIO_3               _SB_MAKEMASK1(K_INT_GPIO_3)
+#define M_INT_GPIO_4               _SB_MAKEMASK1(K_INT_GPIO_4)
+#define M_INT_GPIO_5               _SB_MAKEMASK1(K_INT_GPIO_5)
+#define M_INT_GPIO_6               _SB_MAKEMASK1(K_INT_GPIO_6)
+#define M_INT_GPIO_7               _SB_MAKEMASK1(K_INT_GPIO_7)
+#define M_INT_GPIO_8               _SB_MAKEMASK1(K_INT_GPIO_8)
+#define M_INT_GPIO_9               _SB_MAKEMASK1(K_INT_GPIO_9)
+#define M_INT_GPIO_10              _SB_MAKEMASK1(K_INT_GPIO_10)
+#define M_INT_GPIO_11              _SB_MAKEMASK1(K_INT_GPIO_11)
+#define M_INT_GPIO_12              _SB_MAKEMASK1(K_INT_GPIO_12)
+#define M_INT_GPIO_13              _SB_MAKEMASK1(K_INT_GPIO_13)
+#define M_INT_GPIO_14              _SB_MAKEMASK1(K_INT_GPIO_14)
+#define M_INT_GPIO_15              _SB_MAKEMASK1(K_INT_GPIO_15)
+#define M_INT_LDT_FATAL                    _SB_MAKEMASK1(K_INT_LDT_FATAL)
+#define M_INT_LDT_NONFATAL         _SB_MAKEMASK1(K_INT_LDT_NONFATAL)
+#define M_INT_LDT_SMI              _SB_MAKEMASK1(K_INT_LDT_SMI)
+#define M_INT_LDT_NMI              _SB_MAKEMASK1(K_INT_LDT_NMI)
+#define M_INT_LDT_INIT             _SB_MAKEMASK1(K_INT_LDT_INIT)
+#define M_INT_LDT_STARTUP          _SB_MAKEMASK1(K_INT_LDT_STARTUP)
+#define M_INT_LDT_EXT              _SB_MAKEMASK1(K_INT_LDT_EXT)
+#define M_INT_PCI_ERROR                    _SB_MAKEMASK1(K_INT_PCI_ERROR)
+#define M_INT_PCI_INTA             _SB_MAKEMASK1(K_INT_PCI_INTA)
+#define M_INT_PCI_INTB             _SB_MAKEMASK1(K_INT_PCI_INTB)
+#define M_INT_PCI_INTC             _SB_MAKEMASK1(K_INT_PCI_INTC)
+#define M_INT_PCI_INTD             _SB_MAKEMASK1(K_INT_PCI_INTD)
+#define M_INT_SPARE_2              _SB_MAKEMASK1(K_INT_SPARE_2)

 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define M_INT_MAC_0_CH1                    _SB_MAKEMASK1(K_INT_MAC_0_CH1)
 #define M_INT_MAC_1_CH1                    _SB_MAKEMASK1(K_INT_MAC_1_CH1)
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define M_INT_MAC_0_CH1                    _SB_MAKEMASK1(K_INT_MAC_0_CH1)
 #define M_INT_MAC_1_CH1                    _SB_MAKEMASK1(K_INT_MAC_1_CH1)


@@ -208,9 +208,9 @@
  */
 
 #define S_INT_LDT_INTMSG             0
  */
 
 #define S_INT_LDT_INTMSG             0

-#define M_INT_LDT_INTMSG              _SB_MAKEMASK(3, S_INT_LDT_INTMSG)
-#define V_INT_LDT_INTMSG(x)           _SB_MAKEVALUE(x, S_INT_LDT_INTMSG)
-#define G_INT_LDT_INTMSG(x)           _SB_GETVALUE(x, S_INT_LDT_INTMSG, M_INT_LDT_INTMSG)
+#define M_INT_LDT_INTMSG             _SB_MAKEMASK(3, S_INT_LDT_INTMSG)
+#define V_INT_LDT_INTMSG(x)          _SB_MAKEVALUE(x, S_INT_LDT_INTMSG)
+#define G_INT_LDT_INTMSG(x)          _SB_GETVALUE(x, S_INT_LDT_INTMSG, M_INT_LDT_INTMSG)

 
 #define K_INT_LDT_INTMSG_FIXED       0
 #define K_INT_LDT_INTMSG_ARBITRATED   1
 
 #define K_INT_LDT_INTMSG_FIXED       0
 #define K_INT_LDT_INTMSG_ARBITRATED   1


@@ -221,28 +221,28 @@
 #define K_INT_LDT_INTMSG_EXTINT              6
 #define K_INT_LDT_INTMSG_RESERVED     7
 
 #define K_INT_LDT_INTMSG_EXTINT              6
 #define K_INT_LDT_INTMSG_RESERVED     7
 

-#define M_INT_LDT_EDGETRIGGER         0
-#define M_INT_LDT_LEVELTRIGGER        _SB_MAKEMASK1(3)
+#define M_INT_LDT_EDGETRIGGER        0
+#define M_INT_LDT_LEVELTRIGGER       _SB_MAKEMASK1(3)

 
 

-#define M_INT_LDT_PHYSICALDEST        0
-#define M_INT_LDT_LOGICALDEST         _SB_MAKEMASK1(4)
+#define M_INT_LDT_PHYSICALDEST       0
+#define M_INT_LDT_LOGICALDEST        _SB_MAKEMASK1(4)

 
 

-#define S_INT_LDT_INTDEST             5
-#define M_INT_LDT_INTDEST             _SB_MAKEMASK(10, S_INT_LDT_INTDEST)
-#define V_INT_LDT_INTDEST(x)          _SB_MAKEVALUE(x, S_INT_LDT_INTDEST)
-#define G_INT_LDT_INTDEST(x)          _SB_GETVALUE(x, S_INT_LDT_INTDEST, M_INT_LDT_INTDEST)
+#define S_INT_LDT_INTDEST            5
+#define M_INT_LDT_INTDEST            _SB_MAKEMASK(10, S_INT_LDT_INTDEST)
+#define V_INT_LDT_INTDEST(x)         _SB_MAKEVALUE(x, S_INT_LDT_INTDEST)
+#define G_INT_LDT_INTDEST(x)         _SB_GETVALUE(x, S_INT_LDT_INTDEST, M_INT_LDT_INTDEST)

 
 

-#define S_INT_LDT_VECTOR              13
-#define M_INT_LDT_VECTOR              _SB_MAKEMASK(8, S_INT_LDT_VECTOR)
-#define V_INT_LDT_VECTOR(x)           _SB_MAKEVALUE(x, S_INT_LDT_VECTOR)
-#define G_INT_LDT_VECTOR(x)           _SB_GETVALUE(x, S_INT_LDT_VECTOR, M_INT_LDT_VECTOR)
+#define S_INT_LDT_VECTOR             13
+#define M_INT_LDT_VECTOR             _SB_MAKEMASK(8, S_INT_LDT_VECTOR)
+#define V_INT_LDT_VECTOR(x)          _SB_MAKEVALUE(x, S_INT_LDT_VECTOR)
+#define G_INT_LDT_VECTOR(x)          _SB_GETVALUE(x, S_INT_LDT_VECTOR, M_INT_LDT_VECTOR)

 
 /*
  * Vector format (Table 4-6)
  */
 
 #define M_LDTVECT_RAISEINT             0x00
 
 /*
  * Vector format (Table 4-6)
  */
 
 #define M_LDTVECT_RAISEINT             0x00

-#define M_LDTVECT_RAISEMBOX             0x40
+#define M_LDTVECT_RAISEMBOX            0x40

 
 
 #endif /* 1250/112x */
 
 
 #endif /* 1250/112x */

diff --git a/arch/mips/include/asm/sibyte/sb1250_l2c.h b/arch/mips/include/asm/sibyte/sb1250_l2c.h
index b61a7491607dc26083d2eae69e8c1d6c07140ab1..30092d7cfdc23d67f5dc4606166eb06e5c7f1967 100644 (file)
--- a/arch/mips/include/asm/sibyte/sb1250_l2c.h
+++ b/arch/mips/include/asm/sibyte/sb1250_l2c.h
@@ -39,71 +39,71 @@
  * Level 2 Cache Tag register (Table 5-3)
  */
 
  * Level 2 Cache Tag register (Table 5-3)
  */
 

-#define S_L2C_TAG_MBZ               0
-#define M_L2C_TAG_MBZ               _SB_MAKEMASK(5, S_L2C_TAG_MBZ)
+#define S_L2C_TAG_MBZ              0
+#define M_L2C_TAG_MBZ              _SB_MAKEMASK(5, S_L2C_TAG_MBZ)

 
 

-#define S_L2C_TAG_INDEX             5
-#define M_L2C_TAG_INDEX             _SB_MAKEMASK(12, S_L2C_TAG_INDEX)
-#define V_L2C_TAG_INDEX(x)          _SB_MAKEVALUE(x, S_L2C_TAG_INDEX)
-#define G_L2C_TAG_INDEX(x)          _SB_GETVALUE(x, S_L2C_TAG_INDEX, M_L2C_TAG_INDEX)
+#define S_L2C_TAG_INDEX                    5
+#define M_L2C_TAG_INDEX                    _SB_MAKEMASK(12, S_L2C_TAG_INDEX)
+#define V_L2C_TAG_INDEX(x)         _SB_MAKEVALUE(x, S_L2C_TAG_INDEX)
+#define G_L2C_TAG_INDEX(x)         _SB_GETVALUE(x, S_L2C_TAG_INDEX, M_L2C_TAG_INDEX)

 
 

-#define S_L2C_TAG_TAG               17
-#define M_L2C_TAG_TAG               _SB_MAKEMASK(23, S_L2C_TAG_TAG)
-#define V_L2C_TAG_TAG(x)            _SB_MAKEVALUE(x, S_L2C_TAG_TAG)
-#define G_L2C_TAG_TAG(x)            _SB_GETVALUE(x, S_L2C_TAG_TAG, M_L2C_TAG_TAG)
+#define S_L2C_TAG_TAG              17
+#define M_L2C_TAG_TAG              _SB_MAKEMASK(23, S_L2C_TAG_TAG)
+#define V_L2C_TAG_TAG(x)           _SB_MAKEVALUE(x, S_L2C_TAG_TAG)
+#define G_L2C_TAG_TAG(x)           _SB_GETVALUE(x, S_L2C_TAG_TAG, M_L2C_TAG_TAG)

 
 

-#define S_L2C_TAG_ECC               40
-#define M_L2C_TAG_ECC               _SB_MAKEMASK(6, S_L2C_TAG_ECC)
-#define V_L2C_TAG_ECC(x)            _SB_MAKEVALUE(x, S_L2C_TAG_ECC)
-#define G_L2C_TAG_ECC(x)            _SB_GETVALUE(x, S_L2C_TAG_ECC, M_L2C_TAG_ECC)
+#define S_L2C_TAG_ECC              40
+#define M_L2C_TAG_ECC              _SB_MAKEMASK(6, S_L2C_TAG_ECC)
+#define V_L2C_TAG_ECC(x)           _SB_MAKEVALUE(x, S_L2C_TAG_ECC)
+#define G_L2C_TAG_ECC(x)           _SB_GETVALUE(x, S_L2C_TAG_ECC, M_L2C_TAG_ECC)

 
 

-#define S_L2C_TAG_WAY               46
-#define M_L2C_TAG_WAY               _SB_MAKEMASK(2, S_L2C_TAG_WAY)
-#define V_L2C_TAG_WAY(x)            _SB_MAKEVALUE(x, S_L2C_TAG_WAY)
-#define G_L2C_TAG_WAY(x)            _SB_GETVALUE(x, S_L2C_TAG_WAY, M_L2C_TAG_WAY)
+#define S_L2C_TAG_WAY              46
+#define M_L2C_TAG_WAY              _SB_MAKEMASK(2, S_L2C_TAG_WAY)
+#define V_L2C_TAG_WAY(x)           _SB_MAKEVALUE(x, S_L2C_TAG_WAY)
+#define G_L2C_TAG_WAY(x)           _SB_GETVALUE(x, S_L2C_TAG_WAY, M_L2C_TAG_WAY)

 
 

-#define M_L2C_TAG_DIRTY             _SB_MAKEMASK1(48)
-#define M_L2C_TAG_VALID             _SB_MAKEMASK1(49)
+#define M_L2C_TAG_DIRTY                    _SB_MAKEMASK1(48)
+#define M_L2C_TAG_VALID                    _SB_MAKEMASK1(49)

 
 /*
  * Format of level 2 cache management address (table 5-2)
  */
 
 
 /*
  * Format of level 2 cache management address (table 5-2)
  */
 

-#define S_L2C_MGMT_INDEX            5
-#define M_L2C_MGMT_INDEX            _SB_MAKEMASK(12, S_L2C_MGMT_INDEX)
-#define V_L2C_MGMT_INDEX(x)         _SB_MAKEVALUE(x, S_L2C_MGMT_INDEX)
-#define G_L2C_MGMT_INDEX(x)         _SB_GETVALUE(x, S_L2C_MGMT_INDEX, M_L2C_MGMT_INDEX)
+#define S_L2C_MGMT_INDEX           5
+#define M_L2C_MGMT_INDEX           _SB_MAKEMASK(12, S_L2C_MGMT_INDEX)
+#define V_L2C_MGMT_INDEX(x)        _SB_MAKEVALUE(x, S_L2C_MGMT_INDEX)
+#define G_L2C_MGMT_INDEX(x)        _SB_GETVALUE(x, S_L2C_MGMT_INDEX, M_L2C_MGMT_INDEX)

 
 

-#define S_L2C_MGMT_QUADRANT         15
-#define M_L2C_MGMT_QUADRANT         _SB_MAKEMASK(2, S_L2C_MGMT_QUADRANT)
-#define V_L2C_MGMT_QUADRANT(x)      _SB_MAKEVALUE(x, S_L2C_MGMT_QUADRANT)
-#define G_L2C_MGMT_QUADRANT(x)      _SB_GETVALUE(x, S_L2C_MGMT_QUADRANT, M_L2C_MGMT_QUADRANT)
+#define S_L2C_MGMT_QUADRANT        15
+#define M_L2C_MGMT_QUADRANT        _SB_MAKEMASK(2, S_L2C_MGMT_QUADRANT)
+#define V_L2C_MGMT_QUADRANT(x)     _SB_MAKEVALUE(x, S_L2C_MGMT_QUADRANT)
+#define G_L2C_MGMT_QUADRANT(x)     _SB_GETVALUE(x, S_L2C_MGMT_QUADRANT, M_L2C_MGMT_QUADRANT)

 
 #define S_L2C_MGMT_HALF                    16
 
 #define S_L2C_MGMT_HALF                    16

-#define M_L2C_MGMT_HALF                    _SB_MAKEMASK(1, S_L2C_MGMT_HALF)
+#define M_L2C_MGMT_HALF                    _SB_MAKEMASK(1, S_L2C_MGMT_HALF)

 
 

-#define S_L2C_MGMT_WAY              17
-#define M_L2C_MGMT_WAY              _SB_MAKEMASK(2, S_L2C_MGMT_WAY)
-#define V_L2C_MGMT_WAY(x)           _SB_MAKEVALUE(x, S_L2C_MGMT_WAY)
-#define G_L2C_MGMT_WAY(x)           _SB_GETVALUE(x, S_L2C_MGMT_WAY, M_L2C_MGMT_WAY)
+#define S_L2C_MGMT_WAY             17
+#define M_L2C_MGMT_WAY             _SB_MAKEMASK(2, S_L2C_MGMT_WAY)
+#define V_L2C_MGMT_WAY(x)          _SB_MAKEVALUE(x, S_L2C_MGMT_WAY)
+#define G_L2C_MGMT_WAY(x)          _SB_GETVALUE(x, S_L2C_MGMT_WAY, M_L2C_MGMT_WAY)

 
 

-#define S_L2C_MGMT_ECC_DIAG         21
-#define M_L2C_MGMT_ECC_DIAG         _SB_MAKEMASK(2, S_L2C_MGMT_ECC_DIAG)
-#define V_L2C_MGMT_ECC_DIAG(x)      _SB_MAKEVALUE(x, S_L2C_MGMT_ECC_DIAG)
-#define G_L2C_MGMT_ECC_DIAG(x)      _SB_GETVALUE(x, S_L2C_MGMT_ECC_DIAG, M_L2C_MGMT_ECC_DIAG)
+#define S_L2C_MGMT_ECC_DIAG        21
+#define M_L2C_MGMT_ECC_DIAG        _SB_MAKEMASK(2, S_L2C_MGMT_ECC_DIAG)
+#define V_L2C_MGMT_ECC_DIAG(x)     _SB_MAKEVALUE(x, S_L2C_MGMT_ECC_DIAG)
+#define G_L2C_MGMT_ECC_DIAG(x)     _SB_GETVALUE(x, S_L2C_MGMT_ECC_DIAG, M_L2C_MGMT_ECC_DIAG)

 
 

-#define S_L2C_MGMT_TAG              23
-#define M_L2C_MGMT_TAG              _SB_MAKEMASK(4, S_L2C_MGMT_TAG)
-#define V_L2C_MGMT_TAG(x)           _SB_MAKEVALUE(x, S_L2C_MGMT_TAG)
-#define G_L2C_MGMT_TAG(x)           _SB_GETVALUE(x, S_L2C_MGMT_TAG, M_L2C_MGMT_TAG)
+#define S_L2C_MGMT_TAG             23
+#define M_L2C_MGMT_TAG             _SB_MAKEMASK(4, S_L2C_MGMT_TAG)
+#define V_L2C_MGMT_TAG(x)          _SB_MAKEVALUE(x, S_L2C_MGMT_TAG)
+#define G_L2C_MGMT_TAG(x)          _SB_GETVALUE(x, S_L2C_MGMT_TAG, M_L2C_MGMT_TAG)

 
 

-#define M_L2C_MGMT_DIRTY            _SB_MAKEMASK1(19)
-#define M_L2C_MGMT_VALID            _SB_MAKEMASK1(20)
+#define M_L2C_MGMT_DIRTY           _SB_MAKEMASK1(19)
+#define M_L2C_MGMT_VALID           _SB_MAKEMASK1(20)

 
 

-#define A_L2C_MGMT_TAG_BASE         0x00D0000000
+#define A_L2C_MGMT_TAG_BASE        0x00D0000000

 
 

-#define L2C_ENTRIES_PER_WAY       4096
-#define L2C_NUM_WAYS              4
+#define L2C_ENTRIES_PER_WAY      4096
+#define L2C_NUM_WAYS             4

 
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)

diff --git a/arch/mips/include/asm/sibyte/sb1250_ldt.h b/arch/mips/include/asm/sibyte/sb1250_ldt.h
index bf7f320d1a871524e520c6a6b156291c22e192b8..2340c29dc0c7013c83c77b373a4e8962c145aacd 100644 (file)
--- a/arch/mips/include/asm/sibyte/sb1250_ldt.h
+++ b/arch/mips/include/asm/sibyte/sb1250_ldt.h
@@ -66,7 +66,7 @@
 #define R_LDT_TYPE1_SRICMD     0x0050
 #define R_LDT_TYPE1_SRITXNUM   0x0054
 #define R_LDT_TYPE1_SRIRXNUM   0x0058
 #define R_LDT_TYPE1_SRICMD     0x0050
 #define R_LDT_TYPE1_SRITXNUM   0x0054
 #define R_LDT_TYPE1_SRIRXNUM   0x0058

-#define R_LDT_TYPE1_ERRSTATUS   0x0068
+#define R_LDT_TYPE1_ERRSTATUS  0x0068

 #define R_LDT_TYPE1_SRICTRL    0x006C
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define R_LDT_TYPE1_ADDSTATUS  0x0070
 #define R_LDT_TYPE1_SRICTRL    0x006C
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define R_LDT_TYPE1_ADDSTATUS  0x0070


@@ -258,7 +258,7 @@
 #define M_LDT_LINKCTRL_DWFCOUT_EN      _SB_MAKEMASK1_32(31)
 
 /*
 #define M_LDT_LINKCTRL_DWFCOUT_EN      _SB_MAKEMASK1_32(31)
 
 /*

- * LDT Link frequency register  (Table 8-20) offset 0x48
+ * LDT Link frequency register (Table 8-20) offset 0x48

  */
 
 #define S_LDT_LINKFREQ_FREQ            8
  */
 
 #define S_LDT_LINKFREQ_FREQ            8


@@ -301,8 +301,8 @@
 
 #define S_LDT_SRICMD_TXINITIALOFFSET   28
 #define M_LDT_SRICMD_TXINITIALOFFSET   _SB_MAKEMASK_32(3, S_LDT_SRICMD_TXINITIALOFFSET)
 
 #define S_LDT_SRICMD_TXINITIALOFFSET   28
 #define M_LDT_SRICMD_TXINITIALOFFSET   _SB_MAKEMASK_32(3, S_LDT_SRICMD_TXINITIALOFFSET)

-#define V_LDT_SRICMD_TXINITIALOFFSET(x)        _SB_MAKEVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET)
-#define G_LDT_SRICMD_TXINITIALOFFSET(x)        _SB_GETVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET, M_LDT_SRICMD_TXINITIALOFFSET)
+#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET)
+#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET, M_LDT_SRICMD_TXINITIALOFFSET)

 
 #define M_LDT_SRICMD_LINKFREQDIRECT    _SB_MAKEMASK1_32(31)
 
 
 #define M_LDT_SRICMD_LINKFREQDIRECT    _SB_MAKEMASK1_32(31)
 


@@ -318,16 +318,16 @@
 #define M_LDT_ERRCTL_OVFSYNCFLOOD_EN   _SB_MAKEMASK1_32(5)
 #define M_LDT_ERRCTL_EOCNXAFATAL_EN    _SB_MAKEMASK1_32(6)
 #define M_LDT_ERRCTL_EOCNXANONFATAL_EN _SB_MAKEMASK1_32(7)
 #define M_LDT_ERRCTL_OVFSYNCFLOOD_EN   _SB_MAKEMASK1_32(5)
 #define M_LDT_ERRCTL_EOCNXAFATAL_EN    _SB_MAKEMASK1_32(6)
 #define M_LDT_ERRCTL_EOCNXANONFATAL_EN _SB_MAKEMASK1_32(7)

-#define M_LDT_ERRCTL_EOCNXASYNCFLOOD_EN        _SB_MAKEMASK1_32(8)
+#define M_LDT_ERRCTL_EOCNXASYNCFLOOD_EN _SB_MAKEMASK1_32(8)

 #define M_LDT_ERRCTL_CRCFATAL_EN       _SB_MAKEMASK1_32(9)
 #define M_LDT_ERRCTL_CRCNONFATAL_EN    _SB_MAKEMASK1_32(10)
 #define M_LDT_ERRCTL_SERRFATAL_EN      _SB_MAKEMASK1_32(11)
 #define M_LDT_ERRCTL_SRCTAGFATAL_EN    _SB_MAKEMASK1_32(12)
 #define M_LDT_ERRCTL_SRCTAGNONFATAL_EN _SB_MAKEMASK1_32(13)
 #define M_LDT_ERRCTL_CRCFATAL_EN       _SB_MAKEMASK1_32(9)
 #define M_LDT_ERRCTL_CRCNONFATAL_EN    _SB_MAKEMASK1_32(10)
 #define M_LDT_ERRCTL_SERRFATAL_EN      _SB_MAKEMASK1_32(11)
 #define M_LDT_ERRCTL_SRCTAGFATAL_EN    _SB_MAKEMASK1_32(12)
 #define M_LDT_ERRCTL_SRCTAGNONFATAL_EN _SB_MAKEMASK1_32(13)

-#define M_LDT_ERRCTL_SRCTAGSYNCFLOOD_EN        _SB_MAKEMASK1_32(14)
+#define M_LDT_ERRCTL_SRCTAGSYNCFLOOD_EN _SB_MAKEMASK1_32(14)

 #define M_LDT_ERRCTL_MAPNXAFATAL_EN    _SB_MAKEMASK1_32(15)
 #define M_LDT_ERRCTL_MAPNXANONFATAL_EN _SB_MAKEMASK1_32(16)
 #define M_LDT_ERRCTL_MAPNXAFATAL_EN    _SB_MAKEMASK1_32(15)
 #define M_LDT_ERRCTL_MAPNXANONFATAL_EN _SB_MAKEMASK1_32(16)

-#define M_LDT_ERRCTL_MAPNXASYNCFLOOD_EN        _SB_MAKEMASK1_32(17)
+#define M_LDT_ERRCTL_MAPNXASYNCFLOOD_EN _SB_MAKEMASK1_32(17)

 
 #define M_LDT_ERRCTL_PROTOERR          _SB_MAKEMASK1_32(24)
 #define M_LDT_ERRCTL_OVFERR            _SB_MAKEMASK1_32(25)
 
 #define M_LDT_ERRCTL_PROTOERR          _SB_MAKEMASK1_32(24)
 #define M_LDT_ERRCTL_OVFERR            _SB_MAKEMASK1_32(25)

diff --git a/arch/mips/include/asm/sibyte/sb1250_mac.h b/arch/mips/include/asm/sibyte/sb1250_mac.h
index cfc4d78708821e7fabc8dfda01d84a8bac65ecec..3fa94fc740426294cf992e08373dfe2e3dd991c5 100644 (file)
--- a/arch/mips/include/asm/sibyte/sb1250_mac.h
+++ b/arch/mips/include/asm/sibyte/sb1250_mac.h
@@ -47,86 +47,86 @@
  */
 
 
  */
 
 

-#define M_MAC_RESERVED0             _SB_MAKEMASK1(0)
-#define M_MAC_TX_HOLD_SOP_EN        _SB_MAKEMASK1(1)
-#define M_MAC_RETRY_EN              _SB_MAKEMASK1(2)
-#define M_MAC_RET_DRPREQ_EN         _SB_MAKEMASK1(3)
-#define M_MAC_RET_UFL_EN            _SB_MAKEMASK1(4)
-#define M_MAC_BURST_EN              _SB_MAKEMASK1(5)
-
-#define S_MAC_TX_PAUSE              _SB_MAKE64(6)
-#define M_MAC_TX_PAUSE_CNT          _SB_MAKEMASK(3, S_MAC_TX_PAUSE)
-#define V_MAC_TX_PAUSE_CNT(x)       _SB_MAKEVALUE(x, S_MAC_TX_PAUSE)
-
-#define K_MAC_TX_PAUSE_CNT_512      0
-#define K_MAC_TX_PAUSE_CNT_1K       1
-#define K_MAC_TX_PAUSE_CNT_2K       2
-#define K_MAC_TX_PAUSE_CNT_4K       3
-#define K_MAC_TX_PAUSE_CNT_8K       4
-#define K_MAC_TX_PAUSE_CNT_16K      5
-#define K_MAC_TX_PAUSE_CNT_32K      6
-#define K_MAC_TX_PAUSE_CNT_64K      7
-
-#define V_MAC_TX_PAUSE_CNT_512      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512)
-#define V_MAC_TX_PAUSE_CNT_1K       V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K)
-#define V_MAC_TX_PAUSE_CNT_2K       V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K)
-#define V_MAC_TX_PAUSE_CNT_4K       V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K)
-#define V_MAC_TX_PAUSE_CNT_8K       V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K)
-#define V_MAC_TX_PAUSE_CNT_16K      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K)
-#define V_MAC_TX_PAUSE_CNT_32K      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K)
-#define V_MAC_TX_PAUSE_CNT_64K      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K)
-
-#define M_MAC_RESERVED1             _SB_MAKEMASK(8, 9)
-
-#define M_MAC_AP_STAT_EN            _SB_MAKEMASK1(17)
+#define M_MAC_RESERVED0                    _SB_MAKEMASK1(0)
+#define M_MAC_TX_HOLD_SOP_EN       _SB_MAKEMASK1(1)
+#define M_MAC_RETRY_EN             _SB_MAKEMASK1(2)
+#define M_MAC_RET_DRPREQ_EN        _SB_MAKEMASK1(3)
+#define M_MAC_RET_UFL_EN           _SB_MAKEMASK1(4)
+#define M_MAC_BURST_EN             _SB_MAKEMASK1(5)
+
+#define S_MAC_TX_PAUSE             _SB_MAKE64(6)
+#define M_MAC_TX_PAUSE_CNT         _SB_MAKEMASK(3, S_MAC_TX_PAUSE)
+#define V_MAC_TX_PAUSE_CNT(x)      _SB_MAKEVALUE(x, S_MAC_TX_PAUSE)
+
+#define K_MAC_TX_PAUSE_CNT_512     0
+#define K_MAC_TX_PAUSE_CNT_1K      1
+#define K_MAC_TX_PAUSE_CNT_2K      2
+#define K_MAC_TX_PAUSE_CNT_4K      3
+#define K_MAC_TX_PAUSE_CNT_8K      4
+#define K_MAC_TX_PAUSE_CNT_16K     5
+#define K_MAC_TX_PAUSE_CNT_32K     6
+#define K_MAC_TX_PAUSE_CNT_64K     7
+
+#define V_MAC_TX_PAUSE_CNT_512     V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512)
+#define V_MAC_TX_PAUSE_CNT_1K      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K)
+#define V_MAC_TX_PAUSE_CNT_2K      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K)
+#define V_MAC_TX_PAUSE_CNT_4K      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K)
+#define V_MAC_TX_PAUSE_CNT_8K      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K)
+#define V_MAC_TX_PAUSE_CNT_16K     V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K)
+#define V_MAC_TX_PAUSE_CNT_32K     V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K)
+#define V_MAC_TX_PAUSE_CNT_64K     V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K)
+
+#define M_MAC_RESERVED1                    _SB_MAKEMASK(8, 9)
+
+#define M_MAC_AP_STAT_EN           _SB_MAKEMASK1(17)

 
 #if SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_MAC_TIMESTAMP                    _SB_MAKEMASK1(18)
 #endif
 
 #if SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_MAC_TIMESTAMP                    _SB_MAKEMASK1(18)
 #endif

-#define M_MAC_DRP_ERRPKT_EN         _SB_MAKEMASK1(19)
-#define M_MAC_DRP_FCSERRPKT_EN      _SB_MAKEMASK1(20)
-#define M_MAC_DRP_CODEERRPKT_EN     _SB_MAKEMASK1(21)
-#define M_MAC_DRP_DRBLERRPKT_EN     _SB_MAKEMASK1(22)
-#define M_MAC_DRP_RNTPKT_EN         _SB_MAKEMASK1(23)
-#define M_MAC_DRP_OSZPKT_EN         _SB_MAKEMASK1(24)
-#define M_MAC_DRP_LENERRPKT_EN      _SB_MAKEMASK1(25)
+#define M_MAC_DRP_ERRPKT_EN        _SB_MAKEMASK1(19)
+#define M_MAC_DRP_FCSERRPKT_EN     _SB_MAKEMASK1(20)
+#define M_MAC_DRP_CODEERRPKT_EN            _SB_MAKEMASK1(21)
+#define M_MAC_DRP_DRBLERRPKT_EN            _SB_MAKEMASK1(22)
+#define M_MAC_DRP_RNTPKT_EN        _SB_MAKEMASK1(23)
+#define M_MAC_DRP_OSZPKT_EN        _SB_MAKEMASK1(24)
+#define M_MAC_DRP_LENERRPKT_EN     _SB_MAKEMASK1(25)

 
 

-#define M_MAC_RESERVED3             _SB_MAKEMASK(6, 26)
+#define M_MAC_RESERVED3                    _SB_MAKEMASK(6, 26)

 
 

-#define M_MAC_BYPASS_SEL            _SB_MAKEMASK1(32)
-#define M_MAC_HDX_EN                _SB_MAKEMASK1(33)
+#define M_MAC_BYPASS_SEL           _SB_MAKEMASK1(32)
+#define M_MAC_HDX_EN               _SB_MAKEMASK1(33)

 
 

-#define S_MAC_SPEED_SEL             _SB_MAKE64(34)
-#define M_MAC_SPEED_SEL             _SB_MAKEMASK(2, S_MAC_SPEED_SEL)
+#define S_MAC_SPEED_SEL                    _SB_MAKE64(34)
+#define M_MAC_SPEED_SEL                    _SB_MAKEMASK(2, S_MAC_SPEED_SEL)

 #define V_MAC_SPEED_SEL(x)         _SB_MAKEVALUE(x, S_MAC_SPEED_SEL)
 #define G_MAC_SPEED_SEL(x)         _SB_GETVALUE(x, S_MAC_SPEED_SEL, M_MAC_SPEED_SEL)
 
 #define V_MAC_SPEED_SEL(x)         _SB_MAKEVALUE(x, S_MAC_SPEED_SEL)
 #define G_MAC_SPEED_SEL(x)         _SB_GETVALUE(x, S_MAC_SPEED_SEL, M_MAC_SPEED_SEL)
 

-#define K_MAC_SPEED_SEL_10MBPS      0
-#define K_MAC_SPEED_SEL_100MBPS     1
+#define K_MAC_SPEED_SEL_10MBPS     0
+#define K_MAC_SPEED_SEL_100MBPS            1

 #define K_MAC_SPEED_SEL_1000MBPS    2
 #define K_MAC_SPEED_SEL_RESERVED    3
 
 #define K_MAC_SPEED_SEL_1000MBPS    2
 #define K_MAC_SPEED_SEL_RESERVED    3
 

-#define V_MAC_SPEED_SEL_10MBPS      V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS)
-#define V_MAC_SPEED_SEL_100MBPS     V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS)
+#define V_MAC_SPEED_SEL_10MBPS     V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS)
+#define V_MAC_SPEED_SEL_100MBPS            V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS)

 #define V_MAC_SPEED_SEL_1000MBPS    V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_1000MBPS)
 #define V_MAC_SPEED_SEL_RESERVED    V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_RESERVED)
 
 #define V_MAC_SPEED_SEL_1000MBPS    V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_1000MBPS)
 #define V_MAC_SPEED_SEL_RESERVED    V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_RESERVED)
 

-#define M_MAC_TX_CLK_EDGE_SEL       _SB_MAKEMASK1(36)
-#define M_MAC_LOOPBACK_SEL          _SB_MAKEMASK1(37)
-#define M_MAC_FAST_SYNC             _SB_MAKEMASK1(38)
-#define M_MAC_SS_EN                 _SB_MAKEMASK1(39)
+#define M_MAC_TX_CLK_EDGE_SEL      _SB_MAKEMASK1(36)
+#define M_MAC_LOOPBACK_SEL         _SB_MAKEMASK1(37)
+#define M_MAC_FAST_SYNC                    _SB_MAKEMASK1(38)
+#define M_MAC_SS_EN                _SB_MAKEMASK1(39)

 
 #define S_MAC_BYPASS_CFG           _SB_MAKE64(40)
 
 #define S_MAC_BYPASS_CFG           _SB_MAKE64(40)

-#define M_MAC_BYPASS_CFG            _SB_MAKEMASK(2, S_MAC_BYPASS_CFG)
-#define V_MAC_BYPASS_CFG(x)         _SB_MAKEVALUE(x, S_MAC_BYPASS_CFG)
-#define G_MAC_BYPASS_CFG(x)         _SB_GETVALUE(x, S_MAC_BYPASS_CFG, M_MAC_BYPASS_CFG)
+#define M_MAC_BYPASS_CFG           _SB_MAKEMASK(2, S_MAC_BYPASS_CFG)
+#define V_MAC_BYPASS_CFG(x)        _SB_MAKEVALUE(x, S_MAC_BYPASS_CFG)
+#define G_MAC_BYPASS_CFG(x)        _SB_GETVALUE(x, S_MAC_BYPASS_CFG, M_MAC_BYPASS_CFG)

 
 #define K_MAC_BYPASS_GMII          0
 
 #define K_MAC_BYPASS_GMII          0

-#define K_MAC_BYPASS_ENCODED        1
-#define K_MAC_BYPASS_SOP            2
-#define K_MAC_BYPASS_EOP            3
+#define K_MAC_BYPASS_ENCODED       1
+#define K_MAC_BYPASS_SOP           2
+#define K_MAC_BYPASS_EOP           3

 
 

-#define M_MAC_BYPASS_16             _SB_MAKEMASK1(42)
+#define M_MAC_BYPASS_16                    _SB_MAKEMASK1(42)

 #define M_MAC_BYPASS_FCS_CHK       _SB_MAKEMASK1(43)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_MAC_BYPASS_FCS_CHK       _SB_MAKEMASK1(43)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)


@@ -137,30 +137,30 @@
 #define M_MAC_SPLIT_CH_SEL         _SB_MAKEMASK1(45)
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 #define M_MAC_SPLIT_CH_SEL         _SB_MAKEMASK1(45)
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 

-#define S_MAC_BYPASS_IFG            _SB_MAKE64(46)
-#define M_MAC_BYPASS_IFG            _SB_MAKEMASK(8, S_MAC_BYPASS_IFG)
+#define S_MAC_BYPASS_IFG           _SB_MAKE64(46)
+#define M_MAC_BYPASS_IFG           _SB_MAKEMASK(8, S_MAC_BYPASS_IFG)

 #define V_MAC_BYPASS_IFG(x)        _SB_MAKEVALUE(x, S_MAC_BYPASS_IFG)
 #define G_MAC_BYPASS_IFG(x)        _SB_GETVALUE(x, S_MAC_BYPASS_IFG, M_MAC_BYPASS_IFG)
 
 #define V_MAC_BYPASS_IFG(x)        _SB_MAKEVALUE(x, S_MAC_BYPASS_IFG)
 #define G_MAC_BYPASS_IFG(x)        _SB_GETVALUE(x, S_MAC_BYPASS_IFG, M_MAC_BYPASS_IFG)
 

-#define K_MAC_FC_CMD_DISABLED       0
-#define K_MAC_FC_CMD_ENABLED        1
+#define K_MAC_FC_CMD_DISABLED      0
+#define K_MAC_FC_CMD_ENABLED       1

 #define K_MAC_FC_CMD_ENAB_FALSECARR 2
 
 #define K_MAC_FC_CMD_ENAB_FALSECARR 2
 

-#define V_MAC_FC_CMD_DISABLED       V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED)
-#define V_MAC_FC_CMD_ENABLED        V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED)
+#define V_MAC_FC_CMD_DISABLED      V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED)
+#define V_MAC_FC_CMD_ENABLED       V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED)

 #define V_MAC_FC_CMD_ENAB_FALSECARR V_MAC_FC_CMD(K_MAC_FC_CMD_ENAB_FALSECARR)
 
 #define V_MAC_FC_CMD_ENAB_FALSECARR V_MAC_FC_CMD(K_MAC_FC_CMD_ENAB_FALSECARR)
 

-#define M_MAC_FC_SEL                _SB_MAKEMASK1(54)
+#define M_MAC_FC_SEL               _SB_MAKEMASK1(54)

 
 

-#define S_MAC_FC_CMD                _SB_MAKE64(55)
-#define M_MAC_FC_CMD                _SB_MAKEMASK(2, S_MAC_FC_CMD)
-#define V_MAC_FC_CMD(x)                    _SB_MAKEVALUE(x, S_MAC_FC_CMD)
-#define G_MAC_FC_CMD(x)                    _SB_GETVALUE(x, S_MAC_FC_CMD, M_MAC_FC_CMD)
+#define S_MAC_FC_CMD               _SB_MAKE64(55)
+#define M_MAC_FC_CMD               _SB_MAKEMASK(2, S_MAC_FC_CMD)
+#define V_MAC_FC_CMD(x)                    _SB_MAKEVALUE(x, S_MAC_FC_CMD)
+#define G_MAC_FC_CMD(x)                    _SB_GETVALUE(x, S_MAC_FC_CMD, M_MAC_FC_CMD)

 
 

-#define S_MAC_RX_CH_SEL             _SB_MAKE64(57)
-#define M_MAC_RX_CH_SEL             _SB_MAKEMASK(7, S_MAC_RX_CH_SEL)
-#define V_MAC_RX_CH_SEL(x)          _SB_MAKEVALUE(x, S_MAC_RX_CH_SEL)
-#define G_MAC_RX_CH_SEL(x)          _SB_GETVALUE(x, S_MAC_RX_CH_SEL, M_MAC_RX_CH_SEL)
+#define S_MAC_RX_CH_SEL                    _SB_MAKE64(57)
+#define M_MAC_RX_CH_SEL                    _SB_MAKEMASK(7, S_MAC_RX_CH_SEL)
+#define V_MAC_RX_CH_SEL(x)         _SB_MAKEVALUE(x, S_MAC_RX_CH_SEL)
+#define G_MAC_RX_CH_SEL(x)         _SB_GETVALUE(x, S_MAC_RX_CH_SEL, M_MAC_RX_CH_SEL)

 
 
 /*
 
 
 /*


@@ -170,18 +170,18 @@
  * Register: MAC_ENABLE_2
  */
 
  * Register: MAC_ENABLE_2
  */
 

-#define M_MAC_RXDMA_EN0                    _SB_MAKEMASK1(0)
-#define M_MAC_RXDMA_EN1                    _SB_MAKEMASK1(1)
-#define M_MAC_TXDMA_EN0                    _SB_MAKEMASK1(4)
-#define M_MAC_TXDMA_EN1                    _SB_MAKEMASK1(5)
+#define M_MAC_RXDMA_EN0                    _SB_MAKEMASK1(0)
+#define M_MAC_RXDMA_EN1                    _SB_MAKEMASK1(1)
+#define M_MAC_TXDMA_EN0                    _SB_MAKEMASK1(4)
+#define M_MAC_TXDMA_EN1                    _SB_MAKEMASK1(5)

 
 

-#define M_MAC_PORT_RESET            _SB_MAKEMASK1(8)
+#define M_MAC_PORT_RESET           _SB_MAKEMASK1(8)

 
 #if (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x))
 
 #if (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x))

-#define M_MAC_RX_ENABLE             _SB_MAKEMASK1(10)
-#define M_MAC_TX_ENABLE             _SB_MAKEMASK1(11)
-#define M_MAC_BYP_RX_ENABLE         _SB_MAKEMASK1(12)
-#define M_MAC_BYP_TX_ENABLE         _SB_MAKEMASK1(13)
+#define M_MAC_RX_ENABLE                    _SB_MAKEMASK1(10)
+#define M_MAC_TX_ENABLE                    _SB_MAKEMASK1(11)
+#define M_MAC_BYP_RX_ENABLE        _SB_MAKEMASK1(12)
+#define M_MAC_BYP_TX_ENABLE        _SB_MAKEMASK1(13)

 #endif
 
 /*
 #endif
 
 /*


@@ -203,13 +203,13 @@
 
 #define S_MAC_TXD_WEIGHT0          _SB_MAKE64(0)
 #define M_MAC_TXD_WEIGHT0          _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT0)
 
 #define S_MAC_TXD_WEIGHT0          _SB_MAKE64(0)
 #define M_MAC_TXD_WEIGHT0          _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT0)

-#define V_MAC_TXD_WEIGHT0(x)        _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT0)
-#define G_MAC_TXD_WEIGHT0(x)        _SB_GETVALUE(x, S_MAC_TXD_WEIGHT0, M_MAC_TXD_WEIGHT0)
+#define V_MAC_TXD_WEIGHT0(x)       _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT0)
+#define G_MAC_TXD_WEIGHT0(x)       _SB_GETVALUE(x, S_MAC_TXD_WEIGHT0, M_MAC_TXD_WEIGHT0)

 
 #define S_MAC_TXD_WEIGHT1          _SB_MAKE64(4)
 #define M_MAC_TXD_WEIGHT1          _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT1)
 
 #define S_MAC_TXD_WEIGHT1          _SB_MAKE64(4)
 #define M_MAC_TXD_WEIGHT1          _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT1)

-#define V_MAC_TXD_WEIGHT1(x)        _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT1)
-#define G_MAC_TXD_WEIGHT1(x)        _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1)
+#define V_MAC_TXD_WEIGHT1(x)       _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT1)
+#define G_MAC_TXD_WEIGHT1(x)       _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1)

 
 /*
  * MAC Fifo Threshold registers (Table 9-14)
 
 /*
  * MAC Fifo Threshold registers (Table 9-14)


@@ -218,53 +218,53 @@
  * Register: MAC_THRSH_CFG_2
  */
 
  * Register: MAC_THRSH_CFG_2
  */
 

-#define S_MAC_TX_WR_THRSH           _SB_MAKE64(0)
+#define S_MAC_TX_WR_THRSH          _SB_MAKE64(0)

 #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
 #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)

-/* XXX: Can't enable, as it has the same name as a pass2+ define below.  */
-/* #define M_MAC_TX_WR_THRSH           _SB_MAKEMASK(6, S_MAC_TX_WR_THRSH) */
+/* XXX: Can't enable, as it has the same name as a pass2+ define below.         */
+/* #define M_MAC_TX_WR_THRSH          _SB_MAKEMASK(6, S_MAC_TX_WR_THRSH) */

 #endif /* up to 1250 PASS1 */
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #endif /* up to 1250 PASS1 */
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)

-#define M_MAC_TX_WR_THRSH           _SB_MAKEMASK(7, S_MAC_TX_WR_THRSH)
+#define M_MAC_TX_WR_THRSH          _SB_MAKEMASK(7, S_MAC_TX_WR_THRSH)

 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */

-#define V_MAC_TX_WR_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_TX_WR_THRSH)
-#define G_MAC_TX_WR_THRSH(x)        _SB_GETVALUE(x, S_MAC_TX_WR_THRSH, M_MAC_TX_WR_THRSH)
+#define V_MAC_TX_WR_THRSH(x)       _SB_MAKEVALUE(x, S_MAC_TX_WR_THRSH)
+#define G_MAC_TX_WR_THRSH(x)       _SB_GETVALUE(x, S_MAC_TX_WR_THRSH, M_MAC_TX_WR_THRSH)

 
 

-#define S_MAC_TX_RD_THRSH           _SB_MAKE64(8)
+#define S_MAC_TX_RD_THRSH          _SB_MAKE64(8)

 #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
 #if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)

-/* XXX: Can't enable, as it has the same name as a pass2+ define below.  */
-/* #define M_MAC_TX_RD_THRSH           _SB_MAKEMASK(6, S_MAC_TX_RD_THRSH) */
+/* XXX: Can't enable, as it has the same name as a pass2+ define below.         */
+/* #define M_MAC_TX_RD_THRSH          _SB_MAKEMASK(6, S_MAC_TX_RD_THRSH) */

 #endif /* up to 1250 PASS1 */
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #endif /* up to 1250 PASS1 */
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)

-#define M_MAC_TX_RD_THRSH           _SB_MAKEMASK(7, S_MAC_TX_RD_THRSH)
+#define M_MAC_TX_RD_THRSH          _SB_MAKEMASK(7, S_MAC_TX_RD_THRSH)

 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */

-#define V_MAC_TX_RD_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_TX_RD_THRSH)
-#define G_MAC_TX_RD_THRSH(x)        _SB_GETVALUE(x, S_MAC_TX_RD_THRSH, M_MAC_TX_RD_THRSH)
+#define V_MAC_TX_RD_THRSH(x)       _SB_MAKEVALUE(x, S_MAC_TX_RD_THRSH)
+#define G_MAC_TX_RD_THRSH(x)       _SB_GETVALUE(x, S_MAC_TX_RD_THRSH, M_MAC_TX_RD_THRSH)

 
 

-#define S_MAC_TX_RL_THRSH           _SB_MAKE64(16)
-#define M_MAC_TX_RL_THRSH           _SB_MAKEMASK(4, S_MAC_TX_RL_THRSH)
-#define V_MAC_TX_RL_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_TX_RL_THRSH)
-#define G_MAC_TX_RL_THRSH(x)        _SB_GETVALUE(x, S_MAC_TX_RL_THRSH, M_MAC_TX_RL_THRSH)
+#define S_MAC_TX_RL_THRSH          _SB_MAKE64(16)
+#define M_MAC_TX_RL_THRSH          _SB_MAKEMASK(4, S_MAC_TX_RL_THRSH)
+#define V_MAC_TX_RL_THRSH(x)       _SB_MAKEVALUE(x, S_MAC_TX_RL_THRSH)
+#define G_MAC_TX_RL_THRSH(x)       _SB_GETVALUE(x, S_MAC_TX_RL_THRSH, M_MAC_TX_RL_THRSH)

 
 

-#define S_MAC_RX_PL_THRSH           _SB_MAKE64(24)
-#define M_MAC_RX_PL_THRSH           _SB_MAKEMASK(6, S_MAC_RX_PL_THRSH)
-#define V_MAC_RX_PL_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_RX_PL_THRSH)
-#define G_MAC_RX_PL_THRSH(x)        _SB_GETVALUE(x, S_MAC_RX_PL_THRSH, M_MAC_RX_PL_THRSH)
+#define S_MAC_RX_PL_THRSH          _SB_MAKE64(24)
+#define M_MAC_RX_PL_THRSH          _SB_MAKEMASK(6, S_MAC_RX_PL_THRSH)
+#define V_MAC_RX_PL_THRSH(x)       _SB_MAKEVALUE(x, S_MAC_RX_PL_THRSH)
+#define G_MAC_RX_PL_THRSH(x)       _SB_GETVALUE(x, S_MAC_RX_PL_THRSH, M_MAC_RX_PL_THRSH)

 
 

-#define S_MAC_RX_RD_THRSH           _SB_MAKE64(32)
-#define M_MAC_RX_RD_THRSH           _SB_MAKEMASK(6, S_MAC_RX_RD_THRSH)
-#define V_MAC_RX_RD_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_RX_RD_THRSH)
-#define G_MAC_RX_RD_THRSH(x)        _SB_GETVALUE(x, S_MAC_RX_RD_THRSH, M_MAC_RX_RD_THRSH)
+#define S_MAC_RX_RD_THRSH          _SB_MAKE64(32)
+#define M_MAC_RX_RD_THRSH          _SB_MAKEMASK(6, S_MAC_RX_RD_THRSH)
+#define V_MAC_RX_RD_THRSH(x)       _SB_MAKEVALUE(x, S_MAC_RX_RD_THRSH)
+#define G_MAC_RX_RD_THRSH(x)       _SB_GETVALUE(x, S_MAC_RX_RD_THRSH, M_MAC_RX_RD_THRSH)

 
 

-#define S_MAC_RX_RL_THRSH           _SB_MAKE64(40)
-#define M_MAC_RX_RL_THRSH           _SB_MAKEMASK(6, S_MAC_RX_RL_THRSH)
-#define V_MAC_RX_RL_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_RX_RL_THRSH)
-#define G_MAC_RX_RL_THRSH(x)        _SB_GETVALUE(x, S_MAC_RX_RL_THRSH, M_MAC_RX_RL_THRSH)
+#define S_MAC_RX_RL_THRSH          _SB_MAKE64(40)
+#define M_MAC_RX_RL_THRSH          _SB_MAKEMASK(6, S_MAC_RX_RL_THRSH)
+#define V_MAC_RX_RL_THRSH(x)       _SB_MAKEVALUE(x, S_MAC_RX_RL_THRSH)
+#define G_MAC_RX_RL_THRSH(x)       _SB_GETVALUE(x, S_MAC_RX_RL_THRSH, M_MAC_RX_RL_THRSH)

 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)

-#define S_MAC_ENC_FC_THRSH           _SB_MAKE64(56)
-#define M_MAC_ENC_FC_THRSH           _SB_MAKEMASK(6, S_MAC_ENC_FC_THRSH)
-#define V_MAC_ENC_FC_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_ENC_FC_THRSH)
-#define G_MAC_ENC_FC_THRSH(x)        _SB_GETVALUE(x, S_MAC_ENC_FC_THRSH, M_MAC_ENC_FC_THRSH)
+#define S_MAC_ENC_FC_THRSH          _SB_MAKE64(56)
+#define M_MAC_ENC_FC_THRSH          _SB_MAKEMASK(6, S_MAC_ENC_FC_THRSH)
+#define V_MAC_ENC_FC_THRSH(x)       _SB_MAKEVALUE(x, S_MAC_ENC_FC_THRSH)
+#define G_MAC_ENC_FC_THRSH(x)       _SB_GETVALUE(x, S_MAC_ENC_FC_THRSH, M_MAC_ENC_FC_THRSH)

 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 /*
 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 /*


@@ -275,79 +275,79 @@
  */
 
 /* XXXCGD: ??? Unused in pass2? */
  */
 
 /* XXXCGD: ??? Unused in pass2? */

-#define S_MAC_IFG_RX                _SB_MAKE64(0)
-#define M_MAC_IFG_RX                _SB_MAKEMASK(6, S_MAC_IFG_RX)
-#define V_MAC_IFG_RX(x)             _SB_MAKEVALUE(x, S_MAC_IFG_RX)
-#define G_MAC_IFG_RX(x)             _SB_GETVALUE(x, S_MAC_IFG_RX, M_MAC_IFG_RX)
+#define S_MAC_IFG_RX               _SB_MAKE64(0)
+#define M_MAC_IFG_RX               _SB_MAKEMASK(6, S_MAC_IFG_RX)
+#define V_MAC_IFG_RX(x)                    _SB_MAKEVALUE(x, S_MAC_IFG_RX)
+#define G_MAC_IFG_RX(x)                    _SB_GETVALUE(x, S_MAC_IFG_RX, M_MAC_IFG_RX)

 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)

-#define S_MAC_PRE_LEN               _SB_MAKE64(0)
-#define M_MAC_PRE_LEN               _SB_MAKEMASK(6, S_MAC_PRE_LEN)
-#define V_MAC_PRE_LEN(x)            _SB_MAKEVALUE(x, S_MAC_PRE_LEN)
-#define G_MAC_PRE_LEN(x)            _SB_GETVALUE(x, S_MAC_PRE_LEN, M_MAC_PRE_LEN)
+#define S_MAC_PRE_LEN              _SB_MAKE64(0)
+#define M_MAC_PRE_LEN              _SB_MAKEMASK(6, S_MAC_PRE_LEN)
+#define V_MAC_PRE_LEN(x)           _SB_MAKEVALUE(x, S_MAC_PRE_LEN)
+#define G_MAC_PRE_LEN(x)           _SB_GETVALUE(x, S_MAC_PRE_LEN, M_MAC_PRE_LEN)

 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 

-#define S_MAC_IFG_TX                _SB_MAKE64(6)
-#define M_MAC_IFG_TX                _SB_MAKEMASK(6, S_MAC_IFG_TX)
-#define V_MAC_IFG_TX(x)             _SB_MAKEVALUE(x, S_MAC_IFG_TX)
-#define G_MAC_IFG_TX(x)             _SB_GETVALUE(x, S_MAC_IFG_TX, M_MAC_IFG_TX)
-
-#define S_MAC_IFG_THRSH             _SB_MAKE64(12)
-#define M_MAC_IFG_THRSH             _SB_MAKEMASK(6, S_MAC_IFG_THRSH)
-#define V_MAC_IFG_THRSH(x)          _SB_MAKEVALUE(x, S_MAC_IFG_THRSH)
-#define G_MAC_IFG_THRSH(x)          _SB_GETVALUE(x, S_MAC_IFG_THRSH, M_MAC_IFG_THRSH)
-
-#define S_MAC_BACKOFF_SEL           _SB_MAKE64(18)
-#define M_MAC_BACKOFF_SEL           _SB_MAKEMASK(4, S_MAC_BACKOFF_SEL)
-#define V_MAC_BACKOFF_SEL(x)        _SB_MAKEVALUE(x, S_MAC_BACKOFF_SEL)
-#define G_MAC_BACKOFF_SEL(x)        _SB_GETVALUE(x, S_MAC_BACKOFF_SEL, M_MAC_BACKOFF_SEL)
-
-#define S_MAC_LFSR_SEED             _SB_MAKE64(22)
-#define M_MAC_LFSR_SEED             _SB_MAKEMASK(8, S_MAC_LFSR_SEED)
-#define V_MAC_LFSR_SEED(x)          _SB_MAKEVALUE(x, S_MAC_LFSR_SEED)
-#define G_MAC_LFSR_SEED(x)          _SB_GETVALUE(x, S_MAC_LFSR_SEED, M_MAC_LFSR_SEED)
-
-#define S_MAC_SLOT_SIZE             _SB_MAKE64(30)
-#define M_MAC_SLOT_SIZE             _SB_MAKEMASK(10, S_MAC_SLOT_SIZE)
-#define V_MAC_SLOT_SIZE(x)          _SB_MAKEVALUE(x, S_MAC_SLOT_SIZE)
-#define G_MAC_SLOT_SIZE(x)          _SB_GETVALUE(x, S_MAC_SLOT_SIZE, M_MAC_SLOT_SIZE)
-
-#define S_MAC_MIN_FRAMESZ           _SB_MAKE64(40)
-#define M_MAC_MIN_FRAMESZ           _SB_MAKEMASK(8, S_MAC_MIN_FRAMESZ)
-#define V_MAC_MIN_FRAMESZ(x)        _SB_MAKEVALUE(x, S_MAC_MIN_FRAMESZ)
-#define G_MAC_MIN_FRAMESZ(x)        _SB_GETVALUE(x, S_MAC_MIN_FRAMESZ, M_MAC_MIN_FRAMESZ)
-
-#define S_MAC_MAX_FRAMESZ           _SB_MAKE64(48)
-#define M_MAC_MAX_FRAMESZ           _SB_MAKEMASK(16, S_MAC_MAX_FRAMESZ)
-#define V_MAC_MAX_FRAMESZ(x)        _SB_MAKEVALUE(x, S_MAC_MAX_FRAMESZ)
-#define G_MAC_MAX_FRAMESZ(x)        _SB_GETVALUE(x, S_MAC_MAX_FRAMESZ, M_MAC_MAX_FRAMESZ)
+#define S_MAC_IFG_TX               _SB_MAKE64(6)
+#define M_MAC_IFG_TX               _SB_MAKEMASK(6, S_MAC_IFG_TX)
+#define V_MAC_IFG_TX(x)                    _SB_MAKEVALUE(x, S_MAC_IFG_TX)
+#define G_MAC_IFG_TX(x)                    _SB_GETVALUE(x, S_MAC_IFG_TX, M_MAC_IFG_TX)
+
+#define S_MAC_IFG_THRSH                    _SB_MAKE64(12)
+#define M_MAC_IFG_THRSH                    _SB_MAKEMASK(6, S_MAC_IFG_THRSH)
+#define V_MAC_IFG_THRSH(x)         _SB_MAKEVALUE(x, S_MAC_IFG_THRSH)
+#define G_MAC_IFG_THRSH(x)         _SB_GETVALUE(x, S_MAC_IFG_THRSH, M_MAC_IFG_THRSH)
+
+#define S_MAC_BACKOFF_SEL          _SB_MAKE64(18)
+#define M_MAC_BACKOFF_SEL          _SB_MAKEMASK(4, S_MAC_BACKOFF_SEL)
+#define V_MAC_BACKOFF_SEL(x)       _SB_MAKEVALUE(x, S_MAC_BACKOFF_SEL)
+#define G_MAC_BACKOFF_SEL(x)       _SB_GETVALUE(x, S_MAC_BACKOFF_SEL, M_MAC_BACKOFF_SEL)
+
+#define S_MAC_LFSR_SEED                    _SB_MAKE64(22)
+#define M_MAC_LFSR_SEED                    _SB_MAKEMASK(8, S_MAC_LFSR_SEED)
+#define V_MAC_LFSR_SEED(x)         _SB_MAKEVALUE(x, S_MAC_LFSR_SEED)
+#define G_MAC_LFSR_SEED(x)         _SB_GETVALUE(x, S_MAC_LFSR_SEED, M_MAC_LFSR_SEED)
+
+#define S_MAC_SLOT_SIZE                    _SB_MAKE64(30)
+#define M_MAC_SLOT_SIZE                    _SB_MAKEMASK(10, S_MAC_SLOT_SIZE)
+#define V_MAC_SLOT_SIZE(x)         _SB_MAKEVALUE(x, S_MAC_SLOT_SIZE)
+#define G_MAC_SLOT_SIZE(x)         _SB_GETVALUE(x, S_MAC_SLOT_SIZE, M_MAC_SLOT_SIZE)
+
+#define S_MAC_MIN_FRAMESZ          _SB_MAKE64(40)
+#define M_MAC_MIN_FRAMESZ          _SB_MAKEMASK(8, S_MAC_MIN_FRAMESZ)
+#define V_MAC_MIN_FRAMESZ(x)       _SB_MAKEVALUE(x, S_MAC_MIN_FRAMESZ)
+#define G_MAC_MIN_FRAMESZ(x)       _SB_GETVALUE(x, S_MAC_MIN_FRAMESZ, M_MAC_MIN_FRAMESZ)
+
+#define S_MAC_MAX_FRAMESZ          _SB_MAKE64(48)
+#define M_MAC_MAX_FRAMESZ          _SB_MAKEMASK(16, S_MAC_MAX_FRAMESZ)
+#define V_MAC_MAX_FRAMESZ(x)       _SB_MAKEVALUE(x, S_MAC_MAX_FRAMESZ)
+#define G_MAC_MAX_FRAMESZ(x)       _SB_GETVALUE(x, S_MAC_MAX_FRAMESZ, M_MAC_MAX_FRAMESZ)

 
 /*
  * These constants are used to configure the fields within the Frame
  * Configuration Register.
  */
 
 
 /*
  * These constants are used to configure the fields within the Frame
  * Configuration Register.
  */
 

-#define K_MAC_IFG_RX_10             _SB_MAKE64(0)      /* See table 176, not used */
-#define K_MAC_IFG_RX_100            _SB_MAKE64(0)
-#define K_MAC_IFG_RX_1000           _SB_MAKE64(0)
+#define K_MAC_IFG_RX_10                    _SB_MAKE64(0)       /* See table 176, not used */
+#define K_MAC_IFG_RX_100           _SB_MAKE64(0)
+#define K_MAC_IFG_RX_1000          _SB_MAKE64(0)

 
 

-#define K_MAC_IFG_TX_10             _SB_MAKE64(20)
-#define K_MAC_IFG_TX_100            _SB_MAKE64(20)
-#define K_MAC_IFG_TX_1000           _SB_MAKE64(8)
+#define K_MAC_IFG_TX_10                    _SB_MAKE64(20)
+#define K_MAC_IFG_TX_100           _SB_MAKE64(20)
+#define K_MAC_IFG_TX_1000          _SB_MAKE64(8)

 
 

-#define K_MAC_IFG_THRSH_10          _SB_MAKE64(4)
-#define K_MAC_IFG_THRSH_100         _SB_MAKE64(4)
-#define K_MAC_IFG_THRSH_1000        _SB_MAKE64(0)
+#define K_MAC_IFG_THRSH_10         _SB_MAKE64(4)
+#define K_MAC_IFG_THRSH_100        _SB_MAKE64(4)
+#define K_MAC_IFG_THRSH_1000       _SB_MAKE64(0)

 
 

-#define K_MAC_SLOT_SIZE_10          _SB_MAKE64(0)
-#define K_MAC_SLOT_SIZE_100         _SB_MAKE64(0)
-#define K_MAC_SLOT_SIZE_1000        _SB_MAKE64(0)
+#define K_MAC_SLOT_SIZE_10         _SB_MAKE64(0)
+#define K_MAC_SLOT_SIZE_100        _SB_MAKE64(0)
+#define K_MAC_SLOT_SIZE_1000       _SB_MAKE64(0)

 
 

-#define V_MAC_IFG_RX_10        V_MAC_IFG_RX(K_MAC_IFG_RX_10)
+#define V_MAC_IFG_RX_10               V_MAC_IFG_RX(K_MAC_IFG_RX_10)

 #define V_MAC_IFG_RX_100       V_MAC_IFG_RX(K_MAC_IFG_RX_100)
 #define V_MAC_IFG_RX_1000      V_MAC_IFG_RX(K_MAC_IFG_RX_1000)
 
 #define V_MAC_IFG_RX_100       V_MAC_IFG_RX(K_MAC_IFG_RX_100)
 #define V_MAC_IFG_RX_1000      V_MAC_IFG_RX(K_MAC_IFG_RX_1000)
 

-#define V_MAC_IFG_TX_10        V_MAC_IFG_TX(K_MAC_IFG_TX_10)
+#define V_MAC_IFG_TX_10               V_MAC_IFG_TX(K_MAC_IFG_TX_10)

 #define V_MAC_IFG_TX_100       V_MAC_IFG_TX(K_MAC_IFG_TX_100)
 #define V_MAC_IFG_TX_1000      V_MAC_IFG_TX(K_MAC_IFG_TX_1000)
 
 #define V_MAC_IFG_TX_100       V_MAC_IFG_TX(K_MAC_IFG_TX_100)
 #define V_MAC_IFG_TX_1000      V_MAC_IFG_TX(K_MAC_IFG_TX_1000)
 


@@ -359,15 +359,15 @@
 #define V_MAC_SLOT_SIZE_100    V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100)
 #define V_MAC_SLOT_SIZE_1000   V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000)
 
 #define V_MAC_SLOT_SIZE_100    V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100)
 #define V_MAC_SLOT_SIZE_1000   V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000)
 

-#define K_MAC_MIN_FRAMESZ_FIFO      _SB_MAKE64(9)
+#define K_MAC_MIN_FRAMESZ_FIFO     _SB_MAKE64(9)

 #define K_MAC_MIN_FRAMESZ_DEFAULT   _SB_MAKE64(64)
 #define K_MAC_MAX_FRAMESZ_DEFAULT   _SB_MAKE64(1518)
 #define K_MAC_MIN_FRAMESZ_DEFAULT   _SB_MAKE64(64)
 #define K_MAC_MAX_FRAMESZ_DEFAULT   _SB_MAKE64(1518)

-#define K_MAC_MAX_FRAMESZ_JUMBO     _SB_MAKE64(9216)
+#define K_MAC_MAX_FRAMESZ_JUMBO            _SB_MAKE64(9216)

 
 

-#define V_MAC_MIN_FRAMESZ_FIFO      V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO)
+#define V_MAC_MIN_FRAMESZ_FIFO     V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO)

 #define V_MAC_MIN_FRAMESZ_DEFAULT   V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT)
 #define V_MAC_MAX_FRAMESZ_DEFAULT   V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT)
 #define V_MAC_MIN_FRAMESZ_DEFAULT   V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT)
 #define V_MAC_MAX_FRAMESZ_DEFAULT   V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT)

-#define V_MAC_MAX_FRAMESZ_JUMBO     V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO)
+#define V_MAC_MAX_FRAMESZ_JUMBO            V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO)

 
 /*
  * MAC VLAN Tag Registers (Table 9-16)
 
 /*
  * MAC VLAN Tag Registers (Table 9-16)


@@ -376,23 +376,23 @@
  * Register: MAC_VLANTAG_2
  */
 
  * Register: MAC_VLANTAG_2
  */
 

-#define S_MAC_VLAN_TAG           _SB_MAKE64(0)
-#define M_MAC_VLAN_TAG           _SB_MAKEMASK(32, S_MAC_VLAN_TAG)
-#define V_MAC_VLAN_TAG(x)        _SB_MAKEVALUE(x, S_MAC_VLAN_TAG)
-#define G_MAC_VLAN_TAG(x)        _SB_GETVALUE(x, S_MAC_VLAN_TAG, M_MAC_VLAN_TAG)
+#define S_MAC_VLAN_TAG          _SB_MAKE64(0)
+#define M_MAC_VLAN_TAG          _SB_MAKEMASK(32, S_MAC_VLAN_TAG)
+#define V_MAC_VLAN_TAG(x)       _SB_MAKEVALUE(x, S_MAC_VLAN_TAG)
+#define G_MAC_VLAN_TAG(x)       _SB_GETVALUE(x, S_MAC_VLAN_TAG, M_MAC_VLAN_TAG)

 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)

-#define S_MAC_TX_PKT_OFFSET      _SB_MAKE64(32)
-#define M_MAC_TX_PKT_OFFSET      _SB_MAKEMASK(8, S_MAC_TX_PKT_OFFSET)
-#define V_MAC_TX_PKT_OFFSET(x)   _SB_MAKEVALUE(x, S_MAC_TX_PKT_OFFSET)
-#define G_MAC_TX_PKT_OFFSET(x)   _SB_GETVALUE(x, S_MAC_TX_PKT_OFFSET, M_MAC_TX_PKT_OFFSET)
+#define S_MAC_TX_PKT_OFFSET     _SB_MAKE64(32)
+#define M_MAC_TX_PKT_OFFSET     _SB_MAKEMASK(8, S_MAC_TX_PKT_OFFSET)
+#define V_MAC_TX_PKT_OFFSET(x)  _SB_MAKEVALUE(x, S_MAC_TX_PKT_OFFSET)
+#define G_MAC_TX_PKT_OFFSET(x)  _SB_GETVALUE(x, S_MAC_TX_PKT_OFFSET, M_MAC_TX_PKT_OFFSET)

 
 

-#define S_MAC_TX_CRC_OFFSET      _SB_MAKE64(40)
-#define M_MAC_TX_CRC_OFFSET      _SB_MAKEMASK(8, S_MAC_TX_CRC_OFFSET)
-#define V_MAC_TX_CRC_OFFSET(x)   _SB_MAKEVALUE(x, S_MAC_TX_CRC_OFFSET)
-#define G_MAC_TX_CRC_OFFSET(x)   _SB_GETVALUE(x, S_MAC_TX_CRC_OFFSET, M_MAC_TX_CRC_OFFSET)
+#define S_MAC_TX_CRC_OFFSET     _SB_MAKE64(40)
+#define M_MAC_TX_CRC_OFFSET     _SB_MAKEMASK(8, S_MAC_TX_CRC_OFFSET)
+#define V_MAC_TX_CRC_OFFSET(x)  _SB_MAKEVALUE(x, S_MAC_TX_CRC_OFFSET)
+#define G_MAC_TX_CRC_OFFSET(x)  _SB_GETVALUE(x, S_MAC_TX_CRC_OFFSET, M_MAC_TX_CRC_OFFSET)

 
 

-#define M_MAC_CH_BASE_FC_EN      _SB_MAKEMASK1(48)
+#define M_MAC_CH_BASE_FC_EN     _SB_MAKEMASK1(48)

 #endif /* 1250 PASS3 || 112x PASS1 */
 
 /*
 #endif /* 1250 PASS3 || 112x PASS1 */
 
 /*


@@ -412,29 +412,29 @@
  * on each channel.
  */
 
  * on each channel.
  */
 

-#define S_MAC_RX_CH0                _SB_MAKE64(0)
-#define S_MAC_RX_CH1                _SB_MAKE64(8)
-#define S_MAC_TX_CH0                _SB_MAKE64(16)
-#define S_MAC_TX_CH1                _SB_MAKE64(24)
+#define S_MAC_RX_CH0               _SB_MAKE64(0)
+#define S_MAC_RX_CH1               _SB_MAKE64(8)
+#define S_MAC_TX_CH0               _SB_MAKE64(16)
+#define S_MAC_TX_CH1               _SB_MAKE64(24)

 
 #define S_MAC_TXCHANNELS           _SB_MAKE64(16)      /* this is 1st TX chan */
 
 #define S_MAC_TXCHANNELS           _SB_MAKE64(16)      /* this is 1st TX chan */

-#define S_MAC_CHANWIDTH             _SB_MAKE64(8)      /* bits between channels */
+#define S_MAC_CHANWIDTH                    _SB_MAKE64(8)       /* bits between channels */

 
 /*
 
 /*

- *  These are the same as RX channel 0.  The idea here
+ *  These are the same as RX channel 0.         The idea here

  *  is that you'll use one of the "S_" things above
  *  and pass just the six bits to a DMA-channel-specific ISR
  */
  *  is that you'll use one of the "S_" things above
  *  and pass just the six bits to a DMA-channel-specific ISR
  */

-#define M_MAC_INT_CHANNEL           _SB_MAKEMASK(8, 0)
-#define M_MAC_INT_EOP_COUNT         _SB_MAKEMASK1(0)
-#define M_MAC_INT_EOP_TIMER         _SB_MAKEMASK1(1)
-#define M_MAC_INT_EOP_SEEN          _SB_MAKEMASK1(2)
-#define M_MAC_INT_HWM               _SB_MAKEMASK1(3)
-#define M_MAC_INT_LWM               _SB_MAKEMASK1(4)
-#define M_MAC_INT_DSCR              _SB_MAKEMASK1(5)
-#define M_MAC_INT_ERR               _SB_MAKEMASK1(6)
-#define M_MAC_INT_DZERO             _SB_MAKEMASK1(7)   /* only for TX channels */
-#define M_MAC_INT_DROP              _SB_MAKEMASK1(7)   /* only for RX channels */
+#define M_MAC_INT_CHANNEL          _SB_MAKEMASK(8, 0)
+#define M_MAC_INT_EOP_COUNT        _SB_MAKEMASK1(0)
+#define M_MAC_INT_EOP_TIMER        _SB_MAKEMASK1(1)
+#define M_MAC_INT_EOP_SEEN         _SB_MAKEMASK1(2)
+#define M_MAC_INT_HWM              _SB_MAKEMASK1(3)
+#define M_MAC_INT_LWM              _SB_MAKEMASK1(4)
+#define M_MAC_INT_DSCR             _SB_MAKEMASK1(5)
+#define M_MAC_INT_ERR              _SB_MAKEMASK1(6)
+#define M_MAC_INT_DZERO                    _SB_MAKEMASK1(7)    /* only for TX channels */
+#define M_MAC_INT_DROP             _SB_MAKEMASK1(7)    /* only for RX channels */

 
 /*
  * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see
 
 /*
  * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see


@@ -442,34 +442,34 @@
  */
 #define S_MAC_STATUS_CH_OFFSET(ch, txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH)
 
  */
 #define S_MAC_STATUS_CH_OFFSET(ch, txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH)
 

-#define M_MAC_STATUS_CHANNEL(ch, txrx)   _SB_MAKEVALUE(_SB_MAKEMASK(8, 0), S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_CHANNEL(ch, txrx)  _SB_MAKEVALUE(_SB_MAKEMASK(8, 0), S_MAC_STATUS_CH_OFFSET(ch, txrx))

 #define M_MAC_STATUS_EOP_COUNT(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT, S_MAC_STATUS_CH_OFFSET(ch, txrx))
 #define M_MAC_STATUS_EOP_TIMER(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER, S_MAC_STATUS_CH_OFFSET(ch, txrx))
 #define M_MAC_STATUS_EOP_COUNT(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT, S_MAC_STATUS_CH_OFFSET(ch, txrx))
 #define M_MAC_STATUS_EOP_TIMER(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER, S_MAC_STATUS_CH_OFFSET(ch, txrx))

-#define M_MAC_STATUS_EOP_SEEN(ch, txrx)  _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN, S_MAC_STATUS_CH_OFFSET(ch, txrx))
-#define M_MAC_STATUS_HWM(ch, txrx)       _SB_MAKEVALUE(M_MAC_INT_HWM, S_MAC_STATUS_CH_OFFSET(ch, txrx))
-#define M_MAC_STATUS_LWM(ch, txrx)       _SB_MAKEVALUE(M_MAC_INT_LWM, S_MAC_STATUS_CH_OFFSET(ch, txrx))
-#define M_MAC_STATUS_DSCR(ch, txrx)      _SB_MAKEVALUE(M_MAC_INT_DSCR, S_MAC_STATUS_CH_OFFSET(ch, txrx))
-#define M_MAC_STATUS_ERR(ch, txrx)       _SB_MAKEVALUE(M_MAC_INT_ERR, S_MAC_STATUS_CH_OFFSET(ch, txrx))
-#define M_MAC_STATUS_DZERO(ch, txrx)     _SB_MAKEVALUE(M_MAC_INT_DZERO, S_MAC_STATUS_CH_OFFSET(ch, txrx))
-#define M_MAC_STATUS_DROP(ch, txrx)      _SB_MAKEVALUE(M_MAC_INT_DROP, S_MAC_STATUS_CH_OFFSET(ch, txrx))
-#define M_MAC_STATUS_OTHER_ERR           _SB_MAKEVALUE(_SB_MAKEMASK(7, 0), 40)
-
-
-#define M_MAC_RX_UNDRFL             _SB_MAKEMASK1(40)
-#define M_MAC_RX_OVRFL              _SB_MAKEMASK1(41)
-#define M_MAC_TX_UNDRFL             _SB_MAKEMASK1(42)
-#define M_MAC_TX_OVRFL              _SB_MAKEMASK1(43)
-#define M_MAC_LTCOL_ERR             _SB_MAKEMASK1(44)
-#define M_MAC_EXCOL_ERR             _SB_MAKEMASK1(45)
-#define M_MAC_CNTR_OVRFL_ERR        _SB_MAKEMASK1(46)
+#define M_MAC_STATUS_EOP_SEEN(ch, txrx)         _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_HWM(ch, txrx)      _SB_MAKEVALUE(M_MAC_INT_HWM, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_LWM(ch, txrx)      _SB_MAKEVALUE(M_MAC_INT_LWM, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_DSCR(ch, txrx)     _SB_MAKEVALUE(M_MAC_INT_DSCR, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_ERR(ch, txrx)      _SB_MAKEVALUE(M_MAC_INT_ERR, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_DZERO(ch, txrx)    _SB_MAKEVALUE(M_MAC_INT_DZERO, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_DROP(ch, txrx)     _SB_MAKEVALUE(M_MAC_INT_DROP, S_MAC_STATUS_CH_OFFSET(ch, txrx))
+#define M_MAC_STATUS_OTHER_ERR          _SB_MAKEVALUE(_SB_MAKEMASK(7, 0), 40)
+
+
+#define M_MAC_RX_UNDRFL                    _SB_MAKEMASK1(40)
+#define M_MAC_RX_OVRFL             _SB_MAKEMASK1(41)
+#define M_MAC_TX_UNDRFL                    _SB_MAKEMASK1(42)
+#define M_MAC_TX_OVRFL             _SB_MAKEMASK1(43)
+#define M_MAC_LTCOL_ERR                    _SB_MAKEMASK1(44)
+#define M_MAC_EXCOL_ERR                    _SB_MAKEMASK1(45)
+#define M_MAC_CNTR_OVRFL_ERR       _SB_MAKEMASK1(46)

 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)

-#define M_MAC_SPLIT_EN             _SB_MAKEMASK1(47)   /* interrupt mask only */
+#define M_MAC_SPLIT_EN             _SB_MAKEMASK1(47)   /* interrupt mask only */

 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 

-#define S_MAC_COUNTER_ADDR          _SB_MAKE64(47)
-#define M_MAC_COUNTER_ADDR          _SB_MAKEMASK(5, S_MAC_COUNTER_ADDR)
-#define V_MAC_COUNTER_ADDR(x)       _SB_MAKEVALUE(x, S_MAC_COUNTER_ADDR)
-#define G_MAC_COUNTER_ADDR(x)       _SB_GETVALUE(x, S_MAC_COUNTER_ADDR, M_MAC_COUNTER_ADDR)
+#define S_MAC_COUNTER_ADDR         _SB_MAKE64(47)
+#define M_MAC_COUNTER_ADDR         _SB_MAKEMASK(5, S_MAC_COUNTER_ADDR)
+#define V_MAC_COUNTER_ADDR(x)      _SB_MAKEVALUE(x, S_MAC_COUNTER_ADDR)
+#define G_MAC_COUNTER_ADDR(x)      _SB_GETVALUE(x, S_MAC_COUNTER_ADDR, M_MAC_COUNTER_ADDR)

 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_MAC_TX_PAUSE_ON          _SB_MAKEMASK1(52)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_MAC_TX_PAUSE_ON          _SB_MAKEMASK1(52)


@@ -482,42 +482,42 @@
  * Register: MAC_FIFO_PTRS_2
  */
 
  * Register: MAC_FIFO_PTRS_2
  */
 

-#define S_MAC_TX_WRPTR              _SB_MAKE64(0)
-#define M_MAC_TX_WRPTR              _SB_MAKEMASK(6, S_MAC_TX_WRPTR)
-#define V_MAC_TX_WRPTR(x)           _SB_MAKEVALUE(x, S_MAC_TX_WRPTR)
-#define G_MAC_TX_WRPTR(x)           _SB_GETVALUE(x, S_MAC_TX_WRPTR, M_MAC_TX_WRPTR)
+#define S_MAC_TX_WRPTR             _SB_MAKE64(0)
+#define M_MAC_TX_WRPTR             _SB_MAKEMASK(6, S_MAC_TX_WRPTR)
+#define V_MAC_TX_WRPTR(x)          _SB_MAKEVALUE(x, S_MAC_TX_WRPTR)
+#define G_MAC_TX_WRPTR(x)          _SB_GETVALUE(x, S_MAC_TX_WRPTR, M_MAC_TX_WRPTR)

 
 

-#define S_MAC_TX_RDPTR              _SB_MAKE64(8)
-#define M_MAC_TX_RDPTR              _SB_MAKEMASK(6, S_MAC_TX_RDPTR)
-#define V_MAC_TX_RDPTR(x)           _SB_MAKEVALUE(x, S_MAC_TX_RDPTR)
-#define G_MAC_TX_RDPTR(x)           _SB_GETVALUE(x, S_MAC_TX_RDPTR, M_MAC_TX_RDPTR)
+#define S_MAC_TX_RDPTR             _SB_MAKE64(8)
+#define M_MAC_TX_RDPTR             _SB_MAKEMASK(6, S_MAC_TX_RDPTR)
+#define V_MAC_TX_RDPTR(x)          _SB_MAKEVALUE(x, S_MAC_TX_RDPTR)
+#define G_MAC_TX_RDPTR(x)          _SB_GETVALUE(x, S_MAC_TX_RDPTR, M_MAC_TX_RDPTR)

 
 

-#define S_MAC_RX_WRPTR              _SB_MAKE64(16)
-#define M_MAC_RX_WRPTR              _SB_MAKEMASK(6, S_MAC_RX_WRPTR)
-#define V_MAC_RX_WRPTR(x)           _SB_MAKEVALUE(x, S_MAC_RX_WRPTR)
-#define G_MAC_RX_WRPTR(x)           _SB_GETVALUE(x, S_MAC_RX_WRPTR, M_MAC_TX_WRPTR)
+#define S_MAC_RX_WRPTR             _SB_MAKE64(16)
+#define M_MAC_RX_WRPTR             _SB_MAKEMASK(6, S_MAC_RX_WRPTR)
+#define V_MAC_RX_WRPTR(x)          _SB_MAKEVALUE(x, S_MAC_RX_WRPTR)
+#define G_MAC_RX_WRPTR(x)          _SB_GETVALUE(x, S_MAC_RX_WRPTR, M_MAC_TX_WRPTR)

 
 

-#define S_MAC_RX_RDPTR              _SB_MAKE64(24)
-#define M_MAC_RX_RDPTR              _SB_MAKEMASK(6, S_MAC_RX_RDPTR)
-#define V_MAC_RX_RDPTR(x)           _SB_MAKEVALUE(x, S_MAC_RX_RDPTR)
-#define G_MAC_RX_RDPTR(x)           _SB_GETVALUE(x, S_MAC_RX_RDPTR, M_MAC_TX_RDPTR)
+#define S_MAC_RX_RDPTR             _SB_MAKE64(24)
+#define M_MAC_RX_RDPTR             _SB_MAKEMASK(6, S_MAC_RX_RDPTR)
+#define V_MAC_RX_RDPTR(x)          _SB_MAKEVALUE(x, S_MAC_RX_RDPTR)
+#define G_MAC_RX_RDPTR(x)          _SB_GETVALUE(x, S_MAC_RX_RDPTR, M_MAC_TX_RDPTR)

 
 /*
 
 /*

- * MAC Fifo End Of Packet Count Registers (Table 9-20)  [Debug register]
+ * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register]

  * Register: MAC_EOPCNT_0
  * Register: MAC_EOPCNT_1
  * Register: MAC_EOPCNT_2
  */
 
  * Register: MAC_EOPCNT_0
  * Register: MAC_EOPCNT_1
  * Register: MAC_EOPCNT_2
  */
 

-#define S_MAC_TX_EOP_COUNTER        _SB_MAKE64(0)
-#define M_MAC_TX_EOP_COUNTER        _SB_MAKEMASK(6, S_MAC_TX_EOP_COUNTER)
-#define V_MAC_TX_EOP_COUNTER(x)     _SB_MAKEVALUE(x, S_MAC_TX_EOP_COUNTER)
-#define G_MAC_TX_EOP_COUNTER(x)     _SB_GETVALUE(x, S_MAC_TX_EOP_COUNTER, M_MAC_TX_EOP_COUNTER)
+#define S_MAC_TX_EOP_COUNTER       _SB_MAKE64(0)
+#define M_MAC_TX_EOP_COUNTER       _SB_MAKEMASK(6, S_MAC_TX_EOP_COUNTER)
+#define V_MAC_TX_EOP_COUNTER(x)            _SB_MAKEVALUE(x, S_MAC_TX_EOP_COUNTER)
+#define G_MAC_TX_EOP_COUNTER(x)            _SB_GETVALUE(x, S_MAC_TX_EOP_COUNTER, M_MAC_TX_EOP_COUNTER)

 
 

-#define S_MAC_RX_EOP_COUNTER        _SB_MAKE64(8)
-#define M_MAC_RX_EOP_COUNTER        _SB_MAKEMASK(6, S_MAC_RX_EOP_COUNTER)
-#define V_MAC_RX_EOP_COUNTER(x)     _SB_MAKEVALUE(x, S_MAC_RX_EOP_COUNTER)
-#define G_MAC_RX_EOP_COUNTER(x)     _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER)
+#define S_MAC_RX_EOP_COUNTER       _SB_MAKE64(8)
+#define M_MAC_RX_EOP_COUNTER       _SB_MAKEMASK(6, S_MAC_RX_EOP_COUNTER)
+#define V_MAC_RX_EOP_COUNTER(x)            _SB_MAKEVALUE(x, S_MAC_RX_EOP_COUNTER)
+#define G_MAC_RX_EOP_COUNTER(x)            _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER)

 
 /*
  * MAC Receive Address Filter Exact Match Registers (Table 9-21)
 
 /*
  * MAC Receive Address Filter Exact Match Registers (Table 9-21)


@@ -562,27 +562,27 @@
  * Register: MAC_TYPE_CFG_2
  */
 
  * Register: MAC_TYPE_CFG_2
  */
 

-#define S_TYPECFG_TYPESIZE      _SB_MAKE64(16)
+#define S_TYPECFG_TYPESIZE     _SB_MAKE64(16)

 
 #define S_TYPECFG_TYPE0                _SB_MAKE64(0)
 
 #define S_TYPECFG_TYPE0                _SB_MAKE64(0)

-#define M_TYPECFG_TYPE0         _SB_MAKEMASK(16, S_TYPECFG_TYPE0)
-#define V_TYPECFG_TYPE0(x)      _SB_MAKEVALUE(x, S_TYPECFG_TYPE0)
-#define G_TYPECFG_TYPE0(x)      _SB_GETVALUE(x, S_TYPECFG_TYPE0, M_TYPECFG_TYPE0)
+#define M_TYPECFG_TYPE0                _SB_MAKEMASK(16, S_TYPECFG_TYPE0)
+#define V_TYPECFG_TYPE0(x)     _SB_MAKEVALUE(x, S_TYPECFG_TYPE0)
+#define G_TYPECFG_TYPE0(x)     _SB_GETVALUE(x, S_TYPECFG_TYPE0, M_TYPECFG_TYPE0)

 
 #define S_TYPECFG_TYPE1                _SB_MAKE64(0)
 
 #define S_TYPECFG_TYPE1                _SB_MAKE64(0)

-#define M_TYPECFG_TYPE1         _SB_MAKEMASK(16, S_TYPECFG_TYPE1)
-#define V_TYPECFG_TYPE1(x)      _SB_MAKEVALUE(x, S_TYPECFG_TYPE1)
-#define G_TYPECFG_TYPE1(x)      _SB_GETVALUE(x, S_TYPECFG_TYPE1, M_TYPECFG_TYPE1)
+#define M_TYPECFG_TYPE1                _SB_MAKEMASK(16, S_TYPECFG_TYPE1)
+#define V_TYPECFG_TYPE1(x)     _SB_MAKEVALUE(x, S_TYPECFG_TYPE1)
+#define G_TYPECFG_TYPE1(x)     _SB_GETVALUE(x, S_TYPECFG_TYPE1, M_TYPECFG_TYPE1)

 
 #define S_TYPECFG_TYPE2                _SB_MAKE64(0)
 
 #define S_TYPECFG_TYPE2                _SB_MAKE64(0)

-#define M_TYPECFG_TYPE2         _SB_MAKEMASK(16, S_TYPECFG_TYPE2)
-#define V_TYPECFG_TYPE2(x)      _SB_MAKEVALUE(x, S_TYPECFG_TYPE2)
-#define G_TYPECFG_TYPE2(x)      _SB_GETVALUE(x, S_TYPECFG_TYPE2, M_TYPECFG_TYPE2)
+#define M_TYPECFG_TYPE2                _SB_MAKEMASK(16, S_TYPECFG_TYPE2)
+#define V_TYPECFG_TYPE2(x)     _SB_MAKEVALUE(x, S_TYPECFG_TYPE2)
+#define G_TYPECFG_TYPE2(x)     _SB_GETVALUE(x, S_TYPECFG_TYPE2, M_TYPECFG_TYPE2)

 
 #define S_TYPECFG_TYPE3                _SB_MAKE64(0)
 
 #define S_TYPECFG_TYPE3                _SB_MAKE64(0)

-#define M_TYPECFG_TYPE3         _SB_MAKEMASK(16, S_TYPECFG_TYPE3)
-#define V_TYPECFG_TYPE3(x)      _SB_MAKEVALUE(x, S_TYPECFG_TYPE3)
-#define G_TYPECFG_TYPE3(x)      _SB_GETVALUE(x, S_TYPECFG_TYPE3, M_TYPECFG_TYPE3)
+#define M_TYPECFG_TYPE3                _SB_MAKEMASK(16, S_TYPECFG_TYPE3)
+#define V_TYPECFG_TYPE3(x)     _SB_MAKEVALUE(x, S_TYPECFG_TYPE3)
+#define G_TYPECFG_TYPE3(x)     _SB_GETVALUE(x, S_TYPECFG_TYPE3, M_TYPECFG_TYPE3)

 
 /*
  * MAC Receive Address Filter Control Registers (Table 9-24)
 
 /*
  * MAC Receive Address Filter Control Registers (Table 9-24)


@@ -591,38 +591,38 @@
  * Register: MAC_ADFILTER_CFG_2
  */
 
  * Register: MAC_ADFILTER_CFG_2
  */
 

-#define M_MAC_ALLPKT_EN                _SB_MAKEMASK1(0)
-#define M_MAC_UCAST_EN          _SB_MAKEMASK1(1)
-#define M_MAC_UCAST_INV         _SB_MAKEMASK1(2)
-#define M_MAC_MCAST_EN          _SB_MAKEMASK1(3)
-#define M_MAC_MCAST_INV         _SB_MAKEMASK1(4)
-#define M_MAC_BCAST_EN          _SB_MAKEMASK1(5)
-#define M_MAC_DIRECT_INV        _SB_MAKEMASK1(6)
+#define M_MAC_ALLPKT_EN                _SB_MAKEMASK1(0)
+#define M_MAC_UCAST_EN         _SB_MAKEMASK1(1)
+#define M_MAC_UCAST_INV                _SB_MAKEMASK1(2)
+#define M_MAC_MCAST_EN         _SB_MAKEMASK1(3)
+#define M_MAC_MCAST_INV                _SB_MAKEMASK1(4)
+#define M_MAC_BCAST_EN         _SB_MAKEMASK1(5)
+#define M_MAC_DIRECT_INV       _SB_MAKEMASK1(6)

 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_MAC_ALLMCAST_EN      _SB_MAKEMASK1(7)
 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define M_MAC_ALLMCAST_EN      _SB_MAKEMASK1(7)
 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 

-#define S_MAC_IPHDR_OFFSET      _SB_MAKE64(8)
-#define M_MAC_IPHDR_OFFSET      _SB_MAKEMASK(8, S_MAC_IPHDR_OFFSET)
+#define S_MAC_IPHDR_OFFSET     _SB_MAKE64(8)
+#define M_MAC_IPHDR_OFFSET     _SB_MAKEMASK(8, S_MAC_IPHDR_OFFSET)

 #define V_MAC_IPHDR_OFFSET(x)  _SB_MAKEVALUE(x, S_MAC_IPHDR_OFFSET)
 #define G_MAC_IPHDR_OFFSET(x)  _SB_GETVALUE(x, S_MAC_IPHDR_OFFSET, M_MAC_IPHDR_OFFSET)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define V_MAC_IPHDR_OFFSET(x)  _SB_MAKEVALUE(x, S_MAC_IPHDR_OFFSET)
 #define G_MAC_IPHDR_OFFSET(x)  _SB_GETVALUE(x, S_MAC_IPHDR_OFFSET, M_MAC_IPHDR_OFFSET)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)

-#define S_MAC_RX_CRC_OFFSET     _SB_MAKE64(16)
-#define M_MAC_RX_CRC_OFFSET     _SB_MAKEMASK(8, S_MAC_RX_CRC_OFFSET)
+#define S_MAC_RX_CRC_OFFSET    _SB_MAKE64(16)
+#define M_MAC_RX_CRC_OFFSET    _SB_MAKEMASK(8, S_MAC_RX_CRC_OFFSET)

 #define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_CRC_OFFSET)
 #define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_CRC_OFFSET, M_MAC_RX_CRC_OFFSET)
 
 #define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_CRC_OFFSET)
 #define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_CRC_OFFSET, M_MAC_RX_CRC_OFFSET)
 

-#define S_MAC_RX_PKT_OFFSET     _SB_MAKE64(24)
-#define M_MAC_RX_PKT_OFFSET     _SB_MAKEMASK(8, S_MAC_RX_PKT_OFFSET)
+#define S_MAC_RX_PKT_OFFSET    _SB_MAKE64(24)
+#define M_MAC_RX_PKT_OFFSET    _SB_MAKEMASK(8, S_MAC_RX_PKT_OFFSET)

 #define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_PKT_OFFSET)
 #define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_PKT_OFFSET, M_MAC_RX_PKT_OFFSET)
 
 #define M_MAC_FWDPAUSE_EN      _SB_MAKEMASK1(32)
 #define M_MAC_VLAN_DET_EN      _SB_MAKEMASK1(33)
 
 #define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x, S_MAC_RX_PKT_OFFSET)
 #define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x, S_MAC_RX_PKT_OFFSET, M_MAC_RX_PKT_OFFSET)
 
 #define M_MAC_FWDPAUSE_EN      _SB_MAKEMASK1(32)
 #define M_MAC_VLAN_DET_EN      _SB_MAKEMASK1(33)
 

-#define S_MAC_RX_CH_MSN_SEL     _SB_MAKE64(34)
-#define M_MAC_RX_CH_MSN_SEL     _SB_MAKEMASK(8, S_MAC_RX_CH_MSN_SEL)
+#define S_MAC_RX_CH_MSN_SEL    _SB_MAKE64(34)
+#define M_MAC_RX_CH_MSN_SEL    _SB_MAKEMASK(8, S_MAC_RX_CH_MSN_SEL)

 #define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_MSN_SEL)
 #define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_MSN_SEL, M_MAC_RX_CH_MSN_SEL)
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 #define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x, S_MAC_RX_CH_MSN_SEL)
 #define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x, S_MAC_RX_CH_MSN_SEL, M_MAC_RX_CH_MSN_SEL)
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */

diff --git a/arch/mips/include/asm/sibyte/sb1250_mc.h b/arch/mips/include/asm/sibyte/sb1250_mc.h
index 15048dcaf22f37c0bf4b127f0e8452c8ef0b46b6..8368e411131ffbd31a02cc8dda8591f2c11db647 100644 (file)
--- a/arch/mips/include/asm/sibyte/sb1250_mc.h
+++ b/arch/mips/include/asm/sibyte/sb1250_mc.h
@@ -1,7 +1,7 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
     *
 /*  *********************************************************************
     *  SB1250 Board Support Package
     *

-    *  Memory Controller constants              File: sb1250_mc.h
+    *  Memory Controller constants             File: sb1250_mc.h

     *
     *  This module contains constants and macros useful for
     *  programming the memory controller.
     *
     *  This module contains constants and macros useful for
     *  programming the memory controller.


@@ -39,96 +39,96 @@
  * Memory Channel Config Register (table 6-14)
  */
 
  * Memory Channel Config Register (table 6-14)
  */
 

-#define S_MC_RESERVED0              0
-#define M_MC_RESERVED0              _SB_MAKEMASK(8, S_MC_RESERVED0)
+#define S_MC_RESERVED0             0
+#define M_MC_RESERVED0             _SB_MAKEMASK(8, S_MC_RESERVED0)

 
 

-#define S_MC_CHANNEL_SEL            8
-#define M_MC_CHANNEL_SEL            _SB_MAKEMASK(8, S_MC_CHANNEL_SEL)
-#define V_MC_CHANNEL_SEL(x)         _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL)
-#define G_MC_CHANNEL_SEL(x)         _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL)
+#define S_MC_CHANNEL_SEL           8
+#define M_MC_CHANNEL_SEL           _SB_MAKEMASK(8, S_MC_CHANNEL_SEL)
+#define V_MC_CHANNEL_SEL(x)        _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL)
+#define G_MC_CHANNEL_SEL(x)        _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL)

 
 

-#define S_MC_BANK0_MAP              16
-#define M_MC_BANK0_MAP              _SB_MAKEMASK(4, S_MC_BANK0_MAP)
-#define V_MC_BANK0_MAP(x)           _SB_MAKEVALUE(x, S_MC_BANK0_MAP)
-#define G_MC_BANK0_MAP(x)           _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP)
+#define S_MC_BANK0_MAP             16
+#define M_MC_BANK0_MAP             _SB_MAKEMASK(4, S_MC_BANK0_MAP)
+#define V_MC_BANK0_MAP(x)          _SB_MAKEVALUE(x, S_MC_BANK0_MAP)
+#define G_MC_BANK0_MAP(x)          _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP)

 
 

-#define K_MC_BANK0_MAP_DEFAULT      0x00
-#define V_MC_BANK0_MAP_DEFAULT      V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT)
+#define K_MC_BANK0_MAP_DEFAULT     0x00
+#define V_MC_BANK0_MAP_DEFAULT     V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT)

 
 

-#define S_MC_BANK1_MAP              20
-#define M_MC_BANK1_MAP              _SB_MAKEMASK(4, S_MC_BANK1_MAP)
-#define V_MC_BANK1_MAP(x)           _SB_MAKEVALUE(x, S_MC_BANK1_MAP)
-#define G_MC_BANK1_MAP(x)           _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP)
+#define S_MC_BANK1_MAP             20
+#define M_MC_BANK1_MAP             _SB_MAKEMASK(4, S_MC_BANK1_MAP)
+#define V_MC_BANK1_MAP(x)          _SB_MAKEVALUE(x, S_MC_BANK1_MAP)
+#define G_MC_BANK1_MAP(x)          _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP)

 
 

-#define K_MC_BANK1_MAP_DEFAULT      0x08
-#define V_MC_BANK1_MAP_DEFAULT      V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT)
+#define K_MC_BANK1_MAP_DEFAULT     0x08
+#define V_MC_BANK1_MAP_DEFAULT     V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT)

 
 

-#define S_MC_BANK2_MAP              24
-#define M_MC_BANK2_MAP              _SB_MAKEMASK(4, S_MC_BANK2_MAP)
-#define V_MC_BANK2_MAP(x)           _SB_MAKEVALUE(x, S_MC_BANK2_MAP)
-#define G_MC_BANK2_MAP(x)           _SB_GETVALUE(x, S_MC_BANK2_MAP, M_MC_BANK2_MAP)
+#define S_MC_BANK2_MAP             24
+#define M_MC_BANK2_MAP             _SB_MAKEMASK(4, S_MC_BANK2_MAP)
+#define V_MC_BANK2_MAP(x)          _SB_MAKEVALUE(x, S_MC_BANK2_MAP)
+#define G_MC_BANK2_MAP(x)          _SB_GETVALUE(x, S_MC_BANK2_MAP, M_MC_BANK2_MAP)

 
 

-#define K_MC_BANK2_MAP_DEFAULT      0x09
-#define V_MC_BANK2_MAP_DEFAULT      V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT)
+#define K_MC_BANK2_MAP_DEFAULT     0x09
+#define V_MC_BANK2_MAP_DEFAULT     V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT)

 
 

-#define S_MC_BANK3_MAP              28
-#define M_MC_BANK3_MAP              _SB_MAKEMASK(4, S_MC_BANK3_MAP)
-#define V_MC_BANK3_MAP(x)           _SB_MAKEVALUE(x, S_MC_BANK3_MAP)
-#define G_MC_BANK3_MAP(x)           _SB_GETVALUE(x, S_MC_BANK3_MAP, M_MC_BANK3_MAP)
+#define S_MC_BANK3_MAP             28
+#define M_MC_BANK3_MAP             _SB_MAKEMASK(4, S_MC_BANK3_MAP)
+#define V_MC_BANK3_MAP(x)          _SB_MAKEVALUE(x, S_MC_BANK3_MAP)
+#define G_MC_BANK3_MAP(x)          _SB_GETVALUE(x, S_MC_BANK3_MAP, M_MC_BANK3_MAP)

 
 

-#define K_MC_BANK3_MAP_DEFAULT      0x0C
-#define V_MC_BANK3_MAP_DEFAULT      V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT)
+#define K_MC_BANK3_MAP_DEFAULT     0x0C
+#define V_MC_BANK3_MAP_DEFAULT     V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT)

 
 

-#define M_MC_RESERVED1              _SB_MAKEMASK(8, 32)
+#define M_MC_RESERVED1             _SB_MAKEMASK(8, 32)

 
 #define S_MC_QUEUE_SIZE                    40
 
 #define S_MC_QUEUE_SIZE                    40

-#define M_MC_QUEUE_SIZE             _SB_MAKEMASK(4, S_MC_QUEUE_SIZE)
-#define V_MC_QUEUE_SIZE(x)          _SB_MAKEVALUE(x, S_MC_QUEUE_SIZE)
-#define G_MC_QUEUE_SIZE(x)          _SB_GETVALUE(x, S_MC_QUEUE_SIZE, M_MC_QUEUE_SIZE)
-#define V_MC_QUEUE_SIZE_DEFAULT     V_MC_QUEUE_SIZE(0x0A)
-
-#define S_MC_AGE_LIMIT              44
-#define M_MC_AGE_LIMIT              _SB_MAKEMASK(4, S_MC_AGE_LIMIT)
-#define V_MC_AGE_LIMIT(x)           _SB_MAKEVALUE(x, S_MC_AGE_LIMIT)
-#define G_MC_AGE_LIMIT(x)           _SB_GETVALUE(x, S_MC_AGE_LIMIT, M_MC_AGE_LIMIT)
-#define V_MC_AGE_LIMIT_DEFAULT      V_MC_AGE_LIMIT(8)
-
-#define S_MC_WR_LIMIT               48
-#define M_MC_WR_LIMIT               _SB_MAKEMASK(4, S_MC_WR_LIMIT)
-#define V_MC_WR_LIMIT(x)            _SB_MAKEVALUE(x, S_MC_WR_LIMIT)
-#define G_MC_WR_LIMIT(x)            _SB_GETVALUE(x, S_MC_WR_LIMIT, M_MC_WR_LIMIT)
-#define V_MC_WR_LIMIT_DEFAULT       V_MC_WR_LIMIT(5)
+#define M_MC_QUEUE_SIZE                    _SB_MAKEMASK(4, S_MC_QUEUE_SIZE)
+#define V_MC_QUEUE_SIZE(x)         _SB_MAKEVALUE(x, S_MC_QUEUE_SIZE)
+#define G_MC_QUEUE_SIZE(x)         _SB_GETVALUE(x, S_MC_QUEUE_SIZE, M_MC_QUEUE_SIZE)
+#define V_MC_QUEUE_SIZE_DEFAULT            V_MC_QUEUE_SIZE(0x0A)
+
+#define S_MC_AGE_LIMIT             44
+#define M_MC_AGE_LIMIT             _SB_MAKEMASK(4, S_MC_AGE_LIMIT)
+#define V_MC_AGE_LIMIT(x)          _SB_MAKEVALUE(x, S_MC_AGE_LIMIT)
+#define G_MC_AGE_LIMIT(x)          _SB_GETVALUE(x, S_MC_AGE_LIMIT, M_MC_AGE_LIMIT)
+#define V_MC_AGE_LIMIT_DEFAULT     V_MC_AGE_LIMIT(8)
+
+#define S_MC_WR_LIMIT              48
+#define M_MC_WR_LIMIT              _SB_MAKEMASK(4, S_MC_WR_LIMIT)
+#define V_MC_WR_LIMIT(x)           _SB_MAKEVALUE(x, S_MC_WR_LIMIT)
+#define G_MC_WR_LIMIT(x)           _SB_GETVALUE(x, S_MC_WR_LIMIT, M_MC_WR_LIMIT)
+#define V_MC_WR_LIMIT_DEFAULT      V_MC_WR_LIMIT(5)

 
 #define M_MC_IOB1HIGHPRIORITY      _SB_MAKEMASK1(52)
 
 
 #define M_MC_IOB1HIGHPRIORITY      _SB_MAKEMASK1(52)
 

-#define M_MC_RESERVED2              _SB_MAKEMASK(3, 53)
+#define M_MC_RESERVED2             _SB_MAKEMASK(3, 53)

 
 

-#define S_MC_CS_MODE                56
-#define M_MC_CS_MODE                _SB_MAKEMASK(4, S_MC_CS_MODE)
-#define V_MC_CS_MODE(x)             _SB_MAKEVALUE(x, S_MC_CS_MODE)
-#define G_MC_CS_MODE(x)             _SB_GETVALUE(x, S_MC_CS_MODE, M_MC_CS_MODE)
+#define S_MC_CS_MODE               56
+#define M_MC_CS_MODE               _SB_MAKEMASK(4, S_MC_CS_MODE)
+#define V_MC_CS_MODE(x)                    _SB_MAKEVALUE(x, S_MC_CS_MODE)
+#define G_MC_CS_MODE(x)                    _SB_GETVALUE(x, S_MC_CS_MODE, M_MC_CS_MODE)

 
 

-#define K_MC_CS_MODE_MSB_CS         0
-#define K_MC_CS_MODE_INTLV_CS       15
+#define K_MC_CS_MODE_MSB_CS        0
+#define K_MC_CS_MODE_INTLV_CS      15

 #define K_MC_CS_MODE_MIXED_CS_10    12
 #define K_MC_CS_MODE_MIXED_CS_30    6
 #define K_MC_CS_MODE_MIXED_CS_32    3
 
 #define K_MC_CS_MODE_MIXED_CS_10    12
 #define K_MC_CS_MODE_MIXED_CS_30    6
 #define K_MC_CS_MODE_MIXED_CS_32    3
 

-#define V_MC_CS_MODE_MSB_CS         V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS)
-#define V_MC_CS_MODE_INTLV_CS       V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS)
+#define V_MC_CS_MODE_MSB_CS        V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS)
+#define V_MC_CS_MODE_INTLV_CS      V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS)

 #define V_MC_CS_MODE_MIXED_CS_10    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10)
 #define V_MC_CS_MODE_MIXED_CS_30    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30)
 #define V_MC_CS_MODE_MIXED_CS_32    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32)
 
 #define V_MC_CS_MODE_MIXED_CS_10    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10)
 #define V_MC_CS_MODE_MIXED_CS_30    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30)
 #define V_MC_CS_MODE_MIXED_CS_32    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32)
 

-#define M_MC_ECC_DISABLE            _SB_MAKEMASK1(60)
-#define M_MC_BERR_DISABLE           _SB_MAKEMASK1(61)
-#define M_MC_FORCE_SEQ              _SB_MAKEMASK1(62)
-#define M_MC_DEBUG                  _SB_MAKEMASK1(63)
+#define M_MC_ECC_DISABLE           _SB_MAKEMASK1(60)
+#define M_MC_BERR_DISABLE          _SB_MAKEMASK1(61)
+#define M_MC_FORCE_SEQ             _SB_MAKEMASK1(62)
+#define M_MC_DEBUG                 _SB_MAKEMASK1(63)

 
 

-#define V_MC_CONFIG_DEFAULT     V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \
+#define V_MC_CONFIG_DEFAULT    V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \

                                V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \
                                V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \
                                V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \
                                V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \

-                                M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT
+                               M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT

 
 
 /*
 
 
 /*


@@ -137,96 +137,96 @@
  * Note: this field has been updated to be consistent with the errata to 0.2
  */
 
  * Note: this field has been updated to be consistent with the errata to 0.2
  */
 

-#define S_MC_CLK_RATIO              0
-#define M_MC_CLK_RATIO              _SB_MAKEMASK(4, S_MC_CLK_RATIO)
-#define V_MC_CLK_RATIO(x)           _SB_MAKEVALUE(x, S_MC_CLK_RATIO)
-#define G_MC_CLK_RATIO(x)           _SB_GETVALUE(x, S_MC_CLK_RATIO, M_MC_CLK_RATIO)
+#define S_MC_CLK_RATIO             0
+#define M_MC_CLK_RATIO             _SB_MAKEMASK(4, S_MC_CLK_RATIO)
+#define V_MC_CLK_RATIO(x)          _SB_MAKEVALUE(x, S_MC_CLK_RATIO)
+#define G_MC_CLK_RATIO(x)          _SB_GETVALUE(x, S_MC_CLK_RATIO, M_MC_CLK_RATIO)

 
 

-#define K_MC_CLK_RATIO_2X           4
-#define K_MC_CLK_RATIO_25X          5
-#define K_MC_CLK_RATIO_3X           6
-#define K_MC_CLK_RATIO_35X          7
-#define K_MC_CLK_RATIO_4X           8
+#define K_MC_CLK_RATIO_2X          4
+#define K_MC_CLK_RATIO_25X         5
+#define K_MC_CLK_RATIO_3X          6
+#define K_MC_CLK_RATIO_35X         7
+#define K_MC_CLK_RATIO_4X          8

 #define K_MC_CLK_RATIO_45X         9
 
 #define V_MC_CLK_RATIO_2X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X)
 #define K_MC_CLK_RATIO_45X         9
 
 #define V_MC_CLK_RATIO_2X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X)

-#define V_MC_CLK_RATIO_25X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X)
-#define V_MC_CLK_RATIO_3X           V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X)
-#define V_MC_CLK_RATIO_35X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X)
-#define V_MC_CLK_RATIO_4X           V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X)
-#define V_MC_CLK_RATIO_45X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X)
-#define V_MC_CLK_RATIO_DEFAULT      V_MC_CLK_RATIO_25X
-
-#define S_MC_REF_RATE                8
-#define M_MC_REF_RATE                _SB_MAKEMASK(8, S_MC_REF_RATE)
-#define V_MC_REF_RATE(x)             _SB_MAKEVALUE(x, S_MC_REF_RATE)
-#define G_MC_REF_RATE(x)             _SB_GETVALUE(x, S_MC_REF_RATE, M_MC_REF_RATE)
-
-#define K_MC_REF_RATE_100MHz         0x62
-#define K_MC_REF_RATE_133MHz         0x81
-#define K_MC_REF_RATE_200MHz         0xC4
-
-#define V_MC_REF_RATE_100MHz         V_MC_REF_RATE(K_MC_REF_RATE_100MHz)
-#define V_MC_REF_RATE_133MHz         V_MC_REF_RATE(K_MC_REF_RATE_133MHz)
-#define V_MC_REF_RATE_200MHz         V_MC_REF_RATE(K_MC_REF_RATE_200MHz)
-#define V_MC_REF_RATE_DEFAULT        V_MC_REF_RATE_100MHz
-
-#define S_MC_CLOCK_DRIVE             16
-#define M_MC_CLOCK_DRIVE             _SB_MAKEMASK(4, S_MC_CLOCK_DRIVE)
-#define V_MC_CLOCK_DRIVE(x)          _SB_MAKEVALUE(x, S_MC_CLOCK_DRIVE)
-#define G_MC_CLOCK_DRIVE(x)          _SB_GETVALUE(x, S_MC_CLOCK_DRIVE, M_MC_CLOCK_DRIVE)
+#define V_MC_CLK_RATIO_25X         V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X)
+#define V_MC_CLK_RATIO_3X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X)
+#define V_MC_CLK_RATIO_35X         V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X)
+#define V_MC_CLK_RATIO_4X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X)
+#define V_MC_CLK_RATIO_45X         V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X)
+#define V_MC_CLK_RATIO_DEFAULT     V_MC_CLK_RATIO_25X
+
+#define S_MC_REF_RATE               8
+#define M_MC_REF_RATE               _SB_MAKEMASK(8, S_MC_REF_RATE)
+#define V_MC_REF_RATE(x)            _SB_MAKEVALUE(x, S_MC_REF_RATE)
+#define G_MC_REF_RATE(x)            _SB_GETVALUE(x, S_MC_REF_RATE, M_MC_REF_RATE)
+
+#define K_MC_REF_RATE_100MHz        0x62
+#define K_MC_REF_RATE_133MHz        0x81
+#define K_MC_REF_RATE_200MHz        0xC4
+
+#define V_MC_REF_RATE_100MHz        V_MC_REF_RATE(K_MC_REF_RATE_100MHz)
+#define V_MC_REF_RATE_133MHz        V_MC_REF_RATE(K_MC_REF_RATE_133MHz)
+#define V_MC_REF_RATE_200MHz        V_MC_REF_RATE(K_MC_REF_RATE_200MHz)
+#define V_MC_REF_RATE_DEFAULT       V_MC_REF_RATE_100MHz
+
+#define S_MC_CLOCK_DRIVE            16
+#define M_MC_CLOCK_DRIVE            _SB_MAKEMASK(4, S_MC_CLOCK_DRIVE)
+#define V_MC_CLOCK_DRIVE(x)         _SB_MAKEVALUE(x, S_MC_CLOCK_DRIVE)
+#define G_MC_CLOCK_DRIVE(x)         _SB_GETVALUE(x, S_MC_CLOCK_DRIVE, M_MC_CLOCK_DRIVE)

 #define V_MC_CLOCK_DRIVE_DEFAULT     V_MC_CLOCK_DRIVE(0xF)
 
 #define V_MC_CLOCK_DRIVE_DEFAULT     V_MC_CLOCK_DRIVE(0xF)
 

-#define S_MC_DATA_DRIVE              20
-#define M_MC_DATA_DRIVE              _SB_MAKEMASK(4, S_MC_DATA_DRIVE)
-#define V_MC_DATA_DRIVE(x)           _SB_MAKEVALUE(x, S_MC_DATA_DRIVE)
-#define G_MC_DATA_DRIVE(x)           _SB_GETVALUE(x, S_MC_DATA_DRIVE, M_MC_DATA_DRIVE)
-#define V_MC_DATA_DRIVE_DEFAULT      V_MC_DATA_DRIVE(0x0)
+#define S_MC_DATA_DRIVE                     20
+#define M_MC_DATA_DRIVE                     _SB_MAKEMASK(4, S_MC_DATA_DRIVE)
+#define V_MC_DATA_DRIVE(x)          _SB_MAKEVALUE(x, S_MC_DATA_DRIVE)
+#define G_MC_DATA_DRIVE(x)          _SB_GETVALUE(x, S_MC_DATA_DRIVE, M_MC_DATA_DRIVE)
+#define V_MC_DATA_DRIVE_DEFAULT             V_MC_DATA_DRIVE(0x0)

 
 

-#define S_MC_ADDR_DRIVE              24
-#define M_MC_ADDR_DRIVE              _SB_MAKEMASK(4, S_MC_ADDR_DRIVE)
-#define V_MC_ADDR_DRIVE(x)           _SB_MAKEVALUE(x, S_MC_ADDR_DRIVE)
-#define G_MC_ADDR_DRIVE(x)           _SB_GETVALUE(x, S_MC_ADDR_DRIVE, M_MC_ADDR_DRIVE)
-#define V_MC_ADDR_DRIVE_DEFAULT      V_MC_ADDR_DRIVE(0x0)
+#define S_MC_ADDR_DRIVE                     24
+#define M_MC_ADDR_DRIVE                     _SB_MAKEMASK(4, S_MC_ADDR_DRIVE)
+#define V_MC_ADDR_DRIVE(x)          _SB_MAKEVALUE(x, S_MC_ADDR_DRIVE)
+#define G_MC_ADDR_DRIVE(x)          _SB_GETVALUE(x, S_MC_ADDR_DRIVE, M_MC_ADDR_DRIVE)
+#define V_MC_ADDR_DRIVE_DEFAULT             V_MC_ADDR_DRIVE(0x0)

 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)

-#define M_MC_REF_DISABLE             _SB_MAKEMASK1(30)
+#define M_MC_REF_DISABLE            _SB_MAKEMASK1(30)

 #endif /* 1250 PASS3 || 112x PASS1 */
 
 #endif /* 1250 PASS3 || 112x PASS1 */
 

-#define M_MC_DLL_BYPASS              _SB_MAKEMASK1(31)
-
-#define S_MC_DQI_SKEW               32
-#define M_MC_DQI_SKEW               _SB_MAKEMASK(8, S_MC_DQI_SKEW)
-#define V_MC_DQI_SKEW(x)            _SB_MAKEVALUE(x, S_MC_DQI_SKEW)
-#define G_MC_DQI_SKEW(x)            _SB_GETVALUE(x, S_MC_DQI_SKEW, M_MC_DQI_SKEW)
-#define V_MC_DQI_SKEW_DEFAULT       V_MC_DQI_SKEW(0)
-
-#define S_MC_DQO_SKEW               40
-#define M_MC_DQO_SKEW               _SB_MAKEMASK(8, S_MC_DQO_SKEW)
-#define V_MC_DQO_SKEW(x)            _SB_MAKEVALUE(x, S_MC_DQO_SKEW)
-#define G_MC_DQO_SKEW(x)            _SB_GETVALUE(x, S_MC_DQO_SKEW, M_MC_DQO_SKEW)
-#define V_MC_DQO_SKEW_DEFAULT       V_MC_DQO_SKEW(0)
-
-#define S_MC_ADDR_SKEW               48
-#define M_MC_ADDR_SKEW               _SB_MAKEMASK(8, S_MC_ADDR_SKEW)
-#define V_MC_ADDR_SKEW(x)            _SB_MAKEVALUE(x, S_MC_ADDR_SKEW)
-#define G_MC_ADDR_SKEW(x)            _SB_GETVALUE(x, S_MC_ADDR_SKEW, M_MC_ADDR_SKEW)
-#define V_MC_ADDR_SKEW_DEFAULT       V_MC_ADDR_SKEW(0x0F)
-
-#define S_MC_DLL_DEFAULT             56
-#define M_MC_DLL_DEFAULT             _SB_MAKEMASK(8, S_MC_DLL_DEFAULT)
-#define V_MC_DLL_DEFAULT(x)          _SB_MAKEVALUE(x, S_MC_DLL_DEFAULT)
-#define G_MC_DLL_DEFAULT(x)          _SB_GETVALUE(x, S_MC_DLL_DEFAULT, M_MC_DLL_DEFAULT)
+#define M_MC_DLL_BYPASS                     _SB_MAKEMASK1(31)
+
+#define S_MC_DQI_SKEW              32
+#define M_MC_DQI_SKEW              _SB_MAKEMASK(8, S_MC_DQI_SKEW)
+#define V_MC_DQI_SKEW(x)           _SB_MAKEVALUE(x, S_MC_DQI_SKEW)
+#define G_MC_DQI_SKEW(x)           _SB_GETVALUE(x, S_MC_DQI_SKEW, M_MC_DQI_SKEW)
+#define V_MC_DQI_SKEW_DEFAULT      V_MC_DQI_SKEW(0)
+
+#define S_MC_DQO_SKEW              40
+#define M_MC_DQO_SKEW              _SB_MAKEMASK(8, S_MC_DQO_SKEW)
+#define V_MC_DQO_SKEW(x)           _SB_MAKEVALUE(x, S_MC_DQO_SKEW)
+#define G_MC_DQO_SKEW(x)           _SB_GETVALUE(x, S_MC_DQO_SKEW, M_MC_DQO_SKEW)
+#define V_MC_DQO_SKEW_DEFAULT      V_MC_DQO_SKEW(0)
+
+#define S_MC_ADDR_SKEW              48
+#define M_MC_ADDR_SKEW              _SB_MAKEMASK(8, S_MC_ADDR_SKEW)
+#define V_MC_ADDR_SKEW(x)           _SB_MAKEVALUE(x, S_MC_ADDR_SKEW)
+#define G_MC_ADDR_SKEW(x)           _SB_GETVALUE(x, S_MC_ADDR_SKEW, M_MC_ADDR_SKEW)
+#define V_MC_ADDR_SKEW_DEFAULT      V_MC_ADDR_SKEW(0x0F)
+
+#define S_MC_DLL_DEFAULT            56
+#define M_MC_DLL_DEFAULT            _SB_MAKEMASK(8, S_MC_DLL_DEFAULT)
+#define V_MC_DLL_DEFAULT(x)         _SB_MAKEVALUE(x, S_MC_DLL_DEFAULT)
+#define G_MC_DLL_DEFAULT(x)         _SB_GETVALUE(x, S_MC_DLL_DEFAULT, M_MC_DLL_DEFAULT)

 #define V_MC_DLL_DEFAULT_DEFAULT     V_MC_DLL_DEFAULT(0x10)
 
 #define V_MC_DLL_DEFAULT_DEFAULT     V_MC_DLL_DEFAULT(0x10)
 

-#define V_MC_CLKCONFIG_DEFAULT       V_MC_DLL_DEFAULT_DEFAULT |  \
-                                     V_MC_ADDR_SKEW_DEFAULT | \
-                                     V_MC_DQO_SKEW_DEFAULT | \
-                                     V_MC_DQI_SKEW_DEFAULT | \
-                                     V_MC_ADDR_DRIVE_DEFAULT | \
-                                     V_MC_DATA_DRIVE_DEFAULT | \
-                                     V_MC_CLOCK_DRIVE_DEFAULT | \
-                                     V_MC_REF_RATE_DEFAULT
+#define V_MC_CLKCONFIG_DEFAULT      V_MC_DLL_DEFAULT_DEFAULT |  \
+                                    V_MC_ADDR_SKEW_DEFAULT | \
+                                    V_MC_DQO_SKEW_DEFAULT | \
+                                    V_MC_DQI_SKEW_DEFAULT | \
+                                    V_MC_ADDR_DRIVE_DEFAULT | \
+                                    V_MC_DATA_DRIVE_DEFAULT | \
+                                    V_MC_CLOCK_DRIVE_DEFAULT | \
+                                    V_MC_REF_RATE_DEFAULT

 
 
 
 
 
 


@@ -234,68 +234,68 @@
  * DRAM Command Register (Table 6-13)
  */
 
  * DRAM Command Register (Table 6-13)
  */
 

-#define S_MC_COMMAND                0
-#define M_MC_COMMAND                _SB_MAKEMASK(4, S_MC_COMMAND)
-#define V_MC_COMMAND(x)             _SB_MAKEVALUE(x, S_MC_COMMAND)
-#define G_MC_COMMAND(x)             _SB_GETVALUE(x, S_MC_COMMAND, M_MC_COMMAND)
-
-#define K_MC_COMMAND_EMRS           0
-#define K_MC_COMMAND_MRS            1
-#define K_MC_COMMAND_PRE            2
-#define K_MC_COMMAND_AR             3
-#define K_MC_COMMAND_SETRFSH        4
-#define K_MC_COMMAND_CLRRFSH        5
-#define K_MC_COMMAND_SETPWRDN       6
-#define K_MC_COMMAND_CLRPWRDN       7
-
-#define V_MC_COMMAND_EMRS           V_MC_COMMAND(K_MC_COMMAND_EMRS)
-#define V_MC_COMMAND_MRS            V_MC_COMMAND(K_MC_COMMAND_MRS)
-#define V_MC_COMMAND_PRE            V_MC_COMMAND(K_MC_COMMAND_PRE)
-#define V_MC_COMMAND_AR             V_MC_COMMAND(K_MC_COMMAND_AR)
-#define V_MC_COMMAND_SETRFSH        V_MC_COMMAND(K_MC_COMMAND_SETRFSH)
-#define V_MC_COMMAND_CLRRFSH        V_MC_COMMAND(K_MC_COMMAND_CLRRFSH)
-#define V_MC_COMMAND_SETPWRDN       V_MC_COMMAND(K_MC_COMMAND_SETPWRDN)
-#define V_MC_COMMAND_CLRPWRDN       V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN)
-
-#define M_MC_CS0                    _SB_MAKEMASK1(4)
-#define M_MC_CS1                    _SB_MAKEMASK1(5)
-#define M_MC_CS2                    _SB_MAKEMASK1(6)
-#define M_MC_CS3                    _SB_MAKEMASK1(7)
+#define S_MC_COMMAND               0
+#define M_MC_COMMAND               _SB_MAKEMASK(4, S_MC_COMMAND)
+#define V_MC_COMMAND(x)                    _SB_MAKEVALUE(x, S_MC_COMMAND)
+#define G_MC_COMMAND(x)                    _SB_GETVALUE(x, S_MC_COMMAND, M_MC_COMMAND)
+
+#define K_MC_COMMAND_EMRS          0
+#define K_MC_COMMAND_MRS           1
+#define K_MC_COMMAND_PRE           2
+#define K_MC_COMMAND_AR                    3
+#define K_MC_COMMAND_SETRFSH       4
+#define K_MC_COMMAND_CLRRFSH       5
+#define K_MC_COMMAND_SETPWRDN      6
+#define K_MC_COMMAND_CLRPWRDN      7
+
+#define V_MC_COMMAND_EMRS          V_MC_COMMAND(K_MC_COMMAND_EMRS)
+#define V_MC_COMMAND_MRS           V_MC_COMMAND(K_MC_COMMAND_MRS)
+#define V_MC_COMMAND_PRE           V_MC_COMMAND(K_MC_COMMAND_PRE)
+#define V_MC_COMMAND_AR                    V_MC_COMMAND(K_MC_COMMAND_AR)
+#define V_MC_COMMAND_SETRFSH       V_MC_COMMAND(K_MC_COMMAND_SETRFSH)
+#define V_MC_COMMAND_CLRRFSH       V_MC_COMMAND(K_MC_COMMAND_CLRRFSH)
+#define V_MC_COMMAND_SETPWRDN      V_MC_COMMAND(K_MC_COMMAND_SETPWRDN)
+#define V_MC_COMMAND_CLRPWRDN      V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN)
+
+#define M_MC_CS0                   _SB_MAKEMASK1(4)
+#define M_MC_CS1                   _SB_MAKEMASK1(5)
+#define M_MC_CS2                   _SB_MAKEMASK1(6)
+#define M_MC_CS3                   _SB_MAKEMASK1(7)

 
 /*
  * DRAM Mode Register (Table 6-14)
  */
 
 
 /*
  * DRAM Mode Register (Table 6-14)
  */
 

-#define S_MC_EMODE                  0
-#define M_MC_EMODE                  _SB_MAKEMASK(15, S_MC_EMODE)
-#define V_MC_EMODE(x)               _SB_MAKEVALUE(x, S_MC_EMODE)
-#define G_MC_EMODE(x)               _SB_GETVALUE(x, S_MC_EMODE, M_MC_EMODE)
-#define V_MC_EMODE_DEFAULT          V_MC_EMODE(0)
-
-#define S_MC_MODE                   16
-#define M_MC_MODE                   _SB_MAKEMASK(15, S_MC_MODE)
-#define V_MC_MODE(x)                _SB_MAKEVALUE(x, S_MC_MODE)
-#define G_MC_MODE(x)                _SB_GETVALUE(x, S_MC_MODE, M_MC_MODE)
-#define V_MC_MODE_DEFAULT           V_MC_MODE(0x22)
-
-#define S_MC_DRAM_TYPE              32
-#define M_MC_DRAM_TYPE              _SB_MAKEMASK(3, S_MC_DRAM_TYPE)
-#define V_MC_DRAM_TYPE(x)           _SB_MAKEVALUE(x, S_MC_DRAM_TYPE)
-#define G_MC_DRAM_TYPE(x)           _SB_GETVALUE(x, S_MC_DRAM_TYPE, M_MC_DRAM_TYPE)
-
-#define K_MC_DRAM_TYPE_JEDEC        0
-#define K_MC_DRAM_TYPE_FCRAM        1
+#define S_MC_EMODE                 0
+#define M_MC_EMODE                 _SB_MAKEMASK(15, S_MC_EMODE)
+#define V_MC_EMODE(x)              _SB_MAKEVALUE(x, S_MC_EMODE)
+#define G_MC_EMODE(x)              _SB_GETVALUE(x, S_MC_EMODE, M_MC_EMODE)
+#define V_MC_EMODE_DEFAULT         V_MC_EMODE(0)
+
+#define S_MC_MODE                  16
+#define M_MC_MODE                  _SB_MAKEMASK(15, S_MC_MODE)
+#define V_MC_MODE(x)               _SB_MAKEVALUE(x, S_MC_MODE)
+#define G_MC_MODE(x)               _SB_GETVALUE(x, S_MC_MODE, M_MC_MODE)
+#define V_MC_MODE_DEFAULT          V_MC_MODE(0x22)
+
+#define S_MC_DRAM_TYPE             32
+#define M_MC_DRAM_TYPE             _SB_MAKEMASK(3, S_MC_DRAM_TYPE)
+#define V_MC_DRAM_TYPE(x)          _SB_MAKEVALUE(x, S_MC_DRAM_TYPE)
+#define G_MC_DRAM_TYPE(x)          _SB_GETVALUE(x, S_MC_DRAM_TYPE, M_MC_DRAM_TYPE)
+
+#define K_MC_DRAM_TYPE_JEDEC       0
+#define K_MC_DRAM_TYPE_FCRAM       1

 #define K_MC_DRAM_TYPE_SGRAM       2
 
 #define K_MC_DRAM_TYPE_SGRAM       2
 

-#define V_MC_DRAM_TYPE_JEDEC        V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC)
-#define V_MC_DRAM_TYPE_FCRAM        V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM)
-#define V_MC_DRAM_TYPE_SGRAM        V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM)
+#define V_MC_DRAM_TYPE_JEDEC       V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC)
+#define V_MC_DRAM_TYPE_FCRAM       V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM)
+#define V_MC_DRAM_TYPE_SGRAM       V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM)

 
 #define M_MC_EXTERNALDECODE        _SB_MAKEMASK1(35)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 
 #define M_MC_EXTERNALDECODE        _SB_MAKEMASK1(35)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)

-#define M_MC_PRE_ON_A8              _SB_MAKEMASK1(36)
-#define M_MC_RAM_WITH_A13           _SB_MAKEMASK1(37)
+#define M_MC_PRE_ON_A8             _SB_MAKEMASK1(36)
+#define M_MC_RAM_WITH_A13          _SB_MAKEMASK1(37)

 #endif /* 1250 PASS3 || 112x PASS1 */
 
 
 #endif /* 1250 PASS3 || 112x PASS1 */
 
 


@@ -308,99 +308,99 @@
 #define M_MC_r2wIDLE_TWOCYCLES   _SB_MAKEMASK1(61)
 #define M_MC_r2rIDLE_TWOCYCLES   _SB_MAKEMASK1(62)
 
 #define M_MC_r2wIDLE_TWOCYCLES   _SB_MAKEMASK1(61)
 #define M_MC_r2rIDLE_TWOCYCLES   _SB_MAKEMASK1(62)
 

-#define S_MC_tFIFO                56
-#define M_MC_tFIFO                _SB_MAKEMASK(4, S_MC_tFIFO)
-#define V_MC_tFIFO(x)             _SB_MAKEVALUE(x, S_MC_tFIFO)
-#define G_MC_tFIFO(x)             _SB_GETVALUE(x, S_MC_tFIFO, M_MC_tFIFO)
-#define K_MC_tFIFO_DEFAULT        1
-#define V_MC_tFIFO_DEFAULT        V_MC_tFIFO(K_MC_tFIFO_DEFAULT)
+#define S_MC_tFIFO               56
+#define M_MC_tFIFO               _SB_MAKEMASK(4, S_MC_tFIFO)
+#define V_MC_tFIFO(x)            _SB_MAKEVALUE(x, S_MC_tFIFO)
+#define G_MC_tFIFO(x)            _SB_GETVALUE(x, S_MC_tFIFO, M_MC_tFIFO)
+#define K_MC_tFIFO_DEFAULT       1
+#define V_MC_tFIFO_DEFAULT       V_MC_tFIFO(K_MC_tFIFO_DEFAULT)

 
 

-#define S_MC_tRFC                 52
-#define M_MC_tRFC                 _SB_MAKEMASK(4, S_MC_tRFC)
-#define V_MC_tRFC(x)              _SB_MAKEVALUE(x, S_MC_tRFC)
-#define G_MC_tRFC(x)              _SB_GETVALUE(x, S_MC_tRFC, M_MC_tRFC)
-#define K_MC_tRFC_DEFAULT         12
-#define V_MC_tRFC_DEFAULT         V_MC_tRFC(K_MC_tRFC_DEFAULT)
+#define S_MC_tRFC                52
+#define M_MC_tRFC                _SB_MAKEMASK(4, S_MC_tRFC)
+#define V_MC_tRFC(x)             _SB_MAKEVALUE(x, S_MC_tRFC)
+#define G_MC_tRFC(x)             _SB_GETVALUE(x, S_MC_tRFC, M_MC_tRFC)
+#define K_MC_tRFC_DEFAULT        12
+#define V_MC_tRFC_DEFAULT        V_MC_tRFC(K_MC_tRFC_DEFAULT)

 
 #if SIBYTE_HDR_FEATURE(1250, PASS3)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3)

-#define M_MC_tRFC_PLUS16          _SB_MAKEMASK1(51)    /* 1250C3 and later.  */
+#define M_MC_tRFC_PLUS16         _SB_MAKEMASK1(51)     /* 1250C3 and later.  */

 #endif
 
 #endif
 

-#define S_MC_tCwCr                40
-#define M_MC_tCwCr                _SB_MAKEMASK(4, S_MC_tCwCr)
-#define V_MC_tCwCr(x)             _SB_MAKEVALUE(x, S_MC_tCwCr)
-#define G_MC_tCwCr(x)             _SB_GETVALUE(x, S_MC_tCwCr, M_MC_tCwCr)
-#define K_MC_tCwCr_DEFAULT        4
-#define V_MC_tCwCr_DEFAULT        V_MC_tCwCr(K_MC_tCwCr_DEFAULT)
-
-#define S_MC_tRCr                 28
-#define M_MC_tRCr                 _SB_MAKEMASK(4, S_MC_tRCr)
-#define V_MC_tRCr(x)              _SB_MAKEVALUE(x, S_MC_tRCr)
-#define G_MC_tRCr(x)              _SB_GETVALUE(x, S_MC_tRCr, M_MC_tRCr)
-#define K_MC_tRCr_DEFAULT         9
-#define V_MC_tRCr_DEFAULT         V_MC_tRCr(K_MC_tRCr_DEFAULT)
-
-#define S_MC_tRCw                 24
-#define M_MC_tRCw                 _SB_MAKEMASK(4, S_MC_tRCw)
-#define V_MC_tRCw(x)              _SB_MAKEVALUE(x, S_MC_tRCw)
-#define G_MC_tRCw(x)              _SB_GETVALUE(x, S_MC_tRCw, M_MC_tRCw)
-#define K_MC_tRCw_DEFAULT         10
-#define V_MC_tRCw_DEFAULT         V_MC_tRCw(K_MC_tRCw_DEFAULT)
-
-#define S_MC_tRRD                 20
-#define M_MC_tRRD                 _SB_MAKEMASK(4, S_MC_tRRD)
-#define V_MC_tRRD(x)              _SB_MAKEVALUE(x, S_MC_tRRD)
-#define G_MC_tRRD(x)              _SB_GETVALUE(x, S_MC_tRRD, M_MC_tRRD)
-#define K_MC_tRRD_DEFAULT         2
-#define V_MC_tRRD_DEFAULT         V_MC_tRRD(K_MC_tRRD_DEFAULT)
-
-#define S_MC_tRP                  16
-#define M_MC_tRP                  _SB_MAKEMASK(4, S_MC_tRP)
-#define V_MC_tRP(x)               _SB_MAKEVALUE(x, S_MC_tRP)
-#define G_MC_tRP(x)               _SB_GETVALUE(x, S_MC_tRP, M_MC_tRP)
-#define K_MC_tRP_DEFAULT          4
-#define V_MC_tRP_DEFAULT          V_MC_tRP(K_MC_tRP_DEFAULT)
-
-#define S_MC_tCwD                 8
-#define M_MC_tCwD                 _SB_MAKEMASK(4, S_MC_tCwD)
-#define V_MC_tCwD(x)              _SB_MAKEVALUE(x, S_MC_tCwD)
-#define G_MC_tCwD(x)              _SB_GETVALUE(x, S_MC_tCwD, M_MC_tCwD)
-#define K_MC_tCwD_DEFAULT         1
-#define V_MC_tCwD_DEFAULT         V_MC_tCwD(K_MC_tCwD_DEFAULT)
-
-#define M_tCrDh                   _SB_MAKEMASK1(7)
+#define S_MC_tCwCr               40
+#define M_MC_tCwCr               _SB_MAKEMASK(4, S_MC_tCwCr)
+#define V_MC_tCwCr(x)            _SB_MAKEVALUE(x, S_MC_tCwCr)
+#define G_MC_tCwCr(x)            _SB_GETVALUE(x, S_MC_tCwCr, M_MC_tCwCr)
+#define K_MC_tCwCr_DEFAULT       4
+#define V_MC_tCwCr_DEFAULT       V_MC_tCwCr(K_MC_tCwCr_DEFAULT)
+
+#define S_MC_tRCr                28
+#define M_MC_tRCr                _SB_MAKEMASK(4, S_MC_tRCr)
+#define V_MC_tRCr(x)             _SB_MAKEVALUE(x, S_MC_tRCr)
+#define G_MC_tRCr(x)             _SB_GETVALUE(x, S_MC_tRCr, M_MC_tRCr)
+#define K_MC_tRCr_DEFAULT        9
+#define V_MC_tRCr_DEFAULT        V_MC_tRCr(K_MC_tRCr_DEFAULT)
+
+#define S_MC_tRCw                24
+#define M_MC_tRCw                _SB_MAKEMASK(4, S_MC_tRCw)
+#define V_MC_tRCw(x)             _SB_MAKEVALUE(x, S_MC_tRCw)
+#define G_MC_tRCw(x)             _SB_GETVALUE(x, S_MC_tRCw, M_MC_tRCw)
+#define K_MC_tRCw_DEFAULT        10
+#define V_MC_tRCw_DEFAULT        V_MC_tRCw(K_MC_tRCw_DEFAULT)
+
+#define S_MC_tRRD                20
+#define M_MC_tRRD                _SB_MAKEMASK(4, S_MC_tRRD)
+#define V_MC_tRRD(x)             _SB_MAKEVALUE(x, S_MC_tRRD)
+#define G_MC_tRRD(x)             _SB_GETVALUE(x, S_MC_tRRD, M_MC_tRRD)
+#define K_MC_tRRD_DEFAULT        2
+#define V_MC_tRRD_DEFAULT        V_MC_tRRD(K_MC_tRRD_DEFAULT)
+
+#define S_MC_tRP                 16
+#define M_MC_tRP                 _SB_MAKEMASK(4, S_MC_tRP)
+#define V_MC_tRP(x)              _SB_MAKEVALUE(x, S_MC_tRP)
+#define G_MC_tRP(x)              _SB_GETVALUE(x, S_MC_tRP, M_MC_tRP)
+#define K_MC_tRP_DEFAULT         4
+#define V_MC_tRP_DEFAULT         V_MC_tRP(K_MC_tRP_DEFAULT)
+
+#define S_MC_tCwD                8
+#define M_MC_tCwD                _SB_MAKEMASK(4, S_MC_tCwD)
+#define V_MC_tCwD(x)             _SB_MAKEVALUE(x, S_MC_tCwD)
+#define G_MC_tCwD(x)             _SB_GETVALUE(x, S_MC_tCwD, M_MC_tCwD)
+#define K_MC_tCwD_DEFAULT        1
+#define V_MC_tCwD_DEFAULT        V_MC_tCwD(K_MC_tCwD_DEFAULT)
+
+#define M_tCrDh                          _SB_MAKEMASK1(7)

 #define M_MC_tCrDh               M_tCrDh
 
 #define M_MC_tCrDh               M_tCrDh
 

-#define S_MC_tCrD                 4
-#define M_MC_tCrD                 _SB_MAKEMASK(3, S_MC_tCrD)
-#define V_MC_tCrD(x)              _SB_MAKEVALUE(x, S_MC_tCrD)
-#define G_MC_tCrD(x)              _SB_GETVALUE(x, S_MC_tCrD, M_MC_tCrD)
-#define K_MC_tCrD_DEFAULT         2
-#define V_MC_tCrD_DEFAULT         V_MC_tCrD(K_MC_tCrD_DEFAULT)
-
-#define S_MC_tRCD                 0
-#define M_MC_tRCD                 _SB_MAKEMASK(4, S_MC_tRCD)
-#define V_MC_tRCD(x)              _SB_MAKEVALUE(x, S_MC_tRCD)
-#define G_MC_tRCD(x)              _SB_GETVALUE(x, S_MC_tRCD, M_MC_tRCD)
-#define K_MC_tRCD_DEFAULT         3
-#define V_MC_tRCD_DEFAULT         V_MC_tRCD(K_MC_tRCD_DEFAULT)
-
-#define V_MC_TIMING_DEFAULT     V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \
-                                V_MC_tRFC(K_MC_tRFC_DEFAULT) | \
-                                V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \
-                                V_MC_tRCr(K_MC_tRCr_DEFAULT) | \
-                                V_MC_tRCw(K_MC_tRCw_DEFAULT) | \
-                                V_MC_tRRD(K_MC_tRRD_DEFAULT) | \
-                                V_MC_tRP(K_MC_tRP_DEFAULT) | \
-                                V_MC_tCwD(K_MC_tCwD_DEFAULT) | \
-                                V_MC_tCrD(K_MC_tCrD_DEFAULT) | \
-                                V_MC_tRCD(K_MC_tRCD_DEFAULT) | \
-                                M_MC_r2rIDLE_TWOCYCLES
+#define S_MC_tCrD                4
+#define M_MC_tCrD                _SB_MAKEMASK(3, S_MC_tCrD)
+#define V_MC_tCrD(x)             _SB_MAKEVALUE(x, S_MC_tCrD)
+#define G_MC_tCrD(x)             _SB_GETVALUE(x, S_MC_tCrD, M_MC_tCrD)
+#define K_MC_tCrD_DEFAULT        2
+#define V_MC_tCrD_DEFAULT        V_MC_tCrD(K_MC_tCrD_DEFAULT)
+
+#define S_MC_tRCD                0
+#define M_MC_tRCD                _SB_MAKEMASK(4, S_MC_tRCD)
+#define V_MC_tRCD(x)             _SB_MAKEVALUE(x, S_MC_tRCD)
+#define G_MC_tRCD(x)             _SB_GETVALUE(x, S_MC_tRCD, M_MC_tRCD)
+#define K_MC_tRCD_DEFAULT        3
+#define V_MC_tRCD_DEFAULT        V_MC_tRCD(K_MC_tRCD_DEFAULT)
+
+#define V_MC_TIMING_DEFAULT    V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \
+                               V_MC_tRFC(K_MC_tRFC_DEFAULT) | \
+                               V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \
+                               V_MC_tRCr(K_MC_tRCr_DEFAULT) | \
+                               V_MC_tRCw(K_MC_tRCw_DEFAULT) | \
+                               V_MC_tRRD(K_MC_tRRD_DEFAULT) | \
+                               V_MC_tRP(K_MC_tRP_DEFAULT) | \
+                               V_MC_tCwD(K_MC_tCwD_DEFAULT) | \
+                               V_MC_tCrD(K_MC_tCrD_DEFAULT) | \
+                               V_MC_tRCD(K_MC_tRCD_DEFAULT) | \
+                               M_MC_r2rIDLE_TWOCYCLES

 
 /*
  * Errata says these are not the default
 
 /*
  * Errata says these are not the default

- *                               M_MC_w2rIDLE_TWOCYCLES | \
- *                               M_MC_r2wIDLE_TWOCYCLES | \
+ *                              M_MC_w2rIDLE_TWOCYCLES | \
+ *                              M_MC_r2wIDLE_TWOCYCLES | \

  */
 
 
  */
 
 


@@ -408,143 +408,143 @@
  * Chip Select Start Address Register (Table 6-17)
  */
 
  * Chip Select Start Address Register (Table 6-17)
  */
 

-#define S_MC_CS0_START              0
-#define M_MC_CS0_START              _SB_MAKEMASK(16, S_MC_CS0_START)
-#define V_MC_CS0_START(x)           _SB_MAKEVALUE(x, S_MC_CS0_START)
-#define G_MC_CS0_START(x)           _SB_GETVALUE(x, S_MC_CS0_START, M_MC_CS0_START)
+#define S_MC_CS0_START             0
+#define M_MC_CS0_START             _SB_MAKEMASK(16, S_MC_CS0_START)
+#define V_MC_CS0_START(x)          _SB_MAKEVALUE(x, S_MC_CS0_START)
+#define G_MC_CS0_START(x)          _SB_GETVALUE(x, S_MC_CS0_START, M_MC_CS0_START)

 
 

-#define S_MC_CS1_START              16
-#define M_MC_CS1_START              _SB_MAKEMASK(16, S_MC_CS1_START)
-#define V_MC_CS1_START(x)           _SB_MAKEVALUE(x, S_MC_CS1_START)
-#define G_MC_CS1_START(x)           _SB_GETVALUE(x, S_MC_CS1_START, M_MC_CS1_START)
+#define S_MC_CS1_START             16
+#define M_MC_CS1_START             _SB_MAKEMASK(16, S_MC_CS1_START)
+#define V_MC_CS1_START(x)          _SB_MAKEVALUE(x, S_MC_CS1_START)
+#define G_MC_CS1_START(x)          _SB_GETVALUE(x, S_MC_CS1_START, M_MC_CS1_START)

 
 

-#define S_MC_CS2_START              32
-#define M_MC_CS2_START              _SB_MAKEMASK(16, S_MC_CS2_START)
-#define V_MC_CS2_START(x)           _SB_MAKEVALUE(x, S_MC_CS2_START)
-#define G_MC_CS2_START(x)           _SB_GETVALUE(x, S_MC_CS2_START, M_MC_CS2_START)
+#define S_MC_CS2_START             32
+#define M_MC_CS2_START             _SB_MAKEMASK(16, S_MC_CS2_START)
+#define V_MC_CS2_START(x)          _SB_MAKEVALUE(x, S_MC_CS2_START)
+#define G_MC_CS2_START(x)          _SB_GETVALUE(x, S_MC_CS2_START, M_MC_CS2_START)

 
 

-#define S_MC_CS3_START              48
-#define M_MC_CS3_START              _SB_MAKEMASK(16, S_MC_CS3_START)
-#define V_MC_CS3_START(x)           _SB_MAKEVALUE(x, S_MC_CS3_START)
-#define G_MC_CS3_START(x)           _SB_GETVALUE(x, S_MC_CS3_START, M_MC_CS3_START)
+#define S_MC_CS3_START             48
+#define M_MC_CS3_START             _SB_MAKEMASK(16, S_MC_CS3_START)
+#define V_MC_CS3_START(x)          _SB_MAKEVALUE(x, S_MC_CS3_START)
+#define G_MC_CS3_START(x)          _SB_GETVALUE(x, S_MC_CS3_START, M_MC_CS3_START)

 
 /*
  * Chip Select End Address Register (Table 6-18)
  */
 
 
 /*
  * Chip Select End Address Register (Table 6-18)
  */
 

-#define S_MC_CS0_END                0
-#define M_MC_CS0_END                _SB_MAKEMASK(16, S_MC_CS0_END)
-#define V_MC_CS0_END(x)             _SB_MAKEVALUE(x, S_MC_CS0_END)
-#define G_MC_CS0_END(x)             _SB_GETVALUE(x, S_MC_CS0_END, M_MC_CS0_END)
+#define S_MC_CS0_END               0
+#define M_MC_CS0_END               _SB_MAKEMASK(16, S_MC_CS0_END)
+#define V_MC_CS0_END(x)                    _SB_MAKEVALUE(x, S_MC_CS0_END)
+#define G_MC_CS0_END(x)                    _SB_GETVALUE(x, S_MC_CS0_END, M_MC_CS0_END)

 
 

-#define S_MC_CS1_END                16
-#define M_MC_CS1_END                _SB_MAKEMASK(16, S_MC_CS1_END)
-#define V_MC_CS1_END(x)             _SB_MAKEVALUE(x, S_MC_CS1_END)
-#define G_MC_CS1_END(x)             _SB_GETVALUE(x, S_MC_CS1_END, M_MC_CS1_END)
+#define S_MC_CS1_END               16
+#define M_MC_CS1_END               _SB_MAKEMASK(16, S_MC_CS1_END)
+#define V_MC_CS1_END(x)                    _SB_MAKEVALUE(x, S_MC_CS1_END)
+#define G_MC_CS1_END(x)                    _SB_GETVALUE(x, S_MC_CS1_END, M_MC_CS1_END)

 
 

-#define S_MC_CS2_END                32
-#define M_MC_CS2_END                _SB_MAKEMASK(16, S_MC_CS2_END)
-#define V_MC_CS2_END(x)             _SB_MAKEVALUE(x, S_MC_CS2_END)
-#define G_MC_CS2_END(x)             _SB_GETVALUE(x, S_MC_CS2_END, M_MC_CS2_END)
+#define S_MC_CS2_END               32
+#define M_MC_CS2_END               _SB_MAKEMASK(16, S_MC_CS2_END)
+#define V_MC_CS2_END(x)                    _SB_MAKEVALUE(x, S_MC_CS2_END)
+#define G_MC_CS2_END(x)                    _SB_GETVALUE(x, S_MC_CS2_END, M_MC_CS2_END)

 
 

-#define S_MC_CS3_END                48
-#define M_MC_CS3_END                _SB_MAKEMASK(16, S_MC_CS3_END)
-#define V_MC_CS3_END(x)             _SB_MAKEVALUE(x, S_MC_CS3_END)
-#define G_MC_CS3_END(x)             _SB_GETVALUE(x, S_MC_CS3_END, M_MC_CS3_END)
+#define S_MC_CS3_END               48
+#define M_MC_CS3_END               _SB_MAKEMASK(16, S_MC_CS3_END)
+#define V_MC_CS3_END(x)                    _SB_MAKEVALUE(x, S_MC_CS3_END)
+#define G_MC_CS3_END(x)                    _SB_GETVALUE(x, S_MC_CS3_END, M_MC_CS3_END)

 
 /*
  * Chip Select Interleave Register (Table 6-19)
  */
 
 
 /*
  * Chip Select Interleave Register (Table 6-19)
  */
 

-#define S_MC_INTLV_RESERVED         0
-#define M_MC_INTLV_RESERVED         _SB_MAKEMASK(5, S_MC_INTLV_RESERVED)
+#define S_MC_INTLV_RESERVED        0
+#define M_MC_INTLV_RESERVED        _SB_MAKEMASK(5, S_MC_INTLV_RESERVED)

 
 

-#define S_MC_INTERLEAVE             7
-#define M_MC_INTERLEAVE             _SB_MAKEMASK(18, S_MC_INTERLEAVE)
-#define V_MC_INTERLEAVE(x)          _SB_MAKEVALUE(x, S_MC_INTERLEAVE)
+#define S_MC_INTERLEAVE                    7
+#define M_MC_INTERLEAVE                    _SB_MAKEMASK(18, S_MC_INTERLEAVE)
+#define V_MC_INTERLEAVE(x)         _SB_MAKEVALUE(x, S_MC_INTERLEAVE)

 
 

-#define S_MC_INTLV_MBZ              25
-#define M_MC_INTLV_MBZ              _SB_MAKEMASK(39, S_MC_INTLV_MBZ)
+#define S_MC_INTLV_MBZ             25
+#define M_MC_INTLV_MBZ             _SB_MAKEMASK(39, S_MC_INTLV_MBZ)

 
 /*
  * Row Address Bits Register (Table 6-20)
  */
 
 
 /*
  * Row Address Bits Register (Table 6-20)
  */
 

-#define S_MC_RAS_RESERVED           0
-#define M_MC_RAS_RESERVED           _SB_MAKEMASK(5, S_MC_RAS_RESERVED)
+#define S_MC_RAS_RESERVED          0
+#define M_MC_RAS_RESERVED          _SB_MAKEMASK(5, S_MC_RAS_RESERVED)

 
 

-#define S_MC_RAS_SELECT             12
-#define M_MC_RAS_SELECT             _SB_MAKEMASK(25, S_MC_RAS_SELECT)
-#define V_MC_RAS_SELECT(x)          _SB_MAKEVALUE(x, S_MC_RAS_SELECT)
+#define S_MC_RAS_SELECT                    12
+#define M_MC_RAS_SELECT                    _SB_MAKEMASK(25, S_MC_RAS_SELECT)
+#define V_MC_RAS_SELECT(x)         _SB_MAKEVALUE(x, S_MC_RAS_SELECT)

 
 

-#define S_MC_RAS_MBZ                37
-#define M_MC_RAS_MBZ                _SB_MAKEMASK(27, S_MC_RAS_MBZ)
+#define S_MC_RAS_MBZ               37
+#define M_MC_RAS_MBZ               _SB_MAKEMASK(27, S_MC_RAS_MBZ)

 
 
 /*
  * Column Address Bits Register (Table 6-21)
  */
 
 
 
 /*
  * Column Address Bits Register (Table 6-21)
  */
 

-#define S_MC_CAS_RESERVED           0
-#define M_MC_CAS_RESERVED           _SB_MAKEMASK(5, S_MC_CAS_RESERVED)
+#define S_MC_CAS_RESERVED          0
+#define M_MC_CAS_RESERVED          _SB_MAKEMASK(5, S_MC_CAS_RESERVED)

 
 

-#define S_MC_CAS_SELECT             5
-#define M_MC_CAS_SELECT             _SB_MAKEMASK(18, S_MC_CAS_SELECT)
-#define V_MC_CAS_SELECT(x)          _SB_MAKEVALUE(x, S_MC_CAS_SELECT)
+#define S_MC_CAS_SELECT                    5
+#define M_MC_CAS_SELECT                    _SB_MAKEMASK(18, S_MC_CAS_SELECT)
+#define V_MC_CAS_SELECT(x)         _SB_MAKEVALUE(x, S_MC_CAS_SELECT)

 
 

-#define S_MC_CAS_MBZ                23
-#define M_MC_CAS_MBZ                _SB_MAKEMASK(41, S_MC_CAS_MBZ)
+#define S_MC_CAS_MBZ               23
+#define M_MC_CAS_MBZ               _SB_MAKEMASK(41, S_MC_CAS_MBZ)

 
 
 /*
  * Bank Address Address Bits Register (Table 6-22)
  */
 
 
 
 /*
  * Bank Address Address Bits Register (Table 6-22)
  */
 

-#define S_MC_BA_RESERVED            0
-#define M_MC_BA_RESERVED            _SB_MAKEMASK(5, S_MC_BA_RESERVED)
+#define S_MC_BA_RESERVED           0
+#define M_MC_BA_RESERVED           _SB_MAKEMASK(5, S_MC_BA_RESERVED)

 
 

-#define S_MC_BA_SELECT              5
-#define M_MC_BA_SELECT              _SB_MAKEMASK(20, S_MC_BA_SELECT)
-#define V_MC_BA_SELECT(x)           _SB_MAKEVALUE(x, S_MC_BA_SELECT)
+#define S_MC_BA_SELECT             5
+#define M_MC_BA_SELECT             _SB_MAKEMASK(20, S_MC_BA_SELECT)
+#define V_MC_BA_SELECT(x)          _SB_MAKEVALUE(x, S_MC_BA_SELECT)

 
 

-#define S_MC_BA_MBZ                 25
-#define M_MC_BA_MBZ                 _SB_MAKEMASK(39, S_MC_BA_MBZ)
+#define S_MC_BA_MBZ                25
+#define M_MC_BA_MBZ                _SB_MAKEMASK(39, S_MC_BA_MBZ)

 
 /*
  * Chip Select Attribute Register (Table 6-23)
  */
 
 
 /*
  * Chip Select Attribute Register (Table 6-23)
  */
 

-#define K_MC_CS_ATTR_CLOSED         0
-#define K_MC_CS_ATTR_CASCHECK       1
-#define K_MC_CS_ATTR_HINT           2
-#define K_MC_CS_ATTR_OPEN           3
+#define K_MC_CS_ATTR_CLOSED        0
+#define K_MC_CS_ATTR_CASCHECK      1
+#define K_MC_CS_ATTR_HINT          2
+#define K_MC_CS_ATTR_OPEN          3

 
 

-#define S_MC_CS0_PAGE               0
-#define M_MC_CS0_PAGE               _SB_MAKEMASK(2, S_MC_CS0_PAGE)
-#define V_MC_CS0_PAGE(x)            _SB_MAKEVALUE(x, S_MC_CS0_PAGE)
-#define G_MC_CS0_PAGE(x)            _SB_GETVALUE(x, S_MC_CS0_PAGE, M_MC_CS0_PAGE)
+#define S_MC_CS0_PAGE              0
+#define M_MC_CS0_PAGE              _SB_MAKEMASK(2, S_MC_CS0_PAGE)
+#define V_MC_CS0_PAGE(x)           _SB_MAKEVALUE(x, S_MC_CS0_PAGE)
+#define G_MC_CS0_PAGE(x)           _SB_GETVALUE(x, S_MC_CS0_PAGE, M_MC_CS0_PAGE)

 
 

-#define S_MC_CS1_PAGE               16
-#define M_MC_CS1_PAGE               _SB_MAKEMASK(2, S_MC_CS1_PAGE)
-#define V_MC_CS1_PAGE(x)            _SB_MAKEVALUE(x, S_MC_CS1_PAGE)
-#define G_MC_CS1_PAGE(x)            _SB_GETVALUE(x, S_MC_CS1_PAGE, M_MC_CS1_PAGE)
+#define S_MC_CS1_PAGE              16
+#define M_MC_CS1_PAGE              _SB_MAKEMASK(2, S_MC_CS1_PAGE)
+#define V_MC_CS1_PAGE(x)           _SB_MAKEVALUE(x, S_MC_CS1_PAGE)
+#define G_MC_CS1_PAGE(x)           _SB_GETVALUE(x, S_MC_CS1_PAGE, M_MC_CS1_PAGE)

 
 

-#define S_MC_CS2_PAGE               32
-#define M_MC_CS2_PAGE               _SB_MAKEMASK(2, S_MC_CS2_PAGE)
-#define V_MC_CS2_PAGE(x)            _SB_MAKEVALUE(x, S_MC_CS2_PAGE)
-#define G_MC_CS2_PAGE(x)            _SB_GETVALUE(x, S_MC_CS2_PAGE, M_MC_CS2_PAGE)
+#define S_MC_CS2_PAGE              32
+#define M_MC_CS2_PAGE              _SB_MAKEMASK(2, S_MC_CS2_PAGE)
+#define V_MC_CS2_PAGE(x)           _SB_MAKEVALUE(x, S_MC_CS2_PAGE)
+#define G_MC_CS2_PAGE(x)           _SB_GETVALUE(x, S_MC_CS2_PAGE, M_MC_CS2_PAGE)

 
 

-#define S_MC_CS3_PAGE               48
-#define M_MC_CS3_PAGE               _SB_MAKEMASK(2, S_MC_CS3_PAGE)
-#define V_MC_CS3_PAGE(x)            _SB_MAKEVALUE(x, S_MC_CS3_PAGE)
-#define G_MC_CS3_PAGE(x)            _SB_GETVALUE(x, S_MC_CS3_PAGE, M_MC_CS3_PAGE)
+#define S_MC_CS3_PAGE              48
+#define M_MC_CS3_PAGE              _SB_MAKEMASK(2, S_MC_CS3_PAGE)
+#define V_MC_CS3_PAGE(x)           _SB_MAKEVALUE(x, S_MC_CS3_PAGE)
+#define G_MC_CS3_PAGE(x)           _SB_GETVALUE(x, S_MC_CS3_PAGE, M_MC_CS3_PAGE)

 
 /*
  * ECC Test ECC Register (Table 6-25)
  */
 
 
 /*
  * ECC Test ECC Register (Table 6-25)
  */
 

-#define S_MC_ECC_INVERT             0
-#define M_MC_ECC_INVERT             _SB_MAKEMASK(8, S_MC_ECC_INVERT)
+#define S_MC_ECC_INVERT                    0
+#define M_MC_ECC_INVERT                    _SB_MAKEMASK(8, S_MC_ECC_INVERT)

 
 
 #endif
 
 
 #endif

diff --git a/arch/mips/include/asm/sibyte/sb1250_regs.h b/arch/mips/include/asm/sibyte/sb1250_regs.h
index 29b9f0b26b3abfa26e0c2c7ce26911e6e35ba011..ee86ca0fad32855984293b11e6ad403f70136368 100644 (file)
--- a/arch/mips/include/asm/sibyte/sb1250_regs.h
+++ b/arch/mips/include/asm/sibyte/sb1250_regs.h
@@ -1,7 +1,7 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
     *
 /*  *********************************************************************
     *  SB1250 Board Support Package
     *

-    *  Register Definitions                     File: sb1250_regs.h
+    *  Register Definitions                    File: sb1250_regs.h

     *
     *  This module contains the addresses of the on-chip peripherals
     *  on the SB1250.
     *
     *  This module contains the addresses of the on-chip peripherals
     *  on the SB1250.


@@ -61,45 +61,45 @@
  */
 
 #if SIBYTE_HDR_FEATURE_1250_112x               /* This MC only on 1250 & 112x */
  */
 
 #if SIBYTE_HDR_FEATURE_1250_112x               /* This MC only on 1250 & 112x */

-#define A_MC_BASE_0                 0x0010051000
-#define A_MC_BASE_1                 0x0010052000
-#define MC_REGISTER_SPACING         0x1000
+#define A_MC_BASE_0                0x0010051000
+#define A_MC_BASE_1                0x0010052000
+#define MC_REGISTER_SPACING        0x1000

 
 

-#define A_MC_BASE(ctlid)            ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0)
+#define A_MC_BASE(ctlid)           ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0)

 #define A_MC_REGISTER(ctlid, reg)    (A_MC_BASE(ctlid)+(reg))
 
 #define A_MC_REGISTER(ctlid, reg)    (A_MC_BASE(ctlid)+(reg))
 

-#define R_MC_CONFIG                 0x0000000100
-#define R_MC_DRAMCMD                0x0000000120
-#define R_MC_DRAMMODE               0x0000000140
-#define R_MC_TIMING1                0x0000000160
-#define R_MC_TIMING2                0x0000000180
-#define R_MC_CS_START               0x00000001A0
-#define R_MC_CS_END                 0x00000001C0
-#define R_MC_CS_INTERLEAVE          0x00000001E0
-#define S_MC_CS_STARTEND            16
-
-#define R_MC_CSX_BASE               0x0000000200
-#define R_MC_CSX_ROW                0x0000000000       /* relative to CSX_BASE, above */
-#define R_MC_CSX_COL                0x0000000020       /* relative to CSX_BASE, above */
-#define R_MC_CSX_BA                 0x0000000040       /* relative to CSX_BASE, above */
-#define MC_CSX_SPACING              0x0000000060       /* relative to CSX_BASE, above */
-
-#define R_MC_CS0_ROW                0x0000000200
-#define R_MC_CS0_COL                0x0000000220
-#define R_MC_CS0_BA                 0x0000000240
-#define R_MC_CS1_ROW                0x0000000260
-#define R_MC_CS1_COL                0x0000000280
-#define R_MC_CS1_BA                 0x00000002A0
-#define R_MC_CS2_ROW                0x00000002C0
-#define R_MC_CS2_COL                0x00000002E0
-#define R_MC_CS2_BA                 0x0000000300
-#define R_MC_CS3_ROW                0x0000000320
-#define R_MC_CS3_COL                0x0000000340
-#define R_MC_CS3_BA                 0x0000000360
-#define R_MC_CS_ATTR                0x0000000380
-#define R_MC_TEST_DATA              0x0000000400
-#define R_MC_TEST_ECC               0x0000000420
-#define R_MC_MCLK_CFG               0x0000000500
+#define R_MC_CONFIG                0x0000000100
+#define R_MC_DRAMCMD               0x0000000120
+#define R_MC_DRAMMODE              0x0000000140
+#define R_MC_TIMING1               0x0000000160
+#define R_MC_TIMING2               0x0000000180
+#define R_MC_CS_START              0x00000001A0
+#define R_MC_CS_END                0x00000001C0
+#define R_MC_CS_INTERLEAVE         0x00000001E0
+#define S_MC_CS_STARTEND           16
+
+#define R_MC_CSX_BASE              0x0000000200
+#define R_MC_CSX_ROW               0x0000000000        /* relative to CSX_BASE, above */
+#define R_MC_CSX_COL               0x0000000020        /* relative to CSX_BASE, above */
+#define R_MC_CSX_BA                0x0000000040        /* relative to CSX_BASE, above */
+#define MC_CSX_SPACING             0x0000000060        /* relative to CSX_BASE, above */
+
+#define R_MC_CS0_ROW               0x0000000200
+#define R_MC_CS0_COL               0x0000000220
+#define R_MC_CS0_BA                0x0000000240
+#define R_MC_CS1_ROW               0x0000000260
+#define R_MC_CS1_COL               0x0000000280
+#define R_MC_CS1_BA                0x00000002A0
+#define R_MC_CS2_ROW               0x00000002C0
+#define R_MC_CS2_COL               0x00000002E0
+#define R_MC_CS2_BA                0x0000000300
+#define R_MC_CS3_ROW               0x0000000320
+#define R_MC_CS3_COL               0x0000000340
+#define R_MC_CS3_BA                0x0000000360
+#define R_MC_CS_ATTR               0x0000000380
+#define R_MC_TEST_DATA             0x0000000400
+#define R_MC_TEST_ECC              0x0000000420
+#define R_MC_MCLK_CFG              0x0000000500

 
 #endif /* 1250 & 112x */
 
 
 #endif /* 1250 & 112x */
 


@@ -109,14 +109,14 @@
 
 #if SIBYTE_HDR_FEATURE_1250_112x       /* This L2C only on 1250/112x */
 
 
 #if SIBYTE_HDR_FEATURE_1250_112x       /* This L2C only on 1250/112x */
 

-#define A_L2_READ_TAG               0x0010040018
-#define A_L2_ECC_TAG                0x0010040038
+#define A_L2_READ_TAG              0x0010040018
+#define A_L2_ECC_TAG               0x0010040038

 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)

-#define A_L2_READ_MISC              0x0010040058
+#define A_L2_READ_MISC             0x0010040058

 #endif /* 1250 PASS3 || 112x PASS1 */
 #endif /* 1250 PASS3 || 112x PASS1 */

-#define A_L2_WAY_DISABLE            0x0010041000
-#define A_L2_MAKEDISABLE(x)         (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8))
-#define A_L2_MGMT_TAG_BASE          0x00D0000000
+#define A_L2_WAY_DISABLE           0x0010041000
+#define A_L2_MAKEDISABLE(x)        (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8))
+#define A_L2_MGMT_TAG_BASE         0x00D0000000

 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define A_L2_CACHE_DISABLE        0x0010042000
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define A_L2_CACHE_DISABLE        0x0010042000


@@ -124,10 +124,10 @@
 #define A_L2_MISC_CONFIG          0x0010043000
 #endif /* 1250 PASS2 || 112x PASS1 */
 
 #define A_L2_MISC_CONFIG          0x0010043000
 #endif /* 1250 PASS2 || 112x PASS1 */
 

-/* Backward-compatibility definitions.  */
+/* Backward-compatibility definitions. */

 /* XXX: discourage people from using these constants.  */
 /* XXX: discourage people from using these constants.  */

-#define A_L2_READ_ADDRESS           A_L2_READ_TAG
-#define A_L2_EEC_ADDRESS            A_L2_ECC_TAG
+#define A_L2_READ_ADDRESS          A_L2_READ_TAG
+#define A_L2_EEC_ADDRESS           A_L2_ECC_TAG

 
 #endif
 
 
 #endif
 


@@ -137,8 +137,8 @@
     ********************************************************************* */
 
 #if SIBYTE_HDR_FEATURE_1250_112x       /* This PCI/HT only on 1250/112x */
     ********************************************************************* */
 
 #if SIBYTE_HDR_FEATURE_1250_112x       /* This PCI/HT only on 1250/112x */

-#define A_PCI_TYPE00_HEADER         0x00DE000000
-#define A_PCI_TYPE01_HEADER         0x00DE000800
+#define A_PCI_TYPE00_HEADER        0x00DE000000
+#define A_PCI_TYPE01_HEADER        0x00DE000800

 #endif
 
 
 #endif
 
 


@@ -146,121 +146,121 @@
     * Ethernet DMA and MACs
     ********************************************************************* */
 
     * Ethernet DMA and MACs
     ********************************************************************* */
 

-#define A_MAC_BASE_0                0x0010064000
-#define A_MAC_BASE_1                0x0010065000
+#define A_MAC_BASE_0               0x0010064000
+#define A_MAC_BASE_1               0x0010065000

 #if SIBYTE_HDR_FEATURE_CHIP(1250)
 #if SIBYTE_HDR_FEATURE_CHIP(1250)

-#define A_MAC_BASE_2                0x0010066000
+#define A_MAC_BASE_2               0x0010066000

 #endif /* 1250 */
 
 #endif /* 1250 */
 

-#define MAC_SPACING                 0x1000
-#define MAC_DMA_TXRX_SPACING        0x0400
-#define MAC_DMA_CHANNEL_SPACING     0x0100
-#define DMA_RX                      0
-#define DMA_TX                      1
+#define MAC_SPACING                0x1000
+#define MAC_DMA_TXRX_SPACING       0x0400
+#define MAC_DMA_CHANNEL_SPACING            0x0100
+#define DMA_RX                     0
+#define DMA_TX                     1

 #define MAC_NUM_DMACHAN                    2               /* channels per direction */
 
 /* XXX: not correct; depends on SOC type.  */
 #define MAC_NUM_DMACHAN                    2               /* channels per direction */
 
 /* XXX: not correct; depends on SOC type.  */

-#define MAC_NUM_PORTS               3
+#define MAC_NUM_PORTS              3

 
 

-#define A_MAC_CHANNEL_BASE(macnum)                  \
-            (A_MAC_BASE_0 +                         \
-             MAC_SPACING*(macnum))
+#define A_MAC_CHANNEL_BASE(macnum)                 \
+           (A_MAC_BASE_0 +                         \
+            MAC_SPACING*(macnum))

 
 

-#define A_MAC_REGISTER(macnum,reg)                  \
-            (A_MAC_BASE_0 +                         \
-             MAC_SPACING*(macnum) + (reg))
+#define A_MAC_REGISTER(macnum,reg)                 \
+           (A_MAC_BASE_0 +                         \
+            MAC_SPACING*(macnum) + (reg))

 
 
 #define R_MAC_DMA_CHANNELS             0x800 /* Relative to A_MAC_CHANNEL_BASE */
 
 #define A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan)  \
 
 
 #define R_MAC_DMA_CHANNELS             0x800 /* Relative to A_MAC_CHANNEL_BASE */
 
 #define A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan)  \

-             ((A_MAC_CHANNEL_BASE(macnum)) +        \
-             R_MAC_DMA_CHANNELS +                   \
-             (MAC_DMA_TXRX_SPACING*(txrx)) +        \
-             (MAC_DMA_CHANNEL_SPACING*(chan)))
+            ((A_MAC_CHANNEL_BASE(macnum)) +        \
+            R_MAC_DMA_CHANNELS +                   \
+            (MAC_DMA_TXRX_SPACING*(txrx)) +        \
+            (MAC_DMA_CHANNEL_SPACING*(chan)))

 
 #define R_MAC_DMA_CHANNEL_BASE(txrx, chan)             \
 
 #define R_MAC_DMA_CHANNEL_BASE(txrx, chan)             \

-             (R_MAC_DMA_CHANNELS +                   \
-             (MAC_DMA_TXRX_SPACING*(txrx)) +        \
-             (MAC_DMA_CHANNEL_SPACING*(chan)))
+            (R_MAC_DMA_CHANNELS +                   \
+            (MAC_DMA_TXRX_SPACING*(txrx)) +        \
+            (MAC_DMA_CHANNEL_SPACING*(chan)))

 
 

-#define A_MAC_DMA_REGISTER(macnum, txrx, chan, reg)           \
-            (A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) +    \
-            (reg))
+#define A_MAC_DMA_REGISTER(macnum, txrx, chan, reg)          \
+           (A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) +    \
+           (reg))

 
 

-#define R_MAC_DMA_REGISTER(txrx, chan, reg)           \
-            (R_MAC_DMA_CHANNEL_BASE(txrx, chan) +    \
-            (reg))
+#define R_MAC_DMA_REGISTER(txrx, chan, reg)          \
+           (R_MAC_DMA_CHANNEL_BASE(txrx, chan) +    \
+           (reg))

 
 /*
  * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE
  */
 
 
 /*
  * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE
  */
 

-#define R_MAC_DMA_CONFIG0               0x00000000
-#define R_MAC_DMA_CONFIG1               0x00000008
-#define R_MAC_DMA_DSCR_BASE             0x00000010
-#define R_MAC_DMA_DSCR_CNT              0x00000018
-#define R_MAC_DMA_CUR_DSCRA             0x00000020
-#define R_MAC_DMA_CUR_DSCRB             0x00000028
-#define R_MAC_DMA_CUR_DSCRADDR          0x00000030
+#define R_MAC_DMA_CONFIG0              0x00000000
+#define R_MAC_DMA_CONFIG1              0x00000008
+#define R_MAC_DMA_DSCR_BASE            0x00000010
+#define R_MAC_DMA_DSCR_CNT             0x00000018
+#define R_MAC_DMA_CUR_DSCRA            0x00000020
+#define R_MAC_DMA_CUR_DSCRB            0x00000028
+#define R_MAC_DMA_CUR_DSCRADDR         0x00000030

 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)

-#define R_MAC_DMA_OODPKTLOST_RX         0x00000038     /* rx only */
+#define R_MAC_DMA_OODPKTLOST_RX                0x00000038      /* rx only */

 #endif /* 1250 PASS3 || 112x PASS1 */
 
 /*
  * RMON Counters
  */
 
 #endif /* 1250 PASS3 || 112x PASS1 */
 
 /*
  * RMON Counters
  */
 

-#define R_MAC_RMON_TX_BYTES             0x00000000
-#define R_MAC_RMON_COLLISIONS           0x00000008
-#define R_MAC_RMON_LATE_COL             0x00000010
-#define R_MAC_RMON_EX_COL               0x00000018
-#define R_MAC_RMON_FCS_ERROR            0x00000020
-#define R_MAC_RMON_TX_ABORT             0x00000028
+#define R_MAC_RMON_TX_BYTES            0x00000000
+#define R_MAC_RMON_COLLISIONS          0x00000008
+#define R_MAC_RMON_LATE_COL            0x00000010
+#define R_MAC_RMON_EX_COL              0x00000018
+#define R_MAC_RMON_FCS_ERROR           0x00000020
+#define R_MAC_RMON_TX_ABORT            0x00000028

 /* Counter #6 (0x30) now reserved */
 /* Counter #6 (0x30) now reserved */

-#define R_MAC_RMON_TX_BAD               0x00000038
-#define R_MAC_RMON_TX_GOOD              0x00000040
-#define R_MAC_RMON_TX_RUNT              0x00000048
-#define R_MAC_RMON_TX_OVERSIZE          0x00000050
-#define R_MAC_RMON_RX_BYTES             0x00000080
-#define R_MAC_RMON_RX_MCAST             0x00000088
-#define R_MAC_RMON_RX_BCAST             0x00000090
-#define R_MAC_RMON_RX_BAD               0x00000098
-#define R_MAC_RMON_RX_GOOD              0x000000A0
-#define R_MAC_RMON_RX_RUNT              0x000000A8
-#define R_MAC_RMON_RX_OVERSIZE          0x000000B0
-#define R_MAC_RMON_RX_FCS_ERROR         0x000000B8
-#define R_MAC_RMON_RX_LENGTH_ERROR      0x000000C0
-#define R_MAC_RMON_RX_CODE_ERROR        0x000000C8
-#define R_MAC_RMON_RX_ALIGN_ERROR       0x000000D0
+#define R_MAC_RMON_TX_BAD              0x00000038
+#define R_MAC_RMON_TX_GOOD             0x00000040
+#define R_MAC_RMON_TX_RUNT             0x00000048
+#define R_MAC_RMON_TX_OVERSIZE         0x00000050
+#define R_MAC_RMON_RX_BYTES            0x00000080
+#define R_MAC_RMON_RX_MCAST            0x00000088
+#define R_MAC_RMON_RX_BCAST            0x00000090
+#define R_MAC_RMON_RX_BAD              0x00000098
+#define R_MAC_RMON_RX_GOOD             0x000000A0
+#define R_MAC_RMON_RX_RUNT             0x000000A8
+#define R_MAC_RMON_RX_OVERSIZE         0x000000B0
+#define R_MAC_RMON_RX_FCS_ERROR                0x000000B8
+#define R_MAC_RMON_RX_LENGTH_ERROR     0x000000C0
+#define R_MAC_RMON_RX_CODE_ERROR       0x000000C8
+#define R_MAC_RMON_RX_ALIGN_ERROR      0x000000D0

 
 /* Updated to spec 0.2 */
 
 /* Updated to spec 0.2 */

-#define R_MAC_CFG                       0x00000100
-#define R_MAC_THRSH_CFG                 0x00000108
-#define R_MAC_VLANTAG                   0x00000110
-#define R_MAC_FRAMECFG                  0x00000118
-#define R_MAC_EOPCNT                    0x00000120
-#define R_MAC_FIFO_PTRS                 0x00000128
-#define R_MAC_ADFILTER_CFG              0x00000200
-#define R_MAC_ETHERNET_ADDR             0x00000208
-#define R_MAC_PKT_TYPE                  0x00000210
+#define R_MAC_CFG                      0x00000100
+#define R_MAC_THRSH_CFG                        0x00000108
+#define R_MAC_VLANTAG                  0x00000110
+#define R_MAC_FRAMECFG                 0x00000118
+#define R_MAC_EOPCNT                   0x00000120
+#define R_MAC_FIFO_PTRS                        0x00000128
+#define R_MAC_ADFILTER_CFG             0x00000200
+#define R_MAC_ETHERNET_ADDR            0x00000208
+#define R_MAC_PKT_TYPE                 0x00000210

 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define R_MAC_ADMASK0                  0x00000218
 #define R_MAC_ADMASK1                  0x00000220
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define R_MAC_ADMASK0                  0x00000218
 #define R_MAC_ADMASK1                  0x00000220
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */

-#define R_MAC_HASH_BASE                 0x00000240
-#define R_MAC_ADDR_BASE                 0x00000280
-#define R_MAC_CHLO0_BASE                0x00000300
-#define R_MAC_CHUP0_BASE                0x00000320
-#define R_MAC_ENABLE                    0x00000400
-#define R_MAC_STATUS                    0x00000408
-#define R_MAC_INT_MASK                  0x00000410
-#define R_MAC_TXD_CTL                   0x00000420
-#define R_MAC_MDIO                      0x00000428
+#define R_MAC_HASH_BASE                        0x00000240
+#define R_MAC_ADDR_BASE                        0x00000280
+#define R_MAC_CHLO0_BASE               0x00000300
+#define R_MAC_CHUP0_BASE               0x00000320
+#define R_MAC_ENABLE                   0x00000400
+#define R_MAC_STATUS                   0x00000408
+#define R_MAC_INT_MASK                 0x00000410
+#define R_MAC_TXD_CTL                  0x00000420
+#define R_MAC_MDIO                     0x00000428

 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)

-#define R_MAC_STATUS1                  0x00000430
+#define R_MAC_STATUS1                  0x00000430

 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */

-#define R_MAC_DEBUG_STATUS              0x00000448
+#define R_MAC_DEBUG_STATUS             0x00000448

 
 #define MAC_HASH_COUNT                 8
 #define MAC_ADDR_COUNT                 8
 
 #define MAC_HASH_COUNT                 8
 #define MAC_ADDR_COUNT                 8


@@ -273,11 +273,11 @@
 
 
 #if SIBYTE_HDR_FEATURE_1250_112x    /* This MC only on 1250 & 112x */
 
 
 #if SIBYTE_HDR_FEATURE_1250_112x    /* This MC only on 1250 & 112x */

-#define R_DUART_NUM_PORTS           2
+#define R_DUART_NUM_PORTS          2

 
 

-#define A_DUART                     0x0010060000
+#define A_DUART                            0x0010060000

 
 

-#define DUART_CHANREG_SPACING       0x100
+#define DUART_CHANREG_SPACING      0x100

 
 #define A_DUART_CHANREG(chan, reg)                                     \
        (A_DUART + DUART_CHANREG_SPACING * ((chan) + 1) + (reg))
 
 #define A_DUART_CHANREG(chan, reg)                                     \
        (A_DUART + DUART_CHANREG_SPACING * ((chan) + 1) + (reg))


@@ -341,44 +341,44 @@
  * These constants are the absolute addresses.
  */
 
  * These constants are the absolute addresses.
  */
 

-#define A_DUART_MODE_REG_1_A        0x0010060100
-#define A_DUART_MODE_REG_2_A        0x0010060110
-#define A_DUART_STATUS_A            0x0010060120
-#define A_DUART_CLK_SEL_A           0x0010060130
-#define A_DUART_CMD_A               0x0010060150
-#define A_DUART_RX_HOLD_A           0x0010060160
-#define A_DUART_TX_HOLD_A           0x0010060170
-
-#define A_DUART_MODE_REG_1_B        0x0010060200
-#define A_DUART_MODE_REG_2_B        0x0010060210
-#define A_DUART_STATUS_B            0x0010060220
-#define A_DUART_CLK_SEL_B           0x0010060230
-#define A_DUART_CMD_B               0x0010060250
-#define A_DUART_RX_HOLD_B           0x0010060260
-#define A_DUART_TX_HOLD_B           0x0010060270
-
-#define A_DUART_INPORT_CHNG         0x0010060300
-#define A_DUART_AUX_CTRL            0x0010060310
-#define A_DUART_ISR_A               0x0010060320
-#define A_DUART_IMR_A               0x0010060330
-#define A_DUART_ISR_B               0x0010060340
-#define A_DUART_IMR_B               0x0010060350
-#define A_DUART_OUT_PORT            0x0010060360
-#define A_DUART_OPCR                0x0010060370
-#define A_DUART_IN_PORT             0x0010060380
-#define A_DUART_ISR                 0x0010060390
-#define A_DUART_IMR                 0x00100603A0
-#define A_DUART_SET_OPR             0x00100603B0
-#define A_DUART_CLEAR_OPR           0x00100603C0
-#define A_DUART_INPORT_CHNG_A       0x00100603D0
-#define A_DUART_INPORT_CHNG_B       0x00100603E0
+#define A_DUART_MODE_REG_1_A       0x0010060100
+#define A_DUART_MODE_REG_2_A       0x0010060110
+#define A_DUART_STATUS_A           0x0010060120
+#define A_DUART_CLK_SEL_A          0x0010060130
+#define A_DUART_CMD_A              0x0010060150
+#define A_DUART_RX_HOLD_A          0x0010060160
+#define A_DUART_TX_HOLD_A          0x0010060170
+
+#define A_DUART_MODE_REG_1_B       0x0010060200
+#define A_DUART_MODE_REG_2_B       0x0010060210
+#define A_DUART_STATUS_B           0x0010060220
+#define A_DUART_CLK_SEL_B          0x0010060230
+#define A_DUART_CMD_B              0x0010060250
+#define A_DUART_RX_HOLD_B          0x0010060260
+#define A_DUART_TX_HOLD_B          0x0010060270
+
+#define A_DUART_INPORT_CHNG        0x0010060300
+#define A_DUART_AUX_CTRL           0x0010060310
+#define A_DUART_ISR_A              0x0010060320
+#define A_DUART_IMR_A              0x0010060330
+#define A_DUART_ISR_B              0x0010060340
+#define A_DUART_IMR_B              0x0010060350
+#define A_DUART_OUT_PORT           0x0010060360
+#define A_DUART_OPCR               0x0010060370
+#define A_DUART_IN_PORT                    0x0010060380
+#define A_DUART_ISR                0x0010060390
+#define A_DUART_IMR                0x00100603A0
+#define A_DUART_SET_OPR                    0x00100603B0
+#define A_DUART_CLEAR_OPR          0x00100603C0
+#define A_DUART_INPORT_CHNG_A      0x00100603D0
+#define A_DUART_INPORT_CHNG_B      0x00100603E0

 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define A_DUART_FULL_CTL_A         0x0010060140
 #define A_DUART_FULL_CTL_B         0x0010060240
 
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define A_DUART_FULL_CTL_A         0x0010060140
 #define A_DUART_FULL_CTL_B         0x0010060240
 

-#define A_DUART_OPCR_A             0x0010060180
-#define A_DUART_OPCR_B             0x0010060280
+#define A_DUART_OPCR_A             0x0010060180
+#define A_DUART_OPCR_B             0x0010060280

 
 #define A_DUART_INPORT_CHNG_DEBUG   0x00100603F0
 #endif /* 1250 PASS2 || 112x PASS1 */
 
 #define A_DUART_INPORT_CHNG_DEBUG   0x00100603F0
 #endif /* 1250 PASS2 || 112x PASS1 */


@@ -391,94 +391,94 @@
 
 #if SIBYTE_HDR_FEATURE_1250_112x       /* sync serial only on 1250/112x */
 
 
 #if SIBYTE_HDR_FEATURE_1250_112x       /* sync serial only on 1250/112x */
 

-#define A_SER_BASE_0                0x0010060400
-#define A_SER_BASE_1                0x0010060800
-#define SER_SPACING                 0x400
+#define A_SER_BASE_0               0x0010060400
+#define A_SER_BASE_1               0x0010060800
+#define SER_SPACING                0x400

 
 

-#define SER_DMA_TXRX_SPACING        0x80
+#define SER_DMA_TXRX_SPACING       0x80

 
 

-#define SER_NUM_PORTS               2
+#define SER_NUM_PORTS              2

 
 

-#define A_SER_CHANNEL_BASE(sernum)                  \
-            (A_SER_BASE_0 +                         \
-             SER_SPACING*(sernum))
+#define A_SER_CHANNEL_BASE(sernum)                 \
+           (A_SER_BASE_0 +                         \
+            SER_SPACING*(sernum))

 
 

-#define A_SER_REGISTER(sernum,reg)                  \
-            (A_SER_BASE_0 +                         \
-             SER_SPACING*(sernum) + (reg))
+#define A_SER_REGISTER(sernum,reg)                 \
+           (A_SER_BASE_0 +                         \
+            SER_SPACING*(sernum) + (reg))

 
 
 #define R_SER_DMA_CHANNELS             0   /* Relative to A_SER_BASE_x */
 
 #define A_SER_DMA_CHANNEL_BASE(sernum,txrx)    \
 
 
 #define R_SER_DMA_CHANNELS             0   /* Relative to A_SER_BASE_x */
 
 #define A_SER_DMA_CHANNEL_BASE(sernum,txrx)    \

-             ((A_SER_CHANNEL_BASE(sernum)) +        \
-             R_SER_DMA_CHANNELS +                   \
-             (SER_DMA_TXRX_SPACING*(txrx)))
+            ((A_SER_CHANNEL_BASE(sernum)) +        \
+            R_SER_DMA_CHANNELS +                   \
+            (SER_DMA_TXRX_SPACING*(txrx)))

 
 

-#define A_SER_DMA_REGISTER(sernum, txrx, reg)           \
-            (A_SER_DMA_CHANNEL_BASE(sernum, txrx) +    \
-            (reg))
+#define A_SER_DMA_REGISTER(sernum, txrx, reg)          \
+           (A_SER_DMA_CHANNEL_BASE(sernum, txrx) +    \
+           (reg))

 
 
 /*
  * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE
  */
 
 
 
 /*
  * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE
  */
 

-#define R_SER_DMA_CONFIG0           0x00000000
-#define R_SER_DMA_CONFIG1           0x00000008
-#define R_SER_DMA_DSCR_BASE         0x00000010
-#define R_SER_DMA_DSCR_CNT          0x00000018
-#define R_SER_DMA_CUR_DSCRA         0x00000020
-#define R_SER_DMA_CUR_DSCRB         0x00000028
-#define R_SER_DMA_CUR_DSCRADDR      0x00000030
-
-#define R_SER_DMA_CONFIG0_RX        0x00000000
-#define R_SER_DMA_CONFIG1_RX        0x00000008
-#define R_SER_DMA_DSCR_BASE_RX      0x00000010
-#define R_SER_DMA_DSCR_COUNT_RX     0x00000018
-#define R_SER_DMA_CUR_DSCR_A_RX     0x00000020
-#define R_SER_DMA_CUR_DSCR_B_RX     0x00000028
+#define R_SER_DMA_CONFIG0          0x00000000
+#define R_SER_DMA_CONFIG1          0x00000008
+#define R_SER_DMA_DSCR_BASE        0x00000010
+#define R_SER_DMA_DSCR_CNT         0x00000018
+#define R_SER_DMA_CUR_DSCRA        0x00000020
+#define R_SER_DMA_CUR_DSCRB        0x00000028
+#define R_SER_DMA_CUR_DSCRADDR     0x00000030
+
+#define R_SER_DMA_CONFIG0_RX       0x00000000
+#define R_SER_DMA_CONFIG1_RX       0x00000008
+#define R_SER_DMA_DSCR_BASE_RX     0x00000010
+#define R_SER_DMA_DSCR_COUNT_RX            0x00000018
+#define R_SER_DMA_CUR_DSCR_A_RX            0x00000020
+#define R_SER_DMA_CUR_DSCR_B_RX            0x00000028

 #define R_SER_DMA_CUR_DSCR_ADDR_RX  0x00000030
 
 #define R_SER_DMA_CUR_DSCR_ADDR_RX  0x00000030
 

-#define R_SER_DMA_CONFIG0_TX        0x00000080
-#define R_SER_DMA_CONFIG1_TX        0x00000088
-#define R_SER_DMA_DSCR_BASE_TX      0x00000090
-#define R_SER_DMA_DSCR_COUNT_TX     0x00000098
-#define R_SER_DMA_CUR_DSCR_A_TX     0x000000A0
-#define R_SER_DMA_CUR_DSCR_B_TX     0x000000A8
+#define R_SER_DMA_CONFIG0_TX       0x00000080
+#define R_SER_DMA_CONFIG1_TX       0x00000088
+#define R_SER_DMA_DSCR_BASE_TX     0x00000090
+#define R_SER_DMA_DSCR_COUNT_TX            0x00000098
+#define R_SER_DMA_CUR_DSCR_A_TX            0x000000A0
+#define R_SER_DMA_CUR_DSCR_B_TX            0x000000A8

 #define R_SER_DMA_CUR_DSCR_ADDR_TX  0x000000B0
 
 #define R_SER_DMA_CUR_DSCR_ADDR_TX  0x000000B0
 

-#define R_SER_MODE                  0x00000100
-#define R_SER_MINFRM_SZ             0x00000108
-#define R_SER_MAXFRM_SZ             0x00000110
-#define R_SER_ADDR                  0x00000118
-#define R_SER_USR0_ADDR             0x00000120
-#define R_SER_USR1_ADDR             0x00000128
-#define R_SER_USR2_ADDR             0x00000130
-#define R_SER_USR3_ADDR             0x00000138
-#define R_SER_CMD                   0x00000140
-#define R_SER_TX_RD_THRSH           0x00000160
-#define R_SER_TX_WR_THRSH           0x00000168
-#define R_SER_RX_RD_THRSH           0x00000170
+#define R_SER_MODE                 0x00000100
+#define R_SER_MINFRM_SZ                    0x00000108
+#define R_SER_MAXFRM_SZ                    0x00000110
+#define R_SER_ADDR                 0x00000118
+#define R_SER_USR0_ADDR                    0x00000120
+#define R_SER_USR1_ADDR                    0x00000128
+#define R_SER_USR2_ADDR                    0x00000130
+#define R_SER_USR3_ADDR                    0x00000138
+#define R_SER_CMD                  0x00000140
+#define R_SER_TX_RD_THRSH          0x00000160
+#define R_SER_TX_WR_THRSH          0x00000168
+#define R_SER_RX_RD_THRSH          0x00000170

 #define R_SER_LINE_MODE                    0x00000178
 #define R_SER_LINE_MODE                    0x00000178

-#define R_SER_DMA_ENABLE            0x00000180
-#define R_SER_INT_MASK              0x00000190
-#define R_SER_STATUS                0x00000188
-#define R_SER_STATUS_DEBUG          0x000001A8
-#define R_SER_RX_TABLE_BASE         0x00000200
-#define SER_RX_TABLE_COUNT          16
-#define R_SER_TX_TABLE_BASE         0x00000300
-#define SER_TX_TABLE_COUNT          16
+#define R_SER_DMA_ENABLE           0x00000180
+#define R_SER_INT_MASK             0x00000190
+#define R_SER_STATUS               0x00000188
+#define R_SER_STATUS_DEBUG         0x000001A8
+#define R_SER_RX_TABLE_BASE        0x00000200
+#define SER_RX_TABLE_COUNT         16
+#define R_SER_TX_TABLE_BASE        0x00000300
+#define SER_TX_TABLE_COUNT         16

 
 /* RMON Counters */
 
 /* RMON Counters */

-#define R_SER_RMON_TX_BYTE_LO       0x000001C0
-#define R_SER_RMON_TX_BYTE_HI       0x000001C8
-#define R_SER_RMON_RX_BYTE_LO       0x000001D0
-#define R_SER_RMON_RX_BYTE_HI       0x000001D8
-#define R_SER_RMON_TX_UNDERRUN      0x000001E0
-#define R_SER_RMON_RX_OVERFLOW      0x000001E8
-#define R_SER_RMON_RX_ERRORS        0x000001F0
-#define R_SER_RMON_RX_BADADDR       0x000001F8
+#define R_SER_RMON_TX_BYTE_LO      0x000001C0
+#define R_SER_RMON_TX_BYTE_HI      0x000001C8
+#define R_SER_RMON_RX_BYTE_LO      0x000001D0
+#define R_SER_RMON_RX_BYTE_HI      0x000001D8
+#define R_SER_RMON_TX_UNDERRUN     0x000001E0
+#define R_SER_RMON_RX_OVERFLOW     0x000001E8
+#define R_SER_RMON_RX_ERRORS       0x000001F0
+#define R_SER_RMON_RX_BADADDR      0x000001F8

 
 #endif /* 1250/112x */
 
 
 #endif /* 1250/112x */
 


@@ -486,38 +486,38 @@
     * Generic Bus Registers
     ********************************************************************* */
 
     * Generic Bus Registers
     ********************************************************************* */
 

-#define IO_EXT_CFG_COUNT            8
+#define IO_EXT_CFG_COUNT           8

 
 #define A_IO_EXT_BASE              0x0010061000
 #define A_IO_EXT_REG(r)                    (A_IO_EXT_BASE + (r))
 
 
 #define A_IO_EXT_BASE              0x0010061000
 #define A_IO_EXT_REG(r)                    (A_IO_EXT_BASE + (r))
 

-#define A_IO_EXT_CFG_BASE           0x0010061000
-#define A_IO_EXT_MULT_SIZE_BASE     0x0010061100
+#define A_IO_EXT_CFG_BASE          0x0010061000
+#define A_IO_EXT_MULT_SIZE_BASE            0x0010061100

 #define A_IO_EXT_START_ADDR_BASE    0x0010061200
 #define A_IO_EXT_START_ADDR_BASE    0x0010061200

-#define A_IO_EXT_TIME_CFG0_BASE     0x0010061600
-#define A_IO_EXT_TIME_CFG1_BASE     0x0010061700
+#define A_IO_EXT_TIME_CFG0_BASE            0x0010061600
+#define A_IO_EXT_TIME_CFG1_BASE            0x0010061700

 
 #define IO_EXT_REGISTER_SPACING            8
 #define A_IO_EXT_CS_BASE(cs)       (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs))
 #define R_IO_EXT_REG(reg, cs)      ((cs)*IO_EXT_REGISTER_SPACING + (reg))
 
 #define R_IO_EXT_CFG               0x0000
 
 #define IO_EXT_REGISTER_SPACING            8
 #define A_IO_EXT_CS_BASE(cs)       (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs))
 #define R_IO_EXT_REG(reg, cs)      ((cs)*IO_EXT_REGISTER_SPACING + (reg))
 
 #define R_IO_EXT_CFG               0x0000

-#define R_IO_EXT_MULT_SIZE          0x0100
+#define R_IO_EXT_MULT_SIZE         0x0100

 #define R_IO_EXT_START_ADDR        0x0200
 #define R_IO_EXT_START_ADDR        0x0200

-#define R_IO_EXT_TIME_CFG0          0x0600
-#define R_IO_EXT_TIME_CFG1          0x0700
-
-
-#define A_IO_INTERRUPT_STATUS       0x0010061A00
-#define A_IO_INTERRUPT_DATA0        0x0010061A10
-#define A_IO_INTERRUPT_DATA1        0x0010061A18
-#define A_IO_INTERRUPT_DATA2        0x0010061A20
-#define A_IO_INTERRUPT_DATA3        0x0010061A28
-#define A_IO_INTERRUPT_ADDR0        0x0010061A30
-#define A_IO_INTERRUPT_ADDR1        0x0010061A40
-#define A_IO_INTERRUPT_PARITY       0x0010061A50
-#define A_IO_PCMCIA_CFG             0x0010061A60
-#define A_IO_PCMCIA_STATUS          0x0010061A70
+#define R_IO_EXT_TIME_CFG0         0x0600
+#define R_IO_EXT_TIME_CFG1         0x0700
+
+
+#define A_IO_INTERRUPT_STATUS      0x0010061A00
+#define A_IO_INTERRUPT_DATA0       0x0010061A10
+#define A_IO_INTERRUPT_DATA1       0x0010061A18
+#define A_IO_INTERRUPT_DATA2       0x0010061A20
+#define A_IO_INTERRUPT_DATA3       0x0010061A28
+#define A_IO_INTERRUPT_ADDR0       0x0010061A30
+#define A_IO_INTERRUPT_ADDR1       0x0010061A40
+#define A_IO_INTERRUPT_PARITY      0x0010061A50
+#define A_IO_PCMCIA_CFG                    0x0010061A60
+#define A_IO_PCMCIA_STATUS         0x0010061A70

 #define A_IO_DRIVE_0               0x0010061300
 #define A_IO_DRIVE_1               0x0010061308
 #define A_IO_DRIVE_2               0x0010061310
 #define A_IO_DRIVE_0               0x0010061300
 #define A_IO_DRIVE_1               0x0010061308
 #define A_IO_DRIVE_2               0x0010061310


@@ -527,76 +527,76 @@
 #define R_IO_DRIVE(x)              ((x)*IO_DRIVE_REGISTER_SPACING)
 #define A_IO_DRIVE(x)              (A_IO_DRIVE_BASE + R_IO_DRIVE(x))
 
 #define R_IO_DRIVE(x)              ((x)*IO_DRIVE_REGISTER_SPACING)
 #define A_IO_DRIVE(x)              (A_IO_DRIVE_BASE + R_IO_DRIVE(x))
 

-#define R_IO_INTERRUPT_STATUS       0x0A00
-#define R_IO_INTERRUPT_DATA0        0x0A10
-#define R_IO_INTERRUPT_DATA1        0x0A18
-#define R_IO_INTERRUPT_DATA2        0x0A20
-#define R_IO_INTERRUPT_DATA3        0x0A28
-#define R_IO_INTERRUPT_ADDR0        0x0A30
-#define R_IO_INTERRUPT_ADDR1        0x0A40
-#define R_IO_INTERRUPT_PARITY       0x0A50
-#define R_IO_PCMCIA_CFG             0x0A60
-#define R_IO_PCMCIA_STATUS          0x0A70
+#define R_IO_INTERRUPT_STATUS      0x0A00
+#define R_IO_INTERRUPT_DATA0       0x0A10
+#define R_IO_INTERRUPT_DATA1       0x0A18
+#define R_IO_INTERRUPT_DATA2       0x0A20
+#define R_IO_INTERRUPT_DATA3       0x0A28
+#define R_IO_INTERRUPT_ADDR0       0x0A30
+#define R_IO_INTERRUPT_ADDR1       0x0A40
+#define R_IO_INTERRUPT_PARITY      0x0A50
+#define R_IO_PCMCIA_CFG                    0x0A60
+#define R_IO_PCMCIA_STATUS         0x0A70

 
 /*  *********************************************************************
     * GPIO Registers
     ********************************************************************* */
 
 
 /*  *********************************************************************
     * GPIO Registers
     ********************************************************************* */
 

-#define A_GPIO_CLR_EDGE             0x0010061A80
-#define A_GPIO_INT_TYPE             0x0010061A88
-#define A_GPIO_INPUT_INVERT         0x0010061A90
-#define A_GPIO_GLITCH               0x0010061A98
-#define A_GPIO_READ                 0x0010061AA0
-#define A_GPIO_DIRECTION            0x0010061AA8
-#define A_GPIO_PIN_CLR              0x0010061AB0
-#define A_GPIO_PIN_SET              0x0010061AB8
+#define A_GPIO_CLR_EDGE                    0x0010061A80
+#define A_GPIO_INT_TYPE                    0x0010061A88
+#define A_GPIO_INPUT_INVERT        0x0010061A90
+#define A_GPIO_GLITCH              0x0010061A98
+#define A_GPIO_READ                0x0010061AA0
+#define A_GPIO_DIRECTION           0x0010061AA8
+#define A_GPIO_PIN_CLR             0x0010061AB0
+#define A_GPIO_PIN_SET             0x0010061AB8

 
 #define A_GPIO_BASE                0x0010061A80
 
 
 #define A_GPIO_BASE                0x0010061A80
 

-#define R_GPIO_CLR_EDGE             0x00
-#define R_GPIO_INT_TYPE             0x08
-#define R_GPIO_INPUT_INVERT         0x10
-#define R_GPIO_GLITCH               0x18
-#define R_GPIO_READ                 0x20
-#define R_GPIO_DIRECTION            0x28
-#define R_GPIO_PIN_CLR              0x30
-#define R_GPIO_PIN_SET              0x38
+#define R_GPIO_CLR_EDGE                    0x00
+#define R_GPIO_INT_TYPE                    0x08
+#define R_GPIO_INPUT_INVERT        0x10
+#define R_GPIO_GLITCH              0x18
+#define R_GPIO_READ                0x20
+#define R_GPIO_DIRECTION           0x28
+#define R_GPIO_PIN_CLR             0x30
+#define R_GPIO_PIN_SET             0x38

 
 /*  *********************************************************************
     * SMBus Registers
     ********************************************************************* */
 
 
 /*  *********************************************************************
     * SMBus Registers
     ********************************************************************* */
 

-#define A_SMB_XTRA_0                0x0010060000
-#define A_SMB_XTRA_1                0x0010060008
-#define A_SMB_FREQ_0                0x0010060010
-#define A_SMB_FREQ_1                0x0010060018
-#define A_SMB_STATUS_0              0x0010060020
-#define A_SMB_STATUS_1              0x0010060028
-#define A_SMB_CMD_0                 0x0010060030
-#define A_SMB_CMD_1                 0x0010060038
-#define A_SMB_START_0               0x0010060040
-#define A_SMB_START_1               0x0010060048
-#define A_SMB_DATA_0                0x0010060050
-#define A_SMB_DATA_1                0x0010060058
-#define A_SMB_CONTROL_0             0x0010060060
-#define A_SMB_CONTROL_1             0x0010060068
-#define A_SMB_PEC_0                 0x0010060070
-#define A_SMB_PEC_1                 0x0010060078
-
-#define A_SMB_0                     0x0010060000
-#define A_SMB_1                     0x0010060008
-#define SMB_REGISTER_SPACING        0x8
-#define A_SMB_BASE(idx)             (A_SMB_0+(idx)*SMB_REGISTER_SPACING)
+#define A_SMB_XTRA_0               0x0010060000
+#define A_SMB_XTRA_1               0x0010060008
+#define A_SMB_FREQ_0               0x0010060010
+#define A_SMB_FREQ_1               0x0010060018
+#define A_SMB_STATUS_0             0x0010060020
+#define A_SMB_STATUS_1             0x0010060028
+#define A_SMB_CMD_0                0x0010060030
+#define A_SMB_CMD_1                0x0010060038
+#define A_SMB_START_0              0x0010060040
+#define A_SMB_START_1              0x0010060048
+#define A_SMB_DATA_0               0x0010060050
+#define A_SMB_DATA_1               0x0010060058
+#define A_SMB_CONTROL_0                    0x0010060060
+#define A_SMB_CONTROL_1                    0x0010060068
+#define A_SMB_PEC_0                0x0010060070
+#define A_SMB_PEC_1                0x0010060078
+
+#define A_SMB_0                            0x0010060000
+#define A_SMB_1                            0x0010060008
+#define SMB_REGISTER_SPACING       0x8
+#define A_SMB_BASE(idx)                    (A_SMB_0+(idx)*SMB_REGISTER_SPACING)

 #define A_SMB_REGISTER(idx, reg)    (A_SMB_BASE(idx)+(reg))
 
 #define A_SMB_REGISTER(idx, reg)    (A_SMB_BASE(idx)+(reg))
 

-#define R_SMB_XTRA                  0x0000000000
-#define R_SMB_FREQ                  0x0000000010
-#define R_SMB_STATUS                0x0000000020
-#define R_SMB_CMD                   0x0000000030
-#define R_SMB_START                 0x0000000040
-#define R_SMB_DATA                  0x0000000050
-#define R_SMB_CONTROL               0x0000000060
-#define R_SMB_PEC                   0x0000000070
+#define R_SMB_XTRA                 0x0000000000
+#define R_SMB_FREQ                 0x0000000010
+#define R_SMB_STATUS               0x0000000020
+#define R_SMB_CMD                  0x0000000030
+#define R_SMB_START                0x0000000040
+#define R_SMB_DATA                 0x0000000050
+#define R_SMB_CONTROL              0x0000000060
+#define R_SMB_PEC                  0x0000000070

 
 /*  *********************************************************************
     * Timer Registers
 
 /*  *********************************************************************
     * Timer Registers


@@ -607,55 +607,55 @@
  */
 
 #define A_SCD_WDOG_0               0x0010020050
  */
 
 #define A_SCD_WDOG_0               0x0010020050

-#define A_SCD_WDOG_1                0x0010020150
-#define SCD_WDOG_SPACING            0x100
+#define A_SCD_WDOG_1               0x0010020150
+#define SCD_WDOG_SPACING           0x100

 #define SCD_NUM_WDOGS              2
 #define SCD_NUM_WDOGS              2

-#define A_SCD_WDOG_BASE(w)          (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w))
+#define A_SCD_WDOG_BASE(w)         (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w))

 #define A_SCD_WDOG_REGISTER(w, r)   (A_SCD_WDOG_BASE(w) + (r))
 
 #define R_SCD_WDOG_INIT                    0x0000000000
 #define R_SCD_WDOG_CNT             0x0000000008
 #define R_SCD_WDOG_CFG             0x0000000010
 
 #define A_SCD_WDOG_REGISTER(w, r)   (A_SCD_WDOG_BASE(w) + (r))
 
 #define R_SCD_WDOG_INIT                    0x0000000000
 #define R_SCD_WDOG_CNT             0x0000000008
 #define R_SCD_WDOG_CFG             0x0000000010
 

-#define A_SCD_WDOG_INIT_0           0x0010020050
-#define A_SCD_WDOG_CNT_0            0x0010020058
-#define A_SCD_WDOG_CFG_0            0x0010020060
+#define A_SCD_WDOG_INIT_0          0x0010020050
+#define A_SCD_WDOG_CNT_0           0x0010020058
+#define A_SCD_WDOG_CFG_0           0x0010020060

 
 

-#define A_SCD_WDOG_INIT_1           0x0010020150
-#define A_SCD_WDOG_CNT_1            0x0010020158
-#define A_SCD_WDOG_CFG_1            0x0010020160
+#define A_SCD_WDOG_INIT_1          0x0010020150
+#define A_SCD_WDOG_CNT_1           0x0010020158
+#define A_SCD_WDOG_CFG_1           0x0010020160

 
 /*
  * Generic timers
  */
 
 #define A_SCD_TIMER_0              0x0010020070
 
 /*
  * Generic timers
  */
 
 #define A_SCD_TIMER_0              0x0010020070

-#define A_SCD_TIMER_1               0x0010020078
+#define A_SCD_TIMER_1              0x0010020078

 #define A_SCD_TIMER_2              0x0010020170
 #define A_SCD_TIMER_2              0x0010020170

-#define A_SCD_TIMER_3               0x0010020178
+#define A_SCD_TIMER_3              0x0010020178

 #define SCD_NUM_TIMERS             4
 #define SCD_NUM_TIMERS             4

-#define A_SCD_TIMER_BASE(w)         (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1))
+#define A_SCD_TIMER_BASE(w)        (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1))

 #define A_SCD_TIMER_REGISTER(w, r)  (A_SCD_TIMER_BASE(w) + (r))
 
 #define R_SCD_TIMER_INIT           0x0000000000
 #define R_SCD_TIMER_CNT                    0x0000000010
 #define R_SCD_TIMER_CFG                    0x0000000020
 
 #define A_SCD_TIMER_REGISTER(w, r)  (A_SCD_TIMER_BASE(w) + (r))
 
 #define R_SCD_TIMER_INIT           0x0000000000
 #define R_SCD_TIMER_CNT                    0x0000000010
 #define R_SCD_TIMER_CFG                    0x0000000020
 

-#define A_SCD_TIMER_INIT_0          0x0010020070
-#define A_SCD_TIMER_CNT_0           0x0010020080
-#define A_SCD_TIMER_CFG_0           0x0010020090
+#define A_SCD_TIMER_INIT_0         0x0010020070
+#define A_SCD_TIMER_CNT_0          0x0010020080
+#define A_SCD_TIMER_CFG_0          0x0010020090

 
 

-#define A_SCD_TIMER_INIT_1          0x0010020078
-#define A_SCD_TIMER_CNT_1           0x0010020088
-#define A_SCD_TIMER_CFG_1           0x0010020098
+#define A_SCD_TIMER_INIT_1         0x0010020078
+#define A_SCD_TIMER_CNT_1          0x0010020088
+#define A_SCD_TIMER_CFG_1          0x0010020098

 
 

-#define A_SCD_TIMER_INIT_2          0x0010020170
-#define A_SCD_TIMER_CNT_2           0x0010020180
-#define A_SCD_TIMER_CFG_2           0x0010020190
+#define A_SCD_TIMER_INIT_2         0x0010020170
+#define A_SCD_TIMER_CNT_2          0x0010020180
+#define A_SCD_TIMER_CFG_2          0x0010020190

 
 

-#define A_SCD_TIMER_INIT_3          0x0010020178
-#define A_SCD_TIMER_CNT_3           0x0010020188
-#define A_SCD_TIMER_CFG_3           0x0010020198
+#define A_SCD_TIMER_INIT_3         0x0010020178
+#define A_SCD_TIMER_CNT_3          0x0010020188
+#define A_SCD_TIMER_CFG_3          0x0010020198

 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define A_SCD_SCRATCH             0x0010020C10
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define A_SCD_SCRATCH             0x0010020C10


@@ -671,28 +671,28 @@
     * System Control Registers
     ********************************************************************* */
 
     * System Control Registers
     ********************************************************************* */
 

-#define A_SCD_SYSTEM_REVISION       0x0010020000
-#define A_SCD_SYSTEM_CFG            0x0010020008
-#define A_SCD_SYSTEM_MANUF          0x0010038000
+#define A_SCD_SYSTEM_REVISION      0x0010020000
+#define A_SCD_SYSTEM_CFG           0x0010020008
+#define A_SCD_SYSTEM_MANUF         0x0010038000

 
 /*  *********************************************************************
     * System Address Trap Registers
     ********************************************************************* */
 
 
 /*  *********************************************************************
     * System Address Trap Registers
     ********************************************************************* */
 

-#define A_ADDR_TRAP_INDEX           0x00100200B0
-#define A_ADDR_TRAP_REG             0x00100200B8
-#define A_ADDR_TRAP_UP_0            0x0010020400
-#define A_ADDR_TRAP_UP_1            0x0010020408
-#define A_ADDR_TRAP_UP_2            0x0010020410
-#define A_ADDR_TRAP_UP_3            0x0010020418
-#define A_ADDR_TRAP_DOWN_0          0x0010020420
-#define A_ADDR_TRAP_DOWN_1          0x0010020428
-#define A_ADDR_TRAP_DOWN_2          0x0010020430
-#define A_ADDR_TRAP_DOWN_3          0x0010020438
-#define A_ADDR_TRAP_CFG_0           0x0010020440
-#define A_ADDR_TRAP_CFG_1           0x0010020448
-#define A_ADDR_TRAP_CFG_2           0x0010020450
-#define A_ADDR_TRAP_CFG_3           0x0010020458
+#define A_ADDR_TRAP_INDEX          0x00100200B0
+#define A_ADDR_TRAP_REG                    0x00100200B8
+#define A_ADDR_TRAP_UP_0           0x0010020400
+#define A_ADDR_TRAP_UP_1           0x0010020408
+#define A_ADDR_TRAP_UP_2           0x0010020410
+#define A_ADDR_TRAP_UP_3           0x0010020418
+#define A_ADDR_TRAP_DOWN_0         0x0010020420
+#define A_ADDR_TRAP_DOWN_1         0x0010020428
+#define A_ADDR_TRAP_DOWN_2         0x0010020430
+#define A_ADDR_TRAP_DOWN_3         0x0010020438
+#define A_ADDR_TRAP_CFG_0          0x0010020440
+#define A_ADDR_TRAP_CFG_1          0x0010020448
+#define A_ADDR_TRAP_CFG_2          0x0010020450
+#define A_ADDR_TRAP_CFG_3          0x0010020458

 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define A_ADDR_TRAP_REG_DEBUG      0x0010020460
 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #define A_ADDR_TRAP_REG_DEBUG      0x0010020460
 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */


@@ -708,31 +708,31 @@
     * System Interrupt Mapper Registers
     ********************************************************************* */
 
     * System Interrupt Mapper Registers
     ********************************************************************* */
 

-#define A_IMR_CPU0_BASE                 0x0010020000
-#define A_IMR_CPU1_BASE                 0x0010022000
-#define IMR_REGISTER_SPACING            0x2000
-#define IMR_REGISTER_SPACING_SHIFT      13
+#define A_IMR_CPU0_BASE                        0x0010020000
+#define A_IMR_CPU1_BASE                        0x0010022000
+#define IMR_REGISTER_SPACING           0x2000
+#define IMR_REGISTER_SPACING_SHIFT     13

 
 #define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING)
 #define A_IMR_REGISTER(cpu, reg) (A_IMR_MAPPER(cpu)+(reg))
 
 
 #define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING)
 #define A_IMR_REGISTER(cpu, reg) (A_IMR_MAPPER(cpu)+(reg))
 

-#define R_IMR_INTERRUPT_DIAG            0x0010
-#define R_IMR_INTERRUPT_LDT             0x0018
-#define R_IMR_INTERRUPT_MASK            0x0028
-#define R_IMR_INTERRUPT_TRACE           0x0038
-#define R_IMR_INTERRUPT_SOURCE_STATUS   0x0040
-#define R_IMR_LDT_INTERRUPT_SET         0x0048
-#define R_IMR_LDT_INTERRUPT             0x0018
-#define R_IMR_LDT_INTERRUPT_CLR         0x0020
-#define R_IMR_MAILBOX_CPU               0x00c0
-#define R_IMR_ALIAS_MAILBOX_CPU         0x1000
-#define R_IMR_MAILBOX_SET_CPU           0x00C8
-#define R_IMR_ALIAS_MAILBOX_SET_CPU     0x1008
-#define R_IMR_MAILBOX_CLR_CPU           0x00D0
-#define R_IMR_INTERRUPT_STATUS_BASE     0x0100
-#define R_IMR_INTERRUPT_STATUS_COUNT    7
-#define R_IMR_INTERRUPT_MAP_BASE        0x0200
-#define R_IMR_INTERRUPT_MAP_COUNT       64
+#define R_IMR_INTERRUPT_DIAG           0x0010
+#define R_IMR_INTERRUPT_LDT            0x0018
+#define R_IMR_INTERRUPT_MASK           0x0028
+#define R_IMR_INTERRUPT_TRACE          0x0038
+#define R_IMR_INTERRUPT_SOURCE_STATUS  0x0040
+#define R_IMR_LDT_INTERRUPT_SET                0x0048
+#define R_IMR_LDT_INTERRUPT            0x0018
+#define R_IMR_LDT_INTERRUPT_CLR                0x0020
+#define R_IMR_MAILBOX_CPU              0x00c0
+#define R_IMR_ALIAS_MAILBOX_CPU                0x1000
+#define R_IMR_MAILBOX_SET_CPU          0x00C8
+#define R_IMR_ALIAS_MAILBOX_SET_CPU    0x1008
+#define R_IMR_MAILBOX_CLR_CPU          0x00D0
+#define R_IMR_INTERRUPT_STATUS_BASE    0x0100
+#define R_IMR_INTERRUPT_STATUS_COUNT   7
+#define R_IMR_INTERRUPT_MAP_BASE       0x0200
+#define R_IMR_INTERRUPT_MAP_COUNT      64

 
 /*
  * these macros work together to build the address of a mailbox
 
 /*
  * these macros work together to build the address of a mailbox


@@ -746,11 +746,11 @@
     * System Performance Counter Registers
     ********************************************************************* */
 
     * System Performance Counter Registers
     ********************************************************************* */
 

-#define A_SCD_PERF_CNT_CFG          0x00100204C0
-#define A_SCD_PERF_CNT_0            0x00100204D0
-#define A_SCD_PERF_CNT_1            0x00100204D8
-#define A_SCD_PERF_CNT_2            0x00100204E0
-#define A_SCD_PERF_CNT_3            0x00100204E8
+#define A_SCD_PERF_CNT_CFG         0x00100204C0
+#define A_SCD_PERF_CNT_0           0x00100204D0
+#define A_SCD_PERF_CNT_1           0x00100204D8
+#define A_SCD_PERF_CNT_2           0x00100204E0
+#define A_SCD_PERF_CNT_3           0x00100204E8

 
 #define SCD_NUM_PERF_CNT 4
 #define SCD_PERF_CNT_SPACING 8
 
 #define SCD_NUM_PERF_CNT 4
 #define SCD_PERF_CNT_SPACING 8


@@ -760,46 +760,46 @@
     * System Bus Watcher Registers
     ********************************************************************* */
 
     * System Bus Watcher Registers
     ********************************************************************* */
 

-#define A_SCD_BUS_ERR_STATUS        0x0010020880
+#define A_SCD_BUS_ERR_STATUS       0x0010020880

 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define A_SCD_BUS_ERR_STATUS_DEBUG  0x00100208D0
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define A_SCD_BUS_ERR_STATUS_DEBUG  0x00100208D0

-#define A_BUS_ERR_STATUS_DEBUG  0x00100208D0
+#define A_BUS_ERR_STATUS_DEBUG 0x00100208D0

 #endif /* 1250 PASS2 || 112x PASS1 */
 #endif /* 1250 PASS2 || 112x PASS1 */

-#define A_BUS_ERR_DATA_0            0x00100208A0
-#define A_BUS_ERR_DATA_1            0x00100208A8
-#define A_BUS_ERR_DATA_2            0x00100208B0
-#define A_BUS_ERR_DATA_3            0x00100208B8
-#define A_BUS_L2_ERRORS             0x00100208C0
-#define A_BUS_MEM_IO_ERRORS         0x00100208C8
+#define A_BUS_ERR_DATA_0           0x00100208A0
+#define A_BUS_ERR_DATA_1           0x00100208A8
+#define A_BUS_ERR_DATA_2           0x00100208B0
+#define A_BUS_ERR_DATA_3           0x00100208B8
+#define A_BUS_L2_ERRORS                    0x00100208C0
+#define A_BUS_MEM_IO_ERRORS        0x00100208C8

 
 /*  *********************************************************************
     * System Debug Controller Registers
     ********************************************************************* */
 
 
 /*  *********************************************************************
     * System Debug Controller Registers
     ********************************************************************* */
 

-#define A_SCD_JTAG_BASE             0x0010000000
+#define A_SCD_JTAG_BASE                    0x0010000000

 
 /*  *********************************************************************
     * System Trace Buffer Registers
     ********************************************************************* */
 
 
 /*  *********************************************************************
     * System Trace Buffer Registers
     ********************************************************************* */
 

-#define A_SCD_TRACE_CFG             0x0010020A00
-#define A_SCD_TRACE_READ            0x0010020A08
-#define A_SCD_TRACE_EVENT_0         0x0010020A20
-#define A_SCD_TRACE_EVENT_1         0x0010020A28
-#define A_SCD_TRACE_EVENT_2         0x0010020A30
-#define A_SCD_TRACE_EVENT_3         0x0010020A38
-#define A_SCD_TRACE_SEQUENCE_0      0x0010020A40
-#define A_SCD_TRACE_SEQUENCE_1      0x0010020A48
-#define A_SCD_TRACE_SEQUENCE_2      0x0010020A50
-#define A_SCD_TRACE_SEQUENCE_3      0x0010020A58
-#define A_SCD_TRACE_EVENT_4         0x0010020A60
-#define A_SCD_TRACE_EVENT_5         0x0010020A68
-#define A_SCD_TRACE_EVENT_6         0x0010020A70
-#define A_SCD_TRACE_EVENT_7         0x0010020A78
-#define A_SCD_TRACE_SEQUENCE_4      0x0010020A80
-#define A_SCD_TRACE_SEQUENCE_5      0x0010020A88
-#define A_SCD_TRACE_SEQUENCE_6      0x0010020A90
-#define A_SCD_TRACE_SEQUENCE_7      0x0010020A98
+#define A_SCD_TRACE_CFG                    0x0010020A00
+#define A_SCD_TRACE_READ           0x0010020A08
+#define A_SCD_TRACE_EVENT_0        0x0010020A20
+#define A_SCD_TRACE_EVENT_1        0x0010020A28
+#define A_SCD_TRACE_EVENT_2        0x0010020A30
+#define A_SCD_TRACE_EVENT_3        0x0010020A38
+#define A_SCD_TRACE_SEQUENCE_0     0x0010020A40
+#define A_SCD_TRACE_SEQUENCE_1     0x0010020A48
+#define A_SCD_TRACE_SEQUENCE_2     0x0010020A50
+#define A_SCD_TRACE_SEQUENCE_3     0x0010020A58
+#define A_SCD_TRACE_EVENT_4        0x0010020A60
+#define A_SCD_TRACE_EVENT_5        0x0010020A68
+#define A_SCD_TRACE_EVENT_6        0x0010020A70
+#define A_SCD_TRACE_EVENT_7        0x0010020A78
+#define A_SCD_TRACE_SEQUENCE_4     0x0010020A80
+#define A_SCD_TRACE_SEQUENCE_5     0x0010020A88
+#define A_SCD_TRACE_SEQUENCE_6     0x0010020A90
+#define A_SCD_TRACE_SEQUENCE_7     0x0010020A98

 
 #define TRACE_REGISTER_SPACING 8
 #define TRACE_NUM_REGISTERS    8
 
 #define TRACE_REGISTER_SPACING 8
 #define TRACE_NUM_REGISTERS    8


@@ -814,8 +814,8 @@
     * System Generic DMA Registers
     ********************************************************************* */
 
     * System Generic DMA Registers
     ********************************************************************* */
 

-#define A_DM_0                     0x0010020B00
-#define A_DM_1                     0x0010020B20
+#define A_DM_0                     0x0010020B00
+#define A_DM_1                     0x0010020B20

 #define A_DM_2                     0x0010020B40
 #define A_DM_3                     0x0010020B60
 #define DM_REGISTER_SPACING        0x20
 #define A_DM_2                     0x0010020B40
 #define A_DM_3                     0x0010020B60
 #define DM_REGISTER_SPACING        0x20


@@ -854,39 +854,39 @@
     ********************************************************************* */
 
 #if SIBYTE_HDR_FEATURE_1250_112x
     ********************************************************************* */
 
 #if SIBYTE_HDR_FEATURE_1250_112x

-#define A_PHYS_MEMORY_0                 _SB_MAKE64(0x0000000000)
-#define A_PHYS_MEMORY_SIZE              _SB_MAKE64((256*1024*1024))
-#define A_PHYS_SYSTEM_CTL               _SB_MAKE64(0x0010000000)
-#define A_PHYS_IO_SYSTEM                _SB_MAKE64(0x0010060000)
+#define A_PHYS_MEMORY_0                        _SB_MAKE64(0x0000000000)
+#define A_PHYS_MEMORY_SIZE             _SB_MAKE64((256*1024*1024))
+#define A_PHYS_SYSTEM_CTL              _SB_MAKE64(0x0010000000)
+#define A_PHYS_IO_SYSTEM               _SB_MAKE64(0x0010060000)

 #define A_PHYS_GENBUS                  _SB_MAKE64(0x0010090000)
 #define A_PHYS_GENBUS_END              _SB_MAKE64(0x0040000000)
 #define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000)
 #define A_PHYS_GENBUS                  _SB_MAKE64(0x0010090000)
 #define A_PHYS_GENBUS_END              _SB_MAKE64(0x0040000000)
 #define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000)

-#define A_PHYS_LDTPCI_IO_MATCH_BITS_32  _SB_MAKE64(0x0060000000)
-#define A_PHYS_MEMORY_1                 _SB_MAKE64(0x0080000000)
-#define A_PHYS_MEMORY_2                 _SB_MAKE64(0x0090000000)
-#define A_PHYS_MEMORY_3                 _SB_MAKE64(0x00C0000000)
-#define A_PHYS_L2_CACHE_TEST            _SB_MAKE64(0x00D0000000)
-#define A_PHYS_LDT_SPECIAL_MATCH_BYTES  _SB_MAKE64(0x00D8000000)
-#define A_PHYS_LDTPCI_IO_MATCH_BYTES    _SB_MAKE64(0x00DC000000)
-#define A_PHYS_LDTPCI_CFG_MATCH_BYTES   _SB_MAKE64(0x00DE000000)
-#define A_PHYS_LDT_SPECIAL_MATCH_BITS   _SB_MAKE64(0x00F8000000)
-#define A_PHYS_LDTPCI_IO_MATCH_BITS     _SB_MAKE64(0x00FC000000)
-#define A_PHYS_LDTPCI_CFG_MATCH_BITS    _SB_MAKE64(0x00FE000000)
-#define A_PHYS_MEMORY_EXP               _SB_MAKE64(0x0100000000)
-#define A_PHYS_MEMORY_EXP_SIZE          _SB_MAKE64((508*1024*1024*1024))
-#define A_PHYS_LDT_EXP                  _SB_MAKE64(0x8000000000)
-#define A_PHYS_PCI_FULLACCESS_BYTES     _SB_MAKE64(0xF000000000)
-#define A_PHYS_PCI_FULLACCESS_BITS      _SB_MAKE64(0xF100000000)
-#define A_PHYS_RESERVED                 _SB_MAKE64(0xF200000000)
-#define A_PHYS_RESERVED_SPECIAL_LDT     _SB_MAKE64(0xFD00000000)
-
-#define A_PHYS_L2CACHE_WAY_SIZE         _SB_MAKE64(0x0000020000)
-#define PHYS_L2CACHE_NUM_WAYS           4
-#define A_PHYS_L2CACHE_TOTAL_SIZE       _SB_MAKE64(0x0000080000)
-#define A_PHYS_L2CACHE_WAY0             _SB_MAKE64(0x00D0180000)
-#define A_PHYS_L2CACHE_WAY1             _SB_MAKE64(0x00D01A0000)
-#define A_PHYS_L2CACHE_WAY2             _SB_MAKE64(0x00D01C0000)
-#define A_PHYS_L2CACHE_WAY3             _SB_MAKE64(0x00D01E0000)
+#define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MAKE64(0x0060000000)
+#define A_PHYS_MEMORY_1                        _SB_MAKE64(0x0080000000)
+#define A_PHYS_MEMORY_2                        _SB_MAKE64(0x0090000000)
+#define A_PHYS_MEMORY_3                        _SB_MAKE64(0x00C0000000)
+#define A_PHYS_L2_CACHE_TEST           _SB_MAKE64(0x00D0000000)
+#define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000)
+#define A_PHYS_LDTPCI_IO_MATCH_BYTES   _SB_MAKE64(0x00DC000000)
+#define A_PHYS_LDTPCI_CFG_MATCH_BYTES  _SB_MAKE64(0x00DE000000)
+#define A_PHYS_LDT_SPECIAL_MATCH_BITS  _SB_MAKE64(0x00F8000000)
+#define A_PHYS_LDTPCI_IO_MATCH_BITS    _SB_MAKE64(0x00FC000000)
+#define A_PHYS_LDTPCI_CFG_MATCH_BITS   _SB_MAKE64(0x00FE000000)
+#define A_PHYS_MEMORY_EXP              _SB_MAKE64(0x0100000000)
+#define A_PHYS_MEMORY_EXP_SIZE         _SB_MAKE64((508*1024*1024*1024))
+#define A_PHYS_LDT_EXP                 _SB_MAKE64(0x8000000000)
+#define A_PHYS_PCI_FULLACCESS_BYTES    _SB_MAKE64(0xF000000000)
+#define A_PHYS_PCI_FULLACCESS_BITS     _SB_MAKE64(0xF100000000)
+#define A_PHYS_RESERVED                        _SB_MAKE64(0xF200000000)
+#define A_PHYS_RESERVED_SPECIAL_LDT    _SB_MAKE64(0xFD00000000)
+
+#define A_PHYS_L2CACHE_WAY_SIZE                _SB_MAKE64(0x0000020000)
+#define PHYS_L2CACHE_NUM_WAYS          4
+#define A_PHYS_L2CACHE_TOTAL_SIZE      _SB_MAKE64(0x0000080000)
+#define A_PHYS_L2CACHE_WAY0            _SB_MAKE64(0x00D0180000)
+#define A_PHYS_L2CACHE_WAY1            _SB_MAKE64(0x00D01A0000)
+#define A_PHYS_L2CACHE_WAY2            _SB_MAKE64(0x00D01C0000)
+#define A_PHYS_L2CACHE_WAY3            _SB_MAKE64(0x00D01E0000)

 #endif
 
 
 #endif
 
 

diff --git a/arch/mips/include/asm/sibyte/sb1250_scd.h b/arch/mips/include/asm/sibyte/sb1250_scd.h
index 615e165dbd21d7e7e9c0d945440dee50586d37dc..d725f2f41aface5a89816c7e18d34bb03f1e7225 100644 (file)
--- a/arch/mips/include/asm/sibyte/sb1250_scd.h
+++ b/arch/mips/include/asm/sibyte/sb1250_scd.h
@@ -44,10 +44,10 @@
 
 #define M_SYS_RESERVED             _SB_MAKEMASK(8, 0)
 
 
 #define M_SYS_RESERVED             _SB_MAKEMASK(8, 0)
 

-#define S_SYS_REVISION              _SB_MAKE64(8)
-#define M_SYS_REVISION              _SB_MAKEMASK(8, S_SYS_REVISION)
-#define V_SYS_REVISION(x)           _SB_MAKEVALUE(x, S_SYS_REVISION)
-#define G_SYS_REVISION(x)           _SB_GETVALUE(x, S_SYS_REVISION, M_SYS_REVISION)
+#define S_SYS_REVISION             _SB_MAKE64(8)
+#define M_SYS_REVISION             _SB_MAKEMASK(8, S_SYS_REVISION)
+#define V_SYS_REVISION(x)          _SB_MAKEVALUE(x, S_SYS_REVISION)
+#define G_SYS_REVISION(x)          _SB_GETVALUE(x, S_SYS_REVISION, M_SYS_REVISION)

 
 #define K_SYS_REVISION_BCM1250_PASS1   0x01
 
 
 #define K_SYS_REVISION_BCM1250_PASS1   0x01
 


@@ -93,10 +93,10 @@
 #define K_SYS_REVISION_BCM1480_B0      0x11
 
 /*Cache size - 23:20  of revision register*/
 #define K_SYS_REVISION_BCM1480_B0      0x11
 
 /*Cache size - 23:20  of revision register*/

-#define S_SYS_L2C_SIZE            _SB_MAKE64(20)
-#define M_SYS_L2C_SIZE            _SB_MAKEMASK(4, S_SYS_L2C_SIZE)
-#define V_SYS_L2C_SIZE(x)         _SB_MAKEVALUE(x, S_SYS_L2C_SIZE)
-#define G_SYS_L2C_SIZE(x)         _SB_GETVALUE(x, S_SYS_L2C_SIZE, M_SYS_L2C_SIZE)
+#define S_SYS_L2C_SIZE           _SB_MAKE64(20)
+#define M_SYS_L2C_SIZE           _SB_MAKEMASK(4, S_SYS_L2C_SIZE)
+#define V_SYS_L2C_SIZE(x)        _SB_MAKEVALUE(x, S_SYS_L2C_SIZE)
+#define G_SYS_L2C_SIZE(x)        _SB_GETVALUE(x, S_SYS_L2C_SIZE, M_SYS_L2C_SIZE)

 
 #define K_SYS_L2C_SIZE_1MB     0
 #define K_SYS_L2C_SIZE_512KB   5
 
 #define K_SYS_L2C_SIZE_1MB     0
 #define K_SYS_L2C_SIZE_512KB   5


@@ -109,40 +109,40 @@
 
 
 /* Number of CPU cores, bits 27:24  of revision register*/
 
 
 /* Number of CPU cores, bits 27:24  of revision register*/

-#define S_SYS_NUM_CPUS            _SB_MAKE64(24)
-#define M_SYS_NUM_CPUS            _SB_MAKEMASK(4, S_SYS_NUM_CPUS)
-#define V_SYS_NUM_CPUS(x)         _SB_MAKEVALUE(x, S_SYS_NUM_CPUS)
-#define G_SYS_NUM_CPUS(x)         _SB_GETVALUE(x, S_SYS_NUM_CPUS, M_SYS_NUM_CPUS)
+#define S_SYS_NUM_CPUS           _SB_MAKE64(24)
+#define M_SYS_NUM_CPUS           _SB_MAKEMASK(4, S_SYS_NUM_CPUS)
+#define V_SYS_NUM_CPUS(x)        _SB_MAKEVALUE(x, S_SYS_NUM_CPUS)
+#define G_SYS_NUM_CPUS(x)        _SB_GETVALUE(x, S_SYS_NUM_CPUS, M_SYS_NUM_CPUS)

 
 
 /* XXX: discourage people from using these constants.  */
 
 
 /* XXX: discourage people from using these constants.  */

-#define S_SYS_PART                  _SB_MAKE64(16)
-#define M_SYS_PART                  _SB_MAKEMASK(16, S_SYS_PART)
-#define V_SYS_PART(x)               _SB_MAKEVALUE(x, S_SYS_PART)
-#define G_SYS_PART(x)               _SB_GETVALUE(x, S_SYS_PART, M_SYS_PART)
+#define S_SYS_PART                 _SB_MAKE64(16)
+#define M_SYS_PART                 _SB_MAKEMASK(16, S_SYS_PART)
+#define V_SYS_PART(x)              _SB_MAKEVALUE(x, S_SYS_PART)
+#define G_SYS_PART(x)              _SB_GETVALUE(x, S_SYS_PART, M_SYS_PART)

 
 /* XXX: discourage people from using these constants.  */
 
 /* XXX: discourage people from using these constants.  */

-#define K_SYS_PART_SB1250           0x1250
-#define K_SYS_PART_BCM1120          0x1121
-#define K_SYS_PART_BCM1125          0x1123
-#define K_SYS_PART_BCM1125H         0x1124
-#define K_SYS_PART_BCM1122          0x1113
+#define K_SYS_PART_SB1250          0x1250
+#define K_SYS_PART_BCM1120         0x1121
+#define K_SYS_PART_BCM1125         0x1123
+#define K_SYS_PART_BCM1125H        0x1124
+#define K_SYS_PART_BCM1122         0x1113

 
 
 /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field.  */
 
 
 /* The "peripheral set" (SOC type) is the low 4 bits of the "part" field.  */

-#define S_SYS_SOC_TYPE              _SB_MAKE64(16)
-#define M_SYS_SOC_TYPE              _SB_MAKEMASK(4, S_SYS_SOC_TYPE)
-#define V_SYS_SOC_TYPE(x)           _SB_MAKEVALUE(x, S_SYS_SOC_TYPE)
-#define G_SYS_SOC_TYPE(x)           _SB_GETVALUE(x, S_SYS_SOC_TYPE, M_SYS_SOC_TYPE)
-
-#define K_SYS_SOC_TYPE_BCM1250      0x0
-#define K_SYS_SOC_TYPE_BCM1120      0x1
-#define K_SYS_SOC_TYPE_BCM1250_ALT  0x2                /* 1250pass2 w/ 1/4 L2.  */
-#define K_SYS_SOC_TYPE_BCM1125      0x3
-#define K_SYS_SOC_TYPE_BCM1125H     0x4
-#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5                /* 1250pass2 w/ 1/2 L2.  */
-#define K_SYS_SOC_TYPE_BCM1x80      0x6
-#define K_SYS_SOC_TYPE_BCM1x55      0x7
+#define S_SYS_SOC_TYPE             _SB_MAKE64(16)
+#define M_SYS_SOC_TYPE             _SB_MAKEMASK(4, S_SYS_SOC_TYPE)
+#define V_SYS_SOC_TYPE(x)          _SB_MAKEVALUE(x, S_SYS_SOC_TYPE)
+#define G_SYS_SOC_TYPE(x)          _SB_GETVALUE(x, S_SYS_SOC_TYPE, M_SYS_SOC_TYPE)
+
+#define K_SYS_SOC_TYPE_BCM1250     0x0
+#define K_SYS_SOC_TYPE_BCM1120     0x1
+#define K_SYS_SOC_TYPE_BCM1250_ALT  0x2                /* 1250pass2 w/ 1/4 L2.  */
+#define K_SYS_SOC_TYPE_BCM1125     0x3
+#define K_SYS_SOC_TYPE_BCM1125H            0x4
+#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5                /* 1250pass2 w/ 1/2 L2.  */
+#define K_SYS_SOC_TYPE_BCM1x80     0x6
+#define K_SYS_SOC_TYPE_BCM1x55     0x7

 
 /*
  * Calculate correct SOC type given a copy of system revision register.
 
 /*
  * Calculate correct SOC type given a copy of system revision register.


@@ -169,10 +169,10 @@
         ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev))
 #endif
 
         ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev))
 #endif
 

-#define S_SYS_WID                   _SB_MAKE64(32)
-#define M_SYS_WID                   _SB_MAKEMASK(32, S_SYS_WID)
-#define V_SYS_WID(x)                _SB_MAKEVALUE(x, S_SYS_WID)
-#define G_SYS_WID(x)                _SB_GETVALUE(x, S_SYS_WID, M_SYS_WID)
+#define S_SYS_WID                  _SB_MAKE64(32)
+#define M_SYS_WID                  _SB_MAKEMASK(32, S_SYS_WID)
+#define V_SYS_WID(x)               _SB_MAKEVALUE(x, S_SYS_WID)
+#define G_SYS_WID(x)               _SB_GETVALUE(x, S_SYS_WID, M_SYS_WID)

 
 /*
  * System Manufacturing Register
 
 /*
  * System Manufacturing Register


@@ -181,37 +181,37 @@
 
 #if SIBYTE_HDR_FEATURE_1250_112x
 /* Wafer ID: bits 31:0 */
 
 #if SIBYTE_HDR_FEATURE_1250_112x
 /* Wafer ID: bits 31:0 */

-#define S_SYS_WAFERID1_200        _SB_MAKE64(0)
-#define M_SYS_WAFERID1_200        _SB_MAKEMASK(32, S_SYS_WAFERID1_200)
-#define V_SYS_WAFERID1_200(x)     _SB_MAKEVALUE(x, S_SYS_WAFERID1_200)
-#define G_SYS_WAFERID1_200(x)     _SB_GETVALUE(x, S_SYS_WAFERID1_200, M_SYS_WAFERID1_200)
+#define S_SYS_WAFERID1_200       _SB_MAKE64(0)
+#define M_SYS_WAFERID1_200       _SB_MAKEMASK(32, S_SYS_WAFERID1_200)
+#define V_SYS_WAFERID1_200(x)    _SB_MAKEVALUE(x, S_SYS_WAFERID1_200)
+#define G_SYS_WAFERID1_200(x)    _SB_GETVALUE(x, S_SYS_WAFERID1_200, M_SYS_WAFERID1_200)

 
 

-#define S_SYS_BIN                 _SB_MAKE64(32)
-#define M_SYS_BIN                 _SB_MAKEMASK(4, S_SYS_BIN)
-#define V_SYS_BIN(x)              _SB_MAKEVALUE(x, S_SYS_BIN)
-#define G_SYS_BIN(x)              _SB_GETVALUE(x, S_SYS_BIN, M_SYS_BIN)
+#define S_SYS_BIN                _SB_MAKE64(32)
+#define M_SYS_BIN                _SB_MAKEMASK(4, S_SYS_BIN)
+#define V_SYS_BIN(x)             _SB_MAKEVALUE(x, S_SYS_BIN)
+#define G_SYS_BIN(x)             _SB_GETVALUE(x, S_SYS_BIN, M_SYS_BIN)

 
 /* Wafer ID: bits 39:36 */
 
 /* Wafer ID: bits 39:36 */

-#define S_SYS_WAFERID2_200        _SB_MAKE64(36)
-#define M_SYS_WAFERID2_200        _SB_MAKEMASK(4, S_SYS_WAFERID2_200)
-#define V_SYS_WAFERID2_200(x)     _SB_MAKEVALUE(x, S_SYS_WAFERID2_200)
-#define G_SYS_WAFERID2_200(x)     _SB_GETVALUE(x, S_SYS_WAFERID2_200, M_SYS_WAFERID2_200)
+#define S_SYS_WAFERID2_200       _SB_MAKE64(36)
+#define M_SYS_WAFERID2_200       _SB_MAKEMASK(4, S_SYS_WAFERID2_200)
+#define V_SYS_WAFERID2_200(x)    _SB_MAKEVALUE(x, S_SYS_WAFERID2_200)
+#define G_SYS_WAFERID2_200(x)    _SB_GETVALUE(x, S_SYS_WAFERID2_200, M_SYS_WAFERID2_200)

 
 /* Wafer ID: bits 39:0 */
 
 /* Wafer ID: bits 39:0 */

-#define S_SYS_WAFERID_300         _SB_MAKE64(0)
-#define M_SYS_WAFERID_300         _SB_MAKEMASK(40, S_SYS_WAFERID_300)
-#define V_SYS_WAFERID_300(x)      _SB_MAKEVALUE(x, S_SYS_WAFERID_300)
-#define G_SYS_WAFERID_300(x)      _SB_GETVALUE(x, S_SYS_WAFERID_300, M_SYS_WAFERID_300)
-
-#define S_SYS_XPOS                _SB_MAKE64(40)
-#define M_SYS_XPOS                _SB_MAKEMASK(6, S_SYS_XPOS)
-#define V_SYS_XPOS(x)             _SB_MAKEVALUE(x, S_SYS_XPOS)
-#define G_SYS_XPOS(x)             _SB_GETVALUE(x, S_SYS_XPOS, M_SYS_XPOS)
-
-#define S_SYS_YPOS                _SB_MAKE64(46)
-#define M_SYS_YPOS                _SB_MAKEMASK(6, S_SYS_YPOS)
-#define V_SYS_YPOS(x)             _SB_MAKEVALUE(x, S_SYS_YPOS)
-#define G_SYS_YPOS(x)             _SB_GETVALUE(x, S_SYS_YPOS, M_SYS_YPOS)
+#define S_SYS_WAFERID_300        _SB_MAKE64(0)
+#define M_SYS_WAFERID_300        _SB_MAKEMASK(40, S_SYS_WAFERID_300)
+#define V_SYS_WAFERID_300(x)     _SB_MAKEVALUE(x, S_SYS_WAFERID_300)
+#define G_SYS_WAFERID_300(x)     _SB_GETVALUE(x, S_SYS_WAFERID_300, M_SYS_WAFERID_300)
+
+#define S_SYS_XPOS               _SB_MAKE64(40)
+#define M_SYS_XPOS               _SB_MAKEMASK(6, S_SYS_XPOS)
+#define V_SYS_XPOS(x)            _SB_MAKEVALUE(x, S_SYS_XPOS)
+#define G_SYS_XPOS(x)            _SB_GETVALUE(x, S_SYS_XPOS, M_SYS_XPOS)
+
+#define S_SYS_YPOS               _SB_MAKE64(46)
+#define M_SYS_YPOS               _SB_MAKEMASK(6, S_SYS_YPOS)
+#define V_SYS_YPOS(x)            _SB_MAKEVALUE(x, S_SYS_YPOS)
+#define G_SYS_YPOS(x)            _SB_GETVALUE(x, S_SYS_YPOS, M_SYS_YPOS)

 #endif
 
 
 #endif
 
 


@@ -221,55 +221,55 @@
  */
 
 #if SIBYTE_HDR_FEATURE_1250_112x
  */
 
 #if SIBYTE_HDR_FEATURE_1250_112x

-#define M_SYS_LDT_PLL_BYP           _SB_MAKEMASK1(3)
+#define M_SYS_LDT_PLL_BYP          _SB_MAKEMASK1(3)

 #define M_SYS_PCI_SYNC_TEST_MODE    _SB_MAKEMASK1(4)
 #define M_SYS_PCI_SYNC_TEST_MODE    _SB_MAKEMASK1(4)

-#define M_SYS_IOB0_DIV              _SB_MAKEMASK1(5)
-#define M_SYS_IOB1_DIV              _SB_MAKEMASK1(6)
-
-#define S_SYS_PLL_DIV               _SB_MAKE64(7)
-#define M_SYS_PLL_DIV               _SB_MAKEMASK(5, S_SYS_PLL_DIV)
-#define V_SYS_PLL_DIV(x)            _SB_MAKEVALUE(x, S_SYS_PLL_DIV)
-#define G_SYS_PLL_DIV(x)            _SB_GETVALUE(x, S_SYS_PLL_DIV, M_SYS_PLL_DIV)
-
-#define M_SYS_SER0_ENABLE           _SB_MAKEMASK1(12)
-#define M_SYS_SER0_RSTB_EN          _SB_MAKEMASK1(13)
-#define M_SYS_SER1_ENABLE           _SB_MAKEMASK1(14)
-#define M_SYS_SER1_RSTB_EN          _SB_MAKEMASK1(15)
-#define M_SYS_PCMCIA_ENABLE         _SB_MAKEMASK1(16)
-
-#define S_SYS_BOOT_MODE             _SB_MAKE64(17)
-#define M_SYS_BOOT_MODE             _SB_MAKEMASK(2, S_SYS_BOOT_MODE)
-#define V_SYS_BOOT_MODE(x)          _SB_MAKEVALUE(x, S_SYS_BOOT_MODE)
-#define G_SYS_BOOT_MODE(x)          _SB_GETVALUE(x, S_SYS_BOOT_MODE, M_SYS_BOOT_MODE)
-#define K_SYS_BOOT_MODE_ROM32       0
-#define K_SYS_BOOT_MODE_ROM8        1
+#define M_SYS_IOB0_DIV             _SB_MAKEMASK1(5)
+#define M_SYS_IOB1_DIV             _SB_MAKEMASK1(6)
+
+#define S_SYS_PLL_DIV              _SB_MAKE64(7)
+#define M_SYS_PLL_DIV              _SB_MAKEMASK(5, S_SYS_PLL_DIV)
+#define V_SYS_PLL_DIV(x)           _SB_MAKEVALUE(x, S_SYS_PLL_DIV)
+#define G_SYS_PLL_DIV(x)           _SB_GETVALUE(x, S_SYS_PLL_DIV, M_SYS_PLL_DIV)
+
+#define M_SYS_SER0_ENABLE          _SB_MAKEMASK1(12)
+#define M_SYS_SER0_RSTB_EN         _SB_MAKEMASK1(13)
+#define M_SYS_SER1_ENABLE          _SB_MAKEMASK1(14)
+#define M_SYS_SER1_RSTB_EN         _SB_MAKEMASK1(15)
+#define M_SYS_PCMCIA_ENABLE        _SB_MAKEMASK1(16)
+
+#define S_SYS_BOOT_MODE                    _SB_MAKE64(17)
+#define M_SYS_BOOT_MODE                    _SB_MAKEMASK(2, S_SYS_BOOT_MODE)
+#define V_SYS_BOOT_MODE(x)         _SB_MAKEVALUE(x, S_SYS_BOOT_MODE)
+#define G_SYS_BOOT_MODE(x)         _SB_GETVALUE(x, S_SYS_BOOT_MODE, M_SYS_BOOT_MODE)
+#define K_SYS_BOOT_MODE_ROM32      0
+#define K_SYS_BOOT_MODE_ROM8       1

 #define K_SYS_BOOT_MODE_SMBUS_SMALL 2
 #define K_SYS_BOOT_MODE_SMBUS_BIG   3
 
 #define K_SYS_BOOT_MODE_SMBUS_SMALL 2
 #define K_SYS_BOOT_MODE_SMBUS_BIG   3
 

-#define M_SYS_PCI_HOST              _SB_MAKEMASK1(19)
-#define M_SYS_PCI_ARBITER           _SB_MAKEMASK1(20)
-#define M_SYS_SOUTH_ON_LDT          _SB_MAKEMASK1(21)
-#define M_SYS_BIG_ENDIAN            _SB_MAKEMASK1(22)
-#define M_SYS_GENCLK_EN             _SB_MAKEMASK1(23)
-#define M_SYS_LDT_TEST_EN           _SB_MAKEMASK1(24)
-#define M_SYS_GEN_PARITY_EN         _SB_MAKEMASK1(25)
+#define M_SYS_PCI_HOST             _SB_MAKEMASK1(19)
+#define M_SYS_PCI_ARBITER          _SB_MAKEMASK1(20)
+#define M_SYS_SOUTH_ON_LDT         _SB_MAKEMASK1(21)
+#define M_SYS_BIG_ENDIAN           _SB_MAKEMASK1(22)
+#define M_SYS_GENCLK_EN                    _SB_MAKEMASK1(23)
+#define M_SYS_LDT_TEST_EN          _SB_MAKEMASK1(24)
+#define M_SYS_GEN_PARITY_EN        _SB_MAKEMASK1(25)

 
 

-#define S_SYS_CONFIG                26
-#define M_SYS_CONFIG                _SB_MAKEMASK(6, S_SYS_CONFIG)
-#define V_SYS_CONFIG(x)             _SB_MAKEVALUE(x, S_SYS_CONFIG)
-#define G_SYS_CONFIG(x)             _SB_GETVALUE(x, S_SYS_CONFIG, M_SYS_CONFIG)
+#define S_SYS_CONFIG               26
+#define M_SYS_CONFIG               _SB_MAKEMASK(6, S_SYS_CONFIG)
+#define V_SYS_CONFIG(x)                    _SB_MAKEVALUE(x, S_SYS_CONFIG)
+#define G_SYS_CONFIG(x)                    _SB_GETVALUE(x, S_SYS_CONFIG, M_SYS_CONFIG)

 
 /* The following bits are writeable by JTAG only. */
 
 
 /* The following bits are writeable by JTAG only. */
 

-#define M_SYS_CLKSTOP               _SB_MAKEMASK1(32)
-#define M_SYS_CLKSTEP               _SB_MAKEMASK1(33)
+#define M_SYS_CLKSTOP              _SB_MAKEMASK1(32)
+#define M_SYS_CLKSTEP              _SB_MAKEMASK1(33)

 
 

-#define S_SYS_CLKCOUNT              34
-#define M_SYS_CLKCOUNT              _SB_MAKEMASK(8, S_SYS_CLKCOUNT)
-#define V_SYS_CLKCOUNT(x)           _SB_MAKEVALUE(x, S_SYS_CLKCOUNT)
-#define G_SYS_CLKCOUNT(x)           _SB_GETVALUE(x, S_SYS_CLKCOUNT, M_SYS_CLKCOUNT)
+#define S_SYS_CLKCOUNT             34
+#define M_SYS_CLKCOUNT             _SB_MAKEMASK(8, S_SYS_CLKCOUNT)
+#define V_SYS_CLKCOUNT(x)          _SB_MAKEVALUE(x, S_SYS_CLKCOUNT)
+#define G_SYS_CLKCOUNT(x)          _SB_GETVALUE(x, S_SYS_CLKCOUNT, M_SYS_CLKCOUNT)

 
 

-#define M_SYS_PLL_BYPASS            _SB_MAKEMASK1(42)
+#define M_SYS_PLL_BYPASS           _SB_MAKEMASK1(42)

 
 #define S_SYS_PLL_IREF             43
 #define M_SYS_PLL_IREF             _SB_MAKEMASK(2, S_SYS_PLL_IREF)
 
 #define S_SYS_PLL_IREF             43
 #define M_SYS_PLL_IREF             _SB_MAKEMASK(2, S_SYS_PLL_IREF)


@@ -280,26 +280,26 @@
 #define S_SYS_PLL_VREG             47
 #define M_SYS_PLL_VREG             _SB_MAKEMASK(2, S_SYS_PLL_VREG)
 
 #define S_SYS_PLL_VREG             47
 #define M_SYS_PLL_VREG             _SB_MAKEMASK(2, S_SYS_PLL_VREG)
 

-#define M_SYS_MEM_RESET             _SB_MAKEMASK1(49)
-#define M_SYS_L2C_RESET             _SB_MAKEMASK1(50)
-#define M_SYS_IO_RESET_0            _SB_MAKEMASK1(51)
-#define M_SYS_IO_RESET_1            _SB_MAKEMASK1(52)
-#define M_SYS_SCD_RESET             _SB_MAKEMASK1(53)
+#define M_SYS_MEM_RESET                    _SB_MAKEMASK1(49)
+#define M_SYS_L2C_RESET                    _SB_MAKEMASK1(50)
+#define M_SYS_IO_RESET_0           _SB_MAKEMASK1(51)
+#define M_SYS_IO_RESET_1           _SB_MAKEMASK1(52)
+#define M_SYS_SCD_RESET                    _SB_MAKEMASK1(53)

 
 /* End of bits writable by JTAG only. */
 
 
 /* End of bits writable by JTAG only. */
 

-#define M_SYS_CPU_RESET_0           _SB_MAKEMASK1(54)
-#define M_SYS_CPU_RESET_1           _SB_MAKEMASK1(55)
+#define M_SYS_CPU_RESET_0          _SB_MAKEMASK1(54)
+#define M_SYS_CPU_RESET_1          _SB_MAKEMASK1(55)

 
 

-#define M_SYS_UNICPU0               _SB_MAKEMASK1(56)
-#define M_SYS_UNICPU1               _SB_MAKEMASK1(57)
+#define M_SYS_UNICPU0              _SB_MAKEMASK1(56)
+#define M_SYS_UNICPU1              _SB_MAKEMASK1(57)

 
 

-#define M_SYS_SB_SOFTRES            _SB_MAKEMASK1(58)
-#define M_SYS_EXT_RESET             _SB_MAKEMASK1(59)
-#define M_SYS_SYSTEM_RESET          _SB_MAKEMASK1(60)
+#define M_SYS_SB_SOFTRES           _SB_MAKEMASK1(58)
+#define M_SYS_EXT_RESET                    _SB_MAKEMASK1(59)
+#define M_SYS_SYSTEM_RESET         _SB_MAKEMASK1(60)

 
 

-#define M_SYS_MISR_MODE             _SB_MAKEMASK1(61)
-#define M_SYS_MISR_RESET            _SB_MAKEMASK1(62)
+#define M_SYS_MISR_MODE                    _SB_MAKEMASK1(61)
+#define M_SYS_MISR_RESET           _SB_MAKEMASK1(62)

 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define M_SYS_SW_FLAG              _SB_MAKEMASK1(63)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 #define M_SYS_SW_FLAG              _SB_MAKEMASK1(63)


@@ -313,46 +313,46 @@
  * Registers: SCD_MBOX_CPU_x
  */
 
  * Registers: SCD_MBOX_CPU_x
  */
 

-#define S_MBOX_INT_3                0
-#define M_MBOX_INT_3                _SB_MAKEMASK(16, S_MBOX_INT_3)
-#define S_MBOX_INT_2                16
-#define M_MBOX_INT_2                _SB_MAKEMASK(16, S_MBOX_INT_2)
-#define S_MBOX_INT_1                32
-#define M_MBOX_INT_1                _SB_MAKEMASK(16, S_MBOX_INT_1)
-#define S_MBOX_INT_0                48
-#define M_MBOX_INT_0                _SB_MAKEMASK(16, S_MBOX_INT_0)
+#define S_MBOX_INT_3               0
+#define M_MBOX_INT_3               _SB_MAKEMASK(16, S_MBOX_INT_3)
+#define S_MBOX_INT_2               16
+#define M_MBOX_INT_2               _SB_MAKEMASK(16, S_MBOX_INT_2)
+#define S_MBOX_INT_1               32
+#define M_MBOX_INT_1               _SB_MAKEMASK(16, S_MBOX_INT_1)
+#define S_MBOX_INT_0               48
+#define M_MBOX_INT_0               _SB_MAKEMASK(16, S_MBOX_INT_0)

 
 /*
  * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10)
  * Registers: SCD_WDOG_INIT_CNT_x
  */
 
 
 /*
  * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10)
  * Registers: SCD_WDOG_INIT_CNT_x
  */
 

-#define V_SCD_WDOG_FREQ             1000000
+#define V_SCD_WDOG_FREQ                    1000000

 
 

-#define S_SCD_WDOG_INIT             0
-#define M_SCD_WDOG_INIT             _SB_MAKEMASK(23, S_SCD_WDOG_INIT)
+#define S_SCD_WDOG_INIT                    0
+#define M_SCD_WDOG_INIT                    _SB_MAKEMASK(23, S_SCD_WDOG_INIT)

 
 

-#define S_SCD_WDOG_CNT              0
-#define M_SCD_WDOG_CNT              _SB_MAKEMASK(23, S_SCD_WDOG_CNT)
+#define S_SCD_WDOG_CNT             0
+#define M_SCD_WDOG_CNT             _SB_MAKEMASK(23, S_SCD_WDOG_CNT)

 
 

-#define S_SCD_WDOG_ENABLE           0
-#define M_SCD_WDOG_ENABLE           _SB_MAKEMASK1(S_SCD_WDOG_ENABLE)
+#define S_SCD_WDOG_ENABLE          0
+#define M_SCD_WDOG_ENABLE          _SB_MAKEMASK1(S_SCD_WDOG_ENABLE)

 
 

-#define S_SCD_WDOG_RESET_TYPE       2
-#define M_SCD_WDOG_RESET_TYPE       _SB_MAKEMASK(3, S_SCD_WDOG_RESET_TYPE)
+#define S_SCD_WDOG_RESET_TYPE      2
+#define M_SCD_WDOG_RESET_TYPE      _SB_MAKEMASK(3, S_SCD_WDOG_RESET_TYPE)

 #define V_SCD_WDOG_RESET_TYPE(x)    _SB_MAKEVALUE(x, S_SCD_WDOG_RESET_TYPE)
 #define G_SCD_WDOG_RESET_TYPE(x)    _SB_GETVALUE(x, S_SCD_WDOG_RESET_TYPE, M_SCD_WDOG_RESET_TYPE)
 
 #define V_SCD_WDOG_RESET_TYPE(x)    _SB_MAKEVALUE(x, S_SCD_WDOG_RESET_TYPE)
 #define G_SCD_WDOG_RESET_TYPE(x)    _SB_GETVALUE(x, S_SCD_WDOG_RESET_TYPE, M_SCD_WDOG_RESET_TYPE)
 

-#define K_SCD_WDOG_RESET_FULL       0  /* actually, (x & 1) == 0  */
-#define K_SCD_WDOG_RESET_SOFT       1
-#define K_SCD_WDOG_RESET_CPU0       3
-#define K_SCD_WDOG_RESET_CPU1       5
+#define K_SCD_WDOG_RESET_FULL      0   /* actually, (x & 1) == 0  */
+#define K_SCD_WDOG_RESET_SOFT      1
+#define K_SCD_WDOG_RESET_CPU0      3
+#define K_SCD_WDOG_RESET_CPU1      5

 #define K_SCD_WDOG_RESET_BOTH_CPUS  7
 
 /* This feature is present in 1250 C0 and later, but *not* in 112x A revs.  */
 #if SIBYTE_HDR_FEATURE(1250, PASS3)
 #define K_SCD_WDOG_RESET_BOTH_CPUS  7
 
 /* This feature is present in 1250 C0 and later, but *not* in 112x A revs.  */
 #if SIBYTE_HDR_FEATURE(1250, PASS3)

-#define S_SCD_WDOG_HAS_RESET        8
-#define M_SCD_WDOG_HAS_RESET        _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET)
+#define S_SCD_WDOG_HAS_RESET       8
+#define M_SCD_WDOG_HAS_RESET       _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET)

 #endif
 
 
 #endif
 
 


@@ -360,46 +360,46 @@
  * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13)
  */
 
  * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13)
  */
 

-#define V_SCD_TIMER_FREQ            1000000
+#define V_SCD_TIMER_FREQ           1000000

 
 

-#define S_SCD_TIMER_INIT            0
-#define M_SCD_TIMER_INIT            _SB_MAKEMASK(23, S_SCD_TIMER_INIT)
-#define V_SCD_TIMER_INIT(x)         _SB_MAKEVALUE(x, S_SCD_TIMER_INIT)
-#define G_SCD_TIMER_INIT(x)         _SB_GETVALUE(x, S_SCD_TIMER_INIT, M_SCD_TIMER_INIT)
+#define S_SCD_TIMER_INIT           0
+#define M_SCD_TIMER_INIT           _SB_MAKEMASK(23, S_SCD_TIMER_INIT)
+#define V_SCD_TIMER_INIT(x)        _SB_MAKEVALUE(x, S_SCD_TIMER_INIT)
+#define G_SCD_TIMER_INIT(x)        _SB_GETVALUE(x, S_SCD_TIMER_INIT, M_SCD_TIMER_INIT)

 
 #define V_SCD_TIMER_WIDTH          23
 
 #define V_SCD_TIMER_WIDTH          23

-#define S_SCD_TIMER_CNT             0
-#define M_SCD_TIMER_CNT             _SB_MAKEMASK(V_SCD_TIMER_WIDTH, S_SCD_TIMER_CNT)
-#define V_SCD_TIMER_CNT(x)         _SB_MAKEVALUE(x, S_SCD_TIMER_CNT)
-#define G_SCD_TIMER_CNT(x)         _SB_GETVALUE(x, S_SCD_TIMER_CNT, M_SCD_TIMER_CNT)
+#define S_SCD_TIMER_CNT                    0
+#define M_SCD_TIMER_CNT                    _SB_MAKEMASK(V_SCD_TIMER_WIDTH, S_SCD_TIMER_CNT)
+#define V_SCD_TIMER_CNT(x)        _SB_MAKEVALUE(x, S_SCD_TIMER_CNT)
+#define G_SCD_TIMER_CNT(x)        _SB_GETVALUE(x, S_SCD_TIMER_CNT, M_SCD_TIMER_CNT)

 
 

-#define M_SCD_TIMER_ENABLE          _SB_MAKEMASK1(0)
-#define M_SCD_TIMER_MODE            _SB_MAKEMASK1(1)
+#define M_SCD_TIMER_ENABLE         _SB_MAKEMASK1(0)
+#define M_SCD_TIMER_MODE           _SB_MAKEMASK1(1)

 #define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE
 
 /*
  * System Performance Counters
  */
 
 #define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE
 
 /*
  * System Performance Counters
  */
 

-#define S_SPC_CFG_SRC0            0
-#define M_SPC_CFG_SRC0            _SB_MAKEMASK(8, S_SPC_CFG_SRC0)
-#define V_SPC_CFG_SRC0(x)         _SB_MAKEVALUE(x, S_SPC_CFG_SRC0)
-#define G_SPC_CFG_SRC0(x)         _SB_GETVALUE(x, S_SPC_CFG_SRC0, M_SPC_CFG_SRC0)
+#define S_SPC_CFG_SRC0           0
+#define M_SPC_CFG_SRC0           _SB_MAKEMASK(8, S_SPC_CFG_SRC0)
+#define V_SPC_CFG_SRC0(x)        _SB_MAKEVALUE(x, S_SPC_CFG_SRC0)
+#define G_SPC_CFG_SRC0(x)        _SB_GETVALUE(x, S_SPC_CFG_SRC0, M_SPC_CFG_SRC0)

 
 

-#define S_SPC_CFG_SRC1            8
-#define M_SPC_CFG_SRC1            _SB_MAKEMASK(8, S_SPC_CFG_SRC1)
-#define V_SPC_CFG_SRC1(x)         _SB_MAKEVALUE(x, S_SPC_CFG_SRC1)
-#define G_SPC_CFG_SRC1(x)         _SB_GETVALUE(x, S_SPC_CFG_SRC1, M_SPC_CFG_SRC1)
+#define S_SPC_CFG_SRC1           8
+#define M_SPC_CFG_SRC1           _SB_MAKEMASK(8, S_SPC_CFG_SRC1)
+#define V_SPC_CFG_SRC1(x)        _SB_MAKEVALUE(x, S_SPC_CFG_SRC1)
+#define G_SPC_CFG_SRC1(x)        _SB_GETVALUE(x, S_SPC_CFG_SRC1, M_SPC_CFG_SRC1)

 
 

-#define S_SPC_CFG_SRC2            16
-#define M_SPC_CFG_SRC2            _SB_MAKEMASK(8, S_SPC_CFG_SRC2)
-#define V_SPC_CFG_SRC2(x)         _SB_MAKEVALUE(x, S_SPC_CFG_SRC2)
-#define G_SPC_CFG_SRC2(x)         _SB_GETVALUE(x, S_SPC_CFG_SRC2, M_SPC_CFG_SRC2)
+#define S_SPC_CFG_SRC2           16
+#define M_SPC_CFG_SRC2           _SB_MAKEMASK(8, S_SPC_CFG_SRC2)
+#define V_SPC_CFG_SRC2(x)        _SB_MAKEVALUE(x, S_SPC_CFG_SRC2)
+#define G_SPC_CFG_SRC2(x)        _SB_GETVALUE(x, S_SPC_CFG_SRC2, M_SPC_CFG_SRC2)

 
 

-#define S_SPC_CFG_SRC3            24
-#define M_SPC_CFG_SRC3            _SB_MAKEMASK(8, S_SPC_CFG_SRC3)
-#define V_SPC_CFG_SRC3(x)         _SB_MAKEVALUE(x, S_SPC_CFG_SRC3)
-#define G_SPC_CFG_SRC3(x)         _SB_GETVALUE(x, S_SPC_CFG_SRC3, M_SPC_CFG_SRC3)
+#define S_SPC_CFG_SRC3           24
+#define M_SPC_CFG_SRC3           _SB_MAKEMASK(8, S_SPC_CFG_SRC3)
+#define V_SPC_CFG_SRC3(x)        _SB_MAKEVALUE(x, S_SPC_CFG_SRC3)
+#define G_SPC_CFG_SRC3(x)        _SB_GETVALUE(x, S_SPC_CFG_SRC3, M_SPC_CFG_SRC3)

 
 #if SIBYTE_HDR_FEATURE_1250_112x
 #define M_SPC_CFG_CLEAR                _SB_MAKEMASK1(32)
 
 #if SIBYTE_HDR_FEATURE_1250_112x
 #define M_SPC_CFG_CLEAR                _SB_MAKEMASK1(32)


@@ -411,58 +411,58 @@
  * Bus Watcher
  */
 
  * Bus Watcher
  */
 

-#define S_SCD_BERR_TID            8
-#define M_SCD_BERR_TID            _SB_MAKEMASK(10, S_SCD_BERR_TID)
-#define V_SCD_BERR_TID(x)         _SB_MAKEVALUE(x, S_SCD_BERR_TID)
-#define G_SCD_BERR_TID(x)         _SB_GETVALUE(x, S_SCD_BERR_TID, M_SCD_BERR_TID)
+#define S_SCD_BERR_TID           8
+#define M_SCD_BERR_TID           _SB_MAKEMASK(10, S_SCD_BERR_TID)
+#define V_SCD_BERR_TID(x)        _SB_MAKEVALUE(x, S_SCD_BERR_TID)
+#define G_SCD_BERR_TID(x)        _SB_GETVALUE(x, S_SCD_BERR_TID, M_SCD_BERR_TID)

 
 

-#define S_SCD_BERR_RID            18
-#define M_SCD_BERR_RID            _SB_MAKEMASK(4, S_SCD_BERR_RID)
-#define V_SCD_BERR_RID(x)         _SB_MAKEVALUE(x, S_SCD_BERR_RID)
-#define G_SCD_BERR_RID(x)         _SB_GETVALUE(x, S_SCD_BERR_RID, M_SCD_BERR_RID)
+#define S_SCD_BERR_RID           18
+#define M_SCD_BERR_RID           _SB_MAKEMASK(4, S_SCD_BERR_RID)
+#define V_SCD_BERR_RID(x)        _SB_MAKEVALUE(x, S_SCD_BERR_RID)
+#define G_SCD_BERR_RID(x)        _SB_GETVALUE(x, S_SCD_BERR_RID, M_SCD_BERR_RID)

 
 

-#define S_SCD_BERR_DCODE          22
-#define M_SCD_BERR_DCODE          _SB_MAKEMASK(3, S_SCD_BERR_DCODE)
-#define V_SCD_BERR_DCODE(x)       _SB_MAKEVALUE(x, S_SCD_BERR_DCODE)
-#define G_SCD_BERR_DCODE(x)       _SB_GETVALUE(x, S_SCD_BERR_DCODE, M_SCD_BERR_DCODE)
+#define S_SCD_BERR_DCODE         22
+#define M_SCD_BERR_DCODE         _SB_MAKEMASK(3, S_SCD_BERR_DCODE)
+#define V_SCD_BERR_DCODE(x)      _SB_MAKEVALUE(x, S_SCD_BERR_DCODE)
+#define G_SCD_BERR_DCODE(x)      _SB_GETVALUE(x, S_SCD_BERR_DCODE, M_SCD_BERR_DCODE)

 
 

-#define M_SCD_BERR_MULTERRS       _SB_MAKEMASK1(30)
+#define M_SCD_BERR_MULTERRS      _SB_MAKEMASK1(30)

 
 
 
 

-#define S_SCD_L2ECC_CORR_D        0
-#define M_SCD_L2ECC_CORR_D        _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_D)
-#define V_SCD_L2ECC_CORR_D(x)     _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_D)
-#define G_SCD_L2ECC_CORR_D(x)     _SB_GETVALUE(x, S_SCD_L2ECC_CORR_D, M_SCD_L2ECC_CORR_D)
+#define S_SCD_L2ECC_CORR_D       0
+#define M_SCD_L2ECC_CORR_D       _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_D)
+#define V_SCD_L2ECC_CORR_D(x)    _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_D)
+#define G_SCD_L2ECC_CORR_D(x)    _SB_GETVALUE(x, S_SCD_L2ECC_CORR_D, M_SCD_L2ECC_CORR_D)

 
 

-#define S_SCD_L2ECC_BAD_D         8
-#define M_SCD_L2ECC_BAD_D         _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_D)
-#define V_SCD_L2ECC_BAD_D(x)      _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_D)
-#define G_SCD_L2ECC_BAD_D(x)      _SB_GETVALUE(x, S_SCD_L2ECC_BAD_D, M_SCD_L2ECC_BAD_D)
+#define S_SCD_L2ECC_BAD_D        8
+#define M_SCD_L2ECC_BAD_D        _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_D)
+#define V_SCD_L2ECC_BAD_D(x)     _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_D)
+#define G_SCD_L2ECC_BAD_D(x)     _SB_GETVALUE(x, S_SCD_L2ECC_BAD_D, M_SCD_L2ECC_BAD_D)

 
 

-#define S_SCD_L2ECC_CORR_T        16
-#define M_SCD_L2ECC_CORR_T        _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_T)
-#define V_SCD_L2ECC_CORR_T(x)     _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_T)
-#define G_SCD_L2ECC_CORR_T(x)     _SB_GETVALUE(x, S_SCD_L2ECC_CORR_T, M_SCD_L2ECC_CORR_T)
+#define S_SCD_L2ECC_CORR_T       16
+#define M_SCD_L2ECC_CORR_T       _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_T)
+#define V_SCD_L2ECC_CORR_T(x)    _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_T)
+#define G_SCD_L2ECC_CORR_T(x)    _SB_GETVALUE(x, S_SCD_L2ECC_CORR_T, M_SCD_L2ECC_CORR_T)

 
 

-#define S_SCD_L2ECC_BAD_T         24
-#define M_SCD_L2ECC_BAD_T         _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_T)
-#define V_SCD_L2ECC_BAD_T(x)      _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_T)
-#define G_SCD_L2ECC_BAD_T(x)      _SB_GETVALUE(x, S_SCD_L2ECC_BAD_T, M_SCD_L2ECC_BAD_T)
+#define S_SCD_L2ECC_BAD_T        24
+#define M_SCD_L2ECC_BAD_T        _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_T)
+#define V_SCD_L2ECC_BAD_T(x)     _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_T)
+#define G_SCD_L2ECC_BAD_T(x)     _SB_GETVALUE(x, S_SCD_L2ECC_BAD_T, M_SCD_L2ECC_BAD_T)

 
 

-#define S_SCD_MEM_ECC_CORR        0
-#define M_SCD_MEM_ECC_CORR        _SB_MAKEMASK(8, S_SCD_MEM_ECC_CORR)
-#define V_SCD_MEM_ECC_CORR(x)     _SB_MAKEVALUE(x, S_SCD_MEM_ECC_CORR)
-#define G_SCD_MEM_ECC_CORR(x)     _SB_GETVALUE(x, S_SCD_MEM_ECC_CORR, M_SCD_MEM_ECC_CORR)
+#define S_SCD_MEM_ECC_CORR       0
+#define M_SCD_MEM_ECC_CORR       _SB_MAKEMASK(8, S_SCD_MEM_ECC_CORR)
+#define V_SCD_MEM_ECC_CORR(x)    _SB_MAKEVALUE(x, S_SCD_MEM_ECC_CORR)
+#define G_SCD_MEM_ECC_CORR(x)    _SB_GETVALUE(x, S_SCD_MEM_ECC_CORR, M_SCD_MEM_ECC_CORR)

 
 

-#define S_SCD_MEM_ECC_BAD         8
-#define M_SCD_MEM_ECC_BAD         _SB_MAKEMASK(8, S_SCD_MEM_ECC_BAD)
-#define V_SCD_MEM_ECC_BAD(x)      _SB_MAKEVALUE(x, S_SCD_MEM_ECC_BAD)
-#define G_SCD_MEM_ECC_BAD(x)      _SB_GETVALUE(x, S_SCD_MEM_ECC_BAD, M_SCD_MEM_ECC_BAD)
+#define S_SCD_MEM_ECC_BAD        8
+#define M_SCD_MEM_ECC_BAD        _SB_MAKEMASK(8, S_SCD_MEM_ECC_BAD)
+#define V_SCD_MEM_ECC_BAD(x)     _SB_MAKEVALUE(x, S_SCD_MEM_ECC_BAD)
+#define G_SCD_MEM_ECC_BAD(x)     _SB_GETVALUE(x, S_SCD_MEM_ECC_BAD, M_SCD_MEM_ECC_BAD)

 
 

-#define S_SCD_MEM_BUSERR          16
-#define M_SCD_MEM_BUSERR          _SB_MAKEMASK(8, S_SCD_MEM_BUSERR)
-#define V_SCD_MEM_BUSERR(x)       _SB_MAKEVALUE(x, S_SCD_MEM_BUSERR)
-#define G_SCD_MEM_BUSERR(x)       _SB_GETVALUE(x, S_SCD_MEM_BUSERR, M_SCD_MEM_BUSERR)
+#define S_SCD_MEM_BUSERR         16
+#define M_SCD_MEM_BUSERR         _SB_MAKEMASK(8, S_SCD_MEM_BUSERR)
+#define V_SCD_MEM_BUSERR(x)      _SB_MAKEVALUE(x, S_SCD_MEM_BUSERR)
+#define G_SCD_MEM_BUSERR(x)      _SB_GETVALUE(x, S_SCD_MEM_BUSERR, M_SCD_MEM_BUSERR)

 
 
 /*
 
 
 /*


@@ -473,28 +473,28 @@
 #define M_ATRAP_INDEX            _SB_MAKEMASK(4, 0)
 #define M_ATRAP_ADDRESS                  _SB_MAKEMASK(40, 0)
 
 #define M_ATRAP_INDEX            _SB_MAKEMASK(4, 0)
 #define M_ATRAP_ADDRESS                  _SB_MAKEMASK(40, 0)
 

-#define S_ATRAP_CFG_CNT            0
-#define M_ATRAP_CFG_CNT            _SB_MAKEMASK(3, S_ATRAP_CFG_CNT)
-#define V_ATRAP_CFG_CNT(x)         _SB_MAKEVALUE(x, S_ATRAP_CFG_CNT)
-#define G_ATRAP_CFG_CNT(x)         _SB_GETVALUE(x, S_ATRAP_CFG_CNT, M_ATRAP_CFG_CNT)
+#define S_ATRAP_CFG_CNT                   0
+#define M_ATRAP_CFG_CNT                   _SB_MAKEMASK(3, S_ATRAP_CFG_CNT)
+#define V_ATRAP_CFG_CNT(x)        _SB_MAKEVALUE(x, S_ATRAP_CFG_CNT)
+#define G_ATRAP_CFG_CNT(x)        _SB_GETVALUE(x, S_ATRAP_CFG_CNT, M_ATRAP_CFG_CNT)

 
 #define M_ATRAP_CFG_WRITE         _SB_MAKEMASK1(3)
 
 #define M_ATRAP_CFG_WRITE         _SB_MAKEMASK1(3)

-#define M_ATRAP_CFG_ALL                   _SB_MAKEMASK1(4)
-#define M_ATRAP_CFG_INV                   _SB_MAKEMASK1(5)
+#define M_ATRAP_CFG_ALL                   _SB_MAKEMASK1(4)
+#define M_ATRAP_CFG_INV                   _SB_MAKEMASK1(5)

 #define M_ATRAP_CFG_USESRC        _SB_MAKEMASK1(6)
 #define M_ATRAP_CFG_SRCINV        _SB_MAKEMASK1(7)
 
 #define M_ATRAP_CFG_USESRC        _SB_MAKEMASK1(6)
 #define M_ATRAP_CFG_SRCINV        _SB_MAKEMASK1(7)
 

-#define S_ATRAP_CFG_AGENTID     8
-#define M_ATRAP_CFG_AGENTID     _SB_MAKEMASK(4, S_ATRAP_CFG_AGENTID)
-#define V_ATRAP_CFG_AGENTID(x)  _SB_MAKEVALUE(x, S_ATRAP_CFG_AGENTID)
-#define G_ATRAP_CFG_AGENTID(x)  _SB_GETVALUE(x, S_ATRAP_CFG_AGENTID, M_ATRAP_CFG_AGENTID)
+#define S_ATRAP_CFG_AGENTID    8
+#define M_ATRAP_CFG_AGENTID    _SB_MAKEMASK(4, S_ATRAP_CFG_AGENTID)
+#define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x, S_ATRAP_CFG_AGENTID)
+#define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x, S_ATRAP_CFG_AGENTID, M_ATRAP_CFG_AGENTID)

 
 #define K_BUS_AGENT_CPU0       0
 #define K_BUS_AGENT_CPU1       1
 #define K_BUS_AGENT_IOB0       2
 #define K_BUS_AGENT_IOB1       3
 
 #define K_BUS_AGENT_CPU0       0
 #define K_BUS_AGENT_CPU1       1
 #define K_BUS_AGENT_IOB0       2
 #define K_BUS_AGENT_IOB1       3

-#define K_BUS_AGENT_SCD        4
-#define K_BUS_AGENT_L2C        6
+#define K_BUS_AGENT_SCD 4
+#define K_BUS_AGENT_L2C 6

 #define K_BUS_AGENT_MC 7
 
 #define S_ATRAP_CFG_CATTR     12
 #define K_BUS_AGENT_MC 7
 
 #define S_ATRAP_CFG_CATTR     12


@@ -503,13 +503,13 @@
 #define G_ATRAP_CFG_CATTR(x)  _SB_GETVALUE(x, S_ATRAP_CFG_CATTR, M_ATRAP_CFG_CATTR)
 
 #define K_ATRAP_CFG_CATTR_IGNORE       0
 #define G_ATRAP_CFG_CATTR(x)  _SB_GETVALUE(x, S_ATRAP_CFG_CATTR, M_ATRAP_CFG_CATTR)
 
 #define K_ATRAP_CFG_CATTR_IGNORE       0

-#define K_ATRAP_CFG_CATTR_UNC          1
+#define K_ATRAP_CFG_CATTR_UNC          1

 #define K_ATRAP_CFG_CATTR_CACHEABLE    2
 #define K_ATRAP_CFG_CATTR_CACHEABLE    2

-#define K_ATRAP_CFG_CATTR_NONCOH       3
+#define K_ATRAP_CFG_CATTR_NONCOH       3

 #define K_ATRAP_CFG_CATTR_COHERENT     4
 #define K_ATRAP_CFG_CATTR_NOTUNC       5
 #define K_ATRAP_CFG_CATTR_NOTNONCOH    6
 #define K_ATRAP_CFG_CATTR_COHERENT     4
 #define K_ATRAP_CFG_CATTR_NOTUNC       5
 #define K_ATRAP_CFG_CATTR_NOTNONCOH    6

-#define K_ATRAP_CFG_CATTR_NOTCOHERENT   7
+#define K_ATRAP_CFG_CATTR_NOTCOHERENT  7

 
 #endif /* 1250/112x */
 
 
 #endif /* 1250/112x */
 


@@ -517,16 +517,16 @@
  * Trace Buffer Config register
  */
 
  * Trace Buffer Config register
  */
 

-#define M_SCD_TRACE_CFG_RESET           _SB_MAKEMASK1(0)
-#define M_SCD_TRACE_CFG_START_READ      _SB_MAKEMASK1(1)
-#define M_SCD_TRACE_CFG_START           _SB_MAKEMASK1(2)
-#define M_SCD_TRACE_CFG_STOP            _SB_MAKEMASK1(3)
-#define M_SCD_TRACE_CFG_FREEZE          _SB_MAKEMASK1(4)
-#define M_SCD_TRACE_CFG_FREEZE_FULL     _SB_MAKEMASK1(5)
-#define M_SCD_TRACE_CFG_DEBUG_FULL      _SB_MAKEMASK1(6)
-#define M_SCD_TRACE_CFG_FULL            _SB_MAKEMASK1(7)
+#define M_SCD_TRACE_CFG_RESET          _SB_MAKEMASK1(0)
+#define M_SCD_TRACE_CFG_START_READ     _SB_MAKEMASK1(1)
+#define M_SCD_TRACE_CFG_START          _SB_MAKEMASK1(2)
+#define M_SCD_TRACE_CFG_STOP           _SB_MAKEMASK1(3)
+#define M_SCD_TRACE_CFG_FREEZE         _SB_MAKEMASK1(4)
+#define M_SCD_TRACE_CFG_FREEZE_FULL    _SB_MAKEMASK1(5)
+#define M_SCD_TRACE_CFG_DEBUG_FULL     _SB_MAKEMASK1(6)
+#define M_SCD_TRACE_CFG_FULL           _SB_MAKEMASK1(7)

 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)

-#define M_SCD_TRACE_CFG_FORCECNT        _SB_MAKEMASK1(8)
+#define M_SCD_TRACE_CFG_FORCECNT       _SB_MAKEMASK1(8)

 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 /*
 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 /*


@@ -534,121 +534,121 @@
  * a slightly different place in the register.
  */
 #if SIBYTE_HDR_FEATURE_1250_112x
  * a slightly different place in the register.
  */
 #if SIBYTE_HDR_FEATURE_1250_112x

-#define S_SCD_TRACE_CFG_CUR_ADDR        10
+#define S_SCD_TRACE_CFG_CUR_ADDR       10

 #else
 #if SIBYTE_HDR_FEATURE_CHIP(1480)
 #else
 #if SIBYTE_HDR_FEATURE_CHIP(1480)

-#define S_SCD_TRACE_CFG_CUR_ADDR        24
+#define S_SCD_TRACE_CFG_CUR_ADDR       24

 #endif /* 1480 */
 #endif /* 1480 */

-#endif  /* 1250/112x */
+#endif /* 1250/112x */

 
 

-#define M_SCD_TRACE_CFG_CUR_ADDR        _SB_MAKEMASK(8, S_SCD_TRACE_CFG_CUR_ADDR)
-#define V_SCD_TRACE_CFG_CUR_ADDR(x)     _SB_MAKEVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR)
-#define G_SCD_TRACE_CFG_CUR_ADDR(x)     _SB_GETVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR, M_SCD_TRACE_CFG_CUR_ADDR)
+#define M_SCD_TRACE_CFG_CUR_ADDR       _SB_MAKEMASK(8, S_SCD_TRACE_CFG_CUR_ADDR)
+#define V_SCD_TRACE_CFG_CUR_ADDR(x)    _SB_MAKEVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR)
+#define G_SCD_TRACE_CFG_CUR_ADDR(x)    _SB_GETVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR, M_SCD_TRACE_CFG_CUR_ADDR)

 
 /*
  * Trace Event registers
  */
 
 
 /*
  * Trace Event registers
  */
 

-#define S_SCD_TREVT_ADDR_MATCH          0
-#define M_SCD_TREVT_ADDR_MATCH          _SB_MAKEMASK(4, S_SCD_TREVT_ADDR_MATCH)
-#define V_SCD_TREVT_ADDR_MATCH(x)       _SB_MAKEVALUE(x, S_SCD_TREVT_ADDR_MATCH)
-#define G_SCD_TREVT_ADDR_MATCH(x)       _SB_GETVALUE(x, S_SCD_TREVT_ADDR_MATCH, M_SCD_TREVT_ADDR_MATCH)
-
-#define M_SCD_TREVT_REQID_MATCH         _SB_MAKEMASK1(4)
-#define M_SCD_TREVT_DATAID_MATCH        _SB_MAKEMASK1(5)
-#define M_SCD_TREVT_RESPID_MATCH        _SB_MAKEMASK1(6)
-#define M_SCD_TREVT_INTERRUPT           _SB_MAKEMASK1(7)
-#define M_SCD_TREVT_DEBUG_PIN           _SB_MAKEMASK1(9)
-#define M_SCD_TREVT_WRITE               _SB_MAKEMASK1(10)
-#define M_SCD_TREVT_READ                _SB_MAKEMASK1(11)
-
-#define S_SCD_TREVT_REQID               12
-#define M_SCD_TREVT_REQID               _SB_MAKEMASK(4, S_SCD_TREVT_REQID)
-#define V_SCD_TREVT_REQID(x)            _SB_MAKEVALUE(x, S_SCD_TREVT_REQID)
-#define G_SCD_TREVT_REQID(x)            _SB_GETVALUE(x, S_SCD_TREVT_REQID, M_SCD_TREVT_REQID)
-
-#define S_SCD_TREVT_RESPID              16
-#define M_SCD_TREVT_RESPID              _SB_MAKEMASK(4, S_SCD_TREVT_RESPID)
-#define V_SCD_TREVT_RESPID(x)           _SB_MAKEVALUE(x, S_SCD_TREVT_RESPID)
-#define G_SCD_TREVT_RESPID(x)           _SB_GETVALUE(x, S_SCD_TREVT_RESPID, M_SCD_TREVT_RESPID)
-
-#define S_SCD_TREVT_DATAID              20
-#define M_SCD_TREVT_DATAID              _SB_MAKEMASK(4, S_SCD_TREVT_DATAID)
-#define V_SCD_TREVT_DATAID(x)           _SB_MAKEVALUE(x, S_SCD_TREVT_DATAID)
-#define G_SCD_TREVT_DATAID(x)           _SB_GETVALUE(x, S_SCD_TREVT_DATAID, M_SCD_TREVT_DATID)
-
-#define S_SCD_TREVT_COUNT               24
-#define M_SCD_TREVT_COUNT               _SB_MAKEMASK(8, S_SCD_TREVT_COUNT)
-#define V_SCD_TREVT_COUNT(x)            _SB_MAKEVALUE(x, S_SCD_TREVT_COUNT)
-#define G_SCD_TREVT_COUNT(x)            _SB_GETVALUE(x, S_SCD_TREVT_COUNT, M_SCD_TREVT_COUNT)
+#define S_SCD_TREVT_ADDR_MATCH         0
+#define M_SCD_TREVT_ADDR_MATCH         _SB_MAKEMASK(4, S_SCD_TREVT_ADDR_MATCH)
+#define V_SCD_TREVT_ADDR_MATCH(x)      _SB_MAKEVALUE(x, S_SCD_TREVT_ADDR_MATCH)
+#define G_SCD_TREVT_ADDR_MATCH(x)      _SB_GETVALUE(x, S_SCD_TREVT_ADDR_MATCH, M_SCD_TREVT_ADDR_MATCH)
+
+#define M_SCD_TREVT_REQID_MATCH                _SB_MAKEMASK1(4)
+#define M_SCD_TREVT_DATAID_MATCH       _SB_MAKEMASK1(5)
+#define M_SCD_TREVT_RESPID_MATCH       _SB_MAKEMASK1(6)
+#define M_SCD_TREVT_INTERRUPT          _SB_MAKEMASK1(7)
+#define M_SCD_TREVT_DEBUG_PIN          _SB_MAKEMASK1(9)
+#define M_SCD_TREVT_WRITE              _SB_MAKEMASK1(10)
+#define M_SCD_TREVT_READ               _SB_MAKEMASK1(11)
+
+#define S_SCD_TREVT_REQID              12
+#define M_SCD_TREVT_REQID              _SB_MAKEMASK(4, S_SCD_TREVT_REQID)
+#define V_SCD_TREVT_REQID(x)           _SB_MAKEVALUE(x, S_SCD_TREVT_REQID)
+#define G_SCD_TREVT_REQID(x)           _SB_GETVALUE(x, S_SCD_TREVT_REQID, M_SCD_TREVT_REQID)
+
+#define S_SCD_TREVT_RESPID             16
+#define M_SCD_TREVT_RESPID             _SB_MAKEMASK(4, S_SCD_TREVT_RESPID)
+#define V_SCD_TREVT_RESPID(x)          _SB_MAKEVALUE(x, S_SCD_TREVT_RESPID)
+#define G_SCD_TREVT_RESPID(x)          _SB_GETVALUE(x, S_SCD_TREVT_RESPID, M_SCD_TREVT_RESPID)
+
+#define S_SCD_TREVT_DATAID             20
+#define M_SCD_TREVT_DATAID             _SB_MAKEMASK(4, S_SCD_TREVT_DATAID)
+#define V_SCD_TREVT_DATAID(x)          _SB_MAKEVALUE(x, S_SCD_TREVT_DATAID)
+#define G_SCD_TREVT_DATAID(x)          _SB_GETVALUE(x, S_SCD_TREVT_DATAID, M_SCD_TREVT_DATID)
+
+#define S_SCD_TREVT_COUNT              24
+#define M_SCD_TREVT_COUNT              _SB_MAKEMASK(8, S_SCD_TREVT_COUNT)
+#define V_SCD_TREVT_COUNT(x)           _SB_MAKEVALUE(x, S_SCD_TREVT_COUNT)
+#define G_SCD_TREVT_COUNT(x)           _SB_GETVALUE(x, S_SCD_TREVT_COUNT, M_SCD_TREVT_COUNT)

 
 /*
  * Trace Sequence registers
  */
 
 
 /*
  * Trace Sequence registers
  */
 

-#define S_SCD_TRSEQ_EVENT4              0
-#define M_SCD_TRSEQ_EVENT4              _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT4)
-#define V_SCD_TRSEQ_EVENT4(x)           _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT4)
-#define G_SCD_TRSEQ_EVENT4(x)           _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT4, M_SCD_TRSEQ_EVENT4)
-
-#define S_SCD_TRSEQ_EVENT3              4
-#define M_SCD_TRSEQ_EVENT3              _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT3)
-#define V_SCD_TRSEQ_EVENT3(x)           _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT3)
-#define G_SCD_TRSEQ_EVENT3(x)           _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT3, M_SCD_TRSEQ_EVENT3)
-
-#define S_SCD_TRSEQ_EVENT2              8
-#define M_SCD_TRSEQ_EVENT2              _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT2)
-#define V_SCD_TRSEQ_EVENT2(x)           _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT2)
-#define G_SCD_TRSEQ_EVENT2(x)           _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT2, M_SCD_TRSEQ_EVENT2)
-
-#define S_SCD_TRSEQ_EVENT1              12
-#define M_SCD_TRSEQ_EVENT1              _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT1)
-#define V_SCD_TRSEQ_EVENT1(x)           _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT1)
-#define G_SCD_TRSEQ_EVENT1(x)           _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT1, M_SCD_TRSEQ_EVENT1)
-
-#define K_SCD_TRSEQ_E0                  0
-#define K_SCD_TRSEQ_E1                  1
-#define K_SCD_TRSEQ_E2                  2
-#define K_SCD_TRSEQ_E3                  3
-#define K_SCD_TRSEQ_E0_E1               4
-#define K_SCD_TRSEQ_E1_E2               5
-#define K_SCD_TRSEQ_E2_E3               6
-#define K_SCD_TRSEQ_E0_E1_E2            7
-#define K_SCD_TRSEQ_E0_E1_E2_E3         8
-#define K_SCD_TRSEQ_E0E1                9
-#define K_SCD_TRSEQ_E0E1E2              10
-#define K_SCD_TRSEQ_E0E1E2E3            11
-#define K_SCD_TRSEQ_E0E1_E2             12
-#define K_SCD_TRSEQ_E0E1_E2E3           13
-#define K_SCD_TRSEQ_E0E1_E2_E3          14
-#define K_SCD_TRSEQ_IGNORED             15
-
-#define K_SCD_TRSEQ_TRIGGER_ALL         (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \
-                                         V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \
-                                         V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \
-                                         V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED))
-
-#define S_SCD_TRSEQ_FUNCTION            16
-#define M_SCD_TRSEQ_FUNCTION            _SB_MAKEMASK(4, S_SCD_TRSEQ_FUNCTION)
-#define V_SCD_TRSEQ_FUNCTION(x)         _SB_MAKEVALUE(x, S_SCD_TRSEQ_FUNCTION)
-#define G_SCD_TRSEQ_FUNCTION(x)         _SB_GETVALUE(x, S_SCD_TRSEQ_FUNCTION, M_SCD_TRSEQ_FUNCTION)
-
-#define K_SCD_TRSEQ_FUNC_NOP            0
-#define K_SCD_TRSEQ_FUNC_START          1
-#define K_SCD_TRSEQ_FUNC_STOP           2
-#define K_SCD_TRSEQ_FUNC_FREEZE         3
-
-#define V_SCD_TRSEQ_FUNC_NOP            V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP)
-#define V_SCD_TRSEQ_FUNC_START          V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START)
-#define V_SCD_TRSEQ_FUNC_STOP           V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP)
-#define V_SCD_TRSEQ_FUNC_FREEZE         V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE)
-
-#define M_SCD_TRSEQ_ASAMPLE             _SB_MAKEMASK1(18)
-#define M_SCD_TRSEQ_DSAMPLE             _SB_MAKEMASK1(19)
-#define M_SCD_TRSEQ_DEBUGPIN            _SB_MAKEMASK1(20)
-#define M_SCD_TRSEQ_DEBUGCPU            _SB_MAKEMASK1(21)
-#define M_SCD_TRSEQ_CLEARUSE            _SB_MAKEMASK1(22)
-#define M_SCD_TRSEQ_ALLD_A              _SB_MAKEMASK1(23)
-#define M_SCD_TRSEQ_ALL_A               _SB_MAKEMASK1(24)
+#define S_SCD_TRSEQ_EVENT4             0
+#define M_SCD_TRSEQ_EVENT4             _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT4)
+#define V_SCD_TRSEQ_EVENT4(x)          _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT4)
+#define G_SCD_TRSEQ_EVENT4(x)          _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT4, M_SCD_TRSEQ_EVENT4)
+
+#define S_SCD_TRSEQ_EVENT3             4
+#define M_SCD_TRSEQ_EVENT3             _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT3)
+#define V_SCD_TRSEQ_EVENT3(x)          _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT3)
+#define G_SCD_TRSEQ_EVENT3(x)          _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT3, M_SCD_TRSEQ_EVENT3)
+
+#define S_SCD_TRSEQ_EVENT2             8
+#define M_SCD_TRSEQ_EVENT2             _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT2)
+#define V_SCD_TRSEQ_EVENT2(x)          _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT2)
+#define G_SCD_TRSEQ_EVENT2(x)          _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT2, M_SCD_TRSEQ_EVENT2)
+
+#define S_SCD_TRSEQ_EVENT1             12
+#define M_SCD_TRSEQ_EVENT1             _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT1)
+#define V_SCD_TRSEQ_EVENT1(x)          _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT1)
+#define G_SCD_TRSEQ_EVENT1(x)          _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT1, M_SCD_TRSEQ_EVENT1)
+
+#define K_SCD_TRSEQ_E0                 0
+#define K_SCD_TRSEQ_E1                 1
+#define K_SCD_TRSEQ_E2                 2
+#define K_SCD_TRSEQ_E3                 3
+#define K_SCD_TRSEQ_E0_E1              4
+#define K_SCD_TRSEQ_E1_E2              5
+#define K_SCD_TRSEQ_E2_E3              6
+#define K_SCD_TRSEQ_E0_E1_E2           7
+#define K_SCD_TRSEQ_E0_E1_E2_E3                8
+#define K_SCD_TRSEQ_E0E1               9
+#define K_SCD_TRSEQ_E0E1E2             10
+#define K_SCD_TRSEQ_E0E1E2E3           11
+#define K_SCD_TRSEQ_E0E1_E2            12
+#define K_SCD_TRSEQ_E0E1_E2E3          13
+#define K_SCD_TRSEQ_E0E1_E2_E3         14
+#define K_SCD_TRSEQ_IGNORED            15
+
+#define K_SCD_TRSEQ_TRIGGER_ALL                (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \
+                                        V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \
+                                        V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \
+                                        V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED))
+
+#define S_SCD_TRSEQ_FUNCTION           16
+#define M_SCD_TRSEQ_FUNCTION           _SB_MAKEMASK(4, S_SCD_TRSEQ_FUNCTION)
+#define V_SCD_TRSEQ_FUNCTION(x)                _SB_MAKEVALUE(x, S_SCD_TRSEQ_FUNCTION)
+#define G_SCD_TRSEQ_FUNCTION(x)                _SB_GETVALUE(x, S_SCD_TRSEQ_FUNCTION, M_SCD_TRSEQ_FUNCTION)
+
+#define K_SCD_TRSEQ_FUNC_NOP           0
+#define K_SCD_TRSEQ_FUNC_START         1
+#define K_SCD_TRSEQ_FUNC_STOP          2
+#define K_SCD_TRSEQ_FUNC_FREEZE                3
+
+#define V_SCD_TRSEQ_FUNC_NOP           V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP)
+#define V_SCD_TRSEQ_FUNC_START         V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START)
+#define V_SCD_TRSEQ_FUNC_STOP          V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP)
+#define V_SCD_TRSEQ_FUNC_FREEZE                V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE)
+
+#define M_SCD_TRSEQ_ASAMPLE            _SB_MAKEMASK1(18)
+#define M_SCD_TRSEQ_DSAMPLE            _SB_MAKEMASK1(19)
+#define M_SCD_TRSEQ_DEBUGPIN           _SB_MAKEMASK1(20)
+#define M_SCD_TRSEQ_DEBUGCPU           _SB_MAKEMASK1(21)
+#define M_SCD_TRSEQ_CLEARUSE           _SB_MAKEMASK1(22)
+#define M_SCD_TRSEQ_ALLD_A             _SB_MAKEMASK1(23)
+#define M_SCD_TRSEQ_ALL_A              _SB_MAKEMASK1(24)

 
 #endif
 
 #endif

diff --git a/arch/mips/include/asm/sibyte/sb1250_smbus.h b/arch/mips/include/asm/sibyte/sb1250_smbus.h
index 128d6b75b81980c585305c92ee611839b071bf99..3cb73e89bbbcf05d48ab2cd7e3ed461514f5d7dd 100644 (file)
--- a/arch/mips/include/asm/sibyte/sb1250_smbus.h
+++ b/arch/mips/include/asm/sibyte/sb1250_smbus.h
@@ -1,7 +1,7 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
     *
 /*  *********************************************************************
     *  SB1250 Board Support Package
     *

-    *  SMBUS Constants                          File: sb1250_smbus.h
+    *  SMBUS Constants                         File: sb1250_smbus.h

     *
     *  This module contains constants and macros useful for
     *  manipulating the SB1250's SMbus devices.
     *
     *  This module contains constants and macros useful for
     *  manipulating the SB1250's SMbus devices.


@@ -40,83 +40,83 @@
  * SMBus Clock Frequency Register (Table 14-2)
  */
 
  * SMBus Clock Frequency Register (Table 14-2)
  */
 

-#define S_SMB_FREQ_DIV              0
-#define M_SMB_FREQ_DIV              _SB_MAKEMASK(13, S_SMB_FREQ_DIV)
-#define V_SMB_FREQ_DIV(x)           _SB_MAKEVALUE(x, S_SMB_FREQ_DIV)
+#define S_SMB_FREQ_DIV             0
+#define M_SMB_FREQ_DIV             _SB_MAKEMASK(13, S_SMB_FREQ_DIV)
+#define V_SMB_FREQ_DIV(x)          _SB_MAKEVALUE(x, S_SMB_FREQ_DIV)

 
 #define K_SMB_FREQ_400KHZ          0x1F
 #define K_SMB_FREQ_100KHZ          0x7D
 #define K_SMB_FREQ_10KHZ           1250
 
 
 #define K_SMB_FREQ_400KHZ          0x1F
 #define K_SMB_FREQ_100KHZ          0x7D
 #define K_SMB_FREQ_10KHZ           1250
 

-#define S_SMB_CMD                   0
-#define M_SMB_CMD                   _SB_MAKEMASK(8, S_SMB_CMD)
-#define V_SMB_CMD(x)                _SB_MAKEVALUE(x, S_SMB_CMD)
+#define S_SMB_CMD                  0
+#define M_SMB_CMD                  _SB_MAKEMASK(8, S_SMB_CMD)
+#define V_SMB_CMD(x)               _SB_MAKEVALUE(x, S_SMB_CMD)

 
 /*
  * SMBus control register (Table 14-4)
  */
 
 
 /*
  * SMBus control register (Table 14-4)
  */
 

-#define M_SMB_ERR_INTR              _SB_MAKEMASK1(0)
-#define M_SMB_FINISH_INTR           _SB_MAKEMASK1(1)
+#define M_SMB_ERR_INTR             _SB_MAKEMASK1(0)
+#define M_SMB_FINISH_INTR          _SB_MAKEMASK1(1)

 
 

-#define S_SMB_DATA_OUT              4
-#define M_SMB_DATA_OUT              _SB_MAKEMASK1(S_SMB_DATA_OUT)
-#define V_SMB_DATA_OUT(x)           _SB_MAKEVALUE(x, S_SMB_DATA_OUT)
+#define S_SMB_DATA_OUT             4
+#define M_SMB_DATA_OUT             _SB_MAKEMASK1(S_SMB_DATA_OUT)
+#define V_SMB_DATA_OUT(x)          _SB_MAKEVALUE(x, S_SMB_DATA_OUT)

 
 

-#define M_SMB_DATA_DIR              _SB_MAKEMASK1(5)
-#define M_SMB_DATA_DIR_OUTPUT       M_SMB_DATA_DIR
-#define M_SMB_CLK_OUT               _SB_MAKEMASK1(6)
-#define M_SMB_DIRECT_ENABLE         _SB_MAKEMASK1(7)
+#define M_SMB_DATA_DIR             _SB_MAKEMASK1(5)
+#define M_SMB_DATA_DIR_OUTPUT      M_SMB_DATA_DIR
+#define M_SMB_CLK_OUT              _SB_MAKEMASK1(6)
+#define M_SMB_DIRECT_ENABLE        _SB_MAKEMASK1(7)

 
 /*
  * SMBus status registers (Table 14-5)
  */
 
 
 /*
  * SMBus status registers (Table 14-5)
  */
 

-#define M_SMB_BUSY                  _SB_MAKEMASK1(0)
-#define M_SMB_ERROR                 _SB_MAKEMASK1(1)
-#define M_SMB_ERROR_TYPE            _SB_MAKEMASK1(2)
+#define M_SMB_BUSY                 _SB_MAKEMASK1(0)
+#define M_SMB_ERROR                _SB_MAKEMASK1(1)
+#define M_SMB_ERROR_TYPE           _SB_MAKEMASK1(2)

 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 
 #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)

-#define S_SMB_SCL_IN                5
-#define M_SMB_SCL_IN                _SB_MAKEMASK1(S_SMB_SCL_IN)
-#define V_SMB_SCL_IN(x)             _SB_MAKEVALUE(x, S_SMB_SCL_IN)
-#define G_SMB_SCL_IN(x)             _SB_GETVALUE(x, S_SMB_SCL_IN, M_SMB_SCL_IN)
+#define S_SMB_SCL_IN               5
+#define M_SMB_SCL_IN               _SB_MAKEMASK1(S_SMB_SCL_IN)
+#define V_SMB_SCL_IN(x)                    _SB_MAKEVALUE(x, S_SMB_SCL_IN)
+#define G_SMB_SCL_IN(x)                    _SB_GETVALUE(x, S_SMB_SCL_IN, M_SMB_SCL_IN)

 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 
 #endif /* 1250 PASS3 || 112x PASS1 || 1480 */
 

-#define S_SMB_REF                   6
-#define M_SMB_REF                   _SB_MAKEMASK1(S_SMB_REF)
-#define V_SMB_REF(x)                _SB_MAKEVALUE(x, S_SMB_REF)
-#define G_SMB_REF(x)                _SB_GETVALUE(x, S_SMB_REF, M_SMB_REF)
+#define S_SMB_REF                  6
+#define M_SMB_REF                  _SB_MAKEMASK1(S_SMB_REF)
+#define V_SMB_REF(x)               _SB_MAKEVALUE(x, S_SMB_REF)
+#define G_SMB_REF(x)               _SB_GETVALUE(x, S_SMB_REF, M_SMB_REF)

 
 

-#define S_SMB_DATA_IN               7
-#define M_SMB_DATA_IN               _SB_MAKEMASK1(S_SMB_DATA_IN)
-#define V_SMB_DATA_IN(x)            _SB_MAKEVALUE(x, S_SMB_DATA_IN)
-#define G_SMB_DATA_IN(x)            _SB_GETVALUE(x, S_SMB_DATA_IN, M_SMB_DATA_IN)
+#define S_SMB_DATA_IN              7
+#define M_SMB_DATA_IN              _SB_MAKEMASK1(S_SMB_DATA_IN)
+#define V_SMB_DATA_IN(x)           _SB_MAKEVALUE(x, S_SMB_DATA_IN)
+#define G_SMB_DATA_IN(x)           _SB_GETVALUE(x, S_SMB_DATA_IN, M_SMB_DATA_IN)

 
 /*
  * SMBus Start/Command registers (Table 14-9)
  */
 
 
 /*
  * SMBus Start/Command registers (Table 14-9)
  */
 

-#define S_SMB_ADDR                  0
-#define M_SMB_ADDR                  _SB_MAKEMASK(7, S_SMB_ADDR)
-#define V_SMB_ADDR(x)               _SB_MAKEVALUE(x, S_SMB_ADDR)
-#define G_SMB_ADDR(x)               _SB_GETVALUE(x, S_SMB_ADDR, M_SMB_ADDR)
+#define S_SMB_ADDR                 0
+#define M_SMB_ADDR                 _SB_MAKEMASK(7, S_SMB_ADDR)
+#define V_SMB_ADDR(x)              _SB_MAKEVALUE(x, S_SMB_ADDR)
+#define G_SMB_ADDR(x)              _SB_GETVALUE(x, S_SMB_ADDR, M_SMB_ADDR)

 
 

-#define M_SMB_QDATA                 _SB_MAKEMASK1(7)
+#define M_SMB_QDATA                _SB_MAKEMASK1(7)

 
 

-#define S_SMB_TT                    8
-#define M_SMB_TT                    _SB_MAKEMASK(3, S_SMB_TT)
-#define V_SMB_TT(x)                 _SB_MAKEVALUE(x, S_SMB_TT)
-#define G_SMB_TT(x)                 _SB_GETVALUE(x, S_SMB_TT, M_SMB_TT)
+#define S_SMB_TT                   8
+#define M_SMB_TT                   _SB_MAKEMASK(3, S_SMB_TT)
+#define V_SMB_TT(x)                _SB_MAKEVALUE(x, S_SMB_TT)
+#define G_SMB_TT(x)                _SB_GETVALUE(x, S_SMB_TT, M_SMB_TT)

 
 

-#define K_SMB_TT_WR1BYTE            0
-#define K_SMB_TT_WR2BYTE            1
-#define K_SMB_TT_WR3BYTE            2
-#define K_SMB_TT_CMD_RD1BYTE        3
-#define K_SMB_TT_CMD_RD2BYTE        4
-#define K_SMB_TT_RD1BYTE            5
-#define K_SMB_TT_QUICKCMD           6
-#define K_SMB_TT_EEPROMREAD         7
+#define K_SMB_TT_WR1BYTE           0
+#define K_SMB_TT_WR2BYTE           1
+#define K_SMB_TT_WR3BYTE           2
+#define K_SMB_TT_CMD_RD1BYTE       3
+#define K_SMB_TT_CMD_RD2BYTE       4
+#define K_SMB_TT_RD1BYTE           5
+#define K_SMB_TT_QUICKCMD          6
+#define K_SMB_TT_EEPROMREAD        7

 
 #define V_SMB_TT_WR1BYTE           V_SMB_TT(K_SMB_TT_WR1BYTE)
 #define V_SMB_TT_WR2BYTE           V_SMB_TT(K_SMB_TT_WR2BYTE)
 
 #define V_SMB_TT_WR1BYTE           V_SMB_TT(K_SMB_TT_WR1BYTE)
 #define V_SMB_TT_WR2BYTE           V_SMB_TT(K_SMB_TT_WR2BYTE)


@@ -127,51 +127,51 @@
 #define V_SMB_TT_QUICKCMD          V_SMB_TT(K_SMB_TT_QUICKCMD)
 #define V_SMB_TT_EEPROMREAD        V_SMB_TT(K_SMB_TT_EEPROMREAD)
 
 #define V_SMB_TT_QUICKCMD          V_SMB_TT(K_SMB_TT_QUICKCMD)
 #define V_SMB_TT_EEPROMREAD        V_SMB_TT(K_SMB_TT_EEPROMREAD)
 

-#define M_SMB_PEC                   _SB_MAKEMASK1(15)
+#define M_SMB_PEC                  _SB_MAKEMASK1(15)

 
 /*
  * SMBus Data Register (Table 14-6) and SMBus Extra Register (Table 14-7)
  */
 
 
 /*
  * SMBus Data Register (Table 14-6) and SMBus Extra Register (Table 14-7)
  */
 

-#define S_SMB_LB                    0
-#define M_SMB_LB                    _SB_MAKEMASK(8, S_SMB_LB)
-#define V_SMB_LB(x)                 _SB_MAKEVALUE(x, S_SMB_LB)
+#define S_SMB_LB                   0
+#define M_SMB_LB                   _SB_MAKEMASK(8, S_SMB_LB)
+#define V_SMB_LB(x)                _SB_MAKEVALUE(x, S_SMB_LB)

 
 

-#define S_SMB_MB                    8
-#define M_SMB_MB                    _SB_MAKEMASK(8, S_SMB_MB)
-#define V_SMB_MB(x)                 _SB_MAKEVALUE(x, S_SMB_MB)
+#define S_SMB_MB                   8
+#define M_SMB_MB                   _SB_MAKEMASK(8, S_SMB_MB)
+#define V_SMB_MB(x)                _SB_MAKEVALUE(x, S_SMB_MB)

 
 
 /*
  * SMBus Packet Error Check register (Table 14-8)
  */
 
 
 
 /*
  * SMBus Packet Error Check register (Table 14-8)
  */
 

-#define S_SPEC_PEC                  0
-#define M_SPEC_PEC                  _SB_MAKEMASK(8, S_SPEC_PEC)
-#define V_SPEC_MB(x)                _SB_MAKEVALUE(x, S_SPEC_PEC)
+#define S_SPEC_PEC                 0
+#define M_SPEC_PEC                 _SB_MAKEMASK(8, S_SPEC_PEC)
+#define V_SPEC_MB(x)               _SB_MAKEVALUE(x, S_SPEC_PEC)

 
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 
 
 
 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
 

-#define S_SMB_CMDH                  8
-#define M_SMB_CMDH                  _SB_MAKEMASK(8, S_SMB_CMDH)
-#define V_SMB_CMDH(x)               _SB_MAKEVALUE(x, S_SMB_CMDH)
+#define S_SMB_CMDH                 8
+#define M_SMB_CMDH                 _SB_MAKEMASK(8, S_SMB_CMDH)
+#define V_SMB_CMDH(x)              _SB_MAKEVALUE(x, S_SMB_CMDH)

 
 #define M_SMB_EXTEND               _SB_MAKEMASK1(14)
 
 
 #define M_SMB_EXTEND               _SB_MAKEMASK1(14)
 

-#define S_SMB_DFMT                  8
-#define M_SMB_DFMT                  _SB_MAKEMASK(3, S_SMB_DFMT)
-#define V_SMB_DFMT(x)               _SB_MAKEVALUE(x, S_SMB_DFMT)
-#define G_SMB_DFMT(x)               _SB_GETVALUE(x, S_SMB_DFMT, M_SMB_DFMT)
+#define S_SMB_DFMT                 8
+#define M_SMB_DFMT                 _SB_MAKEMASK(3, S_SMB_DFMT)
+#define V_SMB_DFMT(x)              _SB_MAKEVALUE(x, S_SMB_DFMT)
+#define G_SMB_DFMT(x)              _SB_GETVALUE(x, S_SMB_DFMT, M_SMB_DFMT)

 
 

-#define K_SMB_DFMT_1BYTE            0
-#define K_SMB_DFMT_2BYTE            1
-#define K_SMB_DFMT_3BYTE            2
-#define K_SMB_DFMT_4BYTE            3
-#define K_SMB_DFMT_NODATA           4
-#define K_SMB_DFMT_CMD4BYTE         5
-#define K_SMB_DFMT_CMD5BYTE         6
-#define K_SMB_DFMT_RESERVED         7
+#define K_SMB_DFMT_1BYTE           0
+#define K_SMB_DFMT_2BYTE           1
+#define K_SMB_DFMT_3BYTE           2
+#define K_SMB_DFMT_4BYTE           3
+#define K_SMB_DFMT_NODATA          4
+#define K_SMB_DFMT_CMD4BYTE        5
+#define K_SMB_DFMT_CMD5BYTE        6
+#define K_SMB_DFMT_RESERVED        7

 
 #define V_SMB_DFMT_1BYTE           V_SMB_DFMT(K_SMB_DFMT_1BYTE)
 #define V_SMB_DFMT_2BYTE           V_SMB_DFMT(K_SMB_DFMT_2BYTE)
 
 #define V_SMB_DFMT_1BYTE           V_SMB_DFMT(K_SMB_DFMT_1BYTE)
 #define V_SMB_DFMT_2BYTE           V_SMB_DFMT(K_SMB_DFMT_2BYTE)


@@ -182,13 +182,13 @@
 #define V_SMB_DFMT_CMD5BYTE        V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE)
 #define V_SMB_DFMT_RESERVED        V_SMB_DFMT(K_SMB_DFMT_RESERVED)
 
 #define V_SMB_DFMT_CMD5BYTE        V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE)
 #define V_SMB_DFMT_RESERVED        V_SMB_DFMT(K_SMB_DFMT_RESERVED)
 

-#define S_SMB_AFMT                  11
-#define M_SMB_AFMT                  _SB_MAKEMASK(2, S_SMB_AFMT)
-#define V_SMB_AFMT(x)               _SB_MAKEVALUE(x, S_SMB_AFMT)
-#define G_SMB_AFMT(x)               _SB_GETVALUE(x, S_SMB_AFMT, M_SMB_AFMT)
+#define S_SMB_AFMT                 11
+#define M_SMB_AFMT                 _SB_MAKEMASK(2, S_SMB_AFMT)
+#define V_SMB_AFMT(x)              _SB_MAKEVALUE(x, S_SMB_AFMT)
+#define G_SMB_AFMT(x)              _SB_GETVALUE(x, S_SMB_AFMT, M_SMB_AFMT)

 
 

-#define K_SMB_AFMT_NONE             0
-#define K_SMB_AFMT_ADDR             1
+#define K_SMB_AFMT_NONE                    0
+#define K_SMB_AFMT_ADDR                    1

 #define K_SMB_AFMT_ADDR_CMD1BYTE    2
 #define K_SMB_AFMT_ADDR_CMD2BYTE    3
 
 #define K_SMB_AFMT_ADDR_CMD1BYTE    2
 #define K_SMB_AFMT_ADDR_CMD2BYTE    3
 

diff --git a/arch/mips/include/asm/sibyte/sb1250_syncser.h b/arch/mips/include/asm/sibyte/sb1250_syncser.h
index 274e9179d326bf2555607c7c160bba21822e198f..b3acc75cf0f2ab206d94a708d4f3f46ece624664 100644 (file)
--- a/arch/mips/include/asm/sibyte/sb1250_syncser.h
+++ b/arch/mips/include/asm/sibyte/sb1250_syncser.h
@@ -1,7 +1,7 @@
 /*  *********************************************************************
     *  SB1250 Board Support Package
     *
 /*  *********************************************************************
     *  SB1250 Board Support Package
     *

-    *  Synchronous Serial Constants              File: sb1250_syncser.h
+    *  Synchronous Serial Constants             File: sb1250_syncser.h

     *
     *  This module contains constants and macros useful for
     *  manipulating the SB1250's Synchronous Serial
     *
     *  This module contains constants and macros useful for
     *  manipulating the SB1250's Synchronous Serial


@@ -39,108 +39,108 @@
  * Serial Mode Configuration Register
  */
 
  * Serial Mode Configuration Register
  */
 

-#define M_SYNCSER_CRC_MODE                 _SB_MAKEMASK1(0)
-#define M_SYNCSER_MSB_FIRST                _SB_MAKEMASK1(1)
+#define M_SYNCSER_CRC_MODE                _SB_MAKEMASK1(0)
+#define M_SYNCSER_MSB_FIRST               _SB_MAKEMASK1(1)

 
 

-#define S_SYNCSER_FLAG_NUM                 2
-#define M_SYNCSER_FLAG_NUM                 _SB_MAKEMASK(4, S_SYNCSER_FLAG_NUM)
-#define V_SYNCSER_FLAG_NUM                 _SB_MAKEVALUE(x, S_SYNCSER_FLAG_NUM)
+#define S_SYNCSER_FLAG_NUM                2
+#define M_SYNCSER_FLAG_NUM                _SB_MAKEMASK(4, S_SYNCSER_FLAG_NUM)
+#define V_SYNCSER_FLAG_NUM                _SB_MAKEVALUE(x, S_SYNCSER_FLAG_NUM)

 
 

-#define M_SYNCSER_FLAG_EN                  _SB_MAKEMASK1(6)
-#define M_SYNCSER_HDLC_EN                  _SB_MAKEMASK1(7)
-#define M_SYNCSER_LOOP_MODE                _SB_MAKEMASK1(8)
-#define M_SYNCSER_LOOPBACK                 _SB_MAKEMASK1(9)
+#define M_SYNCSER_FLAG_EN                 _SB_MAKEMASK1(6)
+#define M_SYNCSER_HDLC_EN                 _SB_MAKEMASK1(7)
+#define M_SYNCSER_LOOP_MODE               _SB_MAKEMASK1(8)
+#define M_SYNCSER_LOOPBACK                _SB_MAKEMASK1(9)

 
 /*
  * Serial Clock Source and Line Interface Mode Register
  */
 
 
 /*
  * Serial Clock Source and Line Interface Mode Register
  */
 

-#define M_SYNCSER_RXCLK_INV                _SB_MAKEMASK1(0)
-#define M_SYNCSER_RXCLK_EXT                _SB_MAKEMASK1(1)
+#define M_SYNCSER_RXCLK_INV               _SB_MAKEMASK1(0)
+#define M_SYNCSER_RXCLK_EXT               _SB_MAKEMASK1(1)

 
 

-#define S_SYNCSER_RXSYNC_DLY               2
-#define M_SYNCSER_RXSYNC_DLY               _SB_MAKEMASK(2, S_SYNCSER_RXSYNC_DLY)
-#define V_SYNCSER_RXSYNC_DLY(x)            _SB_MAKEVALUE(x, S_SYNCSER_RXSYNC_DLY)
+#define S_SYNCSER_RXSYNC_DLY              2
+#define M_SYNCSER_RXSYNC_DLY              _SB_MAKEMASK(2, S_SYNCSER_RXSYNC_DLY)
+#define V_SYNCSER_RXSYNC_DLY(x)                   _SB_MAKEVALUE(x, S_SYNCSER_RXSYNC_DLY)

 
 

-#define M_SYNCSER_RXSYNC_LOW               _SB_MAKEMASK1(4)
-#define M_SYNCSER_RXSTRB_LOW               _SB_MAKEMASK1(5)
+#define M_SYNCSER_RXSYNC_LOW              _SB_MAKEMASK1(4)
+#define M_SYNCSER_RXSTRB_LOW              _SB_MAKEMASK1(5)

 
 

-#define M_SYNCSER_RXSYNC_EDGE              _SB_MAKEMASK1(6)
-#define M_SYNCSER_RXSYNC_INT               _SB_MAKEMASK1(7)
+#define M_SYNCSER_RXSYNC_EDGE             _SB_MAKEMASK1(6)
+#define M_SYNCSER_RXSYNC_INT              _SB_MAKEMASK1(7)

 
 

-#define M_SYNCSER_TXCLK_INV                _SB_MAKEMASK1(8)
-#define M_SYNCSER_TXCLK_EXT                _SB_MAKEMASK1(9)
+#define M_SYNCSER_TXCLK_INV               _SB_MAKEMASK1(8)
+#define M_SYNCSER_TXCLK_EXT               _SB_MAKEMASK1(9)

 
 

-#define S_SYNCSER_TXSYNC_DLY               10
-#define M_SYNCSER_TXSYNC_DLY               _SB_MAKEMASK(2, S_SYNCSER_TXSYNC_DLY)
-#define V_SYNCSER_TXSYNC_DLY(x)            _SB_MAKEVALUE(x, S_SYNCSER_TXSYNC_DLY)
+#define S_SYNCSER_TXSYNC_DLY              10
+#define M_SYNCSER_TXSYNC_DLY              _SB_MAKEMASK(2, S_SYNCSER_TXSYNC_DLY)
+#define V_SYNCSER_TXSYNC_DLY(x)                   _SB_MAKEVALUE(x, S_SYNCSER_TXSYNC_DLY)

 
 

-#define M_SYNCSER_TXSYNC_LOW               _SB_MAKEMASK1(12)
-#define M_SYNCSER_TXSTRB_LOW               _SB_MAKEMASK1(13)
+#define M_SYNCSER_TXSYNC_LOW              _SB_MAKEMASK1(12)
+#define M_SYNCSER_TXSTRB_LOW              _SB_MAKEMASK1(13)

 
 

-#define M_SYNCSER_TXSYNC_EDGE              _SB_MAKEMASK1(14)
-#define M_SYNCSER_TXSYNC_INT               _SB_MAKEMASK1(15)
+#define M_SYNCSER_TXSYNC_EDGE             _SB_MAKEMASK1(14)
+#define M_SYNCSER_TXSYNC_INT              _SB_MAKEMASK1(15)

 
 /*
  * Serial Command Register
  */
 
 
 /*
  * Serial Command Register
  */
 

-#define M_SYNCSER_CMD_RX_EN                _SB_MAKEMASK1(0)
-#define M_SYNCSER_CMD_TX_EN                _SB_MAKEMASK1(1)
-#define M_SYNCSER_CMD_RX_RESET             _SB_MAKEMASK1(2)
-#define M_SYNCSER_CMD_TX_RESET             _SB_MAKEMASK1(3)
-#define M_SYNCSER_CMD_TX_PAUSE             _SB_MAKEMASK1(5)
+#define M_SYNCSER_CMD_RX_EN               _SB_MAKEMASK1(0)
+#define M_SYNCSER_CMD_TX_EN               _SB_MAKEMASK1(1)
+#define M_SYNCSER_CMD_RX_RESET            _SB_MAKEMASK1(2)
+#define M_SYNCSER_CMD_TX_RESET            _SB_MAKEMASK1(3)
+#define M_SYNCSER_CMD_TX_PAUSE            _SB_MAKEMASK1(5)

 
 /*
  * Serial DMA Enable Register
  */
 
 
 /*
  * Serial DMA Enable Register
  */
 

-#define M_SYNCSER_DMA_RX_EN                _SB_MAKEMASK1(0)
-#define M_SYNCSER_DMA_TX_EN                _SB_MAKEMASK1(4)
+#define M_SYNCSER_DMA_RX_EN               _SB_MAKEMASK1(0)
+#define M_SYNCSER_DMA_TX_EN               _SB_MAKEMASK1(4)

 
 /*
  * Serial Status Register
  */
 
 
 /*
  * Serial Status Register
  */
 

-#define M_SYNCSER_RX_CRCERR                _SB_MAKEMASK1(0)
-#define M_SYNCSER_RX_ABORT                 _SB_MAKEMASK1(1)
-#define M_SYNCSER_RX_OCTET                 _SB_MAKEMASK1(2)
-#define M_SYNCSER_RX_LONGFRM               _SB_MAKEMASK1(3)
-#define M_SYNCSER_RX_SHORTFRM              _SB_MAKEMASK1(4)
-#define M_SYNCSER_RX_OVERRUN               _SB_MAKEMASK1(5)
-#define M_SYNCSER_RX_SYNC_ERR              _SB_MAKEMASK1(6)
-#define M_SYNCSER_TX_CRCERR                _SB_MAKEMASK1(8)
-#define M_SYNCSER_TX_UNDERRUN              _SB_MAKEMASK1(9)
-#define M_SYNCSER_TX_SYNC_ERR              _SB_MAKEMASK1(10)
-#define M_SYNCSER_TX_PAUSE_COMPLETE        _SB_MAKEMASK1(11)
-#define M_SYNCSER_RX_EOP_COUNT             _SB_MAKEMASK1(16)
-#define M_SYNCSER_RX_EOP_TIMER             _SB_MAKEMASK1(17)
-#define M_SYNCSER_RX_EOP_SEEN              _SB_MAKEMASK1(18)
-#define M_SYNCSER_RX_HWM                   _SB_MAKEMASK1(19)
-#define M_SYNCSER_RX_LWM                   _SB_MAKEMASK1(20)
-#define M_SYNCSER_RX_DSCR                  _SB_MAKEMASK1(21)
-#define M_SYNCSER_RX_DERR                  _SB_MAKEMASK1(22)
-#define M_SYNCSER_TX_EOP_COUNT             _SB_MAKEMASK1(24)
-#define M_SYNCSER_TX_EOP_TIMER             _SB_MAKEMASK1(25)
-#define M_SYNCSER_TX_EOP_SEEN              _SB_MAKEMASK1(26)
-#define M_SYNCSER_TX_HWM                   _SB_MAKEMASK1(27)
-#define M_SYNCSER_TX_LWM                   _SB_MAKEMASK1(28)
-#define M_SYNCSER_TX_DSCR                  _SB_MAKEMASK1(29)
-#define M_SYNCSER_TX_DERR                  _SB_MAKEMASK1(30)
-#define M_SYNCSER_TX_DZERO                 _SB_MAKEMASK1(31)
+#define M_SYNCSER_RX_CRCERR               _SB_MAKEMASK1(0)
+#define M_SYNCSER_RX_ABORT                _SB_MAKEMASK1(1)
+#define M_SYNCSER_RX_OCTET                _SB_MAKEMASK1(2)
+#define M_SYNCSER_RX_LONGFRM              _SB_MAKEMASK1(3)
+#define M_SYNCSER_RX_SHORTFRM             _SB_MAKEMASK1(4)
+#define M_SYNCSER_RX_OVERRUN              _SB_MAKEMASK1(5)
+#define M_SYNCSER_RX_SYNC_ERR             _SB_MAKEMASK1(6)
+#define M_SYNCSER_TX_CRCERR               _SB_MAKEMASK1(8)
+#define M_SYNCSER_TX_UNDERRUN             _SB_MAKEMASK1(9)
+#define M_SYNCSER_TX_SYNC_ERR             _SB_MAKEMASK1(10)
+#define M_SYNCSER_TX_PAUSE_COMPLETE       _SB_MAKEMASK1(11)
+#define M_SYNCSER_RX_EOP_COUNT            _SB_MAKEMASK1(16)
+#define M_SYNCSER_RX_EOP_TIMER            _SB_MAKEMASK1(17)
+#define M_SYNCSER_RX_EOP_SEEN             _SB_MAKEMASK1(18)
+#define M_SYNCSER_RX_HWM                  _SB_MAKEMASK1(19)
+#define M_SYNCSER_RX_LWM                  _SB_MAKEMASK1(20)
+#define M_SYNCSER_RX_DSCR                 _SB_MAKEMASK1(21)
+#define M_SYNCSER_RX_DERR                 _SB_MAKEMASK1(22)
+#define M_SYNCSER_TX_EOP_COUNT            _SB_MAKEMASK1(24)
+#define M_SYNCSER_TX_EOP_TIMER            _SB_MAKEMASK1(25)
+#define M_SYNCSER_TX_EOP_SEEN             _SB_MAKEMASK1(26)
+#define M_SYNCSER_TX_HWM                  _SB_MAKEMASK1(27)
+#define M_SYNCSER_TX_LWM                  _SB_MAKEMASK1(28)
+#define M_SYNCSER_TX_DSCR                 _SB_MAKEMASK1(29)
+#define M_SYNCSER_TX_DERR                 _SB_MAKEMASK1(30)
+#define M_SYNCSER_TX_DZERO                _SB_MAKEMASK1(31)

 
 /*
  * Sequencer Table Entry format
  */
 
 
 /*
  * Sequencer Table Entry format
  */
 

-#define M_SYNCSER_SEQ_LAST                 _SB_MAKEMASK1(0)
-#define M_SYNCSER_SEQ_BYTE                 _SB_MAKEMASK1(1)
+#define M_SYNCSER_SEQ_LAST                _SB_MAKEMASK1(0)
+#define M_SYNCSER_SEQ_BYTE                _SB_MAKEMASK1(1)

 
 

-#define S_SYNCSER_SEQ_COUNT                2
-#define M_SYNCSER_SEQ_COUNT                _SB_MAKEMASK(4, S_SYNCSER_SEQ_COUNT)
-#define V_SYNCSER_SEQ_COUNT(x)             _SB_MAKEVALUE(x, S_SYNCSER_SEQ_COUNT)
+#define S_SYNCSER_SEQ_COUNT               2
+#define M_SYNCSER_SEQ_COUNT               _SB_MAKEMASK(4, S_SYNCSER_SEQ_COUNT)
+#define V_SYNCSER_SEQ_COUNT(x)            _SB_MAKEVALUE(x, S_SYNCSER_SEQ_COUNT)

 
 

-#define M_SYNCSER_SEQ_ENABLE               _SB_MAKEMASK1(6)
-#define M_SYNCSER_SEQ_STROBE               _SB_MAKEMASK1(7)
+#define M_SYNCSER_SEQ_ENABLE              _SB_MAKEMASK1(6)
+#define M_SYNCSER_SEQ_STROBE              _SB_MAKEMASK1(7)

 
 #endif
 
 #endif

diff --git a/arch/mips/include/asm/sibyte/sb1250_uart.h b/arch/mips/include/asm/sibyte/sb1250_uart.h
index bb99ecac58178b85a204b47404b3af68b7a403ac..a43dc197628662678ba09afaba8e7133e0342fd6 100644 (file)
--- a/arch/mips/include/asm/sibyte/sb1250_uart.h
+++ b/arch/mips/include/asm/sibyte/sb1250_uart.h
@@ -45,33 +45,33 @@
  * Register: DUART_MODE_REG_1_B
  */
 
  * Register: DUART_MODE_REG_1_B
  */
 

-#define S_DUART_BITS_PER_CHAR       0
-#define M_DUART_BITS_PER_CHAR       _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR)
+#define S_DUART_BITS_PER_CHAR      0
+#define M_DUART_BITS_PER_CHAR      _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR)

 #define V_DUART_BITS_PER_CHAR(x)    _SB_MAKEVALUE(x, S_DUART_BITS_PER_CHAR)
 
 #define K_DUART_BITS_PER_CHAR_RSV0  0
 #define K_DUART_BITS_PER_CHAR_RSV1  1
 #define V_DUART_BITS_PER_CHAR(x)    _SB_MAKEVALUE(x, S_DUART_BITS_PER_CHAR)
 
 #define K_DUART_BITS_PER_CHAR_RSV0  0
 #define K_DUART_BITS_PER_CHAR_RSV1  1

-#define K_DUART_BITS_PER_CHAR_7     2
-#define K_DUART_BITS_PER_CHAR_8     3
+#define K_DUART_BITS_PER_CHAR_7            2
+#define K_DUART_BITS_PER_CHAR_8            3

 
 #define V_DUART_BITS_PER_CHAR_RSV0  V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0)
 #define V_DUART_BITS_PER_CHAR_RSV1  V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1)
 
 #define V_DUART_BITS_PER_CHAR_RSV0  V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0)
 #define V_DUART_BITS_PER_CHAR_RSV1  V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1)

-#define V_DUART_BITS_PER_CHAR_7     V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7)
-#define V_DUART_BITS_PER_CHAR_8     V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8)
+#define V_DUART_BITS_PER_CHAR_7            V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7)
+#define V_DUART_BITS_PER_CHAR_8            V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8)

 
 
 #define M_DUART_PARITY_TYPE_EVEN    0x00
 
 
 #define M_DUART_PARITY_TYPE_EVEN    0x00

-#define M_DUART_PARITY_TYPE_ODD     _SB_MAKEMASK1(2)
+#define M_DUART_PARITY_TYPE_ODD            _SB_MAKEMASK1(2)

 
 

-#define S_DUART_PARITY_MODE          3
-#define M_DUART_PARITY_MODE         _SB_MAKEMASK(2, S_DUART_PARITY_MODE)
-#define V_DUART_PARITY_MODE(x)      _SB_MAKEVALUE(x, S_DUART_PARITY_MODE)
+#define S_DUART_PARITY_MODE         3
+#define M_DUART_PARITY_MODE        _SB_MAKEMASK(2, S_DUART_PARITY_MODE)
+#define V_DUART_PARITY_MODE(x)     _SB_MAKEVALUE(x, S_DUART_PARITY_MODE)

 
 

-#define K_DUART_PARITY_MODE_ADD       0
+#define K_DUART_PARITY_MODE_ADD              0

 #define K_DUART_PARITY_MODE_ADD_FIXED 1
 #define K_DUART_PARITY_MODE_NONE      2
 
 #define K_DUART_PARITY_MODE_ADD_FIXED 1
 #define K_DUART_PARITY_MODE_NONE      2
 

-#define V_DUART_PARITY_MODE_ADD       V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD)
+#define V_DUART_PARITY_MODE_ADD              V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD)

 #define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED)
 #define V_DUART_PARITY_MODE_NONE      V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE)
 
 #define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED)
 #define V_DUART_PARITY_MODE_NONE      V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE)
 


@@ -81,7 +81,7 @@
 #define M_DUART_RX_IRQ_SEL_RXRDY    0
 #define M_DUART_RX_IRQ_SEL_RXFULL   _SB_MAKEMASK1(6)
 
 #define M_DUART_RX_IRQ_SEL_RXRDY    0
 #define M_DUART_RX_IRQ_SEL_RXFULL   _SB_MAKEMASK1(6)
 

-#define M_DUART_RX_RTS_ENA          _SB_MAKEMASK1(7)
+#define M_DUART_RX_RTS_ENA         _SB_MAKEMASK1(7)

 
 /*
  * DUART Mode Register #2 (Table 10-4)
 
 /*
  * DUART Mode Register #2 (Table 10-4)


@@ -89,18 +89,18 @@
  * Register: DUART_MODE_REG_2_B
  */
 
  * Register: DUART_MODE_REG_2_B
  */
 

-#define M_DUART_MODE_RESERVED1      _SB_MAKEMASK(3, 0)   /* ignored */
+#define M_DUART_MODE_RESERVED1     _SB_MAKEMASK(3, 0)   /* ignored */

 
 

-#define M_DUART_STOP_BIT_LEN_2      _SB_MAKEMASK1(3)
-#define M_DUART_STOP_BIT_LEN_1      0
+#define M_DUART_STOP_BIT_LEN_2     _SB_MAKEMASK1(3)
+#define M_DUART_STOP_BIT_LEN_1     0

 
 

-#define M_DUART_TX_CTS_ENA          _SB_MAKEMASK1(4)
+#define M_DUART_TX_CTS_ENA         _SB_MAKEMASK1(4)

 
 
 
 

-#define M_DUART_MODE_RESERVED2      _SB_MAKEMASK1(5)    /* must be zero */
+#define M_DUART_MODE_RESERVED2     _SB_MAKEMASK1(5)    /* must be zero */

 
 #define S_DUART_CHAN_MODE          6
 
 #define S_DUART_CHAN_MODE          6

-#define M_DUART_CHAN_MODE           _SB_MAKEMASK(2, S_DUART_CHAN_MODE)
+#define M_DUART_CHAN_MODE          _SB_MAKEMASK(2, S_DUART_CHAN_MODE)

 #define V_DUART_CHAN_MODE(x)       _SB_MAKEVALUE(x, S_DUART_CHAN_MODE)
 
 #define K_DUART_CHAN_MODE_NORMAL    0
 #define V_DUART_CHAN_MODE(x)       _SB_MAKEVALUE(x, S_DUART_CHAN_MODE)
 
 #define K_DUART_CHAN_MODE_NORMAL    0


@@ -117,34 +117,34 @@
  * Register: DUART_CMD_B
  */
 
  * Register: DUART_CMD_B
  */
 

-#define M_DUART_RX_EN               _SB_MAKEMASK1(0)
-#define M_DUART_RX_DIS              _SB_MAKEMASK1(1)
-#define M_DUART_TX_EN               _SB_MAKEMASK1(2)
-#define M_DUART_TX_DIS              _SB_MAKEMASK1(3)
+#define M_DUART_RX_EN              _SB_MAKEMASK1(0)
+#define M_DUART_RX_DIS             _SB_MAKEMASK1(1)
+#define M_DUART_TX_EN              _SB_MAKEMASK1(2)
+#define M_DUART_TX_DIS             _SB_MAKEMASK1(3)

 
 #define S_DUART_MISC_CMD           4
 
 #define S_DUART_MISC_CMD           4

-#define M_DUART_MISC_CMD            _SB_MAKEMASK(3, S_DUART_MISC_CMD)
-#define V_DUART_MISC_CMD(x)         _SB_MAKEVALUE(x, S_DUART_MISC_CMD)
-
-#define K_DUART_MISC_CMD_NOACTION0       0
-#define K_DUART_MISC_CMD_NOACTION1       1
-#define K_DUART_MISC_CMD_RESET_RX        2
-#define K_DUART_MISC_CMD_RESET_TX        3
-#define K_DUART_MISC_CMD_NOACTION4       4
+#define M_DUART_MISC_CMD           _SB_MAKEMASK(3, S_DUART_MISC_CMD)
+#define V_DUART_MISC_CMD(x)        _SB_MAKEVALUE(x, S_DUART_MISC_CMD)
+
+#define K_DUART_MISC_CMD_NOACTION0      0
+#define K_DUART_MISC_CMD_NOACTION1      1
+#define K_DUART_MISC_CMD_RESET_RX       2
+#define K_DUART_MISC_CMD_RESET_TX       3
+#define K_DUART_MISC_CMD_NOACTION4      4

 #define K_DUART_MISC_CMD_RESET_BREAK_INT 5
 #define K_DUART_MISC_CMD_RESET_BREAK_INT 5

-#define K_DUART_MISC_CMD_START_BREAK     6
-#define K_DUART_MISC_CMD_STOP_BREAK      7
-
-#define V_DUART_MISC_CMD_NOACTION0       V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0)
-#define V_DUART_MISC_CMD_NOACTION1       V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1)
-#define V_DUART_MISC_CMD_RESET_RX        V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX)
-#define V_DUART_MISC_CMD_RESET_TX        V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX)
-#define V_DUART_MISC_CMD_NOACTION4       V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4)
+#define K_DUART_MISC_CMD_START_BREAK    6
+#define K_DUART_MISC_CMD_STOP_BREAK     7
+
+#define V_DUART_MISC_CMD_NOACTION0      V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0)
+#define V_DUART_MISC_CMD_NOACTION1      V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1)
+#define V_DUART_MISC_CMD_RESET_RX       V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX)
+#define V_DUART_MISC_CMD_RESET_TX       V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX)
+#define V_DUART_MISC_CMD_NOACTION4      V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4)

 #define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT)
 #define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT)

-#define V_DUART_MISC_CMD_START_BREAK     V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK)
-#define V_DUART_MISC_CMD_STOP_BREAK      V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK)
+#define V_DUART_MISC_CMD_START_BREAK    V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK)
+#define V_DUART_MISC_CMD_STOP_BREAK     V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK)

 
 

-#define M_DUART_CMD_RESERVED             _SB_MAKEMASK1(7)
+#define M_DUART_CMD_RESERVED            _SB_MAKEMASK1(7)

 
 /*
  * DUART Status Register (Table 10-6)
 
 /*
  * DUART Status Register (Table 10-6)


@@ -153,14 +153,14 @@
  * READ-ONLY
  */
 
  * READ-ONLY
  */
 

-#define M_DUART_RX_RDY              _SB_MAKEMASK1(0)
-#define M_DUART_RX_FFUL             _SB_MAKEMASK1(1)
-#define M_DUART_TX_RDY              _SB_MAKEMASK1(2)
-#define M_DUART_TX_EMT              _SB_MAKEMASK1(3)
-#define M_DUART_OVRUN_ERR           _SB_MAKEMASK1(4)
-#define M_DUART_PARITY_ERR          _SB_MAKEMASK1(5)
-#define M_DUART_FRM_ERR             _SB_MAKEMASK1(6)
-#define M_DUART_RCVD_BRK            _SB_MAKEMASK1(7)
+#define M_DUART_RX_RDY             _SB_MAKEMASK1(0)
+#define M_DUART_RX_FFUL                    _SB_MAKEMASK1(1)
+#define M_DUART_TX_RDY             _SB_MAKEMASK1(2)
+#define M_DUART_TX_EMT             _SB_MAKEMASK1(3)
+#define M_DUART_OVRUN_ERR          _SB_MAKEMASK1(4)
+#define M_DUART_PARITY_ERR         _SB_MAKEMASK1(5)
+#define M_DUART_FRM_ERR                    _SB_MAKEMASK1(6)
+#define M_DUART_RCVD_BRK           _SB_MAKEMASK1(7)

 
 /*
  * DUART Baud Rate Register (Table 10-7)
 
 /*
  * DUART Baud Rate Register (Table 10-7)


@@ -168,8 +168,8 @@
  * Register: DUART_CLK_SEL_B
  */
 
  * Register: DUART_CLK_SEL_B
  */
 

-#define M_DUART_CLK_COUNTER         _SB_MAKEMASK(12, 0)
-#define V_DUART_BAUD_RATE(x)        (100000000/((x)*20)-1)
+#define M_DUART_CLK_COUNTER        _SB_MAKEMASK(12, 0)
+#define V_DUART_BAUD_RATE(x)       (100000000/((x)*20)-1)

 
 /*
  * DUART Data Registers (Table 10-8 and 10-9)
 
 /*
  * DUART Data Registers (Table 10-8 and 10-9)


@@ -179,33 +179,33 @@
  * Register: DUART_TX_HOLD_B
  */
 
  * Register: DUART_TX_HOLD_B
  */
 

-#define M_DUART_RX_DATA             _SB_MAKEMASK(8, 0)
-#define M_DUART_TX_DATA             _SB_MAKEMASK(8, 0)
+#define M_DUART_RX_DATA                    _SB_MAKEMASK(8, 0)
+#define M_DUART_TX_DATA                    _SB_MAKEMASK(8, 0)

 
 /*
  * DUART Input Port Register (Table 10-10)
  * Register: DUART_IN_PORT
  */
 
 
 /*
  * DUART Input Port Register (Table 10-10)
  * Register: DUART_IN_PORT
  */
 

-#define M_DUART_IN_PIN0_VAL         _SB_MAKEMASK1(0)
-#define M_DUART_IN_PIN1_VAL         _SB_MAKEMASK1(1)
-#define M_DUART_IN_PIN2_VAL         _SB_MAKEMASK1(2)
-#define M_DUART_IN_PIN3_VAL         _SB_MAKEMASK1(3)
-#define M_DUART_IN_PIN4_VAL         _SB_MAKEMASK1(4)
-#define M_DUART_IN_PIN5_VAL         _SB_MAKEMASK1(5)
-#define M_DUART_RIN0_PIN            _SB_MAKEMASK1(6)
-#define M_DUART_RIN1_PIN            _SB_MAKEMASK1(7)
+#define M_DUART_IN_PIN0_VAL        _SB_MAKEMASK1(0)
+#define M_DUART_IN_PIN1_VAL        _SB_MAKEMASK1(1)
+#define M_DUART_IN_PIN2_VAL        _SB_MAKEMASK1(2)
+#define M_DUART_IN_PIN3_VAL        _SB_MAKEMASK1(3)
+#define M_DUART_IN_PIN4_VAL        _SB_MAKEMASK1(4)
+#define M_DUART_IN_PIN5_VAL        _SB_MAKEMASK1(5)
+#define M_DUART_RIN0_PIN           _SB_MAKEMASK1(6)
+#define M_DUART_RIN1_PIN           _SB_MAKEMASK1(7)

 
 /*
  * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13)
  * Register: DUART_INPORT_CHNG
  */
 
 
 /*
  * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13)
  * Register: DUART_INPORT_CHNG
  */
 

-#define S_DUART_IN_PIN_VAL          0
-#define M_DUART_IN_PIN_VAL          _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL)
+#define S_DUART_IN_PIN_VAL         0
+#define M_DUART_IN_PIN_VAL         _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL)

 
 

-#define S_DUART_IN_PIN_CHNG         4
-#define M_DUART_IN_PIN_CHNG         _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG)
+#define S_DUART_IN_PIN_CHNG        4
+#define M_DUART_IN_PIN_CHNG        _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG)

 
 
 /*
 
 
 /*


@@ -213,46 +213,46 @@
  * Register: DUART_OPCR
  */
 
  * Register: DUART_OPCR
  */
 

-#define M_DUART_OPCR_RESERVED0      _SB_MAKEMASK1(0)   /* must be zero */
-#define M_DUART_OPC2_SEL            _SB_MAKEMASK1(1)
-#define M_DUART_OPCR_RESERVED1      _SB_MAKEMASK1(2)   /* must be zero */
-#define M_DUART_OPC3_SEL            _SB_MAKEMASK1(3)
-#define M_DUART_OPCR_RESERVED2      _SB_MAKEMASK(4, 4)  /* must be zero */
+#define M_DUART_OPCR_RESERVED0     _SB_MAKEMASK1(0)   /* must be zero */
+#define M_DUART_OPC2_SEL           _SB_MAKEMASK1(1)
+#define M_DUART_OPCR_RESERVED1     _SB_MAKEMASK1(2)   /* must be zero */
+#define M_DUART_OPC3_SEL           _SB_MAKEMASK1(3)
+#define M_DUART_OPCR_RESERVED2     _SB_MAKEMASK(4, 4)  /* must be zero */

 
 /*
  * DUART Aux Control Register (Table 10-15)
  * Register: DUART_AUX_CTRL
  */
 
 
 /*
  * DUART Aux Control Register (Table 10-15)
  * Register: DUART_AUX_CTRL
  */
 

-#define M_DUART_IP0_CHNG_ENA        _SB_MAKEMASK1(0)
-#define M_DUART_IP1_CHNG_ENA        _SB_MAKEMASK1(1)
-#define M_DUART_IP2_CHNG_ENA        _SB_MAKEMASK1(2)
-#define M_DUART_IP3_CHNG_ENA        _SB_MAKEMASK1(3)
-#define M_DUART_ACR_RESERVED        _SB_MAKEMASK(4, 4)
+#define M_DUART_IP0_CHNG_ENA       _SB_MAKEMASK1(0)
+#define M_DUART_IP1_CHNG_ENA       _SB_MAKEMASK1(1)
+#define M_DUART_IP2_CHNG_ENA       _SB_MAKEMASK1(2)
+#define M_DUART_IP3_CHNG_ENA       _SB_MAKEMASK1(3)
+#define M_DUART_ACR_RESERVED       _SB_MAKEMASK(4, 4)

 
 

-#define M_DUART_CTS_CHNG_ENA        _SB_MAKEMASK1(0)
-#define M_DUART_CIN_CHNG_ENA        _SB_MAKEMASK1(2)
+#define M_DUART_CTS_CHNG_ENA       _SB_MAKEMASK1(0)
+#define M_DUART_CIN_CHNG_ENA       _SB_MAKEMASK1(2)

 
 /*
  * DUART Interrupt Status Register (Table 10-16)
  * Register: DUART_ISR
  */
 
 
 /*
  * DUART Interrupt Status Register (Table 10-16)
  * Register: DUART_ISR
  */
 

-#define M_DUART_ISR_TX_A            _SB_MAKEMASK1(0)
+#define M_DUART_ISR_TX_A           _SB_MAKEMASK1(0)

 
 

-#define S_DUART_ISR_RX_A            1
-#define M_DUART_ISR_RX_A            _SB_MAKEMASK1(S_DUART_ISR_RX_A)
-#define V_DUART_ISR_RX_A(x)         _SB_MAKEVALUE(x, S_DUART_ISR_RX_A)
-#define G_DUART_ISR_RX_A(x)         _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A)
+#define S_DUART_ISR_RX_A           1
+#define M_DUART_ISR_RX_A           _SB_MAKEMASK1(S_DUART_ISR_RX_A)
+#define V_DUART_ISR_RX_A(x)        _SB_MAKEVALUE(x, S_DUART_ISR_RX_A)
+#define G_DUART_ISR_RX_A(x)        _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A)

 
 

-#define M_DUART_ISR_BRK_A           _SB_MAKEMASK1(2)
-#define M_DUART_ISR_IN_A            _SB_MAKEMASK1(3)
+#define M_DUART_ISR_BRK_A          _SB_MAKEMASK1(2)
+#define M_DUART_ISR_IN_A           _SB_MAKEMASK1(3)

 #define M_DUART_ISR_ALL_A          _SB_MAKEMASK(4, 0)
 
 #define M_DUART_ISR_ALL_A          _SB_MAKEMASK(4, 0)
 

-#define M_DUART_ISR_TX_B            _SB_MAKEMASK1(4)
-#define M_DUART_ISR_RX_B            _SB_MAKEMASK1(5)
-#define M_DUART_ISR_BRK_B           _SB_MAKEMASK1(6)
-#define M_DUART_ISR_IN_B            _SB_MAKEMASK1(7)
+#define M_DUART_ISR_TX_B           _SB_MAKEMASK1(4)
+#define M_DUART_ISR_RX_B           _SB_MAKEMASK1(5)
+#define M_DUART_ISR_BRK_B          _SB_MAKEMASK1(6)
+#define M_DUART_ISR_IN_B           _SB_MAKEMASK1(7)

 #define M_DUART_ISR_ALL_B          _SB_MAKEMASK(4, 4)
 
 /*
 #define M_DUART_ISR_ALL_B          _SB_MAKEMASK(4, 4)
 
 /*


@@ -262,29 +262,29 @@
  * Register: DUART_ISR_B
  */
 
  * Register: DUART_ISR_B
  */
 

-#define M_DUART_ISR_TX              _SB_MAKEMASK1(0)
-#define M_DUART_ISR_RX              _SB_MAKEMASK1(1)
-#define M_DUART_ISR_BRK             _SB_MAKEMASK1(2)
-#define M_DUART_ISR_IN              _SB_MAKEMASK1(3)
+#define M_DUART_ISR_TX             _SB_MAKEMASK1(0)
+#define M_DUART_ISR_RX             _SB_MAKEMASK1(1)
+#define M_DUART_ISR_BRK                    _SB_MAKEMASK1(2)
+#define M_DUART_ISR_IN             _SB_MAKEMASK1(3)

 #define M_DUART_ISR_ALL                    _SB_MAKEMASK(4, 0)
 #define M_DUART_ISR_ALL                    _SB_MAKEMASK(4, 0)

-#define M_DUART_ISR_RESERVED        _SB_MAKEMASK(4, 4)
+#define M_DUART_ISR_RESERVED       _SB_MAKEMASK(4, 4)

 
 /*
  * DUART Interrupt Mask Register (Table 10-19)
  * Register: DUART_IMR
  */
 
 
 /*
  * DUART Interrupt Mask Register (Table 10-19)
  * Register: DUART_IMR
  */
 

-#define M_DUART_IMR_TX_A            _SB_MAKEMASK1(0)
-#define M_DUART_IMR_RX_A            _SB_MAKEMASK1(1)
-#define M_DUART_IMR_BRK_A           _SB_MAKEMASK1(2)
-#define M_DUART_IMR_IN_A            _SB_MAKEMASK1(3)
+#define M_DUART_IMR_TX_A           _SB_MAKEMASK1(0)
+#define M_DUART_IMR_RX_A           _SB_MAKEMASK1(1)
+#define M_DUART_IMR_BRK_A          _SB_MAKEMASK1(2)
+#define M_DUART_IMR_IN_A           _SB_MAKEMASK1(3)

 #define M_DUART_IMR_ALL_A          _SB_MAKEMASK(4, 0)
 
 #define M_DUART_IMR_ALL_A          _SB_MAKEMASK(4, 0)
 

-#define M_DUART_IMR_TX_B            _SB_MAKEMASK1(4)
-#define M_DUART_IMR_RX_B            _SB_MAKEMASK1(5)
-#define M_DUART_IMR_BRK_B           _SB_MAKEMASK1(6)
-#define M_DUART_IMR_IN_B            _SB_MAKEMASK1(7)
-#define M_DUART_IMR_ALL_B           _SB_MAKEMASK(4, 4)
+#define M_DUART_IMR_TX_B           _SB_MAKEMASK1(4)
+#define M_DUART_IMR_RX_B           _SB_MAKEMASK1(5)
+#define M_DUART_IMR_BRK_B          _SB_MAKEMASK1(6)
+#define M_DUART_IMR_IN_B           _SB_MAKEMASK1(7)
+#define M_DUART_IMR_ALL_B          _SB_MAKEMASK(4, 4)

 
 /*
  * DUART Channel A Interrupt Mask Register (Table 10-20)
 
 /*
  * DUART Channel A Interrupt Mask Register (Table 10-20)


@@ -293,12 +293,12 @@
  * Register: DUART_IMR_B
  */
 
  * Register: DUART_IMR_B
  */
 

-#define M_DUART_IMR_TX              _SB_MAKEMASK1(0)
-#define M_DUART_IMR_RX              _SB_MAKEMASK1(1)
-#define M_DUART_IMR_BRK             _SB_MAKEMASK1(2)
-#define M_DUART_IMR_IN              _SB_MAKEMASK1(3)
+#define M_DUART_IMR_TX             _SB_MAKEMASK1(0)
+#define M_DUART_IMR_RX             _SB_MAKEMASK1(1)
+#define M_DUART_IMR_BRK                    _SB_MAKEMASK1(2)
+#define M_DUART_IMR_IN             _SB_MAKEMASK1(3)

 #define M_DUART_IMR_ALL                    _SB_MAKEMASK(4, 0)
 #define M_DUART_IMR_ALL                    _SB_MAKEMASK(4, 0)

-#define M_DUART_IMR_RESERVED        _SB_MAKEMASK(4, 4)
+#define M_DUART_IMR_RESERVED       _SB_MAKEMASK(4, 4)

 
 
 /*
 
 
 /*


@@ -306,33 +306,33 @@
  * Register: DUART_SET_OPR
  */
 
  * Register: DUART_SET_OPR
  */
 

-#define M_DUART_SET_OPR0            _SB_MAKEMASK1(0)
-#define M_DUART_SET_OPR1            _SB_MAKEMASK1(1)
-#define M_DUART_SET_OPR2            _SB_MAKEMASK1(2)
-#define M_DUART_SET_OPR3            _SB_MAKEMASK1(3)
-#define M_DUART_OPSR_RESERVED       _SB_MAKEMASK(4, 4)
+#define M_DUART_SET_OPR0           _SB_MAKEMASK1(0)
+#define M_DUART_SET_OPR1           _SB_MAKEMASK1(1)
+#define M_DUART_SET_OPR2           _SB_MAKEMASK1(2)
+#define M_DUART_SET_OPR3           _SB_MAKEMASK1(3)
+#define M_DUART_OPSR_RESERVED      _SB_MAKEMASK(4, 4)

 
 /*
  * DUART Output Port Clear Register (Table 10-23)
  * Register: DUART_CLEAR_OPR
  */
 
 
 /*
  * DUART Output Port Clear Register (Table 10-23)
  * Register: DUART_CLEAR_OPR
  */
 

-#define M_DUART_CLR_OPR0            _SB_MAKEMASK1(0)
-#define M_DUART_CLR_OPR1            _SB_MAKEMASK1(1)
-#define M_DUART_CLR_OPR2            _SB_MAKEMASK1(2)
-#define M_DUART_CLR_OPR3            _SB_MAKEMASK1(3)
-#define M_DUART_OPCR_RESERVED       _SB_MAKEMASK(4, 4)
+#define M_DUART_CLR_OPR0           _SB_MAKEMASK1(0)
+#define M_DUART_CLR_OPR1           _SB_MAKEMASK1(1)
+#define M_DUART_CLR_OPR2           _SB_MAKEMASK1(2)
+#define M_DUART_CLR_OPR3           _SB_MAKEMASK1(3)
+#define M_DUART_OPCR_RESERVED      _SB_MAKEMASK(4, 4)

 
 /*
  * DUART Output Port RTS Register (Table 10-24)
  * Register: DUART_OUT_PORT
  */
 
 
 /*
  * DUART Output Port RTS Register (Table 10-24)
  * Register: DUART_OUT_PORT
  */
 

-#define M_DUART_OUT_PIN_SET0        _SB_MAKEMASK1(0)
-#define M_DUART_OUT_PIN_SET1        _SB_MAKEMASK1(1)
-#define M_DUART_OUT_PIN_CLR0        _SB_MAKEMASK1(2)
-#define M_DUART_OUT_PIN_CLR1        _SB_MAKEMASK1(3)
-#define M_DUART_OPRR_RESERVED       _SB_MAKEMASK(4, 4)
+#define M_DUART_OUT_PIN_SET0       _SB_MAKEMASK1(0)
+#define M_DUART_OUT_PIN_SET1       _SB_MAKEMASK1(1)
+#define M_DUART_OUT_PIN_CLR0       _SB_MAKEMASK1(2)
+#define M_DUART_OUT_PIN_CLR1       _SB_MAKEMASK1(3)
+#define M_DUART_OPRR_RESERVED      _SB_MAKEMASK(4, 4)

 
 #define M_DUART_OUT_PIN_SET(chan) \
     (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1)
 
 #define M_DUART_OUT_PIN_SET(chan) \
     (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1)


@@ -344,15 +344,15 @@
  * Full Interrupt Control Register
  */
 
  * Full Interrupt Control Register
  */
 

-#define S_DUART_SIG_FULL           _SB_MAKE64(0)
-#define M_DUART_SIG_FULL           _SB_MAKEMASK(4, S_DUART_SIG_FULL)
-#define V_DUART_SIG_FULL(x)        _SB_MAKEVALUE(x, S_DUART_SIG_FULL)
-#define G_DUART_SIG_FULL(x)        _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL)
+#define S_DUART_SIG_FULL          _SB_MAKE64(0)
+#define M_DUART_SIG_FULL          _SB_MAKEMASK(4, S_DUART_SIG_FULL)
+#define V_DUART_SIG_FULL(x)       _SB_MAKEVALUE(x, S_DUART_SIG_FULL)
+#define G_DUART_SIG_FULL(x)       _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL)

 
 

-#define S_DUART_INT_TIME           _SB_MAKE64(4)
-#define M_DUART_INT_TIME           _SB_MAKEMASK(4, S_DUART_INT_TIME)
-#define V_DUART_INT_TIME(x)        _SB_MAKEVALUE(x, S_DUART_INT_TIME)
-#define G_DUART_INT_TIME(x)        _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME)
+#define S_DUART_INT_TIME          _SB_MAKE64(4)
+#define M_DUART_INT_TIME          _SB_MAKEMASK(4, S_DUART_INT_TIME)
+#define V_DUART_INT_TIME(x)       _SB_MAKEVALUE(x, S_DUART_INT_TIME)
+#define G_DUART_INT_TIME(x)       _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME)

 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 
 #endif /* 1250 PASS2 || 112x PASS1 || 1480 */
 
 

diff --git a/arch/mips/include/asm/sibyte/sentosa.h b/arch/mips/include/asm/sibyte/sentosa.h
index 64c47874f32d83d1e69e91ff262596283a932c51..0351a46eebbd0ee6a6d12a2990dfa72e4da5eb36 100644 (file)
--- a/arch/mips/include/asm/sibyte/sentosa.h
+++ b/arch/mips/include/asm/sibyte/sentosa.h
@@ -30,11 +30,11 @@
 
 /* Generic bus chip selects */
 #ifdef CONFIG_SIBYTE_RHONE
 
 /* Generic bus chip selects */
 #ifdef CONFIG_SIBYTE_RHONE

-#define LEDS_CS         6
-#define LEDS_PHYS       0x1d0a0000
+#define LEDS_CS                6
+#define LEDS_PHYS      0x1d0a0000

 #endif
 
 /* GPIOs */
 #endif
 
 /* GPIOs */

-#define K_GPIO_DBG_LED  0
+#define K_GPIO_DBG_LED 0

 
 #endif /* __ASM_SIBYTE_SENTOSA_H */
 
 #endif /* __ASM_SIBYTE_SENTOSA_H */

diff --git a/arch/mips/include/asm/sibyte/swarm.h b/arch/mips/include/asm/sibyte/swarm.h
index 114d9d29ca9db4b60f717fe98521401582ebf45f..187cfb1f67cb22d6ce6f3f17eeb518cc4220d3b1 100644 (file)
--- a/arch/mips/include/asm/sibyte/swarm.h
+++ b/arch/mips/include/asm/sibyte/swarm.h
@@ -24,41 +24,41 @@
 #ifdef CONFIG_SIBYTE_SWARM
 #define SIBYTE_BOARD_NAME "BCM91250A (SWARM)"
 #define SIBYTE_HAVE_PCMCIA 1
 #ifdef CONFIG_SIBYTE_SWARM
 #define SIBYTE_BOARD_NAME "BCM91250A (SWARM)"
 #define SIBYTE_HAVE_PCMCIA 1

-#define SIBYTE_HAVE_IDE    1
+#define SIBYTE_HAVE_IDE           1

 #endif
 #ifdef CONFIG_SIBYTE_LITTLESUR
 #define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)"
 #define SIBYTE_HAVE_PCMCIA 0
 #endif
 #ifdef CONFIG_SIBYTE_LITTLESUR
 #define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)"
 #define SIBYTE_HAVE_PCMCIA 0

-#define SIBYTE_HAVE_IDE    1
+#define SIBYTE_HAVE_IDE           1

 #define SIBYTE_DEFAULT_CONSOLE "cfe0"
 #endif
 #ifdef CONFIG_SIBYTE_CRHONE
 #define SIBYTE_BOARD_NAME "BCM91125C (CRhone)"
 #define SIBYTE_HAVE_PCMCIA 0
 #define SIBYTE_DEFAULT_CONSOLE "cfe0"
 #endif
 #ifdef CONFIG_SIBYTE_CRHONE
 #define SIBYTE_BOARD_NAME "BCM91125C (CRhone)"
 #define SIBYTE_HAVE_PCMCIA 0

-#define SIBYTE_HAVE_IDE    0
+#define SIBYTE_HAVE_IDE           0

 #endif
 #ifdef CONFIG_SIBYTE_CRHINE
 #define SIBYTE_BOARD_NAME "BCM91120C (CRhine)"
 #define SIBYTE_HAVE_PCMCIA 0
 #endif
 #ifdef CONFIG_SIBYTE_CRHINE
 #define SIBYTE_BOARD_NAME "BCM91120C (CRhine)"
 #define SIBYTE_HAVE_PCMCIA 0

-#define SIBYTE_HAVE_IDE    0
+#define SIBYTE_HAVE_IDE           0

 #endif
 
 /* Generic bus chip selects */
 #endif
 
 /* Generic bus chip selects */

-#define LEDS_CS         3
-#define LEDS_PHYS       0x100a0000
+#define LEDS_CS                3
+#define LEDS_PHYS      0x100a0000

 
 #ifdef SIBYTE_HAVE_IDE
 
 #ifdef SIBYTE_HAVE_IDE

-#define IDE_CS          4
-#define IDE_PHYS        0x100b0000
-#define K_GPIO_GB_IDE   4
-#define K_INT_GB_IDE    (K_INT_GPIO_0 + K_GPIO_GB_IDE)
+#define IDE_CS         4
+#define IDE_PHYS       0x100b0000
+#define K_GPIO_GB_IDE  4
+#define K_INT_GB_IDE   (K_INT_GPIO_0 + K_GPIO_GB_IDE)

 #endif
 
 #ifdef SIBYTE_HAVE_PCMCIA
 #endif
 
 #ifdef SIBYTE_HAVE_PCMCIA

-#define PCMCIA_CS       6
-#define PCMCIA_PHYS     0x11000000
+#define PCMCIA_CS      6
+#define PCMCIA_PHYS    0x11000000

 #define K_GPIO_PC_READY 9
 #define K_GPIO_PC_READY 9

-#define K_INT_PC_READY  (K_INT_GPIO_0 + K_GPIO_PC_READY)
+#define K_INT_PC_READY (K_INT_GPIO_0 + K_GPIO_PC_READY)

 #endif
 
 #endif /* __ASM_SIBYTE_SWARM_H */
 #endif
 
 #endif /* __ASM_SIBYTE_SWARM_H */

diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index f33b5fd6972b441d3b3a7f342a126b488dfbc12d..eb60087584844381a717bf6dc1ffdf39508dcf1a 100644 (file)
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -26,7 +26,7 @@ extern cpumask_t cpu_sibling_map[];
 #define raw_smp_processor_id() (current_thread_info()->cpu)
 
 /* Map from cpu id to sequential logical cpu number.  This will only
 #define raw_smp_processor_id() (current_thread_info()->cpu)
 
 /* Map from cpu id to sequential logical cpu number.  This will only

-   not be idempotent when cpus failed to come on-line.  */
+   not be idempotent when cpus failed to come on-line. */

 extern int __cpu_number_map[NR_CPUS];
 #define cpu_number_map(cpu)  __cpu_number_map[cpu]
 
 extern int __cpu_number_map[NR_CPUS];
 #define cpu_number_map(cpu)  __cpu_number_map[cpu]
 


@@ -36,7 +36,7 @@ extern int __cpu_logical_map[NR_CPUS];
 
 #define NO_PROC_ID     (-1)
 
 
 #define NO_PROC_ID     (-1)
 

-#define SMP_RESCHEDULE_YOURSELF        0x1     /* XXX braindead */
+#define SMP_RESCHEDULE_YOURSELF 0x1    /* XXX braindead */

 #define SMP_CALL_FUNCTION      0x2
 /* Octeon - Tell another core to flush its icache */
 #define SMP_ICACHE_FLUSH       0x4
 #define SMP_CALL_FUNCTION      0x2
 /* Octeon - Tell another core to flush its icache */
 #define SMP_ICACHE_FLUSH       0x4


@@ -62,14 +62,14 @@ static inline void smp_send_reschedule(int cpu)
 #ifdef CONFIG_HOTPLUG_CPU
 static inline int __cpu_disable(void)
 {
 #ifdef CONFIG_HOTPLUG_CPU
 static inline int __cpu_disable(void)
 {

-       extern struct plat_smp_ops *mp_ops;     /* private */
+       extern struct plat_smp_ops *mp_ops;     /* private */

 
        return mp_ops->cpu_disable();
 }
 
 static inline void __cpu_die(unsigned int cpu)
 {
 
        return mp_ops->cpu_disable();
 }
 
 static inline void __cpu_die(unsigned int cpu)
 {

-       extern struct plat_smp_ops *mp_ops;     /* private */
+       extern struct plat_smp_ops *mp_ops;     /* private */

 
        mp_ops->cpu_die(cpu);
 }
 
        mp_ops->cpu_die(cpu);
 }


@@ -81,14 +81,14 @@ extern asmlinkage void smp_call_function_interrupt(void);
 
 static inline void arch_send_call_function_single_ipi(int cpu)
 {
 
 static inline void arch_send_call_function_single_ipi(int cpu)
 {

-       extern struct plat_smp_ops *mp_ops;     /* private */
+       extern struct plat_smp_ops *mp_ops;     /* private */

 
        mp_ops->send_ipi_mask(&cpumask_of_cpu(cpu), SMP_CALL_FUNCTION);
 }
 
 static inline void arch_send_call_function_ipi_mask(const struct cpumask *mask)
 {
 
        mp_ops->send_ipi_mask(&cpumask_of_cpu(cpu), SMP_CALL_FUNCTION);
 }
 
 static inline void arch_send_call_function_ipi_mask(const struct cpumask *mask)
 {

-       extern struct plat_smp_ops *mp_ops;     /* private */
+       extern struct plat_smp_ops *mp_ops;     /* private */

 
        mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION);
 }
 
        mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION);
 }

diff --git a/arch/mips/include/asm/smtc.h b/arch/mips/include/asm/smtc.h
index 8935426a56ab69c4a0b444b6905819262b5a4f97..e56b439b7871708660d76d9ce96b5c73d22a55f9 100644 (file)
--- a/arch/mips/include/asm/smtc.h
+++ b/arch/mips/include/asm/smtc.h
@@ -14,8 +14,8 @@
 
 extern unsigned int smtc_status;
 
 
 extern unsigned int smtc_status;
 

-#define SMTC_TLB_SHARED        0x00000001
-#define SMTC_MTC_ACTIVE        0x00000002
+#define SMTC_TLB_SHARED 0x00000001
+#define SMTC_MTC_ACTIVE 0x00000002

 
 /*
  * TLB/ASID Management information
 
 /*
  * TLB/ASID Management information

diff --git a/arch/mips/include/asm/sn/addrs.h b/arch/mips/include/asm/sn/addrs.h
index 2367b56dcdef8badffd247e973524007cd859719..66814f8ba8e8c3f082e7372fee20c7f0b169844e 100644 (file)
--- a/arch/mips/include/asm/sn/addrs.h
+++ b/arch/mips/include/asm/sn/addrs.h
@@ -88,8 +88,8 @@
 
 #define SWIN_SIZE_BITS         24
 #define SWIN_SIZE              (UINT64_CAST 1 << 24)
 
 #define SWIN_SIZE_BITS         24
 #define SWIN_SIZE              (UINT64_CAST 1 << 24)

-#define        SWIN_SIZEMASK           (SWIN_SIZE - 1)
-#define        SWIN_WIDGET_MASK        0xF
+#define SWIN_SIZEMASK          (SWIN_SIZE - 1)
+#define SWIN_WIDGET_MASK       0xF

 
 /*
  * Convert smallwindow address to xtalk address.
 
 /*
  * Convert smallwindow address to xtalk address.


@@ -97,8 +97,8 @@
  * 'addr' can be physical or virtual address, but will be converted
  * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
  */
  * 'addr' can be physical or virtual address, but will be converted
  * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
  */

-#define        SWIN_WIDGETADDR(addr)   ((addr) & SWIN_SIZEMASK)
-#define        SWIN_WIDGETNUM(addr)    (((addr)  >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
+#define SWIN_WIDGETADDR(addr)  ((addr) & SWIN_SIZEMASK)
+#define SWIN_WIDGETNUM(addr)   (((addr)  >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)

 /*
  * Verify if addr belongs to small window address on node with "nasid"
  *
 /*
  * Verify if addr belongs to small window address on node with "nasid"
  *


@@ -108,7 +108,7 @@
  *
  *
  */
  *
  *
  */

-#define        NODE_SWIN_ADDR(nasid, addr)     \
+#define NODE_SWIN_ADDR(nasid, addr)    \

                (((addr) >= NODE_SWIN_BASE(nasid, 0))  && \
                 ((addr) <  (NODE_SWIN_BASE(nasid, HUB_NUM_WIDGET) + SWIN_SIZE)\
                 ))
                (((addr) >= NODE_SWIN_BASE(nasid, 0))  && \
                 ((addr) <  (NODE_SWIN_BASE(nasid, HUB_NUM_WIDGET) + SWIN_SIZE)\
                 ))


@@ -150,7 +150,7 @@
 
 #endif
 
 
 #endif
 

-#define        HUB_REGISTER_WIDGET     1
+#define HUB_REGISTER_WIDGET    1

 #define IALIAS_BASE            NODE_SWIN_BASE(0, HUB_REGISTER_WIDGET)
 #define IALIAS_SIZE            0x800000        /* 8 Megabytes */
 #define IS_IALIAS(_a)          (((_a) >= IALIAS_BASE) &&               \
 #define IALIAS_BASE            NODE_SWIN_BASE(0, HUB_REGISTER_WIDGET)
 #define IALIAS_SIZE            0x800000        /* 8 Megabytes */
 #define IS_IALIAS(_a)          (((_a) >= IALIAS_BASE) &&               \


@@ -174,16 +174,16 @@
  *   WARNING: They won't work in assembler.
  *
  *   BDDIR_ENTRY_LO returns the address of the low double-word of the dir
  *   WARNING: They won't work in assembler.
  *
  *   BDDIR_ENTRY_LO returns the address of the low double-word of the dir

- *                  entry corresponding to a physical (Cac or Uncac) address.
+ *                 entry corresponding to a physical (Cac or Uncac) address.

  *   BDDIR_ENTRY_HI returns the address of the high double-word of the entry.
  *   BDPRT_ENTRY    returns the address of the double-word protection entry
  *   BDDIR_ENTRY_HI returns the address of the high double-word of the entry.
  *   BDPRT_ENTRY    returns the address of the double-word protection entry

- *                  corresponding to the page containing the physical address.
+ *                 corresponding to the page containing the physical address.

  *   BDPRT_ENTRY_S  Stores the value into the protection entry.
  *   BDPRT_ENTRY_L  Load the value from the protection entry.
  *   BDECC_ENTRY    returns the address of the ECC byte corresponding to a
  *   BDPRT_ENTRY_S  Stores the value into the protection entry.
  *   BDPRT_ENTRY_L  Load the value from the protection entry.
  *   BDECC_ENTRY    returns the address of the ECC byte corresponding to a

- *                  double-word at a specified physical address.
+ *                 double-word at a specified physical address.

  *   BDECC_ENTRY_H  returns the address of the two ECC bytes corresponding to a
  *   BDECC_ENTRY_H  returns the address of the two ECC bytes corresponding to a

- *                  quad-word at a specified physical address.
+ *                 quad-word at a specified physical address.

  */
 #define NODE_BDOOR_BASE(_n)    (NODE_HSPEC_BASE(_n) + (NODE_ADDRSPACE_SIZE/2))
 
  */
 #define NODE_BDOOR_BASE(_n)    (NODE_HSPEC_BASE(_n) + (NODE_ADDRSPACE_SIZE/2))
 


@@ -226,11 +226,11 @@
 #define BDADDR_IS_DIR(_ba)     ((UINT64_CAST  (_ba) & 0x200) != 0)
 #define BDADDR_IS_PRT(_ba)     ((UINT64_CAST  (_ba) & 0x200) == 0)
 
 #define BDADDR_IS_DIR(_ba)     ((UINT64_CAST  (_ba) & 0x200) != 0)
 #define BDADDR_IS_PRT(_ba)     ((UINT64_CAST  (_ba) & 0x200) == 0)
 

-#define BDDIR_TO_MEM(_ba)      (UINT64_CAST (_ba) & NASID_MASK            | \
+#define BDDIR_TO_MEM(_ba)      (UINT64_CAST (_ba) & NASID_MASK            | \

                                 (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2  | \
                                 (UINT64_CAST(_ba) & 0x1f << 4) << 3)
 
                                 (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2  | \
                                 (UINT64_CAST(_ba) & 0x1f << 4) << 3)
 

-#define BDPRT_TO_MEM(_ba)      (UINT64_CAST (_ba) & NASID_MASK     | \
+#define BDPRT_TO_MEM(_ba)      (UINT64_CAST (_ba) & NASID_MASK     | \

                                 (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2)
 
 #define BDECC_TO_MEM(_ba)      (UINT64_CAST (_ba) & NASID_MASK     | \
                                 (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2)
 
 #define BDECC_TO_MEM(_ba)      (UINT64_CAST (_ba) & NASID_MASK     | \


@@ -251,23 +251,23 @@
 /*
  * WARNING:
  *     When certain Hub chip workaround are defined, it's not sufficient
 /*
  * WARNING:
  *     When certain Hub chip workaround are defined, it's not sufficient

- *     to dereference the *_HUB_ADDR() macros.  You should instead use
+ *     to dereference the *_HUB_ADDR() macros.  You should instead use

  *     HUB_L() and HUB_S() if you must deal with pointers to hub registers.
  *     Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
  *     They're always safe.
  */
 #define LOCAL_HUB_ADDR(_x)     (HUBREG_CAST (IALIAS_BASE + (_x)))
  *     HUB_L() and HUB_S() if you must deal with pointers to hub registers.
  *     Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
  *     They're always safe.
  */
 #define LOCAL_HUB_ADDR(_x)     (HUBREG_CAST (IALIAS_BASE + (_x)))

-#define REMOTE_HUB_ADDR(_n, _x)        (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +   \
+#define REMOTE_HUB_ADDR(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +  \

                                              0x800000 + (_x)))
 #ifdef CONFIG_SGI_IP27
                                              0x800000 + (_x)))
 #ifdef CONFIG_SGI_IP27

-#define REMOTE_HUB_PI_ADDR(_n, _sn, _x)        (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +   \
+#define REMOTE_HUB_PI_ADDR(_n, _sn, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +  \

                                              0x800000 + (_x)))
 #endif /* CONFIG_SGI_IP27 */
 
 #ifndef __ASSEMBLY__
 
 #define HUB_L(_a)                      *(_a)
                                              0x800000 + (_x)))
 #endif /* CONFIG_SGI_IP27 */
 
 #ifndef __ASSEMBLY__
 
 #define HUB_L(_a)                      *(_a)

-#define        HUB_S(_a, _d)                   *(_a) = (_d)
+#define HUB_S(_a, _d)                  *(_a) = (_d)

 
 #define LOCAL_HUB_L(_r)                        HUB_L(LOCAL_HUB_ADDR(_r))
 #define LOCAL_HUB_S(_r, _d)            HUB_S(LOCAL_HUB_ADDR(_r), (_d))
 
 #define LOCAL_HUB_L(_r)                        HUB_L(LOCAL_HUB_ADDR(_r))
 #define LOCAL_HUB_S(_r, _d)            HUB_S(LOCAL_HUB_ADDR(_r), (_d))


@@ -330,14 +330,14 @@
 
 #define KLI_LAUNCH             0               /* Dir. entries */
 #define KLI_KLCONFIG           1
 
 #define KLI_LAUNCH             0               /* Dir. entries */
 #define KLI_KLCONFIG           1

-#define        KLI_NMI                 2
+#define KLI_NMI                        2

 #define KLI_GDA                        3
 #define KLI_FREEMEM            4
 #define KLI_GDA                        3
 #define KLI_FREEMEM            4

-#define        KLI_SYMMON_STK          5
+#define KLI_SYMMON_STK         5

 #define KLI_PI_ERROR           6
 #define KLI_KERN_VARS          7
 #define KLI_PI_ERROR           6
 #define KLI_KERN_VARS          7

-#define        KLI_KERN_XP             8
-#define        KLI_KERN_PARTID         9
+#define KLI_KERN_XP            8
+#define KLI_KERN_PARTID                9

 
 #ifndef __ASSEMBLY__
 
 
 #ifndef __ASSEMBLY__
 


@@ -350,8 +350,8 @@
 #define KLD_SYMMON_STK(nasid)  (KLD_BASE(nasid) + KLI_SYMMON_STK)
 #define KLD_FREEMEM(nasid)     (KLD_BASE(nasid) + KLI_FREEMEM)
 #define KLD_KERN_VARS(nasid)   (KLD_BASE(nasid) + KLI_KERN_VARS)
 #define KLD_SYMMON_STK(nasid)  (KLD_BASE(nasid) + KLI_SYMMON_STK)
 #define KLD_FREEMEM(nasid)     (KLD_BASE(nasid) + KLI_FREEMEM)
 #define KLD_KERN_VARS(nasid)   (KLD_BASE(nasid) + KLI_KERN_VARS)

-#define        KLD_KERN_XP(nasid)      (KLD_BASE(nasid) + KLI_KERN_XP)
-#define        KLD_KERN_PARTID(nasid)  (KLD_BASE(nasid) + KLI_KERN_PARTID)
+#define KLD_KERN_XP(nasid)     (KLD_BASE(nasid) + KLI_KERN_XP)
+#define KLD_KERN_PARTID(nasid) (KLD_BASE(nasid) + KLI_KERN_PARTID)

 
 #define LAUNCH_OFFSET(nasid, slice)                                    \
        (KLD_LAUNCH(nasid)->offset +                                    \
 
 #define LAUNCH_OFFSET(nasid, slice)                                    \
        (KLD_LAUNCH(nasid)->offset +                                    \


@@ -365,7 +365,7 @@
         KLD_NMI(nasid)->stride * (slice))
 #define NMI_ADDR(nasid, slice)                                         \
        TO_NODE_UNCAC((nasid), SN_NMI_OFFSET(nasid, slice))
         KLD_NMI(nasid)->stride * (slice))
 #define NMI_ADDR(nasid, slice)                                         \
        TO_NODE_UNCAC((nasid), SN_NMI_OFFSET(nasid, slice))

-#define NMI_SIZE(nasid)        KLD_NMI(nasid)->size
+#define NMI_SIZE(nasid) KLD_NMI(nasid)->size

 
 #define KLCONFIG_OFFSET(nasid) KLD_KLCONFIG(nasid)->offset
 #define KLCONFIG_ADDR(nasid)                                           \
 
 #define KLCONFIG_OFFSET(nasid) KLD_KLCONFIG(nasid)->offset
 #define KLCONFIG_ADDR(nasid)                                           \


@@ -390,8 +390,8 @@
 /* loading symmon 4k below UNIX. the arcs loader needs the topaddr for a
  * relocatable program
  */
 /* loading symmon 4k below UNIX. the arcs loader needs the topaddr for a
  * relocatable program
  */

-#define        UNIX_DEBUG_LOADADDR     0x300000
-#define        SYMMON_LOADADDR(nasid)                                          \
+#define UNIX_DEBUG_LOADADDR    0x300000
+#define SYMMON_LOADADDR(nasid)                                         \

        TO_NODE(nasid, PHYS_TO_K0(UNIX_DEBUG_LOADADDR - 0x1000))
 
 #define FREEMEM_OFFSET(nasid)  KLD_FREEMEM(nasid)->offset
        TO_NODE(nasid, PHYS_TO_K0(UNIX_DEBUG_LOADADDR - 0x1000))
 
 #define FREEMEM_OFFSET(nasid)  KLD_FREEMEM(nasid)->offset


@@ -420,8 +420,8 @@
 #define KERN_VARS_ADDR(nasid)  KLD_KERN_VARS(nasid)->pointer
 #define KERN_VARS_SIZE(nasid)  KLD_KERN_VARS(nasid)->size
 
 #define KERN_VARS_ADDR(nasid)  KLD_KERN_VARS(nasid)->pointer
 #define KERN_VARS_SIZE(nasid)  KLD_KERN_VARS(nasid)->size
 

-#define        KERN_XP_ADDR(nasid)     KLD_KERN_XP(nasid)->pointer
-#define        KERN_XP_SIZE(nasid)     KLD_KERN_XP(nasid)->size
+#define KERN_XP_ADDR(nasid)    KLD_KERN_XP(nasid)->pointer
+#define KERN_XP_SIZE(nasid)    KLD_KERN_XP(nasid)->size

 
 #define GPDA_ADDR(nasid)       TO_NODE_CAC(nasid, GPDA_OFFSET)
 
 
 #define GPDA_ADDR(nasid)       TO_NODE_CAC(nasid, GPDA_OFFSET)
 

diff --git a/arch/mips/include/asm/sn/agent.h b/arch/mips/include/asm/sn/agent.h
index dc81114d4742494d366e5f566dbd6a3a61286f10..e33d0929301917e4812422bd0648a5928b6da863 100644 (file)
--- a/arch/mips/include/asm/sn/agent.h
+++ b/arch/mips/include/asm/sn/agent.h
@@ -25,21 +25,21 @@
  */
 
 #if defined(CONFIG_SGI_IP27)
  */
 
 #if defined(CONFIG_SGI_IP27)

-#define HUB_NIC_ADDR(_cpuid)                                              \
-       REMOTE_HUB_ADDR(COMPACT_TO_NASID_NODEID(cpu_to_node(_cpuid)),       \
+#define HUB_NIC_ADDR(_cpuid)                                              \
+       REMOTE_HUB_ADDR(COMPACT_TO_NASID_NODEID(cpu_to_node(_cpuid)),       \

                MD_MLAN_CTL)
 #endif
 
                MD_MLAN_CTL)
 #endif
 

-#define SET_HUB_NIC(_my_cpuid, _val)                                      \
+#define SET_HUB_NIC(_my_cpuid, _val)                                      \

        (HUB_S(HUB_NIC_ADDR(_my_cpuid), (_val)))
 
        (HUB_S(HUB_NIC_ADDR(_my_cpuid), (_val)))
 

-#define SET_MY_HUB_NIC(_v)                                                \
+#define SET_MY_HUB_NIC(_v)                                                \

        SET_HUB_NIC(cpuid(), (_v))
 
        SET_HUB_NIC(cpuid(), (_v))
 

-#define GET_HUB_NIC(_my_cpuid)                                                    \
+#define GET_HUB_NIC(_my_cpuid)                                            \

        (HUB_L(HUB_NIC_ADDR(_my_cpuid)))
 
        (HUB_L(HUB_NIC_ADDR(_my_cpuid)))
 

-#define GET_MY_HUB_NIC()                                                  \
+#define GET_MY_HUB_NIC()                                                  \

        GET_HUB_NIC(cpuid())
 
 #endif /* _ASM_SGI_SN_AGENT_H */
        GET_HUB_NIC(cpuid())
 
 #endif /* _ASM_SGI_SN_AGENT_H */

diff --git a/arch/mips/include/asm/sn/arch.h b/arch/mips/include/asm/sn/arch.h
index bd75945e10fffdec2715b444e71a694561dfb3f9..471e6870d8769aa4af1915b2ec5fc67260dcccd6 100644 (file)
--- a/arch/mips/include/asm/sn/arch.h
+++ b/arch/mips/include/asm/sn/arch.h
@@ -28,14 +28,14 @@ typedef u64 hubreg_t;
 #define INVALID_CNODEID                (cnodeid_t)-1
 #define INVALID_PNODEID                (pnodeid_t)-1
 #define INVALID_MODULE         (moduleid_t)-1
 #define INVALID_CNODEID                (cnodeid_t)-1
 #define INVALID_PNODEID                (pnodeid_t)-1
 #define INVALID_MODULE         (moduleid_t)-1

-#define        INVALID_PARTID          (partid_t)-1
+#define INVALID_PARTID         (partid_t)-1

 
 extern nasid_t get_nasid(void);
 extern cnodeid_t get_cpu_cnode(cpuid_t);
 extern int get_cpu_slice(cpuid_t);
 
 /*
 
 extern nasid_t get_nasid(void);
 extern cnodeid_t get_cpu_cnode(cpuid_t);
 extern int get_cpu_slice(cpuid_t);
 
 /*

- * NO ONE should access these arrays directly.  The only reason we refer to
+ * NO ONE should access these arrays directly. The only reason we refer to

  * them here is to avoid the procedure call that would be required in the
  * macros below.  (Really want private data members here :-)
  */
  * them here is to avoid the procedure call that would be required in the
  * macros below.  (Really want private data members here :-)
  */


@@ -44,12 +44,12 @@ extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES];
 
 /*
  * These macros are used by various parts of the kernel to convert
 
 /*
  * These macros are used by various parts of the kernel to convert

- * between the three different kinds of node numbering.   At least some
+ * between the three different kinds of node numbering.          At least some

  * of them may change to procedure calls in the future, but the macros
  * will continue to work.  Don't use the arrays above directly.
  */
 
  * of them may change to procedure calls in the future, but the macros
  * will continue to work.  Don't use the arrays above directly.
  */
 

-#define        NASID_TO_REGION(nnode)          \
+#define NASID_TO_REGION(nnode)         \

     ((nnode) >> \
      (is_fine_dirmode() ? NASID_TO_FINEREG_SHFT : NASID_TO_COARSEREG_SHFT))
 
     ((nnode) >> \
      (is_fine_dirmode() ? NASID_TO_FINEREG_SHFT : NASID_TO_COARSEREG_SHFT))
 

diff --git a/arch/mips/include/asm/sn/fru.h b/arch/mips/include/asm/sn/fru.h
index b3e3606723b77898114aeac611f85722e1d25c89..bbb83257c8e23f75c8ddbd3a3bcc53dd2cdcd47f 100644 (file)
--- a/arch/mips/include/asm/sn/fru.h
+++ b/arch/mips/include/asm/sn/fru.h
@@ -21,24 +21,24 @@ typedef struct kf_mem_s {
                                     * is this necessary ?
                                     */
        confidence_t km_dimm[MAX_DIMMS];
                                     * is this necessary ?
                                     */
        confidence_t km_dimm[MAX_DIMMS];

-                                   /* confidence level that dimm[i] is bad
+                                   /* confidence level that dimm[i] is bad

                                     *I think this is the right number
                                     */
 
 } kf_mem_t;
 
 typedef struct kf_cpu_s {
                                     *I think this is the right number
                                     */
 
 } kf_mem_t;
 
 typedef struct kf_cpu_s {

-       confidence_t    kc_confidence; /* confidence level that cpu is bad */
-       confidence_t    kc_icache; /* confidence level that instr. cache is bad */
-       confidence_t    kc_dcache; /* confidence level that data   cache is bad */
-       confidence_t    kc_scache; /* confidence level that sec.   cache is bad */
+       confidence_t    kc_confidence; /* confidence level that cpu is bad */
+       confidence_t    kc_icache; /* confidence level that instr. cache is bad */
+       confidence_t    kc_dcache; /* confidence level that data   cache is bad */
+       confidence_t    kc_scache; /* confidence level that sec.   cache is bad */

        confidence_t    kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */
 } kf_cpu_t;
 
 typedef struct kf_pci_bus_s {
        confidence_t    kpb_belief;     /* confidence level  that the  pci bus is bad */
        confidence_t    kpb_pcidev_belief[MAX_PCIDEV];
        confidence_t    kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */
 } kf_cpu_t;
 
 typedef struct kf_pci_bus_s {
        confidence_t    kpb_belief;     /* confidence level  that the  pci bus is bad */
        confidence_t    kpb_pcidev_belief[MAX_PCIDEV];

-                                       /* confidence level that the pci dev is bad */
+                                       /* confidence level that the pci dev is bad */

 } kf_pci_bus_t;
 
 #endif /* __ASM_SN_FRU_H */
 } kf_pci_bus_t;
 
 #endif /* __ASM_SN_FRU_H */

diff --git a/arch/mips/include/asm/sn/gda.h b/arch/mips/include/asm/sn/gda.h
index 9cb6ff770915d82444e363be31f2e11b552d68df..85fa1b5f639dea84555165cdff02819dd6cb812e 100644 (file)
--- a/arch/mips/include/asm/sn/gda.h
+++ b/arch/mips/include/asm/sn/gda.h
@@ -8,7 +8,7 @@
  * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
  *
  * gda.h -- Contains the data structure for the global data area,
  * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
  *
  * gda.h -- Contains the data structure for the global data area,

- *     The GDA contains information communicated between the
+ *     The GDA contains information communicated between the

  *     PROM, SYMMON, and the kernel.
  */
 #ifndef _ASM_SN_GDA_H
  *     PROM, SYMMON, and the kernel.
  */
 #ifndef _ASM_SN_GDA_H


@@ -23,8 +23,8 @@
  *
  * Version #   | Change
  * -------------+-------------------------------------------------------
  *
  * Version #   | Change
  * -------------+-------------------------------------------------------

- *     1       | Initial SN0 version
- *     2       | Prom sets g_partid field to the partition number. 0 IS
+ *     1       | Initial SN0 version
+ *     2       | Prom sets g_partid field to the partition number. 0 IS

  *             | a valid partition #.
  */
 
  *             | a valid partition #.
  */
 


@@ -60,7 +60,7 @@ typedef struct gda {
                                /* Pointer to a mask of nodes with copies
                                 * of the kernel. */
        char    g_padding[56];  /* pad out to 128 bytes */
                                /* Pointer to a mask of nodes with copies
                                 * of the kernel. */
        char    g_padding[56];  /* pad out to 128 bytes */

-       nasid_t g_nasidtable[MAX_COMPACT_NODES]; /* NASID of each node,
+       nasid_t g_nasidtable[MAX_COMPACT_NODES]; /* NASID of each node,

                                                  * indexed by cnodeid.
                                                  */
 } gda_t;
                                                  * indexed by cnodeid.
                                                  */
 } gda_t;


@@ -74,7 +74,7 @@ typedef struct gda {
  *             revisions assume GDA is NOT set up, and read partition
  *             information from the board info.
  */
  *             revisions assume GDA is NOT set up, and read partition
  *             information from the board info.
  */

-#define        PART_GDA_VERSION        2
+#define PART_GDA_VERSION       2

 
 /*
  * The following requests can be sent to the PROM during startup.
 
 /*
  * The following requests can be sent to the PROM during startup.


@@ -83,17 +83,17 @@ typedef struct gda {
 #define PROMOP_MAGIC           0x0ead0000
 #define PROMOP_MAGIC_MASK      0x0fff0000
 
 #define PROMOP_MAGIC           0x0ead0000
 #define PROMOP_MAGIC_MASK      0x0fff0000
 

-#define PROMOP_BIST_SHIFT       11
-#define PROMOP_BIST_MASK        (0x3 << 11)
+#define PROMOP_BIST_SHIFT      11
+#define PROMOP_BIST_MASK       (0x3 << 11)

 
 #define PROMOP_REG             PI_ERR_STACK_ADDR_A
 
 #define PROMOP_INVALID         (PROMOP_MAGIC | 0x00)
 
 #define PROMOP_REG             PI_ERR_STACK_ADDR_A
 
 #define PROMOP_INVALID         (PROMOP_MAGIC | 0x00)

-#define PROMOP_HALT             (PROMOP_MAGIC | 0x10)
-#define PROMOP_POWERDOWN        (PROMOP_MAGIC | 0x20)
-#define PROMOP_RESTART          (PROMOP_MAGIC | 0x30)
-#define PROMOP_REBOOT           (PROMOP_MAGIC | 0x40)
-#define PROMOP_IMODE            (PROMOP_MAGIC | 0x50)
+#define PROMOP_HALT            (PROMOP_MAGIC | 0x10)
+#define PROMOP_POWERDOWN       (PROMOP_MAGIC | 0x20)
+#define PROMOP_RESTART         (PROMOP_MAGIC | 0x30)
+#define PROMOP_REBOOT          (PROMOP_MAGIC | 0x40)
+#define PROMOP_IMODE           (PROMOP_MAGIC | 0x50)

 
 #define PROMOP_CMD_MASK                0x00f0
 #define PROMOP_OPTIONS_MASK    0xfff0
 
 #define PROMOP_CMD_MASK                0x00f0
 #define PROMOP_OPTIONS_MASK    0xfff0

diff --git a/arch/mips/include/asm/sn/intr.h b/arch/mips/include/asm/sn/intr.h
index 6718b644b970897bff8b771fb5a2c0101cad2504..fc1348193957a3a7a608fb614a56f07230eef1e3 100644 (file)
--- a/arch/mips/include/asm/sn/intr.h
+++ b/arch/mips/include/asm/sn/intr.h
@@ -14,8 +14,8 @@
 #define INT_PEND0_BASELVL      0
 #define INT_PEND1_BASELVL      64
 
 #define INT_PEND0_BASELVL      0
 #define INT_PEND1_BASELVL      64
 

-#define        N_INTPENDJUNK_BITS      8
-#define        INTPENDJUNK_CLRBIT      0x80
+#define N_INTPENDJUNK_BITS     8
+#define INTPENDJUNK_CLRBIT     0x80

 
 /*
  * Macros to manipulate the interrupt register on the calling hub chip.
 
 /*
  * Macros to manipulate the interrupt register on the calling hub chip.


@@ -32,7 +32,7 @@
  * We do an uncached load of the int_pend0 register to ensure this.
  */
 
  * We do an uncached load of the int_pend0 register to ensure this.
  */
 

-#define LOCAL_HUB_CLR_INTR(level)                              \
+#define LOCAL_HUB_CLR_INTR(level)                              \

 do {                                                           \
        LOCAL_HUB_S(PI_INT_PEND_MOD, (level));                  \
        LOCAL_HUB_L(PI_INT_PEND0);                              \
 do {                                                           \
        LOCAL_HUB_S(PI_INT_PEND_MOD, (level));                  \
        LOCAL_HUB_L(PI_INT_PEND0);                              \


@@ -40,7 +40,7 @@ do {                                                          \
 
 #define REMOTE_HUB_CLR_INTR(hub, level)                                \
 do {                                                           \
 
 #define REMOTE_HUB_CLR_INTR(hub, level)                                \
 do {                                                           \

-       nasid_t  __hub = (hub);                                 \
+       nasid_t  __hub = (hub);                                 \

                                                                \
        REMOTE_HUB_S(__hub, PI_INT_PEND_MOD, (level));          \
        REMOTE_HUB_L(__hub, PI_INT_PEND0);                      \
                                                                \
        REMOTE_HUB_S(__hub, PI_INT_PEND_MOD, (level));          \
        REMOTE_HUB_L(__hub, PI_INT_PEND0);                      \


@@ -102,8 +102,8 @@ do {                                                                \
 #define LLP_PFAIL_INTR_A       41      /* see ml/SN/SN0/sysctlr.c */
 #define LLP_PFAIL_INTR_B       42
 
 #define LLP_PFAIL_INTR_A       41      /* see ml/SN/SN0/sysctlr.c */
 #define LLP_PFAIL_INTR_B       42
 

-#define        TLB_INTR_A              43      /* used for tlb flush random */
-#define        TLB_INTR_B              44
+#define TLB_INTR_A             43      /* used for tlb flush random */
+#define TLB_INTR_B             44

 
 #define IP27_INTR_0            45      /* Reserved for PROM use */
 #define IP27_INTR_1            46      /* do not use in Kernel */
 
 #define IP27_INTR_0            45      /* Reserved for PROM use */
 #define IP27_INTR_1            46      /* do not use in Kernel */


@@ -116,8 +116,8 @@ do {                                                                \
 
 #define BRIDGE_ERROR_INTR      53      /* Setup by PROM to catch       */
                                        /* Bridge Errors */
 
 #define BRIDGE_ERROR_INTR      53      /* Setup by PROM to catch       */
                                        /* Bridge Errors */

-#define        DEBUG_INTR_A            54
-#define        DEBUG_INTR_B            55      /* Used by symmon to stop all cpus */
+#define DEBUG_INTR_A           54
+#define DEBUG_INTR_B           55      /* Used by symmon to stop all cpus */

 #define IO_ERROR_INTR          57      /* Setup by PROM */
 #define CLK_ERR_INTR           58
 #define COR_ERR_INTR_A         59
 #define IO_ERROR_INTR          57      /* Setup by PROM */
 #define CLK_ERR_INTR           58
 #define COR_ERR_INTR_A         59

diff --git a/arch/mips/include/asm/sn/io.h b/arch/mips/include/asm/sn/io.h
index 24c6775fbb0fe9e055acbffaf3d272c4e3a3d9ba..d5174d04538cf50792e994f2555db4488e036e7f 100644 (file)
--- a/arch/mips/include/asm/sn/io.h
+++ b/arch/mips/include/asm/sn/io.h
@@ -31,7 +31,7 @@
 #define HUB_PIO_MAP_TO_MEM     0
 #define HUB_PIO_MAP_TO_IO      1
 
 #define HUB_PIO_MAP_TO_MEM     0
 #define HUB_PIO_MAP_TO_IO      1
 

-#define IIO_ITTE_INVALID_WIDGET        3       /* an invalid widget  */
+#define IIO_ITTE_INVALID_WIDGET 3      /* an invalid widget  */

 
 #define IIO_ITTE_PUT(nasid, bigwin, io_or_mem, widget, addr) \
        REMOTE_HUB_S((nasid), IIO_ITTE(bigwin), \
 
 #define IIO_ITTE_PUT(nasid, bigwin, io_or_mem, widget, addr) \
        REMOTE_HUB_S((nasid), IIO_ITTE(bigwin), \


@@ -52,7 +52,7 @@
  * value _x is expected to be a widget number in the range
  * 0, 8 - 0xF
  */
  * value _x is expected to be a widget number in the range
  * 0, 8 - 0xF
  */

-#define        IIO_IOPRB(_x)   (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
+#define IIO_IOPRB(_x)  (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \

                        (_x) : \
                        (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
 
                        (_x) : \
                        (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
 

diff --git a/arch/mips/include/asm/sn/ioc3.h b/arch/mips/include/asm/sn/ioc3.h
index 099677774d71b73fbfb1b649c9c4de15116ec055..e33f0363235b77e57229846f34fe398078c6f7ca 100644 (file)
--- a/arch/mips/include/asm/sn/ioc3.h
+++ b/arch/mips/include/asm/sn/ioc3.h
@@ -62,8 +62,8 @@ struct ioc3_sioregs {
 
        volatile u8             fill3[0x170 - 0x169 - 1];
 
 
        volatile u8             fill3[0x170 - 0x169 - 1];
 

-       struct ioc3_uartregs    uartb;  /* 0x20170  */
-       struct ioc3_uartregs    uarta;  /* 0x20178  */
+       struct ioc3_uartregs    uartb;  /* 0x20170  */
+       struct ioc3_uartregs    uarta;  /* 0x20178  */

 };
 
 /* Register layout of IOC3 in configuration space.  */
 };
 
 /* Register layout of IOC3 in configuration space.  */


@@ -106,7 +106,7 @@ struct ioc3 {
        volatile u32    ppbr_l_b;       /* 0x00094  */
        volatile u32    ppcr_b;         /* 0x00098  */
 
        volatile u32    ppbr_l_b;       /* 0x00094  */
        volatile u32    ppcr_b;         /* 0x00098  */
 

-       /* Keyboard and Mouse Registers  */
+       /* Keyboard and Mouse Registers  */

        volatile u32    km_csr;         /* 0x0009c  */
        volatile u32    k_rd;           /* 0x000a0  */
        volatile u32    m_rd;           /* 0x000a4  */
        volatile u32    km_csr;         /* 0x0009c  */
        volatile u32    k_rd;           /* 0x000a0  */
        volatile u32    m_rd;           /* 0x000a4  */


@@ -208,7 +208,7 @@ struct ioc3_erxbuf {
 /*
  * Ethernet TX Descriptor
  */
 /*
  * Ethernet TX Descriptor
  */

-#define ETXD_DATALEN    104
+#define ETXD_DATALEN   104

 struct ioc3_etxd {
        u32     cmd;                            /* command field */
        u32     bufcnt;                         /* buffer counts field */
 struct ioc3_etxd {
        u32     cmd;                            /* command field */
        u32     bufcnt;                         /* buffer counts field */

diff --git a/arch/mips/include/asm/sn/klconfig.h b/arch/mips/include/asm/sn/klconfig.h
index fe02900b930d51ba3ee85cc6d7ade0743ff4885f..467c313d57677e3e02f5f980b26b93feb92d4bca 100644 (file)
--- a/arch/mips/include/asm/sn/klconfig.h
+++ b/arch/mips/include/asm/sn/klconfig.h
@@ -8,8 +8,8 @@
  * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
  * Copyright (C) 1999, 2000 by Ralf Baechle
  */
  * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
  * Copyright (C) 1999, 2000 by Ralf Baechle
  */

-#ifndef        _ASM_SN_KLCONFIG_H
-#define        _ASM_SN_KLCONFIG_H
+#ifndef _ASM_SN_KLCONFIG_H
+#define _ASM_SN_KLCONFIG_H

 
 /*
  * The KLCONFIG structures store info about the various BOARDs found
 
 /*
  * The KLCONFIG structures store info about the various BOARDs found


@@ -20,11 +20,11 @@
 /*
  * WARNING:
  *     Certain assembly language routines (notably xxxxx.s) in the IP27PROM
 /*
  * WARNING:
  *     Certain assembly language routines (notably xxxxx.s) in the IP27PROM

- *     will depend on the format of the data structures in this file.  In
- *      most cases, rearranging the fields can seriously break things.
- *      Adding fields in the beginning or middle can also break things.
- *      Add fields if necessary, to the end of a struct in such a way
- *      that offsets of existing fields do not change.
+ *     will depend on the format of the data structures in this file.  In
+ *     most cases, rearranging the fields can seriously break things.
+ *     Adding fields in the beginning or middle can also break things.
+ *     Add fields if necessary, to the end of a struct in such a way
+ *     that offsets of existing fields do not change.

  */
 
 #include <linux/types.h>
  */
 
 #include <linux/types.h>


@@ -35,7 +35,7 @@
 #include <asm/sn/sn0/addrs.h>
 //#include <sys/SN/router.h>
 // XXX Stolen from <sys/SN/router.h>:
 #include <asm/sn/sn0/addrs.h>
 //#include <sys/SN/router.h>
 // XXX Stolen from <sys/SN/router.h>:

-#define MAX_ROUTER_PORTS (6)    /* Max. number of ports on a router */
+#define MAX_ROUTER_PORTS (6)   /* Max. number of ports on a router */

 #include <asm/sn/fru.h>
 //#include <sys/graph.h>
 //#include <sys/xtalk/xbow.h>
 #include <asm/sn/fru.h>
 //#include <sys/graph.h>
 //#include <sys/xtalk/xbow.h>


@@ -63,14 +63,14 @@
 
 typedef u64  nic_t;
 
 
 typedef u64  nic_t;
 

-#define KLCFGINFO_MAGIC        0xbeedbabe
+#define KLCFGINFO_MAGIC 0xbeedbabe

 
 typedef s32 klconf_off_t;
 
 /*
  * Some IMPORTANT OFFSETS. These are the offsets on all NODES.
  */
 
 typedef s32 klconf_off_t;
 
 /*
  * Some IMPORTANT OFFSETS. These are the offsets on all NODES.
  */

-#define        MAX_MODULE_ID           255
+#define MAX_MODULE_ID          255

 #define SIZE_PAD               4096 /* 4k padding for structures */
 /*
  * 1 NODE brd, 2 Router brd (1 8p, 1 meta), 6 Widgets,
 #define SIZE_PAD               4096 /* 4k padding for structures */
 /*
  * 1 NODE brd, 2 Router brd (1 8p, 1 meta), 6 Widgets,


@@ -86,25 +86,25 @@ typedef s32 klconf_off_t;
 /* All bits in this field are currently used. Try the pad fields if
    you need more flag bits */
 
 /* All bits in this field are currently used. Try the pad fields if
    you need more flag bits */
 

-#define ENABLE_BOARD           0x01
-#define FAILED_BOARD           0x02
-#define DUPLICATE_BOARD        0x04    /* Boards like midplanes/routers which
+#define ENABLE_BOARD           0x01
+#define FAILED_BOARD           0x02
+#define DUPLICATE_BOARD                0x04    /* Boards like midplanes/routers which

                                           are discovered twice. Use one of them */
 #define VISITED_BOARD          0x08    /* Used for compact hub numbering. */
                                           are discovered twice. Use one of them */
 #define VISITED_BOARD          0x08    /* Used for compact hub numbering. */

-#define LOCAL_MASTER_IO6       0x10    /* master io6 for that node */
+#define LOCAL_MASTER_IO6       0x10    /* master io6 for that node */

 #define GLOBAL_MASTER_IO6      0x20
 #define GLOBAL_MASTER_IO6      0x20

-#define THIRD_NIC_PRESENT      0x40    /* for future use */
-#define SECOND_NIC_PRESENT     0x80    /* addons like MIO are present */
+#define THIRD_NIC_PRESENT      0x40    /* for future use */
+#define SECOND_NIC_PRESENT     0x80    /* addons like MIO are present */

 
 /* klinfo->flags fields */
 
 
 /* klinfo->flags fields */
 

-#define KLINFO_ENABLE          0x01    /* This component is enabled */
-#define KLINFO_FAILED          0x02    /* This component failed */
-#define KLINFO_DEVICE          0x04    /* This component is a device */
-#define KLINFO_VISITED         0x08    /* This component has been visited */
-#define KLINFO_CONTROLLER      0x10    /* This component is a device controller */
-#define KLINFO_INSTALL         0x20    /* Install a driver */
-#define        KLINFO_HEADLESS         0x40    /* Headless (or hubless) component */
+#define KLINFO_ENABLE          0x01    /* This component is enabled */
+#define KLINFO_FAILED          0x02    /* This component failed */
+#define KLINFO_DEVICE          0x04    /* This component is a device */
+#define KLINFO_VISITED         0x08    /* This component has been visited */
+#define KLINFO_CONTROLLER      0x10    /* This component is a device controller */
+#define KLINFO_INSTALL         0x20    /* Install a driver */
+#define KLINFO_HEADLESS                0x40    /* Headless (or hubless) component */

 #define IS_CONSOLE_IOC3(i)     ((((klinfo_t *)i)->flags) & KLINFO_INSTALL)
 
 #define GB2            0x80000000
 #define IS_CONSOLE_IOC3(i)     ((((klinfo_t *)i)->flags) & KLINFO_INSTALL)
 
 #define GB2            0x80000000


@@ -116,30 +116,30 @@ typedef s32 klconf_off_t;
    is used in the code to allocate various areas.
 */
 
    is used in the code to allocate various areas.
 */
 

-#define BOARD_STRUCT           0
-#define COMPONENT_STRUCT       1
-#define ERRINFO_STRUCT                 2
-#define KLMALLOC_TYPE_MAX      (ERRINFO_STRUCT + 1)
-#define DEVICE_STRUCT          3
+#define BOARD_STRUCT           0
+#define COMPONENT_STRUCT       1
+#define ERRINFO_STRUCT         2
+#define KLMALLOC_TYPE_MAX      (ERRINFO_STRUCT + 1)
+#define DEVICE_STRUCT          3

 
 
 typedef struct console_s {
 
 
 typedef struct console_s {

-       unsigned long   uart_base;
-       unsigned long   config_base;
-       unsigned long   memory_base;
+       unsigned long   uart_base;
+       unsigned long   config_base;
+       unsigned long   memory_base;

        short           baud;
        short           flag;
        int             type;
        nasid_t         nasid;
        char            wid;
        short           baud;
        short           flag;
        int             type;
        nasid_t         nasid;
        char            wid;

-       char            npci;
+       char            npci;

        nic_t           baseio_nic;
 } console_t;
 
 typedef struct klc_malloc_hdr {
        nic_t           baseio_nic;
 } console_t;
 
 typedef struct klc_malloc_hdr {

-        klconf_off_t km_base;
-        klconf_off_t km_limit;
-        klconf_off_t km_current;
+       klconf_off_t km_base;
+       klconf_off_t km_limit;
+       klconf_off_t km_current;

 } klc_malloc_hdr_t;
 
 /* Functions/macros needed to use this structure */
 } klc_malloc_hdr_t;
 
 /* Functions/macros needed to use this structure */


@@ -148,7 +148,7 @@ typedef struct kl_config_hdr {
        u64             ch_magic;       /* set this to KLCFGINFO_MAGIC */
        u32             ch_version;    /* structure version number */
        klconf_off_t    ch_malloc_hdr_off; /* offset of ch_malloc_hdr */
        u64             ch_magic;       /* set this to KLCFGINFO_MAGIC */
        u32             ch_version;    /* structure version number */
        klconf_off_t    ch_malloc_hdr_off; /* offset of ch_malloc_hdr */

-       klconf_off_t    ch_cons_off;       /* offset of ch_cons */
+       klconf_off_t    ch_cons_off;       /* offset of ch_cons */

        klconf_off_t    ch_board_info;  /* the link list of boards */
        console_t       ch_cons_info;   /* address info of the console */
        klc_malloc_hdr_t ch_malloc_hdr[KLMALLOC_TYPE_MAX];
        klconf_off_t    ch_board_info;  /* the link list of boards */
        console_t       ch_cons_info;   /* address info of the console */
        klc_malloc_hdr_t ch_malloc_hdr[KLMALLOC_TYPE_MAX];


@@ -157,27 +157,27 @@ typedef struct kl_config_hdr {
 } kl_config_hdr_t;
 
 
 } kl_config_hdr_t;
 
 

-#define KL_CONFIG_HDR(_nasid)  ((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid)))
+#define KL_CONFIG_HDR(_nasid)  ((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid)))

 #define KL_CONFIG_INFO_OFFSET(_nasid)                                  \
 #define KL_CONFIG_INFO_OFFSET(_nasid)                                  \

-        (KL_CONFIG_HDR(_nasid)->ch_board_info)
+       (KL_CONFIG_HDR(_nasid)->ch_board_info)

 #define KL_CONFIG_INFO_SET_OFFSET(_nasid, _off)                                \
 #define KL_CONFIG_INFO_SET_OFFSET(_nasid, _off)                                \

-        (KL_CONFIG_HDR(_nasid)->ch_board_info = (_off))
+       (KL_CONFIG_HDR(_nasid)->ch_board_info = (_off))

 
 

-#define KL_CONFIG_INFO(_nasid)                                                 \
-        (lboard_t *)((KL_CONFIG_HDR(_nasid)->ch_board_info) ?          \
+#define KL_CONFIG_INFO(_nasid)                                         \
+       (lboard_t *)((KL_CONFIG_HDR(_nasid)->ch_board_info) ?           \

         NODE_OFFSET_TO_K1((_nasid), KL_CONFIG_HDR(_nasid)->ch_board_info) : \
         0)
 #define KL_CONFIG_MAGIC(_nasid)                (KL_CONFIG_HDR(_nasid)->ch_magic)
 
 #define KL_CONFIG_CHECK_MAGIC(_nasid)                                  \
         NODE_OFFSET_TO_K1((_nasid), KL_CONFIG_HDR(_nasid)->ch_board_info) : \
         0)
 #define KL_CONFIG_MAGIC(_nasid)                (KL_CONFIG_HDR(_nasid)->ch_magic)
 
 #define KL_CONFIG_CHECK_MAGIC(_nasid)                                  \

-        (KL_CONFIG_HDR(_nasid)->ch_magic == KLCFGINFO_MAGIC)
+       (KL_CONFIG_HDR(_nasid)->ch_magic == KLCFGINFO_MAGIC)

 
 #define KL_CONFIG_HDR_INIT_MAGIC(_nasid)       \
 
 #define KL_CONFIG_HDR_INIT_MAGIC(_nasid)       \

-                  (KL_CONFIG_HDR(_nasid)->ch_magic = KLCFGINFO_MAGIC)
+                 (KL_CONFIG_HDR(_nasid)->ch_magic = KLCFGINFO_MAGIC)

 
 /* --- New Macros for the changed kl_config_hdr_t structure --- */
 
 
 /* --- New Macros for the changed kl_config_hdr_t structure --- */
 

-#define PTR_CH_MALLOC_HDR(_k)   ((klc_malloc_hdr_t *)\
+#define PTR_CH_MALLOC_HDR(_k)  ((klc_malloc_hdr_t *)\

                        ((unsigned long)_k + (_k->ch_malloc_hdr_off)))
 
 #define KL_CONFIG_CH_MALLOC_HDR(_n)   PTR_CH_MALLOC_HDR(KL_CONFIG_HDR(_n))
                        ((unsigned long)_k + (_k->ch_malloc_hdr_off)))
 
 #define KL_CONFIG_CH_MALLOC_HDR(_n)   PTR_CH_MALLOC_HDR(KL_CONFIG_HDR(_n))


@@ -190,29 +190,29 @@ typedef struct kl_config_hdr {
 /* ------------------------------------------------------------- */
 
 #define KL_CONFIG_INFO_START(_nasid)   \
 /* ------------------------------------------------------------- */
 
 #define KL_CONFIG_INFO_START(_nasid)   \

-        (klconf_off_t)(KLCONFIG_OFFSET(_nasid) + sizeof(kl_config_hdr_t))
+       (klconf_off_t)(KLCONFIG_OFFSET(_nasid) + sizeof(kl_config_hdr_t))

 
 #define KL_CONFIG_BOARD_NASID(_brd)    ((_brd)->brd_nasid)
 #define KL_CONFIG_BOARD_SET_NEXT(_brd, _off)   ((_brd)->brd_next = (_off))
 
 
 #define KL_CONFIG_BOARD_NASID(_brd)    ((_brd)->brd_nasid)
 #define KL_CONFIG_BOARD_SET_NEXT(_brd, _off)   ((_brd)->brd_next = (_off))
 

-#define KL_CONFIG_DUPLICATE_BOARD(_brd)        ((_brd)->brd_flags & DUPLICATE_BOARD)
+#define KL_CONFIG_DUPLICATE_BOARD(_brd) ((_brd)->brd_flags & DUPLICATE_BOARD)

 
 

-#define XBOW_PORT_TYPE_HUB(_xbowp, _link)      \
-               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_HUB)
-#define XBOW_PORT_TYPE_IO(_xbowp, _link)       \
-               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_IO)
+#define XBOW_PORT_TYPE_HUB(_xbowp, _link)      \
+              ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_HUB)
+#define XBOW_PORT_TYPE_IO(_xbowp, _link)       \
+              ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_IO)

 
 

-#define XBOW_PORT_IS_ENABLED(_xbowp, _link)    \
-               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_ENABLE)
-#define XBOW_PORT_NASID(_xbowp, _link)         \
-               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_nasid)
+#define XBOW_PORT_IS_ENABLED(_xbowp, _link)    \
+              ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_ENABLE)
+#define XBOW_PORT_NASID(_xbowp, _link) \
+              ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_nasid)

 
 

-#define XBOW_PORT_IO     0x1
-#define XBOW_PORT_HUB    0x2
+#define XBOW_PORT_IO    0x1
+#define XBOW_PORT_HUB   0x2

 #define XBOW_PORT_ENABLE 0x4
 
 #define XBOW_PORT_ENABLE 0x4
 

-#define        SN0_PORT_FENCE_SHFT     0
-#define        SN0_PORT_FENCE_MASK     (1 << SN0_PORT_FENCE_SHFT)
+#define SN0_PORT_FENCE_SHFT    0
+#define SN0_PORT_FENCE_MASK    (1 << SN0_PORT_FENCE_SHFT)

 
 /*
  * The KLCONFIG area is organized as a LINKED LIST of BOARDs. A BOARD
 
 /*
  * The KLCONFIG area is organized as a LINKED LIST of BOARDs. A BOARD


@@ -242,28 +242,28 @@ typedef struct kl_config_hdr {
  *
  KLCONFIG
 
  *
  KLCONFIG
 

- +------------+      +------------+      +------------+      +------------+
- |  lboard    |  +-->|   lboard   |  +-->|   rboard   |  +-->|   lboard   |
- +------------+  |   +------------+  |   +------------+  |   +------------+
- | board info |  |   | board info |  |   |errinfo,bptr|  |   | board info |
- +------------+  |   +------------+  |   +------------+  |   +------------+
- | offset     |--+   |  offset    |--+   |  offset    |--+   |offset=NULL |
- +------------+      +------------+      +------------+      +------------+
+ +------------+             +------------+      +------------+      +------------+
+ |  lboard    |         +-->|   lboard   |  +-->|   rboard   |  +-->|   lboard   |
+ +------------+         |   +------------+  |   +------------+  |   +------------+
+ | board info |         |   | board info |  |   |errinfo,bptr|  |   | board info |
+ +------------+         |   +------------+  |   +------------+  |   +------------+
+ | offset     |--+   | offset    |--+   |  offset    |--+   |offset=NULL |
+ +------------+             +------------+      +------------+      +------------+

 
 
  +------------+
  | board info |
 
 
  +------------+
  | board info |

- +------------+       +--------------------------------+
+ +------------+              +--------------------------------+

  | compt 1    |------>| type, rev, diaginfo, size ...  |  (CPU)
  | compt 1    |------>| type, rev, diaginfo, size ...  |  (CPU)

- +------------+       +--------------------------------+
+ +------------+              +--------------------------------+

  | compt 2    |--+
  | compt 2    |--+

- +------------+  |    +--------------------------------+
- |  ...       |  +--->| type, rev, diaginfo, size ...  |  (MEM_BANK)
- +------------+       +--------------------------------+
+ +------------+         |    +--------------------------------+
+ |  ...              |  +--->| type, rev, diaginfo, size ...  |  (MEM_BANK)
+ +------------+              +--------------------------------+

  | errinfo    |--+
  | errinfo    |--+

- +------------+  |    +--------------------------------+
-                 +--->|r/l brd errinfo,compt err flags |
-                      +--------------------------------+
+ +------------+         |    +--------------------------------+
+                +--->|r/l brd errinfo,compt err flags |
+                     +--------------------------------+

 
  *
  * Each BOARD consists of COMPONENTs and the BOARD structure has
 
  *
  * Each BOARD consists of COMPONENTs and the BOARD structure has


@@ -311,7 +311,7 @@ typedef struct kl_config_hdr {
  */
 #define KL_CPU_R4000           0x1     /* Standard R4000 */
 #define KL_CPU_TFP             0x2     /* TFP processor */
  */
 #define KL_CPU_R4000           0x1     /* Standard R4000 */
 #define KL_CPU_TFP             0x2     /* TFP processor */

-#define        KL_CPU_R10000           0x3     /* R10000 (T5) */
+#define KL_CPU_R10000          0x3     /* R10000 (T5) */

 #define KL_CPU_NONE            (-1)    /* no cpu present in slot */
 
 /*
 #define KL_CPU_NONE            (-1)    /* no cpu present in slot */
 
 /*


@@ -320,13 +320,13 @@ typedef struct kl_config_hdr {
 
 #define KLCLASS_MASK   0xf0
 #define KLCLASS_NONE   0x00
 
 #define KLCLASS_MASK   0xf0
 #define KLCLASS_NONE   0x00

-#define KLCLASS_NODE   0x10             /* CPU, Memory and HUB board */
+#define KLCLASS_NODE   0x10             /* CPU, Memory and HUB board */

 #define KLCLASS_CPU    KLCLASS_NODE
 #define KLCLASS_CPU    KLCLASS_NODE

-#define KLCLASS_IO     0x20             /* BaseIO, 4 ch SCSI, ethernet, FDDI
+#define KLCLASS_IO     0x20             /* BaseIO, 4 ch SCSI, ethernet, FDDI

                                            and the non-graphics widget boards */
                                            and the non-graphics widget boards */

-#define KLCLASS_ROUTER 0x30             /* Router board */
-#define KLCLASS_MIDPLANE 0x40            /* We need to treat this as a board
-                                            so that we can record error info */
+#define KLCLASS_ROUTER 0x30             /* Router board */
+#define KLCLASS_MIDPLANE 0x40           /* We need to treat this as a board
+                                           so that we can record error info */

 #define KLCLASS_GFX    0x50            /* graphics boards */
 
 #define KLCLASS_PSEUDO_GFX     0x60    /* HDTV type cards that use a gfx
 #define KLCLASS_GFX    0x50            /* graphics boards */
 
 #define KLCLASS_PSEUDO_GFX     0x60    /* HDTV type cards that use a gfx


@@ -336,7 +336,7 @@ typedef struct kl_config_hdr {
 #define KLCLASS_MAX    7               /* Bump this if a new CLASS is added */
 #define KLTYPE_MAX     10              /* Bump this if a new CLASS is added */
 
 #define KLCLASS_MAX    7               /* Bump this if a new CLASS is added */
 #define KLTYPE_MAX     10              /* Bump this if a new CLASS is added */
 

-#define KLCLASS_UNKNOWN        0xf0
+#define KLCLASS_UNKNOWN 0xf0

 
 #define KLCLASS(_x) ((_x) & KLCLASS_MASK)
 
 
 #define KLCLASS(_x) ((_x) & KLCLASS_MASK)
 


@@ -353,36 +353,36 @@ typedef struct kl_config_hdr {
 
 #define KLTYPE_WEIRDIO (KLCLASS_IO  | 0x0)
 #define KLTYPE_BASEIO  (KLCLASS_IO  | 0x1) /* IOC3, SuperIO, Bridge, SCSI */
 
 #define KLTYPE_WEIRDIO (KLCLASS_IO  | 0x0)
 #define KLTYPE_BASEIO  (KLCLASS_IO  | 0x1) /* IOC3, SuperIO, Bridge, SCSI */

-#define KLTYPE_IO6     KLTYPE_BASEIO       /* Additional name */
+#define KLTYPE_IO6     KLTYPE_BASEIO       /* Additional name */

 #define KLTYPE_4CHSCSI (KLCLASS_IO  | 0x2)
 #define KLTYPE_4CHSCSI (KLCLASS_IO  | 0x2)

-#define KLTYPE_MSCSI   KLTYPE_4CHSCSI      /* Additional name */
-#define KLTYPE_ETHERNET        (KLCLASS_IO  | 0x3)
-#define KLTYPE_MENET   KLTYPE_ETHERNET     /* Additional name */
-#define KLTYPE_FDDI    (KLCLASS_IO  | 0x4)
+#define KLTYPE_MSCSI   KLTYPE_4CHSCSI      /* Additional name */
+#define KLTYPE_ETHERNET (KLCLASS_IO  | 0x3)
+#define KLTYPE_MENET   KLTYPE_ETHERNET     /* Additional name */
+#define KLTYPE_FDDI    (KLCLASS_IO  | 0x4)

 #define KLTYPE_UNUSED  (KLCLASS_IO  | 0x5) /* XXX UNUSED */
 #define KLTYPE_UNUSED  (KLCLASS_IO  | 0x5) /* XXX UNUSED */

-#define KLTYPE_HAROLD   (KLCLASS_IO  | 0x6) /* PCI SHOE BOX */
+#define KLTYPE_HAROLD  (KLCLASS_IO  | 0x6) /* PCI SHOE BOX */

 #define KLTYPE_PCI     KLTYPE_HAROLD
 #define KLTYPE_PCI     KLTYPE_HAROLD

-#define KLTYPE_VME      (KLCLASS_IO  | 0x7) /* Any 3rd party VME card */
-#define KLTYPE_MIO     (KLCLASS_IO  | 0x8)
-#define KLTYPE_FC      (KLCLASS_IO  | 0x9)
-#define KLTYPE_LINC            (KLCLASS_IO  | 0xA)
-#define KLTYPE_TPU     (KLCLASS_IO  | 0xB) /* Tensor Processing Unit */
-#define KLTYPE_GSN_A           (KLCLASS_IO  | 0xC) /* Main GSN board */
-#define KLTYPE_GSN_B           (KLCLASS_IO  | 0xD) /* Auxiliary GSN board */
+#define KLTYPE_VME     (KLCLASS_IO  | 0x7) /* Any 3rd party VME card */
+#define KLTYPE_MIO     (KLCLASS_IO  | 0x8)
+#define KLTYPE_FC      (KLCLASS_IO  | 0x9)
+#define KLTYPE_LINC    (KLCLASS_IO  | 0xA)
+#define KLTYPE_TPU     (KLCLASS_IO  | 0xB) /* Tensor Processing Unit */
+#define KLTYPE_GSN_A   (KLCLASS_IO  | 0xC) /* Main GSN board */
+#define KLTYPE_GSN_B   (KLCLASS_IO  | 0xD) /* Auxiliary GSN board */

 
 #define KLTYPE_GFX     (KLCLASS_GFX | 0x0) /* unknown graphics type */
 #define KLTYPE_GFX_KONA (KLCLASS_GFX | 0x1) /* KONA graphics on IP27 */
 #define KLTYPE_GFX_MGRA (KLCLASS_GFX | 0x3) /* MGRAS graphics on IP27 */
 
 #define KLTYPE_WEIRDROUTER (KLCLASS_ROUTER | 0x0)
 
 #define KLTYPE_GFX     (KLCLASS_GFX | 0x0) /* unknown graphics type */
 #define KLTYPE_GFX_KONA (KLCLASS_GFX | 0x1) /* KONA graphics on IP27 */
 #define KLTYPE_GFX_MGRA (KLCLASS_GFX | 0x3) /* MGRAS graphics on IP27 */
 
 #define KLTYPE_WEIRDROUTER (KLCLASS_ROUTER | 0x0)

-#define KLTYPE_ROUTER     (KLCLASS_ROUTER | 0x1)
-#define KLTYPE_ROUTER2    KLTYPE_ROUTER                /* Obsolete! */
+#define KLTYPE_ROUTER    (KLCLASS_ROUTER | 0x1)
+#define KLTYPE_ROUTER2   KLTYPE_ROUTER         /* Obsolete! */

 #define KLTYPE_NULL_ROUTER (KLCLASS_ROUTER | 0x2)
 #define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3)
 
 #define KLTYPE_WEIRDMIDPLANE (KLCLASS_MIDPLANE | 0x0)
 #define KLTYPE_MIDPLANE8  (KLCLASS_MIDPLANE | 0x1) /* 8 slot backplane */
 #define KLTYPE_NULL_ROUTER (KLCLASS_ROUTER | 0x2)
 #define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3)
 
 #define KLTYPE_WEIRDMIDPLANE (KLCLASS_MIDPLANE | 0x0)
 #define KLTYPE_MIDPLANE8  (KLCLASS_MIDPLANE | 0x1) /* 8 slot backplane */

-#define KLTYPE_MIDPLANE    KLTYPE_MIDPLANE8
+#define KLTYPE_MIDPLANE           KLTYPE_MIDPLANE8

 #define KLTYPE_PBRICK_XBOW     (KLCLASS_MIDPLANE | 0x2)
 
 #define KLTYPE_IOBRICK         (KLCLASS_IOBRICK | 0x0)
 #define KLTYPE_PBRICK_XBOW     (KLCLASS_MIDPLANE | 0x2)
 
 #define KLTYPE_IOBRICK         (KLCLASS_IOBRICK | 0x0)


@@ -398,11 +398,11 @@ typedef struct kl_config_hdr {
  * When bringup started nic names had not standardized and so we
  * had to hard code. (For people interested in history.)
  */
  * When bringup started nic names had not standardized and so we
  * had to hard code. (For people interested in history.)
  */

-#define KLTYPE_XTHD    (KLCLASS_PSEUDO_GFX | 0x9)
+#define KLTYPE_XTHD    (KLCLASS_PSEUDO_GFX | 0x9)

 
 #define KLTYPE_UNKNOWN (KLCLASS_UNKNOWN | 0xf)
 
 
 #define KLTYPE_UNKNOWN (KLCLASS_UNKNOWN | 0xf)
 

-#define KLTYPE(_x)     ((_x) & KLTYPE_MASK)
+#define KLTYPE(_x)     ((_x) & KLTYPE_MASK)

 #define IS_MIO_PRESENT(l)      ((l->brd_type == KLTYPE_BASEIO) && \
                                 (l->brd_flags & SECOND_NIC_PRESENT))
 #define IS_MIO_IOC3(l, n)      (IS_MIO_PRESENT(l) && (n > 2))
 #define IS_MIO_PRESENT(l)      ((l->brd_type == KLTYPE_BASEIO) && \
                                 (l->brd_flags & SECOND_NIC_PRESENT))
 #define IS_MIO_IOC3(l, n)      (IS_MIO_PRESENT(l) && (n > 2))


@@ -416,33 +416,33 @@ typedef struct kl_config_hdr {
 #define LOCAL_BOARD 1
 #define REMOTE_BOARD 2
 
 #define LOCAL_BOARD 1
 #define REMOTE_BOARD 2
 

-#define LBOARD_STRUCT_VERSION  2
+#define LBOARD_STRUCT_VERSION  2

 
 typedef struct lboard_s {
 
 typedef struct lboard_s {

-       klconf_off_t    brd_next;         /* Next BOARD */
-       unsigned char   struct_type;      /* type of structure, local or remote */
-       unsigned char   brd_type;         /* type+class */
-       unsigned char   brd_sversion;     /* version of this structure */
-        unsigned char  brd_brevision;    /* board revision */
-        unsigned char  brd_promver;      /* board prom version, if any */
-       unsigned char   brd_flags;        /* Enabled, Disabled etc */
-       unsigned char   brd_slot;         /* slot number */
-       unsigned short  brd_debugsw;      /* Debug switches */
-       moduleid_t      brd_module;       /* module to which it belongs */
-       partid_t        brd_partition;    /* Partition number */
-        unsigned short         brd_diagval;      /* diagnostic value */
-        unsigned short         brd_diagparm;     /* diagnostic parameter */
-        unsigned char  brd_inventory;    /* inventory history */
-        unsigned char  brd_numcompts;    /* Number of components */
-        nic_t          brd_nic;          /* Number in CAN */
-       nasid_t         brd_nasid;        /* passed parameter */
-       klconf_off_t    brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */
-       klconf_off_t    brd_errinfo;      /* Board's error information */
+       klconf_off_t    brd_next;         /* Next BOARD */
+       unsigned char   struct_type;      /* type of structure, local or remote */
+       unsigned char   brd_type;         /* type+class */
+       unsigned char   brd_sversion;     /* version of this structure */
+       unsigned char   brd_brevision;    /* board revision */
+       unsigned char   brd_promver;      /* board prom version, if any */
+       unsigned char   brd_flags;        /* Enabled, Disabled etc */
+       unsigned char   brd_slot;         /* slot number */
+       unsigned short  brd_debugsw;      /* Debug switches */
+       moduleid_t      brd_module;       /* module to which it belongs */
+       partid_t        brd_partition;    /* Partition number */
+       unsigned short  brd_diagval;      /* diagnostic value */
+       unsigned short  brd_diagparm;     /* diagnostic parameter */
+       unsigned char   brd_inventory;    /* inventory history */
+       unsigned char   brd_numcompts;    /* Number of components */
+       nic_t           brd_nic;          /* Number in CAN */
+       nasid_t         brd_nasid;        /* passed parameter */
+       klconf_off_t    brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */
+       klconf_off_t    brd_errinfo;      /* Board's error information */

        struct lboard_s *brd_parent;      /* Logical parent for this brd */
        struct lboard_s *brd_parent;      /* Logical parent for this brd */

-       vertex_hdl_t    brd_graph_link;   /* vertex hdl to connect extern compts */
+       vertex_hdl_t    brd_graph_link;   /* vertex hdl to connect extern compts */

        confidence_t    brd_confidence;   /* confidence that the board is bad */
        confidence_t    brd_confidence;   /* confidence that the board is bad */

-       nasid_t         brd_owner;        /* who owns this board */
-       unsigned char   brd_nic_flags;    /* To handle 8 more NICs */
+       nasid_t         brd_owner;        /* who owns this board */
+       unsigned char   brd_nic_flags;    /* To handle 8 more NICs */

        char            brd_name[32];
 } lboard_t;
 
        char            brd_name[32];
 } lboard_t;
 


@@ -456,23 +456,23 @@ typedef struct lboard_s {
 
 #define KLCF_CLASS(_brd)       KLCLASS((_brd)->brd_type)
 #define KLCF_TYPE(_brd)                KLTYPE((_brd)->brd_type)
 
 #define KLCF_CLASS(_brd)       KLCLASS((_brd)->brd_type)
 #define KLCF_TYPE(_brd)                KLTYPE((_brd)->brd_type)

-#define KLCF_REMOTE(_brd)      (((_brd)->struct_type & LOCAL_BOARD) ? 0 : 1)
+#define KLCF_REMOTE(_brd)      (((_brd)->struct_type & LOCAL_BOARD) ? 0 : 1)

 #define KLCF_NUM_COMPS(_brd)   ((_brd)->brd_numcompts)
 #define KLCF_MODULE_ID(_brd)   ((_brd)->brd_module)
 
 #define KLCF_NUM_COMPS(_brd)   ((_brd)->brd_numcompts)
 #define KLCF_MODULE_ID(_brd)   ((_brd)->brd_module)
 

-#define KLCF_NEXT(_brd)        \
-        ((_brd)->brd_next ?    \
+#define KLCF_NEXT(_brd)                \
+       ((_brd)->brd_next ?     \

         (lboard_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), (_brd)->brd_next)):\
         NULL)
         (lboard_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), (_brd)->brd_next)):\
         NULL)

-#define KLCF_COMP(_brd, _ndx)   \
-                (klinfo_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd),        \
+#define KLCF_COMP(_brd, _ndx)  \
+               (klinfo_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), \

                                               (_brd)->brd_compts[(_ndx)]))
 
 #define KLCF_COMP_ERROR(_brd, _comp)   \
                                               (_brd)->brd_compts[(_ndx)]))
 
 #define KLCF_COMP_ERROR(_brd, _comp)   \

-               (NODE_OFFSET_TO_K1(NASID_GET(_brd), (_comp)->errinfo))
+              (NODE_OFFSET_TO_K1(NASID_GET(_brd), (_comp)->errinfo))

 
 #define KLCF_COMP_TYPE(_comp)  ((_comp)->struct_type)
 
 #define KLCF_COMP_TYPE(_comp)  ((_comp)->struct_type)

-#define KLCF_BRIDGE_W_ID(_comp)        ((_comp)->physid)       /* Widget ID */
+#define KLCF_BRIDGE_W_ID(_comp) ((_comp)->physid)      /* Widget ID */

 
 
 
 
 
 


@@ -481,73 +481,73 @@ typedef struct lboard_s {
  * component.
  */
 
  * component.
  */
 

-typedef struct klinfo_s {                  /* Generic info */
-        unsigned char   struct_type;       /* type of this structure */
-        unsigned char   struct_version;    /* version of this structure */
-        unsigned char   flags;            /* Enabled, disabled etc */
-        unsigned char   revision;         /* component revision */
-        unsigned short  diagval;          /* result of diagnostics */
-        unsigned short  diagparm;         /* diagnostic parameter */
-        unsigned char   inventory;        /* previous inventory status */
-       nic_t           nic;              /* MUst be aligned properly */
-        unsigned char   physid;           /* physical id of component */
-        unsigned int    virtid;           /* virtual id as seen by system */
-       unsigned char   widid;            /* Widget id - if applicable */
-       nasid_t         nasid;            /* node number - from parent */
+typedef struct klinfo_s {                 /* Generic info */
+       unsigned char   struct_type;       /* type of this structure */
+       unsigned char   struct_version;    /* version of this structure */
+       unsigned char   flags;            /* Enabled, disabled etc */
+       unsigned char   revision;         /* component revision */
+       unsigned short  diagval;          /* result of diagnostics */
+       unsigned short  diagparm;         /* diagnostic parameter */
+       unsigned char   inventory;        /* previous inventory status */
+       nic_t           nic;              /* MUst be aligned properly */
+       unsigned char   physid;           /* physical id of component */
+       unsigned int    virtid;           /* virtual id as seen by system */
+       unsigned char   widid;            /* Widget id - if applicable */
+       nasid_t         nasid;            /* node number - from parent */

        char            pad1;             /* pad out structure. */
        char            pad2;             /* pad out structure. */
        char            pad1;             /* pad out structure. */
        char            pad2;             /* pad out structure. */

-       COMPONENT       *arcs_compt;      /* ptr to the arcs struct for ease*/
-        klconf_off_t   errinfo;          /* component specific errors */
-        unsigned short  pad3;             /* pci fields have moved over to */
-        unsigned short  pad4;             /* klbri_t */
+       COMPONENT       *arcs_compt;      /* ptr to the arcs struct for ease*/
+       klconf_off_t    errinfo;          /* component specific errors */
+       unsigned short  pad3;             /* pci fields have moved over to */
+       unsigned short  pad4;             /* klbri_t */

 } klinfo_t ;
 
 #define KLCONFIG_INFO_ENABLED(_i)      ((_i)->flags & KLINFO_ENABLE)
 /*
  * Component structures.
  * Following are the currently identified components:
 } klinfo_t ;
 
 #define KLCONFIG_INFO_ENABLED(_i)      ((_i)->flags & KLINFO_ENABLE)
 /*
  * Component structures.
  * Following are the currently identified components:

- *     CPU, HUB, MEM_BANK,
- *     XBOW(consists of 16 WIDGETs, each of which can be HUB or GRAPHICS or BRIDGE)
- *     BRIDGE, IOC3, SuperIO, SCSI, FDDI
- *     ROUTER
- *     GRAPHICS
+ *     CPU, HUB, MEM_BANK,
+ *     XBOW(consists of 16 WIDGETs, each of which can be HUB or GRAPHICS or BRIDGE)
+ *     BRIDGE, IOC3, SuperIO, SCSI, FDDI
+ *     ROUTER
+ *     GRAPHICS

  */
 #define KLSTRUCT_UNKNOWN       0
  */
 #define KLSTRUCT_UNKNOWN       0

-#define KLSTRUCT_CPU           1
-#define KLSTRUCT_HUB           2
-#define KLSTRUCT_MEMBNK        3
-#define KLSTRUCT_XBOW          4
-#define KLSTRUCT_BRI           5
-#define KLSTRUCT_IOC3          6
-#define KLSTRUCT_PCI           7
-#define KLSTRUCT_VME           8
+#define KLSTRUCT_CPU           1
+#define KLSTRUCT_HUB           2
+#define KLSTRUCT_MEMBNK                3
+#define KLSTRUCT_XBOW          4
+#define KLSTRUCT_BRI           5
+#define KLSTRUCT_IOC3          6
+#define KLSTRUCT_PCI           7
+#define KLSTRUCT_VME           8

 #define KLSTRUCT_ROU           9
 #define KLSTRUCT_ROU           9

-#define KLSTRUCT_GFX           10
-#define KLSTRUCT_SCSI          11
-#define KLSTRUCT_FDDI          12
-#define KLSTRUCT_MIO           13
-#define KLSTRUCT_DISK          14
-#define KLSTRUCT_TAPE          15
-#define KLSTRUCT_CDROM                 16
-#define KLSTRUCT_HUB_UART      17
-#define KLSTRUCT_IOC3ENET      18
-#define KLSTRUCT_IOC3UART      19
+#define KLSTRUCT_GFX           10
+#define KLSTRUCT_SCSI          11
+#define KLSTRUCT_FDDI          12
+#define KLSTRUCT_MIO           13
+#define KLSTRUCT_DISK          14
+#define KLSTRUCT_TAPE          15
+#define KLSTRUCT_CDROM         16
+#define KLSTRUCT_HUB_UART      17
+#define KLSTRUCT_IOC3ENET      18
+#define KLSTRUCT_IOC3UART      19

 #define KLSTRUCT_UNUSED                20 /* XXX UNUSED */
 #define KLSTRUCT_UNUSED                20 /* XXX UNUSED */

-#define KLSTRUCT_IOC3PCKM       21
-#define KLSTRUCT_RAD           22
-#define KLSTRUCT_HUB_TTY        23
-#define KLSTRUCT_IOC3_TTY      24
+#define KLSTRUCT_IOC3PCKM      21
+#define KLSTRUCT_RAD           22
+#define KLSTRUCT_HUB_TTY       23
+#define KLSTRUCT_IOC3_TTY      24

 
 /* Early Access IO proms are compatible
    only with KLSTRUCT values up to 24. */
 
 
 /* Early Access IO proms are compatible
    only with KLSTRUCT values up to 24. */
 

-#define KLSTRUCT_FIBERCHANNEL  25
+#define KLSTRUCT_FIBERCHANNEL  25

 #define KLSTRUCT_MOD_SERIAL_NUM 26
 #define KLSTRUCT_MOD_SERIAL_NUM 26

-#define KLSTRUCT_IOC3MS         27
-#define KLSTRUCT_TPU            28
-#define KLSTRUCT_GSN_A          29
-#define KLSTRUCT_GSN_B          30
-#define KLSTRUCT_XTHD           31
+#define KLSTRUCT_IOC3MS                27
+#define KLSTRUCT_TPU           28
+#define KLSTRUCT_GSN_A         29
+#define KLSTRUCT_GSN_B         30
+#define KLSTRUCT_XTHD          31

 
 /*
  * These are the indices of various components within a lboard structure.
 
 /*
  * These are the indices of various components within a lboard structure.


@@ -583,7 +583,7 @@ typedef u64 *router_t;
  * The port info in ip27_cfg area translates to a lboart_t in the
  * KLCONFIG area. But since KLCONFIG does not use pointers, lboart_t
  * is stored in terms of a nasid and a offset from start of KLCONFIG
  * The port info in ip27_cfg area translates to a lboart_t in the
  * KLCONFIG area. But since KLCONFIG does not use pointers, lboart_t
  * is stored in terms of a nasid and a offset from start of KLCONFIG

- * area  on that nasid.
+ * area         on that nasid.

  */
 typedef struct klport_s {
        nasid_t         port_nasid;
  */
 typedef struct klport_s {
        nasid_t         port_nasid;


@@ -591,20 +591,20 @@ typedef struct klport_s {
        klconf_off_t    port_offset;
 } klport_t;
 
        klconf_off_t    port_offset;
 } klport_t;
 

-typedef struct klcpu_s {                          /* CPU */
-       klinfo_t        cpu_info;
-       unsigned short  cpu_prid;       /* Processor PRID value */
-       unsigned short  cpu_fpirr;      /* FPU IRR value */
-       unsigned short  cpu_speed;      /* Speed in MHZ */
-       unsigned short  cpu_scachesz;   /* secondary cache size in MB */
-       unsigned short  cpu_scachespeed;/* secondary cache speed in MHz */
+typedef struct klcpu_s {                         /* CPU */
+       klinfo_t        cpu_info;
+       unsigned short  cpu_prid;       /* Processor PRID value */
+       unsigned short  cpu_fpirr;      /* FPU IRR value */
+       unsigned short  cpu_speed;      /* Speed in MHZ */
+       unsigned short  cpu_scachesz;   /* secondary cache size in MB */
+       unsigned short  cpu_scachespeed;/* secondary cache speed in MHz */

 } klcpu_t ;
 
 #define CPU_STRUCT_VERSION   2
 
 typedef struct klhub_s {                       /* HUB */
 } klcpu_t ;
 
 #define CPU_STRUCT_VERSION   2
 
 typedef struct klhub_s {                       /* HUB */

-       klinfo_t        hub_info;
-       unsigned int            hub_flags;              /* PCFG_HUB_xxx flags */
+       klinfo_t        hub_info;
+       unsigned int            hub_flags;              /* PCFG_HUB_xxx flags */

        klport_t        hub_port;               /* hub is connected to this */
        nic_t           hub_box_nic;            /* nic of containing box */
        klconf_off_t    hub_mfg_nic;            /* MFG NIC string */
        klport_t        hub_port;               /* hub is connected to this */
        nic_t           hub_box_nic;            /* nic of containing box */
        klconf_off_t    hub_mfg_nic;            /* MFG NIC string */


@@ -612,36 +612,36 @@ typedef struct klhub_s {                  /* HUB */
 } klhub_t ;
 
 typedef struct klhub_uart_s {                  /* HUB */
 } klhub_t ;
 
 typedef struct klhub_uart_s {                  /* HUB */

-       klinfo_t        hubuart_info;
-       unsigned int            hubuart_flags;          /* PCFG_HUB_xxx flags */
+       klinfo_t        hubuart_info;
+       unsigned int            hubuart_flags;          /* PCFG_HUB_xxx flags */

        nic_t           hubuart_box_nic;        /* nic of containing box */
 } klhub_uart_t ;
 
        nic_t           hubuart_box_nic;        /* nic of containing box */
 } klhub_uart_t ;
 

-#define MEMORY_STRUCT_VERSION   2
+#define MEMORY_STRUCT_VERSION  2

 
 typedef struct klmembnk_s {                    /* MEMORY BANK */
 
 typedef struct klmembnk_s {                    /* MEMORY BANK */

-       klinfo_t        membnk_info;
-       short           membnk_memsz;           /* Total memory in megabytes */
+       klinfo_t        membnk_info;
+       short           membnk_memsz;           /* Total memory in megabytes */

        short           membnk_dimm_select; /* bank to physical addr mapping*/
        short           membnk_bnksz[MD_MEM_BANKS]; /* Memory bank sizes */
        short           membnk_attr;
 } klmembnk_t ;
 
 #define KLCONFIG_MEMBNK_SIZE(_info, _bank)     \
        short           membnk_dimm_select; /* bank to physical addr mapping*/
        short           membnk_bnksz[MD_MEM_BANKS]; /* Memory bank sizes */
        short           membnk_attr;
 } klmembnk_t ;
 
 #define KLCONFIG_MEMBNK_SIZE(_info, _bank)     \

-                            ((_info)->membnk_bnksz[(_bank)])
+                           ((_info)->membnk_bnksz[(_bank)])

 
 
 #define MEMBNK_PREMIUM 1
 #define KLCONFIG_MEMBNK_PREMIUM(_info, _bank)  \
 
 
 #define MEMBNK_PREMIUM 1
 #define KLCONFIG_MEMBNK_PREMIUM(_info, _bank)  \

-                            ((_info)->membnk_attr & (MEMBNK_PREMIUM << (_bank)))
+                           ((_info)->membnk_attr & (MEMBNK_PREMIUM << (_bank)))

 
 #define MAX_SERIAL_NUM_SIZE 10
 
 typedef struct klmod_serial_num_s {
 
 #define MAX_SERIAL_NUM_SIZE 10
 
 typedef struct klmod_serial_num_s {

-      klinfo_t        snum_info;
+      klinfo_t       snum_info;

       union {
       union {

-              char snum_str[MAX_SERIAL_NUM_SIZE];
-              unsigned long long       snum_int;
+             char snum_str[MAX_SERIAL_NUM_SIZE];
+             unsigned long long       snum_int;

       } snum;
 } klmod_serial_num_t;
 
       } snum;
 } klmod_serial_num_t;
 


@@ -650,43 +650,43 @@ typedef struct klmod_serial_num_s {
    serial number struct as a component without losing compatibility
    between prom versions. */
 
    serial number struct as a component without losing compatibility
    between prom versions. */
 

-#define GET_SNUM_COMP(_l)      ((klmod_serial_num_t *)\
+#define GET_SNUM_COMP(_l)      ((klmod_serial_num_t *)\

                                KLCF_COMP(_l, _l->brd_numcompts))
 
 #define MAX_XBOW_LINKS 16
 
                                KLCF_COMP(_l, _l->brd_numcompts))
 
 #define MAX_XBOW_LINKS 16
 

-typedef struct klxbow_s {                          /* XBOW */
-       klinfo_t        xbow_info ;
+typedef struct klxbow_s {                         /* XBOW */
+       klinfo_t        xbow_info ;

        klport_t        xbow_port_info[MAX_XBOW_LINKS] ; /* Module number */
        klport_t        xbow_port_info[MAX_XBOW_LINKS] ; /* Module number */

-        int            xbow_master_hub_link;
-        /* type of brd connected+component struct ptr+flags */
+       int             xbow_master_hub_link;
+       /* type of brd connected+component struct ptr+flags */

 } klxbow_t ;
 
 #define MAX_PCI_SLOTS 8
 
 typedef struct klpci_device_s {
        s32     pci_device_id;  /* 32 bits of vendor/device ID. */
 } klxbow_t ;
 
 #define MAX_PCI_SLOTS 8
 
 typedef struct klpci_device_s {
        s32     pci_device_id;  /* 32 bits of vendor/device ID. */

-       s32     pci_device_pad; /* 32 bits of padding. */
+       s32     pci_device_pad; /* 32 bits of padding. */

 } klpci_device_t;
 
 #define BRIDGE_STRUCT_VERSION  2
 
 } klpci_device_t;
 
 #define BRIDGE_STRUCT_VERSION  2
 

-typedef struct klbri_s {                          /* BRIDGE */
-       klinfo_t        bri_info ;
-       unsigned char   bri_eprominfo ;    /* IO6prom connected to bridge */
-       unsigned char   bri_bustype ;      /* PCI/VME BUS bridge/GIO */
-       pci_t           pci_specific  ;    /* PCI Board config info */
+typedef struct klbri_s {                         /* BRIDGE */
+       klinfo_t        bri_info ;
+       unsigned char   bri_eprominfo ;    /* IO6prom connected to bridge */
+       unsigned char   bri_bustype ;      /* PCI/VME BUS bridge/GIO */
+       pci_t           pci_specific  ;    /* PCI Board config info */

        klpci_device_t  bri_devices[MAX_PCI_DEVS] ;     /* PCI IDs */
        klconf_off_t    bri_mfg_nic ;
 } klbri_t ;
 
 #define MAX_IOC3_TTY   2
 
        klpci_device_t  bri_devices[MAX_PCI_DEVS] ;     /* PCI IDs */
        klconf_off_t    bri_mfg_nic ;
 } klbri_t ;
 
 #define MAX_IOC3_TTY   2
 

-typedef struct klioc3_s {                          /* IOC3 */
-       klinfo_t        ioc3_info ;
-       unsigned char   ioc3_ssram ;        /* Info about ssram */
-       unsigned char   ioc3_nvram ;        /* Info about nvram */
-       klinfo_t        ioc3_superio ;      /* Info about superio */
+typedef struct klioc3_s {                         /* IOC3 */
+       klinfo_t        ioc3_info ;
+       unsigned char   ioc3_ssram ;        /* Info about ssram */
+       unsigned char   ioc3_nvram ;        /* Info about nvram */
+       klinfo_t        ioc3_superio ;      /* Info about superio */

        klconf_off_t    ioc3_tty_off ;
        klinfo_t        ioc3_enet ;
        klconf_off_t    ioc3_enet_off ;
        klconf_off_t    ioc3_tty_off ;
        klinfo_t        ioc3_enet ;
        klconf_off_t    ioc3_enet_off ;


@@ -695,27 +695,27 @@ typedef struct klioc3_s {                          /* IOC3 */
 
 #define MAX_VME_SLOTS 8
 
 
 #define MAX_VME_SLOTS 8
 

-typedef struct klvmeb_s {                          /* VME BRIDGE - PCI CTLR */
-       klinfo_t        vmeb_info ;
+typedef struct klvmeb_s {                         /* VME BRIDGE - PCI CTLR */
+       klinfo_t        vmeb_info ;

        vmeb_t          vmeb_specific ;
        vmeb_t          vmeb_specific ;

-       klconf_off_t    vmeb_brdinfo[MAX_VME_SLOTS]   ;    /* VME Board config info */
+       klconf_off_t    vmeb_brdinfo[MAX_VME_SLOTS]   ;    /* VME Board config info */

 } klvmeb_t ;
 
 } klvmeb_t ;
 

-typedef struct klvmed_s {                          /* VME DEVICE - VME BOARD */
+typedef struct klvmed_s {                         /* VME DEVICE - VME BOARD */

        klinfo_t        vmed_info ;
        vmed_t          vmed_specific ;
        klinfo_t        vmed_info ;
        vmed_t          vmed_specific ;

-       klconf_off_t    vmed_brdinfo[MAX_VME_SLOTS]   ;    /* VME Board config info */
+       klconf_off_t    vmed_brdinfo[MAX_VME_SLOTS]   ;    /* VME Board config info */

 } klvmed_t ;
 
 #define ROUTER_VECTOR_VERS     2
 
 /* XXX - Don't we need the number of ports here?!? */
 } klvmed_t ;
 
 #define ROUTER_VECTOR_VERS     2
 
 /* XXX - Don't we need the number of ports here?!? */

-typedef struct klrou_s {                          /* ROUTER */
-       klinfo_t        rou_info ;
-       unsigned int            rou_flags ;           /* PCFG_ROUTER_xxx flags */
-       nic_t           rou_box_nic ;         /* nic of the containing module */
-       klport_t        rou_port[MAX_ROUTER_PORTS + 1] ; /* array index 1 to 6 */
-       klconf_off_t    rou_mfg_nic ;     /* MFG NIC string */
+typedef struct klrou_s {                         /* ROUTER */
+       klinfo_t        rou_info ;
+       unsigned int            rou_flags ;           /* PCFG_ROUTER_xxx flags */
+       nic_t           rou_box_nic ;         /* nic of the containing module */
+       klport_t        rou_port[MAX_ROUTER_PORTS + 1] ; /* array index 1 to 6 */
+       klconf_off_t    rou_mfg_nic ;     /* MFG NIC string */

        u64     rou_vector;       /* vector from master node */
 } klrou_t ;
 
        u64     rou_vector;       /* vector from master node */
 } klrou_t ;
 


@@ -732,30 +732,30 @@ typedef struct klrou_s {                          /* ROUTER */
 #define KLGFX_COOKIE   0x0c0de000
 
 typedef struct klgfx_s {               /* GRAPHICS Device */
 #define KLGFX_COOKIE   0x0c0de000
 
 typedef struct klgfx_s {               /* GRAPHICS Device */

-       klinfo_t        gfx_info;
-       klconf_off_t    old_gndevs;     /* for compatibility with older proms */
-       klconf_off_t    old_gdoff0;     /* for compatibility with older proms */
+       klinfo_t        gfx_info;
+       klconf_off_t    old_gndevs;     /* for compatibility with older proms */
+       klconf_off_t    old_gdoff0;     /* for compatibility with older proms */

        unsigned int            cookie;         /* for compatibility with older proms */
        unsigned int            moduleslot;
        struct klgfx_s  *gfx_next_pipe;
        graphics_t      gfx_specific;
        unsigned int            cookie;         /* for compatibility with older proms */
        unsigned int            moduleslot;
        struct klgfx_s  *gfx_next_pipe;
        graphics_t      gfx_specific;

-       klconf_off_t    pad0;           /* for compatibility with older proms */
-       klconf_off_t    gfx_mfg_nic;
+       klconf_off_t    pad0;           /* for compatibility with older proms */
+       klconf_off_t    gfx_mfg_nic;

 } klgfx_t;
 
 typedef struct klxthd_s {
 } klgfx_t;
 
 typedef struct klxthd_s {

-       klinfo_t        xthd_info ;
-       klconf_off_t    xthd_mfg_nic ;        /* MFG NIC string */
+       klinfo_t        xthd_info ;
+       klconf_off_t    xthd_mfg_nic ;        /* MFG NIC string */

 } klxthd_t ;
 
 } klxthd_t ;
 

-typedef struct kltpu_s {                     /* TPU board */
-       klinfo_t        tpu_info ;
-       klconf_off_t    tpu_mfg_nic ;        /* MFG NIC string */
+typedef struct kltpu_s {                    /* TPU board */
+       klinfo_t        tpu_info ;
+       klconf_off_t    tpu_mfg_nic ;        /* MFG NIC string */

 } kltpu_t ;
 
 } kltpu_t ;
 

-typedef struct klgsn_s {                     /* GSN board */
-       klinfo_t        gsn_info ;
-       klconf_off_t    gsn_mfg_nic ;        /* MFG NIC string */
+typedef struct klgsn_s {                    /* GSN board */
+       klinfo_t        gsn_info ;
+       klconf_off_t    gsn_mfg_nic ;        /* MFG NIC string */

 } klgsn_t ;
 
 #define MAX_SCSI_DEVS 16
 } klgsn_t ;
 
 #define MAX_SCSI_DEVS 16


@@ -767,57 +767,57 @@ typedef struct klgsn_s {                     /* GSN board */
  * that as the size to be klmalloced.
  */
 
  * that as the size to be klmalloced.
  */
 

-typedef struct klscsi_s {                          /* SCSI Controller */
-       klinfo_t        scsi_info ;
-       scsi_t          scsi_specific   ;
-       unsigned char   scsi_numdevs ;
+typedef struct klscsi_s {                         /* SCSI Controller */
+       klinfo_t        scsi_info ;
+       scsi_t          scsi_specific   ;
+       unsigned char   scsi_numdevs ;

        klconf_off_t    scsi_devinfo[MAX_SCSI_DEVS] ;
 } klscsi_t ;
 
        klconf_off_t    scsi_devinfo[MAX_SCSI_DEVS] ;
 } klscsi_t ;
 

-typedef struct klscdev_s {                          /* SCSI device */
-       klinfo_t        scdev_info ;
+typedef struct klscdev_s {                         /* SCSI device */
+       klinfo_t        scdev_info ;

        struct scsidisk_data *scdev_cfg ; /* driver fills up this */
 } klscdev_t ;
 
        struct scsidisk_data *scdev_cfg ; /* driver fills up this */
 } klscdev_t ;
 

-typedef struct klttydev_s {                          /* TTY device */
-       klinfo_t        ttydev_info ;
+typedef struct klttydev_s {                         /* TTY device */
+       klinfo_t        ttydev_info ;

        struct terminal_data *ttydev_cfg ; /* driver fills up this */
 } klttydev_t ;
 
        struct terminal_data *ttydev_cfg ; /* driver fills up this */
 } klttydev_t ;
 

-typedef struct klenetdev_s {                          /* ENET device */
-       klinfo_t        enetdev_info ;
+typedef struct klenetdev_s {                         /* ENET device */
+       klinfo_t        enetdev_info ;

        struct net_data *enetdev_cfg ; /* driver fills up this */
 } klenetdev_t ;
 
        struct net_data *enetdev_cfg ; /* driver fills up this */
 } klenetdev_t ;
 

-typedef struct klkbddev_s {                          /* KBD device */
-       klinfo_t        kbddev_info ;
+typedef struct klkbddev_s {                         /* KBD device */
+       klinfo_t        kbddev_info ;

        struct keyboard_data *kbddev_cfg ; /* driver fills up this */
 } klkbddev_t ;
 
        struct keyboard_data *kbddev_cfg ; /* driver fills up this */
 } klkbddev_t ;
 

-typedef struct klmsdev_s {                          /* mouse device */
-        klinfo_t        msdev_info ;
-        void           *msdev_cfg ;
+typedef struct klmsdev_s {                         /* mouse device */
+       klinfo_t        msdev_info ;
+       void            *msdev_cfg ;

 } klmsdev_t ;
 
 #define MAX_FDDI_DEVS 10 /* XXX Is this true */
 
 } klmsdev_t ;
 
 #define MAX_FDDI_DEVS 10 /* XXX Is this true */
 

-typedef struct klfddi_s {                          /* FDDI */
-       klinfo_t        fddi_info ;
-       fddi_t          fddi_specific ;
+typedef struct klfddi_s {                         /* FDDI */
+       klinfo_t        fddi_info ;
+       fddi_t          fddi_specific ;

        klconf_off_t    fddi_devinfo[MAX_FDDI_DEVS] ;
 } klfddi_t ;
 
        klconf_off_t    fddi_devinfo[MAX_FDDI_DEVS] ;
 } klfddi_t ;
 

-typedef struct klmio_s {                          /* MIO */
-       klinfo_t        mio_info ;
-       mio_t           mio_specific   ;
+typedef struct klmio_s {                         /* MIO */
+       klinfo_t        mio_info ;
+       mio_t           mio_specific   ;

 } klmio_t ;
 
 
 typedef union klcomp_s {
        klcpu_t         kc_cpu;
        klhub_t         kc_hub;
 } klmio_t ;
 
 
 typedef union klcomp_s {
        klcpu_t         kc_cpu;
        klhub_t         kc_hub;

-       klmembnk_t      kc_mem;
-       klxbow_t        kc_xbow;
+       klmembnk_t      kc_mem;
+       klxbow_t        kc_xbow;

        klbri_t         kc_bri;
        klioc3_t        kc_ioc3;
        klvmeb_t        kc_vmeb;
        klbri_t         kc_bri;
        klioc3_t        kc_ioc3;
        klvmeb_t        kc_vmeb;


@@ -831,11 +831,11 @@ typedef union klcomp_s {
        klmod_serial_num_t kc_snum ;
 } klcomp_t;
 
        klmod_serial_num_t kc_snum ;
 } klcomp_t;
 

-typedef union kldev_s {      /* for device structure allocation */
+typedef union kldev_s {             /* for device structure allocation */

        klscdev_t       kc_scsi_dev ;
        klttydev_t      kc_tty_dev ;
        klenetdev_t     kc_enet_dev ;
        klscdev_t       kc_scsi_dev ;
        klttydev_t      kc_tty_dev ;
        klenetdev_t     kc_enet_dev ;

-       klkbddev_t      kc_kbd_dev ;
+       klkbddev_t      kc_kbd_dev ;

 } kldev_t ;
 
 /* Data structure interface routines. TBD */
 } kldev_t ;
 
 /* Data structure interface routines. TBD */

diff --git a/arch/mips/include/asm/sn/kldir.h b/arch/mips/include/asm/sn/kldir.h
index 1327e12e96456c02b3d953a5aff0268eca06dfb7..bfb3aec9453940348f99a98287b357ac316e1041 100644 (file)
--- a/arch/mips/include/asm/sn/kldir.h
+++ b/arch/mips/include/asm/sn/kldir.h
@@ -16,8 +16,8 @@
  * The kldir memory area resides at a fixed place in each node's memory and
  * provides pointers to most other IP27 memory areas.  This allows us to
  * resize and/or relocate memory areas at a later time without breaking all
  * The kldir memory area resides at a fixed place in each node's memory and
  * provides pointers to most other IP27 memory areas.  This allows us to
  * resize and/or relocate memory areas at a later time without breaking all

- * firmware and kernels that use them.  Indices in the array are
- * permanently dedicated to areas listed below.  Some memory areas (marked
+ * firmware and kernels that use them. Indices in the array are
+ * permanently dedicated to areas listed below.         Some memory areas (marked

  * below) reside at a permanently fixed location, but are included in the
  * directory for completeness.
  */
  * below) reside at a permanently fixed location, but are included in the
  * directory for completeness.
  */


@@ -28,98 +28,98 @@
  * The upper portion of the memory map applies during boot
  * only and is overwritten by IRIX/SYMMON.
  *
  * The upper portion of the memory map applies during boot
  * only and is overwritten by IRIX/SYMMON.
  *

- *                                    MEMORY MAP PER NODE
+ *                                   MEMORY MAP PER NODE

  *
  *

- * 0x2000000 (32M)         +-----------------------------------------+
- *                         |      IO6 BUFFERS FOR FLASH ENET IOC3    |
- * 0x1F80000 (31.5M)       +-----------------------------------------+
- *                         |      IO6 TEXT/DATA/BSS/stack            |
- * 0x1C00000 (30M)         +-----------------------------------------+
- *                         |      IO6 PROM DEBUG TEXT/DATA/BSS/stack |
- * 0x0800000 (28M)         +-----------------------------------------+
- *                         |      IP27 PROM TEXT/DATA/BSS/stack      |
- * 0x1B00000 (27M)         +-----------------------------------------+
- *                         |      IP27 CFG                           |
- * 0x1A00000 (26M)         +-----------------------------------------+
- *                         |      Graphics PROM                      |
- * 0x1800000 (24M)         +-----------------------------------------+
- *                         |      3rd Party PROM drivers             |
- * 0x1600000 (22M)         +-----------------------------------------+
- *                         |                                         |
- *                         |      Free                               |
- *                         |                                         |
- *                         +-----------------------------------------+
- *                         |      UNIX DEBUG Version                 |
- * 0x190000 (2M--)         +-----------------------------------------+
- *                         |      SYMMON                             |
- *                         |      (For UNIX Debug only)              |
- * 0x34000 (208K)          +-----------------------------------------+
- *                         |      SYMMON STACK [NUM_CPU_PER_NODE]    |
- *                         |      (For UNIX Debug only)              |
- * 0x25000 (148K)          +-----------------------------------------+
- *                         |      KLCONFIG - II (temp)               |
- *                         |                                         |
- *                         |    ----------------------------         |
- *                         |                                         |
- *                         |      UNIX NON-DEBUG Version             |
- * 0x19000 (100K)          +-----------------------------------------+
+ * 0x2000000 (32M)        +-----------------------------------------+
+ *                        |      IO6 BUFFERS FOR FLASH ENET IOC3    |
+ * 0x1F80000 (31.5M)      +-----------------------------------------+
+ *                        |      IO6 TEXT/DATA/BSS/stack            |
+ * 0x1C00000 (30M)        +-----------------------------------------+
+ *                        |      IO6 PROM DEBUG TEXT/DATA/BSS/stack |
+ * 0x0800000 (28M)        +-----------------------------------------+
+ *                        |      IP27 PROM TEXT/DATA/BSS/stack      |
+ * 0x1B00000 (27M)        +-----------------------------------------+
+ *                        |      IP27 CFG                           |
+ * 0x1A00000 (26M)        +-----------------------------------------+
+ *                        |      Graphics PROM                      |
+ * 0x1800000 (24M)        +-----------------------------------------+
+ *                        |      3rd Party PROM drivers             |
+ * 0x1600000 (22M)        +-----------------------------------------+
+ *                        |                                         |
+ *                        |      Free                               |
+ *                        |                                         |
+ *                        +-----------------------------------------+
+ *                        |      UNIX DEBUG Version                 |
+ * 0x190000 (2M--)        +-----------------------------------------+
+ *                        |      SYMMON                             |
+ *                        |      (For UNIX Debug only)              |
+ * 0x34000 (208K)         +-----------------------------------------+
+ *                        |      SYMMON STACK [NUM_CPU_PER_NODE]    |
+ *                        |      (For UNIX Debug only)              |
+ * 0x25000 (148K)         +-----------------------------------------+
+ *                        |      KLCONFIG - II (temp)               |
+ *                        |                                         |
+ *                        |    ----------------------------         |
+ *                        |                                         |
+ *                        |      UNIX NON-DEBUG Version             |
+ * 0x19000 (100K)         +-----------------------------------------+

  *
  *
  * The lower portion of the memory map contains information that is
  * permanent and is used by the IP27PROM, IO6PROM and IRIX.
  *
  *
  *
  * The lower portion of the memory map contains information that is
  * permanent and is used by the IP27PROM, IO6PROM and IRIX.
  *

- * 0x19000 (100K)          +-----------------------------------------+
- *                         |                                         |
- *                         |      PI Error Spools (32K)              |
- *                         |                                         |
- * 0x12000 (72K)           +-----------------------------------------+
- *                         |      Unused                             |
- * 0x11c00 (71K)           +-----------------------------------------+
- *                         |      CPU 1 NMI Eframe area             |
- * 0x11a00 (70.5K)         +-----------------------------------------+
- *                         |      CPU 0 NMI Eframe area             |
- * 0x11800 (70K)           +-----------------------------------------+
- *                         |      CPU 1 NMI Register save area       |
- * 0x11600 (69.5K)         +-----------------------------------------+
- *                         |      CPU 0 NMI Register save area       |
- * 0x11400 (69K)           +-----------------------------------------+
- *                         |      GDA (1k)                           |
- * 0x11000 (68K)           +-----------------------------------------+
- *                         |      Early cache Exception stack        |
- *                         |             and/or                      |
- *                        |      kernel/io6prom nmi registers       |
+ * 0x19000 (100K)         +-----------------------------------------+
+ *                        |                                         |
+ *                        |      PI Error Spools (32K)              |
+ *                        |                                         |
+ * 0x12000 (72K)          +-----------------------------------------+
+ *                        |      Unused                             |
+ * 0x11c00 (71K)          +-----------------------------------------+
+ *                        |      CPU 1 NMI Eframe area              |
+ * 0x11a00 (70.5K)        +-----------------------------------------+
+ *                        |      CPU 0 NMI Eframe area              |
+ * 0x11800 (70K)          +-----------------------------------------+
+ *                        |      CPU 1 NMI Register save area       |
+ * 0x11600 (69.5K)        +-----------------------------------------+
+ *                        |      CPU 0 NMI Register save area       |
+ * 0x11400 (69K)          +-----------------------------------------+
+ *                        |      GDA (1k)                           |
+ * 0x11000 (68K)          +-----------------------------------------+
+ *                        |      Early cache Exception stack        |
+ *                        |             and/or                      |
+ *                        |      kernel/io6prom nmi registers       |

  * 0x10800  (66k)         +-----------------------------------------+
  * 0x10800  (66k)         +-----------------------------------------+

- *                        |      cache error eframe                 |
- * 0x10400 (65K)           +-----------------------------------------+
- *                         |      Exception Handlers (UALIAS copy)   |
- * 0x10000 (64K)           +-----------------------------------------+
- *                         |                                         |
- *                         |                                         |
- *                         |      KLCONFIG - I (permanent) (48K)     |
- *                         |                                         |
- *                         |                                         |
- *                         |                                         |
- * 0x4000 (16K)            +-----------------------------------------+
- *                         |      NMI Handler (Protected Page)       |
- * 0x3000 (12K)            +-----------------------------------------+
- *                         |      ARCS PVECTORS (master node only)   |
- * 0x2c00 (11K)            +-----------------------------------------+
- *                         |      ARCS TVECTORS (master node only)   |
- * 0x2800 (10K)            +-----------------------------------------+
- *                         |      LAUNCH [NUM_CPU]                   |
- * 0x2400 (9K)             +-----------------------------------------+
- *                         |      Low memory directory (KLDIR)       |
- * 0x2000 (8K)             +-----------------------------------------+
- *                         |      ARCS SPB (1K)                      |
- * 0x1000 (4K)             +-----------------------------------------+
- *                         |      Early cache Exception stack        |
- *                         |             and/or                      |
- *                        |      kernel/io6prom nmi registers       |
- * 0x800  (2k)            +-----------------------------------------+
- *                        |      cache error eframe                 |
- * 0x400 (1K)              +-----------------------------------------+
- *                         |      Exception Handlers                 |
- * 0x0   (0K)              +-----------------------------------------+
+ *                        |      cache error eframe                 |
+ * 0x10400 (65K)          +-----------------------------------------+
+ *                        |      Exception Handlers (UALIAS copy)   |
+ * 0x10000 (64K)          +-----------------------------------------+
+ *                        |                                         |
+ *                        |                                         |
+ *                        |      KLCONFIG - I (permanent) (48K)     |
+ *                        |                                         |
+ *                        |                                         |
+ *                        |                                         |
+ * 0x4000 (16K)                   +-----------------------------------------+
+ *                        |      NMI Handler (Protected Page)       |
+ * 0x3000 (12K)                   +-----------------------------------------+
+ *                        |      ARCS PVECTORS (master node only)   |
+ * 0x2c00 (11K)                   +-----------------------------------------+
+ *                        |      ARCS TVECTORS (master node only)   |
+ * 0x2800 (10K)                   +-----------------------------------------+
+ *                        |      LAUNCH [NUM_CPU]                   |
+ * 0x2400 (9K)            +-----------------------------------------+
+ *                        |      Low memory directory (KLDIR)       |
+ * 0x2000 (8K)            +-----------------------------------------+
+ *                        |      ARCS SPB (1K)                      |
+ * 0x1000 (4K)            +-----------------------------------------+
+ *                        |      Early cache Exception stack        |
+ *                        |             and/or                      |
+ *                        |      kernel/io6prom nmi registers       |
+ * 0x800  (2k)            +-----------------------------------------+
+ *                        |      cache error eframe                 |
+ * 0x400 (1K)             +-----------------------------------------+
+ *                        |      Exception Handlers                 |
+ * 0x0  (0K)              +-----------------------------------------+

  */
 
 #ifdef __ASSEMBLY__
  */
 
 #ifdef __ASSEMBLY__


@@ -202,13 +202,13 @@
 
 #ifndef __ASSEMBLY__
 typedef struct kldir_ent_s {
 
 #ifndef __ASSEMBLY__
 typedef struct kldir_ent_s {

-       u64             magic;          /* Indicates validity of entry      */
+       u64             magic;          /* Indicates validity of entry      */

        off_t           offset;         /* Offset from start of node space  */
        unsigned long   pointer;        /* Pointer to area in some cases    */
        off_t           offset;         /* Offset from start of node space  */
        unsigned long   pointer;        /* Pointer to area in some cases    */

-       size_t          size;           /* Size in bytes                    */
+       size_t          size;           /* Size in bytes                    */

        u64             count;          /* Repeat count if array, 1 if not  */
        u64             count;          /* Repeat count if array, 1 if not  */

-       size_t          stride;         /* Stride if array, 0 if not        */
-       char            rsvd[16];       /* Pad entry to 0x40 bytes          */
+       size_t          stride;         /* Stride if array, 0 if not        */
+       char            rsvd[16];       /* Pad entry to 0x40 bytes          */

        /* NOTE: These 16 bytes are used in the Partition KLDIR
           entry to store partition info. Refer to klpart.h for this. */
 } kldir_ent_t;
        /* NOTE: These 16 bytes are used in the Partition KLDIR
           entry to store partition info. Refer to klpart.h for this. */
 } kldir_ent_t;

diff --git a/arch/mips/include/asm/sn/launch.h b/arch/mips/include/asm/sn/launch.h
index b7c2226312c627122183ac8d18d7c74ee39b49f3..04226d8d30c42c6ea8bcc1b074f2851622dab481 100644 (file)
--- a/arch/mips/include/asm/sn/launch.h
+++ b/arch/mips/include/asm/sn/launch.h
@@ -19,7 +19,7 @@
  *
  * The master stores launch parameters in the launch structure
  * corresponding to a target processor that is in a slave loop, then sends
  *
  * The master stores launch parameters in the launch structure
  * corresponding to a target processor that is in a slave loop, then sends

- * an interrupt to the slave processor.  The slave calls the desired
+ * an interrupt to the slave processor.         The slave calls the desired

  * function, then returns to the slave loop.  The master may poll or wait
  * for the slaves to finish.
  *
  * function, then returns to the slave loop.  The master may poll or wait
  * for the slaves to finish.
  *


@@ -33,7 +33,7 @@
 #define LAUNCH_PADSZ           0xa0
 #endif
 
 #define LAUNCH_PADSZ           0xa0
 #endif
 

-#define LAUNCH_OFF_MAGIC       0x00    /* Struct offsets for assembly      */
+#define LAUNCH_OFF_MAGIC       0x00    /* Struct offsets for assembly      */

 #define LAUNCH_OFF_BUSY                0x08
 #define LAUNCH_OFF_CALL                0x10
 #define LAUNCH_OFF_CALLC       0x18
 #define LAUNCH_OFF_BUSY                0x08
 #define LAUNCH_OFF_CALL                0x10
 #define LAUNCH_OFF_CALLC       0x18


@@ -44,7 +44,7 @@
 #define LAUNCH_OFF_BEVNORMAL   0x40
 #define LAUNCH_OFF_BEVECC      0x48
 
 #define LAUNCH_OFF_BEVNORMAL   0x40
 #define LAUNCH_OFF_BEVECC      0x48
 

-#define LAUNCH_STATE_DONE      0       /* Return value of LAUNCH_POLL      */
+#define LAUNCH_STATE_DONE      0       /* Return value of LAUNCH_POLL      */

 #define LAUNCH_STATE_SENT      1
 #define LAUNCH_STATE_RECD      2
 
 #define LAUNCH_STATE_SENT      1
 #define LAUNCH_STATE_RECD      2
 


@@ -65,16 +65,16 @@ typedef int launch_state_t;
 typedef void (*launch_proc_t)(u64 call_parm);
 
 typedef struct launch_s {
 typedef void (*launch_proc_t)(u64 call_parm);
 
 typedef struct launch_s {

-       volatile u64            magic;  /* Magic number                     */
-       volatile u64            busy;   /* Slave currently active           */
+       volatile u64            magic;  /* Magic number                     */
+       volatile u64            busy;   /* Slave currently active           */

        volatile launch_proc_t  call_addr;      /* Func. for slave to call  */
        volatile u64            call_addr_c;    /* 1's complement of call_addr*/
        volatile u64            call_parm;      /* Single parm passed to call*/
        volatile void *stack_addr;      /* Stack pointer for slave function */
        volatile void *gp_addr;         /* Global pointer for slave func.   */
        volatile launch_proc_t  call_addr;      /* Func. for slave to call  */
        volatile u64            call_addr_c;    /* 1's complement of call_addr*/
        volatile u64            call_parm;      /* Single parm passed to call*/
        volatile void *stack_addr;      /* Stack pointer for slave function */
        volatile void *gp_addr;         /* Global pointer for slave func.   */

-       volatile char           *bevutlb;/* Address of bev utlb ex handler   */
-       volatile char           *bevnormal;/*Address of bev normal ex handler */
-       volatile char           *bevecc;/* Address of bev cache err handler */
+       volatile char           *bevutlb;/* Address of bev utlb ex handler   */
+       volatile char           *bevnormal;/*Address of bev normal ex handler */
+       volatile char           *bevecc;/* Address of bev cache err handler */

        volatile char           pad[160];       /* Pad to LAUNCH_SIZEOF     */
 } launch_t;
 
        volatile char           pad[160];       /* Pad to LAUNCH_SIZEOF     */
 } launch_t;
 

diff --git a/arch/mips/include/asm/sn/mapped_kernel.h b/arch/mips/include/asm/sn/mapped_kernel.h
index 721496a0bb92979161c8ed3cc2946f7c069d256d..401f3b0eee17ec74b085bca4292821be2ab7b035 100644 (file)
--- a/arch/mips/include/asm/sn/mapped_kernel.h
+++ b/arch/mips/include/asm/sn/mapped_kernel.h
@@ -48,7 +48,7 @@
 
 #endif /* CONFIG_MAPPED_KERNEL */
 
 
 #endif /* CONFIG_MAPPED_KERNEL */
 

-#define MAPPED_KERN_RO_TO_K0(x)        PHYS_TO_K0(MAPPED_KERN_RO_TO_PHYS(x))
-#define MAPPED_KERN_RW_TO_K0(x)        PHYS_TO_K0(MAPPED_KERN_RW_TO_PHYS(x))
+#define MAPPED_KERN_RO_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RO_TO_PHYS(x))
+#define MAPPED_KERN_RW_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RW_TO_PHYS(x))

 
 #endif /* __ASM_SN_MAPPED_KERNEL_H  */
 
 #endif /* __ASM_SN_MAPPED_KERNEL_H  */

diff --git a/arch/mips/include/asm/sn/nmi.h b/arch/mips/include/asm/sn/nmi.h
index 1af49897d4e169635e345b355090e6f0aafda0b5..12ac210f12a174ca66ab1be6f70d4aeaf4f2f238 100644 (file)
--- a/arch/mips/include/asm/sn/nmi.h
+++ b/arch/mips/include/asm/sn/nmi.h
@@ -19,7 +19,7 @@
  *
  * The master stores launch parameters in the launch structure
  * corresponding to a target processor that is in a slave loop, then sends
  *
  * The master stores launch parameters in the launch structure
  * corresponding to a target processor that is in a slave loop, then sends

- * an interrupt to the slave processor.  The slave calls the desired
+ * an interrupt to the slave processor.         The slave calls the desired

  * function, followed by an optional rendezvous function, then returns to
  * the slave loop.  The master does not wait for the slaves before
  * returning.
  * function, followed by an optional rendezvous function, then returns to
  * the slave loop.  The master does not wait for the slaves before
  * returning.


@@ -31,7 +31,7 @@
 #define NMI_MAGIC              0x48414d4d455201
 #define NMI_SIZEOF             0x40
 
 #define NMI_MAGIC              0x48414d4d455201
 #define NMI_SIZEOF             0x40
 

-#define NMI_OFF_MAGIC          0x00    /* Struct offsets for assembly      */
+#define NMI_OFF_MAGIC          0x00    /* Struct offsets for assembly      */

 #define NMI_OFF_FLAGS          0x08
 #define NMI_OFF_CALL           0x10
 #define NMI_OFF_CALLC          0x18
 #define NMI_OFF_FLAGS          0x08
 #define NMI_OFF_CALL           0x10
 #define NMI_OFF_CALLC          0x18


@@ -53,8 +53,8 @@
 typedef struct nmi_s {
        volatile unsigned long   magic;         /* Magic number */
        volatile unsigned long   flags;         /* Combination of flags above */
 typedef struct nmi_s {
        volatile unsigned long   magic;         /* Magic number */
        volatile unsigned long   flags;         /* Combination of flags above */

-       volatile void *call_addr;       /* Routine for slave to call        */
-       volatile void *call_addr_c;     /* 1's complement of address        */
+       volatile void *call_addr;       /* Routine for slave to call        */
+       volatile void *call_addr_c;     /* 1's complement of address        */

        volatile void *call_parm;       /* Single parm passed to call       */
        volatile unsigned long   gmaster;       /* Flag true only on global master*/
 } nmi_t;
        volatile void *call_parm;       /* Single parm passed to call       */
        volatile unsigned long   gmaster;       /* Flag true only on global master*/
 } nmi_t;

diff --git a/arch/mips/include/asm/sn/sn0/addrs.h b/arch/mips/include/asm/sn/sn0/addrs.h
index b06190093bbc6093e0930bba4421b069afc0a92b..6b53070f400f03f2ea432dc063efd4daca0b3c80 100644 (file)
--- a/arch/mips/include/asm/sn/sn0/addrs.h
+++ b/arch/mips/include/asm/sn/sn0/addrs.h
@@ -29,7 +29,7 @@
  * chapter of the Hub specification.
  *
  * NOTE: This header file is included both by C and by assembler source
  * chapter of the Hub specification.
  *
  * NOTE: This header file is included both by C and by assembler source

- *      files.  Please bracket any language-dependent definitions
+ *      files.  Please bracket any language-dependent definitions

  *      appropriately.
  */
 
  *      appropriately.
  */
 


@@ -102,14 +102,14 @@
 
 #define BWIN_INDEX_BITS                3
 #define BWIN_SIZE              (UINT64_CAST 1 << BWIN_SIZE_BITS)
 
 #define BWIN_INDEX_BITS                3
 #define BWIN_SIZE              (UINT64_CAST 1 << BWIN_SIZE_BITS)

-#define        BWIN_SIZEMASK           (BWIN_SIZE - 1)
-#define        BWIN_WIDGET_MASK        0x7
+#define BWIN_SIZEMASK          (BWIN_SIZE - 1)
+#define BWIN_WIDGET_MASK       0x7

 #define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE)
 #define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE)

-#define NODE_BWIN_BASE(nasid, bigwin)  (NODE_BWIN_BASE0(nasid) +       \
+#define NODE_BWIN_BASE(nasid, bigwin)  (NODE_BWIN_BASE0(nasid) +       \

                        (UINT64_CAST(bigwin) << BWIN_SIZE_BITS))
 
                        (UINT64_CAST(bigwin) << BWIN_SIZE_BITS))
 

-#define        BWIN_WIDGETADDR(addr)   ((addr) & BWIN_SIZEMASK)
-#define        BWIN_WINDOWNUM(addr)    (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
+#define BWIN_WIDGETADDR(addr)  ((addr) & BWIN_SIZEMASK)
+#define BWIN_WINDOWNUM(addr)   (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)

 /*
  * Verify if addr belongs to large window address of node with "nasid"
  *
 /*
  * Verify if addr belongs to large window address of node with "nasid"
  *


@@ -120,7 +120,7 @@
  *
  */
 
  *
  */
 

-#define        NODE_BWIN_ADDR(nasid, addr)     \
+#define NODE_BWIN_ADDR(nasid, addr)    \

                (((addr) >= NODE_BWIN_BASE0(nasid)) && \
                 ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \
                                BWIN_SIZE)))
                (((addr) >= NODE_BWIN_BASE0(nasid)) && \
                 ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \
                                BWIN_SIZE)))


@@ -129,7 +129,7 @@
  * The following define the major position-independent aliases used
  * in SN0.
  *     CALIAS -- Varies in size, points to the first n bytes of memory
  * The following define the major position-independent aliases used
  * in SN0.
  *     CALIAS -- Varies in size, points to the first n bytes of memory

- *                     on the reader's node.
+ *                     on the reader's node.

  */
 
 #define CALIAS_BASE            CAC_BASE
  */
 
 #define CALIAS_BASE            CAC_BASE


@@ -146,7 +146,7 @@
 
 #ifndef __ASSEMBLY__
 #define KERN_NMI_ADDR(nasid, slice)                                    \
 
 #ifndef __ASSEMBLY__
 #define KERN_NMI_ADDR(nasid, slice)                                    \

-                    TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET +     \
+                   TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET +      \

                                  (IP27_NMI_KREGS_CPU_SIZE * (slice)))
 #endif /* !__ASSEMBLY__ */
 
                                  (IP27_NMI_KREGS_CPU_SIZE * (slice)))
 #endif /* !__ASSEMBLY__ */
 


@@ -203,7 +203,7 @@
 
 #define IO6PROM_BASE           PHYS_TO_K0(0x01c00000)
 #define IO6PROM_SIZE           0x400000
 
 #define IO6PROM_BASE           PHYS_TO_K0(0x01c00000)
 #define IO6PROM_SIZE           0x400000

-#define        IO6PROM_BASE_MAPPED     (UNCAC_BASE | 0x11c00000)
+#define IO6PROM_BASE_MAPPED    (UNCAC_BASE | 0x11c00000)

 #define IO6DPROM_BASE          PHYS_TO_K0(0x01c00000)
 #define IO6DPROM_SIZE          0x200000
 
 #define IO6DPROM_BASE          PHYS_TO_K0(0x01c00000)
 #define IO6DPROM_SIZE          0x200000
 

diff --git a/arch/mips/include/asm/sn/sn0/arch.h b/arch/mips/include/asm/sn/sn0/arch.h
index f734f2007f2400be504183c3386321f3e462be70..425a67e6a947b6f271233592d59f59a634036752 100644 (file)
--- a/arch/mips/include/asm/sn/sn0/arch.h
+++ b/arch/mips/include/asm/sn/sn0/arch.h
@@ -12,23 +12,23 @@
 #define _ASM_SN_SN0_ARCH_H
 
 
 #define _ASM_SN_SN0_ARCH_H
 
 

-#ifndef SN0XXL  /* 128 cpu SMP max */
+#ifndef SN0XXL /* 128 cpu SMP max */

 /*
  * This is the maximum number of nodes that can be part of a kernel.
  * Effectively, it's the maximum number of compact node ids (cnodeid_t).
  */
 /*
  * This is the maximum number of nodes that can be part of a kernel.
  * Effectively, it's the maximum number of compact node ids (cnodeid_t).
  */

-#define MAX_COMPACT_NODES       64
+#define MAX_COMPACT_NODES      64

 
 /*
  * MAXCPUS refers to the maximum number of CPUs in a single kernel.
  * This is not necessarily the same as MAXNODES * CPUS_PER_NODE
  */
 
 /*
  * MAXCPUS refers to the maximum number of CPUs in a single kernel.
  * This is not necessarily the same as MAXNODES * CPUS_PER_NODE
  */

-#define MAXCPUS                 128
+#define MAXCPUS                        128

 
 #else /* SN0XXL system */
 
 
 #else /* SN0XXL system */
 

-#define MAX_COMPACT_NODES       128
-#define MAXCPUS                 256
+#define MAX_COMPACT_NODES      128
+#define MAXCPUS                        256

 
 #endif /* SN0XXL */
 
 
 #endif /* SN0XXL */
 


@@ -41,9 +41,9 @@
 /*
  * MAX_REGIONS refers to the maximum number of hardware partitioned regions.
  */
 /*
  * MAX_REGIONS refers to the maximum number of hardware partitioned regions.
  */

-#define        MAX_REGIONS             64
-#define MAX_NONPREMIUM_REGIONS  16
-#define MAX_PREMIUM_REGIONS     MAX_REGIONS
+#define MAX_REGIONS            64
+#define MAX_NONPREMIUM_REGIONS 16
+#define MAX_PREMIUM_REGIONS    MAX_REGIONS

 
 /*
  * MAX_PARITIONS refers to the maximum number of logically defined
 
 /*
  * MAX_PARITIONS refers to the maximum number of logically defined


@@ -57,12 +57,12 @@
  * Slot constants for SN0
  */
 #ifdef CONFIG_SGI_SN_N_MODE
  * Slot constants for SN0
  */
 #ifdef CONFIG_SGI_SN_N_MODE

-#define MAX_MEM_SLOTS   16                      /* max slots per node */
+#define MAX_MEM_SLOTS  16                      /* max slots per node */

 #else /* !CONFIG_SGI_SN_N_MODE, assume CONFIG_SGI_SN_M_MODE */
 #else /* !CONFIG_SGI_SN_N_MODE, assume CONFIG_SGI_SN_M_MODE */

-#define MAX_MEM_SLOTS   32                      /* max slots per node */
+#define MAX_MEM_SLOTS  32                      /* max slots per node */

 #endif /* CONFIG_SGI_SN_M_MODE */
 
 #endif /* CONFIG_SGI_SN_M_MODE */
 

-#define SLOT_SHIFT             (27)
+#define SLOT_SHIFT             (27)

 #define SLOT_MIN_MEM_SIZE      (32*1024*1024)
 
 #define CPUS_PER_NODE          2       /* CPUs on a single hub */
 #define SLOT_MIN_MEM_SIZE      (32*1024*1024)
 
 #define CPUS_PER_NODE          2       /* CPUs on a single hub */

diff --git a/arch/mips/include/asm/sn/sn0/hub.h b/arch/mips/include/asm/sn/sn0/hub.h
index 3e228f8e79695ff386d3d8f56989486733697d4a..d78dd76d5dcfb370a90723016fcc3cb217e88bdc 100644 (file)
--- a/arch/mips/include/asm/sn/sn0/hub.h
+++ b/arch/mips/include/asm/sn/sn0/hub.h
@@ -19,8 +19,8 @@
 #define HUB_REV_2_0            2
 #define HUB_REV_2_1            3
 #define HUB_REV_2_2            4
 #define HUB_REV_2_0            2
 #define HUB_REV_2_1            3
 #define HUB_REV_2_2            4

-#define HUB_REV_2_3             5
-#define HUB_REV_2_4             6
+#define HUB_REV_2_3            5
+#define HUB_REV_2_4            6

 
 #define MAX_HUB_PATH           80
 
 
 #define MAX_HUB_PATH           80
 


@@ -32,9 +32,9 @@
 //#include <asm/sn/sn0/hubcore.h>
 
 /* Translation of uncached attributes */
 //#include <asm/sn/sn0/hubcore.h>
 
 /* Translation of uncached attributes */

-#define        UATTR_HSPEC     0
-#define        UATTR_IO        1
-#define        UATTR_MSPEC     2
-#define        UATTR_UNCAC     3
+#define UATTR_HSPEC    0
+#define UATTR_IO       1
+#define UATTR_MSPEC    2
+#define UATTR_UNCAC    3

 
 #endif /* _ASM_SN_SN0_HUB_H */
 
 #endif /* _ASM_SN_SN0_HUB_H */

diff --git a/arch/mips/include/asm/sn/sn0/hubio.h b/arch/mips/include/asm/sn/sn0/hubio.h
index 46286d8302a791765641b2f9b71e1103734016fc..5998b13e976498c42b32c34850115bb7388f533a 100644 (file)
--- a/arch/mips/include/asm/sn/sn0/hubio.h
+++ b/arch/mips/include/asm/sn/sn0/hubio.h
@@ -8,8 +8,8 @@
  * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
  * Copyright (C) 1999 by Ralf Baechle
  */
  * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
  * Copyright (C) 1999 by Ralf Baechle
  */

-#ifndef        _ASM_SGI_SN_SN0_HUBIO_H
-#define        _ASM_SGI_SN_SN0_HUBIO_H
+#ifndef _ASM_SGI_SN_SN0_HUBIO_H
+#define _ASM_SGI_SN_SN0_HUBIO_H

 
 /*
  * Hub I/O interface registers
 
 /*
  * Hub I/O interface registers


@@ -22,7 +22,7 @@
  * Slightly friendlier names for some common registers.
  * The hardware definitions follow.
  */
  * Slightly friendlier names for some common registers.
  * The hardware definitions follow.
  */

-#define IIO_WIDGET             IIO_WID      /* Widget identification */
+#define IIO_WIDGET             IIO_WID      /* Widget identification */

 #define IIO_WIDGET_STAT                IIO_WSTAT    /* Widget status register */
 #define IIO_WIDGET_CTRL                IIO_WCR      /* Widget control register */
 #define IIO_WIDGET_TOUT                IIO_WRTO     /* Widget request timeout */
 #define IIO_WIDGET_STAT                IIO_WSTAT    /* Widget status register */
 #define IIO_WIDGET_CTRL                IIO_WCR      /* Widget control register */
 #define IIO_WIDGET_TOUT                IIO_WRTO     /* Widget request timeout */


@@ -37,21 +37,21 @@
 #define IIO_XTALKCC_TOUT       IIO_IXCC     /* Xtalk credit count timeout*/
 #define IIO_XTALKTT_TOUT       IIO_IXTT     /* Xtalk tail timeout */
 #define IIO_IO_ERR_CLR         IIO_IECLR    /* IO error clear */
 #define IIO_XTALKCC_TOUT       IIO_IXCC     /* Xtalk credit count timeout*/
 #define IIO_XTALKTT_TOUT       IIO_IXTT     /* Xtalk tail timeout */
 #define IIO_IO_ERR_CLR         IIO_IECLR    /* IO error clear */

-#define IIO_BTE_CRB_CNT         IIO_IBCN     /* IO BTE CRB count */
+#define IIO_BTE_CRB_CNT                IIO_IBCN     /* IO BTE CRB count */

 
 #define IIO_LLP_CSR_IS_UP              0x00002000
 
 #define IIO_LLP_CSR_IS_UP              0x00002000

-#define        IIO_LLP_CSR_LLP_STAT_MASK       0x00003000
-#define        IIO_LLP_CSR_LLP_STAT_SHFT       12
+#define IIO_LLP_CSR_LLP_STAT_MASK      0x00003000
+#define IIO_LLP_CSR_LLP_STAT_SHFT      12

 
 /* key to IIO_PROTECT_OVRRD */
 #define IIO_PROTECT_OVRRD_KEY  0x53474972756c6573ull   /* "SGIrules" */
 
 /* BTE register names */
 #define IIO_BTE_STAT_0         IIO_IBLS_0   /* Also BTE length/status 0 */
 
 /* key to IIO_PROTECT_OVRRD */
 #define IIO_PROTECT_OVRRD_KEY  0x53474972756c6573ull   /* "SGIrules" */
 
 /* BTE register names */
 #define IIO_BTE_STAT_0         IIO_IBLS_0   /* Also BTE length/status 0 */

-#define IIO_BTE_SRC_0          IIO_IBSA_0   /* Also BTE source address  0 */
+#define IIO_BTE_SRC_0          IIO_IBSA_0   /* Also BTE source address  0 */

 #define IIO_BTE_DEST_0         IIO_IBDA_0   /* Also BTE dest. address 0 */
 #define IIO_BTE_CTRL_0         IIO_IBCT_0   /* Also BTE control/terminate 0 */
 #define IIO_BTE_DEST_0         IIO_IBDA_0   /* Also BTE dest. address 0 */
 #define IIO_BTE_CTRL_0         IIO_IBCT_0   /* Also BTE control/terminate 0 */

-#define IIO_BTE_NOTIFY_0       IIO_IBNA_0   /* Also BTE notification 0 */
+#define IIO_BTE_NOTIFY_0       IIO_IBNA_0   /* Also BTE notification 0 */

 #define IIO_BTE_INT_0          IIO_IBIA_0   /* Also BTE interrupt 0 */
 #define IIO_BTE_OFF_0          0            /* Base offset from BTE 0 regs. */
 #define IIO_BTE_OFF_1  IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */
 #define IIO_BTE_INT_0          IIO_IBIA_0   /* Also BTE interrupt 0 */
 #define IIO_BTE_OFF_0          0            /* Base offset from BTE 0 regs. */
 #define IIO_BTE_OFF_1  IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */


@@ -83,11 +83,11 @@
 #define IIO_WSTAT      0x400008        /* Widget status */
 #define IIO_WCR                0x400020        /* Widget control */
 
 #define IIO_WSTAT      0x400008        /* Widget status */
 #define IIO_WCR                0x400020        /* Widget control */
 

-#define        IIO_WSTAT_ECRAZY        (1ULL << 32)    /* Hub gone crazy */
-#define        IIO_WSTAT_TXRETRY       (1ULL << 9)     /* Hub Tx Retry timeout */
-#define        IIO_WSTAT_TXRETRY_MASK  (0x7F)
-#define        IIO_WSTAT_TXRETRY_SHFT  (16)
-#define        IIO_WSTAT_TXRETRY_CNT(w)        (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
+#define IIO_WSTAT_ECRAZY       (1ULL << 32)    /* Hub gone crazy */
+#define IIO_WSTAT_TXRETRY      (1ULL << 9)     /* Hub Tx Retry timeout */
+#define IIO_WSTAT_TXRETRY_MASK (0x7F)
+#define IIO_WSTAT_TXRETRY_SHFT (16)
+#define IIO_WSTAT_TXRETRY_CNT(w)       (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \

                                          IIO_WSTAT_TXRETRY_MASK)
 
 #define IIO_ILAPR      0x400100        /* Local Access Protection */
                                          IIO_WSTAT_TXRETRY_MASK)
 
 #define IIO_ILAPR      0x400100        /* Local Access Protection */


@@ -130,12 +130,12 @@
 #define IIO_IGFX_INIT(widget, node, cpu, valid)                                (\
        (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) |     \
        (((node)   & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) |     \
 #define IIO_IGFX_INIT(widget, node, cpu, valid)                                (\
        (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) |     \
        (((node)   & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) |     \

-       (((cpu)    & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT) |     \
-       (((valid)  & IIO_IGFX_VLD_MASK)   << IIO_IGFX_VLD_SHIFT)         )
+       (((cpu)    & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT) |     \
+       (((valid)  & IIO_IGFX_VLD_MASK)   << IIO_IGFX_VLD_SHIFT)         )

 
 /* Scratch registers (not all bits available) */
 #define IIO_SCRATCH_REG0       0x400150
 
 /* Scratch registers (not all bits available) */
 #define IIO_SCRATCH_REG0       0x400150

-#define        IIO_SCRATCH_REG1        0x400158
+#define IIO_SCRATCH_REG1       0x400158

 #define IIO_SCRATCH_MASK       0x0000000f00f11fff
 
 #define IIO_SCRATCH_BIT0_0     0x0000000800000000
 #define IIO_SCRATCH_MASK       0x0000000f00f11fff
 
 #define IIO_SCRATCH_BIT0_0     0x0000000800000000


@@ -174,43 +174,43 @@
 typedef union hubii_wid_u {
        u64     wid_reg_value;
        struct {
 typedef union hubii_wid_u {
        u64     wid_reg_value;
        struct {

-               u64     wid_rsvd:       32,     /* unused */
+               u64     wid_rsvd:       32,     /* unused */

                        wid_rev_num:     4,     /* revision number */
                        wid_part_num:   16,     /* the widget type: hub=c101 */
                        wid_mfg_num:    11,     /* Manufacturer id (IBM) */
                        wid_rsvd1:       1;     /* Reserved */
                        wid_rev_num:     4,     /* revision number */
                        wid_part_num:   16,     /* the widget type: hub=c101 */
                        wid_mfg_num:    11,     /* Manufacturer id (IBM) */
                        wid_rsvd1:       1;     /* Reserved */

-        } wid_fields_s;
+       } wid_fields_s;

 } hubii_wid_t;
 
 
 typedef union hubii_wcr_u {
        u64     wcr_reg_value;
        struct {
 } hubii_wid_t;
 
 
 typedef union hubii_wcr_u {
        u64     wcr_reg_value;
        struct {

-               u64     wcr_rsvd:       41,     /* unused */
+               u64     wcr_rsvd:       41,     /* unused */

                        wcr_e_thresh:    5,     /* elasticity threshold */
                        wcr_dir_con:     1,     /* widget direct connect */
                        wcr_f_bad_pkt:   1,     /* Force bad llp pkt enable */
                        wcr_xbar_crd:    3,     /* LLP crossbar credit */
                        wcr_rsvd1:       8,     /* Reserved */
                        wcr_e_thresh:    5,     /* elasticity threshold */
                        wcr_dir_con:     1,     /* widget direct connect */
                        wcr_f_bad_pkt:   1,     /* Force bad llp pkt enable */
                        wcr_xbar_crd:    3,     /* LLP crossbar credit */
                        wcr_rsvd1:       8,     /* Reserved */

-                       wcr_tag_mode:    1,     /* Tag mode */
+                       wcr_tag_mode:    1,     /* Tag mode */

                        wcr_widget_id:   4;     /* LLP crossbar credit */
                        wcr_widget_id:   4;     /* LLP crossbar credit */

-        } wcr_fields_s;
+       } wcr_fields_s;

 } hubii_wcr_t;
 
 } hubii_wcr_t;
 

-#define        iwcr_dir_con    wcr_fields_s.wcr_dir_con
+#define iwcr_dir_con   wcr_fields_s.wcr_dir_con

 
 typedef union hubii_wstat_u {
 
 typedef union hubii_wstat_u {

-       u64      reg_value;
+       u64      reg_value;

        struct {
                u64     rsvd1:          31,
                        crazy:           1,     /* Crazy bit            */
                        rsvd2:           8,
        struct {
                u64     rsvd1:          31,
                        crazy:           1,     /* Crazy bit            */
                        rsvd2:           8,

-                       llp_tx_cnt:      8,     /* LLP Xmit retry counter */
+                       llp_tx_cnt:      8,     /* LLP Xmit retry counter */

                        rsvd3:           6,
                        tx_max_rtry:     1,     /* LLP Retry Timeout Signal */
                        rsvd4:           2,
                        xt_tail_to:      1,     /* Xtalk Tail Timeout   */
                        rsvd3:           6,
                        tx_max_rtry:     1,     /* LLP Retry Timeout Signal */
                        rsvd4:           2,
                        xt_tail_to:      1,     /* Xtalk Tail Timeout   */

-                       xt_crd_to:       1,     /* Xtalk Credit Timeout */
+                       xt_crd_to:       1,     /* Xtalk Credit Timeout */

                        pending:         4;     /* Pending Requests     */
        } wstat_fields_s;
 } hubii_wstat_t;
                        pending:         4;     /* Pending Requests     */
        } wstat_fields_s;
 } hubii_wstat_t;


@@ -219,50 +219,50 @@ typedef union hubii_wstat_u {
 typedef union hubii_ilcsr_u {
        u64     icsr_reg_value;
        struct {
 typedef union hubii_ilcsr_u {
        u64     icsr_reg_value;
        struct {

-               u64     icsr_rsvd:      22,     /* unused */
-                       icsr_max_burst: 10,     /* max burst */
-                        icsr_rsvd4:     6,     /* reserved */
-                       icsr_max_retry: 10,     /* max retry */
-                        icsr_rsvd3:     2,     /* reserved */
-                        icsr_lnk_stat:  2,     /* link status */
-                        icsr_bm8:       1,     /* Bit mode 8 */
-                        icsr_llp_en:    1,     /* LLP enable bit */
-                       icsr_rsvd2:      1,     /* reserver */
-                        icsr_wrm_reset:         1,     /* Warm reset bit */
+               u64     icsr_rsvd:      22,     /* unused */
+                       icsr_max_burst: 10,     /* max burst */
+                       icsr_rsvd4:      6,     /* reserved */
+                       icsr_max_retry: 10,     /* max retry */
+                       icsr_rsvd3:      2,     /* reserved */
+                       icsr_lnk_stat:   2,     /* link status */
+                       icsr_bm8:        1,     /* Bit mode 8 */
+                       icsr_llp_en:     1,     /* LLP enable bit */
+                       icsr_rsvd2:      1,     /* reserver */
+                       icsr_wrm_reset:  1,     /* Warm reset bit */

                        icsr_rsvd1:      2,     /* Data ready offset */
                        icsr_rsvd1:      2,     /* Data ready offset */

-                        icsr_null_to:   6;     /* Null timeout   */
+                       icsr_null_to:    6;     /* Null timeout   */

 
 

-        } icsr_fields_s;
+       } icsr_fields_s;

 } hubii_ilcsr_t;
 
 
 typedef union hubii_iowa_u {
        u64     iowa_reg_value;
        struct {
 } hubii_ilcsr_t;
 
 
 typedef union hubii_iowa_u {
        u64     iowa_reg_value;
        struct {

-               u64     iowa_rsvd:      48,     /* unused */
+               u64     iowa_rsvd:      48,     /* unused */

                        iowa_wxoac:      8,     /* xtalk widget access bits */
                        iowa_rsvd1:      7,     /* xtalk widget access bits */
                        iowa_w0oac:      1;     /* xtalk widget access bits */
                        iowa_wxoac:      8,     /* xtalk widget access bits */
                        iowa_rsvd1:      7,     /* xtalk widget access bits */
                        iowa_w0oac:      1;     /* xtalk widget access bits */

-        } iowa_fields_s;
+       } iowa_fields_s;

 } hubii_iowa_t;
 
 typedef union hubii_iiwa_u {
        u64     iiwa_reg_value;
        struct {
 } hubii_iowa_t;
 
 typedef union hubii_iiwa_u {
        u64     iiwa_reg_value;
        struct {

-               u64     iiwa_rsvd:      48,     /* unused */
+               u64     iiwa_rsvd:      48,     /* unused */

                        iiwa_wxiac:      8,     /* hub wid access bits */
                        iiwa_rsvd1:      7,     /* reserved */
                        iiwa_w0iac:      1;     /* hub wid0 access */
                        iiwa_wxiac:      8,     /* hub wid access bits */
                        iiwa_rsvd1:      7,     /* reserved */
                        iiwa_w0iac:      1;     /* hub wid0 access */

-        } iiwa_fields_s;
+       } iiwa_fields_s;

 } hubii_iiwa_t;
 
 typedef union  hubii_illr_u {
        u64     illr_reg_value;
        struct {
 } hubii_iiwa_t;
 
 typedef union  hubii_illr_u {
        u64     illr_reg_value;
        struct {

-               u64     illr_rsvd:      32,     /* unused */
+               u64     illr_rsvd:      32,     /* unused */

                        illr_cb_cnt:    16,     /* checkbit error count */
                        illr_sn_cnt:    16;     /* sequence number count */
                        illr_cb_cnt:    16,     /* checkbit error count */
                        illr_sn_cnt:    16;     /* sequence number count */

-        } illr_fields_s;
+       } illr_fields_s;

 } hubii_illr_t;
 
 /* The structures below are defined to extract and modify the ii
 } hubii_illr_t;
 
 /* The structures below are defined to extract and modify the ii


@@ -273,7 +273,7 @@ performance registers */
 typedef union io_perf_sel {
        u64 perf_sel_reg;
        struct {
 typedef union io_perf_sel {
        u64 perf_sel_reg;
        struct {

-               u64     perf_rsvd  : 48,
+               u64     perf_rsvd  : 48,

                        perf_icct  :  8,
                        perf_ippr1 :  4,
                        perf_ippr0 :  4;
                        perf_icct  :  8,
                        perf_ippr1 :  4,
                        perf_ippr0 :  4;


@@ -301,7 +301,7 @@ typedef union io_perf_cnt {
 #define IIO_LLP_SN_MAX 0xffff
 
 /* IO PRB Entries */
 #define IIO_LLP_SN_MAX 0xffff
 
 /* IO PRB Entries */

-#define        IIO_NUM_IPRBS   (9)
+#define IIO_NUM_IPRBS  (9)

 #define IIO_IOPRB_0    0x400198        /* PRB entry 0 */
 #define IIO_IOPRB_8    0x4001a0        /* PRB entry 8 */
 #define IIO_IOPRB_9    0x4001a8        /* PRB entry 9 */
 #define IIO_IOPRB_0    0x400198        /* PRB entry 0 */
 #define IIO_IOPRB_8    0x4001a0        /* PRB entry 8 */
 #define IIO_IOPRB_9    0x4001a8        /* PRB entry 9 */


@@ -318,21 +318,21 @@ typedef union io_perf_cnt {
 #define IIO_IMEM       0x4001e8        /* Miscellaneous Enable Mask */
 #define IIO_IXTT       0x4001f0        /* Crosstalk tail timeout */
 #define IIO_IECLR      0x4001f8        /* IO error clear */
 #define IIO_IMEM       0x4001e8        /* Miscellaneous Enable Mask */
 #define IIO_IXTT       0x4001f0        /* Crosstalk tail timeout */
 #define IIO_IECLR      0x4001f8        /* IO error clear */

-#define IIO_IBCN        0x400200        /* IO BTE CRB count */
+#define IIO_IBCN       0x400200        /* IO BTE CRB count */

 
 /*
  * IIO_IMEM Register fields.
  */
 
 /*
  * IIO_IMEM Register fields.
  */

-#define IIO_IMEM_W0ESD  0x1             /* Widget 0 shut down due to error */
-#define IIO_IMEM_B0ESD  (1 << 4)        /* BTE 0 shut down due to error */
-#define IIO_IMEM_B1ESD  (1 << 8)        /* BTE 1 Shut down due to error */
+#define IIO_IMEM_W0ESD 0x1             /* Widget 0 shut down due to error */
+#define IIO_IMEM_B0ESD (1 << 4)        /* BTE 0 shut down due to error */
+#define IIO_IMEM_B1ESD (1 << 8)        /* BTE 1 Shut down due to error */

 
 /* PIO Read address Table Entries */
 #define IIO_IPCA       0x400300        /* PRB Counter adjust */
 #define IIO_NUM_PRTES  8               /* Total number of PRB table entries */
 #define IIO_PRTE_0     0x400308        /* PIO Read address table entry 0 */
 #define IIO_PRTE(_x)   (IIO_PRTE_0 + (8 * (_x)))
 
 /* PIO Read address Table Entries */
 #define IIO_IPCA       0x400300        /* PRB Counter adjust */
 #define IIO_NUM_PRTES  8               /* Total number of PRB table entries */
 #define IIO_PRTE_0     0x400308        /* PIO Read address table entry 0 */
 #define IIO_PRTE(_x)   (IIO_PRTE_0 + (8 * (_x)))

-#define        IIO_WIDPRTE(x)  IIO_PRTE(((x) - 8)) /* widget ID to its PRTE num */
+#define IIO_WIDPRTE(x) IIO_PRTE(((x) - 8)) /* widget ID to its PRTE num */

 #define IIO_IPDR       0x400388        /* PIO table entry deallocation */
 #define IIO_ICDR       0x400390        /* CRB Entry Deallocation */
 #define IIO_IFDR       0x400398        /* IOQ FIFO Depth */
 #define IIO_IPDR       0x400388        /* PIO table entry deallocation */
 #define IIO_ICDR       0x400390        /* CRB Entry Deallocation */
 #define IIO_IFDR       0x400398        /* IOQ FIFO Depth */


@@ -369,35 +369,35 @@ typedef union io_perf_cnt {
 /*
  * IIO PIO Deallocation register field masks : (IIO_IPDR)
  */
 /*
  * IIO PIO Deallocation register field masks : (IIO_IPDR)
  */

-#define        IIO_IPDR_PND    (1 << 4)
+#define IIO_IPDR_PND   (1 << 4)

 
 /*
  * IIO CRB deallocation register field masks: (IIO_ICDR)
  */
 
 /*
  * IIO CRB deallocation register field masks: (IIO_ICDR)
  */

-#define        IIO_ICDR_PND    (1 << 4)
+#define IIO_ICDR_PND   (1 << 4)

 
 /*
  * IIO CRB control register Fields: IIO_ICCR
  */
 
 /*
  * IIO CRB control register Fields: IIO_ICCR
  */

-#define        IIO_ICCR_PENDING        (0x10000)
-#define        IIO_ICCR_CMD_MASK       (0xFF)
-#define        IIO_ICCR_CMD_SHFT       (7)
-#define        IIO_ICCR_CMD_NOP        (0x0)   /* No Op */
-#define        IIO_ICCR_CMD_WAKE       (0x100) /* Reactivate CRB entry and process */
-#define        IIO_ICCR_CMD_TIMEOUT    (0x200) /* Make CRB timeout & mark invalid */
-#define        IIO_ICCR_CMD_EJECT      (0x400) /* Contents of entry written to memory
+#define IIO_ICCR_PENDING       (0x10000)
+#define IIO_ICCR_CMD_MASK      (0xFF)
+#define IIO_ICCR_CMD_SHFT      (7)
+#define IIO_ICCR_CMD_NOP       (0x0)   /* No Op */
+#define IIO_ICCR_CMD_WAKE      (0x100) /* Reactivate CRB entry and process */
+#define IIO_ICCR_CMD_TIMEOUT   (0x200) /* Make CRB timeout & mark invalid */
+#define IIO_ICCR_CMD_EJECT     (0x400) /* Contents of entry written to memory

                                         * via a WB
                                         */
                                         * via a WB
                                         */

-#define        IIO_ICCR_CMD_FLUSH      (0x800)
+#define IIO_ICCR_CMD_FLUSH     (0x800)

 
 /*
  * CRB manipulation macros
  *     The CRB macros are slightly complicated, since there are up to
 
 /*
  * CRB manipulation macros
  *     The CRB macros are slightly complicated, since there are up to

- *     four registers associated with each CRB entry.
+ *     four registers associated with each CRB entry.

  */
 #define IIO_NUM_CRBS           15      /* Number of CRBs */
  */
 #define IIO_NUM_CRBS           15      /* Number of CRBs */

-#define IIO_NUM_NORMAL_CRBS     12     /* Number of regular CRB entries */
-#define IIO_NUM_PC_CRBS        4       /* Number of partial cache CRBs */
+#define IIO_NUM_NORMAL_CRBS    12      /* Number of regular CRB entries */
+#define IIO_NUM_PC_CRBS                4       /* Number of partial cache CRBs */

 #define IIO_ICRB_OFFSET                8
 #define IIO_ICRB_0             0x400400
 /* XXX - This is now tuneable:
 #define IIO_ICRB_OFFSET                8
 #define IIO_ICRB_0             0x400400
 /* XXX - This is now tuneable:


@@ -405,9 +405,9 @@ typedef union io_perf_cnt {
  */
 
 #define IIO_ICRB_A(_x) (IIO_ICRB_0 + (4 * IIO_ICRB_OFFSET * (_x)))
  */
 
 #define IIO_ICRB_A(_x) (IIO_ICRB_0 + (4 * IIO_ICRB_OFFSET * (_x)))

-#define IIO_ICRB_B(_x)  (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)
+#define IIO_ICRB_B(_x) (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)

 #define IIO_ICRB_C(_x) (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)
 #define IIO_ICRB_C(_x) (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)

-#define IIO_ICRB_D(_x)  (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)
+#define IIO_ICRB_D(_x) (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)

 
 /* XXX - IBUE register coming for Hub 2 */
 
 
 /* XXX - IBUE register coming for Hub 2 */
 


@@ -444,16 +444,16 @@ typedef union io_perf_cnt {
 typedef union icrba_u {
        u64     reg_value;
        struct {
 typedef union icrba_u {
        u64     reg_value;
        struct {

-               u64     resvd:  6,
+               u64     resvd:  6,

                        stall_bte0: 1,  /* Stall BTE 0 */
                        stall_bte1: 1,  /* Stall BTE 1 */
                        error:  1,      /* CRB has an error     */
                        stall_bte0: 1,  /* Stall BTE 0 */
                        stall_bte1: 1,  /* Stall BTE 1 */
                        error:  1,      /* CRB has an error     */

-                       ecode:  3,      /* Error Code           */
+                       ecode:  3,      /* Error Code           */

                        lnetuce: 1,     /* SN0net Uncorrectable error */
                        lnetuce: 1,     /* SN0net Uncorrectable error */

-                       mark:   1,      /* CRB Has been marked  */
+                       mark:   1,      /* CRB Has been marked  */

                        xerr:   1,      /* Error bit set in xtalk header */
                        sidn:   4,      /* SIDN field from xtalk        */
                        xerr:   1,      /* Error bit set in xtalk header */
                        sidn:   4,      /* SIDN field from xtalk        */

-                       tnum:   5,      /* TNUM field in xtalk          */
+                       tnum:   5,      /* TNUM field in xtalk          */

                        addr:   38,     /* Address of request   */
                        valid:  1,      /* Valid status         */
                        iow:    1;      /* IO Write operation   */
                        addr:   38,     /* Address of request   */
                        valid:  1,      /* Valid status         */
                        iow:    1;      /* IO Write operation   */


@@ -467,15 +467,15 @@ typedef union h1_icrba_u {
        u64     reg_value;
 
        struct {
        u64     reg_value;
 
        struct {

-               u64     resvd:  6,
-                       unused: 1,      /* Unused but RW!!      */
+               u64     resvd:  6,
+                       unused: 1,      /* Unused but RW!!      */

                        error:  1,      /* CRB has an error     */
                        error:  1,      /* CRB has an error     */

-                       ecode:  4,      /* Error Code           */
+                       ecode:  4,      /* Error Code           */

                        lnetuce: 1,     /* SN0net Uncorrectable error */
                        lnetuce: 1,     /* SN0net Uncorrectable error */

-                       mark:   1,      /* CRB Has been marked  */
+                       mark:   1,      /* CRB Has been marked  */

                        xerr:   1,      /* Error bit set in xtalk header */
                        sidn:   4,      /* SIDN field from xtalk        */
                        xerr:   1,      /* Error bit set in xtalk header */
                        sidn:   4,      /* SIDN field from xtalk        */

-                       tnum:   5,      /* TNUM field in xtalk          */
+                       tnum:   5,      /* TNUM field in xtalk          */

                        addr:   38,     /* Address of request   */
                        valid:  1,      /* Valid status         */
                        iow:    1;      /* IO Write operation   */
                        addr:   38,     /* Address of request   */
                        valid:  1,      /* Valid status         */
                        iow:    1;      /* IO Write operation   */


@@ -488,21 +488,21 @@ typedef union h1_icrba_u {
 
 #endif /* !__ASSEMBLY__ */
 
 
 #endif /* !__ASSEMBLY__ */
 

-#define        IIO_ICRB_ADDR_SHFT      2       /* Shift to get proper address */
+#define IIO_ICRB_ADDR_SHFT     2       /* Shift to get proper address */

 
 /*
  * values for "ecode" field
  */
 
 /*
  * values for "ecode" field
  */

-#define        IIO_ICRB_ECODE_DERR     0       /* Directory error due to IIO access */
-#define        IIO_ICRB_ECODE_PERR     1       /* Poison error on IO access */
-#define        IIO_ICRB_ECODE_WERR     2       /* Write error by IIO access
+#define IIO_ICRB_ECODE_DERR    0       /* Directory error due to IIO access */
+#define IIO_ICRB_ECODE_PERR    1       /* Poison error on IO access */
+#define IIO_ICRB_ECODE_WERR    2       /* Write error by IIO access

                                         * e.g. WINV to a Read only line.
                                         */
                                         * e.g. WINV to a Read only line.
                                         */

-#define        IIO_ICRB_ECODE_AERR     3       /* Access error caused by IIO access */
-#define        IIO_ICRB_ECODE_PWERR    4       /* Error on partial write       */
-#define        IIO_ICRB_ECODE_PRERR    5       /* Error on partial read        */
-#define        IIO_ICRB_ECODE_TOUT     6       /* CRB timeout before deallocating */
-#define        IIO_ICRB_ECODE_XTERR    7       /* Incoming xtalk pkt had error bit */
+#define IIO_ICRB_ECODE_AERR    3       /* Access error caused by IIO access */
+#define IIO_ICRB_ECODE_PWERR   4       /* Error on partial write       */
+#define IIO_ICRB_ECODE_PRERR   5       /* Error on partial read        */
+#define IIO_ICRB_ECODE_TOUT    6       /* CRB timeout before deallocating */
+#define IIO_ICRB_ECODE_XTERR   7       /* Incoming xtalk pkt had error bit */

 
 
 
 
 
 


@@ -513,10 +513,10 @@ typedef union h1_icrba_u {
 typedef union icrbb_u {
        u64     reg_value;
        struct {
 typedef union icrbb_u {
        u64     reg_value;
        struct {

-           u64 rsvd1:  5,
-               btenum: 1,      /* BTE to which entry belongs to */
-               cohtrans: 1,    /* Coherent transaction */
-               xtsize: 2,      /* Xtalk operation size
+           u64 rsvd1:  5,
+               btenum: 1,      /* BTE to which entry belongs to */
+               cohtrans: 1,    /* Coherent transaction */
+               xtsize: 2,      /* Xtalk operation size

                                 * 0: Double Word
                                 * 1: 32 Bytes.
                                 * 2: 128 Bytes,
                                 * 0: Double Word
                                 * 1: 32 Bytes.
                                 * 2: 128 Bytes,


@@ -526,11 +526,11 @@ typedef union icrbb_u {
                srcinit: 2,     /* Source Initiator:
                                 * See below for field values.
                                 */
                srcinit: 2,     /* Source Initiator:
                                 * See below for field values.
                                 */

-               useold: 1,      /* Use OLD command for processing */
+               useold: 1,      /* Use OLD command for processing */

                imsgtype: 2,    /* Incoming message type
                                 * see below for field values
                                 */
                imsgtype: 2,    /* Incoming message type
                                 * see below for field values
                                 */

-               imsg:   8,      /* Incoming message     */
+               imsg:   8,      /* Incoming message     */

                initator: 3,    /* Initiator of original request
                                 * See below for field values.
                                 */
                initator: 3,    /* Initiator of original request
                                 * See below for field values.
                                 */


@@ -538,12 +538,12 @@ typedef union icrbb_u {
                                 * See below for field values.
                                 */
                rsvd2:  7,
                                 * See below for field values.
                                 */
                rsvd2:  7,

-               ackcnt: 11,     /* Invalidate ack count */
+               ackcnt: 11,     /* Invalidate ack count */

                resp:   1,      /* data response  given to processor */
                resp:   1,      /* data response  given to processor */

-               ack:    1,      /* indicates data ack received  */
+               ack:    1,      /* indicates data ack received  */

                hold:   1,      /* entry is gathering inval acks */
                wb_pend:1,      /* waiting for writeback to complete */
                hold:   1,      /* entry is gathering inval acks */
                wb_pend:1,      /* waiting for writeback to complete */

-               intvn:  1,      /* Intervention */
+               intvn:  1,      /* Intervention */

                stall_ib: 1,    /* Stall Ibuf (from crosstalk) */
                stall_intr: 1;  /* Stall internal interrupts */
        } icrbb_field_s;
                stall_ib: 1,    /* Stall Ibuf (from crosstalk) */
                stall_intr: 1;  /* Stall internal interrupts */
        } icrbb_field_s;


@@ -556,9 +556,9 @@ typedef union h1_icrbb_u {
        u64     reg_value;
        struct {
                u64     rsvd1:  5,
        u64     reg_value;
        struct {
                u64     rsvd1:  5,

-                       btenum: 1,      /* BTE to which entry belongs to */
-                       cohtrans: 1,    /* Coherent transaction */
-                       xtsize: 2,      /* Xtalk operation size
+                       btenum: 1,      /* BTE to which entry belongs to */
+                       cohtrans: 1,    /* Coherent transaction */
+                       xtsize: 2,      /* Xtalk operation size

                                         * 0: Double Word
                                         * 1: 32 Bytes.
                                         * 2: 128 Bytes,
                                         * 0: Double Word
                                         * 1: 32 Bytes.
                                         * 2: 128 Bytes,


@@ -568,99 +568,99 @@ typedef union h1_icrbb_u {
                        srcinit: 2,     /* Source Initiator:
                                         * See below for field values.
                                         */
                        srcinit: 2,     /* Source Initiator:
                                         * See below for field values.
                                         */

-                       useold: 1,      /* Use OLD command for processing */
+                       useold: 1,      /* Use OLD command for processing */

                        imsgtype: 2,    /* Incoming message type
                                         * see below for field values
                                         */
                        imsgtype: 2,    /* Incoming message type
                                         * see below for field values
                                         */

-                       imsg:   8,      /* Incoming message     */
+                       imsg:   8,      /* Incoming message     */

                        initator: 3,    /* Initiator of original request
                                         * See below for field values.
                                         */
                        initator: 3,    /* Initiator of original request
                                         * See below for field values.
                                         */

-                       rsvd2:  1,
+                       rsvd2:  1,

                        pcache: 1,      /* entry belongs to partial cache */
                        reqtype: 5,     /* Identifies type of request
                                         * See below for field values.
                                         */
                        pcache: 1,      /* entry belongs to partial cache */
                        reqtype: 5,     /* Identifies type of request
                                         * See below for field values.
                                         */

-                       stl_ib: 1,      /* stall Ibus coming from xtalk */
+                       stl_ib: 1,      /* stall Ibus coming from xtalk */

                        stl_intr: 1,    /* Stall internal interrupts */
                        stl_intr: 1,    /* Stall internal interrupts */

-                       stl_bte0: 1,    /* Stall BTE 0  */
+                       stl_bte0: 1,    /* Stall BTE 0  */

                        stl_bte1: 1,    /* Stall BTE 1  */
                        stl_bte1: 1,    /* Stall BTE 1  */

-                       intrvn: 1,      /* Req was target of intervention */
-                       ackcnt: 11,     /* Invalidate ack count */
+                       intrvn: 1,      /* Req was target of intervention */
+                       ackcnt: 11,     /* Invalidate ack count */

                        resp:   1,      /* data response  given to processor */
                        resp:   1,      /* data response  given to processor */

-                       ack:    1,      /* indicates data ack received  */
+                       ack:    1,      /* indicates data ack received  */

                        hold:   1,      /* entry is gathering inval acks */
                        wb_pend:1,      /* waiting for writeback to complete */
                        hold:   1,      /* entry is gathering inval acks */
                        wb_pend:1,      /* waiting for writeback to complete */

-                       sleep:  1,      /* xtalk req sleeping till IO-sync */
+                       sleep:  1,      /* xtalk req sleeping till IO-sync */

                        pnd_reply: 1,   /* replies not issed due to IOQ full */
                        pnd_req: 1;     /* reqs not issued due to IOQ full */
        } h1_icrbb_field_s;
 } h1_icrbb_t;
 
 
                        pnd_reply: 1,   /* replies not issed due to IOQ full */
                        pnd_req: 1;     /* reqs not issued due to IOQ full */
        } h1_icrbb_field_s;
 } h1_icrbb_t;
 
 

-#define        b_imsgtype      icrbb_field_s.imsgtype
-#define        b_btenum        icrbb_field_s.btenum
-#define        b_cohtrans      icrbb_field_s.cohtrans
-#define        b_xtsize        icrbb_field_s.xtsize
-#define        b_srcnode       icrbb_field_s.srcnode
-#define        b_srcinit       icrbb_field_s.srcinit
-#define        b_imsgtype      icrbb_field_s.imsgtype
-#define        b_imsg          icrbb_field_s.imsg
-#define        b_initiator     icrbb_field_s.initiator
+#define b_imsgtype     icrbb_field_s.imsgtype
+#define b_btenum       icrbb_field_s.btenum
+#define b_cohtrans     icrbb_field_s.cohtrans
+#define b_xtsize       icrbb_field_s.xtsize
+#define b_srcnode      icrbb_field_s.srcnode
+#define b_srcinit      icrbb_field_s.srcinit
+#define b_imsgtype     icrbb_field_s.imsgtype
+#define b_imsg         icrbb_field_s.imsg
+#define b_initiator    icrbb_field_s.initiator

 
 #endif /* !__ASSEMBLY__ */
 
 /*
  * values for field xtsize
  */
 
 #endif /* !__ASSEMBLY__ */
 
 /*
  * values for field xtsize
  */

-#define        IIO_ICRB_XTSIZE_DW      0       /* Xtalk operation size is 8 bytes  */
-#define        IIO_ICRB_XTSIZE_32      1       /* Xtalk operation size is 32 bytes */
-#define        IIO_ICRB_XTSIZE_128     2       /* Xtalk operation size is 128 bytes */
+#define IIO_ICRB_XTSIZE_DW     0       /* Xtalk operation size is 8 bytes  */
+#define IIO_ICRB_XTSIZE_32     1       /* Xtalk operation size is 32 bytes */
+#define IIO_ICRB_XTSIZE_128    2       /* Xtalk operation size is 128 bytes */

 
 /*
  * values for field srcinit
  */
 
 /*
  * values for field srcinit
  */

-#define        IIO_ICRB_PROC0          0       /* Source of request is Proc 0 */
-#define        IIO_ICRB_PROC1          1       /* Source of request is Proc 1 */
-#define        IIO_ICRB_GB_REQ         2       /* Source is Guaranteed BW request */
-#define        IIO_ICRB_IO_REQ         3       /* Source is Normal IO request  */
+#define IIO_ICRB_PROC0         0       /* Source of request is Proc 0 */
+#define IIO_ICRB_PROC1         1       /* Source of request is Proc 1 */
+#define IIO_ICRB_GB_REQ                2       /* Source is Guaranteed BW request */
+#define IIO_ICRB_IO_REQ                3       /* Source is Normal IO request  */

 
 /*
  * Values for field imsgtype
  */
 
 /*
  * Values for field imsgtype
  */

-#define        IIO_ICRB_IMSGT_XTALK    0       /* Incoming Meessage from Xtalk */
-#define        IIO_ICRB_IMSGT_BTE      1       /* Incoming message from BTE    */
-#define        IIO_ICRB_IMSGT_SN0NET   2       /* Incoming message from SN0 net */
-#define        IIO_ICRB_IMSGT_CRB      3       /* Incoming message from CRB ???  */
+#define IIO_ICRB_IMSGT_XTALK   0       /* Incoming Meessage from Xtalk */
+#define IIO_ICRB_IMSGT_BTE     1       /* Incoming message from BTE    */
+#define IIO_ICRB_IMSGT_SN0NET  2       /* Incoming message from SN0 net */
+#define IIO_ICRB_IMSGT_CRB     3       /* Incoming message from CRB ???  */

 
 /*
  * values for field initiator.
  */
 
 /*
  * values for field initiator.
  */

-#define        IIO_ICRB_INIT_XTALK     0       /* Message originated in xtalk  */
-#define        IIO_ICRB_INIT_BTE0      0x1     /* Message originated in BTE 0  */
-#define        IIO_ICRB_INIT_SN0NET    0x2     /* Message originated in SN0net */
-#define        IIO_ICRB_INIT_CRB       0x3     /* Message originated in CRB ?  */
-#define        IIO_ICRB_INIT_BTE1      0x5     /* MEssage originated in BTE 1  */
+#define IIO_ICRB_INIT_XTALK    0       /* Message originated in xtalk  */
+#define IIO_ICRB_INIT_BTE0     0x1     /* Message originated in BTE 0  */
+#define IIO_ICRB_INIT_SN0NET   0x2     /* Message originated in SN0net */
+#define IIO_ICRB_INIT_CRB      0x3     /* Message originated in CRB ?  */
+#define IIO_ICRB_INIT_BTE1     0x5     /* MEssage originated in BTE 1  */

 
 /*
  * Values for field reqtype.
  */
 /* XXX - Need to fix this for Hub 2 */
 
 /*
  * Values for field reqtype.
  */
 /* XXX - Need to fix this for Hub 2 */

-#define        IIO_ICRB_REQ_DWRD       0       /* Request type double word     */
-#define        IIO_ICRB_REQ_QCLRD      1       /* Request is Qrtr Caceh line Rd */
-#define        IIO_ICRB_REQ_BLKRD      2       /* Request is block read        */
-#define        IIO_ICRB_REQ_RSHU       6       /* Request is BTE block read    */
-#define        IIO_ICRB_REQ_REXU       7       /* request is BTE Excl Read     */
-#define        IIO_ICRB_REQ_RDEX       8       /* Request is Read Exclusive    */
-#define        IIO_ICRB_REQ_WINC       9       /* Request is Write Invalidate  */
-#define        IIO_ICRB_REQ_BWINV      10      /* Request is BTE Winv          */
-#define        IIO_ICRB_REQ_PIORD      11      /* Request is PIO read          */
-#define        IIO_ICRB_REQ_PIOWR      12      /* Request is PIO Write         */
-#define        IIO_ICRB_REQ_PRDM       13      /* Request is Fetch&Op          */
-#define        IIO_ICRB_REQ_PWRM       14      /* Request is Store &Op         */
-#define        IIO_ICRB_REQ_PTPWR      15      /* Request is Peer to peer      */
-#define        IIO_ICRB_REQ_WB         16      /* Request is Write back        */
-#define        IIO_ICRB_REQ_DEX        17      /* Retained DEX Cache line      */
+#define IIO_ICRB_REQ_DWRD      0       /* Request type double word     */
+#define IIO_ICRB_REQ_QCLRD     1       /* Request is Qrtr Caceh line Rd */
+#define IIO_ICRB_REQ_BLKRD     2       /* Request is block read        */
+#define IIO_ICRB_REQ_RSHU      6       /* Request is BTE block read    */
+#define IIO_ICRB_REQ_REXU      7       /* request is BTE Excl Read     */
+#define IIO_ICRB_REQ_RDEX      8       /* Request is Read Exclusive    */
+#define IIO_ICRB_REQ_WINC      9       /* Request is Write Invalidate  */
+#define IIO_ICRB_REQ_BWINV     10      /* Request is BTE Winv          */
+#define IIO_ICRB_REQ_PIORD     11      /* Request is PIO read          */
+#define IIO_ICRB_REQ_PIOWR     12      /* Request is PIO Write         */
+#define IIO_ICRB_REQ_PRDM      13      /* Request is Fetch&Op          */
+#define IIO_ICRB_REQ_PWRM      14      /* Request is Store &Op         */
+#define IIO_ICRB_REQ_PTPWR     15      /* Request is Peer to peer      */
+#define IIO_ICRB_REQ_WB                16      /* Request is Write back        */
+#define IIO_ICRB_REQ_DEX       17      /* Retained DEX Cache line      */

 
 /*
  * Fields in CRB Register C
 
 /*
  * Fields in CRB Register C


@@ -674,8 +674,8 @@ typedef union icrbc_s {
                u64     rsvd:   6,
                        sleep:  1,
                        pricnt: 4,      /* Priority count sent with Read req */
                u64     rsvd:   6,
                        sleep:  1,
                        pricnt: 4,      /* Priority count sent with Read req */

-                       pripsc: 4,      /* Priority Pre scalar  */
-                       bteop:  1,      /* BTE Operation        */
+                       pripsc: 4,      /* Priority Pre scalar  */
+                       bteop:  1,      /* BTE Operation        */

                        push_be: 34,    /* Push address Byte enable
                                         * Holds push addr, if CRB is for BTE
                                         * If CRB belongs to Partial cache,
                        push_be: 34,    /* Push address Byte enable
                                         * Holds push addr, if CRB is for BTE
                                         * If CRB belongs to Partial cache,


@@ -684,20 +684,20 @@ typedef union icrbc_s {
                                         */
                        suppl:  11,     /* Supplemental field   */
                        barrop: 1,      /* Barrier Op bit set in xtalk req */
                                         */
                        suppl:  11,     /* Supplemental field   */
                        barrop: 1,      /* Barrier Op bit set in xtalk req */

-                       doresp: 1,      /* Xtalk req needs a response   */
-                       gbr:    1;      /* GBR bit set in xtalk packet  */
+                       doresp: 1,      /* Xtalk req needs a response   */
+                       gbr:    1;      /* GBR bit set in xtalk packet  */

        } icrbc_field_s;
 } icrbc_t;
 
        } icrbc_field_s;
 } icrbc_t;
 

-#define        c_pricnt        icrbc_field_s.pricnt
-#define        c_pripsc        icrbc_field_s.pripsc
-#define        c_bteop         icrbc_field_s.bteop
-#define        c_bteaddr       icrbc_field_s.push_be   /* push_be field has 2 names */
-#define c_benable      icrbc_field_s.push_be   /* push_be field has 2 names */
-#define        c_suppl         icrbc_field_s.suppl
-#define        c_barrop        icrbc_field_s.barrop
-#define        c_doresp        icrbc_field_s.doresp
-#define        c_gbr   icrbc_field_s.gbr
+#define c_pricnt       icrbc_field_s.pricnt
+#define c_pripsc       icrbc_field_s.pripsc
+#define c_bteop                icrbc_field_s.bteop
+#define c_bteaddr      icrbc_field_s.push_be   /* push_be field has 2 names */
+#define c_benable      icrbc_field_s.push_be   /* push_be field has 2 names */
+#define c_suppl                icrbc_field_s.suppl
+#define c_barrop       icrbc_field_s.barrop
+#define c_doresp       icrbc_field_s.doresp
+#define c_gbr  icrbc_field_s.gbr

 #endif /* !__ASSEMBLY__ */
 
 /*
 #endif /* !__ASSEMBLY__ */
 
 /*


@@ -708,31 +708,31 @@ typedef union icrbc_s {
 typedef union icrbd_s {
        u64     reg_value;
        struct {
 typedef union icrbd_s {
        u64     reg_value;
        struct {

-           u64 rsvd:   38,
+           u64 rsvd:   38,

                toutvld: 1,     /* Timeout in progress for this CRB */
                toutvld: 1,     /* Timeout in progress for this CRB */

-               ctxtvld: 1,     /* Context field below is valid */
+               ctxtvld: 1,     /* Context field below is valid */

                rsvd2:  1,
                rsvd2:  1,

-               context: 15,    /* Bit vector:
+               context: 15,    /* Bit vector:

                                 * Has a bit set for each CRB entry
                                 * which needs to be deallocated
                                 * before this CRB entry is processed.
                                 * Set only for barrier operations.
                                 */
                                 * Has a bit set for each CRB entry
                                 * which needs to be deallocated
                                 * before this CRB entry is processed.
                                 * Set only for barrier operations.
                                 */

-               timeout: 8;     /* Timeout Upper 8 bits */
+               timeout: 8;     /* Timeout Upper 8 bits */

        } icrbd_field_s;
 } icrbd_t;
 
        } icrbd_field_s;
 } icrbd_t;
 

-#define        icrbd_toutvld   icrbd_field_s.toutvld
-#define        icrbd_ctxtvld   icrbd_field_s.ctxtvld
-#define        icrbd_context   icrbd_field_s.context
+#define icrbd_toutvld  icrbd_field_s.toutvld
+#define icrbd_ctxtvld  icrbd_field_s.ctxtvld
+#define icrbd_context  icrbd_field_s.context

 
 
 typedef union hubii_ifdr_u {
        u64     hi_ifdr_value;
        struct {
                u64     ifdr_rsvd:      49,
 
 
 typedef union hubii_ifdr_u {
        u64     hi_ifdr_value;
        struct {
                u64     ifdr_rsvd:      49,

-                       ifdr_maxrp:      7,
-                       ifdr_rsvd1:      1,
+                       ifdr_maxrp:      7,
+                       ifdr_rsvd1:      1,

                        ifdr_maxrq:      7;
        } hi_ifdr_fields;
 } hubii_ifdr_t;
                        ifdr_maxrq:      7;
        } hi_ifdr_fields;
 } hubii_ifdr_t;


@@ -789,26 +789,26 @@ typedef union hubii_ifdr_u {
 typedef union iprte_a {
        u64     entry;
        struct {
 typedef union iprte_a {
        u64     entry;
        struct {

-           u64 rsvd1     : 7,  /* Reserved field               */
-               valid     : 1,  /* Maps to a timeout entry      */
-               rsvd2     : 1,
-               srcnode   : 9,  /* Node which did this PIO      */
-               initiator : 2,  /* If T5A or T5B or IO          */
-               rsvd3     : 3,
-               addr      : 38, /* Physical address of PIO      */
-               rsvd4     : 3;
+           u64 rsvd1     : 7,  /* Reserved field               */
+               valid     : 1,  /* Maps to a timeout entry      */
+               rsvd2     : 1,
+               srcnode   : 9,  /* Node which did this PIO      */
+               initiator : 2,  /* If T5A or T5B or IO          */
+               rsvd3     : 3,
+               addr      : 38, /* Physical address of PIO      */
+               rsvd4     : 3;

        } iprte_fields;
 } iprte_a_t;
 
        } iprte_fields;
 } iprte_a_t;
 

-#define        iprte_valid     iprte_fields.valid
-#define        iprte_timeout   iprte_fields.timeout
-#define        iprte_srcnode   iprte_fields.srcnode
-#define        iprte_init      iprte_fields.initiator
-#define        iprte_addr      iprte_fields.addr
+#define iprte_valid    iprte_fields.valid
+#define iprte_timeout  iprte_fields.timeout
+#define iprte_srcnode  iprte_fields.srcnode
+#define iprte_init     iprte_fields.initiator
+#define iprte_addr     iprte_fields.addr

 
 #endif /* !__ASSEMBLY__ */
 
 
 #endif /* !__ASSEMBLY__ */
 

-#define        IPRTE_ADDRSHFT  3
+#define IPRTE_ADDRSHFT 3

 
 /*
  * Hub IIO PRB Register format.
 
 /*
  * Hub IIO PRB Register format.


@@ -823,14 +823,14 @@ typedef union iprte_a {
 typedef union iprb_u {
        u64     reg_value;
        struct {
 typedef union iprb_u {
        u64     reg_value;
        struct {

-           u64 rsvd1:  15,
+           u64 rsvd1:  15,

                error:  1,      /* Widget rcvd wr resp pkt w/ error */
                error:  1,      /* Widget rcvd wr resp pkt w/ error */

-               ovflow: 5,      /* Overflow count. perf measurement */
+               ovflow: 5,      /* Overflow count. perf measurement */

                fire_and_forget: 1, /* Launch Write without response */
                mode:   2,      /* Widget operation Mode        */
                rsvd2:  2,
                bnakctr: 14,
                fire_and_forget: 1, /* Launch Write without response */
                mode:   2,      /* Widget operation Mode        */
                rsvd2:  2,
                bnakctr: 14,

-               rsvd3:  2,
+               rsvd3:  2,

                anakctr: 14,
                xtalkctr: 8;
        } iprb_fields_s;
                anakctr: 14,
                xtalkctr: 8;
        } iprb_fields_s;


@@ -838,13 +838,13 @@ typedef union iprb_u {
 
 #define iprb_regval    reg_value
 
 
 #define iprb_regval    reg_value
 

-#define        iprb_error      iprb_fields_s.error
-#define        iprb_ovflow     iprb_fields_s.ovflow
-#define        iprb_ff         iprb_fields_s.fire_and_forget
-#define        iprb_mode       iprb_fields_s.mode
-#define        iprb_bnakctr    iprb_fields_s.bnakctr
-#define        iprb_anakctr    iprb_fields_s.anakctr
-#define        iprb_xtalkctr   iprb_fields_s.xtalkctr
+#define iprb_error     iprb_fields_s.error
+#define iprb_ovflow    iprb_fields_s.ovflow
+#define iprb_ff                iprb_fields_s.fire_and_forget
+#define iprb_mode      iprb_fields_s.mode
+#define iprb_bnakctr   iprb_fields_s.bnakctr
+#define iprb_anakctr   iprb_fields_s.anakctr
+#define iprb_xtalkctr  iprb_fields_s.xtalkctr

 
 #endif /* !__ASSEMBLY__ */
 
 
 #endif /* !__ASSEMBLY__ */
 


@@ -853,10 +853,10 @@ typedef union iprb_u {
  * For details of the meanings of NAK and Accept, refer the PIO flow
  * document
  */
  * For details of the meanings of NAK and Accept, refer the PIO flow
  * document
  */

-#define        IPRB_MODE_NORMAL        (0)
-#define        IPRB_MODE_COLLECT_A     (1)     /* PRB in collect A mode */
-#define        IPRB_MODE_SERVICE_A     (2)     /* NAK B and Accept A */
-#define        IPRB_MODE_SERVICE_B     (3)     /* NAK A and Accept B */
+#define IPRB_MODE_NORMAL       (0)
+#define IPRB_MODE_COLLECT_A    (1)     /* PRB in collect A mode */
+#define IPRB_MODE_SERVICE_A    (2)     /* NAK B and Accept A */
+#define IPRB_MODE_SERVICE_B    (3)     /* NAK A and Accept B */

 
 /*
  * IO CRB entry C_A to E_A : Partial (cache) CRBS
 
 /*
  * IO CRB entry C_A to E_A : Partial (cache) CRBS


@@ -865,31 +865,31 @@ typedef union iprb_u {
 typedef union icrbp_a {
        u64   ip_reg;       /* the entire register value        */
        struct {
 typedef union icrbp_a {
        u64   ip_reg;       /* the entire register value        */
        struct {

-            u64 error: 1,  /*    63, error occurred            */
-               ln_uce: 1,  /*    62: uncorrectable memory      */
-               ln_ae:  1,  /*    61: protection violation      */
-               ln_werr:1,  /*    60: write access error        */
-               ln_aerr:1,  /*    59: sn0net: Address error     */
-               ln_perr:1,  /*    58: sn0net: poison error      */
-               timeout:1,  /*    57: CRB timed out             */
-               l_bdpkt:1,  /*    56: truncated pkt on sn0net   */
-               c_bdpkt:1,  /*    55: truncated pkt on xtalk    */
-               c_err:  1,  /*    54: incoming xtalk req, err set*/
+            u64 error: 1,  /*    63, error occurred            */
+               ln_uce: 1,  /*    62: uncorrectable memory      */
+               ln_ae:  1,  /*    61: protection violation      */
+               ln_werr:1,  /*    60: write access error        */
+               ln_aerr:1,  /*    59: sn0net: Address error     */
+               ln_perr:1,  /*    58: sn0net: poison error      */
+               timeout:1,  /*    57: CRB timed out             */
+               l_bdpkt:1,  /*    56: truncated pkt on sn0net   */
+               c_bdpkt:1,  /*    55: truncated pkt on xtalk    */
+               c_err:  1,  /*    54: incoming xtalk req, err set*/

                rsvd1: 12,  /* 53-42: reserved                  */
                rsvd1: 12,  /* 53-42: reserved                  */

-               valid:  1,  /*    41: Valid status              */
+               valid:  1,  /*    41: Valid status              */

                sidn:   4,  /* 40-37: SIDN field of xtalk rqst  */
                tnum:   5,  /* 36-32: TNUM of xtalk request     */
                sidn:   4,  /* 40-37: SIDN field of xtalk rqst  */
                tnum:   5,  /* 36-32: TNUM of xtalk request     */

-               bo:     1,  /*    31: barrier op set in xtalk rqst*/
-               resprqd:1,  /*    30: xtalk rqst requires response*/
-               gbr:    1,  /*    29: gbr bit set in xtalk rqst */
+               bo:     1,  /*    31: barrier op set in xtalk rqst*/
+               resprqd:1,  /*    30: xtalk rqst requires response*/
+               gbr:    1,  /*    29: gbr bit set in xtalk rqst */

                size:   2,  /* 28-27: size of xtalk request     */
                excl:   4,  /* 26-23: exclusive bit(s)          */
                stall:  3,  /* 22-20: stall (xtalk, bte 0/1)    */
                size:   2,  /* 28-27: size of xtalk request     */
                excl:   4,  /* 26-23: exclusive bit(s)          */
                stall:  3,  /* 22-20: stall (xtalk, bte 0/1)    */

-               intvn:  1,  /*    19: rqst target of intervention*/
-               resp:   1,  /*    18: Data response given to t5 */
-               ack:    1,  /*    17: Data ack received.        */
-               hold:   1,  /*    16: crb gathering invalidate acks*/
-               wb:     1,  /*    15: writeback pending.        */
+               intvn:  1,  /*    19: rqst target of intervention*/
+               resp:   1,  /*    18: Data response given to t5 */
+               ack:    1,  /*    17: Data ack received.        */
+               hold:   1,  /*    16: crb gathering invalidate acks*/
+               wb:     1,  /*    15: writeback pending.        */

                ack_cnt:11, /* 14-04: counter of invalidate acks*/
                tscaler:4;  /* 03-00: Timeout prescaler         */
        } ip_fmt;
                ack_cnt:11, /* 14-04: counter of invalidate acks*/
                tscaler:4;  /* 03-00: Timeout prescaler         */
        } ip_fmt;


@@ -908,13 +908,13 @@ typedef union hubii_idsr {
        u64 iin_reg;
        struct {
                u64 rsvd1 : 35,
        u64 iin_reg;
        struct {
                u64 rsvd1 : 35,

-                   isent : 1,
-                   rsvd2 : 3,
-                   ienable: 1,
-                   rsvd  : 7,
-                   node  : 9,
-                   rsvd4 : 1,
-                   level : 7;
+                   isent : 1,
+                   rsvd2 : 3,
+                   ienable: 1,
+                   rsvd  : 7,
+                   node  : 9,
+                   rsvd4 : 1,
+                   level : 7;

        } iin_fmt;
 } hubii_idsr_t;
 #endif /* !__ASSEMBLY__ */
        } iin_fmt;
 } hubii_idsr_t;
 #endif /* !__ASSEMBLY__ */


@@ -966,7 +966,7 @@ typedef union hubii_idsr {
  * Value of 3 is required by Xbow 1.1
  * We may be able to increase this to 4 with Xbow 1.2.
  */
  * Value of 3 is required by Xbow 1.1
  * We may be able to increase this to 4 with Xbow 1.2.
  */

-#define       HUBII_XBOW_CREDIT       3
+#define              HUBII_XBOW_CREDIT       3

 #define              HUBII_XBOW_REV2_CREDIT  4
 
 #endif /* _ASM_SGI_SN_SN0_HUBIO_H */
 #define              HUBII_XBOW_REV2_CREDIT  4
 
 #endif /* _ASM_SGI_SN_SN0_HUBIO_H */

diff --git a/arch/mips/include/asm/sn/sn0/hubmd.h b/arch/mips/include/asm/sn/sn0/hubmd.h
index 14c225d80664b38faeab3aafd81cc847383ffd7f..305d002be182594e2c37f4d5a134ebb47f251a56 100644 (file)
--- a/arch/mips/include/asm/sn/sn0/hubmd.h
+++ b/arch/mips/include/asm/sn/sn0/hubmd.h
@@ -8,16 +8,16 @@
  * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
  * Copyright (C) 1999 by Ralf Baechle
  */
  * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
  * Copyright (C) 1999 by Ralf Baechle
  */

-#ifndef        _ASM_SN_SN0_HUBMD_H
-#define        _ASM_SN_SN0_HUBMD_H
+#ifndef _ASM_SN_SN0_HUBMD_H
+#define _ASM_SN_SN0_HUBMD_H

 
 
 /*
  * Hub Memory/Directory interface registers
  */
 
 
 /*
  * Hub Memory/Directory interface registers
  */

-#define CACHE_SLINE_SIZE        128    /* Secondary cache line size on SN0 */
+#define CACHE_SLINE_SIZE       128     /* Secondary cache line size on SN0 */

 
 

-#define        MAX_REGIONS             64
+#define MAX_REGIONS            64

 
 /* Hardware page size and shift */
 
 
 /* Hardware page size and shift */
 


@@ -34,62 +34,62 @@
 #define MD_IO_PROT_OVRRD       0x200008 /* Clear my bit in MD_IO_PROTECT   */
 #define MD_HSPEC_PROTECT       0x200010 /* BDDIR, LBOOT, RBOOT protection  */
 #define MD_MEMORY_CONFIG       0x200018 /* Memory/Directory DIMM control   */
 #define MD_IO_PROT_OVRRD       0x200008 /* Clear my bit in MD_IO_PROTECT   */
 #define MD_HSPEC_PROTECT       0x200010 /* BDDIR, LBOOT, RBOOT protection  */
 #define MD_MEMORY_CONFIG       0x200018 /* Memory/Directory DIMM control   */

-#define        MD_REFRESH_CONTROL      0x200020 /* Memory/Directory refresh ctrl   */
-#define        MD_FANDOP_CAC_STAT      0x200028 /* Fetch-and-op cache status       */
-#define        MD_MIG_DIFF_THRESH      0x200030 /* Page migr. count diff thresh.   */
-#define        MD_MIG_VALUE_THRESH     0x200038 /* Page migr. count abs. thresh.   */
-#define        MD_MIG_CANDIDATE        0x200040 /* Latest page migration candidate */
-#define        MD_MIG_CANDIDATE_CLR    0x200048 /* Clear page migration candidate  */
-#define MD_DIR_ERROR           0x200050 /* Directory DIMM error            */
-#define MD_DIR_ERROR_CLR       0x200058 /* Directory DIMM error clear      */
-#define MD_PROTOCOL_ERROR      0x200060 /* Directory protocol error        */
+#define MD_REFRESH_CONTROL     0x200020 /* Memory/Directory refresh ctrl   */
+#define MD_FANDOP_CAC_STAT     0x200028 /* Fetch-and-op cache status       */
+#define MD_MIG_DIFF_THRESH     0x200030 /* Page migr. count diff thresh.   */
+#define MD_MIG_VALUE_THRESH    0x200038 /* Page migr. count abs. thresh.   */
+#define MD_MIG_CANDIDATE       0x200040 /* Latest page migration candidate */
+#define MD_MIG_CANDIDATE_CLR   0x200048 /* Clear page migration candidate  */
+#define MD_DIR_ERROR           0x200050 /* Directory DIMM error            */
+#define MD_DIR_ERROR_CLR       0x200058 /* Directory DIMM error clear      */
+#define MD_PROTOCOL_ERROR      0x200060 /* Directory protocol error        */

 #define MD_PROTOCOL_ERROR_CLR  0x200068 /* Directory protocol error clear  */
 #define MD_PROTOCOL_ERROR_CLR  0x200068 /* Directory protocol error clear  */

-#define MD_MEM_ERROR           0x200070 /* Memory DIMM error               */
-#define MD_MEM_ERROR_CLR       0x200078 /* Memory DIMM error clear         */
-#define MD_MISC_ERROR          0x200080 /* Miscellaneous MD error          */
+#define MD_MEM_ERROR           0x200070 /* Memory DIMM error               */
+#define MD_MEM_ERROR_CLR       0x200078 /* Memory DIMM error clear         */
+#define MD_MISC_ERROR          0x200080 /* Miscellaneous MD error          */

 #define MD_MISC_ERROR_CLR      0x200088 /* Miscellaneous MD error clear    */
 #define MD_MEM_DIMM_INIT       0x200090 /* Memory DIMM mode initization.   */
 #define MD_MISC_ERROR_CLR      0x200088 /* Miscellaneous MD error clear    */
 #define MD_MEM_DIMM_INIT       0x200090 /* Memory DIMM mode initization.   */

-#define MD_DIR_DIMM_INIT       0x200098 /* Directory DIMM mode init.       */
-#define MD_MOQ_SIZE            0x2000a0 /* MD outgoing queue size          */
+#define MD_DIR_DIMM_INIT       0x200098 /* Directory DIMM mode init.       */
+#define MD_MOQ_SIZE            0x2000a0 /* MD outgoing queue size          */

 #define MD_MLAN_CTL            0x2000a8 /* NIC (Microlan) control register */
 
 #define MD_MLAN_CTL            0x2000a8 /* NIC (Microlan) control register */
 

-#define MD_PERF_SEL            0x210000 /* Select perf monitor events      */
-#define MD_PERF_CNT0           0x210010 /* Performance counter 0           */
-#define MD_PERF_CNT1           0x210018 /* Performance counter 1           */
-#define MD_PERF_CNT2           0x210020 /* Performance counter 2           */
-#define MD_PERF_CNT3           0x210028 /* Performance counter 3           */
-#define MD_PERF_CNT4           0x210030 /* Performance counter 4           */
-#define MD_PERF_CNT5           0x210038 /* Performance counter 5           */
-
-#define MD_UREG0_0             0x220000 /* uController/UART 0 register     */
-#define MD_UREG0_1             0x220008 /* uController/UART 0 register     */
-#define MD_UREG0_2             0x220010 /* uController/UART 0 register     */
-#define MD_UREG0_3             0x220018 /* uController/UART 0 register     */
-#define MD_UREG0_4             0x220020 /* uController/UART 0 register     */
-#define MD_UREG0_5             0x220028 /* uController/UART 0 register     */
-#define MD_UREG0_6             0x220030 /* uController/UART 0 register     */
-#define MD_UREG0_7             0x220038 /* uController/UART 0 register     */
+#define MD_PERF_SEL            0x210000 /* Select perf monitor events      */
+#define MD_PERF_CNT0           0x210010 /* Performance counter 0           */
+#define MD_PERF_CNT1           0x210018 /* Performance counter 1           */
+#define MD_PERF_CNT2           0x210020 /* Performance counter 2           */
+#define MD_PERF_CNT3           0x210028 /* Performance counter 3           */
+#define MD_PERF_CNT4           0x210030 /* Performance counter 4           */
+#define MD_PERF_CNT5           0x210038 /* Performance counter 5           */
+
+#define MD_UREG0_0             0x220000 /* uController/UART 0 register     */
+#define MD_UREG0_1             0x220008 /* uController/UART 0 register     */
+#define MD_UREG0_2             0x220010 /* uController/UART 0 register     */
+#define MD_UREG0_3             0x220018 /* uController/UART 0 register     */
+#define MD_UREG0_4             0x220020 /* uController/UART 0 register     */
+#define MD_UREG0_5             0x220028 /* uController/UART 0 register     */
+#define MD_UREG0_6             0x220030 /* uController/UART 0 register     */
+#define MD_UREG0_7             0x220038 /* uController/UART 0 register     */

 
 #define MD_SLOTID_USTAT                0x220048 /* Hub slot ID & UART/uCtlr status */
 
 #define MD_SLOTID_USTAT                0x220048 /* Hub slot ID & UART/uCtlr status */

-#define MD_LED0                        0x220050 /* Eight-bit LED for CPU A         */
-#define MD_LED1                        0x220058 /* Eight-bit LED for CPU B         */
-
-#define MD_UREG1_0             0x220080 /* uController/UART 1 register     */
-#define MD_UREG1_1             0x220088 /* uController/UART 1 register     */
-#define MD_UREG1_2             0x220090 /* uController/UART 1 register     */
-#define MD_UREG1_3             0x220098 /* uController/UART 1 register     */
-#define MD_UREG1_4             0x2200a0 /* uController/UART 1 register     */
-#define MD_UREG1_5             0x2200a8 /* uController/UART 1 register     */
-#define MD_UREG1_6             0x2200b0 /* uController/UART 1 register     */
-#define MD_UREG1_7             0x2200b8 /* uController/UART 1 register     */
-#define MD_UREG1_8             0x2200c0 /* uController/UART 1 register     */
-#define MD_UREG1_9             0x2200c8 /* uController/UART 1 register     */
-#define MD_UREG1_10            0x2200d0 /* uController/UART 1 register     */
-#define MD_UREG1_11            0x2200d8 /* uController/UART 1 register     */
-#define MD_UREG1_12            0x2200e0 /* uController/UART 1 register     */
-#define MD_UREG1_13            0x2200e8 /* uController/UART 1 register     */
-#define MD_UREG1_14            0x2200f0 /* uController/UART 1 register     */
-#define MD_UREG1_15            0x2200f8 /* uController/UART 1 register     */
+#define MD_LED0                        0x220050 /* Eight-bit LED for CPU A         */
+#define MD_LED1                        0x220058 /* Eight-bit LED for CPU B         */
+
+#define MD_UREG1_0             0x220080 /* uController/UART 1 register     */
+#define MD_UREG1_1             0x220088 /* uController/UART 1 register     */
+#define MD_UREG1_2             0x220090 /* uController/UART 1 register     */
+#define MD_UREG1_3             0x220098 /* uController/UART 1 register     */
+#define MD_UREG1_4             0x2200a0 /* uController/UART 1 register     */
+#define MD_UREG1_5             0x2200a8 /* uController/UART 1 register     */
+#define MD_UREG1_6             0x2200b0 /* uController/UART 1 register     */
+#define MD_UREG1_7             0x2200b8 /* uController/UART 1 register     */
+#define MD_UREG1_8             0x2200c0 /* uController/UART 1 register     */
+#define MD_UREG1_9             0x2200c8 /* uController/UART 1 register     */
+#define MD_UREG1_10            0x2200d0 /* uController/UART 1 register     */
+#define MD_UREG1_11            0x2200d8 /* uController/UART 1 register     */
+#define MD_UREG1_12            0x2200e0 /* uController/UART 1 register     */
+#define MD_UREG1_13            0x2200e8 /* uController/UART 1 register     */
+#define MD_UREG1_14            0x2200f0 /* uController/UART 1 register     */
+#define MD_UREG1_15            0x2200f8 /* uController/UART 1 register     */

 
 #ifdef CONFIG_SGI_SN_N_MODE
 #define MD_MEM_BANKS           4        /* 4 banks of memory max in N mode */
 
 #ifdef CONFIG_SGI_SN_N_MODE
 #define MD_MEM_BANKS           4        /* 4 banks of memory max in N mode */


@@ -106,14 +106,14 @@
  *   Bits not used by the MD are used by software.
  */
 
  *   Bits not used by the MD are used by software.
  */
 

-#define MD_SIZE_EMPTY          0       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_EMPTY          0       /* Valid in MEMORY_CONFIG           */

 #define MD_SIZE_8MB            1
 #define MD_SIZE_16MB           2
 #define MD_SIZE_32MB           3       /* Broken in Hub 1                  */
 #define MD_SIZE_8MB            1
 #define MD_SIZE_16MB           2
 #define MD_SIZE_32MB           3       /* Broken in Hub 1                  */

-#define MD_SIZE_64MB           4       /* Valid in MEMORY_CONFIG           */
-#define MD_SIZE_128MB          5       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_64MB           4       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_128MB          5       /* Valid in MEMORY_CONFIG           */

 #define MD_SIZE_256MB          6
 #define MD_SIZE_256MB          6

-#define MD_SIZE_512MB          7       /* Valid in MEMORY_CONFIG           */
+#define MD_SIZE_512MB          7       /* Valid in MEMORY_CONFIG           */

 #define MD_SIZE_1GB            8
 #define MD_SIZE_2GB            9
 #define MD_SIZE_4GB            10
 #define MD_SIZE_1GB            8
 #define MD_SIZE_2GB            9
 #define MD_SIZE_4GB            10


@@ -207,16 +207,16 @@
 
 /* MD_SLOTID_USTAT bit definitions */
 
 
 /* MD_SLOTID_USTAT bit definitions */
 

-#define MSU_CORECLK_TST_SHFT   7       /* You don't wanna know             */
+#define MSU_CORECLK_TST_SHFT   7       /* You don't wanna know             */

 #define MSU_CORECLK_TST_MASK   (UINT64_CAST 1 << 7)
 #define MSU_CORECLK_TST                (UINT64_CAST 1 << 7)
 #define MSU_CORECLK_TST_MASK   (UINT64_CAST 1 << 7)
 #define MSU_CORECLK_TST                (UINT64_CAST 1 << 7)

-#define MSU_CORECLK_SHFT       6       /* You don't wanna know             */
+#define MSU_CORECLK_SHFT       6       /* You don't wanna know             */

 #define MSU_CORECLK_MASK       (UINT64_CAST 1 << 6)
 #define MSU_CORECLK            (UINT64_CAST 1 << 6)
 #define MSU_CORECLK_MASK       (UINT64_CAST 1 << 6)
 #define MSU_CORECLK            (UINT64_CAST 1 << 6)

-#define MSU_NETSYNC_SHFT       5       /* You don't wanna know             */
+#define MSU_NETSYNC_SHFT       5       /* You don't wanna know             */

 #define MSU_NETSYNC_MASK       (UINT64_CAST 1 << 5)
 #define MSU_NETSYNC            (UINT64_CAST 1 << 5)
 #define MSU_NETSYNC_MASK       (UINT64_CAST 1 << 5)
 #define MSU_NETSYNC            (UINT64_CAST 1 << 5)

-#define MSU_FPROMRDY_SHFT      4       /* Flash PROM ready bit             */
+#define MSU_FPROMRDY_SHFT      4       /* Flash PROM ready bit             */

 #define MSU_FPROMRDY_MASK      (UINT64_CAST 1 << 4)
 #define MSU_FPROMRDY           (UINT64_CAST 1 << 4)
 #define MSU_I2CINTR_SHFT               3       /* I2C interrupt bit   */
 #define MSU_FPROMRDY_MASK      (UINT64_CAST 1 << 4)
 #define MSU_FPROMRDY           (UINT64_CAST 1 << 4)
 #define MSU_I2CINTR_SHFT               3       /* I2C interrupt bit   */


@@ -228,8 +228,8 @@
 #define MSU_SN00_SLOTID_SHFT   7
 #define MSU_SN00_SLOTID_MASK   (UINT64_CAST 0x80)
 
 #define MSU_SN00_SLOTID_SHFT   7
 #define MSU_SN00_SLOTID_MASK   (UINT64_CAST 0x80)
 

-#define        MSU_PIMM_PSC_SHFT       4
-#define        MSU_PIMM_PSC_MASK       (0xf << MSU_PIMM_PSC_SHFT)
+#define MSU_PIMM_PSC_SHFT      4
+#define MSU_PIMM_PSC_MASK      (0xf << MSU_PIMM_PSC_SHFT)

 
 /* MD_MIG_DIFF_THRESH bit definitions */
 
 
 /* MD_MIG_DIFF_THRESH bit definitions */
 


@@ -260,7 +260,7 @@
 
 /* Other MD definitions */
 
 
 /* Other MD definitions */
 

-#define MD_BANK_SHFT           29                      /* log2(512 MB)     */
+#define MD_BANK_SHFT           29                      /* log2(512 MB)     */

 #define MD_BANK_MASK           (UINT64_CAST 7 << 29)
 #define MD_BANK_SIZE           (UINT64_CAST 1 << MD_BANK_SHFT)   /* 512 MB */
 #define MD_BANK_OFFSET(_b)     (UINT64_CAST (_b) << MD_BANK_SHFT)
 #define MD_BANK_MASK           (UINT64_CAST 7 << 29)
 #define MD_BANK_SIZE           (UINT64_CAST 1 << MD_BANK_SHFT)   /* 512 MB */
 #define MD_BANK_OFFSET(_b)     (UINT64_CAST (_b) << MD_BANK_SHFT)


@@ -300,32 +300,32 @@
  * Format C:  STATE != shared (FINE must be 0)
  */
 
  * Format C:  STATE != shared (FINE must be 0)
  */
 

-#define MD_PDIR_MASK           0xffffffffffff          /* Whole entry      */
+#define MD_PDIR_MASK           0xffffffffffff          /* Whole entry      */

 #define MD_PDIR_ECC_SHFT       0                       /* ABC low or high  */
 #define MD_PDIR_ECC_MASK       0x7f
 #define MD_PDIR_ECC_SHFT       0                       /* ABC low or high  */
 #define MD_PDIR_ECC_MASK       0x7f

-#define MD_PDIR_PRIO_SHFT      8                       /* ABC low          */
+#define MD_PDIR_PRIO_SHFT      8                       /* ABC low          */

 #define MD_PDIR_PRIO_MASK      (0xf << 8)
 #define MD_PDIR_PRIO_MASK      (0xf << 8)

-#define MD_PDIR_AX_SHFT                7                       /* ABC low          */
+#define MD_PDIR_AX_SHFT                7                       /* ABC low          */

 #define MD_PDIR_AX_MASK                (1 << 7)
 #define MD_PDIR_AX             (1 << 7)
 #define MD_PDIR_AX_MASK                (1 << 7)
 #define MD_PDIR_AX             (1 << 7)

-#define MD_PDIR_FINE_SHFT      12                      /* ABC low          */
+#define MD_PDIR_FINE_SHFT      12                      /* ABC low          */

 #define MD_PDIR_FINE_MASK      (1 << 12)
 #define MD_PDIR_FINE           (1 << 12)
 #define MD_PDIR_FINE_MASK      (1 << 12)
 #define MD_PDIR_FINE           (1 << 12)

-#define MD_PDIR_OCT_SHFT       13                      /* A low            */
+#define MD_PDIR_OCT_SHFT       13                      /* A low            */

 #define MD_PDIR_OCT_MASK       (7 << 13)
 #define MD_PDIR_OCT_MASK       (7 << 13)

-#define MD_PDIR_STATE_SHFT     13                      /* BC low           */
+#define MD_PDIR_STATE_SHFT     13                      /* BC low           */

 #define MD_PDIR_STATE_MASK     (7 << 13)
 #define MD_PDIR_STATE_MASK     (7 << 13)

-#define MD_PDIR_ONECNT_SHFT    16                      /* BC low           */
+#define MD_PDIR_ONECNT_SHFT    16                      /* BC low           */

 #define MD_PDIR_ONECNT_MASK    (0x3f << 16)
 #define MD_PDIR_ONECNT_MASK    (0x3f << 16)

-#define MD_PDIR_PTR_SHFT       22                      /* C low            */
+#define MD_PDIR_PTR_SHFT       22                      /* C low            */

 #define MD_PDIR_PTR_MASK       (UINT64_CAST 0x7ff << 22)
 #define MD_PDIR_PTR_MASK       (UINT64_CAST 0x7ff << 22)

-#define MD_PDIR_VECMSB_SHFT    22                      /* AB low           */
+#define MD_PDIR_VECMSB_SHFT    22                      /* AB low           */

 #define MD_PDIR_VECMSB_BITMASK 0x3ffffff
 #define MD_PDIR_VECMSB_BITSHFT 27
 #define MD_PDIR_VECMSB_MASK    (UINT64_CAST MD_PDIR_VECMSB_BITMASK << 22)
 #define MD_PDIR_VECMSB_BITMASK 0x3ffffff
 #define MD_PDIR_VECMSB_BITSHFT 27
 #define MD_PDIR_VECMSB_MASK    (UINT64_CAST MD_PDIR_VECMSB_BITMASK << 22)

-#define MD_PDIR_CWOFF_SHFT     7                       /* C high           */
+#define MD_PDIR_CWOFF_SHFT     7                       /* C high           */

 #define MD_PDIR_CWOFF_MASK     (7 << 7)
 #define MD_PDIR_CWOFF_MASK     (7 << 7)

-#define MD_PDIR_VECLSB_SHFT    10                      /* AB high          */
+#define MD_PDIR_VECLSB_SHFT    10                      /* AB high          */

 #define MD_PDIR_VECLSB_BITMASK (UINT64_CAST 0x3fffffffff)
 #define MD_PDIR_VECLSB_BITSHFT 0
 #define MD_PDIR_VECLSB_MASK    (MD_PDIR_VECLSB_BITMASK << 10)
 #define MD_PDIR_VECLSB_BITMASK (UINT64_CAST 0x3fffffffff)
 #define MD_PDIR_VECLSB_BITSHFT 0
 #define MD_PDIR_VECLSB_MASK    (MD_PDIR_VECLSB_BITMASK << 10)


@@ -349,25 +349,25 @@
  * Format C:  STATE != shared
  */
 
  * Format C:  STATE != shared
  */
 

-#define MD_SDIR_MASK           0xffff                  /* Whole entry      */
+#define MD_SDIR_MASK           0xffff                  /* Whole entry      */

 #define MD_SDIR_ECC_SHFT       0                       /* AC low or high   */
 #define MD_SDIR_ECC_MASK       0x1f
 #define MD_SDIR_ECC_SHFT       0                       /* AC low or high   */
 #define MD_SDIR_ECC_MASK       0x1f

-#define MD_SDIR_PRIO_SHFT      6                       /* AC low           */
+#define MD_SDIR_PRIO_SHFT      6                       /* AC low           */

 #define MD_SDIR_PRIO_MASK      (1 << 6)
 #define MD_SDIR_PRIO_MASK      (1 << 6)

-#define MD_SDIR_AX_SHFT                5                       /* AC low           */
+#define MD_SDIR_AX_SHFT                5                       /* AC low           */

 #define MD_SDIR_AX_MASK                (1 << 5)
 #define MD_SDIR_AX             (1 << 5)
 #define MD_SDIR_AX_MASK                (1 << 5)
 #define MD_SDIR_AX             (1 << 5)

-#define MD_SDIR_STATE_SHFT     7                       /* AC low           */
+#define MD_SDIR_STATE_SHFT     7                       /* AC low           */

 #define MD_SDIR_STATE_MASK     (7 << 7)
 #define MD_SDIR_STATE_MASK     (7 << 7)

-#define MD_SDIR_PTR_SHFT       10                      /* C low            */
+#define MD_SDIR_PTR_SHFT       10                      /* C low            */

 #define MD_SDIR_PTR_MASK       (0x3f << 10)
 #define MD_SDIR_PTR_MASK       (0x3f << 10)

-#define MD_SDIR_CWOFF_SHFT     5                       /* C high           */
+#define MD_SDIR_CWOFF_SHFT     5                       /* C high           */

 #define MD_SDIR_CWOFF_MASK     (7 << 5)
 #define MD_SDIR_CWOFF_MASK     (7 << 5)

-#define MD_SDIR_VECMSB_SHFT    11                      /* A low            */
+#define MD_SDIR_VECMSB_SHFT    11                      /* A low            */

 #define MD_SDIR_VECMSB_BITMASK 0x1f
 #define MD_SDIR_VECMSB_BITSHFT 7
 #define MD_SDIR_VECMSB_MASK    (MD_SDIR_VECMSB_BITMASK << 11)
 #define MD_SDIR_VECMSB_BITMASK 0x1f
 #define MD_SDIR_VECMSB_BITSHFT 7
 #define MD_SDIR_VECMSB_MASK    (MD_SDIR_VECMSB_BITMASK << 11)

-#define MD_SDIR_VECLSB_SHFT    5                       /* A high           */
+#define MD_SDIR_VECLSB_SHFT    5                       /* A high           */

 #define MD_SDIR_VECLSB_BITMASK 0x7ff
 #define MD_SDIR_VECLSB_BITSHFT 0
 #define MD_SDIR_VECLSB_MASK    (MD_SDIR_VECLSB_BITMASK << 5)
 #define MD_SDIR_VECLSB_BITMASK 0x7ff
 #define MD_SDIR_VECLSB_BITSHFT 0
 #define MD_SDIR_VECLSB_MASK    (MD_SDIR_VECLSB_BITMASK << 5)


@@ -390,7 +390,7 @@
 
 /* Premium SIMM protection entry shifts and masks. */
 
 
 /* Premium SIMM protection entry shifts and masks. */
 

-#define MD_PPROT_SHFT          0                       /* Prot. field      */
+#define MD_PPROT_SHFT          0                       /* Prot. field      */

 #define MD_PPROT_MASK          7
 #define MD_PPROT_MIGMD_SHFT    3                       /* Migration mode   */
 #define MD_PPROT_MIGMD_MASK    (3 << 3)
 #define MD_PPROT_MASK          7
 #define MD_PPROT_MIGMD_SHFT    3                       /* Migration mode   */
 #define MD_PPROT_MIGMD_MASK    (3 << 3)


@@ -403,7 +403,7 @@
 
 /* Standard SIMM protection entry shifts and masks. */
 
 
 /* Standard SIMM protection entry shifts and masks. */
 

-#define MD_SPROT_SHFT          0                       /* Prot. field      */
+#define MD_SPROT_SHFT          0                       /* Prot. field      */

 #define MD_SPROT_MASK          7
 #define MD_SPROT_MIGMD_SHFT    3                       /* Migration mode   */
 #define MD_SPROT_MIGMD_MASK    (3 << 3)
 #define MD_SPROT_MASK          7
 #define MD_SPROT_MIGMD_SHFT    3                       /* Migration mode   */
 #define MD_SPROT_MIGMD_MASK    (3 << 3)


@@ -431,13 +431,13 @@
 
 #define CPU_LED_ADDR(_nasid, _slice)                                      \
        (private.p_sn00 ?                                                  \
 
 #define CPU_LED_ADDR(_nasid, _slice)                                      \
        (private.p_sn00 ?                                                  \

-        REMOTE_HUB_ADDR((_nasid), MD_UREG1_0 + ((_slice) << 5)) :         \
+        REMOTE_HUB_ADDR((_nasid), MD_UREG1_0 + ((_slice) << 5)) :         \

         REMOTE_HUB_ADDR((_nasid), MD_LED0    + ((_slice) << 3)))
 
 #define SET_CPU_LEDS(_nasid, _slice,  _val)                               \
        (HUB_S(CPU_LED_ADDR(_nasid, _slice), (_val)))
 
         REMOTE_HUB_ADDR((_nasid), MD_LED0    + ((_slice) << 3)))
 
 #define SET_CPU_LEDS(_nasid, _slice,  _val)                               \
        (HUB_S(CPU_LED_ADDR(_nasid, _slice), (_val)))
 

-#define SET_MY_LEDS(_v)                                                   \
+#define SET_MY_LEDS(_v)                                                           \

        SET_CPU_LEDS(get_nasid(), get_slice(), (_v))
 
 /*
        SET_CPU_LEDS(get_nasid(), get_slice(), (_v))
 
 /*


@@ -541,7 +541,7 @@
  */
 
 struct dir_error_reg {
  */
 
 struct dir_error_reg {

-       u64     uce_vld:   1,   /*    63: valid directory uce   */
+       u64     uce_vld:   1,   /*    63: valid directory uce   */

                ae_vld:    1,   /*    62: valid dir prot ecc error */
                ce_vld:    1,   /*    61: valid correctable ECC err*/
                rsvd1:    19,   /* 60-42: reserved              */
                ae_vld:    1,   /*    62: valid dir prot ecc error */
                ce_vld:    1,   /*    61: valid correctable ECC err*/
                rsvd1:    19,   /* 60-42: reserved              */


@@ -555,13 +555,13 @@ struct dir_error_reg {
 };
 
 typedef union md_dir_error {
 };
 
 typedef union md_dir_error {

-       u64     derr_reg;       /* the entire register          */
+       u64     derr_reg;       /* the entire register          */

        struct dir_error_reg derr_fmt;  /* the register format          */
 } md_dir_error_t;
 
 
 struct mem_error_reg {
        struct dir_error_reg derr_fmt;  /* the register format          */
 } md_dir_error_t;
 
 
 struct mem_error_reg {

-       u64     uce_vld:   1,   /*    63: valid memory uce      */
+       u64     uce_vld:   1,   /*    63: valid memory uce      */

                ce_vld:    1,   /*    62: valid correctable ECC err*/
                rsvd1:    22,   /* 61-40: reserved              */
                bad_syn:   8,   /* 39-32: bad mem ecc syndrome  */
                ce_vld:    1,   /*    62: valid correctable ECC err*/
                rsvd1:    22,   /* 61-40: reserved              */
                bad_syn:   8,   /* 39-32: bad mem ecc syndrome  */


@@ -573,8 +573,8 @@ struct mem_error_reg {
 
 
 typedef union md_mem_error {
 
 
 typedef union md_mem_error {

-       u64     merr_reg;       /* the entire register          */
-       struct mem_error_reg  merr_fmt; /* format of the mem_error reg  */
+       u64     merr_reg;       /* the entire register          */
+       struct mem_error_reg  merr_fmt; /* format of the mem_error reg  */

 } md_mem_error_t;
 
 
 } md_mem_error_t;
 
 


@@ -594,7 +594,7 @@ struct proto_error_reg {
 };
 
 typedef union md_proto_error {
 };
 
 typedef union md_proto_error {

-       u64     perr_reg;       /* the entire register          */
+       u64     perr_reg;       /* the entire register          */

        struct proto_error_reg  perr_fmt; /* format of the register     */
 } md_proto_error_t;
 
        struct proto_error_reg  perr_fmt; /* format of the register     */
 } md_proto_error_t;
 


@@ -695,33 +695,33 @@ typedef union md_pdir_loent {
  *   represent directory memory information.
  */
 
  *   represent directory memory information.
  */
 

-typedef        union   md_dir_high     {
-        md_sdir_high_t md_sdir_high;
-        md_pdir_high_t md_pdir_high;
+typedef union  md_dir_high     {
+       md_sdir_high_t  md_sdir_high;
+       md_pdir_high_t  md_pdir_high;

 } md_dir_high_t;
 
 } md_dir_high_t;
 

-typedef        union   md_dir_low      {
-        md_sdir_low_t  md_sdir_low;
-        md_pdir_low_t  md_pdir_low;
+typedef union  md_dir_low      {
+       md_sdir_low_t   md_sdir_low;
+       md_pdir_low_t   md_pdir_low;

 } md_dir_low_t;
 
 } md_dir_low_t;
 

-typedef        struct  bddir_entry     {
-        md_dir_low_t   md_dir_low;
-        md_dir_high_t  md_dir_high;
+typedef struct bddir_entry     {
+       md_dir_low_t    md_dir_low;
+       md_dir_high_t   md_dir_high;

 } bddir_entry_t;
 
 typedef struct dir_mem_entry   {
 } bddir_entry_t;
 
 typedef struct dir_mem_entry   {

-        u64            prcpf[MAX_REGIONS];
-        bddir_entry_t  directory_words[MD_PAGE_SIZE/CACHE_SLINE_SIZE];
+       u64             prcpf[MAX_REGIONS];
+       bddir_entry_t   directory_words[MD_PAGE_SIZE/CACHE_SLINE_SIZE];

 } dir_mem_entry_t;
 
 
 
 typedef union md_perf_sel {
 } dir_mem_entry_t;
 
 
 
 typedef union md_perf_sel {

-       u64     perf_sel_reg;
+       u64     perf_sel_reg;

        struct  {
                u64     perf_rsvd : 60,
        struct  {
                u64     perf_rsvd : 60,

-                       perf_en   :  1,
+                       perf_en   :  1,

                        perf_sel  :  3;
        } perf_sel_bits;
 } md_perf_sel_t;
                        perf_sel  :  3;
        } perf_sel_bits;
 } md_perf_sel_t;


@@ -730,7 +730,7 @@ typedef union md_perf_cnt {
        u64     perf_cnt;
        struct  {
                u64     perf_rsvd : 44,
        u64     perf_cnt;
        struct  {
                u64     perf_rsvd : 44,

-                       perf_cnt  : 20;
+                       perf_cnt  : 20;

        } perf_cnt_bits;
 } md_perf_cnt_t;
 
        } perf_cnt_bits;
 } md_perf_cnt_t;
 

diff --git a/arch/mips/include/asm/sn/sn0/hubni.h b/arch/mips/include/asm/sn/sn0/hubni.h
index b40d3ef97a12c575dd93fae2709245fb2fe938d8..b73c4bee65f2d3420fb67d986781a8a6aa51e62c 100644 (file)
--- a/arch/mips/include/asm/sn/sn0/hubni.h
+++ b/arch/mips/include/asm/sn/sn0/hubni.h
@@ -25,38 +25,38 @@
 #define NI_BASE_TABLES         0x630000
 
 #define NI_STATUS_REV_ID       0x600000 /* Hub network status, rev, and ID */
 #define NI_BASE_TABLES         0x630000
 
 #define NI_STATUS_REV_ID       0x600000 /* Hub network status, rev, and ID */

-#define NI_PORT_RESET          0x600008 /* Reset the network interface     */
+#define NI_PORT_RESET          0x600008 /* Reset the network interface     */

 #define NI_PROTECTION          0x600010 /* NI register access permissions  */
 #define NI_PROTECTION          0x600010 /* NI register access permissions  */

-#define NI_GLOBAL_PARMS                0x600018 /* LLP parameters                  */
+#define NI_GLOBAL_PARMS                0x600018 /* LLP parameters                  */

 #define NI_SCRATCH_REG0                0x600100 /* Scratch register 0 (64 bits)    */
 #define NI_SCRATCH_REG1                0x600108 /* Scratch register 1 (64 bits)    */
 #define NI_DIAG_PARMS          0x600110 /* Parameters for diags            */
 
 #define NI_VECTOR_PARMS                0x600200 /* Vector PIO routing parameters   */
 #define NI_SCRATCH_REG0                0x600100 /* Scratch register 0 (64 bits)    */
 #define NI_SCRATCH_REG1                0x600108 /* Scratch register 1 (64 bits)    */
 #define NI_DIAG_PARMS          0x600110 /* Parameters for diags            */
 
 #define NI_VECTOR_PARMS                0x600200 /* Vector PIO routing parameters   */

-#define NI_VECTOR              0x600208 /* Vector PIO route                */
-#define NI_VECTOR_DATA         0x600210 /* Vector PIO data                 */
-#define NI_VECTOR_STATUS       0x600300 /* Vector PIO return status        */
-#define NI_RETURN_VECTOR       0x600308 /* Vector PIO return vector        */
-#define NI_VECTOR_READ_DATA    0x600310 /* Vector PIO read data            */
+#define NI_VECTOR              0x600208 /* Vector PIO route                */
+#define NI_VECTOR_DATA         0x600210 /* Vector PIO data                 */
+#define NI_VECTOR_STATUS       0x600300 /* Vector PIO return status        */
+#define NI_RETURN_VECTOR       0x600308 /* Vector PIO return vector        */
+#define NI_VECTOR_READ_DATA    0x600310 /* Vector PIO read data            */

 #define NI_VECTOR_CLEAR                0x600380 /* Vector PIO read & clear status  */
 
 #define NI_VECTOR_CLEAR                0x600380 /* Vector PIO read & clear status  */
 

-#define NI_IO_PROTECT          0x600400 /* PIO protection bits             */
-#define NI_IO_PROT_OVRRD       0x600408 /* PIO protection bit override     */
-
-#define NI_AGE_CPU0_MEMORY     0x600500 /* CPU 0 memory age control        */
-#define NI_AGE_CPU0_PIO                0x600508 /* CPU 0 PIO age control           */
-#define NI_AGE_CPU1_MEMORY     0x600510 /* CPU 1 memory age control        */
-#define NI_AGE_CPU1_PIO                0x600518 /* CPU 1 PIO age control           */
-#define NI_AGE_GBR_MEMORY      0x600520 /* GBR memory age control          */
-#define NI_AGE_GBR_PIO         0x600528 /* GBR PIO age control             */
-#define NI_AGE_IO_MEMORY       0x600530 /* IO memory age control           */
-#define NI_AGE_IO_PIO          0x600538 /* IO PIO age control              */
+#define NI_IO_PROTECT          0x600400 /* PIO protection bits             */
+#define NI_IO_PROT_OVRRD       0x600408 /* PIO protection bit override     */
+
+#define NI_AGE_CPU0_MEMORY     0x600500 /* CPU 0 memory age control        */
+#define NI_AGE_CPU0_PIO                0x600508 /* CPU 0 PIO age control           */
+#define NI_AGE_CPU1_MEMORY     0x600510 /* CPU 1 memory age control        */
+#define NI_AGE_CPU1_PIO                0x600518 /* CPU 1 PIO age control           */
+#define NI_AGE_GBR_MEMORY      0x600520 /* GBR memory age control          */
+#define NI_AGE_GBR_PIO         0x600528 /* GBR PIO age control             */
+#define NI_AGE_IO_MEMORY       0x600530 /* IO memory age control           */
+#define NI_AGE_IO_PIO          0x600538 /* IO PIO age control              */

 #define NI_AGE_REG_MIN         NI_AGE_CPU0_MEMORY
 #define NI_AGE_REG_MAX         NI_AGE_IO_PIO
 
 #define NI_AGE_REG_MIN         NI_AGE_CPU0_MEMORY
 #define NI_AGE_REG_MAX         NI_AGE_IO_PIO
 

-#define NI_PORT_PARMS          0x608000 /* LLP Parameters                  */
-#define NI_PORT_ERROR          0x608008 /* LLP Errors                      */
-#define NI_PORT_ERROR_CLEAR    0x608088 /* Clear the error bits            */
+#define NI_PORT_PARMS          0x608000 /* LLP Parameters                  */
+#define NI_PORT_ERROR          0x608008 /* LLP Errors                      */
+#define NI_PORT_ERROR_CLEAR    0x608088 /* Clear the error bits            */

 
 #define NI_META_TABLE0         0x638000 /* First meta routing table entry  */
 #define NI_META_TABLE(_x)      (NI_META_TABLE0 + (8 * (_x)))
 
 #define NI_META_TABLE0         0x638000 /* First meta routing table entry  */
 #define NI_META_TABLE(_x)      (NI_META_TABLE0 + (8 * (_x)))


@@ -76,13 +76,13 @@
 #define NSRI_LINKUP_SHFT       29
 #define NSRI_LINKUP_MASK       (UINT64_CAST 0x1 << 29)
 #define NSRI_DOWNREASON_SHFT   28              /* 0=failed, 1=never came   */
 #define NSRI_LINKUP_SHFT       29
 #define NSRI_LINKUP_MASK       (UINT64_CAST 0x1 << 29)
 #define NSRI_DOWNREASON_SHFT   28              /* 0=failed, 1=never came   */

-#define NSRI_DOWNREASON_MASK   (UINT64_CAST 0x1 << 28) /*    out of reset. */
+#define NSRI_DOWNREASON_MASK   (UINT64_CAST 0x1 << 28) /*    out of reset. */

 #define NSRI_MORENODES_SHFT    18
 #define NSRI_MORENODES_MASK    (UINT64_CAST 1 << 18)   /* Max. # of nodes  */
 #define         MORE_MEMORY            0
 #define         MORE_NODES             1
 #define NSRI_REGIONSIZE_SHFT   17
 #define NSRI_MORENODES_SHFT    18
 #define NSRI_MORENODES_MASK    (UINT64_CAST 1 << 18)   /* Max. # of nodes  */
 #define         MORE_MEMORY            0
 #define         MORE_NODES             1
 #define NSRI_REGIONSIZE_SHFT   17

-#define NSRI_REGIONSIZE_MASK   (UINT64_CAST 1 << 17)   /* Granularity      */
+#define NSRI_REGIONSIZE_MASK   (UINT64_CAST 1 << 17)   /* Granularity      */

 #define         REGIONSIZE_FINE        1
 #define         REGIONSIZE_COARSE      0
 #define NSRI_NODEID_SHFT       8
 #define         REGIONSIZE_FINE        1
 #define         REGIONSIZE_COARSE      0
 #define NSRI_NODEID_SHFT       8


@@ -90,14 +90,14 @@
 #define NSRI_REV_SHFT          4
 #define NSRI_REV_MASK          (UINT64_CAST 0xf << 4)  /* Chip Revision    */
 #define NSRI_CHIPID_SHFT       0
 #define NSRI_REV_SHFT          4
 #define NSRI_REV_MASK          (UINT64_CAST 0xf << 4)  /* Chip Revision    */
 #define NSRI_CHIPID_SHFT       0

-#define NSRI_CHIPID_MASK       (UINT64_CAST 0xf)       /* Chip type ID     */
+#define NSRI_CHIPID_MASK       (UINT64_CAST 0xf)       /* Chip type ID     */

 
 /*
 
 /*

- * In fine mode, each node is a region.  In coarse mode, there are
+ * In fine mode, each node is a region.         In coarse mode, there are

  * eight nodes per region.
  */
 #define NASID_TO_FINEREG_SHFT  0
  * eight nodes per region.
  */
 #define NASID_TO_FINEREG_SHFT  0

-#define NASID_TO_COARSEREG_SHFT        3
+#define NASID_TO_COARSEREG_SHFT 3

 
 /* NI_PORT_RESET mask definitions */
 
 
 /* NI_PORT_RESET mask definitions */
 


@@ -111,21 +111,21 @@
 
 /* NI_GLOBAL_PARMS mask and shift definitions */
 
 
 /* NI_GLOBAL_PARMS mask and shift definitions */
 

-#define NGP_MAXRETRY_SHFT      48              /* Maximum retries          */
+#define NGP_MAXRETRY_SHFT      48              /* Maximum retries          */

 #define NGP_MAXRETRY_MASK      (UINT64_CAST 0x3ff << 48)
 #define NGP_MAXRETRY_MASK      (UINT64_CAST 0x3ff << 48)

-#define NGP_TAILTOWRAP_SHFT    32              /* Tail timeout wrap        */
+#define NGP_TAILTOWRAP_SHFT    32              /* Tail timeout wrap        */

 #define NGP_TAILTOWRAP_MASK    (UINT64_CAST 0xffff << 32)
 
 #define NGP_TAILTOWRAP_MASK    (UINT64_CAST 0xffff << 32)
 

-#define NGP_CREDITTOVAL_SHFT   16              /* Tail timeout wrap        */
+#define NGP_CREDITTOVAL_SHFT   16              /* Tail timeout wrap        */

 #define NGP_CREDITTOVAL_MASK   (UINT64_CAST 0xf << 16)
 #define NGP_CREDITTOVAL_MASK   (UINT64_CAST 0xf << 16)

-#define NGP_TAILTOVAL_SHFT     4               /* Tail timeout value       */
+#define NGP_TAILTOVAL_SHFT     4               /* Tail timeout value       */

 #define NGP_TAILTOVAL_MASK     (UINT64_CAST 0xf << 4)
 
 /* NI_DIAG_PARMS mask and shift definitions */
 
 #define NDP_PORTTORESET                (UINT64_CAST 1 << 18)   /* Port tmout reset */
 #define NDP_LLP8BITMODE                (UINT64_CAST 1 << 12)   /* LLP 8-bit mode   */
 #define NGP_TAILTOVAL_MASK     (UINT64_CAST 0xf << 4)
 
 /* NI_DIAG_PARMS mask and shift definitions */
 
 #define NDP_PORTTORESET                (UINT64_CAST 1 << 18)   /* Port tmout reset */
 #define NDP_LLP8BITMODE                (UINT64_CAST 1 << 12)   /* LLP 8-bit mode   */

-#define NDP_PORTDISABLE                (UINT64_CAST 1 <<  6)   /* Port disable     */
+#define NDP_PORTDISABLE                (UINT64_CAST 1 <<  6)   /* Port disable     */

 #define NDP_SENDERROR          (UINT64_CAST 1)         /* Send data error  */
 
 /*
 #define NDP_SENDERROR          (UINT64_CAST 1)         /* Send data error  */
 
 /*


@@ -137,7 +137,7 @@
 #define NVP_PIOID_MASK         (UINT64_CAST 0x3ff << 40)
 #define NVP_WRITEID_SHFT       32
 #define NVP_WRITEID_MASK       (UINT64_CAST 0xff << 32)
 #define NVP_PIOID_MASK         (UINT64_CAST 0x3ff << 40)
 #define NVP_WRITEID_SHFT       32
 #define NVP_WRITEID_MASK       (UINT64_CAST 0xff << 32)

-#define NVP_ADDRESS_MASK       (UINT64_CAST 0xffff8)   /* Bits 19:3        */
+#define NVP_ADDRESS_MASK       (UINT64_CAST 0xffff8)   /* Bits 19:3        */

 #define NVP_TYPE_SHFT          0
 #define NVP_TYPE_MASK          (UINT64_CAST 0x3)
 
 #define NVP_TYPE_SHFT          0
 #define NVP_TYPE_MASK          (UINT64_CAST 0x3)
 


@@ -151,7 +151,7 @@
 #define NVS_PIOID_MASK         (UINT64_CAST 0x3ff << 40)
 #define NVS_WRITEID_SHFT       32
 #define NVS_WRITEID_MASK       (UINT64_CAST 0xff << 32)
 #define NVS_PIOID_MASK         (UINT64_CAST 0x3ff << 40)
 #define NVS_WRITEID_SHFT       32
 #define NVS_WRITEID_MASK       (UINT64_CAST 0xff << 32)

-#define NVS_ADDRESS_MASK       (UINT64_CAST 0xfffffff8)   /* Bits 31:3     */
+#define NVS_ADDRESS_MASK       (UINT64_CAST 0xfffffff8)   /* Bits 31:3     */

 #define NVS_TYPE_SHFT          0
 #define NVS_TYPE_MASK          (UINT64_CAST 0x7)
 #define NVS_ERROR_MASK         (UINT64_CAST 0x4)  /* bit set means error */
 #define NVS_TYPE_SHFT          0
 #define NVS_TYPE_MASK          (UINT64_CAST 0x7)
 #define NVS_ERROR_MASK         (UINT64_CAST 0x4)  /* bit set means error */


@@ -161,10 +161,10 @@
 #define         PIOTYPE_WRITE          1       /* VECTOR_PARMS and VECTOR_STATUS   */
 #define         PIOTYPE_UNDEFINED      2       /* VECTOR_PARMS and VECTOR_STATUS   */
 #define         PIOTYPE_EXCHANGE       3       /* VECTOR_PARMS and VECTOR_STATUS   */
 #define         PIOTYPE_WRITE          1       /* VECTOR_PARMS and VECTOR_STATUS   */
 #define         PIOTYPE_UNDEFINED      2       /* VECTOR_PARMS and VECTOR_STATUS   */
 #define         PIOTYPE_EXCHANGE       3       /* VECTOR_PARMS and VECTOR_STATUS   */

-#define         PIOTYPE_ADDR_ERR       4       /* VECTOR_STATUS only               */
-#define         PIOTYPE_CMD_ERR        5       /* VECTOR_STATUS only               */
-#define         PIOTYPE_PROT_ERR       6       /* VECTOR_STATUS only               */
-#define         PIOTYPE_UNKNOWN        7       /* VECTOR_STATUS only               */
+#define         PIOTYPE_ADDR_ERR       4       /* VECTOR_STATUS only               */
+#define         PIOTYPE_CMD_ERR        5       /* VECTOR_STATUS only               */
+#define         PIOTYPE_PROT_ERR       6       /* VECTOR_STATUS only               */
+#define         PIOTYPE_UNKNOWN        7       /* VECTOR_STATUS only               */

 
 /* NI_AGE_XXX mask and shift definitions */
 
 
 /* NI_AGE_XXX mask and shift definitions */
 


@@ -215,7 +215,7 @@
 
 #define NPE_FATAL_ERRORS       (NPE_LINKRESET | NPE_INTERNALERROR |    \
                                 NPE_BADMESSAGE | NPE_BADDEST |         \
 
 #define NPE_FATAL_ERRORS       (NPE_LINKRESET | NPE_INTERNALERROR |    \
                                 NPE_BADMESSAGE | NPE_BADDEST |         \

-                                NPE_FIFOOVERFLOW | NPE_CREDITTO_MASK | \
+                                NPE_FIFOOVERFLOW | NPE_CREDITTO_MASK | \

                                 NPE_TAILTO_MASK)
 
 /* NI_META_TABLE mask and shift definitions */
                                 NPE_TAILTO_MASK)
 
 /* NI_META_TABLE mask and shift definitions */


@@ -231,7 +231,7 @@
 typedef union  hubni_port_error_u {
        u64     nipe_reg_value;
        struct {
 typedef union  hubni_port_error_u {
        u64     nipe_reg_value;
        struct {

-           u64 nipe_rsvd:      26,     /* unused */
+           u64 nipe_rsvd:      26,     /* unused */

                nipe_lnk_reset:  1,     /* link reset */
                nipe_intl_err:   1,     /* internal error */
                nipe_bad_msg:    1,     /* bad message */
                nipe_lnk_reset:  1,     /* link reset */
                nipe_intl_err:   1,     /* internal error */
                nipe_bad_msg:    1,     /* bad message */

diff --git a/arch/mips/include/asm/sn/sn0/hubpi.h b/arch/mips/include/asm/sn/sn0/hubpi.h
index e39f5f9da040595d2e80c124398ecae29012ba55..7b83655913c521be4081ae66b294f6005150fba8 100644 (file)
--- a/arch/mips/include/asm/sn/sn0/hubpi.h
+++ b/arch/mips/include/asm/sn/sn0/hubpi.h
@@ -8,8 +8,8 @@
  * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
  * Copyright (C) 1999 by Ralf Baechle
  */
  * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
  * Copyright (C) 1999 by Ralf Baechle
  */

-#ifndef        _ASM_SN_SN0_HUBPI_H
-#define        _ASM_SN_SN0_HUBPI_H
+#ifndef _ASM_SN_SN0_HUBPI_H
+#define _ASM_SN_SN0_HUBPI_H

 
 #include <linux/types.h>
 
 
 #include <linux/types.h>
 


@@ -25,13 +25,13 @@
 
 /* General protection and control registers */
 
 
 /* General protection and control registers */
 

-#define PI_CPU_PROTECT         0x000000 /* CPU Protection                  */
-#define PI_PROT_OVERRD         0x000008 /* Clear CPU Protection bit        */
-#define        PI_IO_PROTECT           0x000010 /* Interrupt Pending Protection    */
+#define PI_CPU_PROTECT         0x000000 /* CPU Protection                  */
+#define PI_PROT_OVERRD         0x000008 /* Clear CPU Protection bit        */
+#define PI_IO_PROTECT          0x000010 /* Interrupt Pending Protection    */

 #define PI_REGION_PRESENT      0x000018 /* Indicates whether region exists */
 #define PI_REGION_PRESENT      0x000018 /* Indicates whether region exists */

-#define PI_CPU_NUM             0x000020 /* CPU Number ID                   */
-#define PI_CALIAS_SIZE         0x000028 /* Cached Alias Size               */
-#define PI_MAX_CRB_TIMEOUT     0x000030 /* Maximum Timeout for CRB         */
+#define PI_CPU_NUM             0x000020 /* CPU Number ID                   */
+#define PI_CALIAS_SIZE         0x000028 /* Cached Alias Size               */
+#define PI_MAX_CRB_TIMEOUT     0x000030 /* Maximum Timeout for CRB         */

 #define PI_CRB_SFACTOR         0x000038 /* Scale factor for CRB timeout    */
 
 /* CALIAS values */
 #define PI_CRB_SFACTOR         0x000038 /* Scale factor for CRB timeout    */
 
 /* CALIAS values */


@@ -54,28 +54,28 @@
 
 /* Processor control and status checking */
 
 
 /* Processor control and status checking */
 

-#define PI_CPU_PRESENT_A       0x000040 /* CPU Present A                   */
-#define PI_CPU_PRESENT_B       0x000048 /* CPU Present B                   */
-#define PI_CPU_ENABLE_A                0x000050 /* CPU Enable A                    */
-#define PI_CPU_ENABLE_B                0x000058 /* CPU Enable B                    */
-#define PI_REPLY_LEVEL         0x000060 /* Reply Level                     */
+#define PI_CPU_PRESENT_A       0x000040 /* CPU Present A                   */
+#define PI_CPU_PRESENT_B       0x000048 /* CPU Present B                   */
+#define PI_CPU_ENABLE_A                0x000050 /* CPU Enable A                    */
+#define PI_CPU_ENABLE_B                0x000058 /* CPU Enable B                    */
+#define PI_REPLY_LEVEL         0x000060 /* Reply Level                     */

 #define PI_HARDRESET_BIT       0x020068 /* Bit cleared by s/w on SR        */
 #define PI_HARDRESET_BIT       0x020068 /* Bit cleared by s/w on SR        */

-#define PI_NMI_A               0x000070 /* NMI to CPU A                    */
-#define PI_NMI_B               0x000078 /* NMI to CPU B                    */
+#define PI_NMI_A               0x000070 /* NMI to CPU A                    */
+#define PI_NMI_B               0x000078 /* NMI to CPU B                    */

 #define PI_NMI_OFFSET          (PI_NMI_B - PI_NMI_A)
 #define PI_NMI_OFFSET          (PI_NMI_B - PI_NMI_A)

-#define PI_SOFTRESET           0x000080 /* Softreset (to both CPUs)        */
+#define PI_SOFTRESET           0x000080 /* Softreset (to both CPUs)        */

 
 

-/* Regular Interrupt register checking.  */
+/* Regular Interrupt register checking.         */

 
 #define PI_INT_PEND_MOD                0x000090 /* Write to set pending ints       */
 
 #define PI_INT_PEND_MOD                0x000090 /* Write to set pending ints       */

-#define PI_INT_PEND0           0x000098 /* Read to get pending ints        */
-#define PI_INT_PEND1           0x0000a0 /* Read to get pending ints        */
-#define PI_INT_MASK0_A         0x0000a8 /* Interrupt Mask 0 for CPU A      */
-#define PI_INT_MASK1_A         0x0000b0 /* Interrupt Mask 1 for CPU A      */
-#define PI_INT_MASK0_B         0x0000b8 /* Interrupt Mask 0 for CPU B      */
-#define PI_INT_MASK1_B         0x0000c0 /* Interrupt Mask 1 for CPU B      */
+#define PI_INT_PEND0           0x000098 /* Read to get pending ints        */
+#define PI_INT_PEND1           0x0000a0 /* Read to get pending ints        */
+#define PI_INT_MASK0_A         0x0000a8 /* Interrupt Mask 0 for CPU A      */
+#define PI_INT_MASK1_A         0x0000b0 /* Interrupt Mask 1 for CPU A      */
+#define PI_INT_MASK0_B         0x0000b8 /* Interrupt Mask 0 for CPU B      */
+#define PI_INT_MASK1_B         0x0000c0 /* Interrupt Mask 1 for CPU B      */

 
 

-#define PI_INT_MASK_OFFSET     0x10     /* Offset from A to B              */
+#define PI_INT_MASK_OFFSET     0x10     /* Offset from A to B              */

 
 /* Crosscall interrupts */
 
 
 /* Crosscall interrupts */
 


@@ -83,49 +83,49 @@
 #define PI_CC_PEND_SET_B       0x0000d0 /* CC Interrupt Pending Set, CPU B */
 #define PI_CC_PEND_CLR_A       0x0000d8 /* CC Interrupt Pending Clr, CPU A */
 #define PI_CC_PEND_CLR_B       0x0000e0 /* CC Interrupt Pending Clr, CPU B */
 #define PI_CC_PEND_SET_B       0x0000d0 /* CC Interrupt Pending Set, CPU B */
 #define PI_CC_PEND_CLR_A       0x0000d8 /* CC Interrupt Pending Clr, CPU A */
 #define PI_CC_PEND_CLR_B       0x0000e0 /* CC Interrupt Pending Clr, CPU B */

-#define PI_CC_MASK             0x0000e8 /* CC Interrupt mask               */
+#define PI_CC_MASK             0x0000e8 /* CC Interrupt mask               */

 
 

-#define PI_INT_SET_OFFSET      0x08     /* Offset from A to B              */
+#define PI_INT_SET_OFFSET      0x08     /* Offset from A to B              */

 
 /* Realtime Counter and Profiler control registers */
 
 
 /* Realtime Counter and Profiler control registers */
 

-#define PI_RT_COUNT            0x030100 /* Real Time Counter               */
-#define PI_RT_COMPARE_A                0x000108 /* Real Time Compare A             */
-#define PI_RT_COMPARE_B                0x000110 /* Real Time Compare B             */
+#define PI_RT_COUNT            0x030100 /* Real Time Counter               */
+#define PI_RT_COMPARE_A                0x000108 /* Real Time Compare A             */
+#define PI_RT_COMPARE_B                0x000110 /* Real Time Compare B             */

 #define PI_PROFILE_COMPARE     0x000118 /* L5 int to both cpus when == RTC */
 #define PI_PROFILE_COMPARE     0x000118 /* L5 int to both cpus when == RTC */

-#define PI_RT_PEND_A           0x000120 /* Set if RT int for A pending     */
-#define PI_RT_PEND_B           0x000128 /* Set if RT int for B pending     */
+#define PI_RT_PEND_A           0x000120 /* Set if RT int for A pending     */
+#define PI_RT_PEND_B           0x000128 /* Set if RT int for B pending     */

 #define PI_PROF_PEND_A         0x000130 /* Set if Prof int for A pending   */
 #define PI_PROF_PEND_B         0x000138 /* Set if Prof int for B pending   */
 #define PI_PROF_PEND_A         0x000130 /* Set if Prof int for A pending   */
 #define PI_PROF_PEND_B         0x000138 /* Set if Prof int for B pending   */

-#define PI_RT_EN_A             0x000140 /* RT int for CPU A enable         */
-#define PI_RT_EN_B             0x000148 /* RT int for CPU B enable         */
-#define PI_PROF_EN_A           0x000150 /* PROF int for CPU A enable       */
-#define PI_PROF_EN_B           0x000158 /* PROF int for CPU B enable       */
-#define PI_RT_LOCAL_CTRL       0x000160 /* RT control register             */
+#define PI_RT_EN_A             0x000140 /* RT int for CPU A enable         */
+#define PI_RT_EN_B             0x000148 /* RT int for CPU B enable         */
+#define PI_PROF_EN_A           0x000150 /* PROF int for CPU A enable       */
+#define PI_PROF_EN_B           0x000158 /* PROF int for CPU B enable       */
+#define PI_RT_LOCAL_CTRL       0x000160 /* RT control register             */

 #define PI_RT_FILTER_CTRL      0x000168 /* GCLK Filter control register    */
 
 #define PI_COUNT_OFFSET                0x08     /* A to B offset for all counts    */
 
 /* Built-In Self Test support */
 
 #define PI_RT_FILTER_CTRL      0x000168 /* GCLK Filter control register    */
 
 #define PI_COUNT_OFFSET                0x08     /* A to B offset for all counts    */
 
 /* Built-In Self Test support */
 

-#define PI_BIST_WRITE_DATA     0x000200 /* BIST write data                 */
-#define PI_BIST_READ_DATA      0x000208 /* BIST read data                  */
-#define PI_BIST_COUNT_TARG     0x000210 /* BIST Count and Target           */
-#define PI_BIST_READY          0x000218 /* BIST Ready indicator            */
-#define PI_BIST_SHIFT_LOAD     0x000220 /* BIST control                    */
-#define PI_BIST_SHIFT_UNLOAD   0x000228 /* BIST control                    */
-#define PI_BIST_ENTER_RUN      0x000230 /* BIST control                    */
+#define PI_BIST_WRITE_DATA     0x000200 /* BIST write data                 */
+#define PI_BIST_READ_DATA      0x000208 /* BIST read data                  */
+#define PI_BIST_COUNT_TARG     0x000210 /* BIST Count and Target           */
+#define PI_BIST_READY          0x000218 /* BIST Ready indicator            */
+#define PI_BIST_SHIFT_LOAD     0x000220 /* BIST control                    */
+#define PI_BIST_SHIFT_UNLOAD   0x000228 /* BIST control                    */
+#define PI_BIST_ENTER_RUN      0x000230 /* BIST control                    */

 
 /* Graphics control registers */
 
 
 /* Graphics control registers */
 

-#define PI_GFX_PAGE_A          0x000300 /* Graphics page A                 */
-#define PI_GFX_CREDIT_CNTR_A   0x000308 /* Graphics credit counter A       */
-#define PI_GFX_BIAS_A          0x000310 /* Graphics bias A                 */
+#define PI_GFX_PAGE_A          0x000300 /* Graphics page A                 */
+#define PI_GFX_CREDIT_CNTR_A   0x000308 /* Graphics credit counter A       */
+#define PI_GFX_BIAS_A          0x000310 /* Graphics bias A                 */

 #define PI_GFX_INT_CNTR_A      0x000318 /* Graphics interrupt counter A    */
 #define PI_GFX_INT_CMP_A       0x000320 /* Graphics interrupt comparator A */
 #define PI_GFX_INT_CNTR_A      0x000318 /* Graphics interrupt counter A    */
 #define PI_GFX_INT_CMP_A       0x000320 /* Graphics interrupt comparator A */

-#define PI_GFX_PAGE_B          0x000328 /* Graphics page B                 */
-#define PI_GFX_CREDIT_CNTR_B   0x000330 /* Graphics credit counter B       */
-#define PI_GFX_BIAS_B          0x000338 /* Graphics bias B                 */
+#define PI_GFX_PAGE_B          0x000328 /* Graphics page B                 */
+#define PI_GFX_CREDIT_CNTR_B   0x000330 /* Graphics credit counter B       */
+#define PI_GFX_BIAS_B          0x000338 /* Graphics bias B                 */

 #define PI_GFX_INT_CNTR_B      0x000340 /* Graphics interrupt counter B    */
 #define PI_GFX_INT_CMP_B       0x000348 /* Graphics interrupt comparator B */
 
 #define PI_GFX_INT_CNTR_B      0x000340 /* Graphics interrupt counter B    */
 #define PI_GFX_INT_CMP_B       0x000348 /* Graphics interrupt comparator B */
 


@@ -138,24 +138,24 @@
 #define PI_ERR_INT_MASK_B      0x000410 /* Error Interrupt mask for CPU B  */
 #define PI_ERR_STACK_ADDR_A    0x000418 /* Error stack address for CPU A   */
 #define PI_ERR_STACK_ADDR_B    0x000420 /* Error stack address for CPU B   */
 #define PI_ERR_INT_MASK_B      0x000410 /* Error Interrupt mask for CPU B  */
 #define PI_ERR_STACK_ADDR_A    0x000418 /* Error stack address for CPU A   */
 #define PI_ERR_STACK_ADDR_B    0x000420 /* Error stack address for CPU B   */

-#define PI_ERR_STACK_SIZE      0x000428 /* Error Stack Size                */
-#define PI_ERR_STATUS0_A       0x000430 /* Error Status 0A                 */
+#define PI_ERR_STACK_SIZE      0x000428 /* Error Stack Size                */
+#define PI_ERR_STATUS0_A       0x000430 /* Error Status 0A                 */

 #define PI_ERR_STATUS0_A_RCLR  0x000438 /* Error Status 0A clear on read   */
 #define PI_ERR_STATUS0_A_RCLR  0x000438 /* Error Status 0A clear on read   */

-#define PI_ERR_STATUS1_A       0x000440 /* Error Status 1A                 */
+#define PI_ERR_STATUS1_A       0x000440 /* Error Status 1A                 */

 #define PI_ERR_STATUS1_A_RCLR  0x000448 /* Error Status 1A clear on read   */
 #define PI_ERR_STATUS1_A_RCLR  0x000448 /* Error Status 1A clear on read   */

-#define PI_ERR_STATUS0_B       0x000450 /* Error Status 0B                 */
+#define PI_ERR_STATUS0_B       0x000450 /* Error Status 0B                 */

 #define PI_ERR_STATUS0_B_RCLR  0x000458 /* Error Status 0B clear on read   */
 #define PI_ERR_STATUS0_B_RCLR  0x000458 /* Error Status 0B clear on read   */

-#define PI_ERR_STATUS1_B       0x000460 /* Error Status 1B                 */
+#define PI_ERR_STATUS1_B       0x000460 /* Error Status 1B                 */

 #define PI_ERR_STATUS1_B_RCLR  0x000468 /* Error Status 1B clear on read   */
 #define PI_ERR_STATUS1_B_RCLR  0x000468 /* Error Status 1B clear on read   */

-#define PI_SPOOL_CMP_A         0x000470 /* Spool compare for CPU A         */
-#define PI_SPOOL_CMP_B         0x000478 /* Spool compare for CPU B         */
-#define PI_CRB_TIMEOUT_A       0x000480 /* Timed out CRB entries for A     */
-#define PI_CRB_TIMEOUT_B       0x000488 /* Timed out CRB entries for B     */
+#define PI_SPOOL_CMP_A         0x000470 /* Spool compare for CPU A         */
+#define PI_SPOOL_CMP_B         0x000478 /* Spool compare for CPU B         */
+#define PI_CRB_TIMEOUT_A       0x000480 /* Timed out CRB entries for A     */
+#define PI_CRB_TIMEOUT_B       0x000488 /* Timed out CRB entries for B     */

 #define PI_SYSAD_ERRCHK_EN     0x000490 /* Enables SYSAD error checking    */
 #define PI_SYSAD_ERRCHK_EN     0x000490 /* Enables SYSAD error checking    */

-#define PI_BAD_CHECK_BIT_A     0x000498 /* Force SYSAD check bit error     */
-#define PI_BAD_CHECK_BIT_B     0x0004a0 /* Force SYSAD check bit error     */
-#define PI_NACK_CNT_A          0x0004a8 /* Consecutive NACK counter        */
-#define PI_NACK_CNT_B          0x0004b0 /*     "       " for CPU B         */
+#define PI_BAD_CHECK_BIT_A     0x000498 /* Force SYSAD check bit error     */
+#define PI_BAD_CHECK_BIT_B     0x0004a0 /* Force SYSAD check bit error     */
+#define PI_NACK_CNT_A          0x0004a8 /* Consecutive NACK counter        */
+#define PI_NACK_CNT_B          0x0004b0 /*     "       " for CPU B         */

 #define PI_NACK_CMP            0x0004b8 /* NACK count compare              */
 #define PI_STACKADDR_OFFSET    (PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A)
 #define PI_ERRSTAT_OFFSET      (PI_ERR_STATUS0_B - PI_ERR_STATUS0_A)
 #define PI_NACK_CMP            0x0004b8 /* NACK count compare              */
 #define PI_STACKADDR_OFFSET    (PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A)
 #define PI_ERRSTAT_OFFSET      (PI_ERR_STATUS0_B - PI_ERR_STATUS0_A)


@@ -168,7 +168,7 @@
 #define PI_ERR_SPUR_MSG_A      0x00000008
 #define PI_ERR_WRB_TERR_B      0x00000010      /* WRB TERR                 */
 #define PI_ERR_WRB_TERR_A      0x00000020
 #define PI_ERR_SPUR_MSG_A      0x00000008
 #define PI_ERR_WRB_TERR_B      0x00000010      /* WRB TERR                 */
 #define PI_ERR_WRB_TERR_A      0x00000020

-#define PI_ERR_WRB_WERR_B      0x00000040      /* WRB WERR                 */
+#define PI_ERR_WRB_WERR_B      0x00000040      /* WRB WERR                 */

 #define PI_ERR_WRB_WERR_A      0x00000080
 #define PI_ERR_SYSSTATE_B      0x00000100      /* SysState parity error    */
 #define PI_ERR_SYSSTATE_A      0x00000200
 #define PI_ERR_WRB_WERR_A      0x00000080
 #define PI_ERR_SYSSTATE_B      0x00000100      /* SysState parity error    */
 #define PI_ERR_SYSSTATE_A      0x00000200


@@ -196,32 +196,32 @@
  * The following three macros define all possible error int pends.
  */
 
  * The following three macros define all possible error int pends.
  */
 

-#define PI_FATAL_ERR_CPU_A     (PI_ERR_SYSSTATE_TAG_A  | \
-                                PI_ERR_BAD_SPOOL_A     | \
-                                PI_ERR_SYSCMD_ADDR_A   | \
-                                PI_ERR_SYSCMD_DATA_A   | \
-                                PI_ERR_SYSAD_ADDR_A    | \
+#define PI_FATAL_ERR_CPU_A     (PI_ERR_SYSSTATE_TAG_A  | \
+                                PI_ERR_BAD_SPOOL_A     | \
+                                PI_ERR_SYSCMD_ADDR_A   | \
+                                PI_ERR_SYSCMD_DATA_A   | \
+                                PI_ERR_SYSAD_ADDR_A    | \

                                 PI_ERR_SYSAD_DATA_A    | \
                                 PI_ERR_SYSSTATE_A)
 
                                 PI_ERR_SYSAD_DATA_A    | \
                                 PI_ERR_SYSSTATE_A)
 

-#define PI_MISC_ERR_CPU_A      (PI_ERR_UNCAC_UNCORR_A  | \
-                                PI_ERR_WRB_WERR_A      | \
-                                PI_ERR_WRB_TERR_A      | \
-                                PI_ERR_SPUR_MSG_A      | \
+#define PI_MISC_ERR_CPU_A      (PI_ERR_UNCAC_UNCORR_A  | \
+                                PI_ERR_WRB_WERR_A      | \
+                                PI_ERR_WRB_TERR_A      | \
+                                PI_ERR_SPUR_MSG_A      | \

                                 PI_ERR_SPOOL_CMP_A)
 
                                 PI_ERR_SPOOL_CMP_A)
 

-#define PI_FATAL_ERR_CPU_B     (PI_ERR_SYSSTATE_TAG_B  | \
-                                PI_ERR_BAD_SPOOL_B     | \
-                                PI_ERR_SYSCMD_ADDR_B   | \
-                                PI_ERR_SYSCMD_DATA_B   | \
-                                PI_ERR_SYSAD_ADDR_B    | \
+#define PI_FATAL_ERR_CPU_B     (PI_ERR_SYSSTATE_TAG_B  | \
+                                PI_ERR_BAD_SPOOL_B     | \
+                                PI_ERR_SYSCMD_ADDR_B   | \
+                                PI_ERR_SYSCMD_DATA_B   | \
+                                PI_ERR_SYSAD_ADDR_B    | \

                                 PI_ERR_SYSAD_DATA_B    | \
                                 PI_ERR_SYSSTATE_B)
 
                                 PI_ERR_SYSAD_DATA_B    | \
                                 PI_ERR_SYSSTATE_B)
 

-#define PI_MISC_ERR_CPU_B      (PI_ERR_UNCAC_UNCORR_B  | \
-                                PI_ERR_WRB_WERR_B      | \
-                                PI_ERR_WRB_TERR_B      | \
-                                PI_ERR_SPUR_MSG_B      | \
+#define PI_MISC_ERR_CPU_B      (PI_ERR_UNCAC_UNCORR_B  | \
+                                PI_ERR_WRB_WERR_B      | \
+                                PI_ERR_WRB_TERR_B      | \
+                                PI_ERR_SPUR_MSG_B      | \

                                 PI_ERR_SPOOL_CMP_B)
 
 #define PI_ERR_GENERIC (PI_ERR_MD_UNCORR)
                                 PI_ERR_SPOOL_CMP_B)
 
 #define PI_ERR_GENERIC (PI_ERR_MD_UNCORR)


@@ -242,24 +242,24 @@
 #define PI_ERR_ST0_CMD_SHFT    17
 #define PI_ERR_ST0_ADDR_MASK   0x3ffffffffe000000
 #define PI_ERR_ST0_ADDR_SHFT   25
 #define PI_ERR_ST0_CMD_SHFT    17
 #define PI_ERR_ST0_ADDR_MASK   0x3ffffffffe000000
 #define PI_ERR_ST0_ADDR_SHFT   25

-#define PI_ERR_ST0_OVERRUN_MASK        0x4000000000000000
-#define PI_ERR_ST0_OVERRUN_SHFT        62
+#define PI_ERR_ST0_OVERRUN_MASK 0x4000000000000000
+#define PI_ERR_ST0_OVERRUN_SHFT 62

 #define PI_ERR_ST0_VALID_MASK  0x8000000000000000
 #define PI_ERR_ST0_VALID_SHFT  63
 
 /* Fields in PI_ERR_STATUS1_[AB] */
 #define PI_ERR_ST1_SPOOL_MASK  0x00000000001fffff
 #define PI_ERR_ST1_SPOOL_SHFT  0
 #define PI_ERR_ST0_VALID_MASK  0x8000000000000000
 #define PI_ERR_ST0_VALID_SHFT  63
 
 /* Fields in PI_ERR_STATUS1_[AB] */
 #define PI_ERR_ST1_SPOOL_MASK  0x00000000001fffff
 #define PI_ERR_ST1_SPOOL_SHFT  0

-#define PI_ERR_ST1_TOUTCNT_MASK        0x000000001fe00000
-#define PI_ERR_ST1_TOUTCNT_SHFT        21
+#define PI_ERR_ST1_TOUTCNT_MASK 0x000000001fe00000
+#define PI_ERR_ST1_TOUTCNT_SHFT 21

 #define PI_ERR_ST1_INVCNT_MASK 0x0000007fe0000000
 #define PI_ERR_ST1_INVCNT_SHFT 29
 #define PI_ERR_ST1_CRBNUM_MASK 0x0000038000000000
 #define PI_ERR_ST1_CRBNUM_SHFT 39
 #define PI_ERR_ST1_WRBRRB_MASK 0x0000040000000000
 #define PI_ERR_ST1_WRBRRB_SHFT 42
 #define PI_ERR_ST1_INVCNT_MASK 0x0000007fe0000000
 #define PI_ERR_ST1_INVCNT_SHFT 29
 #define PI_ERR_ST1_CRBNUM_MASK 0x0000038000000000
 #define PI_ERR_ST1_CRBNUM_SHFT 39
 #define PI_ERR_ST1_WRBRRB_MASK 0x0000040000000000
 #define PI_ERR_ST1_WRBRRB_SHFT 42

-#define PI_ERR_ST1_CRBSTAT_MASK        0x001ff80000000000
-#define PI_ERR_ST1_CRBSTAT_SHFT        43
+#define PI_ERR_ST1_CRBSTAT_MASK 0x001ff80000000000
+#define PI_ERR_ST1_CRBSTAT_SHFT 43

 #define PI_ERR_ST1_MSGSRC_MASK 0xffe0000000000000
 #define PI_ERR_ST1_MSGSRC_SHFT 53
 
 #define PI_ERR_ST1_MSGSRC_MASK 0xffe0000000000000
 #define PI_ERR_ST1_MSGSRC_SHFT 53
 


@@ -274,8 +274,8 @@
 #define PI_ERR_STK_CRBNUM_SHFT 9
 #define PI_ERR_STK_WRBRRB_MASK 0x0000000000001000
 #define PI_ERR_STK_WRBRRB_SHFT 12
 #define PI_ERR_STK_CRBNUM_SHFT 9
 #define PI_ERR_STK_WRBRRB_MASK 0x0000000000001000
 #define PI_ERR_STK_WRBRRB_SHFT 12

-#define PI_ERR_STK_CRBSTAT_MASK        0x00000000007fe000
-#define PI_ERR_STK_CRBSTAT_SHFT        13
+#define PI_ERR_STK_CRBSTAT_MASK 0x00000000007fe000
+#define PI_ERR_STK_CRBSTAT_SHFT 13

 #define PI_ERR_STK_CMD_MASK    0x000000007f800000
 #define PI_ERR_STK_CMD_SHFT    23
 #define PI_ERR_STK_ADDR_MASK   0xffffffff80000000
 #define PI_ERR_STK_CMD_MASK    0x000000007f800000
 #define PI_ERR_STK_CMD_SHFT    23
 #define PI_ERR_STK_ADDR_MASK   0xffffffff80000000


@@ -364,11 +364,11 @@ typedef u64       rtc_time_t;
 
 /* Bits in PI_SYSAD_ERRCHK_EN */
 #define PI_SYSAD_ERRCHK_ECCGEN 0x01    /* Enable ECC generation            */
 
 /* Bits in PI_SYSAD_ERRCHK_EN */
 #define PI_SYSAD_ERRCHK_ECCGEN 0x01    /* Enable ECC generation            */

-#define PI_SYSAD_ERRCHK_QUALGEN        0x02    /* Enable data quality signal gen.  */
-#define PI_SYSAD_ERRCHK_SADP   0x04    /* Enable SysAD parity checking     */
+#define PI_SYSAD_ERRCHK_QUALGEN 0x02   /* Enable data quality signal gen.  */
+#define PI_SYSAD_ERRCHK_SADP   0x04    /* Enable SysAD parity checking     */

 #define PI_SYSAD_ERRCHK_CMDP   0x08    /* Enable SysCmd parity checking    */
 #define PI_SYSAD_ERRCHK_STATE  0x10    /* Enable SysState parity checking  */
 #define PI_SYSAD_ERRCHK_CMDP   0x08    /* Enable SysCmd parity checking    */
 #define PI_SYSAD_ERRCHK_STATE  0x10    /* Enable SysState parity checking  */

-#define PI_SYSAD_ERRCHK_QUAL   0x20    /* Enable data quality checking     */
+#define PI_SYSAD_ERRCHK_QUAL   0x20    /* Enable data quality checking     */

 #define PI_SYSAD_CHECK_ALL     0x3f    /* Generate and check all signals.  */
 
 /* Interrupt pending bits on R10000 */
 #define PI_SYSAD_CHECK_ALL     0x3f    /* Generate and check all signals.  */
 
 /* Interrupt pending bits on R10000 */

diff --git a/arch/mips/include/asm/sn/sn0/ip27.h b/arch/mips/include/asm/sn/sn0/ip27.h
index 3c97e0855c8d69a724643ed8a9d3f28eb193395e..3b5efeefcc3f6d8d793bcc7a4da5d140e8115033 100644 (file)
--- a/arch/mips/include/asm/sn/sn0/ip27.h
+++ b/arch/mips/include/asm/sn/sn0/ip27.h
@@ -21,14 +21,14 @@
 
 #ifndef __ASSEMBLY__
 
 
 #ifndef __ASSEMBLY__
 

-#define CAUSE_BERRINTR                 IE_IRQ5
+#define CAUSE_BERRINTR         IE_IRQ5

 
 

-#define ECCF_CACHE_ERR  0
-#define ECCF_TAGLO      1
-#define ECCF_ECC        2
-#define ECCF_ERROREPC   3
-#define ECCF_PADDR      4
-#define ECCF_SIZE       (5 * sizeof(long))
+#define ECCF_CACHE_ERR 0
+#define ECCF_TAGLO     1
+#define ECCF_ECC       2
+#define ECCF_ERROREPC  3
+#define ECCF_PADDR     4
+#define ECCF_SIZE      (5 * sizeof(long))

 
 #endif /* !__ASSEMBLY__ */
 
 
 #endif /* !__ASSEMBLY__ */
 


@@ -39,8 +39,8 @@
  * the processor number of the calling processor.  The proc parameters
  * must be a register.
  */
  * the processor number of the calling processor.  The proc parameters
  * must be a register.
  */

-#define KL_GET_CPUNUM(proc)                            \
-       dli     proc, LOCAL_HUB(0);                     \
+#define KL_GET_CPUNUM(proc)                            \
+       dli     proc, LOCAL_HUB(0);                     \

        ld      proc, PI_CPU_NUM(proc)
 
 #endif /* __ASSEMBLY__ */
        ld      proc, PI_CPU_NUM(proc)
 
 #endif /* __ASSEMBLY__ */


@@ -71,15 +71,15 @@
 
 #define NUM_CAUSE_INTRS                8
 
 
 #define NUM_CAUSE_INTRS                8
 

-#define SCACHE_LINESIZE        128
-#define SCACHE_LINEMASK        (SCACHE_LINESIZE - 1)
+#define SCACHE_LINESIZE 128
+#define SCACHE_LINEMASK (SCACHE_LINESIZE - 1)

 
 #include <asm/sn/addrs.h>
 
 
 #include <asm/sn/addrs.h>
 

-#define LED_CYCLE_MASK  0x0f
-#define LED_CYCLE_SHFT  4
+#define LED_CYCLE_MASK 0x0f
+#define LED_CYCLE_SHFT 4

 
 #define SEND_NMI(_nasid, _slice)       \
 
 #define SEND_NMI(_nasid, _slice)       \

-          REMOTE_HUB_S((_nasid),  (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1)
+         REMOTE_HUB_S((_nasid),  (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1)

 
 #endif /* _ASM_SN_SN0_IP27_H */
 
 #endif /* _ASM_SN_SN0_IP27_H */

diff --git a/arch/mips/include/asm/sn/types.h b/arch/mips/include/asm/sn/types.h
index 74d0bb260b86d2068b2c730d1d1d918a4c49a8a9..c4813d67aec3f5543272a53e1d87e9a1b202e193 100644 (file)
--- a/arch/mips/include/asm/sn/types.h
+++ b/arch/mips/include/asm/sn/types.h
@@ -11,7 +11,7 @@
 
 #include <linux/types.h>
 
 
 #include <linux/types.h>
 

-typedef unsigned long  cpuid_t;
+typedef unsigned long  cpuid_t;

 typedef unsigned long  cnodemask_t;
 typedef signed short   nasid_t;        /* node id in numa-as-id space */
 typedef signed short   cnodeid_t;      /* node id in compact-id space */
 typedef unsigned long  cnodemask_t;
 typedef signed short   nasid_t;        /* node id in numa-as-id space */
 typedef signed short   cnodeid_t;      /* node id in compact-id space */


@@ -19,7 +19,7 @@ typedef signed char   partid_t;       /* partition ID type */
 typedef signed short   moduleid_t;     /* user-visible module number type */
 typedef signed short   cmoduleid_t;    /* kernel compact module id type */
 typedef unsigned char  clusterid_t;    /* Clusterid of the cell */
 typedef signed short   moduleid_t;     /* user-visible module number type */
 typedef signed short   cmoduleid_t;    /* kernel compact module id type */
 typedef unsigned char  clusterid_t;    /* Clusterid of the cell */

-typedef unsigned long  pfn_t;
+typedef unsigned long  pfn_t;

 
 typedef dev_t          vertex_hdl_t;   /* hardware graph vertex handle */
 
 
 typedef dev_t          vertex_hdl_t;   /* hardware graph vertex handle */
 

diff --git a/arch/mips/include/asm/sni.h b/arch/mips/include/asm/sni.h
index 8c1eb02c6d16fdd66a3945358d78a9f0d4d909ba..a107201a2e1e21bfd064ed018610e68f4b816de5 100644 (file)
--- a/arch/mips/include/asm/sni.h
+++ b/arch/mips/include/asm/sni.h
@@ -13,27 +13,27 @@
 
 extern unsigned int sni_brd_type;
 
 
 extern unsigned int sni_brd_type;
 

-#define SNI_BRD_10                 2
-#define SNI_BRD_10NEW              3
-#define SNI_BRD_TOWER_OASIC        4
-#define SNI_BRD_MINITOWER          5
-#define SNI_BRD_PCI_TOWER          6
-#define SNI_BRD_RM200              7
-#define SNI_BRD_PCI_MTOWER         8
-#define SNI_BRD_PCI_DESKTOP        9
-#define SNI_BRD_PCI_TOWER_CPLUS   10
+#define SNI_BRD_10                2
+#define SNI_BRD_10NEW             3
+#define SNI_BRD_TOWER_OASIC       4
+#define SNI_BRD_MINITOWER         5
+#define SNI_BRD_PCI_TOWER         6
+#define SNI_BRD_RM200             7
+#define SNI_BRD_PCI_MTOWER        8
+#define SNI_BRD_PCI_DESKTOP       9
+#define SNI_BRD_PCI_TOWER_CPLUS          10

 #define SNI_BRD_PCI_MTOWER_CPLUS  11
 
 /* RM400 cpu types */
 #define SNI_BRD_PCI_MTOWER_CPLUS  11
 
 /* RM400 cpu types */

-#define SNI_CPU_M8021           0x01
-#define SNI_CPU_M8030           0x04
-#define SNI_CPU_M8031           0x06
-#define SNI_CPU_M8034           0x0f
-#define SNI_CPU_M8037           0x07
-#define SNI_CPU_M8040           0x05
-#define SNI_CPU_M8043           0x09
-#define SNI_CPU_M8050           0x0b
-#define SNI_CPU_M8053           0x0d
+#define SNI_CPU_M8021          0x01
+#define SNI_CPU_M8030          0x04
+#define SNI_CPU_M8031          0x06
+#define SNI_CPU_M8034          0x0f
+#define SNI_CPU_M8037          0x07
+#define SNI_CPU_M8040          0x05
+#define SNI_CPU_M8043          0x09
+#define SNI_CPU_M8050          0x0b
+#define SNI_CPU_M8053          0x0d

 
 #define SNI_PORT_BASE          CKSEG1ADDR(0xb4000000)
 
 
 #define SNI_PORT_BASE          CKSEG1ADDR(0xb4000000)
 


@@ -52,14 +52,14 @@ extern unsigned int sni_brd_type;
 #define PCIMT_ERRADDR          CKSEG1ADDR(0xbfff0044)
 #define PCIMT_SYNDROME         CKSEG1ADDR(0xbfff004c)
 #define PCIMT_ITPEND           CKSEG1ADDR(0xbfff0054)
 #define PCIMT_ERRADDR          CKSEG1ADDR(0xbfff0044)
 #define PCIMT_SYNDROME         CKSEG1ADDR(0xbfff004c)
 #define PCIMT_ITPEND           CKSEG1ADDR(0xbfff0054)

-#define  IT_INT2               0x01
-#define  IT_INTD               0x02
-#define  IT_INTC               0x04
-#define  IT_INTB               0x08
-#define  IT_INTA               0x10
-#define  IT_EISA               0x20
-#define  IT_SCSI               0x40
-#define  IT_ETH                        0x80
+#define         IT_INT2                0x01
+#define         IT_INTD                0x02
+#define         IT_INTC                0x04
+#define         IT_INTB                0x08
+#define         IT_INTA                0x10
+#define         IT_EISA                0x20
+#define         IT_SCSI                0x40
+#define         IT_ETH                 0x80

 #define PCIMT_IRQSEL           CKSEG1ADDR(0xbfff005c)
 #define PCIMT_TESTMEM          CKSEG1ADDR(0xbfff0064)
 #define PCIMT_ECCREG           CKSEG1ADDR(0xbfff006c)
 #define PCIMT_IRQSEL           CKSEG1ADDR(0xbfff005c)
 #define PCIMT_TESTMEM          CKSEG1ADDR(0xbfff0064)
 #define PCIMT_ECCREG           CKSEG1ADDR(0xbfff006c)


@@ -86,14 +86,14 @@ extern unsigned int sni_brd_type;
 #define PCIMT_ERRADDR          CKSEG1ADDR(0xbfff0040)
 #define PCIMT_SYNDROME         CKSEG1ADDR(0xbfff0048)
 #define PCIMT_ITPEND           CKSEG1ADDR(0xbfff0050)
 #define PCIMT_ERRADDR          CKSEG1ADDR(0xbfff0040)
 #define PCIMT_SYNDROME         CKSEG1ADDR(0xbfff0048)
 #define PCIMT_ITPEND           CKSEG1ADDR(0xbfff0050)

-#define  IT_INT2               0x01
-#define  IT_INTD               0x02
-#define  IT_INTC               0x04
-#define  IT_INTB               0x08
-#define  IT_INTA               0x10
-#define  IT_EISA               0x20
-#define  IT_SCSI               0x40
-#define  IT_ETH                        0x80
+#define         IT_INT2                0x01
+#define         IT_INTD                0x02
+#define         IT_INTC                0x04
+#define         IT_INTB                0x08
+#define         IT_INTA                0x10
+#define         IT_EISA                0x20
+#define         IT_SCSI                0x40
+#define         IT_ETH                 0x80

 #define PCIMT_IRQSEL           CKSEG1ADDR(0xbfff0058)
 #define PCIMT_TESTMEM          CKSEG1ADDR(0xbfff0060)
 #define PCIMT_ECCREG           CKSEG1ADDR(0xbfff0068)
 #define PCIMT_IRQSEL           CKSEG1ADDR(0xbfff0058)
 #define PCIMT_TESTMEM          CKSEG1ADDR(0xbfff0060)
 #define PCIMT_ECCREG           CKSEG1ADDR(0xbfff0068)


@@ -137,29 +137,29 @@ extern unsigned int sni_brd_type;
 /*
  * A20R based boards
  */
 /*
  * A20R based boards
  */

-#define A20R_PT_CLOCK_BASE      CKSEG1ADDR(0xbc040000)
-#define A20R_PT_TIM0_ACK        CKSEG1ADDR(0xbc050000)
-#define A20R_PT_TIM1_ACK        CKSEG1ADDR(0xbc060000)
+#define A20R_PT_CLOCK_BASE     CKSEG1ADDR(0xbc040000)
+#define A20R_PT_TIM0_ACK       CKSEG1ADDR(0xbc050000)
+#define A20R_PT_TIM1_ACK       CKSEG1ADDR(0xbc060000)

 
 

-#define SNI_A20R_IRQ_BASE       MIPS_CPU_IRQ_BASE
-#define SNI_A20R_IRQ_TIMER      (SNI_A20R_IRQ_BASE+5)
+#define SNI_A20R_IRQ_BASE      MIPS_CPU_IRQ_BASE
+#define SNI_A20R_IRQ_TIMER     (SNI_A20R_IRQ_BASE+5)

 
 

-#define SNI_PCIT_INT_REG        CKSEG1ADDR(0xbfff000c)
+#define SNI_PCIT_INT_REG       CKSEG1ADDR(0xbfff000c)

 
 

-#define SNI_PCIT_INT_START      24
-#define SNI_PCIT_INT_END        30
+#define SNI_PCIT_INT_START     24
+#define SNI_PCIT_INT_END       30

 
 

-#define PCIT_IRQ_ETHERNET       (MIPS_CPU_IRQ_BASE + 5)
-#define PCIT_IRQ_INTA           (SNI_PCIT_INT_START + 0)
-#define PCIT_IRQ_INTB           (SNI_PCIT_INT_START + 1)
-#define PCIT_IRQ_INTC           (SNI_PCIT_INT_START + 2)
-#define PCIT_IRQ_INTD           (SNI_PCIT_INT_START + 3)
-#define PCIT_IRQ_SCSI0          (SNI_PCIT_INT_START + 4)
-#define PCIT_IRQ_SCSI1          (SNI_PCIT_INT_START + 5)
+#define PCIT_IRQ_ETHERNET      (MIPS_CPU_IRQ_BASE + 5)
+#define PCIT_IRQ_INTA          (SNI_PCIT_INT_START + 0)
+#define PCIT_IRQ_INTB          (SNI_PCIT_INT_START + 1)
+#define PCIT_IRQ_INTC          (SNI_PCIT_INT_START + 2)
+#define PCIT_IRQ_INTD          (SNI_PCIT_INT_START + 3)
+#define PCIT_IRQ_SCSI0         (SNI_PCIT_INT_START + 4)
+#define PCIT_IRQ_SCSI1         (SNI_PCIT_INT_START + 5)

 
 
 /*
 
 
 /*

- * Interrupt 0-16 are EISA interrupts.  Interrupts from 16 on are assigned
+ * Interrupt 0-16 are EISA interrupts. Interrupts from 16 on are assigned

  * to the other interrupts generated by ASIC PCI.
  *
  * INT2 is a wired-or of the push button interrupt, high temperature interrupt
  * to the other interrupts generated by ASIC PCI.
  *
  * INT2 is a wired-or of the push button interrupt, high temperature interrupt


@@ -204,12 +204,12 @@ extern unsigned int sni_brd_type;
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 #define __SNI_END 3
 #endif
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 #define __SNI_END 3
 #endif

-#define SNI_IDPROM_BASE        CKSEG1ADDR(0x1ff00000)
+#define SNI_IDPROM_BASE               CKSEG1ADDR(0x1ff00000)

 #define SNI_IDPROM_MEMSIZE     (SNI_IDPROM_BASE + (0x28 ^ __SNI_END))
 #define SNI_IDPROM_BRDTYPE     (SNI_IDPROM_BASE + (0x29 ^ __SNI_END))
 #define SNI_IDPROM_CPUTYPE     (SNI_IDPROM_BASE + (0x30 ^ __SNI_END))
 
 #define SNI_IDPROM_MEMSIZE     (SNI_IDPROM_BASE + (0x28 ^ __SNI_END))
 #define SNI_IDPROM_BRDTYPE     (SNI_IDPROM_BASE + (0x29 ^ __SNI_END))
 #define SNI_IDPROM_CPUTYPE     (SNI_IDPROM_BASE + (0x30 ^ __SNI_END))
 

-#define SNI_IDPROM_SIZE        0x1000
+#define SNI_IDPROM_SIZE 0x1000

 
 /* board specific init functions */
 extern void sni_a20r_init(void);
 
 /* board specific init functions */
 extern void sni_a20r_init(void);

diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h
index 65900dab3ad382825143d66d7f206f93d561e34d..d2da53c2c2f8eaf2419e7cc41ad33192b15dc60c 100644 (file)
--- a/arch/mips/include/asm/sparsemem.h
+++ b/arch/mips/include/asm/sparsemem.h
@@ -11,7 +11,7 @@
 #else
 # define SECTION_SIZE_BITS     28
 #endif
 #else
 # define SECTION_SIZE_BITS     28
 #endif

-#define MAX_PHYSMEM_BITS        35
+#define MAX_PHYSMEM_BITS       35

 
 #endif /* CONFIG_SPARSEMEM */
 #endif /* _MIPS_SPARSEMEM_H */
 
 #endif /* CONFIG_SPARSEMEM */
 #endif /* _MIPS_SPARSEMEM_H */

diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index ca61e846ab0f479406531a0996e14c623505705e..5130c88d64204b398be70c968823d408bb27f93c 100644 (file)
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -17,7 +17,7 @@
 /*
  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  *
 /*
  * Your basic SMP spinlocks, allowing only a single CPU anywhere
  *

- * Simple spin lock operations.  There are two variants, one clears IRQ's
+ * Simple spin lock operations.         There are two variants, one clears IRQ's

  * on the local processor, one does not.
  *
  * These are fair FIFO ticket locks
  * on the local processor, one does not.
  *
  * These are fair FIFO ticket locks


@@ -222,7 +222,7 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock)
  * write_can_lock - would write_trylock() succeed?
  * @lock: the rwlock in question.
  */
  * write_can_lock - would write_trylock() succeed?
  * @lock: the rwlock in question.
  */

-#define arch_write_can_lock(rw)        (!(rw)->lock)
+#define arch_write_can_lock(rw) (!(rw)->lock)

 
 static inline void arch_read_lock(arch_rwlock_t *rw)
 {
 
 static inline void arch_read_lock(arch_rwlock_t *rw)
 {

diff --git a/arch/mips/include/asm/spinlock_types.h b/arch/mips/include/asm/spinlock_types.h
index c52f36013a9da4e77b7307ca61b233be10ad974b..9b2528e612c0c35d64a6c2a2779fc38b78bcaf5e 100644 (file)
--- a/arch/mips/include/asm/spinlock_types.h
+++ b/arch/mips/include/asm/spinlock_types.h
@@ -11,7 +11,7 @@
 
 typedef union {
        /*
 
 typedef union {
        /*

-        * bits  0..15 : serving_now
+        * bits  0..15 : serving_now

         * bits 16..31 : ticket
         */
        u32 lock;
         * bits 16..31 : ticket
         */
        u32 lock;

diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index cb41af5f3406cbddc91e23633463fe6a3b65e769..c99384018161ec77fe54e72f1ae851b2b04c8ac3 100644 (file)
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -218,17 +218,17 @@
                ori     $28, sp, _THREAD_MASK
                xori    $28, _THREAD_MASK
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
                ori     $28, sp, _THREAD_MASK
                xori    $28, _THREAD_MASK
 #ifdef CONFIG_CPU_CAVIUM_OCTEON

-               .set    mips64
-               pref    0, 0($28)       /* Prefetch the current pointer */
-               pref    0, PT_R31(sp)   /* Prefetch the $31(ra) */
+               .set    mips64
+               pref    0, 0($28)       /* Prefetch the current pointer */
+               pref    0, PT_R31(sp)   /* Prefetch the $31(ra) */

                /* The Octeon multiplier state is affected by general multiply
                    instructions. It must be saved before and kernel code might
                    corrupt it */
                /* The Octeon multiplier state is affected by general multiply
                    instructions. It must be saved before and kernel code might
                    corrupt it */

-               jal     octeon_mult_save
-               LONG_L  v1, 0($28)  /* Load the current pointer */
+               jal     octeon_mult_save
+               LONG_L  v1, 0($28)  /* Load the current pointer */

                         /* Restore $31(ra) that was changed by the jal */
                         /* Restore $31(ra) that was changed by the jal */

-               LONG_L  ra, PT_R31(sp)
-               pref    0, 0(v1)    /* Prefetch the current thread */
+               LONG_L  ra, PT_R31(sp)
+               pref    0, 0(v1)    /* Prefetch the current thread */

 #endif
                .set    pop
                .endm
 #endif
                .set    pop
                .endm

diff --git a/arch/mips/include/asm/string.h b/arch/mips/include/asm/string.h
index 436e3ad352d95e78d8d9a24d72043fee0c087366..29030cb398ee5d3a9e8b9ee3962c4bd09af01252 100644 (file)
--- a/arch/mips/include/asm/string.h
+++ b/arch/mips/include/asm/string.h
@@ -35,7 +35,7 @@ static __inline__ char *strcpy(char *__dest, __const__ char *__src)
        ".set\tat\n\t"
        ".set\treorder"
        : "=r" (__dest), "=r" (__src)
        ".set\tat\n\t"
        ".set\treorder"
        : "=r" (__dest), "=r" (__src)

-        : "0" (__dest), "1" (__src)
+       : "0" (__dest), "1" (__src)

        : "memory");
 
   return __xdest;
        : "memory");
 
   return __xdest;


@@ -62,9 +62,9 @@ static __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n)
        "2:\n\t"
        ".set\tat\n\t"
        ".set\treorder"
        "2:\n\t"
        ".set\tat\n\t"
        ".set\treorder"

-        : "=r" (__dest), "=r" (__src), "=r" (__n)
-        : "0" (__dest), "1" (__src), "2" (__n)
-        : "memory");
+       : "=r" (__dest), "=r" (__src), "=r" (__n)
+       : "0" (__dest), "1" (__src), "2" (__n)
+       : "memory");

 
   return __xdest;
 }
 
   return __xdest;
 }

diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h
index 4f8ddba8c360050703d6d760b5909e92944e8b23..fd16bcb6c31111d34009b60fce8db7a1edff472a 100644 (file)
--- a/arch/mips/include/asm/switch_to.h
+++ b/arch/mips/include/asm/switch_to.h
@@ -30,7 +30,7 @@ extern struct task_struct *ll_task;
 #ifdef CONFIG_MIPS_MT_FPAFF
 
 /*
 #ifdef CONFIG_MIPS_MT_FPAFF
 
 /*

- * Handle the scheduler resume end of FPU affinity management.  We do this
+ * Handle the scheduler resume end of FPU affinity management. We do this

  * inline to try to keep the overhead down. If we have been forced to run on
  * a "CPU" with an FPU because of a previous high level of FP computation,
  * but did not actually use the FPU during the most recent time-slice (CU1
  * inline to try to keep the overhead down. If we have been forced to run on
  * a "CPU" with an FPU because of a previous high level of FP computation,
  * but did not actually use the FPU during the most recent time-slice (CU1


@@ -72,7 +72,7 @@ do {                                                                  \
                __save_dsp(prev);                                       \
        __clear_software_ll_bit();                                      \
        __usedfpu = test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU);  \
                __save_dsp(prev);                                       \
        __clear_software_ll_bit();                                      \
        __usedfpu = test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU);  \

-       (last) = resume(prev, next, task_thread_info(next), __usedfpu); \
+       (last) = resume(prev, next, task_thread_info(next), __usedfpu); \

 } while (0)
 
 #define finish_arch_switch(prev)                                       \
 } while (0)
 
 #define finish_arch_switch(prev)                                       \

diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index b2050b9e64b1702c6596553276626a7cd7fc09c4..178f7924149ad4b5e06ff4aa1a1db868734a10d8 100644 (file)
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -44,7 +44,7 @@ struct thread_info {
 #define INIT_THREAD_INFO(tsk)                  \
 {                                              \
        .task           = &tsk,                 \
 #define INIT_THREAD_INFO(tsk)                  \
 {                                              \
        .task           = &tsk,                 \

-       .exec_domain    = &default_exec_domain, \
+       .exec_domain    = &default_exec_domain, \

        .flags          = _TIF_FIXADE,          \
        .cpu            = 0,                    \
        .preempt_count  = INIT_PREEMPT_COUNT,   \
        .flags          = _TIF_FIXADE,          \
        .cpu            = 0,                    \
        .preempt_count  = INIT_PREEMPT_COUNT,   \

diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index 761f2e92119ea5945027ad173476982df2d89329..96353075cc60ab3ef8600ae0723ac153a51e0ab4 100644 (file)
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -6,8 +6,8 @@
  * include/asm-mips/time.h
  *     header file for the new style time.c file and time services.
  *
  * include/asm-mips/time.h
  *     header file for the new style time.c file and time services.
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/include/asm/tlb.h b/arch/mips/include/asm/tlb.h
index 80d9dfcf1e88ed9d0567aef1a273b26433a8a53b..c67842bc8ef3831c42c59ed42235f5bf999a8ead 100644 (file)
--- a/arch/mips/include/asm/tlb.h
+++ b/arch/mips/include/asm/tlb.h
@@ -5,7 +5,7 @@
  * MIPS doesn't need any special per-pte or per-vma handling, except
  * we need to flush cache for area to be unmapped.
  */
  * MIPS doesn't need any special per-pte or per-vma handling, except
  * we need to flush cache for area to be unmapped.
  */

-#define tlb_start_vma(tlb, vma)                                \
+#define tlb_start_vma(tlb, vma)                                        \

        do {                                                    \
                if (!tlb->fullmm)                               \
                        flush_cache_range(vma, vma->vm_start, vma->vm_end); \
        do {                                                    \
                if (!tlb->fullmm)                               \
                        flush_cache_range(vma, vma->vm_start, vma->vm_end); \

diff --git a/arch/mips/include/asm/topology.h b/arch/mips/include/asm/topology.h
index 259145e07e9724a2e1bcd22e3ed9ee52a8f9580c..12609a17dc8b5893faacf8df47b954b10a140664 100644 (file)
--- a/arch/mips/include/asm/topology.h
+++ b/arch/mips/include/asm/topology.h
@@ -11,7 +11,7 @@
 #include <topology.h>
 
 #ifdef CONFIG_SMP
 #include <topology.h>
 
 #ifdef CONFIG_SMP

-#define smt_capable()   (smp_num_siblings > 1)
+#define smt_capable()  (smp_num_siblings > 1)

 #endif
 
 #endif /* __ASM_TOPOLOGY_H */
 #endif
 
 #endif /* __ASM_TOPOLOGY_H */

diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h
index 420ca06b2f42df601e8fcfbd5f148626f2df225d..f41cf3ee82a7d2553358a5d1acfd97814325ab64 100644 (file)
--- a/arch/mips/include/asm/traps.h
+++ b/arch/mips/include/asm/traps.h
@@ -14,7 +14,7 @@
 /*
  * Possible status responses for a board_be_handler backend.
  */
 /*
  * Possible status responses for a board_be_handler backend.
  */

-#define MIPS_BE_DISCARD        0               /* return with no action */
+#define MIPS_BE_DISCARD 0              /* return with no action */

 #define MIPS_BE_FIXUP  1               /* return to the fixup code */
 #define MIPS_BE_FATAL  2               /* treat as an unrecoverable error */
 
 #define MIPS_BE_FIXUP  1               /* return to the fixup code */
 #define MIPS_BE_FATAL  2               /* treat as an unrecoverable error */
 

diff --git a/arch/mips/include/asm/txx9/jmr3927.h b/arch/mips/include/asm/txx9/jmr3927.h
index 8808d7f82da022a7cde69f52900699c65739d3db..aab959dc30baff5cfc7dfbacee98cf5cef32e5a7 100644 (file)
--- a/arch/mips/include/asm/txx9/jmr3927.h
+++ b/arch/mips/include/asm/txx9/jmr3927.h
@@ -40,7 +40,7 @@
 #define JMR3927_PCIIO_BASE     (KSEG1 + JMR3927_PCIIO)
 
 #define JMR3927_IOC_REV_ADDR   (JMR3927_IOC_BASE + 0x00000000)
 #define JMR3927_PCIIO_BASE     (KSEG1 + JMR3927_PCIIO)
 
 #define JMR3927_IOC_REV_ADDR   (JMR3927_IOC_BASE + 0x00000000)

-#define JMR3927_IOC_NVRAMB_ADDR        (JMR3927_IOC_BASE + 0x00010000)
+#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000)

 #define JMR3927_IOC_LED_ADDR   (JMR3927_IOC_BASE + 0x00020000)
 #define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000)
 #define JMR3927_IOC_BREV_ADDR  (JMR3927_IOC_BASE + 0x00040000)
 #define JMR3927_IOC_LED_ADDR   (JMR3927_IOC_BASE + 0x00020000)
 #define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000)
 #define JMR3927_IOC_BREV_ADDR  (JMR3927_IOC_BASE + 0x00040000)


@@ -115,9 +115,9 @@
 #define JMR3927_NR_IRQ_IRC     16      /* On-Chip IRC */
 #define JMR3927_NR_IRQ_IOC     8       /* PCI/MODEM/INT[6:7] */
 
 #define JMR3927_NR_IRQ_IRC     16      /* On-Chip IRC */
 #define JMR3927_NR_IRQ_IOC     8       /* PCI/MODEM/INT[6:7] */
 

-#define JMR3927_IRQ_IRC        TXX9_IRQ_BASE
-#define JMR3927_IRQ_IOC        (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
-#define JMR3927_IRQ_END        (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
+#define JMR3927_IRQ_IRC TXX9_IRQ_BASE
+#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
+#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)

 
 #define JMR3927_IRQ_IRC_INT0   (JMR3927_IRQ_IRC + TX3927_IR_INT0)
 #define JMR3927_IRQ_IRC_INT1   (JMR3927_IRQ_IRC + TX3927_IR_INT1)
 
 #define JMR3927_IRQ_IRC_INT0   (JMR3927_IRQ_IRC + TX3927_IR_INT0)
 #define JMR3927_IRQ_IRC_INT1   (JMR3927_IRQ_IRC + TX3927_IR_INT1)


@@ -127,11 +127,11 @@
 #define JMR3927_IRQ_IRC_INT5   (JMR3927_IRQ_IRC + TX3927_IR_INT5)
 #define JMR3927_IRQ_IRC_SIO0   (JMR3927_IRQ_IRC + TX3927_IR_SIO0)
 #define JMR3927_IRQ_IRC_SIO1   (JMR3927_IRQ_IRC + TX3927_IR_SIO1)
 #define JMR3927_IRQ_IRC_INT5   (JMR3927_IRQ_IRC + TX3927_IR_INT5)
 #define JMR3927_IRQ_IRC_SIO0   (JMR3927_IRQ_IRC + TX3927_IR_SIO0)
 #define JMR3927_IRQ_IRC_SIO1   (JMR3927_IRQ_IRC + TX3927_IR_SIO1)

-#define JMR3927_IRQ_IRC_SIO(ch)        (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch))
+#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch))

 #define JMR3927_IRQ_IRC_DMA    (JMR3927_IRQ_IRC + TX3927_IR_DMA)
 #define JMR3927_IRQ_IRC_PIO    (JMR3927_IRQ_IRC + TX3927_IR_PIO)
 #define JMR3927_IRQ_IRC_PCI    (JMR3927_IRQ_IRC + TX3927_IR_PCI)
 #define JMR3927_IRQ_IRC_DMA    (JMR3927_IRQ_IRC + TX3927_IR_DMA)
 #define JMR3927_IRQ_IRC_PIO    (JMR3927_IRQ_IRC + TX3927_IR_PIO)
 #define JMR3927_IRQ_IRC_PCI    (JMR3927_IRQ_IRC + TX3927_IR_PCI)

-#define JMR3927_IRQ_IRC_TMR(ch)        (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch))
+#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch))

 #define JMR3927_IRQ_IOC_PCIA   (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
 #define JMR3927_IRQ_IOC_PCIB   (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
 #define JMR3927_IRQ_IOC_PCIC   (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
 #define JMR3927_IRQ_IOC_PCIA   (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
 #define JMR3927_IRQ_IOC_PCIB   (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
 #define JMR3927_IRQ_IOC_PCIC   (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)


@@ -147,7 +147,7 @@
 #define JMR3927_IRQ_ETHER0     JMR3927_IRQ_IRC_INT3
 
 /* Clocks */
 #define JMR3927_IRQ_ETHER0     JMR3927_IRQ_IRC_INT3
 
 /* Clocks */

-#define JMR3927_CORECLK        132710400       /* 132.7MHz */
+#define JMR3927_CORECLK 132710400      /* 132.7MHz */

 
 /*
  * TX3927 Pin Configuration:
 
 /*
  * TX3927 Pin Configuration:

diff --git a/arch/mips/include/asm/txx9/rbtx4927.h b/arch/mips/include/asm/txx9/rbtx4927.h
index b2adab3d1acceef690627a1feeff82338cc291ba..4060ad26ca99fc5fe2d47d70d4a724206596b745 100644 (file)
--- a/arch/mips/include/asm/txx9/rbtx4927.h
+++ b/arch/mips/include/asm/txx9/rbtx4927.h
@@ -1,6 +1,6 @@
 /*
  * Author: MontaVista Software, Inc.
 /*
  * Author: MontaVista Software, Inc.

- *         source@mvista.com
+ *        source@mvista.com

  *
  * Copyright 2001-2002 MontaVista Software Inc.
  *
  *
  * Copyright 2001-2002 MontaVista Software Inc.
  *


@@ -38,7 +38,7 @@
 #define RBTX4927_IMASK_ADDR    (IO_BASE + TXX9_CE(2) + 0x00002000)
 #define RBTX4927_IMSTAT_ADDR   (IO_BASE + TXX9_CE(2) + 0x00002006)
 #define RBTX4927_SOFTINT_ADDR  (IO_BASE + TXX9_CE(2) + 0x00003000)
 #define RBTX4927_IMASK_ADDR    (IO_BASE + TXX9_CE(2) + 0x00002000)
 #define RBTX4927_IMSTAT_ADDR   (IO_BASE + TXX9_CE(2) + 0x00002006)
 #define RBTX4927_SOFTINT_ADDR  (IO_BASE + TXX9_CE(2) + 0x00003000)

-#define RBTX4927_SOFTRESET_ADDR        (IO_BASE + TXX9_CE(2) + 0x0000f000)
+#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)

 #define RBTX4927_SOFTRESETLOCK_ADDR    (IO_BASE + TXX9_CE(2) + 0x0000f002)
 #define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006)
 #define RBTX4927_BRAMRTC_BASE  (IO_BASE + TXX9_CE(2) + 0x00010000)
 #define RBTX4927_SOFTRESETLOCK_ADDR    (IO_BASE + TXX9_CE(2) + 0x0000f002)
 #define RBTX4927_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f006)
 #define RBTX4927_BRAMRTC_BASE  (IO_BASE + TXX9_CE(2) + 0x00010000)


@@ -50,7 +50,7 @@
 #define rbtx4927_imask_addr    ((__u8 __iomem *)RBTX4927_IMASK_ADDR)
 #define rbtx4927_imstat_addr   ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR)
 #define rbtx4927_softint_addr  ((__u8 __iomem *)RBTX4927_SOFTINT_ADDR)
 #define rbtx4927_imask_addr    ((__u8 __iomem *)RBTX4927_IMASK_ADDR)
 #define rbtx4927_imstat_addr   ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR)
 #define rbtx4927_softint_addr  ((__u8 __iomem *)RBTX4927_SOFTINT_ADDR)

-#define rbtx4927_softreset_addr        ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR)
+#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR)

 #define rbtx4927_softresetlock_addr    \
                                ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR)
 #define rbtx4927_pcireset_addr ((__u8 __iomem *)RBTX4927_PCIRESET_ADDR)
 #define rbtx4927_softresetlock_addr    \
                                ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR)
 #define rbtx4927_pcireset_addr ((__u8 __iomem *)RBTX4927_PCIRESET_ADDR)

diff --git a/arch/mips/include/asm/txx9/rbtx4938.h b/arch/mips/include/asm/txx9/rbtx4938.h
index 9f0441a28126fc32d57309cdb6eb5fed168d8c2d..9c969dd3c6eb736343b504812a94fbf2d3d3f04a 100644 (file)
--- a/arch/mips/include/asm/txx9/rbtx4938.h
+++ b/arch/mips/include/asm/txx9/rbtx4938.h
@@ -36,7 +36,7 @@
 #define RBTX4938_SPICS_ADDR    (IO_BASE + TXX9_CE(2) + 0x00005002)
 #define RBTX4938_SFPWR_ADDR    (IO_BASE + TXX9_CE(2) + 0x00005008)
 #define RBTX4938_SFVOL_ADDR    (IO_BASE + TXX9_CE(2) + 0x0000500a)
 #define RBTX4938_SPICS_ADDR    (IO_BASE + TXX9_CE(2) + 0x00005002)
 #define RBTX4938_SFPWR_ADDR    (IO_BASE + TXX9_CE(2) + 0x00005008)
 #define RBTX4938_SFVOL_ADDR    (IO_BASE + TXX9_CE(2) + 0x0000500a)

-#define RBTX4938_SOFTRESET_ADDR        (IO_BASE + TXX9_CE(2) + 0x00007000)
+#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000)

 #define RBTX4938_SOFTRESETLOCK_ADDR    (IO_BASE + TXX9_CE(2) + 0x00007002)
 #define RBTX4938_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007004)
 #define RBTX4938_ETHER_BASE    (IO_BASE + TXX9_CE(2) + 0x00020000)
 #define RBTX4938_SOFTRESETLOCK_ADDR    (IO_BASE + TXX9_CE(2) + 0x00007002)
 #define RBTX4938_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007004)
 #define RBTX4938_ETHER_BASE    (IO_BASE + TXX9_CE(2) + 0x00020000)


@@ -78,7 +78,7 @@
 #define rbtx4938_spics_addr    ((__u8 __iomem *)RBTX4938_SPICS_ADDR)
 #define rbtx4938_sfpwr_addr    ((__u8 __iomem *)RBTX4938_SFPWR_ADDR)
 #define rbtx4938_sfvol_addr    ((__u8 __iomem *)RBTX4938_SFVOL_ADDR)
 #define rbtx4938_spics_addr    ((__u8 __iomem *)RBTX4938_SPICS_ADDR)
 #define rbtx4938_sfpwr_addr    ((__u8 __iomem *)RBTX4938_SFPWR_ADDR)
 #define rbtx4938_sfvol_addr    ((__u8 __iomem *)RBTX4938_SFVOL_ADDR)

-#define rbtx4938_softreset_addr        ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR)
+#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR)

 #define rbtx4938_softresetlock_addr    \
                                ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR)
 #define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR)
 #define rbtx4938_softresetlock_addr    \
                                ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR)
 #define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR)


@@ -94,7 +94,7 @@
 
 /* These are the virtual IRQ numbers, we divide all IRQ's into
  * 'spaces', the 'space' determines where and how to enable/disable
 
 /* These are the virtual IRQ numbers, we divide all IRQ's into
  * 'spaces', the 'space' determines where and how to enable/disable

- * that particular IRQ on an RBTX4938 machine.  Add new 'spaces' as new
+ * that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new

  * IRQ hardware is supported.
  */
 #define RBTX4938_NR_IRQ_IOC    8
  * IRQ hardware is supported.
  */
 #define RBTX4938_NR_IRQ_IOC    8


@@ -103,18 +103,18 @@
 #define RBTX4938_IRQ_IOC       (TXX9_IRQ_BASE + TX4938_NUM_IR)
 #define RBTX4938_IRQ_END       (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
 
 #define RBTX4938_IRQ_IOC       (TXX9_IRQ_BASE + TX4938_NUM_IR)
 #define RBTX4938_IRQ_END       (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
 

-#define RBTX4938_IRQ_IRC_ECCERR        (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
-#define RBTX4938_IRQ_IRC_WTOERR        (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
-#define RBTX4938_IRQ_IRC_INT(n)        (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
-#define RBTX4938_IRQ_IRC_SIO(n)        (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
+#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
+#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
+#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
+#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))

 #define RBTX4938_IRQ_IRC_DMA(ch, n)    (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n))
 #define RBTX4938_IRQ_IRC_PIO   (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
 #define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
 #define RBTX4938_IRQ_IRC_PCIC  (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
 #define RBTX4938_IRQ_IRC_DMA(ch, n)    (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n))
 #define RBTX4938_IRQ_IRC_PIO   (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
 #define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
 #define RBTX4938_IRQ_IRC_PCIC  (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)

-#define RBTX4938_IRQ_IRC_TMR(n)        (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
+#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))

 #define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC)
 #define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC)

-#define RBTX4938_IRQ_IRC_PCIERR        (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
-#define RBTX4938_IRQ_IRC_PCIPME        (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
+#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
+#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)

 #define RBTX4938_IRQ_IRC_ACLC  (RBTX4938_IRQ_IRC + TX4938_IR_ACLC)
 #define RBTX4938_IRQ_IRC_ACLCPME       (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME)
 #define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1)
 #define RBTX4938_IRQ_IRC_ACLC  (RBTX4938_IRQ_IRC + TX4938_IR_ACLC)
 #define RBTX4938_IRQ_IRC_ACLCPME       (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME)
 #define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1)

diff --git a/arch/mips/include/asm/txx9/rbtx4939.h b/arch/mips/include/asm/txx9/rbtx4939.h
index e517899794a8c6780b866d6b60ce24ee2e7e8669..6157bfd90848d2b2f2c235b3bf46a5047b0c32f4 100644 (file)
--- a/arch/mips/include/asm/txx9/rbtx4939.h
+++ b/arch/mips/include/asm/txx9/rbtx4939.h
@@ -17,7 +17,7 @@
 
 /* Address map */
 #define RBTX4939_IOC_REG_ADDR  (IO_BASE + TXX9_CE(1) + 0x00000000)
 
 /* Address map */
 #define RBTX4939_IOC_REG_ADDR  (IO_BASE + TXX9_CE(1) + 0x00000000)

-#define RBTX4939_BOARD_REV_ADDR        (IO_BASE + TXX9_CE(1) + 0x00000000)
+#define RBTX4939_BOARD_REV_ADDR (IO_BASE + TXX9_CE(1) + 0x00000000)

 #define RBTX4939_IOC_REV_ADDR  (IO_BASE + TXX9_CE(1) + 0x00000002)
 #define RBTX4939_CONFIG1_ADDR  (IO_BASE + TXX9_CE(1) + 0x00000004)
 #define RBTX4939_CONFIG2_ADDR  (IO_BASE + TXX9_CE(1) + 0x00000006)
 #define RBTX4939_IOC_REV_ADDR  (IO_BASE + TXX9_CE(1) + 0x00000002)
 #define RBTX4939_CONFIG1_ADDR  (IO_BASE + TXX9_CE(1) + 0x00000004)
 #define RBTX4939_CONFIG2_ADDR  (IO_BASE + TXX9_CE(1) + 0x00000006)


@@ -46,9 +46,9 @@
 #define RBTX4939_VPSIN_ADDR    (IO_BASE + TXX9_CE(1) + 0x0000500c)
 #define RBTX4939_7SEG_ADDR(s, ch)      \
        (IO_BASE + TXX9_CE(1) + 0x00006000 + (s) * 16 + ((ch) & 3) * 2)
 #define RBTX4939_VPSIN_ADDR    (IO_BASE + TXX9_CE(1) + 0x0000500c)
 #define RBTX4939_7SEG_ADDR(s, ch)      \
        (IO_BASE + TXX9_CE(1) + 0x00006000 + (s) * 16 + ((ch) & 3) * 2)

-#define RBTX4939_SOFTRESET_ADDR        (IO_BASE + TXX9_CE(1) + 0x00007000)
+#define RBTX4939_SOFTRESET_ADDR (IO_BASE + TXX9_CE(1) + 0x00007000)

 #define RBTX4939_RESETEN_ADDR  (IO_BASE + TXX9_CE(1) + 0x00007002)
 #define RBTX4939_RESETEN_ADDR  (IO_BASE + TXX9_CE(1) + 0x00007002)

-#define RBTX4939_RESETSTAT_ADDR        (IO_BASE + TXX9_CE(1) + 0x00007004)
+#define RBTX4939_RESETSTAT_ADDR (IO_BASE + TXX9_CE(1) + 0x00007004)

 #define RBTX4939_ETHER_BASE    (IO_BASE + TXX9_CE(1) + 0x00020000)
 
 /* Ethernet port address */
 #define RBTX4939_ETHER_BASE    (IO_BASE + TXX9_CE(1) + 0x00020000)
 
 /* Ethernet port address */


@@ -77,11 +77,11 @@
 #define RBTX4939_PE2_CIR       0x08
 #define RBTX4939_PE2_SPI       0x10
 #define RBTX4939_PE2_GPIO      0x20
 #define RBTX4939_PE2_CIR       0x08
 #define RBTX4939_PE2_SPI       0x10
 #define RBTX4939_PE2_GPIO      0x20

-#define RBTX4939_PE3_VP        0x01
+#define RBTX4939_PE3_VP 0x01

 #define RBTX4939_PE3_VP_P      0x02
 #define RBTX4939_PE3_VP_S      0x04
 
 #define RBTX4939_PE3_VP_P      0x02
 #define RBTX4939_PE3_VP_S      0x04
 

-#define rbtx4939_board_rev_addr        ((u8 __iomem *)RBTX4939_BOARD_REV_ADDR)
+#define rbtx4939_board_rev_addr ((u8 __iomem *)RBTX4939_BOARD_REV_ADDR)

 #define rbtx4939_ioc_rev_addr  ((u8 __iomem *)RBTX4939_IOC_REV_ADDR)
 #define rbtx4939_config1_addr  ((u8 __iomem *)RBTX4939_CONFIG1_ADDR)
 #define rbtx4939_config2_addr  ((u8 __iomem *)RBTX4939_CONFIG2_ADDR)
 #define rbtx4939_ioc_rev_addr  ((u8 __iomem *)RBTX4939_IOC_REV_ADDR)
 #define rbtx4939_config1_addr  ((u8 __iomem *)RBTX4939_CONFIG1_ADDR)
 #define rbtx4939_config2_addr  ((u8 __iomem *)RBTX4939_CONFIG2_ADDR)


@@ -110,9 +110,9 @@
 #define rbtx4939_vpsin_addr    ((u8 __iomem *)RBTX4939_VPSIN_ADDR)
 #define rbtx4939_7seg_addr(s, ch) \
                                ((u8 __iomem *)RBTX4939_7SEG_ADDR(s, ch))
 #define rbtx4939_vpsin_addr    ((u8 __iomem *)RBTX4939_VPSIN_ADDR)
 #define rbtx4939_7seg_addr(s, ch) \
                                ((u8 __iomem *)RBTX4939_7SEG_ADDR(s, ch))

-#define rbtx4939_softreset_addr        ((u8 __iomem *)RBTX4939_SOFTRESET_ADDR)
+#define rbtx4939_softreset_addr ((u8 __iomem *)RBTX4939_SOFTRESET_ADDR)

 #define rbtx4939_reseten_addr  ((u8 __iomem *)RBTX4939_RESETEN_ADDR)
 #define rbtx4939_reseten_addr  ((u8 __iomem *)RBTX4939_RESETEN_ADDR)

-#define rbtx4939_resetstat_addr        ((u8 __iomem *)RBTX4939_RESETSTAT_ADDR)
+#define rbtx4939_resetstat_addr ((u8 __iomem *)RBTX4939_RESETSTAT_ADDR)

 
 /*
  * IRQ mappings
 
 /*
  * IRQ mappings

diff --git a/arch/mips/include/asm/txx9/smsc_fdc37m81x.h b/arch/mips/include/asm/txx9/smsc_fdc37m81x.h
index d1d6332b4ca6092380830e8bd0fc083f550e8562..926d08f18463f0037646a4970968702fe79a4efd 100644 (file)
--- a/arch/mips/include/asm/txx9/smsc_fdc37m81x.h
+++ b/arch/mips/include/asm/txx9/smsc_fdc37m81x.h
@@ -18,43 +18,43 @@
 /* Common Registers */
 #define SMSC_FDC37M81X_CONFIG_INDEX  0x00
 #define SMSC_FDC37M81X_CONFIG_DATA   0x01
 /* Common Registers */
 #define SMSC_FDC37M81X_CONFIG_INDEX  0x00
 #define SMSC_FDC37M81X_CONFIG_DATA   0x01

-#define SMSC_FDC37M81X_CONF          0x02
-#define SMSC_FDC37M81X_INDEX         0x03
-#define SMSC_FDC37M81X_DNUM          0x07
-#define SMSC_FDC37M81X_DID           0x20
-#define SMSC_FDC37M81X_DREV          0x21
-#define SMSC_FDC37M81X_PCNT          0x22
-#define SMSC_FDC37M81X_PMGT          0x23
-#define SMSC_FDC37M81X_OSC           0x24
-#define SMSC_FDC37M81X_CONFPA0       0x26
-#define SMSC_FDC37M81X_CONFPA1       0x27
-#define SMSC_FDC37M81X_TEST4         0x2B
-#define SMSC_FDC37M81X_TEST5         0x2C
-#define SMSC_FDC37M81X_TEST1         0x2D
-#define SMSC_FDC37M81X_TEST2         0x2E
-#define SMSC_FDC37M81X_TEST3         0x2F
+#define SMSC_FDC37M81X_CONF         0x02
+#define SMSC_FDC37M81X_INDEX        0x03
+#define SMSC_FDC37M81X_DNUM         0x07
+#define SMSC_FDC37M81X_DID          0x20
+#define SMSC_FDC37M81X_DREV         0x21
+#define SMSC_FDC37M81X_PCNT         0x22
+#define SMSC_FDC37M81X_PMGT         0x23
+#define SMSC_FDC37M81X_OSC          0x24
+#define SMSC_FDC37M81X_CONFPA0      0x26
+#define SMSC_FDC37M81X_CONFPA1      0x27
+#define SMSC_FDC37M81X_TEST4        0x2B
+#define SMSC_FDC37M81X_TEST5        0x2C
+#define SMSC_FDC37M81X_TEST1        0x2D
+#define SMSC_FDC37M81X_TEST2        0x2E
+#define SMSC_FDC37M81X_TEST3        0x2F

 
 /* Logical device numbers */
 
 /* Logical device numbers */

-#define SMSC_FDC37M81X_FDD           0x00
-#define SMSC_FDC37M81X_PARALLEL      0x03
-#define SMSC_FDC37M81X_SERIAL1       0x04
-#define SMSC_FDC37M81X_SERIAL2       0x05
-#define SMSC_FDC37M81X_KBD           0x07
-#define SMSC_FDC37M81X_AUXIO         0x08
-#define SMSC_FDC37M81X_NONE          0xff
+#define SMSC_FDC37M81X_FDD          0x00
+#define SMSC_FDC37M81X_PARALLEL             0x03
+#define SMSC_FDC37M81X_SERIAL1      0x04
+#define SMSC_FDC37M81X_SERIAL2      0x05
+#define SMSC_FDC37M81X_KBD          0x07
+#define SMSC_FDC37M81X_AUXIO        0x08
+#define SMSC_FDC37M81X_NONE         0xff

 
 /* Logical device Config Registers */
 
 /* Logical device Config Registers */

-#define SMSC_FDC37M81X_ACTIVE        0x30
+#define SMSC_FDC37M81X_ACTIVE       0x30

 #define SMSC_FDC37M81X_BASEADDR0     0x60
 #define SMSC_FDC37M81X_BASEADDR1     0x61
 #define SMSC_FDC37M81X_BASEADDR0     0x60
 #define SMSC_FDC37M81X_BASEADDR1     0x61

-#define SMSC_FDC37M81X_INT           0x70
-#define SMSC_FDC37M81X_INT2          0x72
-#define SMSC_FDC37M81X_LDCR_F0       0xF0
+#define SMSC_FDC37M81X_INT          0x70
+#define SMSC_FDC37M81X_INT2         0x72
+#define SMSC_FDC37M81X_LDCR_F0      0xF0

 
 /* Chip Config Values */
 #define SMSC_FDC37M81X_CONFIG_ENTER  0x55
 #define SMSC_FDC37M81X_CONFIG_EXIT   0xaa
 
 /* Chip Config Values */
 #define SMSC_FDC37M81X_CONFIG_ENTER  0x55
 #define SMSC_FDC37M81X_CONFIG_EXIT   0xaa

-#define SMSC_FDC37M81X_CHIP_ID       0x4d
+#define SMSC_FDC37M81X_CHIP_ID      0x4d

 
 unsigned long smsc_fdc37m81x_init(unsigned long port);
 
 
 unsigned long smsc_fdc37m81x_init(unsigned long port);
 

diff --git a/arch/mips/include/asm/txx9/tx3927.h b/arch/mips/include/asm/txx9/tx3927.h
index dc30c8d420616b881a24740459dda18788aa3a34..149fab4f832768562048187ef328e74b94782131 100644 (file)
--- a/arch/mips/include/asm/txx9/tx3927.h
+++ b/arch/mips/include/asm/txx9/tx3927.h
@@ -8,8 +8,8 @@
 #ifndef __ASM_TXX9_TX3927_H
 #define __ASM_TXX9_TX3927_H
 
 #ifndef __ASM_TXX9_TX3927_H
 #define __ASM_TXX9_TX3927_H
 

-#define TX3927_REG_BASE        0xfffe0000UL
-#define TX3927_REG_SIZE        0x00010000
+#define TX3927_REG_BASE 0xfffe0000UL
+#define TX3927_REG_SIZE 0x00010000

 #define TX3927_SDRAMC_REG      (TX3927_REG_BASE + 0x8000)
 #define TX3927_ROMC_REG                (TX3927_REG_BASE + 0x9000)
 #define TX3927_DMA_REG         (TX3927_REG_BASE + 0xb000)
 #define TX3927_SDRAMC_REG      (TX3927_REG_BASE + 0x8000)
 #define TX3927_ROMC_REG                (TX3927_REG_BASE + 0x9000)
 #define TX3927_DMA_REG         (TX3927_REG_BASE + 0xb000)


@@ -191,8 +191,8 @@ struct tx3927_ccfg_reg {
 #define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2)
 #define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4)
 #define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5)
 #define TX3927_DMA_CCR_XFSZ_1W TX3927_DMA_CCR_XFSZ(2)
 #define TX3927_DMA_CCR_XFSZ_4W TX3927_DMA_CCR_XFSZ(4)
 #define TX3927_DMA_CCR_XFSZ_8W TX3927_DMA_CCR_XFSZ(5)

-#define TX3927_DMA_CCR_XFSZ_16W        TX3927_DMA_CCR_XFSZ(6)
-#define TX3927_DMA_CCR_XFSZ_32W        TX3927_DMA_CCR_XFSZ(7)
+#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
+#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)

 #define TX3927_DMA_CCR_MEMIO   0x00000002
 #define TX3927_DMA_CCR_ONEAD   0x00000001
 
 #define TX3927_DMA_CCR_MEMIO   0x00000002
 #define TX3927_DMA_CCR_ONEAD   0x00000001
 


@@ -250,7 +250,7 @@ struct tx3927_ccfg_reg {
 /* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
 
 /* bits for PBAPMC */
 /* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
 
 /* bits for PBAPMC */

-#define TX3927_PCIC_PBAPMC_RPBA        0x00000004
+#define TX3927_PCIC_PBAPMC_RPBA 0x00000004

 #define TX3927_PCIC_PBAPMC_PBAEN       0x00000002
 #define TX3927_PCIC_PBAPMC_BMCEN       0x00000001
 
 #define TX3927_PCIC_PBAPMC_PBAEN       0x00000002
 #define TX3927_PCIC_PBAPMC_BMCEN       0x00000001
 


@@ -282,7 +282,7 @@ struct tx3927_ccfg_reg {
 #define TX3927_CCFG_TLBOFF     0x00020000
 #define TX3927_CCFG_BEOW       0x00010000
 #define TX3927_CCFG_WR 0x00008000
 #define TX3927_CCFG_TLBOFF     0x00020000
 #define TX3927_CCFG_BEOW       0x00010000
 #define TX3927_CCFG_WR 0x00008000

-#define TX3927_CCFG_TOE        0x00004000
+#define TX3927_CCFG_TOE 0x00004000

 #define TX3927_CCFG_PCIXARB    0x00002000
 #define TX3927_CCFG_PCI3       0x00001000
 #define TX3927_CCFG_PSNP       0x00000800
 #define TX3927_CCFG_PCIXARB    0x00002000
 #define TX3927_CCFG_PCI3       0x00001000
 #define TX3927_CCFG_PSNP       0x00000800


@@ -301,8 +301,8 @@ struct tx3927_ccfg_reg {
 #define TX3927_PCFG_SELALL     0x0003ffff
 #define TX3927_PCFG_SELCS      0x00020000
 #define TX3927_PCFG_SELDSF     0x00010000
 #define TX3927_PCFG_SELALL     0x0003ffff
 #define TX3927_PCFG_SELCS      0x00020000
 #define TX3927_PCFG_SELDSF     0x00010000

-#define TX3927_PCFG_SELSIOC_ALL        0x0000c000
-#define TX3927_PCFG_SELSIOC(ch)        (0x00004000<<(ch))
+#define TX3927_PCFG_SELSIOC_ALL 0x0000c000
+#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))

 #define TX3927_PCFG_SELSIO_ALL 0x00003000
 #define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch))
 #define TX3927_PCFG_SELTMR_ALL 0x00000e00
 #define TX3927_PCFG_SELSIO_ALL 0x00003000
 #define TX3927_PCFG_SELSIO(ch) (0x00001000<<(ch))
 #define TX3927_PCFG_SELTMR_ALL 0x00000e00

diff --git a/arch/mips/include/asm/txx9/tx4927.h b/arch/mips/include/asm/txx9/tx4927.h
index 18c98c52afdb133ec8ea376f8bf35a29173f10a7..284eea752d550cbe978928a141e1352b8d8f4497 100644 (file)
--- a/arch/mips/include/asm/txx9/tx4927.h
+++ b/arch/mips/include/asm/txx9/tx4927.h
@@ -1,6 +1,6 @@
 /*
  * Author: MontaVista Software, Inc.
 /*
  * Author: MontaVista Software, Inc.

- *         source@mvista.com
+ *        source@mvista.com

  *
  * Copyright 2001-2006 MontaVista Software Inc.
  *
  *
  * Copyright 2001-2006 MontaVista Software Inc.
  *


@@ -33,11 +33,11 @@
 #include <asm/txx9/tx4927pcic.h>
 
 #ifdef CONFIG_64BIT
 #include <asm/txx9/tx4927pcic.h>
 
 #ifdef CONFIG_64BIT

-#define TX4927_REG_BASE        0xffffffffff1f0000UL
+#define TX4927_REG_BASE 0xffffffffff1f0000UL

 #else
 #else

-#define TX4927_REG_BASE        0xff1f0000UL
+#define TX4927_REG_BASE 0xff1f0000UL

 #endif
 #endif

-#define TX4927_REG_SIZE        0x00010000
+#define TX4927_REG_SIZE 0x00010000

 
 #define TX4927_SDRAMC_REG      (TX4927_REG_BASE + 0x8000)
 #define TX4927_EBUSC_REG       (TX4927_REG_BASE + 0x9000)
 
 #define TX4927_SDRAMC_REG      (TX4927_REG_BASE + 0x8000)
 #define TX4927_EBUSC_REG       (TX4927_REG_BASE + 0x9000)


@@ -118,10 +118,10 @@ struct tx4927_ccfg_reg {
 #define TX4927_CCFG_DIVMODE_2  (0x4 << 17)
 #define TX4927_CCFG_DIVMODE_3  (0x5 << 17)
 #define TX4927_CCFG_DIVMODE_4  (0x6 << 17)
 #define TX4927_CCFG_DIVMODE_2  (0x4 << 17)
 #define TX4927_CCFG_DIVMODE_3  (0x5 << 17)
 #define TX4927_CCFG_DIVMODE_4  (0x6 << 17)

-#define TX4927_CCFG_DIVMODE_2_5        (0x7 << 17)
+#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)

 #define TX4927_CCFG_BEOW       0x00010000
 #define TX4927_CCFG_WR 0x00008000
 #define TX4927_CCFG_BEOW       0x00010000
 #define TX4927_CCFG_WR 0x00008000

-#define TX4927_CCFG_TOE        0x00004000
+#define TX4927_CCFG_TOE 0x00004000

 #define TX4927_CCFG_PCIARB     0x00002000
 #define TX4927_CCFG_PCIDIVMODE_MASK    0x00001800
 #define TX4927_CCFG_PCIDIVMODE_2_5     0x00000000
 #define TX4927_CCFG_PCIARB     0x00002000
 #define TX4927_CCFG_PCIDIVMODE_MASK    0x00001800
 #define TX4927_CCFG_PCIDIVMODE_2_5     0x00000000


@@ -136,10 +136,10 @@ struct tx4927_ccfg_reg {
 
 /* PCFG : Pin Configuration */
 #define TX4927_PCFG_SDCLKDLY_MASK      0x30000000
 
 /* PCFG : Pin Configuration */
 #define TX4927_PCFG_SDCLKDLY_MASK      0x30000000

-#define TX4927_PCFG_SDCLKDLY(d)        ((d)<<28)
+#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)

 #define TX4927_PCFG_SYSCLKEN   0x08000000
 #define TX4927_PCFG_SYSCLKEN   0x08000000

-#define TX4927_PCFG_SDCLKEN_ALL        0x07800000
-#define TX4927_PCFG_SDCLKEN(ch)        (0x00800000<<(ch))
+#define TX4927_PCFG_SDCLKEN_ALL 0x07800000
+#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))

 #define TX4927_PCFG_PCICLKEN_ALL       0x003f0000
 #define TX4927_PCFG_PCICLKEN(ch)       (0x00010000<<(ch))
 #define TX4927_PCFG_SEL2       0x00000200
 #define TX4927_PCFG_PCICLKEN_ALL       0x003f0000
 #define TX4927_PCFG_PCICLKEN(ch)       (0x00010000<<(ch))
 #define TX4927_PCFG_SEL2       0x00000200

diff --git a/arch/mips/include/asm/txx9/tx4927pcic.h b/arch/mips/include/asm/txx9/tx4927pcic.h
index c470b8a5fe570dfa79807f746697643e2633f3f0..9eab2698caecfe36005689fc3b147f9724ce11d7 100644 (file)
--- a/arch/mips/include/asm/txx9/tx4927pcic.h
+++ b/arch/mips/include/asm/txx9/tx4927pcic.h
@@ -93,7 +93,7 @@ struct tx4927_pcic_reg {
 
 /* bits for PBACFG */
 #define TX4927_PCIC_PBACFG_FIXPA       0x00000008
 
 /* bits for PBACFG */
 #define TX4927_PCIC_PBACFG_FIXPA       0x00000008

-#define TX4927_PCIC_PBACFG_RPBA        0x00000004
+#define TX4927_PCIC_PBACFG_RPBA 0x00000004

 #define TX4927_PCIC_PBACFG_PBAEN       0x00000002
 #define TX4927_PCIC_PBACFG_BMCEN       0x00000001
 
 #define TX4927_PCIC_PBACFG_PBAEN       0x00000002
 #define TX4927_PCIC_PBACFG_BMCEN       0x00000001
 


@@ -165,7 +165,7 @@ struct tx4927_pcic_reg {
 #define TX4927_PCIC_PDMCFG_CHNEN       0x00000080
 #define TX4927_PCIC_PDMCFG_XFRACT      0x00000040
 #define TX4927_PCIC_PDMCFG_BSWAP       0x00000020
 #define TX4927_PCIC_PDMCFG_CHNEN       0x00000080
 #define TX4927_PCIC_PDMCFG_XFRACT      0x00000040
 #define TX4927_PCIC_PDMCFG_BSWAP       0x00000020

-#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK        0x0000000c
+#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c

 #define TX4927_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000
 #define TX4927_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004
 #define TX4927_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008
 #define TX4927_PCIC_PDMCFG_XFRSIZE_1DW 0x00000000
 #define TX4927_PCIC_PDMCFG_XFRSIZE_1QW 0x00000004
 #define TX4927_PCIC_PDMCFG_XFRSIZE_4QW 0x00000008


@@ -174,7 +174,7 @@ struct tx4927_pcic_reg {
 
 /* bits for PDMSTS */
 #define TX4927_PCIC_PDMSTS_REQCNT_MASK 0x3f000000
 
 /* bits for PDMSTS */
 #define TX4927_PCIC_PDMSTS_REQCNT_MASK 0x3f000000

-#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK        0x00f00000
+#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000

 #define TX4927_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000
 #define TX4927_PCIC_PDMSTS_FIFORP_MASK 0x00030000
 #define TX4927_PCIC_PDMSTS_ERRINT      0x00000800
 #define TX4927_PCIC_PDMSTS_FIFOWP_MASK 0x000c0000
 #define TX4927_PCIC_PDMSTS_FIFORP_MASK 0x00030000
 #define TX4927_PCIC_PDMSTS_ERRINT      0x00000800

diff --git a/arch/mips/include/asm/txx9/tx4938.h b/arch/mips/include/asm/txx9/tx4938.h
index 8a178f186f7d0d0e56951ec9b6e1a70493f83056..6ca767ee6467ca88c9f75b4e3681538ac88c4201 100644 (file)
--- a/arch/mips/include/asm/txx9/tx4938.h
+++ b/arch/mips/include/asm/txx9/tx4938.h
@@ -16,11 +16,11 @@
 #include <asm/txx9/tx4927.h>
 
 #ifdef CONFIG_64BIT
 #include <asm/txx9/tx4927.h>
 
 #ifdef CONFIG_64BIT

-#define TX4938_REG_BASE        0xffffffffff1f0000UL /* == TX4937_REG_BASE */
+#define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */

 #else
 #else

-#define TX4938_REG_BASE        0xff1f0000UL /* == TX4937_REG_BASE */
+#define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */

 #endif
 #endif

-#define TX4938_REG_SIZE        0x00010000 /* == TX4937_REG_SIZE */
+#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */

 
 /* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
 #define TX4938_NDFMC_REG       (TX4938_REG_BASE + 0x5000)
 
 /* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
 #define TX4938_NDFMC_REG       (TX4938_REG_BASE + 0x5000)


@@ -72,16 +72,16 @@ struct tx4938_ccfg_reg {
 #define TX4938_NUM_IR_DMA      4
 #define TX4938_IR_DMA(ch, n)   ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */
 #define TX4938_IR_PIO  14
 #define TX4938_NUM_IR_DMA      4
 #define TX4938_IR_DMA(ch, n)   ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */
 #define TX4938_IR_PIO  14

-#define TX4938_IR_PDMAC        15
+#define TX4938_IR_PDMAC 15

 #define TX4938_IR_PCIC 16
 #define TX4938_NUM_IR_TMR      3
 #define TX4938_IR_TMR(n)       (17 + (n))
 #define TX4938_IR_PCIC 16
 #define TX4938_NUM_IR_TMR      3
 #define TX4938_IR_TMR(n)       (17 + (n))

-#define TX4938_IR_NDFMC        21
+#define TX4938_IR_NDFMC 21

 #define TX4938_IR_PCIERR       22
 #define TX4938_IR_PCIPME       23
 #define TX4938_IR_ACLC 24
 #define TX4938_IR_ACLCPME      25
 #define TX4938_IR_PCIERR       22
 #define TX4938_IR_PCIPME       23
 #define TX4938_IR_ACLC 24
 #define TX4938_IR_ACLCPME      25

-#define TX4938_IR_PCIC1        26
+#define TX4938_IR_PCIC1 26

 #define TX4938_IR_SPI  31
 #define TX4938_NUM_IR  32
 /* multiplex */
 #define TX4938_IR_SPI  31
 #define TX4938_NUM_IR  32
 /* multiplex */


@@ -105,10 +105,10 @@ struct tx4938_ccfg_reg {
 #define TX4938_CCFG_PCI1_66    0x00200000
 #define TX4938_CCFG_DIVMODE_MASK       0x001e0000
 #define TX4938_CCFG_DIVMODE_2  (0x4 << 17)
 #define TX4938_CCFG_PCI1_66    0x00200000
 #define TX4938_CCFG_DIVMODE_MASK       0x001e0000
 #define TX4938_CCFG_DIVMODE_2  (0x4 << 17)

-#define TX4938_CCFG_DIVMODE_2_5        (0xf << 17)
+#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)

 #define TX4938_CCFG_DIVMODE_3  (0x5 << 17)
 #define TX4938_CCFG_DIVMODE_4  (0x6 << 17)
 #define TX4938_CCFG_DIVMODE_3  (0x5 << 17)
 #define TX4938_CCFG_DIVMODE_4  (0x6 << 17)

-#define TX4938_CCFG_DIVMODE_4_5        (0xd << 17)
+#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)

 #define TX4938_CCFG_DIVMODE_8  (0x0 << 17)
 #define TX4938_CCFG_DIVMODE_10 (0xb << 17)
 #define TX4938_CCFG_DIVMODE_12 (0x1 << 17)
 #define TX4938_CCFG_DIVMODE_8  (0x0 << 17)
 #define TX4938_CCFG_DIVMODE_10 (0xb << 17)
 #define TX4938_CCFG_DIVMODE_12 (0x1 << 17)


@@ -116,7 +116,7 @@ struct tx4938_ccfg_reg {
 #define TX4938_CCFG_DIVMODE_18 (0x9 << 17)
 #define TX4938_CCFG_BEOW       0x00010000
 #define TX4938_CCFG_WR 0x00008000
 #define TX4938_CCFG_DIVMODE_18 (0x9 << 17)
 #define TX4938_CCFG_BEOW       0x00010000
 #define TX4938_CCFG_WR 0x00008000

-#define TX4938_CCFG_TOE        0x00004000
+#define TX4938_CCFG_TOE 0x00004000

 #define TX4938_CCFG_PCIARB     0x00002000
 #define TX4938_CCFG_PCIDIVMODE_MASK    0x00001c00
 #define TX4938_CCFG_PCIDIVMODE_4       (0x1 << 10)
 #define TX4938_CCFG_PCIARB     0x00002000
 #define TX4938_CCFG_PCIDIVMODE_MASK    0x00001c00
 #define TX4938_CCFG_PCIDIVMODE_4       (0x1 << 10)


@@ -141,10 +141,10 @@ struct tx4938_ccfg_reg {
 #define TX4938_PCFG_SPI_SEL    0x0800000000000000ULL
 #define TX4938_PCFG_NDF_SEL    0x0400000000000000ULL
 #define TX4938_PCFG_SDCLKDLY_MASK      0x30000000
 #define TX4938_PCFG_SPI_SEL    0x0800000000000000ULL
 #define TX4938_PCFG_NDF_SEL    0x0400000000000000ULL
 #define TX4938_PCFG_SDCLKDLY_MASK      0x30000000

-#define TX4938_PCFG_SDCLKDLY(d)        ((d)<<28)
+#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)

 #define TX4938_PCFG_SYSCLKEN   0x08000000
 #define TX4938_PCFG_SYSCLKEN   0x08000000

-#define TX4938_PCFG_SDCLKEN_ALL        0x07800000
-#define TX4938_PCFG_SDCLKEN(ch)        (0x00800000<<(ch))
+#define TX4938_PCFG_SDCLKEN_ALL 0x07800000
+#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))

 #define TX4938_PCFG_PCICLKEN_ALL       0x003f0000
 #define TX4938_PCFG_PCICLKEN(ch)       (0x00010000<<(ch))
 #define TX4938_PCFG_SEL2       0x00000200
 #define TX4938_PCFG_PCICLKEN_ALL       0x003f0000
 #define TX4938_PCFG_PCICLKEN(ch)       (0x00010000<<(ch))
 #define TX4938_PCFG_SEL2       0x00000200


@@ -230,8 +230,8 @@ struct tx4938_ccfg_reg {
 #define TX4938_DMA_CCR_XFSZ_2W TX4938_DMA_CCR_XFSZ(3)
 #define TX4938_DMA_CCR_XFSZ_4W TX4938_DMA_CCR_XFSZ(4)
 #define TX4938_DMA_CCR_XFSZ_8W TX4938_DMA_CCR_XFSZ(5)
 #define TX4938_DMA_CCR_XFSZ_2W TX4938_DMA_CCR_XFSZ(3)
 #define TX4938_DMA_CCR_XFSZ_4W TX4938_DMA_CCR_XFSZ(4)
 #define TX4938_DMA_CCR_XFSZ_8W TX4938_DMA_CCR_XFSZ(5)

-#define TX4938_DMA_CCR_XFSZ_16W        TX4938_DMA_CCR_XFSZ(6)
-#define TX4938_DMA_CCR_XFSZ_32W        TX4938_DMA_CCR_XFSZ(7)
+#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
+#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)

 #define TX4938_DMA_CCR_MEMIO   0x00000002
 #define TX4938_DMA_CCR_SNGAD   0x00000001
 
 #define TX4938_DMA_CCR_MEMIO   0x00000002
 #define TX4938_DMA_CCR_SNGAD   0x00000001
 


@@ -263,9 +263,9 @@ struct tx4938_ccfg_reg {
 #define TX4938_REV_PCODE()     \
        ((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
 
 #define TX4938_REV_PCODE()     \
        ((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
 

-#define tx4938_ccfg_clear(bits)        tx4927_ccfg_clear(bits)
+#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)

 #define tx4938_ccfg_set(bits)  tx4927_ccfg_set(bits)
 #define tx4938_ccfg_set(bits)  tx4927_ccfg_set(bits)

-#define tx4938_ccfg_change(change, new)        tx4927_ccfg_change(change, new)
+#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)

 
 #define TX4938_SDRAMC_CR(ch)   TX4927_SDRAMC_CR(ch)
 #define TX4938_SDRAMC_BA(ch)   TX4927_SDRAMC_BA(ch)
 
 #define TX4938_SDRAMC_CR(ch)   TX4927_SDRAMC_CR(ch)
 #define TX4938_SDRAMC_BA(ch)   TX4927_SDRAMC_BA(ch)

diff --git a/arch/mips/include/asm/txx9/tx4939.h b/arch/mips/include/asm/txx9/tx4939.h
index d4f342cd593927537f209183089fc8cb7de25c59..6d667087f2aa1dc1ac8aac7a6fc45e107d664027 100644 (file)
--- a/arch/mips/include/asm/txx9/tx4939.h
+++ b/arch/mips/include/asm/txx9/tx4939.h
@@ -14,11 +14,11 @@
 #include <asm/txx9/tx4938.h>
 
 #ifdef CONFIG_64BIT
 #include <asm/txx9/tx4938.h>
 
 #ifdef CONFIG_64BIT

-#define TX4939_REG_BASE        0xffffffffff1f0000UL /* == TX4938_REG_BASE */
+#define TX4939_REG_BASE 0xffffffffff1f0000UL /* == TX4938_REG_BASE */

 #else
 #else

-#define TX4939_REG_BASE        0xff1f0000UL /* == TX4938_REG_BASE */
+#define TX4939_REG_BASE 0xff1f0000UL /* == TX4938_REG_BASE */

 #endif
 #endif

-#define TX4939_REG_SIZE        0x00010000 /* == TX4938_REG_SIZE */
+#define TX4939_REG_SIZE 0x00010000 /* == TX4938_REG_SIZE */

 
 #define TX4939_ATA_REG(ch)     (TX4939_REG_BASE + 0x3000 + (ch) * 0x1000)
 #define TX4939_NDFMC_REG       (TX4939_REG_BASE + 0x5000)
 
 #define TX4939_ATA_REG(ch)     (TX4939_REG_BASE + 0x3000 + (ch) * 0x1000)
 #define TX4939_NDFMC_REG       (TX4939_REG_BASE + 0x5000)


@@ -189,14 +189,14 @@ struct tx4939_vpc_desc {
 #define TX4939_IR_INT(n)       (3 + (n))
 #define TX4939_NUM_IR_ETH      2
 #define TX4939_IR_ETH(n)       ((n) ? 43 : 6)
 #define TX4939_IR_INT(n)       (3 + (n))
 #define TX4939_NUM_IR_ETH      2
 #define TX4939_IR_ETH(n)       ((n) ? 43 : 6)

-#define TX4939_IR_VIDEO        7
+#define TX4939_IR_VIDEO 7

 #define TX4939_IR_CIR  8
 #define TX4939_NUM_IR_SIO      4
 #define TX4939_IR_SIO(n)       ((n) ? 43 + (n) : 9)    /* 9,44-46 */
 #define TX4939_NUM_IR_DMA      4
 #define TX4939_IR_DMA(ch, n)   (((ch) ? 22 : 10) + (n)) /* 10-13,22-25 */
 #define TX4939_IR_IRC  14
 #define TX4939_IR_CIR  8
 #define TX4939_NUM_IR_SIO      4
 #define TX4939_IR_SIO(n)       ((n) ? 43 + (n) : 9)    /* 9,44-46 */
 #define TX4939_NUM_IR_DMA      4
 #define TX4939_IR_DMA(ch, n)   (((ch) ? 22 : 10) + (n)) /* 10-13,22-25 */
 #define TX4939_IR_IRC  14

-#define TX4939_IR_PDMAC        15
+#define TX4939_IR_PDMAC 15

 #define TX4939_NUM_IR_TMR      6
 #define TX4939_IR_TMR(n)       (((n) >= 3 ? 45 : 16) + (n)) /* 16-18,48-50 */
 #define TX4939_NUM_IR_ATA      2
 #define TX4939_NUM_IR_TMR      6
 #define TX4939_IR_TMR(n)       (((n) >= 3 ? 45 : 16) + (n)) /* 16-18,48-50 */
 #define TX4939_NUM_IR_ATA      2


@@ -210,10 +210,10 @@ struct tx4939_vpc_desc {
 #define TX4939_IR_I2C  33
 #define TX4939_IR_SPI  34
 #define TX4939_IR_PCIC 35
 #define TX4939_IR_I2C  33
 #define TX4939_IR_SPI  34
 #define TX4939_IR_PCIC 35

-#define TX4939_IR_PCIC1        36
+#define TX4939_IR_PCIC1 36

 #define TX4939_IR_PCIERR       37
 #define TX4939_IR_PCIPME       38
 #define TX4939_IR_PCIERR       37
 #define TX4939_IR_PCIPME       38

-#define TX4939_IR_NDFMC        39
+#define TX4939_IR_NDFMC 39

 #define TX4939_IR_ACLCPME      40
 #define TX4939_IR_RTC  41
 #define TX4939_IR_RND  42
 #define TX4939_IR_ACLCPME      40
 #define TX4939_IR_RTC  41
 #define TX4939_IR_RND  42


@@ -239,7 +239,7 @@ struct tx4939_vpc_desc {
 #define TX4939_CCFG_PCI66      0x00800000
 #define TX4939_CCFG_PCIMODE    0x00400000
 #define TX4939_CCFG_SSCG       0x00100000
 #define TX4939_CCFG_PCI66      0x00800000
 #define TX4939_CCFG_PCIMODE    0x00400000
 #define TX4939_CCFG_SSCG       0x00100000

-#define TX4939_CCFG_MULCLK_MASK        0x000e0000
+#define TX4939_CCFG_MULCLK_MASK 0x000e0000

 #define TX4939_CCFG_MULCLK_8   (0x7 << 17)
 #define TX4939_CCFG_MULCLK_9   (0x0 << 17)
 #define TX4939_CCFG_MULCLK_10  (0x1 << 17)
 #define TX4939_CCFG_MULCLK_8   (0x7 << 17)
 #define TX4939_CCFG_MULCLK_9   (0x0 << 17)
 #define TX4939_CCFG_MULCLK_10  (0x1 << 17)


@@ -250,7 +250,7 @@ struct tx4939_vpc_desc {
 #define TX4939_CCFG_MULCLK_15  (0x6 << 17)
 #define TX4939_CCFG_BEOW       0x00010000
 #define TX4939_CCFG_WR 0x00008000
 #define TX4939_CCFG_MULCLK_15  (0x6 << 17)
 #define TX4939_CCFG_BEOW       0x00010000
 #define TX4939_CCFG_WR 0x00008000

-#define TX4939_CCFG_TOE        0x00004000
+#define TX4939_CCFG_TOE 0x00004000

 #define TX4939_CCFG_PCIARB     0x00002000
 #define TX4939_CCFG_YDIVMODE_MASK      0x00001c00
 #define TX4939_CCFG_YDIVMODE_2 (0x0 << 10)
 #define TX4939_CCFG_PCIARB     0x00002000
 #define TX4939_CCFG_YDIVMODE_MASK      0x00001c00
 #define TX4939_CCFG_YDIVMODE_2 (0x0 << 10)


@@ -275,7 +275,7 @@ struct tx4939_vpc_desc {
 #define TX4939_PCFG_I2CMODE    0x1000000000000000ULL
 #define TX4939_PCFG_I2SMODE_MASK       0x0c00000000000000ULL
 #define TX4939_PCFG_I2SMODE_GPIO       0x0c00000000000000ULL
 #define TX4939_PCFG_I2CMODE    0x1000000000000000ULL
 #define TX4939_PCFG_I2SMODE_MASK       0x0c00000000000000ULL
 #define TX4939_PCFG_I2SMODE_GPIO       0x0c00000000000000ULL

-#define TX4939_PCFG_I2SMODE_I2S        0x0800000000000000ULL
+#define TX4939_PCFG_I2SMODE_I2S 0x0800000000000000ULL

 #define TX4939_PCFG_I2SMODE_I2S_ALT    0x0400000000000000ULL
 #define TX4939_PCFG_I2SMODE_ACLC       0x0000000000000000ULL
 #define TX4939_PCFG_SIO3MODE   0x0200000000000000ULL
 #define TX4939_PCFG_I2SMODE_I2S_ALT    0x0400000000000000ULL
 #define TX4939_PCFG_I2SMODE_ACLC       0x0000000000000000ULL
 #define TX4939_PCFG_SIO3MODE   0x0200000000000000ULL


@@ -392,15 +392,15 @@ struct tx4939_vpc_desc {
 /*
  * CRYPTO
  */
 /*
  * CRYPTO
  */

-#define TX4939_CRYPTO_CSR_SAESO        0x08000000
-#define TX4939_CRYPTO_CSR_SAESI        0x04000000
-#define TX4939_CRYPTO_CSR_SDESO        0x02000000
-#define TX4939_CRYPTO_CSR_SDESI        0x01000000
+#define TX4939_CRYPTO_CSR_SAESO 0x08000000
+#define TX4939_CRYPTO_CSR_SAESI 0x04000000
+#define TX4939_CRYPTO_CSR_SDESO 0x02000000
+#define TX4939_CRYPTO_CSR_SDESI 0x01000000

 #define TX4939_CRYPTO_CSR_INDXBST_MASK 0x00700000
 #define TX4939_CRYPTO_CSR_INDXBST(n)   ((n) << 20)
 #define TX4939_CRYPTO_CSR_INDXBST_MASK 0x00700000
 #define TX4939_CRYPTO_CSR_INDXBST(n)   ((n) << 20)

-#define TX4939_CRYPTO_CSR_TOINT        0x00080000
-#define TX4939_CRYPTO_CSR_DCINT        0x00040000
-#define TX4939_CRYPTO_CSR_GBINT        0x00010000
+#define TX4939_CRYPTO_CSR_TOINT 0x00080000
+#define TX4939_CRYPTO_CSR_DCINT 0x00040000
+#define TX4939_CRYPTO_CSR_GBINT 0x00010000

 #define TX4939_CRYPTO_CSR_INDXAST_MASK 0x0000e000
 #define TX4939_CRYPTO_CSR_INDXAST(n)   ((n) << 13)
 #define TX4939_CRYPTO_CSR_CSWAP_MASK   0x00001800
 #define TX4939_CRYPTO_CSR_INDXAST_MASK 0x0000e000
 #define TX4939_CRYPTO_CSR_INDXAST(n)   ((n) << 13)
 #define TX4939_CRYPTO_CSR_CSWAP_MASK   0x00001800


@@ -418,7 +418,7 @@ struct tx4939_vpc_desc {
 #define TX4939_CRYPTO_CSR_PDINT_END    0x00000040
 #define TX4939_CRYPTO_CSR_PDINT_NEXT   0x00000080
 #define TX4939_CRYPTO_CSR_PDINT_NONE   0x000000c0
 #define TX4939_CRYPTO_CSR_PDINT_END    0x00000040
 #define TX4939_CRYPTO_CSR_PDINT_NEXT   0x00000080
 #define TX4939_CRYPTO_CSR_PDINT_NONE   0x000000c0

-#define TX4939_CRYPTO_CSR_GINTE        0x00000008
+#define TX4939_CRYPTO_CSR_GINTE 0x00000008

 #define TX4939_CRYPTO_CSR_RSTD 0x00000004
 #define TX4939_CRYPTO_CSR_RSTC 0x00000002
 #define TX4939_CRYPTO_CSR_ENCR 0x00000001
 #define TX4939_CRYPTO_CSR_RSTD 0x00000004
 #define TX4939_CRYPTO_CSR_RSTC 0x00000002
 #define TX4939_CRYPTO_CSR_ENCR 0x00000001


@@ -442,7 +442,7 @@ struct tx4939_vpc_desc {
 #define TX4939_CRYPTO_DESC_START       0x00000200
 #define TX4939_CRYPTO_DESC_END 0x00000100
 #define TX4939_CRYPTO_DESC_XOR 0x00000010
 #define TX4939_CRYPTO_DESC_START       0x00000200
 #define TX4939_CRYPTO_DESC_END 0x00000100
 #define TX4939_CRYPTO_DESC_XOR 0x00000010

-#define TX4939_CRYPTO_DESC_LAST        0x00000008
+#define TX4939_CRYPTO_DESC_LAST 0x00000008

 #define TX4939_CRYPTO_DESC_ERR_MASK    0x00000006
 #define TX4939_CRYPTO_DESC_ERR_NONE    0x00000000
 #define TX4939_CRYPTO_DESC_ERR_TOUT    0x00000002
 #define TX4939_CRYPTO_DESC_ERR_MASK    0x00000006
 #define TX4939_CRYPTO_DESC_ERR_NONE    0x00000000
 #define TX4939_CRYPTO_DESC_ERR_TOUT    0x00000002


@@ -457,7 +457,7 @@ struct tx4939_vpc_desc {
 
 #define TX4939_CRYPTO_NR_SET   6
 
 
 #define TX4939_CRYPTO_NR_SET   6
 

-#define TX4939_CRYPTO_RCSR_INTE        0x00000008
+#define TX4939_CRYPTO_RCSR_INTE 0x00000008

 #define TX4939_CRYPTO_RCSR_RST 0x00000004
 #define TX4939_CRYPTO_RCSR_FIN 0x00000002
 #define TX4939_CRYPTO_RCSR_ST  0x00000001
 #define TX4939_CRYPTO_RCSR_RST 0x00000004
 #define TX4939_CRYPTO_RCSR_FIN 0x00000002
 #define TX4939_CRYPTO_RCSR_ST  0x00000001


@@ -480,8 +480,8 @@ struct tx4939_vpc_desc {
 #define TX4939_VPC_CTRLA_PDINT_ALL     0x00000000
 #define TX4939_VPC_CTRLA_PDINT_NEXT    0x00000010
 #define TX4939_VPC_CTRLA_PDINT_NONE    0x00000030
 #define TX4939_VPC_CTRLA_PDINT_ALL     0x00000000
 #define TX4939_VPC_CTRLA_PDINT_NEXT    0x00000010
 #define TX4939_VPC_CTRLA_PDINT_NONE    0x00000030

-#define TX4939_VPC_CTRLA_VDVLDP        0x00000008
-#define TX4939_VPC_CTRLA_VDMODE        0x00000004
+#define TX4939_VPC_CTRLA_VDVLDP 0x00000008
+#define TX4939_VPC_CTRLA_VDMODE 0x00000004

 #define TX4939_VPC_CTRLA_VDFOR 0x00000002
 #define TX4939_VPC_CTRLA_ENVPC 0x00000001
 
 #define TX4939_VPC_CTRLA_VDFOR 0x00000002
 #define TX4939_VPC_CTRLA_ENVPC 0x00000001
 


@@ -512,9 +512,9 @@ struct tx4939_vpc_desc {
        ((__u32)((__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_BCFG_MASK) \
                 >> 32))
 
        ((__u32)((__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_BCFG_MASK) \
                 >> 32))
 

-#define tx4939_ccfg_clear(bits)        tx4938_ccfg_clear(bits)
+#define tx4939_ccfg_clear(bits) tx4938_ccfg_clear(bits)

 #define tx4939_ccfg_set(bits)  tx4938_ccfg_set(bits)
 #define tx4939_ccfg_set(bits)  tx4938_ccfg_set(bits)

-#define tx4939_ccfg_change(change, new)        tx4938_ccfg_change(change, new)
+#define tx4939_ccfg_change(change, new) tx4938_ccfg_change(change, new)

 
 #define TX4939_EBUSC_CR(ch)    TX4927_EBUSC_CR(ch)
 #define TX4939_EBUSC_BA(ch)    TX4927_EBUSC_BA(ch)
 
 #define TX4939_EBUSC_CR(ch)    TX4927_EBUSC_CR(ch)
 #define TX4939_EBUSC_BA(ch)    TX4927_EBUSC_BA(ch)


@@ -522,7 +522,7 @@ struct tx4939_vpc_desc {
 #define TX4939_EBUSC_WIDTH(ch) \
        (16 >> ((__u32)(TX4939_EBUSC_CR(ch) >> 20) & 0x1))
 
 #define TX4939_EBUSC_WIDTH(ch) \
        (16 >> ((__u32)(TX4939_EBUSC_CR(ch) >> 20) & 0x1))
 

-/* SCLK0 = MSTCLK * 429/19 * 16/245 / 2  (14.745MHz for MST 20MHz) */
+/* SCLK0 = MSTCLK * 429/19 * 16/245 / 2         (14.745MHz for MST 20MHz) */

 #define TX4939_SCLK0(mst)      \
        ((((mst) + 245/2) / 245UL * 429 * 16 + 19) / 19 / 2)
 
 #define TX4939_SCLK0(mst)      \
        ((((mst) + 245/2) / 245UL * 429 * 16 + 19) / 19 / 2)
 

diff --git a/arch/mips/include/asm/txx9tmr.h b/arch/mips/include/asm/txx9tmr.h
index 67f70a8f09bd2b1e8cab8d7b8793a3592d8935cb..466a3def386698e9536c84c9636d6a1365d23884 100644 (file)
--- a/arch/mips/include/asm/txx9tmr.h
+++ b/arch/mips/include/asm/txx9tmr.h
@@ -59,9 +59,9 @@ void txx9_clockevent_init(unsigned long baseaddr, int irq,
 void txx9_tmr_init(unsigned long baseaddr);
 
 #ifdef CONFIG_CPU_TX39XX
 void txx9_tmr_init(unsigned long baseaddr);
 
 #ifdef CONFIG_CPU_TX39XX

-#define TXX9_TIMER_BITS        24
+#define TXX9_TIMER_BITS 24

 #else
 #else

-#define TXX9_TIMER_BITS        32
+#define TXX9_TIMER_BITS 32

 #endif
 
 #endif /* __ASM_TXX9TMR_H */
 #endif
 
 #endif /* __ASM_TXX9TMR_H */

diff --git a/arch/mips/include/asm/uaccess.h b/arch/mips/include/asm/uaccess.h
index 3b92efef56d3c9fb139d374a4436d4398bf8c9d5..bd87e36bf26a3cc980c73804bbb8a5d009f4d2ef 100644 (file)
--- a/arch/mips/include/asm/uaccess.h
+++ b/arch/mips/include/asm/uaccess.h
@@ -87,12 +87,12 @@ extern u64 __ua_limit;
 /*
  * access_ok: - Checks if a user space pointer is valid
  * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE.  Note that
 /*
  * access_ok: - Checks if a user space pointer is valid
  * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE.  Note that

- *        %VERIFY_WRITE is a superset of %VERIFY_READ - if it is safe
- *        to write to a block, it is always safe to read from it.
+ *       %VERIFY_WRITE is a superset of %VERIFY_READ - if it is safe
+ *       to write to a block, it is always safe to read from it.

  * @addr: User space pointer to start of block to check
  * @size: Size of block to check
  *
  * @addr: User space pointer to start of block to check
  * @size: Size of block to check
  *

- * Context: User context only.  This function may sleep.
+ * Context: User context only. This function may sleep.

  *
  * Checks if a pointer to a block of memory in user space is valid.
  *
  *
  * Checks if a pointer to a block of memory in user space is valid.
  *


@@ -124,10 +124,10 @@ extern u64 __ua_limit;
 
 /*
  * put_user: - Write a simple value into user space.
 
 /*
  * put_user: - Write a simple value into user space.

- * @x:   Value to copy to user space.
+ * @x:  Value to copy to user space.

  * @ptr: Destination address, in user space.
  *
  * @ptr: Destination address, in user space.
  *

- * Context: User context only.  This function may sleep.
+ * Context: User context only. This function may sleep.

  *
  * This macro copies a single simple value from kernel space to user
  * space.  It supports simple types like char and int, but not larger
  *
  * This macro copies a single simple value from kernel space to user
  * space.  It supports simple types like char and int, but not larger


@@ -138,15 +138,15 @@ extern u64 __ua_limit;
  *
  * Returns zero on success, or -EFAULT on error.
  */
  *
  * Returns zero on success, or -EFAULT on error.
  */

-#define put_user(x,ptr)        \
+#define put_user(x,ptr) \

        __put_user_check((x), (ptr), sizeof(*(ptr)))
 
 /*
  * get_user: - Get a simple variable from user space.
        __put_user_check((x), (ptr), sizeof(*(ptr)))
 
 /*
  * get_user: - Get a simple variable from user space.

- * @x:   Variable to store result.
+ * @x:  Variable to store result.

  * @ptr: Source address, in user space.
  *
  * @ptr: Source address, in user space.
  *

- * Context: User context only.  This function may sleep.
+ * Context: User context only. This function may sleep.

  *
  * This macro copies a single simple variable from user space to kernel
  * space.  It supports simple types like char and int, but not larger
  *
  * This macro copies a single simple variable from user space to kernel
  * space.  It supports simple types like char and int, but not larger


@@ -163,10 +163,10 @@ extern u64 __ua_limit;
 
 /*
  * __put_user: - Write a simple value into user space, with less checking.
 
 /*
  * __put_user: - Write a simple value into user space, with less checking.

- * @x:   Value to copy to user space.
+ * @x:  Value to copy to user space.

  * @ptr: Destination address, in user space.
  *
  * @ptr: Destination address, in user space.
  *

- * Context: User context only.  This function may sleep.
+ * Context: User context only. This function may sleep.

  *
  * This macro copies a single simple value from kernel space to user
  * space.  It supports simple types like char and int, but not larger
  *
  * This macro copies a single simple value from kernel space to user
  * space.  It supports simple types like char and int, but not larger


@@ -185,10 +185,10 @@ extern u64 __ua_limit;
 
 /*
  * __get_user: - Get a simple variable from user space, with less checking.
 
 /*
  * __get_user: - Get a simple variable from user space, with less checking.

- * @x:   Variable to store result.
+ * @x:  Variable to store result.

  * @ptr: Source address, in user space.
  *
  * @ptr: Source address, in user space.
  *

- * Context: User context only.  This function may sleep.
+ * Context: User context only. This function may sleep.

  *
  * This macro copies a single simple variable from user space to kernel
  * space.  It supports simple types like char and int, but not larger
  *
  * This macro copies a single simple variable from user space to kernel
  * space.  It supports simple types like char and int, but not larger


@@ -390,10 +390,10 @@ extern void __put_user_unknown(void);
 
 /*
  * put_user_unaligned: - Write a simple value into user space.
 
 /*
  * put_user_unaligned: - Write a simple value into user space.

- * @x:   Value to copy to user space.
+ * @x:  Value to copy to user space.

  * @ptr: Destination address, in user space.
  *
  * @ptr: Destination address, in user space.
  *

- * Context: User context only.  This function may sleep.
+ * Context: User context only. This function may sleep.

  *
  * This macro copies a single simple value from kernel space to user
  * space.  It supports simple types like char and int, but not larger
  *
  * This macro copies a single simple value from kernel space to user
  * space.  It supports simple types like char and int, but not larger


@@ -409,10 +409,10 @@ extern void __put_user_unknown(void);
 
 /*
  * get_user_unaligned: - Get a simple variable from user space.
 
 /*
  * get_user_unaligned: - Get a simple variable from user space.

- * @x:   Variable to store result.
+ * @x:  Variable to store result.

  * @ptr: Source address, in user space.
  *
  * @ptr: Source address, in user space.
  *

- * Context: User context only.  This function may sleep.
+ * Context: User context only. This function may sleep.

  *
  * This macro copies a single simple variable from user space to kernel
  * space.  It supports simple types like char and int, but not larger
  *
  * This macro copies a single simple variable from user space to kernel
  * space.  It supports simple types like char and int, but not larger


@@ -429,10 +429,10 @@ extern void __put_user_unknown(void);
 
 /*
  * __put_user_unaligned: - Write a simple value into user space, with less checking.
 
 /*
  * __put_user_unaligned: - Write a simple value into user space, with less checking.

- * @x:   Value to copy to user space.
+ * @x:  Value to copy to user space.

  * @ptr: Destination address, in user space.
  *
  * @ptr: Destination address, in user space.
  *

- * Context: User context only.  This function may sleep.
+ * Context: User context only. This function may sleep.

  *
  * This macro copies a single simple value from kernel space to user
  * space.  It supports simple types like char and int, but not larger
  *
  * This macro copies a single simple value from kernel space to user
  * space.  It supports simple types like char and int, but not larger


@@ -451,10 +451,10 @@ extern void __put_user_unknown(void);
 
 /*
  * __get_user_unaligned: - Get a simple variable from user space, with less checking.
 
 /*
  * __get_user_unaligned: - Get a simple variable from user space, with less checking.

- * @x:   Variable to store result.
+ * @x:  Variable to store result.

  * @ptr: Source address, in user space.
  *
  * @ptr: Source address, in user space.
  *

- * Context: User context only.  This function may sleep.
+ * Context: User context only. This function may sleep.

  *
  * This macro copies a single simple variable from user space to kernel
  * space.  It supports simple types like char and int, but not larger
  *
  * This macro copies a single simple variable from user space to kernel
  * space.  It supports simple types like char and int, but not larger


@@ -543,7 +543,7 @@ do {                                                                        \
  */
 #define __get_user_unaligned_asm_ll32(val, addr)                       \
 {                                                                      \
  */
 #define __get_user_unaligned_asm_ll32(val, addr)                       \
 {                                                                      \

-        unsigned long long __gu_tmp;                                   \
+       unsigned long long __gu_tmp;                                    \

                                                                        \
        __asm__ __volatile__(                                           \
        "1:     ulw     %1, (%3)                                \n"     \
                                                                        \
        __asm__ __volatile__(                                           \
        "1:     ulw     %1, (%3)                                \n"     \


@@ -631,7 +631,7 @@ do {                                                                        \
 #define __put_user_unaligned_asm_ll32(ptr)                             \
 {                                                                      \
        __asm__ __volatile__(                                           \
 #define __put_user_unaligned_asm_ll32(ptr)                             \
 {                                                                      \
        __asm__ __volatile__(                                           \

-       "1:     sw      %2, (%3)        # __put_user_unaligned_asm_ll32 \n" \
+       "1:     sw      %2, (%3)        # __put_user_unaligned_asm_ll32 \n" \

        "2:     sw      %D2, 4(%3)                              \n"     \
        "3:                                                     \n"     \
        "       .section        .fixup,\"ax\"                   \n"     \
        "2:     sw      %D2, 4(%3)                              \n"     \
        "3:                                                     \n"     \
        "       .section        .fixup,\"ax\"                   \n"     \


@@ -658,7 +658,7 @@ extern void __put_user_unaligned_unknown(void);
 #ifdef MODULE
 #define __MODULE_JAL(destination)                                      \
        ".set\tnoat\n\t"                                                \
 #ifdef MODULE
 #define __MODULE_JAL(destination)                                      \
        ".set\tnoat\n\t"                                                \

-       __UA_LA "\t$1, " #destination "\n\t"                            \
+       __UA_LA "\t$1, " #destination "\n\t"                            \

        "jalr\t$1\n\t"                                                  \
        ".set\tat\n\t"
 #else
        "jalr\t$1\n\t"                                                  \
        ".set\tat\n\t"
 #else


@@ -694,11 +694,11 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
 
 /*
  * __copy_to_user: - Copy a block of data into user space, with less checking.
 
 /*
  * __copy_to_user: - Copy a block of data into user space, with less checking.

- * @to:   Destination address, in user space.
+ * @to:          Destination address, in user space.

  * @from: Source address, in kernel space.
  * @from: Source address, in kernel space.

- * @n:    Number of bytes to copy.
+ * @n:   Number of bytes to copy.

  *
  *

- * Context: User context only.  This function may sleep.
+ * Context: User context only. This function may sleep.

  *
  * Copy data from kernel space to user space.  Caller must check
  * the specified block with access_ok() before calling this function.
  *
  * Copy data from kernel space to user space.  Caller must check
  * the specified block with access_ok() before calling this function.


@@ -716,7 +716,7 @@ extern size_t __copy_user(void *__to, const void *__from, size_t __n);
        __cu_from = (from);                                             \
        __cu_len = (n);                                                 \
        might_fault();                                                  \
        __cu_from = (from);                                             \
        __cu_len = (n);                                                 \
        might_fault();                                                  \

-       __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \
+       __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \

        __cu_len;                                                       \
 })
 
        __cu_len;                                                       \
 })
 


@@ -731,7 +731,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
        __cu_to = (to);                                                 \
        __cu_from = (from);                                             \
        __cu_len = (n);                                                 \
        __cu_to = (to);                                                 \
        __cu_from = (from);                                             \
        __cu_len = (n);                                                 \

-       __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \
+       __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \

        __cu_len;                                                       \
 })
 
        __cu_len;                                                       \
 })
 


@@ -744,18 +744,18 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
        __cu_to = (to);                                                 \
        __cu_from = (from);                                             \
        __cu_len = (n);                                                 \
        __cu_to = (to);                                                 \
        __cu_from = (from);                                             \
        __cu_len = (n);                                                 \

-       __cu_len = __invoke_copy_from_user_inatomic(__cu_to, __cu_from, \
-                                                   __cu_len);          \
+       __cu_len = __invoke_copy_from_user_inatomic(__cu_to, __cu_from, \
+                                                   __cu_len);          \

        __cu_len;                                                       \
 })
 
 /*
  * copy_to_user: - Copy a block of data into user space.
        __cu_len;                                                       \
 })
 
 /*
  * copy_to_user: - Copy a block of data into user space.

- * @to:   Destination address, in user space.
+ * @to:          Destination address, in user space.

  * @from: Source address, in kernel space.
  * @from: Source address, in kernel space.

- * @n:    Number of bytes to copy.
+ * @n:   Number of bytes to copy.

  *
  *

- * Context: User context only.  This function may sleep.
+ * Context: User context only. This function may sleep.

  *
  * Copy data from kernel space to user space.
  *
  *
  * Copy data from kernel space to user space.
  *


@@ -774,7 +774,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
        if (access_ok(VERIFY_WRITE, __cu_to, __cu_len)) {               \
                might_fault();                                          \
                __cu_len = __invoke_copy_to_user(__cu_to, __cu_from,    \
        if (access_ok(VERIFY_WRITE, __cu_to, __cu_len)) {               \
                might_fault();                                          \
                __cu_len = __invoke_copy_to_user(__cu_to, __cu_from,    \

-                                                __cu_len);             \
+                                                __cu_len);             \

        }                                                               \
        __cu_len;                                                       \
 })
        }                                                               \
        __cu_len;                                                       \
 })


@@ -827,11 +827,11 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
 
 /*
  * __copy_from_user: - Copy a block of data from user space, with less checking.
 
 /*
  * __copy_from_user: - Copy a block of data from user space, with less checking.

- * @to:   Destination address, in kernel space.
+ * @to:          Destination address, in kernel space.

  * @from: Source address, in user space.
  * @from: Source address, in user space.

- * @n:    Number of bytes to copy.
+ * @n:   Number of bytes to copy.

  *
  *

- * Context: User context only.  This function may sleep.
+ * Context: User context only. This function may sleep.

  *
  * Copy data from user space to kernel space.  Caller must check
  * the specified block with access_ok() before calling this function.
  *
  * Copy data from user space to kernel space.  Caller must check
  * the specified block with access_ok() before calling this function.


@@ -853,17 +853,17 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
        __cu_len = (n);                                                 \
        might_fault();                                                  \
        __cu_len = __invoke_copy_from_user(__cu_to, __cu_from,          \
        __cu_len = (n);                                                 \
        might_fault();                                                  \
        __cu_len = __invoke_copy_from_user(__cu_to, __cu_from,          \

-                                          __cu_len);                   \
+                                          __cu_len);                   \

        __cu_len;                                                       \
 })
 
 /*
  * copy_from_user: - Copy a block of data from user space.
        __cu_len;                                                       \
 })
 
 /*
  * copy_from_user: - Copy a block of data from user space.

- * @to:   Destination address, in kernel space.
+ * @to:          Destination address, in kernel space.

  * @from: Source address, in user space.
  * @from: Source address, in user space.

- * @n:    Number of bytes to copy.
+ * @n:   Number of bytes to copy.

  *
  *

- * Context: User context only.  This function may sleep.
+ * Context: User context only. This function may sleep.

  *
  * Copy data from user space to kernel space.
  *
  *
  * Copy data from user space to kernel space.
  *


@@ -885,7 +885,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
        if (access_ok(VERIFY_READ, __cu_from, __cu_len)) {              \
                might_fault();                                          \
                __cu_len = __invoke_copy_from_user(__cu_to, __cu_from,  \
        if (access_ok(VERIFY_READ, __cu_from, __cu_len)) {              \
                might_fault();                                          \
                __cu_len = __invoke_copy_from_user(__cu_to, __cu_from,  \

-                                                  __cu_len);           \
+                                                  __cu_len);           \

        }                                                               \
        __cu_len;                                                       \
 })
        }                                                               \
        __cu_len;                                                       \
 })


@@ -901,7 +901,7 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
        __cu_len = (n);                                                 \
        might_fault();                                                  \
        __cu_len = __invoke_copy_from_user(__cu_to, __cu_from,          \
        __cu_len = (n);                                                 \
        might_fault();                                                  \
        __cu_len = __invoke_copy_from_user(__cu_to, __cu_from,          \

-                                          __cu_len);                   \
+                                          __cu_len);                   \

        __cu_len;                                                       \
 })
 
        __cu_len;                                                       \
 })
 


@@ -915,18 +915,18 @@ extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
        __cu_from = (from);                                             \
        __cu_len = (n);                                                 \
        if (likely(access_ok(VERIFY_READ, __cu_from, __cu_len) &&       \
        __cu_from = (from);                                             \
        __cu_len = (n);                                                 \
        if (likely(access_ok(VERIFY_READ, __cu_from, __cu_len) &&       \

-                  access_ok(VERIFY_WRITE, __cu_to, __cu_len))) {       \
+                  access_ok(VERIFY_WRITE, __cu_to, __cu_len))) {       \

                might_fault();                                          \
                __cu_len = __invoke_copy_from_user(__cu_to, __cu_from,  \
                might_fault();                                          \
                __cu_len = __invoke_copy_from_user(__cu_to, __cu_from,  \

-                                                  __cu_len);           \
+                                                  __cu_len);           \

        }                                                               \
        __cu_len;                                                       \
 })
 
 /*
  * __clear_user: - Zero a block of memory in user space, with less checking.
        }                                                               \
        __cu_len;                                                       \
 })
 
 /*
  * __clear_user: - Zero a block of memory in user space, with less checking.

- * @to:   Destination address, in user space.
- * @n:    Number of bytes to zero.
+ * @to:          Destination address, in user space.
+ * @n:   Number of bytes to zero.

  *
  * Zero a block of memory in user space.  Caller must check
  * the specified block with access_ok() before calling this function.
  *
  * Zero a block of memory in user space.  Caller must check
  * the specified block with access_ok() before calling this function.


@@ -966,7 +966,7 @@ __clear_user(void __user *addr, __kernel_size_t size)
 /*
  * __strncpy_from_user: - Copy a NUL terminated string from userspace, with less checking.
  * @dst:   Destination address, in kernel space.  This buffer must be at
 /*
  * __strncpy_from_user: - Copy a NUL terminated string from userspace, with less checking.
  * @dst:   Destination address, in kernel space.  This buffer must be at

- *         least @count bytes long.
+ *        least @count bytes long.

  * @src:   Source address, in user space.
  * @count: Maximum number of bytes to copy, including the trailing NUL.
  *
  * @src:   Source address, in user space.
  * @count: Maximum number of bytes to copy, including the trailing NUL.
  *


@@ -1005,7 +1005,7 @@ __strncpy_from_user(char *__to, const char __user *__from, long __len)
 /*
  * strncpy_from_user: - Copy a NUL terminated string from userspace.
  * @dst:   Destination address, in kernel space.  This buffer must be at
 /*
  * strncpy_from_user: - Copy a NUL terminated string from userspace.
  * @dst:   Destination address, in kernel space.  This buffer must be at

- *         least @count bytes long.
+ *        least @count bytes long.

  * @src:   Source address, in user space.
  * @count: Maximum number of bytes to copy, including the trailing NUL.
  *
  * @src:   Source address, in user space.
  * @count: Maximum number of bytes to copy, including the trailing NUL.
  *


@@ -1060,7 +1060,7 @@ static inline long __strlen_user(const char __user *s)
  * strlen_user: - Get the size of a string in user space.
  * @str: The string to measure.
  *
  * strlen_user: - Get the size of a string in user space.
  * @str: The string to measure.
  *

- * Context: User context only.  This function may sleep.
+ * Context: User context only. This function may sleep.

  *
  * Get the size of a NUL-terminated string in user space.
  *
  *
  * Get the size of a NUL-terminated string in user space.
  *


@@ -1108,7 +1108,7 @@ static inline long __strnlen_user(const char __user *s, long n)
  * strlen_user: - Get the size of a string in user space.
  * @str: The string to measure.
  *
  * strlen_user: - Get the size of a string in user space.
  * @str: The string to measure.
  *

- * Context: User context only.  This function may sleep.
+ * Context: User context only. This function may sleep.

  *
  * Get the size of a NUL-terminated string in user space.
  *
  *
  * Get the size of a NUL-terminated string in user space.
  *

diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 7e0bf17c93243653dc92d8bcb44f2097e60f3965..058e941626a6ab51e823fa352e8c1f63e1d06624 100644 (file)
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *

- * Copyright (C) 2004, 2005, 2006, 2008  Thiemo Seufer
+ * Copyright (C) 2004, 2005, 2006, 2008         Thiemo Seufer

  * Copyright (C) 2005  Maciej W. Rozycki
  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
  * Copyright (C) 2012  MIPS Technologies, Inc.
  * Copyright (C) 2005  Maciej W. Rozycki
  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
  * Copyright (C) 2012  MIPS Technologies, Inc.

diff --git a/arch/mips/include/asm/user.h b/arch/mips/include/asm/user.h
index afa83a4c188843bf6b563f7a3a5c2bc70927abd2..6bad61b0a53a77385444802b19742024fd360eb5 100644 (file)
--- a/arch/mips/include/asm/user.h
+++ b/arch/mips/include/asm/user.h
@@ -20,7 +20,7 @@
  *  upage: 1 page consisting of a user struct that tells gdb
  *     what is present in the file.  Directly after this is a
  *     copy of the task_struct, which is currently not used by gdb,
  *  upage: 1 page consisting of a user struct that tells gdb
  *     what is present in the file.  Directly after this is a
  *     copy of the task_struct, which is currently not used by gdb,

- *     but it may come in handy at some point.  All of the registers
+ *     but it may come in handy at some point.  All of the registers

  *     are stored as part of the upage.  The upage should always be
  *     only one page long.
  *  data: The data segment follows next.  We use current->end_text to
  *     are stored as part of the upage.  The upage should always be
  *     only one page long.
  *  data: The data segment follows next.  We use current->end_text to

diff --git a/arch/mips/include/asm/vr41xx/pci.h b/arch/mips/include/asm/vr41xx/pci.h
index c231a3d6cfd8fb5ccb01b1da7cdb72238c1a84b3..a866918cfea5e2a6e1f45c30772fcee6caf9ba00 100644 (file)
--- a/arch/mips/include/asm/vr41xx/pci.h
+++ b/arch/mips/include/asm/vr41xx/pci.h
@@ -20,7 +20,7 @@
 #ifndef __NEC_VR41XX_PCI_H
 #define __NEC_VR41XX_PCI_H
 
 #ifndef __NEC_VR41XX_PCI_H
 #define __NEC_VR41XX_PCI_H
 

-#define PCI_MASTER_ADDRESS_MASK        0x7fffffffU
+#define PCI_MASTER_ADDRESS_MASK 0x7fffffffU

 
 struct pci_master_address_conversion {
        uint32_t bus_base_address;
 
 struct pci_master_address_conversion {
        uint32_t bus_base_address;

diff --git a/arch/mips/include/asm/vr41xx/tb0287.h b/arch/mips/include/asm/vr41xx/tb0287.h
index 61bead68abf0dd6638b5684158af4479e7f4670a..d58b5678f243b397c21088072b9486b44f5d5c67 100644 (file)
--- a/arch/mips/include/asm/vr41xx/tb0287.h
+++ b/arch/mips/include/asm/vr41xx/tb0287.h
@@ -1,7 +1,7 @@
 /*
  *  tb0287.h, Include file for TANBAC TB0287 mini-ITX board.
  *
 /*
  *  tb0287.h, Include file for TANBAC TB0287 mini-ITX board.
  *

- *  Copyright (C) 2005  Media Lab Inc. <ito@mlb.co.jp>
+ *  Copyright (C) 2005 Media Lab Inc. <ito@mlb.co.jp>

  *
  *  This code is largely based on tb0219.h.
  *
  *
  *  This code is largely based on tb0219.h.
  *

diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index 65e344532dedc1a355176202ae016a44f615874e..9344e247a6c8c93a92a4c0bf829485f0fb24aa77 100644 (file)
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -83,30 +83,30 @@
 #endif
 
 /*
 #endif
 
 /*

- * Pleasures of the R4600 V1.x.  Cite from the IDT R4600 V1.7 errata:
+ * Pleasures of the R4600 V1.x.         Cite from the IDT R4600 V1.7 errata:

  *
  *  18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
  *
  *  18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,

- *      Hit_Invalidate_D and Create_Dirty_Excl_D should only be
- *      executed if there is no other dcache activity. If the dcache is
- *      accessed for another instruction immeidately preceding when these
- *      cache instructions are executing, it is possible that the dcache
- *      tag match outputs used by these cache instructions will be
- *      incorrect. These cache instructions should be preceded by at least
- *      four instructions that are not any kind of load or store
- *      instruction.
- *
- *      This is not allowed:    lw
- *                              nop
- *                              nop
- *                              nop
- *                              cache       Hit_Writeback_Invalidate_D
- *
- *      This is allowed:        lw
- *                              nop
- *                              nop
- *                              nop
- *                              nop
- *                              cache       Hit_Writeback_Invalidate_D
+ *     Hit_Invalidate_D and Create_Dirty_Excl_D should only be
+ *     executed if there is no other dcache activity. If the dcache is
+ *     accessed for another instruction immeidately preceding when these
+ *     cache instructions are executing, it is possible that the dcache
+ *     tag match outputs used by these cache instructions will be
+ *     incorrect. These cache instructions should be preceded by at least
+ *     four instructions that are not any kind of load or store
+ *     instruction.
+ *
+ *     This is not allowed:    lw
+ *                             nop
+ *                             nop
+ *                             nop
+ *                             cache       Hit_Writeback_Invalidate_D
+ *
+ *     This is allowed:        lw
+ *                             nop
+ *                             nop
+ *                             nop
+ *                             nop
+ *                             cache       Hit_Writeback_Invalidate_D

  */
 #ifndef R4600_V1_HIT_CACHEOP_WAR
 #error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform
  */
 #ifndef R4600_V1_HIT_CACHEOP_WAR
 #error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform


@@ -118,7 +118,7 @@
  *
  * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
  * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
  *
  * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
  * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only

- * operate correctly if the internal data cache refill buffer is empty.  These
+ * operate correctly if the internal data cache refill buffer is empty.         These

  * CACHE instructions should be separated from any potential data cache miss
  * by a load instruction to an uncached address to empty the response buffer."
  * (Revision 2.0 device errata from IDT available on http://www.idt.com/
  * CACHE instructions should be separated from any potential data cache miss
  * by a load instruction to an uncached address to empty the response buffer."
  * (Revision 2.0 device errata from IDT available on http://www.idt.com/

diff --git a/arch/mips/include/asm/xtalk/xtalk.h b/arch/mips/include/asm/xtalk/xtalk.h
index 79bac882a7394bb6388f4964ed172b752a5818f7..680e7efebbaf6bd08246ade5a9dd14a8a6640a57 100644 (file)
--- a/arch/mips/include/asm/xtalk/xtalk.h
+++ b/arch/mips/include/asm/xtalk/xtalk.h
@@ -16,15 +16,15 @@
 /*
  * User-level device driver visible types
  */
 /*
  * User-level device driver visible types
  */

-typedef char            xwidgetnum_t;  /* xtalk widget number  (0..15) */
+typedef char           xwidgetnum_t;   /* xtalk widget number  (0..15) */

 
 #define XWIDGET_NONE           -1
 
 
 #define XWIDGET_NONE           -1
 

-typedef int xwidget_part_num_t;        /* xtalk widget part number */
+typedef int xwidget_part_num_t; /* xtalk widget part number */

 
 #define XWIDGET_PART_NUM_NONE  -1
 
 
 #define XWIDGET_PART_NUM_NONE  -1
 

-typedef int             xwidget_rev_num_t;     /* xtalk widget revision number */
+typedef int            xwidget_rev_num_t;      /* xtalk widget revision number */

 
 #define XWIDGET_REV_NUM_NONE   -1
 
 
 #define XWIDGET_REV_NUM_NONE   -1
 


@@ -37,15 +37,15 @@ typedef struct xtalk_piomap_s *xtalk_piomap_t;
 /* It is often convenient to fold the XIO target port
  * number into the XIO address.
  */
 /* It is often convenient to fold the XIO target port
  * number into the XIO address.
  */

-#define        XIO_NOWHERE     (0xFFFFFFFFFFFFFFFFull)
-#define        XIO_ADDR_BITS   (0x0000FFFFFFFFFFFFull)
-#define        XIO_PORT_BITS   (0xF000000000000000ull)
-#define        XIO_PORT_SHIFT  (60)
-
-#define        XIO_PACKED(x)   (((x)&XIO_PORT_BITS) != 0)
-#define        XIO_ADDR(x)     ((x)&XIO_ADDR_BITS)
-#define        XIO_PORT(x)     ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT))
-#define        XIO_PACK(p, o)  ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS))
+#define XIO_NOWHERE    (0xFFFFFFFFFFFFFFFFull)
+#define XIO_ADDR_BITS  (0x0000FFFFFFFFFFFFull)
+#define XIO_PORT_BITS  (0xF000000000000000ull)
+#define XIO_PORT_SHIFT (60)
+
+#define XIO_PACKED(x)  (((x)&XIO_PORT_BITS) != 0)
+#define XIO_ADDR(x)    ((x)&XIO_ADDR_BITS)
+#define XIO_PORT(x)    ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT))
+#define XIO_PACK(p, o) ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS))

 
 #endif /* !__ASSEMBLY__ */
 
 
 #endif /* !__ASSEMBLY__ */
 

diff --git a/arch/mips/include/asm/xtalk/xwidget.h b/arch/mips/include/asm/xtalk/xwidget.h
index b4a13d7405ee852d9fca9c1e2c9530b408e50e05..32e4e884f9b9ee6fbe40cf2b5af05f0bc511330c 100644 (file)
--- a/arch/mips/include/asm/xtalk/xwidget.h
+++ b/arch/mips/include/asm/xtalk/xwidget.h
@@ -45,12 +45,12 @@
 #define WIDGET_PENDING                 0x0000001f
 
 /* WIDGET_ERR_UPPER_ADDR */
 #define WIDGET_PENDING                 0x0000001f
 
 /* WIDGET_ERR_UPPER_ADDR */

-#define        WIDGET_ERR_UPPER_ADDR_ONLY      0x0000ffff
+#define WIDGET_ERR_UPPER_ADDR_ONLY     0x0000ffff

 
 /* WIDGET_CONTROL */
 #define WIDGET_F_BAD_PKT               0x00010000
 #define WIDGET_LLP_XBAR_CRD            0x0000f000
 
 /* WIDGET_CONTROL */
 #define WIDGET_F_BAD_PKT               0x00010000
 #define WIDGET_LLP_XBAR_CRD            0x0000f000

-#define        WIDGET_LLP_XBAR_CRD_SHFT        12
+#define WIDGET_LLP_XBAR_CRD_SHFT       12

 #define WIDGET_CLR_RLLP_CNT            0x00000800
 #define WIDGET_CLR_TLLP_CNT            0x00000400
 #define WIDGET_SYS_END                 0x00000200
 #define WIDGET_CLR_RLLP_CNT            0x00000800
 #define WIDGET_CLR_TLLP_CNT            0x00000400
 #define WIDGET_SYS_END                 0x00000200


@@ -86,8 +86,8 @@
 
 /*
  * according to the crosstalk spec, only 32-bits access to the widget
 
 /*
  * according to the crosstalk spec, only 32-bits access to the widget

- * configuration registers is allowed.  some widgets may allow 64-bits
- * access but software should not depend on it.  registers beyond the
+ * configuration registers is allowed. some widgets may allow 64-bits
+ * access but software should not depend on it.         registers beyond the

  * widget target flush register are widget dependent thus will not be
  * defined here
  */
  * widget target flush register are widget dependent thus will not be
  * defined here
  */

diff --git a/arch/mips/include/uapi/asm/break.h b/arch/mips/include/uapi/asm/break.h
index 9161e684cb4c6ce81cf9875024e0301893c8063d..e5fa7b5b0556116388283e78aff257972f207d91 100644 (file)
--- a/arch/mips/include/uapi/asm/break.h
+++ b/arch/mips/include/uapi/asm/break.h
@@ -19,7 +19,7 @@
 #define BRK_KERNELBP   1       /* Break in the kernel */
 #define BRK_ABORT      2       /* Sometimes used by abort(3) to SIGIOT */
 #define BRK_BD_TAKEN   3       /* For bd slot emulation - not implemented */
 #define BRK_KERNELBP   1       /* Break in the kernel */
 #define BRK_ABORT      2       /* Sometimes used by abort(3) to SIGIOT */
 #define BRK_BD_TAKEN   3       /* For bd slot emulation - not implemented */

-#define BRK_BD_NOTTAKEN        4       /* For bd slot emulation - not implemented */
+#define BRK_BD_NOTTAKEN 4      /* For bd slot emulation - not implemented */

 #define BRK_SSTEPBP    5       /* User bp (used by debuggers) */
 #define BRK_OVERFLOW   6       /* Overflow check */
 #define BRK_DIVZERO    7       /* Divide by zero check */
 #define BRK_SSTEPBP    5       /* User bp (used by debuggers) */
 #define BRK_OVERFLOW   6       /* Overflow check */
 #define BRK_DIVZERO    7       /* Divide by zero check */

diff --git a/arch/mips/include/uapi/asm/cachectl.h b/arch/mips/include/uapi/asm/cachectl.h
index f3ce721861d3859a2624669c1928cf4a91c1ca2f..2303909087734adbac1c35c2d778df3099a48eea 100644 (file)
--- a/arch/mips/include/uapi/asm/cachectl.h
+++ b/arch/mips/include/uapi/asm/cachectl.h
@@ -5,15 +5,15 @@
  *
  * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
  */
  *
  * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
  */

-#ifndef        _ASM_CACHECTL
-#define        _ASM_CACHECTL
+#ifndef _ASM_CACHECTL
+#define _ASM_CACHECTL

 
 /*
  * Options for cacheflush system call
  */
 
 /*
  * Options for cacheflush system call
  */

-#define        ICACHE  (1<<0)          /* flush instruction cache        */
-#define        DCACHE  (1<<1)          /* writeback and flush data cache */
-#define        BCACHE  (ICACHE|DCACHE) /* flush both caches              */
+#define ICACHE (1<<0)          /* flush instruction cache        */
+#define DCACHE (1<<1)          /* writeback and flush data cache */
+#define BCACHE (ICACHE|DCACHE) /* flush both caches              */

 
 /*
  * Caching modes for the cachectl(2) call
 
 /*
  * Caching modes for the cachectl(2) call

diff --git a/arch/mips/include/uapi/asm/errno.h b/arch/mips/include/uapi/asm/errno.h
index bd67b15042ece85d9291a690afb539b33d8b9d21..31575e2fd1bdfe7f0a4228ada72f49515631faf3 100644 (file)
--- a/arch/mips/include/uapi/asm/errno.h
+++ b/arch/mips/include/uapi/asm/errno.h
@@ -14,95 +14,95 @@
 
 #include <asm-generic/errno-base.h>
 
 
 #include <asm-generic/errno-base.h>
 

-#define        ENOMSG          35      /* No message of desired type */
-#define        EIDRM           36      /* Identifier removed */
-#define        ECHRNG          37      /* Channel number out of range */
-#define        EL2NSYNC        38      /* Level 2 not synchronized */
-#define        EL3HLT          39      /* Level 3 halted */
-#define        EL3RST          40      /* Level 3 reset */
-#define        ELNRNG          41      /* Link number out of range */
-#define        EUNATCH         42      /* Protocol driver not attached */
-#define        ENOCSI          43      /* No CSI structure available */
-#define        EL2HLT          44      /* Level 2 halted */
-#define        EDEADLK         45      /* Resource deadlock would occur */
-#define        ENOLCK          46      /* No record locks available */
-#define        EBADE           50      /* Invalid exchange */
-#define        EBADR           51      /* Invalid request descriptor */
-#define        EXFULL          52      /* Exchange full */
-#define        ENOANO          53      /* No anode */
-#define        EBADRQC         54      /* Invalid request code */
-#define        EBADSLT         55      /* Invalid slot */
-#define        EDEADLOCK       56      /* File locking deadlock error */
-#define        EBFONT          59      /* Bad font file format */
-#define        ENOSTR          60      /* Device not a stream */
-#define        ENODATA         61      /* No data available */
-#define        ETIME           62      /* Timer expired */
-#define        ENOSR           63      /* Out of streams resources */
-#define        ENONET          64      /* Machine is not on the network */
-#define        ENOPKG          65      /* Package not installed */
-#define        EREMOTE         66      /* Object is remote */
-#define        ENOLINK         67      /* Link has been severed */
-#define        EADV            68      /* Advertise error */
-#define        ESRMNT          69      /* Srmount error */
-#define        ECOMM           70      /* Communication error on send */
-#define        EPROTO          71      /* Protocol error */
-#define        EDOTDOT         73      /* RFS specific error */
-#define        EMULTIHOP       74      /* Multihop attempted */
-#define        EBADMSG         77      /* Not a data message */
-#define        ENAMETOOLONG    78      /* File name too long */
-#define        EOVERFLOW       79      /* Value too large for defined data type */
-#define        ENOTUNIQ        80      /* Name not unique on network */
-#define        EBADFD          81      /* File descriptor in bad state */
-#define        EREMCHG         82      /* Remote address changed */
-#define        ELIBACC         83      /* Can not access a needed shared library */
-#define        ELIBBAD         84      /* Accessing a corrupted shared library */
-#define        ELIBSCN         85      /* .lib section in a.out corrupted */
-#define        ELIBMAX         86      /* Attempting to link in too many shared libraries */
-#define        ELIBEXEC        87      /* Cannot exec a shared library directly */
-#define        EILSEQ          88      /* Illegal byte sequence */
-#define        ENOSYS          89      /* Function not implemented */
-#define        ELOOP           90      /* Too many symbolic links encountered */
-#define        ERESTART        91      /* Interrupted system call should be restarted */
-#define        ESTRPIPE        92      /* Streams pipe error */
-#define        ENOTEMPTY       93      /* Directory not empty */
-#define        EUSERS          94      /* Too many users */
-#define        ENOTSOCK        95      /* Socket operation on non-socket */
-#define        EDESTADDRREQ    96      /* Destination address required */
-#define        EMSGSIZE        97      /* Message too long */
-#define        EPROTOTYPE      98      /* Protocol wrong type for socket */
-#define        ENOPROTOOPT     99      /* Protocol not available */
-#define        EPROTONOSUPPORT 120     /* Protocol not supported */
-#define        ESOCKTNOSUPPORT 121     /* Socket type not supported */
-#define        EOPNOTSUPP      122     /* Operation not supported on transport endpoint */
-#define        EPFNOSUPPORT    123     /* Protocol family not supported */
-#define        EAFNOSUPPORT    124     /* Address family not supported by protocol */
-#define        EADDRINUSE      125     /* Address already in use */
-#define        EADDRNOTAVAIL   126     /* Cannot assign requested address */
-#define        ENETDOWN        127     /* Network is down */
-#define        ENETUNREACH     128     /* Network is unreachable */
-#define        ENETRESET       129     /* Network dropped connection because of reset */
-#define        ECONNABORTED    130     /* Software caused connection abort */
-#define        ECONNRESET      131     /* Connection reset by peer */
-#define        ENOBUFS         132     /* No buffer space available */
-#define        EISCONN         133     /* Transport endpoint is already connected */
-#define        ENOTCONN        134     /* Transport endpoint is not connected */
-#define        EUCLEAN         135     /* Structure needs cleaning */
-#define        ENOTNAM         137     /* Not a XENIX named type file */
-#define        ENAVAIL         138     /* No XENIX semaphores available */
-#define        EISNAM          139     /* Is a named type file */
-#define        EREMOTEIO       140     /* Remote I/O error */
+#define ENOMSG         35      /* No message of desired type */
+#define EIDRM          36      /* Identifier removed */
+#define ECHRNG         37      /* Channel number out of range */
+#define EL2NSYNC       38      /* Level 2 not synchronized */
+#define EL3HLT         39      /* Level 3 halted */
+#define EL3RST         40      /* Level 3 reset */
+#define ELNRNG         41      /* Link number out of range */
+#define EUNATCH                42      /* Protocol driver not attached */
+#define ENOCSI         43      /* No CSI structure available */
+#define EL2HLT         44      /* Level 2 halted */
+#define EDEADLK                45      /* Resource deadlock would occur */
+#define ENOLCK         46      /* No record locks available */
+#define EBADE          50      /* Invalid exchange */
+#define EBADR          51      /* Invalid request descriptor */
+#define EXFULL         52      /* Exchange full */
+#define ENOANO         53      /* No anode */
+#define EBADRQC                54      /* Invalid request code */
+#define EBADSLT                55      /* Invalid slot */
+#define EDEADLOCK      56      /* File locking deadlock error */
+#define EBFONT         59      /* Bad font file format */
+#define ENOSTR         60      /* Device not a stream */
+#define ENODATA                61      /* No data available */
+#define ETIME          62      /* Timer expired */
+#define ENOSR          63      /* Out of streams resources */
+#define ENONET         64      /* Machine is not on the network */
+#define ENOPKG         65      /* Package not installed */
+#define EREMOTE                66      /* Object is remote */
+#define ENOLINK                67      /* Link has been severed */
+#define EADV           68      /* Advertise error */
+#define ESRMNT         69      /* Srmount error */
+#define ECOMM          70      /* Communication error on send */
+#define EPROTO         71      /* Protocol error */
+#define EDOTDOT                73      /* RFS specific error */
+#define EMULTIHOP      74      /* Multihop attempted */
+#define EBADMSG                77      /* Not a data message */
+#define ENAMETOOLONG   78      /* File name too long */
+#define EOVERFLOW      79      /* Value too large for defined data type */
+#define ENOTUNIQ       80      /* Name not unique on network */
+#define EBADFD         81      /* File descriptor in bad state */
+#define EREMCHG                82      /* Remote address changed */
+#define ELIBACC                83      /* Can not access a needed shared library */
+#define ELIBBAD                84      /* Accessing a corrupted shared library */
+#define ELIBSCN                85      /* .lib section in a.out corrupted */
+#define ELIBMAX                86      /* Attempting to link in too many shared libraries */
+#define ELIBEXEC       87      /* Cannot exec a shared library directly */
+#define EILSEQ         88      /* Illegal byte sequence */
+#define ENOSYS         89      /* Function not implemented */
+#define ELOOP          90      /* Too many symbolic links encountered */
+#define ERESTART       91      /* Interrupted system call should be restarted */
+#define ESTRPIPE       92      /* Streams pipe error */
+#define ENOTEMPTY      93      /* Directory not empty */
+#define EUSERS         94      /* Too many users */
+#define ENOTSOCK       95      /* Socket operation on non-socket */
+#define EDESTADDRREQ   96      /* Destination address required */
+#define EMSGSIZE       97      /* Message too long */
+#define EPROTOTYPE     98      /* Protocol wrong type for socket */
+#define ENOPROTOOPT    99      /* Protocol not available */
+#define EPROTONOSUPPORT 120    /* Protocol not supported */
+#define ESOCKTNOSUPPORT 121    /* Socket type not supported */
+#define EOPNOTSUPP     122     /* Operation not supported on transport endpoint */
+#define EPFNOSUPPORT   123     /* Protocol family not supported */
+#define EAFNOSUPPORT   124     /* Address family not supported by protocol */
+#define EADDRINUSE     125     /* Address already in use */
+#define EADDRNOTAVAIL  126     /* Cannot assign requested address */
+#define ENETDOWN       127     /* Network is down */
+#define ENETUNREACH    128     /* Network is unreachable */
+#define ENETRESET      129     /* Network dropped connection because of reset */
+#define ECONNABORTED   130     /* Software caused connection abort */
+#define ECONNRESET     131     /* Connection reset by peer */
+#define ENOBUFS                132     /* No buffer space available */
+#define EISCONN                133     /* Transport endpoint is already connected */
+#define ENOTCONN       134     /* Transport endpoint is not connected */
+#define EUCLEAN                135     /* Structure needs cleaning */
+#define ENOTNAM                137     /* Not a XENIX named type file */
+#define ENAVAIL                138     /* No XENIX semaphores available */
+#define EISNAM         139     /* Is a named type file */
+#define EREMOTEIO      140     /* Remote I/O error */

 #define EINIT          141     /* Reserved */
 #define EREMDEV                142     /* Error 142 */
 #define EINIT          141     /* Reserved */
 #define EREMDEV                142     /* Error 142 */

-#define        ESHUTDOWN       143     /* Cannot send after transport endpoint shutdown */
-#define        ETOOMANYREFS    144     /* Too many references: cannot splice */
-#define        ETIMEDOUT       145     /* Connection timed out */
-#define        ECONNREFUSED    146     /* Connection refused */
-#define        EHOSTDOWN       147     /* Host is down */
-#define        EHOSTUNREACH    148     /* No route to host */
-#define        EWOULDBLOCK     EAGAIN  /* Operation would block */
-#define        EALREADY        149     /* Operation already in progress */
-#define        EINPROGRESS     150     /* Operation now in progress */
-#define        ESTALE          151     /* Stale NFS file handle */
+#define ESHUTDOWN      143     /* Cannot send after transport endpoint shutdown */
+#define ETOOMANYREFS   144     /* Too many references: cannot splice */
+#define ETIMEDOUT      145     /* Connection timed out */
+#define ECONNREFUSED   146     /* Connection refused */
+#define EHOSTDOWN      147     /* Host is down */
+#define EHOSTUNREACH   148     /* No route to host */
+#define EWOULDBLOCK    EAGAIN  /* Operation would block */
+#define EALREADY       149     /* Operation already in progress */
+#define EINPROGRESS    150     /* Operation now in progress */
+#define ESTALE         151     /* Stale NFS file handle */

 #define ECANCELED      158     /* AIO operation canceled */
 
 /*
 #define ECANCELED      158     /* AIO operation canceled */
 
 /*


@@ -110,16 +110,16 @@
  */
 #define ENOMEDIUM      159     /* No medium found */
 #define EMEDIUMTYPE    160     /* Wrong medium type */
  */
 #define ENOMEDIUM      159     /* No medium found */
 #define EMEDIUMTYPE    160     /* Wrong medium type */

-#define        ENOKEY          161     /* Required key not available */
-#define        EKEYEXPIRED     162     /* Key has expired */
-#define        EKEYREVOKED     163     /* Key has been revoked */
-#define        EKEYREJECTED    164     /* Key was rejected by service */
+#define ENOKEY         161     /* Required key not available */
+#define EKEYEXPIRED    162     /* Key has expired */
+#define EKEYREVOKED    163     /* Key has been revoked */
+#define EKEYREJECTED   164     /* Key was rejected by service */

 
 /* for robust mutexes */
 
 /* for robust mutexes */

-#define        EOWNERDEAD      165     /* Owner died */
-#define        ENOTRECOVERABLE 166     /* State not recoverable */
+#define EOWNERDEAD     165     /* Owner died */
+#define ENOTRECOVERABLE 166    /* State not recoverable */

 
 

-#define        ERFKILL         167     /* Operation not possible due to RF-kill */
+#define ERFKILL                167     /* Operation not possible due to RF-kill */

 
 #define EHWPOISON      168     /* Memory page has hardware error */
 
 
 #define EHWPOISON      168     /* Memory page has hardware error */
 

diff --git a/arch/mips/include/uapi/asm/fcntl.h b/arch/mips/include/uapi/asm/fcntl.h
index 75eddedcfc3ee31a5ba500089fb92215311f51eb..0bda78f70e1e5930438c78e00897b7e86d244d75 100644 (file)
--- a/arch/mips/include/uapi/asm/fcntl.h
+++ b/arch/mips/include/uapi/asm/fcntl.h
@@ -12,7 +12,7 @@
 #define O_APPEND       0x0008
 #define O_DSYNC                0x0010  /* used to be O_SYNC, see below */
 #define O_NONBLOCK     0x0080
 #define O_APPEND       0x0008
 #define O_DSYNC                0x0010  /* used to be O_SYNC, see below */
 #define O_NONBLOCK     0x0080

-#define O_CREAT         0x0100 /* not fcntl */
+#define O_CREAT                0x0100  /* not fcntl */

 #define O_TRUNC                0x0200  /* not fcntl */
 #define O_EXCL         0x0400  /* not fcntl */
 #define O_NOCTTY       0x0800  /* not fcntl */
 #define O_TRUNC                0x0200  /* not fcntl */
 #define O_EXCL         0x0400  /* not fcntl */
 #define O_NOCTTY       0x0800  /* not fcntl */


@@ -50,7 +50,7 @@
 
 /*
  * The flavours of struct flock.  "struct flock" is the ABI compliant
 
 /*
  * The flavours of struct flock.  "struct flock" is the ABI compliant

- * variant.  Finally struct flock64 is the LFS variant of struct flock.  As
+ * variant.  Finally struct flock64 is the LFS variant of struct flock.         As

  * a historic accident and inconsistence with the ABI definition it doesn't
  * contain all the same fields as struct flock.
  */
  * a historic accident and inconsistence with the ABI definition it doesn't
  * contain all the same fields as struct flock.
  */

diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index fb77a0e01cd788762337b872cb9eba46c8710ad0..4d078815eaa5448d933ecce88e1ada2503f629ce 100644 (file)
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -96,11 +96,11 @@ enum rt_op {
  * rs field of cop opcodes.
  */
 enum cop_op {
  * rs field of cop opcodes.
  */
 enum cop_op {

-       mfc_op        = 0x00, dmfc_op       = 0x01,
-       cfc_op        = 0x02, mtc_op        = 0x04,
-       dmtc_op       = 0x05, ctc_op        = 0x06,
-       bc_op         = 0x08, cop_op        = 0x10,
-       copm_op       = 0x18
+       mfc_op        = 0x00, dmfc_op       = 0x01,
+       cfc_op        = 0x02, mtc_op        = 0x04,
+       dmtc_op       = 0x05, ctc_op        = 0x06,
+       bc_op         = 0x08, cop_op        = 0x10,
+       copm_op       = 0x18

 };
 
 /*
 };
 
 /*


@@ -114,18 +114,18 @@ enum bcop_op {
  * func field of cop0 coi opcodes.
  */
 enum cop0_coi_func {
  * func field of cop0 coi opcodes.
  */
 enum cop0_coi_func {

-       tlbr_op       = 0x01, tlbwi_op      = 0x02,
-       tlbwr_op      = 0x06, tlbp_op       = 0x08,
-       rfe_op        = 0x10, eret_op       = 0x18
+       tlbr_op       = 0x01, tlbwi_op      = 0x02,
+       tlbwr_op      = 0x06, tlbp_op       = 0x08,
+       rfe_op        = 0x10, eret_op       = 0x18

 };
 
 /*
  * func field of cop0 com opcodes.
  */
 enum cop0_com_func {
 };
 
 /*
  * func field of cop0 com opcodes.
  */
 enum cop0_com_func {

-       tlbr1_op      = 0x01, tlbw_op       = 0x02,
-       tlbp1_op      = 0x08, dctr_op       = 0x09,
-       dctw_op       = 0x0a
+       tlbr1_op      = 0x01, tlbw_op       = 0x02,
+       tlbp1_op      = 0x08, dctr_op       = 0x09,
+       dctw_op       = 0x0a

 };
 
 /*
 };
 
 /*


@@ -140,43 +140,43 @@ enum cop1_fmt {
  * func field of cop1 instructions using d, s or w format.
  */
 enum cop1_sdw_func {
  * func field of cop1 instructions using d, s or w format.
  */
 enum cop1_sdw_func {

-       fadd_op      =  0x00, fsub_op      =  0x01,
-       fmul_op      =  0x02, fdiv_op      =  0x03,
-       fsqrt_op     =  0x04, fabs_op      =  0x05,
-       fmov_op      =  0x06, fneg_op      =  0x07,
-       froundl_op   =  0x08, ftruncl_op   =  0x09,
-       fceill_op    =  0x0a, ffloorl_op   =  0x0b,
-       fround_op    =  0x0c, ftrunc_op    =  0x0d,
-       fceil_op     =  0x0e, ffloor_op    =  0x0f,
-       fmovc_op     =  0x11, fmovz_op     =  0x12,
-       fmovn_op     =  0x13, frecip_op    =  0x15,
-       frsqrt_op    =  0x16, fcvts_op     =  0x20,
-       fcvtd_op     =  0x21, fcvte_op     =  0x22,
-       fcvtw_op     =  0x24, fcvtl_op     =  0x25,
-       fcmp_op      =  0x30
+       fadd_op      =  0x00, fsub_op      =  0x01,
+       fmul_op      =  0x02, fdiv_op      =  0x03,
+       fsqrt_op     =  0x04, fabs_op      =  0x05,
+       fmov_op      =  0x06, fneg_op      =  0x07,
+       froundl_op   =  0x08, ftruncl_op   =  0x09,
+       fceill_op    =  0x0a, ffloorl_op   =  0x0b,
+       fround_op    =  0x0c, ftrunc_op    =  0x0d,
+       fceil_op     =  0x0e, ffloor_op    =  0x0f,
+       fmovc_op     =  0x11, fmovz_op     =  0x12,
+       fmovn_op     =  0x13, frecip_op    =  0x15,
+       frsqrt_op    =  0x16, fcvts_op     =  0x20,
+       fcvtd_op     =  0x21, fcvte_op     =  0x22,
+       fcvtw_op     =  0x24, fcvtl_op     =  0x25,
+       fcmp_op      =  0x30

 };
 
 /*
  * func field of cop1x opcodes (MIPS IV).
  */
 enum cop1x_func {
 };
 
 /*
  * func field of cop1x opcodes (MIPS IV).
  */
 enum cop1x_func {

-       lwxc1_op     =  0x00, ldxc1_op     =  0x01,
-       pfetch_op    =  0x07, swxc1_op     =  0x08,
-       sdxc1_op     =  0x09, madd_s_op    =  0x20,
-       madd_d_op    =  0x21, madd_e_op    =  0x22,
-       msub_s_op    =  0x28, msub_d_op    =  0x29,
-       msub_e_op    =  0x2a, nmadd_s_op   =  0x30,
-       nmadd_d_op   =  0x31, nmadd_e_op   =  0x32,
-       nmsub_s_op   =  0x38, nmsub_d_op   =  0x39,
-       nmsub_e_op   =  0x3a
+       lwxc1_op     =  0x00, ldxc1_op     =  0x01,
+       pfetch_op    =  0x07, swxc1_op     =  0x08,
+       sdxc1_op     =  0x09, madd_s_op    =  0x20,
+       madd_d_op    =  0x21, madd_e_op    =  0x22,
+       msub_s_op    =  0x28, msub_d_op    =  0x29,
+       msub_e_op    =  0x2a, nmadd_s_op   =  0x30,
+       nmadd_d_op   =  0x31, nmadd_e_op   =  0x32,
+       nmsub_s_op   =  0x38, nmsub_d_op   =  0x39,
+       nmsub_e_op   =  0x3a

 };
 
 /*
  * func field for mad opcodes (MIPS IV).
  */
 enum mad_func {
 };
 
 /*
  * func field for mad opcodes (MIPS IV).
  */
 enum mad_func {

-       madd_fp_op      = 0x08, msub_fp_op      = 0x0a,
-       nmadd_fp_op     = 0x0c, nmsub_fp_op     = 0x0e
+       madd_fp_op      = 0x08, msub_fp_op      = 0x0a,
+       nmadd_fp_op     = 0x0c, nmsub_fp_op     = 0x0e

 };
 
 /*
 };
 
 /*


@@ -185,10 +185,10 @@ enum mad_func {
 enum lx_func {
        lwx_op  = 0x00,
        lhx_op  = 0x04,
 enum lx_func {
        lwx_op  = 0x00,
        lhx_op  = 0x04,

-       lbux_op = 0x06,
+       lbux_op = 0x06,

        ldx_op  = 0x08,
        ldx_op  = 0x08,

-       lwux_op = 0x10,
-       lhux_op = 0x14,
+       lwux_op = 0x10,
+       lhux_op = 0x14,

        lbx_op  = 0x16,
 };
 
        lbx_op  = 0x16,
 };
 


@@ -211,7 +211,7 @@ enum lx_func {
 #endif
 
 struct j_format {
 #endif
 
 struct j_format {

-       BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
+       BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */

        BITFIELD_FIELD(unsigned int target : 26,
        ;))
 };
        BITFIELD_FIELD(unsigned int target : 26,
        ;))
 };


@@ -261,7 +261,7 @@ struct p_format {           /* Performance counter format (R10000) */
        ;))))))
 };
 
        ;))))))
 };
 

-struct f_format {                      /* FPU register format */
+struct f_format {                      /* FPU register format */

        BITFIELD_FIELD(unsigned int opcode : 6,
        BITFIELD_FIELD(unsigned int : 1,
        BITFIELD_FIELD(unsigned int fmt : 4,
        BITFIELD_FIELD(unsigned int opcode : 6,
        BITFIELD_FIELD(unsigned int : 1,
        BITFIELD_FIELD(unsigned int fmt : 4,

diff --git a/arch/mips/include/uapi/asm/ioctls.h b/arch/mips/include/uapi/asm/ioctls.h
index addd56b60694fcc2a40d8f4e9a2c5c3a389eacc1..b1e637757fe342a1d848251f2c4a8d4d5f27ab01 100644 (file)
--- a/arch/mips/include/uapi/asm/ioctls.h
+++ b/arch/mips/include/uapi/asm/ioctls.h
@@ -41,7 +41,7 @@
 #define         TIOCPKT_START          0x08    /* start output */
 #define         TIOCPKT_NOSTOP         0x10    /* no more ^S, ^Q */
 #define         TIOCPKT_DOSTOP         0x20    /* now do ^S ^Q */
 #define         TIOCPKT_START          0x08    /* start output */
 #define         TIOCPKT_NOSTOP         0x10    /* no more ^S, ^Q */
 #define         TIOCPKT_DOSTOP         0x20    /* now do ^S ^Q */

-#define  TIOCPKT_IOCTL         0x40    /* state change of pty driver */
+#define         TIOCPKT_IOCTL          0x40    /* state change of pty driver */

 #define TIOCSWINSZ     _IOW('t', 103, struct winsize)  /* set window size */
 #define TIOCGWINSZ     _IOR('t', 104, struct winsize)  /* get window size */
 #define TIOCNOTTY      0x5471          /* void tty association */
 #define TIOCSWINSZ     _IOW('t', 103, struct winsize)  /* set window size */
 #define TIOCGWINSZ     _IOR('t', 104, struct winsize)  /* get window size */
 #define TIOCNOTTY      0x5471          /* void tty association */


@@ -63,9 +63,9 @@
 #define FIONREAD       0x467f
 #define TIOCINQ                FIONREAD
 
 #define FIONREAD       0x467f
 #define TIOCINQ                FIONREAD
 

-#define TIOCGETP        0x7408
-#define TIOCSETP        0x7409
-#define TIOCSETN        0x740a                 /* TIOCSETP wo flush */
+#define TIOCGETP       0x7408
+#define TIOCSETP       0x7409
+#define TIOCSETN       0x740a                  /* TIOCSETP wo flush */

 
 /* #define TIOCSETA    _IOW('t', 20, struct termios) set termios struct */
 /* #define TIOCSETAW   _IOW('t', 21, struct termios) drain output, set */
 
 /* #define TIOCSETA    _IOW('t', 20, struct termios) set termios struct */
 /* #define TIOCSETAW   _IOW('t', 21, struct termios) drain output, set */


@@ -74,9 +74,9 @@
 /* #define TIOCSETD    _IOW('t', 27, int)      set line discipline */
                                                /* 127-124 compat */
 
 /* #define TIOCSETD    _IOW('t', 27, int)      set line discipline */
                                                /* 127-124 compat */
 

-#define TIOCSBRK       0x5427  /* BSD compatibility */
-#define TIOCCBRK       0x5428  /* BSD compatibility */
-#define TIOCGSID       0x7416  /* Return the session ID of FD */
+#define TIOCSBRK       0x5427  /* BSD compatibility */
+#define TIOCCBRK       0x5428  /* BSD compatibility */
+#define TIOCGSID       0x7416  /* Return the session ID of FD */

 #define TCGETS2                _IOR('T', 0x2A, struct termios2)
 #define TCSETS2                _IOW('T', 0x2B, struct termios2)
 #define TCSETSW2       _IOW('T', 0x2C, struct termios2)
 #define TCGETS2                _IOR('T', 0x2A, struct termios2)
 #define TCSETS2                _IOW('T', 0x2B, struct termios2)
 #define TCSETSW2       _IOW('T', 0x2C, struct termios2)


@@ -104,10 +104,10 @@
 #define TIOCGLCKTRMIOS 0x548b
 #define TIOCSLCKTRMIOS 0x548c
 #define TIOCSERGSTRUCT 0x548d /* For debugging only */
 #define TIOCGLCKTRMIOS 0x548b
 #define TIOCSLCKTRMIOS 0x548c
 #define TIOCSERGSTRUCT 0x548d /* For debugging only */

-#define TIOCSERGETLSR   0x548e /* Get line status register */
-#define TIOCSERGETMULTI 0x548f /* Get multiport config  */
+#define TIOCSERGETLSR  0x548e /* Get line status register */
+#define TIOCSERGETMULTI 0x548f /* Get multiport config */

 #define TIOCSERSETMULTI 0x5490 /* Set multiport config */
 #define TIOCSERSETMULTI 0x5490 /* Set multiport config */

-#define TIOCMIWAIT      0x5491 /* wait for a change on serial input line(s) */
-#define TIOCGICOUNT     0x5492 /* read serial port inline interrupt counts */
+#define TIOCMIWAIT     0x5491 /* wait for a change on serial input line(s) */
+#define TIOCGICOUNT    0x5492 /* read serial port inline interrupt counts */

 
 #endif /* __ASM_IOCTLS_H */
 
 #endif /* __ASM_IOCTLS_H */

diff --git a/arch/mips/include/uapi/asm/mman.h b/arch/mips/include/uapi/asm/mman.h
index 9a936ac9a9424d3433bbfd546bf292d65dd42547..cfcb876cae6bc017e7fbf53e3df33fdc637680f3 100644 (file)
--- a/arch/mips/include/uapi/asm/mman.h
+++ b/arch/mips/include/uapi/asm/mman.h
@@ -64,7 +64,7 @@
 
 #define MADV_NORMAL    0               /* no further special treatment */
 #define MADV_RANDOM    1               /* expect random page references */
 
 #define MADV_NORMAL    0               /* no further special treatment */
 #define MADV_RANDOM    1               /* expect random page references */

-#define MADV_SEQUENTIAL        2               /* expect sequential page references */
+#define MADV_SEQUENTIAL 2              /* expect sequential page references */

 #define MADV_WILLNEED  3               /* will need these pages */
 #define MADV_DONTNEED  4               /* don't need these pages */
 
 #define MADV_WILLNEED  3               /* will need these pages */
 #define MADV_DONTNEED  4               /* don't need these pages */
 


@@ -73,14 +73,14 @@
 #define MADV_DONTFORK  10              /* don't inherit across fork */
 #define MADV_DOFORK    11              /* do inherit across fork */
 
 #define MADV_DONTFORK  10              /* don't inherit across fork */
 #define MADV_DOFORK    11              /* do inherit across fork */
 

-#define MADV_MERGEABLE   12            /* KSM may merge identical pages */
+#define MADV_MERGEABLE  12             /* KSM may merge identical pages */

 #define MADV_UNMERGEABLE 13            /* KSM may not merge identical pages */
 #define MADV_UNMERGEABLE 13            /* KSM may not merge identical pages */

-#define MADV_HWPOISON    100           /* poison a page for testing */
+#define MADV_HWPOISON   100            /* poison a page for testing */

 
 #define MADV_HUGEPAGE  14              /* Worth backing with hugepages */
 
 #define MADV_HUGEPAGE  14              /* Worth backing with hugepages */

-#define MADV_NOHUGEPAGE        15              /* Not worth backing with hugepages */
+#define MADV_NOHUGEPAGE 15             /* Not worth backing with hugepages */

 
 

-#define MADV_DONTDUMP   16             /* Explicity exclude from the core dump,
+#define MADV_DONTDUMP  16              /* Explicity exclude from the core dump,

                                           overrides the coredump filter bits */
 #define MADV_DODUMP    17              /* Clear the MADV_NODUMP flag */
 
                                           overrides the coredump filter bits */
 #define MADV_DODUMP    17              /* Clear the MADV_NODUMP flag */
 

diff --git a/arch/mips/include/uapi/asm/ptrace.h b/arch/mips/include/uapi/asm/ptrace.h
index 1bc1f52f40d78879bbb8d613b318c68458cf1235..4d58d8468705940a77764f2615946a7c89485807 100644 (file)
--- a/arch/mips/include/uapi/asm/ptrace.h
+++ b/arch/mips/include/uapi/asm/ptrace.h
@@ -49,8 +49,8 @@ struct pt_regs {
        unsigned long cp0_tcstatus;
 #endif /* CONFIG_MIPS_MT_SMTC */
 #ifdef CONFIG_CPU_CAVIUM_OCTEON
        unsigned long cp0_tcstatus;
 #endif /* CONFIG_MIPS_MT_SMTC */
 #ifdef CONFIG_CPU_CAVIUM_OCTEON

-       unsigned long long mpl[3];        /* MTM{0,1,2} */
-       unsigned long long mtp[3];        /* MTP{0,1,2} */
+       unsigned long long mpl[3];        /* MTM{0,1,2} */
+       unsigned long long mtp[3];        /* MTP{0,1,2} */

 #endif
 } __attribute__ ((aligned (8)));
 
 #endif
 } __attribute__ ((aligned (8)));
 


@@ -67,14 +67,14 @@ struct pt_regs {
 #define PTRACE_GET_THREAD_AREA 25
 #define PTRACE_SET_THREAD_AREA 26
 
 #define PTRACE_GET_THREAD_AREA 25
 #define PTRACE_SET_THREAD_AREA 26
 

-/* Calls to trace a 64bit program from a 32bit program.  */
+/* Calls to trace a 64bit program from a 32bit program.         */

 #define PTRACE_PEEKTEXT_3264   0xc0
 #define PTRACE_PEEKDATA_3264   0xc1
 #define PTRACE_POKETEXT_3264   0xc2
 #define PTRACE_POKEDATA_3264   0xc3
 #define PTRACE_GET_THREAD_AREA_3264    0xc4
 
 #define PTRACE_PEEKTEXT_3264   0xc0
 #define PTRACE_PEEKDATA_3264   0xc1
 #define PTRACE_POKETEXT_3264   0xc2
 #define PTRACE_POKEDATA_3264   0xc3
 #define PTRACE_GET_THREAD_AREA_3264    0xc4
 

-/* Read and write watchpoint registers.  */
+/* Read and write watchpoint registers.         */

 enum pt_watch_style {
        pt_watch_style_mips32,
        pt_watch_style_mips64
 enum pt_watch_style {
        pt_watch_style_mips32,
        pt_watch_style_mips64

diff --git a/arch/mips/include/uapi/asm/sembuf.h b/arch/mips/include/uapi/asm/sembuf.h
index 7281a4decaa0162da34d1d717efb22fde5ad4a50..e1085ac880f2ec14afce2950b96ffbf91fd7185e 100644 (file)
--- a/arch/mips/include/uapi/asm/sembuf.h
+++ b/arch/mips/include/uapi/asm/sembuf.h
@@ -12,8 +12,8 @@
 
 struct semid64_ds {
        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
 
 struct semid64_ds {
        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */

-       __kernel_time_t sem_otime;              /* last semop time */
-       __kernel_time_t sem_ctime;              /* last change time */
+       __kernel_time_t sem_otime;              /* last semop time */
+       __kernel_time_t sem_ctime;              /* last change time */

        unsigned long   sem_nsems;              /* no. of semaphores in array */
        unsigned long   __unused1;
        unsigned long   __unused2;
        unsigned long   sem_nsems;              /* no. of semaphores in array */
        unsigned long   __unused1;
        unsigned long   __unused2;

diff --git a/arch/mips/include/uapi/asm/siginfo.h b/arch/mips/include/uapi/asm/siginfo.h
index 73446508d84620efb1bd22fcab96324fdc99f8b5..6a8714193fb9b03ad5bdeb753642e1622247961d 100644 (file)
--- a/arch/mips/include/uapi/asm/siginfo.h
+++ b/arch/mips/include/uapi/asm/siginfo.h
@@ -11,7 +11,7 @@
 
 
 #define __ARCH_SIGEV_PREAMBLE_SIZE (sizeof(long) + 2*sizeof(int))
 
 
 #define __ARCH_SIGEV_PREAMBLE_SIZE (sizeof(long) + 2*sizeof(int))

-#undef __ARCH_SI_TRAPNO        /* exception code needs to fill this ...  */
+#undef __ARCH_SI_TRAPNO /* exception code needs to fill this ...  */

 
 #define HAVE_ARCH_SIGINFO_T
 
 
 #define HAVE_ARCH_SIGINFO_T
 


@@ -55,7 +55,7 @@ typedef struct siginfo {
                        int _overrun;           /* overrun count */
                        char _pad[sizeof( __ARCH_SI_UID_T) - sizeof(int)];
                        sigval_t _sigval;       /* same as below */
                        int _overrun;           /* overrun count */
                        char _pad[sizeof( __ARCH_SI_UID_T) - sizeof(int)];
                        sigval_t _sigval;       /* same as below */

-                       int _sys_private;       /* not to be passed to user */
+                       int _sys_private;       /* not to be passed to user */

                } _timer;
 
                /* POSIX.1b signals */
                } _timer;
 
                /* POSIX.1b signals */


@@ -91,9 +91,9 @@ typedef struct siginfo {
                        short _addr_lsb;
                } _sigfault;
 
                        short _addr_lsb;
                } _sigfault;
 

-               /* SIGPOLL, SIGXFSZ (To do ...)  */
+               /* SIGPOLL, SIGXFSZ (To do ...)  */

                struct {
                struct {

-                       __ARCH_SI_BAND_T _band; /* POLL_IN, POLL_OUT, POLL_MSG */
+                       __ARCH_SI_BAND_T _band; /* POLL_IN, POLL_OUT, POLL_MSG */

                        int _fd;
                } _sigpoll;
        } _sifields;
                        int _fd;
                } _sigpoll;
        } _sifields;

diff --git a/arch/mips/include/uapi/asm/signal.h b/arch/mips/include/uapi/asm/signal.h
index 770732cb8d0387e6ce692b0eae45d205681608d1..e66e3984b1d4307e1e5f43f94db688938d4882a6 100644 (file)
--- a/arch/mips/include/uapi/asm/signal.h
+++ b/arch/mips/include/uapi/asm/signal.h
@@ -24,28 +24,28 @@ typedef unsigned long old_sigset_t;         /* at least 32 bits */
 #define SIGHUP          1      /* Hangup (POSIX).  */
 #define SIGINT          2      /* Interrupt (ANSI).  */
 #define SIGQUIT                 3      /* Quit (POSIX).  */
 #define SIGHUP          1      /* Hangup (POSIX).  */
 #define SIGINT          2      /* Interrupt (ANSI).  */
 #define SIGQUIT                 3      /* Quit (POSIX).  */

-#define SIGILL          4      /* Illegal instruction (ANSI).  */
-#define SIGTRAP                 5      /* Trace trap (POSIX).  */
-#define SIGIOT          6      /* IOT trap (4.2 BSD).  */
-#define SIGABRT                 SIGIOT /* Abort (ANSI).  */
+#define SIGILL          4      /* Illegal instruction (ANSI).  */
+#define SIGTRAP                 5      /* Trace trap (POSIX).  */
+#define SIGIOT          6      /* IOT trap (4.2 BSD).  */
+#define SIGABRT                 SIGIOT /* Abort (ANSI).  */

 #define SIGEMT          7
 #define SIGFPE          8      /* Floating-point exception (ANSI).  */
 #define SIGKILL                 9      /* Kill, unblockable (POSIX).  */
 #define SIGEMT          7
 #define SIGFPE          8      /* Floating-point exception (ANSI).  */
 #define SIGKILL                 9      /* Kill, unblockable (POSIX).  */

-#define SIGBUS         10      /* BUS error (4.2 BSD).  */
+#define SIGBUS         10      /* BUS error (4.2 BSD).  */

 #define SIGSEGV                11      /* Segmentation violation (ANSI).  */
 #define SIGSYS         12
 #define SIGSEGV                11      /* Segmentation violation (ANSI).  */
 #define SIGSYS         12

-#define SIGPIPE                13      /* Broken pipe (POSIX).  */
-#define SIGALRM                14      /* Alarm clock (POSIX).  */
-#define SIGTERM                15      /* Termination (ANSI).  */
+#define SIGPIPE                13      /* Broken pipe (POSIX).  */
+#define SIGALRM                14      /* Alarm clock (POSIX).  */
+#define SIGTERM                15      /* Termination (ANSI).  */

 #define SIGUSR1                16      /* User-defined signal 1 (POSIX).  */
 #define SIGUSR2                17      /* User-defined signal 2 (POSIX).  */
 #define SIGCHLD                18      /* Child status has changed (POSIX).  */
 #define SIGUSR1                16      /* User-defined signal 1 (POSIX).  */
 #define SIGUSR2                17      /* User-defined signal 2 (POSIX).  */
 #define SIGCHLD                18      /* Child status has changed (POSIX).  */

-#define SIGCLD         SIGCHLD /* Same as SIGCHLD (System V).  */
+#define SIGCLD         SIGCHLD /* Same as SIGCHLD (System V).  */

 #define SIGPWR         19      /* Power failure restart (System V).  */
 #define SIGWINCH       20      /* Window size change (4.3 BSD, Sun).  */
 #define SIGURG         21      /* Urgent condition on socket (4.2 BSD).  */
 #define SIGPWR         19      /* Power failure restart (System V).  */
 #define SIGWINCH       20      /* Window size change (4.3 BSD, Sun).  */
 #define SIGURG         21      /* Urgent condition on socket (4.2 BSD).  */

-#define SIGIO          22      /* I/O now possible (4.2 BSD).  */
-#define SIGPOLL                SIGIO   /* Pollable event occurred (System V).  */
+#define SIGIO          22      /* I/O now possible (4.2 BSD).  */
+#define SIGPOLL                SIGIO   /* Pollable event occurred (System V).  */

 #define SIGSTOP                23      /* Stop, unblockable (POSIX).  */
 #define SIGTSTP                24      /* Keyboard stop (POSIX).  */
 #define SIGCONT                25      /* Continue (POSIX).  */
 #define SIGSTOP                23      /* Stop, unblockable (POSIX).  */
 #define SIGTSTP                24      /* Keyboard stop (POSIX).  */
 #define SIGCONT                25      /* Continue (POSIX).  */


@@ -54,7 +54,7 @@ typedef unsigned long old_sigset_t;           /* at least 32 bits */
 #define SIGVTALRM      28      /* Virtual alarm clock (4.2 BSD).  */
 #define SIGPROF                29      /* Profiling alarm clock (4.2 BSD).  */
 #define SIGXCPU                30      /* CPU limit exceeded (4.2 BSD).  */
 #define SIGVTALRM      28      /* Virtual alarm clock (4.2 BSD).  */
 #define SIGPROF                29      /* Profiling alarm clock (4.2 BSD).  */
 #define SIGXCPU                30      /* CPU limit exceeded (4.2 BSD).  */

-#define SIGXFSZ                31      /* File size limit exceeded (4.2 BSD).  */
+#define SIGXFSZ                31      /* File size limit exceeded (4.2 BSD).  */

 
 /* These should not be considered constants from userland.  */
 #define SIGRTMIN       32
 
 /* These should not be considered constants from userland.  */
 #define SIGRTMIN       32

diff --git a/arch/mips/include/uapi/asm/socket.h b/arch/mips/include/uapi/asm/socket.h
index 17307ab90474271e4c77f9d48bfb775f2049db74..cc208f9f89201e40868f839225356fd7ede2658b 100644 (file)
--- a/arch/mips/include/uapi/asm/socket.h
+++ b/arch/mips/include/uapi/asm/socket.h
@@ -24,23 +24,23 @@
                                   SIGPIPE when they die.  */
 #define SO_DONTROUTE   0x0010  /* Don't do local routing.  */
 #define SO_BROADCAST   0x0020  /* Allow transmission of
                                   SIGPIPE when they die.  */
 #define SO_DONTROUTE   0x0010  /* Don't do local routing.  */
 #define SO_BROADCAST   0x0020  /* Allow transmission of

-                                  broadcast messages.  */
+                                  broadcast messages.  */

 #define SO_LINGER      0x0080  /* Block on close of a reliable
                                   socket to transmit pending data.  */
 #define SO_OOBINLINE 0x0100    /* Receive out-of-band data in-band.  */
 #if 0
 #define SO_LINGER      0x0080  /* Block on close of a reliable
                                   socket to transmit pending data.  */
 #define SO_OOBINLINE 0x0100    /* Receive out-of-band data in-band.  */
 #if 0

-To add: #define SO_REUSEPORT 0x0200    /* Allow local address and port reuse.  */
+To add: #define SO_REUSEPORT 0x0200    /* Allow local address and port reuse.  */

 #endif
 
 #define SO_TYPE                0x1008  /* Compatible name for SO_STYLE.  */
 #endif
 
 #define SO_TYPE                0x1008  /* Compatible name for SO_STYLE.  */

-#define SO_STYLE       SO_TYPE /* Synonym */
+#define SO_STYLE       SO_TYPE /* Synonym */

 #define SO_ERROR       0x1007  /* get error status and clear */
 #define SO_SNDBUF      0x1001  /* Send buffer size. */
 #define SO_RCVBUF      0x1002  /* Receive buffer. */
 #define SO_SNDLOWAT    0x1003  /* send low-water mark */
 #define SO_RCVLOWAT    0x1004  /* receive low-water mark */
 #define SO_SNDTIMEO    0x1005  /* send timeout */
 #define SO_ERROR       0x1007  /* get error status and clear */
 #define SO_SNDBUF      0x1001  /* Send buffer size. */
 #define SO_RCVBUF      0x1002  /* Receive buffer. */
 #define SO_SNDLOWAT    0x1003  /* send low-water mark */
 #define SO_RCVLOWAT    0x1004  /* receive low-water mark */
 #define SO_SNDTIMEO    0x1005  /* send timeout */

-#define SO_RCVTIMEO    0x1006  /* receive timeout */
+#define SO_RCVTIMEO    0x1006  /* receive timeout */

 #define SO_ACCEPTCONN  0x1009
 #define SO_PROTOCOL    0x1028  /* protocol type */
 #define SO_DOMAIN      0x1029  /* domain/socket family */
 #define SO_ACCEPTCONN  0x1009
 #define SO_PROTOCOL    0x1028  /* protocol type */
 #define SO_DOMAIN      0x1029  /* domain/socket family */


@@ -61,11 +61,11 @@ To add: #define SO_REUSEPORT 0x0200 /* Allow local address and port reuse.  */
 #define SO_BINDTODEVICE                25
 
 /* Socket filtering */
 #define SO_BINDTODEVICE                25
 
 /* Socket filtering */

-#define SO_ATTACH_FILTER        26
-#define SO_DETACH_FILTER        27
+#define SO_ATTACH_FILTER       26
+#define SO_DETACH_FILTER       27

 #define SO_GET_FILTER          SO_ATTACH_FILTER
 
 #define SO_GET_FILTER          SO_ATTACH_FILTER
 

-#define SO_PEERNAME             28
+#define SO_PEERNAME            28

 #define SO_TIMESTAMP           29
 #define SCM_TIMESTAMP          SO_TIMESTAMP
 
 #define SO_TIMESTAMP           29
 #define SCM_TIMESTAMP          SO_TIMESTAMP
 


@@ -81,7 +81,7 @@ To add: #define SO_REUSEPORT 0x0200   /* Allow local address and port reuse.  */
 #define SO_TIMESTAMPING                37
 #define SCM_TIMESTAMPING       SO_TIMESTAMPING
 
 #define SO_TIMESTAMPING                37
 #define SCM_TIMESTAMPING       SO_TIMESTAMPING
 

-#define SO_RXQ_OVFL             40
+#define SO_RXQ_OVFL            40

 
 #define SO_WIFI_STATUS         41
 #define SCM_WIFI_STATUS                SO_WIFI_STATUS
 
 #define SO_WIFI_STATUS         41
 #define SCM_WIFI_STATUS                SO_WIFI_STATUS

diff --git a/arch/mips/include/uapi/asm/sockios.h b/arch/mips/include/uapi/asm/sockios.h
index ed1a5f78d22f401b58cfd303ea322b7e54d706e4..419fbe661da32994a1c45b28cccdf9822068df57 100644 (file)
--- a/arch/mips/include/uapi/asm/sockios.h
+++ b/arch/mips/include/uapi/asm/sockios.h
@@ -14,7 +14,7 @@
 
 /* Socket-level I/O control calls. */
 #define FIOGETOWN      _IOR('f', 123, int)
 
 /* Socket-level I/O control calls. */
 #define FIOGETOWN      _IOR('f', 123, int)

-#define FIOSETOWN      _IOW('f', 124, int)
+#define FIOSETOWN      _IOW('f', 124, int)

 
 #define SIOCATMARK     _IOR('s', 7, int)
 #define SIOCSPGRP      _IOW('s', 8, pid_t)
 
 #define SIOCATMARK     _IOR('s', 7, int)
 #define SIOCSPGRP      _IOW('s', 8, pid_t)

diff --git a/arch/mips/include/uapi/asm/stat.h b/arch/mips/include/uapi/asm/stat.h
index fe9a4c3ec5a1f2d9f557adf7c32348b0c892e374..b47bc541bbc07133e58390c1d52e9baa3bba2fbe 100644 (file)
--- a/arch/mips/include/uapi/asm/stat.h
+++ b/arch/mips/include/uapi/asm/stat.h
@@ -23,7 +23,7 @@ struct stat {
        __u32           st_nlink;
        uid_t           st_uid;
        gid_t           st_gid;
        __u32           st_nlink;
        uid_t           st_uid;
        gid_t           st_gid;

-       unsigned        st_rdev;
+       unsigned        st_rdev;

        long            st_pad2[2];
        off_t           st_size;
        long            st_pad3;
        long            st_pad2[2];
        off_t           st_size;
        long            st_pad3;

diff --git a/arch/mips/include/uapi/asm/statfs.h b/arch/mips/include/uapi/asm/statfs.h
index 0f805c7a42a5a45c3dd880abf022843d70e6a496..3305c834fc1644989d0b2e8e2d24ff191bb26d49 100644 (file)
--- a/arch/mips/include/uapi/asm/statfs.h
+++ b/arch/mips/include/uapi/asm/statfs.h
@@ -15,7 +15,7 @@
 
 #include <linux/types.h>
 
 
 #include <linux/types.h>
 

-typedef __kernel_fsid_t        fsid_t;
+typedef __kernel_fsid_t               fsid_t;

 
 #endif
 
 
 #endif
 


@@ -31,7 +31,7 @@ struct statfs {
        long            f_bavail;
 
        /* Linux specials */
        long            f_bavail;
 
        /* Linux specials */

-       __kernel_fsid_t f_fsid;
+       __kernel_fsid_t f_fsid;

        long            f_namelen;
        long            f_flags;
        long            f_spare[5];
        long            f_namelen;
        long            f_flags;
        long            f_spare[5];


@@ -73,7 +73,7 @@ struct statfs64 {                     /* Same as struct statfs */
        long            f_bavail;
 
        /* Linux specials */
        long            f_bavail;
 
        /* Linux specials */

-       __kernel_fsid_t f_fsid;
+       __kernel_fsid_t f_fsid;

        long            f_namelen;
        long            f_flags;
        long            f_spare[5];
        long            f_namelen;
        long            f_flags;
        long            f_spare[5];

diff --git a/arch/mips/include/uapi/asm/sysmips.h b/arch/mips/include/uapi/asm/sysmips.h
index 4f47b7d6a5f71490a92aedc89b6591aa09a5fb4e..ae637e9078562305f094dffbd56a4b78ad23a4ed 100644 (file)
--- a/arch/mips/include/uapi/asm/sysmips.h
+++ b/arch/mips/include/uapi/asm/sysmips.h
@@ -16,10 +16,10 @@
  * sysmips(2) is deprecated - though some existing software uses it.
  * We only support the following commands.
  */
  * sysmips(2) is deprecated - though some existing software uses it.
  * We only support the following commands.
  */

-#define SETNAME                    1   /* set hostname                  */
+#define SETNAME                           1    /* set hostname                  */

 #define FLUSH_CACHE               3    /* writeback and invalidate caches */
 #define FLUSH_CACHE               3    /* writeback and invalidate caches */

-#define MIPS_FIXADE                7   /* control address error fixing  */
-#define MIPS_RDNVRAM              10   /* read NVRAM */
-#define MIPS_ATOMIC_SET                2001    /* atomically set variable       */
+#define MIPS_FIXADE               7    /* control address error fixing  */
+#define MIPS_RDNVRAM             10    /* read NVRAM */
+#define MIPS_ATOMIC_SET                2001    /* atomically set variable       */

 
 #endif /* _ASM_SYSMIPS_H */
 
 #endif /* _ASM_SYSMIPS_H */

diff --git a/arch/mips/include/uapi/asm/termbits.h b/arch/mips/include/uapi/asm/termbits.h
index 76630b396fac3b2545fd9260b0addad0b04bd069..2750203e1e7d1760c650e7d5802c4da1b595c61b 100644 (file)
--- a/arch/mips/include/uapi/asm/termbits.h
+++ b/arch/mips/include/uapi/asm/termbits.h
@@ -53,7 +53,7 @@ struct ktermios {
 };
 
 /* c_cc characters */
 };
 
 /* c_cc characters */

-#define VINTR           0              /* Interrupt character [ISIG].  */
+#define VINTR           0              /* Interrupt character [ISIG].  */

 #define VQUIT           1              /* Quit character [ISIG].  */
 #define VERASE          2              /* Erase character [ICANON].  */
 #define VKILL           3              /* Kill-line character [ICANON].  */
 #define VQUIT           1              /* Quit character [ISIG].  */
 #define VERASE          2              /* Erase character [ICANON].  */
 #define VKILL           3              /* Kill-line character [ICANON].  */


@@ -72,7 +72,7 @@ struct ktermios {
 #define VDSUSP         11              /* Delayed suspend character [ISIG].  */
 #endif
 #define VREPRINT       12              /* Reprint-line character [ICANON].  */
 #define VDSUSP         11              /* Delayed suspend character [ISIG].  */
 #endif
 #define VREPRINT       12              /* Reprint-line character [ICANON].  */

-#define VDISCARD       13              /* Discard character [IEXTEN].  */
+#define VDISCARD       13              /* Discard character [IEXTEN].  */

 #define VWERASE                14              /* Word-erase character [ICANON].  */
 #define VLNEXT         15              /* Literal-next character [IEXTEN].  */
 #define VEOF           16              /* End-of-file character [ICANON].  */
 #define VWERASE                14              /* Word-erase character [ICANON].  */
 #define VLNEXT         15              /* Literal-next character [IEXTEN].  */
 #define VEOF           16              /* End-of-file character [ICANON].  */


@@ -92,7 +92,7 @@ struct ktermios {
 #define IXON   0002000         /* Enable start/stop output control.  */
 #define IXANY  0004000         /* Any character will restart after stop.  */
 #define IXOFF  0010000         /* Enable start/stop input control.  */
 #define IXON   0002000         /* Enable start/stop output control.  */
 #define IXANY  0004000         /* Any character will restart after stop.  */
 #define IXOFF  0010000         /* Enable start/stop input control.  */

-#define IMAXBEL        0020000         /* Ring bell when input queue is full.  */
+#define IMAXBEL 0020000                /* Ring bell when input queue is full.  */

 #define IUTF8  0040000         /* Input is UTF-8 */
 
 /* c_oflag bits */
 #define IUTF8  0040000         /* Input is UTF-8 */
 
 /* c_oflag bits */


@@ -105,123 +105,123 @@ struct ktermios {
 #define OFILL  0000100
 #define OFDEL  0000200
 #define NLDLY  0000400
 #define OFILL  0000100
 #define OFDEL  0000200
 #define NLDLY  0000400

-#define   NL0  0000000
-#define   NL1  0000400
+#define          NL0   0000000
+#define          NL1   0000400

 #define CRDLY  0003000
 #define CRDLY  0003000

-#define   CR0  0000000
-#define   CR1  0001000
-#define   CR2  0002000
-#define   CR3  0003000
+#define          CR0   0000000
+#define          CR1   0001000
+#define          CR2   0002000
+#define          CR3   0003000

 #define TABDLY 0014000
 #define TABDLY 0014000

-#define   TAB0 0000000
-#define   TAB1 0004000
-#define   TAB2 0010000
-#define   TAB3 0014000
-#define   XTABS        0014000
+#define          TAB0  0000000
+#define          TAB1  0004000
+#define          TAB2  0010000
+#define          TAB3  0014000
+#define          XTABS 0014000

 #define BSDLY  0020000
 #define BSDLY  0020000

-#define   BS0  0000000
-#define   BS1  0020000
+#define          BS0   0000000
+#define          BS1   0020000

 #define VTDLY  0040000
 #define VTDLY  0040000

-#define   VT0  0000000
-#define   VT1  0040000
+#define          VT0   0000000
+#define          VT1   0040000

 #define FFDLY  0100000
 #define FFDLY  0100000

-#define   FF0  0000000
-#define   FF1  0100000
+#define          FF0   0000000
+#define          FF1   0100000

 /*
 #define PAGEOUT ???
 /*
 #define PAGEOUT ???

-#define WRAP    ???
+#define WRAP   ???

  */
 
 /* c_cflag bit meaning */
 #define CBAUD  0010017
  */
 
 /* c_cflag bit meaning */
 #define CBAUD  0010017

-#define  B0    0000000         /* hang up */
-#define  B50   0000001
-#define  B75   0000002
-#define  B110  0000003
-#define  B134  0000004
-#define  B150  0000005
-#define  B200  0000006
-#define  B300  0000007
-#define  B600  0000010
-#define  B1200 0000011
-#define  B1800 0000012
-#define  B2400 0000013
-#define  B4800 0000014
-#define  B9600 0000015
-#define  B19200        0000016
-#define  B38400        0000017
+#define         B0     0000000         /* hang up */
+#define         B50    0000001
+#define         B75    0000002
+#define         B110   0000003
+#define         B134   0000004
+#define         B150   0000005
+#define         B200   0000006
+#define         B300   0000007
+#define         B600   0000010
+#define         B1200  0000011
+#define         B1800  0000012
+#define         B2400  0000013
+#define         B4800  0000014
+#define         B9600  0000015
+#define         B19200 0000016
+#define         B38400 0000017

 #define EXTA B19200
 #define EXTB B38400
 #define CSIZE  0000060         /* Number of bits per byte (mask).  */
 #define EXTA B19200
 #define EXTB B38400
 #define CSIZE  0000060         /* Number of bits per byte (mask).  */

-#define   CS5  0000000         /* 5 bits per byte.  */
-#define   CS6  0000020         /* 6 bits per byte.  */
-#define   CS7  0000040         /* 7 bits per byte.  */
-#define   CS8  0000060         /* 8 bits per byte.  */
+#define          CS5   0000000         /* 5 bits per byte.  */
+#define          CS6   0000020         /* 6 bits per byte.  */
+#define          CS7   0000040         /* 7 bits per byte.  */
+#define          CS8   0000060         /* 8 bits per byte.  */

 #define CSTOPB 0000100         /* Two stop bits instead of one.  */
 #define CREAD  0000200         /* Enable receiver.  */
 #define PARENB 0000400         /* Parity enable.  */
 #define CSTOPB 0000100         /* Two stop bits instead of one.  */
 #define CREAD  0000200         /* Enable receiver.  */
 #define PARENB 0000400         /* Parity enable.  */

-#define PARODD 0001000         /* Odd parity instead of even.  */
+#define PARODD 0001000         /* Odd parity instead of even.  */

 #define HUPCL  0002000         /* Hang up on last close.  */
 #define CLOCAL 0004000         /* Ignore modem status lines.  */
 #define CBAUDEX 0010000
 #define HUPCL  0002000         /* Hang up on last close.  */
 #define CLOCAL 0004000         /* Ignore modem status lines.  */
 #define CBAUDEX 0010000

-#define    BOTHER 0010000
-#define    B57600 0010001
-#define   B115200 0010002
-#define   B230400 0010003
-#define   B460800 0010004
-#define   B500000 0010005
-#define   B576000 0010006
-#define   B921600 0010007
-#define  B1000000 0010010
-#define  B1152000 0010011
-#define  B1500000 0010012
-#define  B2000000 0010013
-#define  B2500000 0010014
-#define  B3000000 0010015
-#define  B3500000 0010016
-#define  B4000000 0010017
+#define           BOTHER 0010000
+#define           B57600 0010001
+#define          B115200 0010002
+#define          B230400 0010003
+#define          B460800 0010004
+#define          B500000 0010005
+#define          B576000 0010006
+#define          B921600 0010007
+#define         B1000000 0010010
+#define         B1152000 0010011
+#define         B1500000 0010012
+#define         B2000000 0010013
+#define         B2500000 0010014
+#define         B3000000 0010015
+#define         B3500000 0010016
+#define         B4000000 0010017

 #define CIBAUD   002003600000  /* input baud rate */
 #define CIBAUD   002003600000  /* input baud rate */

-#define CMSPAR    010000000000 /* mark or space (stick) parity */
+#define CMSPAR   010000000000  /* mark or space (stick) parity */

 #define CRTSCTS          020000000000  /* flow control */
 
 #define CRTSCTS          020000000000  /* flow control */
 

-#define IBSHIFT        16              /* Shift from CBAUD to CIBAUD */
+#define IBSHIFT 16             /* Shift from CBAUD to CIBAUD */

 
 /* c_lflag bits */
 #define ISIG   0000001         /* Enable signals.  */
 #define ICANON 0000002         /* Do erase and kill processing.  */
 #define XCASE  0000004
 
 /* c_lflag bits */
 #define ISIG   0000001         /* Enable signals.  */
 #define ICANON 0000002         /* Do erase and kill processing.  */
 #define XCASE  0000004

-#define ECHO   0000010         /* Enable echo.  */
+#define ECHO   0000010         /* Enable echo.  */

 #define ECHOE  0000020         /* Visual erase for ERASE.  */
 #define ECHOE  0000020         /* Visual erase for ERASE.  */

-#define ECHOK  0000040         /* Echo NL after KILL.  */
-#define ECHONL 0000100         /* Echo NL even if ECHO is off.  */
+#define ECHOK  0000040         /* Echo NL after KILL.  */
+#define ECHONL 0000100         /* Echo NL even if ECHO is off.  */

 #define NOFLSH 0000200         /* Disable flush after interrupt.  */
 #define IEXTEN 0000400         /* Enable DISCARD and LNEXT.  */
 #define NOFLSH 0000200         /* Disable flush after interrupt.  */
 #define IEXTEN 0000400         /* Enable DISCARD and LNEXT.  */

-#define ECHOCTL        0001000         /* Echo control characters as ^X.  */
-#define ECHOPRT        0002000         /* Hardcopy visual erase.  */
+#define ECHOCTL 0001000                /* Echo control characters as ^X.  */
+#define ECHOPRT 0002000                /* Hardcopy visual erase.  */

 #define ECHOKE 0004000         /* Visual erase for KILL.  */
 #define FLUSHO 0020000
 #define PENDIN 0040000         /* Retype pending input (state).  */
 #define ECHOKE 0004000         /* Visual erase for KILL.  */
 #define FLUSHO 0020000
 #define PENDIN 0040000         /* Retype pending input (state).  */

-#define TOSTOP 0100000         /* Send SIGTTOU for background output.  */
-#define ITOSTOP        TOSTOP
-#define EXTPROC        0200000         /* External processing on pty */
+#define TOSTOP 0100000         /* Send SIGTTOU for background output.  */
+#define ITOSTOP TOSTOP
+#define EXTPROC 0200000                /* External processing on pty */

 
 /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
 
 /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */

-#define TIOCSER_TEMT    0x01   /* Transmitter physically empty */
+#define TIOCSER_TEMT   0x01    /* Transmitter physically empty */

 
 /* tcflow() and TCXONC use these */
 
 /* tcflow() and TCXONC use these */

-#define        TCOOFF          0       /* Suspend output.  */
-#define        TCOON           1       /* Restart suspended output.  */
-#define        TCIOFF          2       /* Send a STOP character.  */
-#define        TCION           3       /* Send a START character.  */
+#define TCOOFF         0       /* Suspend output.  */
+#define TCOON          1       /* Restart suspended output.  */
+#define TCIOFF         2       /* Send a STOP character.  */
+#define TCION          3       /* Send a START character.  */

 
 /* tcflush() and TCFLSH use these */
 
 /* tcflush() and TCFLSH use these */

-#define        TCIFLUSH        0       /* Discard data received but not yet read.  */
-#define        TCOFLUSH        1       /* Discard data written but not yet sent.  */
-#define        TCIOFLUSH       2       /* Discard all pending data.  */
+#define TCIFLUSH       0       /* Discard data received but not yet read.  */
+#define TCOFLUSH       1       /* Discard data written but not yet sent.  */
+#define TCIOFLUSH      2       /* Discard all pending data.  */

 
 /* tcsetattr uses these */
 
 /* tcsetattr uses these */

-#define        TCSANOW         TCSETS  /* Change immediately.  */
-#define        TCSADRAIN       TCSETSW /* Change when pending output is written.  */
-#define        TCSAFLUSH       TCSETSF /* Flush pending input before changing.  */
+#define TCSANOW                TCSETS  /* Change immediately.  */
+#define TCSADRAIN      TCSETSW /* Change when pending output is written.  */
+#define TCSAFLUSH      TCSETSF /* Flush pending input before changing.  */

 
 #endif /* _ASM_TERMBITS_H */
 
 #endif /* _ASM_TERMBITS_H */

diff --git a/arch/mips/include/uapi/asm/termios.h b/arch/mips/include/uapi/asm/termios.h
index 574fbdfb72029e2f898c2a4fedb2c68d8a0491ad..baeb2fa874512e6c46067179478e8eac543cddc2 100644 (file)
--- a/arch/mips/include/uapi/asm/termios.h
+++ b/arch/mips/include/uapi/asm/termios.h
@@ -31,12 +31,12 @@ struct tchars {
 };
 
 struct ltchars {
 };
 
 struct ltchars {

-        char    t_suspc;        /* stop process signal */
-        char    t_dsuspc;       /* delayed stop process signal */
-        char    t_rprntc;       /* reprint line */
-        char    t_flushc;       /* flush output (toggles) */
-        char    t_werasc;       /* word erase */
-        char    t_lnextc;       /* literal next character */
+       char    t_suspc;        /* stop process signal */
+       char    t_dsuspc;       /* delayed stop process signal */
+       char    t_rprntc;       /* reprint line */
+       char    t_flushc;       /* flush output (toggles) */
+       char    t_werasc;       /* word erase */
+       char    t_lnextc;       /* literal next character */

 };
 
 /* TIOCGSIZE, TIOCSSIZE not defined yet.  Only needed for SunOS source
 };
 
 /* TIOCGSIZE, TIOCSSIZE not defined yet.  Only needed for SunOS source

diff --git a/arch/mips/include/uapi/asm/unistd.h b/arch/mips/include/uapi/asm/unistd.h
index 0eebf3c3e03c26f2a2f310e36f1831bcdad9aec6..16338b84fa79d337c9d0f32c64f37de9a23a43e3 100644 (file)
--- a/arch/mips/include/uapi/asm/unistd.h
+++ b/arch/mips/include/uapi/asm/unistd.h
@@ -20,16 +20,16 @@
  * Linux o32 style syscalls are in the range from 4000 to 4999.
  */
 #define __NR_Linux                     4000
  * Linux o32 style syscalls are in the range from 4000 to 4999.
  */
 #define __NR_Linux                     4000

-#define __NR_syscall                   (__NR_Linux +   0)
-#define __NR_exit                      (__NR_Linux +   1)
-#define __NR_fork                      (__NR_Linux +   2)
-#define __NR_read                      (__NR_Linux +   3)
-#define __NR_write                     (__NR_Linux +   4)
-#define __NR_open                      (__NR_Linux +   5)
-#define __NR_close                     (__NR_Linux +   6)
-#define __NR_waitpid                   (__NR_Linux +   7)
-#define __NR_creat                     (__NR_Linux +   8)
-#define __NR_link                      (__NR_Linux +   9)
+#define __NR_syscall                   (__NR_Linux +   0)
+#define __NR_exit                      (__NR_Linux +   1)
+#define __NR_fork                      (__NR_Linux +   2)
+#define __NR_read                      (__NR_Linux +   3)
+#define __NR_write                     (__NR_Linux +   4)
+#define __NR_open                      (__NR_Linux +   5)
+#define __NR_close                     (__NR_Linux +   6)
+#define __NR_waitpid                   (__NR_Linux +   7)
+#define __NR_creat                     (__NR_Linux +   8)
+#define __NR_link                      (__NR_Linux +   9)

 #define __NR_unlink                    (__NR_Linux +  10)
 #define __NR_execve                    (__NR_Linux +  11)
 #define __NR_chdir                     (__NR_Linux +  12)
 #define __NR_unlink                    (__NR_Linux +  10)
 #define __NR_execve                    (__NR_Linux +  11)
 #define __NR_chdir                     (__NR_Linux +  12)


@@ -386,16 +386,16 @@
  * Linux 64-bit syscalls are in the range from 5000 to 5999.
  */
 #define __NR_Linux                     5000
  * Linux 64-bit syscalls are in the range from 5000 to 5999.
  */
 #define __NR_Linux                     5000

-#define __NR_read                      (__NR_Linux +   0)
-#define __NR_write                     (__NR_Linux +   1)
-#define __NR_open                      (__NR_Linux +   2)
-#define __NR_close                     (__NR_Linux +   3)
-#define __NR_stat                      (__NR_Linux +   4)
-#define __NR_fstat                     (__NR_Linux +   5)
-#define __NR_lstat                     (__NR_Linux +   6)
-#define __NR_poll                      (__NR_Linux +   7)
-#define __NR_lseek                     (__NR_Linux +   8)
-#define __NR_mmap                      (__NR_Linux +   9)
+#define __NR_read                      (__NR_Linux +   0)
+#define __NR_write                     (__NR_Linux +   1)
+#define __NR_open                      (__NR_Linux +   2)
+#define __NR_close                     (__NR_Linux +   3)
+#define __NR_stat                      (__NR_Linux +   4)
+#define __NR_fstat                     (__NR_Linux +   5)
+#define __NR_lstat                     (__NR_Linux +   6)
+#define __NR_poll                      (__NR_Linux +   7)
+#define __NR_lseek                     (__NR_Linux +   8)
+#define __NR_mmap                      (__NR_Linux +   9)

 #define __NR_mprotect                  (__NR_Linux +  10)
 #define __NR_munmap                    (__NR_Linux +  11)
 #define __NR_brk                       (__NR_Linux +  12)
 #define __NR_mprotect                  (__NR_Linux +  10)
 #define __NR_munmap                    (__NR_Linux +  11)
 #define __NR_brk                       (__NR_Linux +  12)


@@ -711,16 +711,16 @@
  * Linux N32 syscalls are in the range from 6000 to 6999.
  */
 #define __NR_Linux                     6000
  * Linux N32 syscalls are in the range from 6000 to 6999.
  */
 #define __NR_Linux                     6000

-#define __NR_read                      (__NR_Linux +   0)
-#define __NR_write                     (__NR_Linux +   1)
-#define __NR_open                      (__NR_Linux +   2)
-#define __NR_close                     (__NR_Linux +   3)
-#define __NR_stat                      (__NR_Linux +   4)
-#define __NR_fstat                     (__NR_Linux +   5)
-#define __NR_lstat                     (__NR_Linux +   6)
-#define __NR_poll                      (__NR_Linux +   7)
-#define __NR_lseek                     (__NR_Linux +   8)
-#define __NR_mmap                      (__NR_Linux +   9)
+#define __NR_read                      (__NR_Linux +   0)
+#define __NR_write                     (__NR_Linux +   1)
+#define __NR_open                      (__NR_Linux +   2)
+#define __NR_close                     (__NR_Linux +   3)
+#define __NR_stat                      (__NR_Linux +   4)
+#define __NR_fstat                     (__NR_Linux +   5)
+#define __NR_lstat                     (__NR_Linux +   6)
+#define __NR_poll                      (__NR_Linux +   7)
+#define __NR_lseek                     (__NR_Linux +   8)
+#define __NR_mmap                      (__NR_Linux +   9)

 #define __NR_mprotect                  (__NR_Linux +  10)
 #define __NR_munmap                    (__NR_Linux +  11)
 #define __NR_brk                       (__NR_Linux +  12)
 #define __NR_mprotect                  (__NR_Linux +  10)
 #define __NR_munmap                    (__NR_Linux +  11)
 #define __NR_brk                       (__NR_Linux +  12)

diff --git a/arch/mips/jazz/Makefile b/arch/mips/jazz/Makefile
index dd9d99bfcf7a2d5cf6535740f2a7cb1594aa2e58..624b0ee3e5d435860569c2acdeb3bd0d1aedb47c 100644 (file)
--- a/arch/mips/jazz/Makefile
+++ b/arch/mips/jazz/Makefile
@@ -2,4 +2,4 @@
 # Makefile for the Jazz family specific parts of the kernel
 #
 
 # Makefile for the Jazz family specific parts of the kernel
 #
 

-obj-y          := irq.o jazzdma.o reset.o setup.o
+obj-y          := irq.o jazzdma.o reset.o setup.o

diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index f21868b28b24e19575d49210bb709333d3653309..e1ea4f625f7a455795c07cc7d5e155edfbb2bd95 100644 (file)
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -111,7 +111,7 @@ asmlinkage void plat_irq_dispatch(void)
 }
 
 static void r4030_set_mode(enum clock_event_mode mode,
 }
 
 static void r4030_set_mode(enum clock_event_mode mode,

-                           struct clock_event_device *evt)
+                          struct clock_event_device *evt)

 {
        /* Nothing to do ...  */
 }
 {
        /* Nothing to do ...  */
 }


@@ -146,7 +146,7 @@ void __init plat_time_init(void)
 
        BUG_ON(HZ != 100);
 
 
        BUG_ON(HZ != 100);
 

-       cd->cpumask             = cpumask_of(cpu);
+       cd->cpumask             = cpumask_of(cpu);

        clockevents_register_device(cd);
        action->dev_id = cd;
        setup_irq(JAZZ_TIMER_IRQ, action);
        clockevents_register_device(cd);
        action->dev_id = cd;
        setup_irq(JAZZ_TIMER_IRQ, action);

diff --git a/arch/mips/jazz/jazzdma.c b/arch/mips/jazz/jazzdma.c
index 2d8e447cb8281577ea2d7b01064c62f649f1d58c..db6f5afff4ff1a785a0b0ae8913ebe06b3061260 100644 (file)
--- a/arch/mips/jazz/jazzdma.c
+++ b/arch/mips/jazz/jazzdma.c
@@ -63,7 +63,7 @@ static inline void vdma_pgtbl_init(void)
 static int __init vdma_init(void)
 {
        /*
 static int __init vdma_init(void)
 {
        /*

-        * Allocate 32k of memory for DMA page tables.  This needs to be page
+        * Allocate 32k of memory for DMA page tables.  This needs to be page

         * aligned and should be uncached to avoid cache flushing after every
         * update.
         */
         * aligned and should be uncached to avoid cache flushing after every
         * update.
         */


@@ -218,14 +218,14 @@ int vdma_remap(unsigned long laddr, unsigned long paddr, unsigned long size)
                        printk
                            ("vdma_map: Invalid logical address: %08lx\n",
                             laddr);
                        printk
                            ("vdma_map: Invalid logical address: %08lx\n",
                             laddr);

-               return -EINVAL; /* invalid logical address */
+               return -EINVAL; /* invalid logical address */

        }
        if (paddr > 0x1fffffff) {
                if (vdma_debug)
                        printk
                            ("vdma_map: Invalid physical address: %08lx\n",
                             paddr);
        }
        if (paddr > 0x1fffffff) {
                if (vdma_debug)
                        printk
                            ("vdma_map: Invalid physical address: %08lx\n",
                             paddr);

-               return -EINVAL; /* invalid physical address */
+               return -EINVAL; /* invalid physical address */

        }
 
        pages = (((paddr & (VDMA_PAGESIZE - 1)) + size) >> 12) + 1;
        }
 
        pages = (((paddr & (VDMA_PAGESIZE - 1)) + size) >> 12) + 1;

diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c
index 820e926dacbc5856167fdd34893d4b1c59ead161..e4374a5651ce3f426d30b51377ced01bf7b298c1 100644 (file)
--- a/arch/mips/jazz/setup.c
+++ b/arch/mips/jazz/setup.c
@@ -137,9 +137,9 @@ static struct resource jazz_esp_rsrc[] = {
 };
 
 static struct platform_device jazz_esp_pdev = {
 };
 
 static struct platform_device jazz_esp_pdev = {

-       .name           = "jazz_esp",
-       .num_resources  = ARRAY_SIZE(jazz_esp_rsrc),
-       .resource       = jazz_esp_rsrc
+       .name           = "jazz_esp",
+       .num_resources  = ARRAY_SIZE(jazz_esp_rsrc),
+       .resource       = jazz_esp_rsrc

 };
 
 static struct resource jazz_sonic_rsrc[] = {
 };
 
 static struct resource jazz_sonic_rsrc[] = {


@@ -156,9 +156,9 @@ static struct resource jazz_sonic_rsrc[] = {
 };
 
 static struct platform_device jazz_sonic_pdev = {
 };
 
 static struct platform_device jazz_sonic_pdev = {

-       .name           = "jazzsonic",
-       .num_resources  = ARRAY_SIZE(jazz_sonic_rsrc),
-       .resource       = jazz_sonic_rsrc
+       .name           = "jazzsonic",
+       .num_resources  = ARRAY_SIZE(jazz_sonic_rsrc),
+       .resource       = jazz_sonic_rsrc

 };
 
 static struct resource jazz_cmos_rsrc[] = {
 };
 
 static struct resource jazz_cmos_rsrc[] = {


@@ -175,13 +175,13 @@ static struct resource jazz_cmos_rsrc[] = {
 };
 
 static struct platform_device jazz_cmos_pdev = {
 };
 
 static struct platform_device jazz_cmos_pdev = {

-       .name           = "rtc_cmos",
-       .num_resources  = ARRAY_SIZE(jazz_cmos_rsrc),
-       .resource       = jazz_cmos_rsrc
+       .name           = "rtc_cmos",
+       .num_resources  = ARRAY_SIZE(jazz_cmos_rsrc),
+       .resource       = jazz_cmos_rsrc

 };
 
 static struct platform_device pcspeaker_pdev = {
 };
 
 static struct platform_device pcspeaker_pdev = {

-       .name           = "pcspkr",
+       .name           = "pcspkr",

        .id             = -1,
 };
 
        .id             = -1,
 };
 

diff --git a/arch/mips/jz4740/board-qi_lb60.c b/arch/mips/jz4740/board-qi_lb60.c
index 43d964d3628803102f4384bf734de428cb3049a4..be2b3deeef1da7acf3fd3f62a665874e3e689a9e 100644 (file)
--- a/arch/mips/jz4740/board-qi_lb60.c
+++ b/arch/mips/jz4740/board-qi_lb60.c
@@ -52,7 +52,7 @@ static bool is_avt2;
 static struct nand_ecclayout qi_lb60_ecclayout_1gb = {
        .eccbytes = 36,
        .eccpos = {
 static struct nand_ecclayout qi_lb60_ecclayout_1gb = {
        .eccbytes = 36,
        .eccpos = {

-               6,  7,  8,  9,  10, 11, 12, 13,
+               6,  7,  8,  9,  10, 11, 12, 13,

                14, 15, 16, 17, 18, 19, 20, 21,
                22, 23, 24, 25, 26, 27, 28, 29,
                30, 31, 32, 33, 34, 35, 36, 37,
                14, 15, 16, 17, 18, 19, 20, 21,
                22, 23, 24, 25, 26, 27, 28, 29,
                30, 31, 32, 33, 34, 35, 36, 37,


@@ -210,7 +210,7 @@ static const uint32_t qi_lb60_keymap[] = {
        KEY(6, 7, KEY_RIGHT),   /* S57 */
 
        KEY(7, 0, KEY_LEFTSHIFT),       /* S58 */
        KEY(6, 7, KEY_RIGHT),   /* S57 */
 
        KEY(7, 0, KEY_LEFTSHIFT),       /* S58 */

-       KEY(7, 1, KEY_LEFTALT), /* S59 */
+       KEY(7, 1, KEY_LEFTALT), /* S59 */

        KEY(7, 2, KEY_QI_FN),   /* S60 */
 };
 
        KEY(7, 2, KEY_QI_FN),   /* S60 */
 };
 


@@ -317,7 +317,7 @@ static struct spi_board_info qi_lb60_spi_board_info[] = {
 
 /* Battery */
 static struct jz_battery_platform_data qi_lb60_battery_pdata = {
 
 /* Battery */
 static struct jz_battery_platform_data qi_lb60_battery_pdata = {

-       .gpio_charge =  JZ_GPIO_PORTC(27),
+       .gpio_charge =  JZ_GPIO_PORTC(27),

        .gpio_charge_active_low = 1,
        .info = {
                .name = "battery",
        .gpio_charge_active_low = 1,
        .info = {
                .name = "battery",


@@ -344,7 +344,7 @@ static struct gpio_keys_platform_data qi_lb60_gpio_keys_data = {
 };
 
 static struct platform_device qi_lb60_gpio_keys = {
 };
 
 static struct platform_device qi_lb60_gpio_keys = {

-       .name = "gpio-keys",
+       .name = "gpio-keys",

        .id =   -1,
        .dev = {
                .platform_data = &qi_lb60_gpio_keys_data,
        .id =   -1,
        .dev = {
                .platform_data = &qi_lb60_gpio_keys_data,

diff --git a/arch/mips/jz4740/clock-debugfs.c b/arch/mips/jz4740/clock-debugfs.c
index 330a0f2bf17bb5a062ebd1e32a573cbbb15c25f5..a8acdeff267ea87dd48c4097948c570823683d38 100644 (file)
--- a/arch/mips/jz4740/clock-debugfs.c
+++ b/arch/mips/jz4740/clock-debugfs.c
@@ -3,7 +3,7 @@
  *  JZ4740 SoC clock support debugfs entries
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  JZ4740 SoC clock support debugfs entries
  *
  *  This program is free software; you can redistribute it and/or modify it

- *  under  the terms of the GNU General  Public License as published by the
+ *  under  the terms of the GNU General         Public License as published by the

  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *
  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *

diff --git a/arch/mips/jz4740/clock.c b/arch/mips/jz4740/clock.c
index 118a8a5562ddce782a3ac35e44740a63862f6e0a..484d38a0864fe875f5d93469bb51323fe8ec3b2f 100644 (file)
--- a/arch/mips/jz4740/clock.c
+++ b/arch/mips/jz4740/clock.c
@@ -3,7 +3,7 @@
  *  JZ4740 SoC clock support
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  JZ4740 SoC clock support
  *
  *  This program is free software; you can redistribute it and/or modify it

- *  under  the terms of the GNU General  Public License as published by the
+ *  under  the terms of the GNU General         Public License as published by the

  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *
  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *


@@ -31,7 +31,7 @@
 #define JZ_REG_CLOCK_LOW_POWER 0x04
 #define JZ_REG_CLOCK_PLL       0x10
 #define JZ_REG_CLOCK_GATE      0x20
 #define JZ_REG_CLOCK_LOW_POWER 0x04
 #define JZ_REG_CLOCK_PLL       0x10
 #define JZ_REG_CLOCK_GATE      0x20

-#define JZ_REG_CLOCK_SLEEP_CTRL        0x24
+#define JZ_REG_CLOCK_SLEEP_CTRL 0x24

 #define JZ_REG_CLOCK_I2S       0x60
 #define JZ_REG_CLOCK_LCD       0x64
 #define JZ_REG_CLOCK_MMC       0x68
 #define JZ_REG_CLOCK_I2S       0x60
 #define JZ_REG_CLOCK_LCD       0x64
 #define JZ_REG_CLOCK_MMC       0x68

diff --git a/arch/mips/jz4740/dma.c b/arch/mips/jz4740/dma.c
index d7feb898692c5cf6c1997bcaab742d29e9a91bb2..317ec6fffb12723e9ed3fe13b1902ddeeec166da 100644 (file)
--- a/arch/mips/jz4740/dma.c
+++ b/arch/mips/jz4740/dma.c
@@ -3,7 +3,7 @@
  *  JZ4740 SoC DMA support
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  JZ4740 SoC DMA support
  *
  *  This program is free software; you can redistribute it and/or modify it

- *  under  the terms of the GNU General  Public License as published by the
+ *  under  the terms of the GNU General         Public License as published by the

  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *
  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *

diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c
index e1ddb95c05e3459569105a34933a50906be65097..00b798d2fb7cfadaa39cf0f825ac26b97dad0f84 100644 (file)
--- a/arch/mips/jz4740/gpio.c
+++ b/arch/mips/jz4740/gpio.c
@@ -3,7 +3,7 @@
  *  JZ4740 platform GPIO support
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  JZ4740 platform GPIO support
  *
  *  This program is free software; you can redistribute it and/or modify it

- *  under  the terms of the GNU General  Public License as published by the
+ *  under  the terms of the GNU General         Public License as published by the

  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *
  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *

diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c
index fc57ded326d869d591f202cd90df59d8ef903869..2531da1d3add4d0af7dcc3a3d1cfb82ae4c61216 100644 (file)
--- a/arch/mips/jz4740/irq.c
+++ b/arch/mips/jz4740/irq.c
@@ -3,7 +3,7 @@
  *  JZ4740 platform IRQ support
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  JZ4740 platform IRQ support
  *
  *  This program is free software; you can redistribute it and/or modify it

- *  under  the terms of the GNU General  Public License as published by the
+ *  under  the terms of the GNU General         Public License as published by the

  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *
  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *

diff --git a/arch/mips/jz4740/irq.h b/arch/mips/jz4740/irq.h
index f75e39d62885858d187da42e72e283e5700c6a55..0f48720b5b63aec2c7bc758848234ae55286c157 100644 (file)
--- a/arch/mips/jz4740/irq.h
+++ b/arch/mips/jz4740/irq.h
@@ -2,7 +2,7 @@
  *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
  *
  *  This program is free software; you can redistribute it and/or modify it

- *  under  the terms of the GNU General  Public License as published by the
+ *  under  the terms of the GNU General         Public License as published by the

  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *
  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *

diff --git a/arch/mips/jz4740/platform.c b/arch/mips/jz4740/platform.c
index 6d14dcdbd9083639ebb7a73f3ab0edc00aada7c8..e9348fd26a35fb9c4825f06585bb3161cb166488 100644 (file)
--- a/arch/mips/jz4740/platform.c
+++ b/arch/mips/jz4740/platform.c
@@ -3,7 +3,7 @@
  *  JZ4740 platform devices
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  JZ4740 platform devices
  *
  *  This program is free software; you can redistribute it and/or modify it

- *  under  the terms of the GNU General  Public License as published by the
+ *  under  the terms of the GNU General         Public License as published by the

  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *
  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *


@@ -102,7 +102,7 @@ struct platform_device jz4740_mmc_device = {
                .dma_mask = &jz4740_mmc_device.dev.coherent_dma_mask,
                .coherent_dma_mask = DMA_BIT_MASK(32),
        },
                .dma_mask = &jz4740_mmc_device.dev.coherent_dma_mask,
                .coherent_dma_mask = DMA_BIT_MASK(32),
        },

-       .num_resources  = ARRAY_SIZE(jz4740_mmc_resources),
+       .num_resources  = ARRAY_SIZE(jz4740_mmc_resources),

        .resource       = jz4740_mmc_resources,
 };
 
        .resource       = jz4740_mmc_resources,
 };
 


@@ -114,7 +114,7 @@ static struct resource jz4740_rtc_resources[] = {
                .flags  = IORESOURCE_MEM,
        },
        {
                .flags  = IORESOURCE_MEM,
        },
        {

-               .start  = JZ4740_IRQ_RTC,
+               .start  = JZ4740_IRQ_RTC,

                .end    = JZ4740_IRQ_RTC,
                .flags  = IORESOURCE_IRQ,
        },
                .end    = JZ4740_IRQ_RTC,
                .flags  = IORESOURCE_IRQ,
        },


@@ -144,7 +144,7 @@ static struct resource jz4740_i2c_resources[] = {
 struct platform_device jz4740_i2c_device = {
        .name           = "jz4740-i2c",
        .id             = 0,
 struct platform_device jz4740_i2c_device = {
        .name           = "jz4740-i2c",
        .id             = 0,

-       .num_resources  = ARRAY_SIZE(jz4740_i2c_resources),
+       .num_resources  = ARRAY_SIZE(jz4740_i2c_resources),

        .resource       = jz4740_i2c_resources,
 };
 
        .resource       = jz4740_i2c_resources,
 };
 


@@ -318,8 +318,8 @@ static struct resource jz4740_wdt_resources[] = {
 };
 
 struct platform_device jz4740_wdt_device = {
 };
 
 struct platform_device jz4740_wdt_device = {

-       .name          = "jz4740-wdt",
-       .id            = -1,
+       .name          = "jz4740-wdt",
+       .id            = -1,

        .num_resources = ARRAY_SIZE(jz4740_wdt_resources),
        .resource      = jz4740_wdt_resources,
 };
        .num_resources = ARRAY_SIZE(jz4740_wdt_resources),
        .resource      = jz4740_wdt_resources,
 };

diff --git a/arch/mips/jz4740/pm.c b/arch/mips/jz4740/pm.c
index 6744fa723f72d19bf024d1a0da16788192300ccf..d8e213010169b6145e5c46aac8511357325d6636 100644 (file)
--- a/arch/mips/jz4740/pm.c
+++ b/arch/mips/jz4740/pm.c
@@ -3,7 +3,7 @@
  *     JZ4740 SoC power management support
  *
  *  This program is free software; you can redistribute it and/or modify it
  *     JZ4740 SoC power management support
  *
  *  This program is free software; you can redistribute it and/or modify it

- *  under  the terms of the GNU General  Public License as published by the
+ *  under  the terms of the GNU General         Public License as published by the

  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *
  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *

diff --git a/arch/mips/jz4740/prom.c b/arch/mips/jz4740/prom.c
index 4a70407f55bb7df9d68bc46256b8c007c08c6e59..5a93f381590dbb04cb45bb105536d0c072659523 100644 (file)
--- a/arch/mips/jz4740/prom.c
+++ b/arch/mips/jz4740/prom.c
@@ -3,7 +3,7 @@
  *  JZ4740 SoC prom code
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  JZ4740 SoC prom code
  *
  *  This program is free software; you can redistribute it and/or modify it

- *  under  the terms of the GNU General  Public License as published by the
+ *  under  the terms of the GNU General         Public License as published by the

  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *
  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *

diff --git a/arch/mips/jz4740/reset.c b/arch/mips/jz4740/reset.c
index 6c0da5afcf17ef1fdcd97d70f83dff183fcd57f3..b6c6343d2834fab7f77290cc289c161cc12bb89b 100644 (file)
--- a/arch/mips/jz4740/reset.c
+++ b/arch/mips/jz4740/reset.c
@@ -2,7 +2,7 @@
  *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
  *
  *  This program is free software; you can redistribute it and/or modify it

- *  under  the terms of the GNU General  Public License as published by the
+ *  under  the terms of the GNU General         Public License as published by the

  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *
  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *

diff --git a/arch/mips/jz4740/setup.c b/arch/mips/jz4740/setup.c
index d97cfbf882f5fdf16f7cd7ed3bb1f16b0cbe117c..76eafcb79c89e40ec78a41c2188c9fc57f43225b 100644 (file)
--- a/arch/mips/jz4740/setup.c
+++ b/arch/mips/jz4740/setup.c
@@ -4,7 +4,7 @@
  *  JZ4740 setup code
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  JZ4740 setup code
  *
  *  This program is free software; you can redistribute it and/or modify it

- *  under  the terms of the GNU General  Public License as published by the
+ *  under  the terms of the GNU General         Public License as published by the

  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *
  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *

diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c
index 39bb4bbf43e7073e9327a634f221f5c1942b2855..5e430ce9ac7e7d727f1b10237b07599ba8b081db 100644 (file)
--- a/arch/mips/jz4740/time.c
+++ b/arch/mips/jz4740/time.c
@@ -3,7 +3,7 @@
  *  JZ4740 platform time support
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  JZ4740 platform time support
  *
  *  This program is free software; you can redistribute it and/or modify it

- *  under  the terms of the GNU General  Public License as published by the
+ *  under  the terms of the GNU General         Public License as published by the

  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *
  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *

diff --git a/arch/mips/jz4740/timer.c b/arch/mips/jz4740/timer.c
index 22f11d73a17d85833da49c9692efa162a0564c4a..4992461787aa4f9c12486fc61955dcc7facdcb35 100644 (file)
--- a/arch/mips/jz4740/timer.c
+++ b/arch/mips/jz4740/timer.c
@@ -3,7 +3,7 @@
  *  JZ4740 platform timer support
  *
  *  This program is free software; you can redistribute it and/or modify it
  *  JZ4740 platform timer support
  *
  *  This program is free software; you can redistribute it and/or modify it

- *  under  the terms of the GNU General  Public License as published by the
+ *  under  the terms of the GNU General         Public License as published by the

  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *
  *  Free Software Foundation;  either version 2 of the License, or (at your
  *  option) any later version.
  *

diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 007c33d737154a20c04a8cc2fa109504d77dc151..c48ed923fd553d93fded8ee624dc8541b766a0b6 100644 (file)
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -39,7 +39,7 @@ obj-$(CONFIG_CPU_R4K_FPU)     += r4k_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_R3000)                += r2300_fpu.o r2300_switch.o
 obj-$(CONFIG_CPU_R6000)                += r6000_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_TX39XX)       += r2300_fpu.o r2300_switch.o
 obj-$(CONFIG_CPU_R3000)                += r2300_fpu.o r2300_switch.o
 obj-$(CONFIG_CPU_R6000)                += r6000_fpu.o r4k_switch.o
 obj-$(CONFIG_CPU_TX39XX)       += r2300_fpu.o r2300_switch.o

-obj-$(CONFIG_CPU_CAVIUM_OCTEON)        += octeon_switch.o
+obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o

 
 obj-$(CONFIG_SMP)              += smp.o
 obj-$(CONFIG_SMP_UP)           += smp-up.o
 
 obj-$(CONFIG_SMP)              += smp.o
 obj-$(CONFIG_SMP_UP)           += smp-up.o


@@ -53,7 +53,7 @@ obj-$(CONFIG_MIPS_CMP)                += smp-cmp.o
 obj-$(CONFIG_CPU_MIPSR2)       += spram.o
 
 obj-$(CONFIG_MIPS_VPE_LOADER)  += vpe.o
 obj-$(CONFIG_CPU_MIPSR2)       += spram.o
 
 obj-$(CONFIG_MIPS_VPE_LOADER)  += vpe.o

-obj-$(CONFIG_MIPS_VPE_APSP_API)        += rtlx.o
+obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o

 
 obj-$(CONFIG_I8259)            += i8259.o
 obj-$(CONFIG_IRQ_CPU)          += irq_cpu.o
 
 obj-$(CONFIG_I8259)            += i8259.o
 obj-$(CONFIG_IRQ_CPU)          += irq_cpu.o

diff --git a/arch/mips/kernel/binfmt_elfn32.c b/arch/mips/kernel/binfmt_elfn32.c
index 9fdd8bcdd21ef1785c90cc40b0579b6acb4dc1a0..e06f777e9c493167d81b9b31acb8bb6a38803a48 100644 (file)
--- a/arch/mips/kernel/binfmt_elfn32.c
+++ b/arch/mips/kernel/binfmt_elfn32.c
@@ -6,7 +6,7 @@
  *
  * Heavily inspired by the 32-bit Sparc compat code which is
  * Copyright (C) 1995, 1996, 1997, 1998 David S. Miller (davem@redhat.com)
  *
  * Heavily inspired by the 32-bit Sparc compat code which is
  * Copyright (C) 1995, 1996, 1997, 1998 David S. Miller (davem@redhat.com)

- * Copyright (C) 1995, 1996, 1997, 1998 Jakub Jelinek   (jj@ultra.linux.cz)
+ * Copyright (C) 1995, 1996, 1997, 1998 Jakub Jelinek  (jj@ultra.linux.cz)

  */
 
 #define ELF_ARCH               EM_MIPS
  */
 
 #define ELF_ARCH               EM_MIPS


@@ -48,7 +48,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 
 #define TASK32_SIZE            0x7fff8000UL
 #undef ELF_ET_DYN_BASE
 
 #define TASK32_SIZE            0x7fff8000UL
 #undef ELF_ET_DYN_BASE

-#define ELF_ET_DYN_BASE         (TASK32_SIZE / 3 * 2)
+#define ELF_ET_DYN_BASE                (TASK32_SIZE / 3 * 2)

 
 #include <asm/processor.h>
 #include <linux/module.h>
 
 #include <asm/processor.h>
 #include <linux/module.h>


@@ -67,8 +67,8 @@ struct elf_prstatus32
        pid_t   pr_ppid;
        pid_t   pr_pgrp;
        pid_t   pr_sid;
        pid_t   pr_ppid;
        pid_t   pr_pgrp;
        pid_t   pr_sid;

-       struct compat_timeval pr_utime; /* User time */
-       struct compat_timeval pr_stime; /* System time */
+       struct compat_timeval pr_utime; /* User time */
+       struct compat_timeval pr_stime; /* System time */

        struct compat_timeval pr_cutime;/* Cumulative user time */
        struct compat_timeval pr_cstime;/* Cumulative system time */
        elf_gregset_t pr_reg;   /* GP registers */
        struct compat_timeval pr_cutime;/* Cumulative user time */
        struct compat_timeval pr_cstime;/* Cumulative system time */
        elf_gregset_t pr_reg;   /* GP registers */


@@ -88,7 +88,7 @@ struct elf_prpsinfo32
        pid_t   pr_pid, pr_ppid, pr_pgrp, pr_sid;
        /* Lots missing */
        char    pr_fname[16];   /* filename of executable */
        pid_t   pr_pid, pr_ppid, pr_pgrp, pr_sid;
        /* Lots missing */
        char    pr_fname[16];   /* filename of executable */

-       char    pr_psargs[ELF_PRARGSZ]; /* initial part of arg list */
+       char    pr_psargs[ELF_PRARGSZ]; /* initial part of arg list */

 };
 
 #define elf_caddr_t    u32
 };
 
 #define elf_caddr_t    u32

diff --git a/arch/mips/kernel/binfmt_elfo32.c b/arch/mips/kernel/binfmt_elfo32.c
index ff448233dab55737ca2ba1aa54edfa252263b924..556a4357d7fc69f79b024fd968ef409bcbe20fb8 100644 (file)
--- a/arch/mips/kernel/binfmt_elfo32.c
+++ b/arch/mips/kernel/binfmt_elfo32.c
@@ -6,7 +6,7 @@
  *
  * Heavily inspired by the 32-bit Sparc compat code which is
  * Copyright (C) 1995, 1996, 1997, 1998 David S. Miller (davem@redhat.com)
  *
  * Heavily inspired by the 32-bit Sparc compat code which is
  * Copyright (C) 1995, 1996, 1997, 1998 David S. Miller (davem@redhat.com)

- * Copyright (C) 1995, 1996, 1997, 1998 Jakub Jelinek   (jj@ultra.linux.cz)
+ * Copyright (C) 1995, 1996, 1997, 1998 Jakub Jelinek  (jj@ultra.linux.cz)

  */
 
 #define ELF_ARCH               EM_MIPS
  */
 
 #define ELF_ARCH               EM_MIPS


@@ -50,7 +50,7 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
 
 #define TASK32_SIZE            0x7fff8000UL
 #undef ELF_ET_DYN_BASE
 
 #define TASK32_SIZE            0x7fff8000UL
 #undef ELF_ET_DYN_BASE

-#define ELF_ET_DYN_BASE         (TASK32_SIZE / 3 * 2)
+#define ELF_ET_DYN_BASE                (TASK32_SIZE / 3 * 2)

 
 #include <asm/processor.h>
 
 
 #include <asm/processor.h>
 


@@ -86,8 +86,8 @@ struct elf_prstatus32
        pid_t   pr_ppid;
        pid_t   pr_pgrp;
        pid_t   pr_sid;
        pid_t   pr_ppid;
        pid_t   pr_pgrp;
        pid_t   pr_sid;

-       struct compat_timeval pr_utime; /* User time */
-       struct compat_timeval pr_stime; /* System time */
+       struct compat_timeval pr_utime; /* User time */
+       struct compat_timeval pr_stime; /* System time */

        struct compat_timeval pr_cutime;/* Cumulative user time */
        struct compat_timeval pr_cstime;/* Cumulative system time */
        elf_gregset_t pr_reg;   /* GP registers */
        struct compat_timeval pr_cutime;/* Cumulative user time */
        struct compat_timeval pr_cstime;/* Cumulative system time */
        elf_gregset_t pr_reg;   /* GP registers */


@@ -107,7 +107,7 @@ struct elf_prpsinfo32
        pid_t   pr_pid, pr_ppid, pr_pgrp, pr_sid;
        /* Lots missing */
        char    pr_fname[16];   /* filename of executable */
        pid_t   pr_pid, pr_ppid, pr_pgrp, pr_sid;
        /* Lots missing */
        char    pr_fname[16];   /* filename of executable */

-       char    pr_psargs[ELF_PRARGSZ]; /* initial part of arg list */
+       char    pr_psargs[ELF_PRARGSZ]; /* initial part of arg list */

 };
 
 #define elf_caddr_t    u32
 };
 
 #define elf_caddr_t    u32

diff --git a/arch/mips/kernel/bmips_vec.S b/arch/mips/kernel/bmips_vec.S
index e908e81330b1bb8378458adcfc625148fe2b3287..64c4fd62cf08b2577ac40186469dd65dc5ccd334 100644 (file)
--- a/arch/mips/kernel/bmips_vec.S
+++ b/arch/mips/kernel/bmips_vec.S
@@ -170,7 +170,7 @@ bmips_smp_entry:
 
        /* switch to permanent stack and continue booting */
 
 
        /* switch to permanent stack and continue booting */
 

-       .global bmips_secondary_reentry
+       .global bmips_secondary_reentry

 bmips_secondary_reentry:
        la      k0, bmips_smp_boot_sp
        lw      sp, 0(k0)
 bmips_secondary_reentry:
        la      k0, bmips_smp_boot_sp
        lw      sp, 0(k0)


@@ -182,7 +182,7 @@ bmips_secondary_reentry:
 #endif /* CONFIG_SMP */
 
        .align  4
 #endif /* CONFIG_SMP */
 
        .align  4

-       .global bmips_reset_nmi_vec_end
+       .global bmips_reset_nmi_vec_end

 bmips_reset_nmi_vec_end:
 
 END(bmips_reset_nmi_vec)
 bmips_reset_nmi_vec_end:
 
 END(bmips_reset_nmi_vec)


@@ -206,7 +206,7 @@ LEAF(bmips_smp_int_vec)
        eret
 
        .align  4
        eret
 
        .align  4

-       .global bmips_smp_int_vec_end
+       .global bmips_smp_int_vec_end

 bmips_smp_int_vec_end:
 
 END(bmips_smp_int_vec)
 bmips_smp_int_vec_end:
 
 END(bmips_smp_int_vec)

diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 4d735d0e58f5c9caea2ae5936054e0ce1a66dd08..83ffe950f710f86c985d56e9febabb0aafe39d75 100644 (file)
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -57,7 +57,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
         */
        case bcond_op:
                switch (insn.i_format.rt) {
         */
        case bcond_op:
                switch (insn.i_format.rt) {

-               case bltz_op:
+               case bltz_op:

                case bltzl_op:
                        if ((long)regs->regs[insn.i_format.rs] < 0) {
                                epc = epc + 4 + (insn.i_format.simmediate << 2);
                case bltzl_op:
                        if ((long)regs->regs[insn.i_format.rs] < 0) {
                                epc = epc + 4 + (insn.i_format.simmediate << 2);


@@ -197,8 +197,8 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
                bit += (bit != 0);
                bit += 23;
                switch (insn.i_format.rt & 3) {
                bit += (bit != 0);
                bit += 23;
                switch (insn.i_format.rt & 3) {

-               case 0: /* bc1f */
-               case 2: /* bc1fl */
+               case 0: /* bc1f */
+               case 2: /* bc1fl */

                        if (~fcr31 & (1 << bit)) {
                                epc = epc + 4 + (insn.i_format.simmediate << 2);
                                if (insn.i_format.rt == 2)
                        if (~fcr31 & (1 << bit)) {
                                epc = epc + 4 + (insn.i_format.simmediate << 2);
                                if (insn.i_format.rt == 2)


@@ -208,8 +208,8 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
                        regs->cp0_epc = epc;
                        break;
 
                        regs->cp0_epc = epc;
                        break;
 

-               case 1: /* bc1t */
-               case 3: /* bc1tl */
+               case 1: /* bc1t */
+               case 3: /* bc1tl */

                        if (fcr31 & (1 << bit)) {
                                epc = epc + 4 + (insn.i_format.simmediate << 2);
                                if (insn.i_format.rt == 3)
                        if (fcr31 & (1 << bit)) {
                                epc = epc + 4 + (insn.i_format.simmediate << 2);
                                if (insn.i_format.rt == 3)

diff --git a/arch/mips/kernel/cevt-bcm1480.c b/arch/mips/kernel/cevt-bcm1480.c
index 69bbfae183bcfafd46f4c4b559e3368233085df2..15f618b40cf6c1dcaf8f8c835f7e2d1f7d89382a 100644 (file)
--- a/arch/mips/kernel/cevt-bcm1480.c
+++ b/arch/mips/kernel/cevt-bcm1480.c
@@ -41,7 +41,7 @@
  * the rest of the system
  */
 static void sibyte_set_mode(enum clock_event_mode mode,
  * the rest of the system
  */
 static void sibyte_set_mode(enum clock_event_mode mode,

-                           struct clock_event_device *evt)
+                          struct clock_event_device *evt)

 {
        unsigned int cpu = smp_processor_id();
        void __iomem *cfg, *init;
 {
        unsigned int cpu = smp_processor_id();
        void __iomem *cfg, *init;


@@ -144,7 +144,7 @@ void __cpuinit sb1480_clockevent_init(void)
 
        bcm1480_unmask_irq(cpu, irq);
 
 
        bcm1480_unmask_irq(cpu, irq);
 

-       action->handler = sibyte_counter_handler;
+       action->handler = sibyte_counter_handler;

        action->flags   = IRQF_PERCPU | IRQF_TIMER;
        action->name    = name;
        action->dev_id  = cd;
        action->flags   = IRQF_PERCPU | IRQF_TIMER;
        action->name    = name;
        action->dev_id  = cd;

diff --git a/arch/mips/kernel/cevt-ds1287.c b/arch/mips/kernel/cevt-ds1287.c
index ed648cb5a69fcc9229fcecbdcb70f30d55c55656..ff1f01b72270fdd4e4051799fc93580b884dcd23 100644 (file)
--- a/arch/mips/kernel/cevt-ds1287.c
+++ b/arch/mips/kernel/cevt-ds1287.c
@@ -1,7 +1,7 @@
 /*
  *  DS1287 clockevent driver
  *
 /*
  *  DS1287 clockevent driver
  *

- *  Copyright (C) 2008  Yoichi Yuasa <yuasa@linux-mips.org>
+ *  Copyright (C) 2008 Yoichi Yuasa <yuasa@linux-mips.org>

  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by


@@ -89,7 +89,7 @@ static void ds1287_event_handler(struct clock_event_device *dev)
 static struct clock_event_device ds1287_clockevent = {
        .name           = "ds1287",
        .features       = CLOCK_EVT_FEAT_PERIODIC,
 static struct clock_event_device ds1287_clockevent = {
        .name           = "ds1287",
        .features       = CLOCK_EVT_FEAT_PERIODIC,

-       .set_next_event = ds1287_set_next_event,
+       .set_next_event = ds1287_set_next_event,

        .set_mode       = ds1287_set_mode,
        .event_handler  = ds1287_event_handler,
 };
        .set_mode       = ds1287_set_mode,
        .event_handler  = ds1287_event_handler,
 };

diff --git a/arch/mips/kernel/cevt-gt641xx.c b/arch/mips/kernel/cevt-gt641xx.c
index 831b47585b7ceac273790c2cfa92ffff4160e0c4..f069460751ab931d10077875556ad0eec90d8bac 100644 (file)
--- a/arch/mips/kernel/cevt-gt641xx.c
+++ b/arch/mips/kernel/cevt-gt641xx.c
@@ -1,7 +1,7 @@
 /*
  *  GT641xx clockevent routines.
  *
 /*
  *  GT641xx clockevent routines.
  *

- *  Copyright (C) 2007  Yoichi Yuasa <yuasa@linux-mips.org>
+ *  Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>

  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by


@@ -98,7 +98,7 @@ static struct clock_event_device gt641xx_timer0_clockevent = {
        .name           = "gt641xx-timer0",
        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
        .irq            = GT641XX_TIMER0_IRQ,
        .name           = "gt641xx-timer0",
        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
        .irq            = GT641XX_TIMER0_IRQ,

-       .set_next_event = gt641xx_timer0_set_next_event,
+       .set_next_event = gt641xx_timer0_set_next_event,

        .set_mode       = gt641xx_timer0_set_mode,
        .event_handler  = gt641xx_timer0_event_handler,
 };
        .set_mode       = gt641xx_timer0_set_mode,
        .event_handler  = gt641xx_timer0_event_handler,
 };

diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 75323925e5377b644a49851add5846841ec9f0f1..07b847d77f5da029dca6a6cbb53198807ff781a8 100644 (file)
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -25,7 +25,7 @@
 #ifndef CONFIG_MIPS_MT_SMTC
 
 static int mips_next_event(unsigned long delta,
 #ifndef CONFIG_MIPS_MT_SMTC
 
 static int mips_next_event(unsigned long delta,

-                           struct clock_event_device *evt)
+                          struct clock_event_device *evt)

 {
        unsigned int cnt;
        int res;
 {
        unsigned int cnt;
        int res;


@@ -66,7 +66,7 @@ irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
                goto out;
 
        /*
                goto out;
 
        /*

-        * The same applies to performance counter interrupts.  But with the
+        * The same applies to performance counter interrupts.  But with the

         * above we now know that the reason we got here must be a timer
         * interrupt.  Being the paranoiacs we are we check anyway.
         */
         * above we now know that the reason we got here must be a timer
         * interrupt.  Being the paranoiacs we are we check anyway.
         */


@@ -119,7 +119,7 @@ int c0_compare_int_usable(void)
        unsigned int cnt;
 
        /*
        unsigned int cnt;
 
        /*

-        * IP7 already pending?  Try to clear it by acking the timer.
+        * IP7 already pending?  Try to clear it by acking the timer.

         */
        if (c0_compare_int_pending()) {
                cnt = read_c0_count();
         */
        if (c0_compare_int_pending()) {
                cnt = read_c0_count();

diff --git a/arch/mips/kernel/cevt-sb1250.c b/arch/mips/kernel/cevt-sb1250.c
index e73439fd685078114996819991dac66a4181fe9e..200f2778bf3660f8acb6cbc4b9eef72f37f0418e 100644 (file)
--- a/arch/mips/kernel/cevt-sb1250.c
+++ b/arch/mips/kernel/cevt-sb1250.c
@@ -39,7 +39,7 @@
  * the rest of the system
  */
 static void sibyte_set_mode(enum clock_event_mode mode,
  * the rest of the system
  */
 static void sibyte_set_mode(enum clock_event_mode mode,

-                           struct clock_event_device *evt)
+                          struct clock_event_device *evt)

 {
        unsigned int cpu = smp_processor_id();
        void __iomem *cfg, *init;
 {
        unsigned int cpu = smp_processor_id();
        void __iomem *cfg, *init;


@@ -143,7 +143,7 @@ void __cpuinit sb1250_clockevent_init(void)
 
        sb1250_unmask_irq(cpu, irq);
 
 
        sb1250_unmask_irq(cpu, irq);
 

-       action->handler = sibyte_counter_handler;
+       action->handler = sibyte_counter_handler;

        action->flags   = IRQF_PERCPU | IRQF_TIMER;
        action->name    = name;
        action->dev_id  = cd;
        action->flags   = IRQF_PERCPU | IRQF_TIMER;
        action->name    = name;
        action->dev_id  = cd;

diff --git a/arch/mips/kernel/cevt-smtc.c b/arch/mips/kernel/cevt-smtc.c
index 2e72d30b2f05a9b2b0d1a40dd90699c658925d5b..9de5ed7ef1a36f79da437e377a2d69d0a4d1bca5 100644 (file)
--- a/arch/mips/kernel/cevt-smtc.c
+++ b/arch/mips/kernel/cevt-smtc.c
@@ -49,7 +49,7 @@ static int smtc_nextinvpe[NR_CPUS];
 
 /*
  * Timestamps stored are absolute values to be programmed
 
 /*
  * Timestamps stored are absolute values to be programmed

- * into Count register.  Valid timestamps will never be zero.
+ * into Count register.         Valid timestamps will never be zero.

  * If a Zero Count value is actually calculated, it is converted
  * to be a 1, which will introduce 1 or two CPU cycles of error
  * roughly once every four billion events, which at 1000 HZ means
  * If a Zero Count value is actually calculated, it is converted
  * to be a 1, which will introduce 1 or two CPU cycles of error
  * roughly once every four billion events, which at 1000 HZ means

diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c
index e5c30b1d0860f5e1e669070619833f4605cfef1c..2ae08462e46e935acce52941965dae24094907ac 100644 (file)
--- a/arch/mips/kernel/cevt-txx9.c
+++ b/arch/mips/kernel/cevt-txx9.c
@@ -4,7 +4,7 @@
  * for more details.
  *
  * Based on linux/arch/mips/kernel/cevt-r4k.c,
  * for more details.
  *
  * Based on linux/arch/mips/kernel/cevt-r4k.c,

- *          linux/arch/mips/jmr3927/rbhma3100/setup.c
+ *         linux/arch/mips/jmr3927/rbhma3100/setup.c

  *
  * Copyright 2001 MontaVista Software Inc.
  * Copyright (C) 2000-2001 Toshiba Corporation
  *
  * Copyright 2001 MontaVista Software Inc.
  * Copyright (C) 2000-2001 Toshiba Corporation


@@ -129,7 +129,7 @@ static struct txx9_clock_event_device txx9_clock_event_device = {
                                  CLOCK_EVT_FEAT_ONESHOT,
                .rating         = 200,
                .set_mode       = txx9tmr_set_mode,
                                  CLOCK_EVT_FEAT_ONESHOT,
                .rating         = 200,
                .set_mode       = txx9tmr_set_mode,

-               .set_next_event = txx9tmr_set_next_event,
+               .set_next_event = txx9tmr_set_next_event,

        },
 };
 
        },
 };
 


@@ -139,7 +139,7 @@ static irqreturn_t txx9tmr_interrupt(int irq, void *dev_id)
        struct clock_event_device *cd = &txx9_cd->cd;
        struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
 
        struct clock_event_device *cd = &txx9_cd->cd;
        struct txx9_tmr_reg __iomem *tmrptr = txx9_cd->tmrptr;
 

-       __raw_writel(0, &tmrptr->tisr); /* ack interrupt */
+       __raw_writel(0, &tmrptr->tisr); /* ack interrupt */

        cd->event_handler(cd);
        return IRQ_HANDLED;
 }
        cd->event_handler(cd);
        return IRQ_HANDLED;
 }

diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c
index d6a18644365ac07df1a7fe5ddb1d3a1629539560..de3c25ffd9f91e38487303696402b8c97f46bf45 100644 (file)
--- a/arch/mips/kernel/cpu-bugs64.c
+++ b/arch/mips/kernel/cpu-bugs64.c
@@ -84,9 +84,9 @@ static inline void mult_sh_align_mod(long *v1, long *v2, long *w,
                ".set   noreorder\n\t"
                ".set   nomacro\n\t"
                "mult   %2, %3\n\t"
                ".set   noreorder\n\t"
                ".set   nomacro\n\t"
                "mult   %2, %3\n\t"

-               "dsll32 %0, %4, %5\n\t"
+               "dsll32 %0, %4, %5\n\t"

                "mflo   $0\n\t"
                "mflo   $0\n\t"

-               "dsll32 %1, %4, %5\n\t"
+               "dsll32 %1, %4, %5\n\t"

                "nop\n\t"
                ".set   pop"
                : "=&r" (lv1), "=r" (lw)
                "nop\n\t"
                ".set   pop"
                : "=&r" (lv1), "=r" (lw)


@@ -239,7 +239,7 @@ static inline void check_daddi(void)
        panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
 }
 
        panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
 }
 

-int daddiu_bug  = -1;
+int daddiu_bug = -1;

 
 static inline void check_daddiu(void)
 {
 
 static inline void check_daddiu(void)
 {


@@ -273,7 +273,7 @@ static inline void check_daddiu(void)
 #ifdef HAVE_AS_SET_DADDI
                ".set   daddi\n\t"
 #endif
 #ifdef HAVE_AS_SET_DADDI
                ".set   daddi\n\t"
 #endif

-               "daddiu %0, %2, %4\n\t"
+               "daddiu %0, %2, %4\n\t"

                "addiu  %1, $0, %4\n\t"
                "daddu  %1, %2\n\t"
                ".set   pop"
                "addiu  %1, $0, %4\n\t"
                "daddu  %1, %2\n\t"
                ".set   pop"


@@ -292,7 +292,7 @@ static inline void check_daddiu(void)
        asm volatile(
                "addiu  %2, $0, %3\n\t"
                "dsrl   %2, %2, 1\n\t"
        asm volatile(
                "addiu  %2, $0, %3\n\t"
                "dsrl   %2, %2, 1\n\t"

-               "daddiu %0, %2, %4\n\t"
+               "daddiu %0, %2, %4\n\t"

                "addiu  %1, $0, %4\n\t"
                "daddu  %1, %2"
                : "=&r" (v), "=&r" (w), "=&r" (tmp)
                "addiu  %1, $0, %4\n\t"
                "daddu  %1, %2"
                : "=&r" (v), "=&r" (w), "=&r" (tmp)

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index cce3782c96c9b792e412abc32fed55547dcde7c9..760139ee7a990b80cf784cee57e9cfcfee1c9569 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -4,7 +4,7 @@
  * Copyright (C) xxxx  the Anonymous
  * Copyright (C) 1994 - 2006 Ralf Baechle
  * Copyright (C) 2003, 2004  Maciej W. Rozycki
  * Copyright (C) xxxx  the Anonymous
  * Copyright (C) 1994 - 2006 Ralf Baechle
  * Copyright (C) 2003, 2004  Maciej W. Rozycki

- * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
+ * Copyright (C) 2001, 2004, 2011, 2012         MIPS Technologies, Inc.

  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License


@@ -69,12 +69,12 @@ void r4k_wait_irqoff(void)
                        "       wait                    \n"
                        "       .set    pop             \n");
        local_irq_enable();
                        "       wait                    \n"
                        "       .set    pop             \n");
        local_irq_enable();

-       __asm__("       .globl __pastwait       \n"
+       __asm__("       .globl __pastwait       \n"

                "__pastwait:                    \n");
 }
 
 /*
                "__pastwait:                    \n");
 }
 
 /*

- * The RM7000 variant has to handle erratum 38.  The workaround is to not
+ * The RM7000 variant has to handle erratum 38.         The workaround is to not

  * have any pending stores when the WAIT instruction is executed.
  */
 static void rm7k_wait_irqoff(void)
  * have any pending stores when the WAIT instruction is executed.
  */
 static void rm7k_wait_irqoff(void)


@@ -469,7 +469,7 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c)
        c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 
        ok = decode_config0(c);                 /* Read Config registers.  */
        c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 
        ok = decode_config0(c);                 /* Read Config registers.  */

-       BUG_ON(!ok);                            /* Arch spec violation!  */
+       BUG_ON(!ok);                            /* Arch spec violation!  */

        if (ok)
                ok = decode_config1(c);
        if (ok)
        if (ok)
                ok = decode_config1(c);
        if (ok)


@@ -710,12 +710,12 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
                             MIPS_CPU_LLSC;
                /*
                c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
                             MIPS_CPU_LLSC;
                /*

-                * Undocumented RM7000:  Bit 29 in the info register of
+                * Undocumented RM7000:  Bit 29 in the info register of

                 * the RM7000 v2.0 indicates if the TLB has 48 or 64
                 * entries.
                 *
                 * the RM7000 v2.0 indicates if the TLB has 48 or 64
                 * entries.
                 *

-                * 29      1 =>    64 entry JTLB
-                *         0 =>    48 entry JTLB
+                * 29      1 =>    64 entry JTLB
+                *         0 =>    48 entry JTLB

                 */
                c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
                break;
                 */
                c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
                break;


@@ -729,8 +729,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                 * Bit 29 in the info register of the RM9000
                 * indicates if the TLB has 48 or 64 entries.
                 *
                 * Bit 29 in the info register of the RM9000
                 * indicates if the TLB has 48 or 64 entries.
                 *

-                * 29      1 =>    64 entry JTLB
-                *         0 =>    48 entry JTLB
+                * 29      1 =>    64 entry JTLB
+                *         0 =>    48 entry JTLB

                 */
                c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
                break;
                 */
                c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
                break;


@@ -1053,12 +1053,12 @@ static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
                return;
        }
 
                return;
        }
 

-       c->options = (MIPS_CPU_TLB       |
-                       MIPS_CPU_4KEX    |
+       c->options = (MIPS_CPU_TLB       |
+                       MIPS_CPU_4KEX    |

                        MIPS_CPU_COUNTER |
                        MIPS_CPU_COUNTER |

-                       MIPS_CPU_DIVEC   |
-                       MIPS_CPU_WATCH   |
-                       MIPS_CPU_EJTAG   |
+                       MIPS_CPU_DIVEC   |
+                       MIPS_CPU_WATCH   |
+                       MIPS_CPU_EJTAG   |

                        MIPS_CPU_LLSC);
 
        switch (c->processor_id & 0xff00) {
                        MIPS_CPU_LLSC);
 
        switch (c->processor_id & 0xff00) {


@@ -1129,7 +1129,7 @@ __cpuinit void cpu_probe(void)
        struct cpuinfo_mips *c = &current_cpu_data;
        unsigned int cpu = smp_processor_id();
 
        struct cpuinfo_mips *c = &current_cpu_data;
        unsigned int cpu = smp_processor_id();
 

-       c->processor_id = PRID_IMP_UNKNOWN;
+       c->processor_id = PRID_IMP_UNKNOWN;

        c->fpu_id       = FPIR_IMP_NONE;
        c->cputype      = CPU_UNKNOWN;
 
        c->fpu_id       = FPIR_IMP_NONE;
        c->cputype      = CPU_UNKNOWN;
 

diff --git a/arch/mips/kernel/cpufreq/loongson2_cpufreq.c b/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
index e7c98e2b78b647bfb312b8977bcc9b140beb1e77..bb51d3193ad4e0ea6803477903327b1bcaf6cd56 100644 (file)
--- a/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
+++ b/arch/mips/kernel/cpufreq/loongson2_cpufreq.c
@@ -195,8 +195,8 @@ static void loongson2_cpu_wait(void)
 
        spin_lock_irqsave(&loongson2_wait_lock, flags);
        cpu_freq = LOONGSON_CHIPCFG0;
 
        spin_lock_irqsave(&loongson2_wait_lock, flags);
        cpu_freq = LOONGSON_CHIPCFG0;

-       LOONGSON_CHIPCFG0 &= ~0x7;      /* Put CPU into wait mode */
-       LOONGSON_CHIPCFG0 = cpu_freq;   /* Restore CPU state */
+       LOONGSON_CHIPCFG0 &= ~0x7;      /* Put CPU into wait mode */
+       LOONGSON_CHIPCFG0 = cpu_freq;   /* Restore CPU state */

        spin_unlock_irqrestore(&loongson2_wait_lock, flags);
 }
 
        spin_unlock_irqrestore(&loongson2_wait_lock, flags);
 }
 

diff --git a/arch/mips/kernel/crash.c b/arch/mips/kernel/crash.c
index 0f53c39324bb69fd6b850f6c2b63ac8e4b2212d0..93aa302948d7236d70dc9f0b5ae9e96b7b123c8b 100644 (file)
--- a/arch/mips/kernel/crash.c
+++ b/arch/mips/kernel/crash.c
@@ -59,7 +59,7 @@ static void crash_kexec_prepare_cpus(void)
 
 #else /* !defined(CONFIG_SMP)  */
 static void crash_kexec_prepare_cpus(void) {}
 
 #else /* !defined(CONFIG_SMP)  */
 static void crash_kexec_prepare_cpus(void) {}

-#endif /* !defined(CONFIG_SMP)  */
+#endif /* !defined(CONFIG_SMP) */

 
 void default_machine_crash_shutdown(struct pt_regs *regs)
 {
 
 void default_machine_crash_shutdown(struct pt_regs *regs)
 {

diff --git a/arch/mips/kernel/csrc-bcm1480.c b/arch/mips/kernel/csrc-bcm1480.c
index f96f99c794a32add278e8b41d4cd4ead3796c336..468f3eba413228c38452f181ccdcbac32f78d6c4 100644 (file)
--- a/arch/mips/kernel/csrc-bcm1480.c
+++ b/arch/mips/kernel/csrc-bcm1480.c
@@ -35,7 +35,7 @@ static cycle_t bcm1480_hpt_read(struct clocksource *cs)
 
 struct clocksource bcm1480_clocksource = {
        .name   = "zbbus-cycles",
 
 struct clocksource bcm1480_clocksource = {
        .name   = "zbbus-cycles",

-       .rating = 200,
+       .rating = 200,

        .read   = bcm1480_hpt_read,
        .mask   = CLOCKSOURCE_MASK(64),
        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
        .read   = bcm1480_hpt_read,
        .mask   = CLOCKSOURCE_MASK(64),
        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,

diff --git a/arch/mips/kernel/csrc-ioasic.c b/arch/mips/kernel/csrc-ioasic.c
index 46bd7fa98d6ca6efba607d3134e80a2d97b61f30..0654bff9b69c5b0ea701e965cf3b7587d9dc4dd1 100644 (file)
--- a/arch/mips/kernel/csrc-ioasic.c
+++ b/arch/mips/kernel/csrc-ioasic.c
@@ -1,7 +1,7 @@
 /*
  *  DEC I/O ASIC's counter clocksource
  *
 /*
  *  DEC I/O ASIC's counter clocksource
  *

- *  Copyright (C) 2008  Yoichi Yuasa <yuasa@linux-mips.org>
+ *  Copyright (C) 2008 Yoichi Yuasa <yuasa@linux-mips.org>

  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by

diff --git a/arch/mips/kernel/csrc-powertv.c b/arch/mips/kernel/csrc-powertv.c
index 2e7c5232da8d72c09c399bacaf3ad45e2eaa726e..abd99ea911ae0c2630de01b6d095a376d9c52cbd 100644 (file)
--- a/arch/mips/kernel/csrc-powertv.c
+++ b/arch/mips/kernel/csrc-powertv.c
@@ -45,7 +45,7 @@ unsigned int __init mips_get_pll_freq(void)
        m = PLL_GET_M(pll_reg);
        n = PLL_GET_N(pll_reg);
        p = PLL_GET_P(pll_reg);
        m = PLL_GET_M(pll_reg);
        n = PLL_GET_N(pll_reg);
        p = PLL_GET_P(pll_reg);

-       pr_info("MIPS PLL Register:0x%x  M=%d  N=%d  P=%d\n", pll_reg, m, n, p);
+       pr_info("MIPS PLL Register:0x%x  M=%d  N=%d  P=%d\n", pll_reg, m, n, p);

 
        /* Calculate clock frequency = (2 * N * 54MHz) / (M * (2**P)) */
        fout = ((2 * n * fin) / (m * (0x01 << p)));
 
        /* Calculate clock frequency = (2 * N * 54MHz) / (M * (2**P)) */
        fout = ((2 * n * fin) / (m * (0x01 << p)));


@@ -83,8 +83,8 @@ static void __init powertv_c0_hpt_clocksource_init(void)
 
 /**
  * struct tim_c - free running counter
 
 /**
  * struct tim_c - free running counter

- * @hi:        High 16 bits of the counter
- * @lo:        Low 32 bits of the counter
+ * @hi: High 16 bits of the counter
+ * @lo: Low 32 bits of the counter

  *
  * Lays out the structure of the free running counter in memory. This counter
  * increments at a rate of 27 MHz/8 on all platforms.
  *
  * Lays out the structure of the free running counter in memory. This counter
  * increments at a rate of 27 MHz/8 on all platforms.

diff --git a/arch/mips/kernel/csrc-sb1250.c b/arch/mips/kernel/csrc-sb1250.c
index e9606d9076858f74f78a0180d8c9edc6a2410249..6ecb77d820631972a8bf3494ffa7b9a56098b610 100644 (file)
--- a/arch/mips/kernel/csrc-sb1250.c
+++ b/arch/mips/kernel/csrc-sb1250.c
@@ -44,7 +44,7 @@ static cycle_t sb1250_hpt_read(struct clocksource *cs)
 
 struct clocksource bcm1250_clocksource = {
        .name   = "bcm1250-counter-3",
 
 struct clocksource bcm1250_clocksource = {
        .name   = "bcm1250-counter-3",

-       .rating = 200,
+       .rating = 200,

        .read   = sb1250_hpt_read,
        .mask   = CLOCKSOURCE_MASK(23),
        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
        .read   = sb1250_hpt_read,
        .mask   = CLOCKSOURCE_MASK(23),
        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,

diff --git a/arch/mips/kernel/ftrace.c b/arch/mips/kernel/ftrace.c
index 83fa1460e294e02cf602cd5d611af6d02abbba39..cf5509f13dd57bc832e1db50d65f88ccda6e81c7 100644 (file)
--- a/arch/mips/kernel/ftrace.c
+++ b/arch/mips/kernel/ftrace.c
@@ -125,21 +125,21 @@ static int ftrace_modify_code_2(unsigned long ip, unsigned int new_code1,
  *
  * 2.1 For KBUILD_MCOUNT_RA_ADDRESS and CONFIG_32BIT
  *
  *
  * 2.1 For KBUILD_MCOUNT_RA_ADDRESS and CONFIG_32BIT
  *

- * lui v1, hi_16bit_of_mcount        --> b 1f (0x10000005)
+ * lui v1, hi_16bit_of_mcount       --> b 1f (0x10000005)

  * addiu v1, v1, low_16bit_of_mcount
  * move at, ra
  * move $12, ra_address
  * jalr v1
  *  sub sp, sp, 8
  * addiu v1, v1, low_16bit_of_mcount
  * move at, ra
  * move $12, ra_address
  * jalr v1
  *  sub sp, sp, 8

- *                                  1: offset = 5 instructions
+ *                                 1: offset = 5 instructions

  * 2.2 For the Other situations
  *
  * 2.2 For the Other situations
  *

- * lui v1, hi_16bit_of_mcount        --> b 1f (0x10000004)
+ * lui v1, hi_16bit_of_mcount       --> b 1f (0x10000004)

  * addiu v1, v1, low_16bit_of_mcount
  * move at, ra
  * jalr v1
  *  nop | move $12, ra_address | sub sp, sp, 8
  * addiu v1, v1, low_16bit_of_mcount
  * move at, ra
  * jalr v1
  *  nop | move $12, ra_address | sub sp, sp, 8

- *                                  1: offset = 4 instructions
+ *                                 1: offset = 4 instructions

  */
 
 #define INSN_B_1F (0x10000000 | MCOUNT_OFFSET_INSNS)
  */
 
 #define INSN_B_1F (0x10000000 | MCOUNT_OFFSET_INSNS)


@@ -228,8 +228,8 @@ int ftrace_disable_ftrace_graph_caller(void)
 
 #ifndef KBUILD_MCOUNT_RA_ADDRESS
 
 
 #ifndef KBUILD_MCOUNT_RA_ADDRESS
 

-#define S_RA_SP        (0xafbf << 16)  /* s{d,w} ra, offset(sp) */
-#define S_R_SP (0xafb0 << 16)  /* s{d,w} R, offset(sp) */
+#define S_RA_SP (0xafbf << 16) /* s{d,w} ra, offset(sp) */
+#define S_R_SP (0xafb0 << 16)  /* s{d,w} R, offset(sp) */

 #define OFFSET_MASK    0xffff  /* stack offset range: 0 ~ PT_SIZE */
 
 unsigned long ftrace_get_parent_ra_addr(unsigned long self_ra, unsigned long
 #define OFFSET_MASK    0xffff  /* stack offset range: 0 ~ PT_SIZE */
 
 unsigned long ftrace_get_parent_ra_addr(unsigned long self_ra, unsigned long

diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index 8a0096d62812c07ea328bf1c78186e36019538f8..ecb347ce1b3d03edc9cb15c3d5dcaf9bb434da84 100644 (file)
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -160,7 +160,7 @@ LEAF(r4k_wait)
        .set pop
        .endm
 
        .set pop
        .endm
 

-       .align  5
+       .align  5

 BUILD_ROLLBACK_PROLOGUE handle_int
 NESTED(handle_int, PT_SIZE, sp)
 #ifdef CONFIG_TRACE_IRQFLAGS
 BUILD_ROLLBACK_PROLOGUE handle_int
 NESTED(handle_int, PT_SIZE, sp)
 #ifdef CONFIG_TRACE_IRQFLAGS


@@ -362,7 +362,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
        .set    push
        .set    noat
        SAVE_ALL
        .set    push
        .set    noat
        SAVE_ALL

-       move    a0, sp
+       move    a0, sp

        jal     nmi_exception_handler
        RESTORE_ALL
        .set    mips3
        jal     nmi_exception_handler
        RESTORE_ALL
        .set    mips3


@@ -409,7 +409,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
           string escapes and emits bogus warnings if it believes to
           recognize an unknown escape code.  So make the arguments
           start with an n and gas will believe \n is ok ...  */
           string escapes and emits bogus warnings if it believes to
           recognize an unknown escape code.  So make the arguments
           start with an n and gas will believe \n is ok ...  */

-       .macro  __BUILD_verbose nexception
+       .macro  __BUILD_verbose nexception

        LONG_L  a1, PT_EPC(sp)
 #ifdef CONFIG_32BIT
        PRINT("Got \nexception at %08lx\012")
        LONG_L  a1, PT_EPC(sp)
 #ifdef CONFIG_32BIT
        PRINT("Got \nexception at %08lx\012")


@@ -442,7 +442,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
        .endm
 
        .macro  BUILD_HANDLER exception handler clear verbose
        .endm
 
        .macro  BUILD_HANDLER exception handler clear verbose

-       __BUILD_HANDLER \exception \handler \clear \verbose _int
+       __BUILD_HANDLER \exception \handler \clear \verbose _int

        .endm
 
        BUILD_HANDLER adel ade ade silent               /* #4  */
        .endm
 
        BUILD_HANDLER adel ade ade silent               /* #4  */


@@ -456,7 +456,7 @@ NESTED(nmi_handler, PT_SIZE, sp)
        BUILD_HANDLER tr tr sti silent                  /* #13 */
        BUILD_HANDLER fpe fpe fpe silent                /* #15 */
        BUILD_HANDLER mdmx mdmx sti silent              /* #22 */
        BUILD_HANDLER tr tr sti silent                  /* #13 */
        BUILD_HANDLER fpe fpe fpe silent                /* #15 */
        BUILD_HANDLER mdmx mdmx sti silent              /* #22 */

-#ifdef         CONFIG_HARDWARE_WATCHPOINTS
+#ifdef CONFIG_HARDWARE_WATCHPOINTS

        /*
         * For watch, interrupts will be enabled after the watch
         * registers are read.
        /*
         * For watch, interrupts will be enabled after the watch
         * registers are read.


@@ -482,8 +482,8 @@ NESTED(nmi_handler, PT_SIZE, sp)
        MFC0    k1, CP0_ENTRYHI
        andi    k1, 0xff        /* ASID_MASK */
        MFC0    k0, CP0_EPC
        MFC0    k1, CP0_ENTRYHI
        andi    k1, 0xff        /* ASID_MASK */
        MFC0    k0, CP0_EPC

-       PTR_SRL k0, _PAGE_SHIFT + 1
-       PTR_SLL k0, _PAGE_SHIFT + 1
+       PTR_SRL k0, _PAGE_SHIFT + 1
+       PTR_SLL k0, _PAGE_SHIFT + 1

        or      k1, k0
        MTC0    k1, CP0_ENTRYHI
        mtc0_tlbw_hazard
        or      k1, k0
        MTC0    k1, CP0_ENTRYHI
        mtc0_tlbw_hazard

diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index fcf97312f32812fe6935d0cff13dd7091af33633..c61cdaed2b1d998f2614be9f9a7451837f59ebaf 100644 (file)
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -133,7 +133,7 @@ EXPORT(_stext)
 #ifdef CONFIG_BOOT_RAW
        /*
         * Give us a fighting chance of running if execution beings at the
 #ifdef CONFIG_BOOT_RAW
        /*
         * Give us a fighting chance of running if execution beings at the

-        * kernel load address.  This is needed because this platform does
+        * kernel load address.  This is needed because this platform does

         * not have a ELF loader yet.
         */
 FEXPORT(__kernel_entry)
         * not have a ELF loader yet.
         */
 FEXPORT(__kernel_entry)


@@ -201,7 +201,7 @@ NESTED(kernel_entry, 16, sp)                        # kernel entry point
 
 #ifdef CONFIG_SMP
 /*
 
 #ifdef CONFIG_SMP
 /*

- * SMP slave cpus entry point.  Board specific code for bootstrap calls this
+ * SMP slave cpus entry point. Board specific code for bootstrap calls this

  * function after setting up the stack and gp registers.
  */
 NESTED(smp_bootstrap, 16, sp)
  * function after setting up the stack and gp registers.
  */
 NESTED(smp_bootstrap, 16, sp)

diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index 32b397b646ee16074c93cf541b72eee85a4aafa4..2b91fe80c43633b6c85d9f21ae2359643c3d745d 100644 (file)
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -178,7 +178,7 @@ handle_real_irq:
        } else {
                inb(PIC_MASTER_IMR);    /* DUMMY - (do we need this?) */
                outb(cached_master_mask, PIC_MASTER_IMR);
        } else {
                inb(PIC_MASTER_IMR);    /* DUMMY - (do we need this?) */
                outb(cached_master_mask, PIC_MASTER_IMR);

-               outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
+               outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */

        }
        smtc_im_ack_irq(irq);
        raw_spin_unlock_irqrestore(&i8259A_lock, flags);
        }
        smtc_im_ack_irq(irq);
        raw_spin_unlock_irqrestore(&i8259A_lock, flags);

diff --git a/arch/mips/kernel/irq-gt641xx.c b/arch/mips/kernel/irq-gt641xx.c
index 883fc6cead360c086b85e35a0cde476db12b22a4..44a1f792e399a9efa6479ad9924cff46955dc758 100644 (file)
--- a/arch/mips/kernel/irq-gt641xx.c
+++ b/arch/mips/kernel/irq-gt641xx.c
@@ -1,7 +1,7 @@
 /*
  *  GT641xx IRQ routines.
  *
 /*
  *  GT641xx IRQ routines.
  *

- *  Copyright (C) 2007  Yoichi Yuasa <yuasa@linux-mips.org>
+ *  Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>

  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by


@@ -25,7 +25,7 @@
 
 #include <asm/gt64120.h>
 
 
 #include <asm/gt64120.h>
 

-#define GT641XX_IRQ_TO_BIT(irq)        (1U << (irq - GT641XX_IRQ_BASE))
+#define GT641XX_IRQ_TO_BIT(irq) (1U << (irq - GT641XX_IRQ_BASE))

 
 static DEFINE_RAW_SPINLOCK(gt641xx_irq_lock);
 
 
 static DEFINE_RAW_SPINLOCK(gt641xx_irq_lock);
 

diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index 14ac52c5ae86c15a380b9ded947309ed61af80bc..fab40f7d2e0331713883e6b63ce05600b6ff738b 100644 (file)
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -1,6 +1,6 @@
 /*
 /*

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  *
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  *


@@ -86,7 +86,7 @@ static void edge_mask_and_ack_msc_irq(struct irq_data *d)
  */
 void ll_msc_irq(void)
 {
  */
 void ll_msc_irq(void)
 {

-       unsigned int irq;
+       unsigned int irq;

 
        /* read the interrupt vector register */
        MSCIC_READ(MSC01_IC_VEC, irq);
 
        /* read the interrupt vector register */
        MSCIC_READ(MSC01_IC_VEC, irq);

diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c
index b0662cf97ea86532a96a5688bedcbca55c981242..26f4e4c9db1a10b9c93e98ad5825fd714cc4ecf2 100644 (file)
--- a/arch/mips/kernel/irq-rm7000.c
+++ b/arch/mips/kernel/irq-rm7000.c
@@ -1,8 +1,8 @@
 /*
  * Copyright (C) 2003 Ralf Baechle
  *
 /*
  * Copyright (C) 2003 Ralf Baechle
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  *
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  *

diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index a5aa43d07c8ed2fca645cd865bb596eed8db177e..d1fea7a054be6bc3024ef3e8496e7d44f01d0cbf 100644 (file)
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -48,7 +48,7 @@ again:
 }
 
 /*
 }
 
 /*

- * Allocate the 16 legacy interrupts for i8259 devices.  This happens early
+ * Allocate the 16 legacy interrupts for i8259 devices.         This happens early

  * in the kernel initialization so treating allocation failure as BUG() is
  * ok.
  */
  * in the kernel initialization so treating allocation failure as BUG() is
  * ok.
  */

diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 972263bcf403fca9491cd36628651e06f00c279a..0207a44917bf7c0698aa8f48a757a46b09dc7ebe 100644 (file)
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -3,13 +3,13 @@
  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
  *
  * Copyright (C) 2001 Ralf Baechle
  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
  *
  * Copyright (C) 2001 Ralf Baechle

- * Copyright (C) 2005  MIPS Technologies, Inc.  All rights reserved.
- *      Author: Maciej W. Rozycki <macro@mips.com>
+ * Copyright (C) 2005  MIPS Technologies, Inc. All rights reserved.
+ *     Author: Maciej W. Rozycki <macro@mips.com>

  *
  * This file define the irq handler for MIPS CPU interrupts.
  *
  *
  * This file define the irq handler for MIPS CPU interrupts.
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/kernel/irq_txx9.c b/arch/mips/kernel/irq_txx9.c
index b0c55b50218e9e4f1940e3fcd518aa8aecb55fda..ab00e490482f6d91505c79e54ddbc5388c30076d 100644 (file)
--- a/arch/mips/kernel/irq_txx9.c
+++ b/arch/mips/kernel/irq_txx9.c
@@ -1,12 +1,12 @@
 /*
  * Based on linux/arch/mips/jmr3927/rbhma3100/irq.c,
 /*
  * Based on linux/arch/mips/jmr3927/rbhma3100/irq.c,

- *          linux/arch/mips/tx4927/common/tx4927_irq.c,
- *          linux/arch/mips/tx4938/common/irq.c
+ *         linux/arch/mips/tx4927/common/tx4927_irq.c,
+ *         linux/arch/mips/tx4938/common/irq.c

  *
  * Copyright 2001, 2003-2005 MontaVista Software Inc.
  * Author: MontaVista Software, Inc.
  *
  * Copyright 2001, 2003-2005 MontaVista Software Inc.
  * Author: MontaVista Software, Inc.

- *         ahennessy@mvista.com
- *         source@mvista.com
+ *        ahennessy@mvista.com
+ *        source@mvista.com

  * Copyright (C) 2000-2001 Toshiba Corporation
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * Copyright (C) 2000-2001 Toshiba Corporation
  *
  * This file is subject to the terms and conditions of the GNU General Public


@@ -122,7 +122,7 @@ static int txx9_irq_set_type(struct irq_data *d, unsigned int flow_type)
        switch (flow_type & IRQF_TRIGGER_MASK) {
        case IRQF_TRIGGER_RISING:       mode = TXx9_IRCR_UP;    break;
        case IRQF_TRIGGER_FALLING:      mode = TXx9_IRCR_DOWN;  break;
        switch (flow_type & IRQF_TRIGGER_MASK) {
        case IRQF_TRIGGER_RISING:       mode = TXx9_IRCR_UP;    break;
        case IRQF_TRIGGER_FALLING:      mode = TXx9_IRCR_DOWN;  break;

-       case IRQF_TRIGGER_HIGH: mode = TXx9_IRCR_HIGH;  break;
+       case IRQF_TRIGGER_HIGH: mode = TXx9_IRCR_HIGH;  break;

        case IRQF_TRIGGER_LOW:  mode = TXx9_IRCR_LOW;   break;
        default:
                return -EINVAL;
        case IRQF_TRIGGER_LOW:  mode = TXx9_IRCR_LOW;   break;
        default:
                return -EINVAL;

diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c
index 23817a6e32b606cde0a3a714c810db342b91fd0f..fcaac2f132f08e850e1a4088788e6327c2ce4f64 100644 (file)
--- a/arch/mips/kernel/kgdb.c
+++ b/arch/mips/kernel/kgdb.c
@@ -40,7 +40,7 @@ static struct hard_trap_info {
        { 6, SIGBUS },          /* instruction bus error */
        { 7, SIGBUS },          /* data bus error */
        { 9, SIGTRAP },         /* break */
        { 6, SIGBUS },          /* instruction bus error */
        { 7, SIGBUS },          /* data bus error */
        { 9, SIGTRAP },         /* break */

-/*     { 11, SIGILL }, */      /* CPU unusable */
+/*     { 11, SIGILL }, */      /* CPU unusable */

        { 12, SIGFPE },         /* overflow */
        { 13, SIGTRAP },        /* trap */
        { 14, SIGSEGV },        /* virtual instruction cache coherency */
        { 12, SIGFPE },         /* overflow */
        { 13, SIGTRAP },        /* trap */
        { 14, SIGSEGV },        /* virtual instruction cache coherency */


@@ -321,7 +321,7 @@ int kgdb_ll_trap(int cmd, const char *str,
                .regs   = regs,
                .str    = str,
                .err    = err,
                .regs   = regs,
                .str    = str,
                .err    = err,

-               .trapnr = trap,
+               .trapnr = trap,

                .signr  = sig,
 
        };
                .signr  = sig,
 
        };


@@ -371,7 +371,7 @@ int kgdb_arch_init(void)
        union mips_instruction insn = {
                .r_format = {
                        .opcode = spec_op,
        union mips_instruction insn = {
                .r_format = {
                        .opcode = spec_op,

-                       .func   = break_op,
+                       .func   = break_op,

                }
        };
        memcpy(arch_kgdb_ops.gdb_bpt_instr, insn.byte, BREAK_INSTR_SIZE);
                }
        };
        memcpy(arch_kgdb_ops.gdb_bpt_instr, insn.byte, BREAK_INSTR_SIZE);

diff --git a/arch/mips/kernel/kprobes.c b/arch/mips/kernel/kprobes.c
index 158467da9bc1cd134d797ef4a6c3993617523d34..a14be5fa5ec8928f0f8dd4dce9c12286f661d08f 100644 (file)
--- a/arch/mips/kernel/kprobes.c
+++ b/arch/mips/kernel/kprobes.c
@@ -307,7 +307,7 @@ static void prepare_singlestep(struct kprobe *p, struct pt_regs *regs,
 /*
  * Called after single-stepping.  p->addr is the address of the
  * instruction whose first byte has been replaced by the "break 0"
 /*
  * Called after single-stepping.  p->addr is the address of the
  * instruction whose first byte has been replaced by the "break 0"

- * instruction.  To avoid the SMP problems that can occur when we
+ * instruction.         To avoid the SMP problems that can occur when we

  * temporarily put back the original opcode to single-step, we
  * single-stepped a copy of the instruction.  The address of this
  * copy is p->ainsn.insn.
  * temporarily put back the original opcode to single-step, we
  * single-stepped a copy of the instruction.  The address of this
  * copy is p->ainsn.insn.


@@ -535,7 +535,7 @@ void jprobe_return_end(void);
 
 void __kprobes jprobe_return(void)
 {
 
 void __kprobes jprobe_return(void)
 {

-       /* Assembler quirk necessitates this '0,code' business.  */
+       /* Assembler quirk necessitates this '0,code' business.  */

        asm volatile(
                "break 0,%0\n\t"
                ".globl jprobe_return_end\n"
        asm volatile(
                "break 0,%0\n\t"
                ".globl jprobe_return_end\n"


@@ -614,9 +614,9 @@ static int __kprobes trampoline_probe_handler(struct kprobe *p,
         * We can handle this because:
         *     - instances are always inserted at the head of the list
         *     - when multiple return probes are registered for the same
         * We can handle this because:
         *     - instances are always inserted at the head of the list
         *     - when multiple return probes are registered for the same

-        *       function, the first instance's ret_addr will point to the
-        *       real return address, and all the rest will point to
-        *       kretprobe_trampoline
+        *       function, the first instance's ret_addr will point to the
+        *       real return address, and all the rest will point to
+        *       kretprobe_trampoline

         */
        hlist_for_each_entry_safe(ri, node, tmp, head, hlist) {
                if (ri->task != current)
         */
        hlist_for_each_entry_safe(ri, node, tmp, head, hlist) {
                if (ri->task != current)

diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 7adab86c632ce32efdb6550c87f6f6024fb5006f..16bf4a5d3d1ad1cc4de5e061345536878ada2871 100644 (file)
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -76,7 +76,7 @@ out:
        return error;
 }
 
        return error;
 }
 

-#define RLIM_INFINITY32        0x7fffffff
+#define RLIM_INFINITY32 0x7fffffff

 #define RESOURCE32(x) ((x > RLIM_INFINITY32) ? RLIM_INFINITY32 : x)
 
 struct rlimit32 {
 #define RESOURCE32(x) ((x > RLIM_INFINITY32) ? RLIM_INFINITY32 : x)
 
 struct rlimit32 {


@@ -105,7 +105,7 @@ SYSCALL_DEFINE5(32_llseek, unsigned int, fd, unsigned int, offset_high,
 
 /* From the Single Unix Spec: pread & pwrite act like lseek to pos + op +
    lseek back to original location.  They fail just like lseek does on
 
 /* From the Single Unix Spec: pread & pwrite act like lseek to pos + op +
    lseek back to original location.  They fail just like lseek does on

-   non-seekable files.  */
+   non-seekable files. */

 
 SYSCALL_DEFINE6(32_pread, unsigned long, fd, char __user *, buf, size_t, count,
        unsigned long, unused, unsigned long, a4, unsigned long, a5)
 
 SYSCALL_DEFINE6(32_pread, unsigned long, fd, char __user *, buf, size_t, count,
        unsigned long, unused, unsigned long, a4, unsigned long, a5)


@@ -263,7 +263,7 @@ SYSCALL_DEFINE4(32_sendfile, long, out_fd, long, in_fd,
 }
 
 asmlinkage ssize_t sys32_readahead(int fd, u32 pad0, u64 a2, u64 a3,
 }
 
 asmlinkage ssize_t sys32_readahead(int fd, u32 pad0, u64 a2, u64 a3,

-                                   size_t count)
+                                  size_t count)

 {
        return sys_readahead(fd, merge_64(a2, a3), count);
 }
 {
        return sys_readahead(fd, merge_64(a2, a3), count);
 }


@@ -292,7 +292,7 @@ asmlinkage long sys32_fallocate(int fd, int mode, unsigned offset_a2,
        unsigned offset_a3, unsigned len_a4, unsigned len_a5)
 {
        return sys_fallocate(fd, mode, merge_64(offset_a2, offset_a3),
        unsigned offset_a3, unsigned len_a4, unsigned len_a5)
 {
        return sys_fallocate(fd, mode, merge_64(offset_a2, offset_a3),

-                            merge_64(len_a4, len_a5));
+                            merge_64(len_a4, len_a5));

 }
 
 save_static_function(sys32_clone);
 }
 
 save_static_function(sys32_clone);


@@ -313,7 +313,7 @@ _sys32_clone(nabi_no_regargs struct pt_regs regs)
           syscall() works.  */
        child_tidptr = (int __user *) __dummy4;
        return do_fork(clone_flags, newsp, 0,
           syscall() works.  */
        child_tidptr = (int __user *) __dummy4;
        return do_fork(clone_flags, newsp, 0,

-                      parent_tidptr, child_tidptr);
+                      parent_tidptr, child_tidptr);

 }
 
 asmlinkage long sys32_lookup_dcookie(u32 a0, u32 a1, char __user *buf,
 }
 
 asmlinkage long sys32_lookup_dcookie(u32 a0, u32 a1, char __user *buf,


@@ -323,7 +323,7 @@ asmlinkage long sys32_lookup_dcookie(u32 a0, u32 a1, char __user *buf,
 }
 
 SYSCALL_DEFINE6(32_fanotify_mark, int, fanotify_fd, unsigned int, flags,
 }
 
 SYSCALL_DEFINE6(32_fanotify_mark, int, fanotify_fd, unsigned int, flags,

-               u64, a3, u64, a4, int, dfd, const char  __user *, pathname)
+               u64, a3, u64, a4, int, dfd, const char  __user *, pathname)

 {
        return sys_fanotify_mark(fanotify_fd, flags, merge_64(a3, a4),
                                 dfd, pathname);
 {
        return sys_fanotify_mark(fanotify_fd, flags, merge_64(a3, a4),
                                 dfd, pathname);

diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c
index df1e3e455f9a872c70c2c110755cdf1e0b8cfe03..6e58e97fcd39bb09581d39030a38940cc9a4f848 100644 (file)
--- a/arch/mips/kernel/mips_ksyms.c
+++ b/arch/mips/kernel/mips_ksyms.c
@@ -17,9 +17,9 @@
 
 extern void *__bzero(void *__s, size_t __count);
 extern long __strncpy_from_user_nocheck_asm(char *__to,
 
 extern void *__bzero(void *__s, size_t __count);
 extern long __strncpy_from_user_nocheck_asm(char *__to,

-                                            const char *__from, long __len);
+                                           const char *__from, long __len);

 extern long __strncpy_from_user_asm(char *__to, const char *__from,
 extern long __strncpy_from_user_asm(char *__to, const char *__from,

-                                    long __len);
+                                   long __len);

 extern long __strlen_user_nocheck_asm(const char *s);
 extern long __strlen_user_asm(const char *s);
 extern long __strnlen_user_nocheck_asm(const char *s);
 extern long __strlen_user_nocheck_asm(const char *s);
 extern long __strlen_user_asm(const char *s);
 extern long __strnlen_user_nocheck_asm(const char *s);

diff --git a/arch/mips/kernel/module-rela.c b/arch/mips/kernel/module-rela.c
index 61d60028b888d20382c25bd32ce84527b9c6aa44..2b70723071c322018dbb616a0b158bae4da85d0e 100644 (file)
--- a/arch/mips/kernel/module-rela.c
+++ b/arch/mips/kernel/module-rela.c
@@ -55,7 +55,7 @@ static int apply_r_mips_26_rela(struct module *me, u32 *location, Elf_Addr v)
 static int apply_r_mips_hi16_rela(struct module *me, u32 *location, Elf_Addr v)
 {
        *location = (*location & 0xffff0000) |
 static int apply_r_mips_hi16_rela(struct module *me, u32 *location, Elf_Addr v)
 {
        *location = (*location & 0xffff0000) |

-                   ((((long long) v + 0x8000LL) >> 16) & 0xffff);
+                   ((((long long) v + 0x8000LL) >> 16) & 0xffff);

 
        return 0;
 }
 
        return 0;
 }


@@ -78,7 +78,7 @@ static int apply_r_mips_higher_rela(struct module *me, u32 *location,
                                    Elf_Addr v)
 {
        *location = (*location & 0xffff0000) |
                                    Elf_Addr v)
 {
        *location = (*location & 0xffff0000) |

-                   ((((long long) v + 0x80008000LL) >> 32) & 0xffff);
+                   ((((long long) v + 0x80008000LL) >> 32) & 0xffff);

 
        return 0;
 }
 
        return 0;
 }


@@ -87,7 +87,7 @@ static int apply_r_mips_highest_rela(struct module *me, u32 *location,
                                     Elf_Addr v)
 {
        *location = (*location & 0xffff0000) |
                                     Elf_Addr v)
 {
        *location = (*location & 0xffff0000) |

-                   ((((long long) v + 0x800080008000LL) >> 48) & 0xffff);
+                   ((((long long) v + 0x800080008000LL) >> 48) & 0xffff);

 
        return 0;
 }
 
        return 0;
 }

diff --git a/arch/mips/kernel/module.c b/arch/mips/kernel/module.c
index 07ff5812ffaf7503826f74af41aa3a7e7dce4a6f..977a623d9253ca3580084652ee264b3c4f59a6c2 100644 (file)
--- a/arch/mips/kernel/module.c
+++ b/arch/mips/kernel/module.c
@@ -79,7 +79,7 @@ static int apply_r_mips_26_rel(struct module *me, u32 *location, Elf_Addr v)
        }
 
        *location = (*location & ~0x03ffffff) |
        }
 
        *location = (*location & ~0x03ffffff) |

-                   ((*location + (v >> 2)) & 0x03ffffff);
+                   ((*location + (v >> 2)) & 0x03ffffff);

 
        return 0;
 }
 
        return 0;
 }


@@ -122,7 +122,7 @@ static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v)
        struct mips_hi16 *l;
        Elf_Addr val, vallo;
 
        struct mips_hi16 *l;
        Elf_Addr val, vallo;
 

-       /* Sign extend the addend we extract from the lo insn.  */
+       /* Sign extend the addend we extract from the lo insn.  */

        vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000;
 
        if (me->arch.r_mips_hi16_list != NULL) {
        vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000;
 
        if (me->arch.r_mips_hi16_list != NULL) {


@@ -165,7 +165,7 @@ static int apply_r_mips_lo16_rel(struct module *me, u32 *location, Elf_Addr v)
        }
 
        /*
        }
 
        /*

-        * Ok, we're done with the HI16 relocs.  Now deal with the LO16.
+        * Ok, we're done with the HI16 relocs.  Now deal with the LO16.

         */
        val = v + vallo;
        insnlo = (insnlo & ~0xffff) | (val & 0xffff);
         */
        val = v + vallo;
        insnlo = (insnlo & ~0xffff) | (val & 0xffff);


@@ -230,7 +230,7 @@ int apply_relocate(Elf_Shdr *sechdrs, const char *strtab,
        }
 
        /*
        }
 
        /*

-        * Normally the hi16 list should be deallocated at this point.  A
+        * Normally the hi16 list should be deallocated at this point.  A

         * malformed binary however could contain a series of R_MIPS_HI16
         * relocations not followed by a R_MIPS_LO16 relocation.  In that
         * case, free up the list and return an error.
         * malformed binary however could contain a series of R_MIPS_HI16
         * relocations not followed by a R_MIPS_LO16 relocation.  In that
         * case, free up the list and return an error.


@@ -261,7 +261,7 @@ const struct exception_table_entry *search_module_dbetables(unsigned long addr)
        spin_unlock_irqrestore(&dbe_lock, flags);
 
        /* Now, if we found one, we are running inside it now, hence
        spin_unlock_irqrestore(&dbe_lock, flags);
 
        /* Now, if we found one, we are running inside it now, hence

-           we cannot unload the module, hence no refcnt needed. */
+          we cannot unload the module, hence no refcnt needed. */

        return e;
 }
 
        return e;
 }
 

diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
index 207f1341578ba73abcffcd0ee7bbeda43f1e5643..0e23343eb0a98cb2f620262e06b775c814a433de 100644 (file)
--- a/arch/mips/kernel/octeon_switch.S
+++ b/arch/mips/kernel/octeon_switch.S
@@ -30,7 +30,7 @@
 
 /*
  * task_struct *resume(task_struct *prev, task_struct *next,
 
 /*
  * task_struct *resume(task_struct *prev, task_struct *next,

- *                     struct thread_info *next_ti, int usedfpu)
+ *                    struct thread_info *next_ti, int usedfpu)

  */
        .align  7
        LEAF(resume)
  */
        .align  7
        LEAF(resume)


@@ -69,7 +69,7 @@
 1:
 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
        /* Check if we need to store CVMSEG state */
 1:
 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
        /* Check if we need to store CVMSEG state */

-       mfc0    t0, $11,7       /* CvmMemCtl */
+       mfc0    t0, $11,7       /* CvmMemCtl */

        bbit0   t0, 6, 3f       /* Is user access enabled? */
 
        /* Store the CVMSEG state */
        bbit0   t0, 6, 3f       /* Is user access enabled? */
 
        /* Store the CVMSEG state */


@@ -77,8 +77,8 @@
        andi    t0, 0x3f
        /* Multiply * (cache line size/sizeof(long)/2) */
        sll     t0, 7-LONGLOG-1
        andi    t0, 0x3f
        /* Multiply * (cache line size/sizeof(long)/2) */
        sll     t0, 7-LONGLOG-1

-       li      t1, -32768      /* Base address of CVMSEG */
-       LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */
+       li      t1, -32768      /* Base address of CVMSEG */
+       LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */

        synciobdma
 2:
        .set noreorder
        synciobdma
 2:
        .set noreorder


@@ -89,13 +89,13 @@
        LONG_S  t8, 0(t2)       /* Store CVMSEG to thread storage */
        LONG_ADDU t2, LONGSIZE*2 /* Increment loc in thread storage */
        bnez    t0, 2b          /* Loop until we've copied it all */
        LONG_S  t8, 0(t2)       /* Store CVMSEG to thread storage */
        LONG_ADDU t2, LONGSIZE*2 /* Increment loc in thread storage */
        bnez    t0, 2b          /* Loop until we've copied it all */

-        LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
+        LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */

        .set reorder
 
        /* Disable access to CVMSEG */
        .set reorder
 
        /* Disable access to CVMSEG */

-       mfc0    t0, $11,7       /* CvmMemCtl */
+       mfc0    t0, $11,7       /* CvmMemCtl */

        xori    t0, t0, 0x40    /* Bit 6 is CVMSEG user enable */
        xori    t0, t0, 0x40    /* Bit 6 is CVMSEG user enable */

-       mtc0    t0, $11,7       /* CvmMemCtl */
+       mtc0    t0, $11,7       /* CvmMemCtl */

 #endif
 3:
        /*
 #endif
 3:
        /*


@@ -133,7 +133,7 @@
 
        dmfc0   t9, $9,7        /* CvmCtl register. */
 
 
        dmfc0   t9, $9,7        /* CvmCtl register. */
 

-        /* Save the COP2 CRC state */
+       /* Save the COP2 CRC state */

        dmfc2   t0, 0x0201
        dmfc2   t1, 0x0202
        dmfc2   t2, 0x0200
        dmfc2   t0, 0x0201
        dmfc2   t1, 0x0202
        dmfc2   t2, 0x0200


@@ -149,30 +149,30 @@
        sd      t0, OCTEON_CP2_LLM_DAT(a0)
        sd      t1, OCTEON_CP2_LLM_DAT+8(a0)
 
        sd      t0, OCTEON_CP2_LLM_DAT(a0)
        sd      t1, OCTEON_CP2_LLM_DAT+8(a0)
 

-1:      bbit1  t9, 26, 3f      /* done if CvmCtl[NOCRYPTO] set */
+1:     bbit1   t9, 26, 3f      /* done if CvmCtl[NOCRYPTO] set */

 
        /* Save the COP2 crypto state */
 
        /* Save the COP2 crypto state */

-        /* this part is mostly common to both pass 1 and later revisions */
-       dmfc2   t0, 0x0084
-       dmfc2   t1, 0x0080
-       dmfc2   t2, 0x0081
-       dmfc2   t3, 0x0082
+       /* this part is mostly common to both pass 1 and later revisions */
+       dmfc2   t0, 0x0084
+       dmfc2   t1, 0x0080
+       dmfc2   t2, 0x0081
+       dmfc2   t3, 0x0082

        sd      t0, OCTEON_CP2_3DES_IV(a0)
        sd      t0, OCTEON_CP2_3DES_IV(a0)

-       dmfc2   t0, 0x0088
+       dmfc2   t0, 0x0088

        sd      t1, OCTEON_CP2_3DES_KEY(a0)
        sd      t1, OCTEON_CP2_3DES_KEY(a0)

-       dmfc2   t1, 0x0111                      /* only necessary for pass 1 */
+       dmfc2   t1, 0x0111                      /* only necessary for pass 1 */

        sd      t2, OCTEON_CP2_3DES_KEY+8(a0)
        sd      t2, OCTEON_CP2_3DES_KEY+8(a0)

-       dmfc2   t2, 0x0102
+       dmfc2   t2, 0x0102

        sd      t3, OCTEON_CP2_3DES_KEY+16(a0)
        sd      t3, OCTEON_CP2_3DES_KEY+16(a0)

-       dmfc2   t3, 0x0103
+       dmfc2   t3, 0x0103

        sd      t0, OCTEON_CP2_3DES_RESULT(a0)
        sd      t0, OCTEON_CP2_3DES_RESULT(a0)

-       dmfc2   t0, 0x0104
-       sd      t1, OCTEON_CP2_AES_INP0(a0)     /* only necessary for pass 1 */
-       dmfc2   t1, 0x0105
+       dmfc2   t0, 0x0104
+       sd      t1, OCTEON_CP2_AES_INP0(a0)     /* only necessary for pass 1 */
+       dmfc2   t1, 0x0105

        sd      t2, OCTEON_CP2_AES_IV(a0)
        dmfc2   t2, 0x0106
        sd      t3, OCTEON_CP2_AES_IV+8(a0)
        sd      t2, OCTEON_CP2_AES_IV(a0)
        dmfc2   t2, 0x0106
        sd      t3, OCTEON_CP2_AES_IV+8(a0)

-       dmfc2   t3, 0x0107
+       dmfc2   t3, 0x0107

        sd      t0, OCTEON_CP2_AES_KEY(a0)
        dmfc2   t0, 0x0110
        sd      t1, OCTEON_CP2_AES_KEY+8(a0)
        sd      t0, OCTEON_CP2_AES_KEY(a0)
        dmfc2   t0, 0x0110
        sd      t1, OCTEON_CP2_AES_KEY+8(a0)


@@ -180,7 +180,7 @@
        sd      t2, OCTEON_CP2_AES_KEY+16(a0)
        dmfc2   t2, 0x0101
        sd      t3, OCTEON_CP2_AES_KEY+24(a0)
        sd      t2, OCTEON_CP2_AES_KEY+16(a0)
        dmfc2   t2, 0x0101
        sd      t3, OCTEON_CP2_AES_KEY+24(a0)

-       mfc0    t3, $15,0       /* Get the processor ID register */
+       mfc0    t3, $15,0       /* Get the processor ID register */

        sd      t0, OCTEON_CP2_AES_KEYLEN(a0)
        li      t0, 0x000d0000  /* This is the processor ID of Octeon Pass1 */
        sd      t1, OCTEON_CP2_AES_RESULT(a0)
        sd      t0, OCTEON_CP2_AES_KEYLEN(a0)
        li      t0, 0x000d0000  /* This is the processor ID of Octeon Pass1 */
        sd      t1, OCTEON_CP2_AES_RESULT(a0)


@@ -188,7 +188,7 @@
        /* Skip to the Pass1 version of the remainder of the COP2 state */
        beq     t3, t0, 2f
 
        /* Skip to the Pass1 version of the remainder of the COP2 state */
        beq     t3, t0, 2f
 

-        /* the non-pass1 state when !CvmCtl[NOCRYPTO] */
+       /* the non-pass1 state when !CvmCtl[NOCRYPTO] */

        dmfc2   t1, 0x0240
        dmfc2   t2, 0x0241
        dmfc2   t3, 0x0242
        dmfc2   t1, 0x0240
        dmfc2   t2, 0x0241
        dmfc2   t3, 0x0242


@@ -214,7 +214,7 @@
        sd      t2, OCTEON_CP2_HSH_DATW+72(a0)
        dmfc2   t2, 0x024D
        sd      t3, OCTEON_CP2_HSH_DATW+80(a0)
        sd      t2, OCTEON_CP2_HSH_DATW+72(a0)
        dmfc2   t2, 0x024D
        sd      t3, OCTEON_CP2_HSH_DATW+80(a0)

-       dmfc2   t3, 0x024E
+       dmfc2   t3, 0x024E

        sd      t0, OCTEON_CP2_HSH_DATW+88(a0)
        dmfc2   t0, 0x0250
        sd      t1, OCTEON_CP2_HSH_DATW+96(a0)
        sd      t0, OCTEON_CP2_HSH_DATW+88(a0)
        dmfc2   t0, 0x0250
        sd      t1, OCTEON_CP2_HSH_DATW+96(a0)


@@ -232,9 +232,9 @@
        sd      t3, OCTEON_CP2_HSH_IVW+24(a0)
        dmfc2   t3, 0x0257
        sd      t0, OCTEON_CP2_HSH_IVW+32(a0)
        sd      t3, OCTEON_CP2_HSH_IVW+24(a0)
        dmfc2   t3, 0x0257
        sd      t0, OCTEON_CP2_HSH_IVW+32(a0)

-       dmfc2   t0, 0x0258
+       dmfc2   t0, 0x0258

        sd      t1, OCTEON_CP2_HSH_IVW+40(a0)
        sd      t1, OCTEON_CP2_HSH_IVW+40(a0)

-       dmfc2   t1, 0x0259
+       dmfc2   t1, 0x0259

        sd      t2, OCTEON_CP2_HSH_IVW+48(a0)
        dmfc2   t2, 0x025E
        sd      t3, OCTEON_CP2_HSH_IVW+56(a0)
        sd      t2, OCTEON_CP2_HSH_IVW+48(a0)
        dmfc2   t2, 0x025E
        sd      t3, OCTEON_CP2_HSH_IVW+56(a0)


@@ -247,7 +247,7 @@
        sd      t0, OCTEON_CP2_GFM_RESULT+8(a0)
        jr      ra
 
        sd      t0, OCTEON_CP2_GFM_RESULT+8(a0)
        jr      ra
 

-2:      /* pass 1 special stuff when !CvmCtl[NOCRYPTO] */
+2:     /* pass 1 special stuff when !CvmCtl[NOCRYPTO] */

        dmfc2   t3, 0x0040
        dmfc2   t0, 0x0041
        dmfc2   t1, 0x0042
        dmfc2   t3, 0x0040
        dmfc2   t0, 0x0041
        dmfc2   t1, 0x0042


@@ -269,7 +269,7 @@
        sd      t3, OCTEON_CP2_HSH_IVW+8(a0)
        sd      t0, OCTEON_CP2_HSH_IVW+16(a0)
 
        sd      t3, OCTEON_CP2_HSH_IVW+8(a0)
        sd      t0, OCTEON_CP2_HSH_IVW+16(a0)
 

-3:      /* pass 1 or CvmCtl[NOCRYPTO] set */
+3:     /* pass 1 or CvmCtl[NOCRYPTO] set */

        jr      ra
        END(octeon_cop2_save)
 
        jr      ra
        END(octeon_cop2_save)
 


@@ -280,19 +280,19 @@
        .set push
        .set noreorder
        LEAF(octeon_cop2_restore)
        .set push
        .set noreorder
        LEAF(octeon_cop2_restore)

-        /* First cache line was prefetched before the call */
-        pref    4,  128(a0)
+       /* First cache line was prefetched before the call */
+       pref    4,  128(a0)

        dmfc0   t9, $9,7        /* CvmCtl register. */
 
        dmfc0   t9, $9,7        /* CvmCtl register. */
 

-        pref    4,  256(a0)
+       pref    4,  256(a0)

        ld      t0, OCTEON_CP2_CRC_IV(a0)
        ld      t0, OCTEON_CP2_CRC_IV(a0)

-        pref    4,  384(a0)
+       pref    4,  384(a0)

        ld      t1, OCTEON_CP2_CRC_LENGTH(a0)
        ld      t2, OCTEON_CP2_CRC_POLY(a0)
 
        /* Restore the COP2 CRC state */
        dmtc2   t0, 0x0201
        ld      t1, OCTEON_CP2_CRC_LENGTH(a0)
        ld      t2, OCTEON_CP2_CRC_POLY(a0)
 
        /* Restore the COP2 CRC state */
        dmtc2   t0, 0x0201

-       dmtc2   t1, 0x1202
+       dmtc2   t1, 0x1202

        bbit1   t9, 28, 2f      /* Skip LLM if CvmCtl[NODFA_CP2] is set */
         dmtc2  t2, 0x4200
 
        bbit1   t9, 28, 2f      /* Skip LLM if CvmCtl[NODFA_CP2] is set */
         dmtc2  t2, 0x4200
 


@@ -310,19 +310,19 @@
        ld      t0, OCTEON_CP2_3DES_IV(a0)
        ld      t1, OCTEON_CP2_3DES_KEY(a0)
        ld      t2, OCTEON_CP2_3DES_KEY+8(a0)
        ld      t0, OCTEON_CP2_3DES_IV(a0)
        ld      t1, OCTEON_CP2_3DES_KEY(a0)
        ld      t2, OCTEON_CP2_3DES_KEY+8(a0)

-       dmtc2   t0, 0x0084
+       dmtc2   t0, 0x0084

        ld      t0, OCTEON_CP2_3DES_KEY+16(a0)
        ld      t0, OCTEON_CP2_3DES_KEY+16(a0)

-       dmtc2   t1, 0x0080
+       dmtc2   t1, 0x0080

        ld      t1, OCTEON_CP2_3DES_RESULT(a0)
        ld      t1, OCTEON_CP2_3DES_RESULT(a0)

-       dmtc2   t2, 0x0081
+       dmtc2   t2, 0x0081

        ld      t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */
        dmtc2   t0, 0x0082
        ld      t0, OCTEON_CP2_AES_IV(a0)
        ld      t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */
        dmtc2   t0, 0x0082
        ld      t0, OCTEON_CP2_AES_IV(a0)

-       dmtc2   t1, 0x0098
+       dmtc2   t1, 0x0098

        ld      t1, OCTEON_CP2_AES_IV+8(a0)
        ld      t1, OCTEON_CP2_AES_IV+8(a0)

-       dmtc2   t2, 0x010A                  /* only really needed for pass 1 */
+       dmtc2   t2, 0x010A                  /* only really needed for pass 1 */

        ld      t2, OCTEON_CP2_AES_KEY(a0)
        ld      t2, OCTEON_CP2_AES_KEY(a0)

-       dmtc2   t0, 0x0102
+       dmtc2   t0, 0x0102

        ld      t0, OCTEON_CP2_AES_KEY+8(a0)
        dmtc2   t1, 0x0103
        ld      t1, OCTEON_CP2_AES_KEY+16(a0)
        ld      t0, OCTEON_CP2_AES_KEY+8(a0)
        dmtc2   t1, 0x0103
        ld      t1, OCTEON_CP2_AES_KEY+16(a0)


@@ -334,14 +334,14 @@
        ld      t1, OCTEON_CP2_AES_RESULT(a0)
        dmtc2   t2, 0x0107
        ld      t2, OCTEON_CP2_AES_RESULT+8(a0)
        ld      t1, OCTEON_CP2_AES_RESULT(a0)
        dmtc2   t2, 0x0107
        ld      t2, OCTEON_CP2_AES_RESULT+8(a0)

-       mfc0    t3, $15,0       /* Get the processor ID register */
+       mfc0    t3, $15,0       /* Get the processor ID register */

        dmtc2   t0, 0x0110
        li      t0, 0x000d0000  /* This is the processor ID of Octeon Pass1 */
        dmtc2   t1, 0x0100
        bne     t0, t3, 3f      /* Skip the next stuff for non-pass1 */
         dmtc2  t2, 0x0101
 
        dmtc2   t0, 0x0110
        li      t0, 0x000d0000  /* This is the processor ID of Octeon Pass1 */
        dmtc2   t1, 0x0100
        bne     t0, t3, 3f      /* Skip the next stuff for non-pass1 */
         dmtc2  t2, 0x0101
 

-        /* this code is specific for pass 1 */
+       /* this code is specific for pass 1 */

        ld      t0, OCTEON_CP2_HSH_DATW(a0)
        ld      t1, OCTEON_CP2_HSH_DATW+8(a0)
        ld      t2, OCTEON_CP2_HSH_DATW+16(a0)
        ld      t0, OCTEON_CP2_HSH_DATW(a0)
        ld      t1, OCTEON_CP2_HSH_DATW+8(a0)
        ld      t2, OCTEON_CP2_HSH_DATW+16(a0)


@@ -361,10 +361,10 @@
        ld      t0, OCTEON_CP2_HSH_IVW+16(a0)
        dmtc2   t1, 0x0048
        dmtc2   t2, 0x0049
        ld      t0, OCTEON_CP2_HSH_IVW+16(a0)
        dmtc2   t1, 0x0048
        dmtc2   t2, 0x0049

-        b done_restore   /* unconditional branch */
+       b done_restore   /* unconditional branch */

         dmtc2  t0, 0x004A
 
         dmtc2  t0, 0x004A
 

-3:      /* this is post-pass1 code */
+3:     /* this is post-pass1 code */

        ld      t2, OCTEON_CP2_HSH_DATW(a0)
        ld      t0, OCTEON_CP2_HSH_DATW+8(a0)
        ld      t1, OCTEON_CP2_HSH_DATW+16(a0)
        ld      t2, OCTEON_CP2_HSH_DATW(a0)
        ld      t0, OCTEON_CP2_HSH_DATW+8(a0)
        ld      t1, OCTEON_CP2_HSH_DATW+16(a0)


@@ -433,7 +433,7 @@ done_restore:
  * sp is assumed to point to a struct pt_regs
  *
  * NOTE: This is called in SAVE_SOME in stackframe.h. It can only
  * sp is assumed to point to a struct pt_regs
  *
  * NOTE: This is called in SAVE_SOME in stackframe.h. It can only

- *       safely modify k0 and k1.
+ *      safely modify k0 and k1.

  */
        .align  7
        .set push
  */
        .align  7
        .set push


@@ -446,14 +446,14 @@ done_restore:
        /* Save the multiplier state */
        v3mulu  k0, $0, $0
        v3mulu  k1, $0, $0
        /* Save the multiplier state */
        v3mulu  k0, $0, $0
        v3mulu  k1, $0, $0

-       sd      k0, PT_MTP(sp)        /* PT_MTP    has P0 */
+       sd      k0, PT_MTP(sp)        /* PT_MTP    has P0 */

        v3mulu  k0, $0, $0
        sd      k1, PT_MTP+8(sp)      /* PT_MTP+8  has P1 */
        ori     k1, $0, 1
        v3mulu  k1, k1, $0
        sd      k0, PT_MTP+16(sp)     /* PT_MTP+16 has P2 */
        v3mulu  k0, $0, $0
        v3mulu  k0, $0, $0
        sd      k1, PT_MTP+8(sp)      /* PT_MTP+8  has P1 */
        ori     k1, $0, 1
        v3mulu  k1, k1, $0
        sd      k0, PT_MTP+16(sp)     /* PT_MTP+16 has P2 */
        v3mulu  k0, $0, $0

-       sd      k1, PT_MPL(sp)        /* PT_MPL    has MPL0 */
+       sd      k1, PT_MPL(sp)        /* PT_MPL    has MPL0 */

        v3mulu  k1, $0, $0
        sd      k0, PT_MPL+8(sp)      /* PT_MPL+8  has MPL1 */
        jr      ra
        v3mulu  k1, $0, $0
        sd      k0, PT_MPL+8(sp)      /* PT_MPL+8  has MPL1 */
        jr      ra


@@ -475,19 +475,19 @@ done_restore:
        .set noreorder
        LEAF(octeon_mult_restore)
        dmfc0   k1, $9,7                /* CvmCtl register. */
        .set noreorder
        LEAF(octeon_mult_restore)
        dmfc0   k1, $9,7                /* CvmCtl register. */

-       ld      v0, PT_MPL(sp)          /* MPL0 */
-       ld      v1, PT_MPL+8(sp)        /* MPL1 */
-       ld      k0, PT_MPL+16(sp)       /* MPL2 */
+       ld      v0, PT_MPL(sp)          /* MPL0 */
+       ld      v1, PT_MPL+8(sp)        /* MPL1 */
+       ld      k0, PT_MPL+16(sp)       /* MPL2 */

        bbit1   k1, 27, 1f              /* Skip CvmCtl[NOMUL] */
        /* Normally falls through, so no time wasted here */
        nop
 
        /* Restore the multiplier state */
        bbit1   k1, 27, 1f              /* Skip CvmCtl[NOMUL] */
        /* Normally falls through, so no time wasted here */
        nop
 
        /* Restore the multiplier state */

-       ld      k1, PT_MTP+16(sp)       /* P2 */
+       ld      k1, PT_MTP+16(sp)       /* P2 */

        MTM0    v0                      /* MPL0 */
        ld      v0, PT_MTP+8(sp)        /* P1 */
        MTM1    v1                      /* MPL1 */
        MTM0    v0                      /* MPL0 */
        ld      v0, PT_MTP+8(sp)        /* P1 */
        MTM1    v1                      /* MPL1 */

-       ld      v1, PT_MTP(sp)          /* P0 */
+       ld      v1, PT_MTP(sp)          /* P0 */

        MTM2    k0                      /* MPL2 */
        MTP2    k1                      /* P2 */
        MTP1    v0                      /* P1 */
        MTM2    k0                      /* MPL2 */
        MTP2    k1                      /* P2 */
        MTP1    v0                      /* P1 */

diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index d9c81c5a6c90cfc0800fb96984697aecee900088..45f1ffcf1a4b6299b181cf99e9d08cac59da6cfb 100644 (file)
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -103,13 +103,13 @@ static struct mips_pmu mipspmu;
 
 #define M_CONFIG1_PC   (1 << 4)
 
 
 #define M_CONFIG1_PC   (1 << 4)
 

-#define M_PERFCTL_EXL                  (1      <<  0)
-#define M_PERFCTL_KERNEL               (1      <<  1)
-#define M_PERFCTL_SUPERVISOR           (1      <<  2)
-#define M_PERFCTL_USER                 (1      <<  3)
-#define M_PERFCTL_INTERRUPT_ENABLE     (1      <<  4)
+#define M_PERFCTL_EXL                  (1      <<  0)
+#define M_PERFCTL_KERNEL               (1      <<  1)
+#define M_PERFCTL_SUPERVISOR           (1      <<  2)
+#define M_PERFCTL_USER                 (1      <<  3)
+#define M_PERFCTL_INTERRUPT_ENABLE     (1      <<  4)

 #define M_PERFCTL_EVENT(event)         (((event) & 0x3ff)  << 5)
 #define M_PERFCTL_EVENT(event)         (((event) & 0x3ff)  << 5)

-#define M_PERFCTL_VPEID(vpe)           ((vpe)    << 16)
+#define M_PERFCTL_VPEID(vpe)           ((vpe)    << 16)

 
 #ifdef CONFIG_CPU_BMIPS5000
 #define M_PERFCTL_MT_EN(filter)                0
 
 #ifdef CONFIG_CPU_BMIPS5000
 #define M_PERFCTL_MT_EN(filter)                0


@@ -117,13 +117,13 @@ static struct mips_pmu mipspmu;
 #define M_PERFCTL_MT_EN(filter)                ((filter) << 20)
 #endif /* CONFIG_CPU_BMIPS5000 */
 
 #define M_PERFCTL_MT_EN(filter)                ((filter) << 20)
 #endif /* CONFIG_CPU_BMIPS5000 */
 

-#define    M_TC_EN_ALL                 M_PERFCTL_MT_EN(0)
-#define    M_TC_EN_VPE                 M_PERFCTL_MT_EN(1)
-#define    M_TC_EN_TC                  M_PERFCTL_MT_EN(2)
-#define M_PERFCTL_TCID(tcid)           ((tcid)   << 22)
-#define M_PERFCTL_WIDE                 (1      << 30)
-#define M_PERFCTL_MORE                 (1      << 31)
-#define M_PERFCTL_TC                   (1      << 30)
+#define           M_TC_EN_ALL                  M_PERFCTL_MT_EN(0)
+#define           M_TC_EN_VPE                  M_PERFCTL_MT_EN(1)
+#define           M_TC_EN_TC                   M_PERFCTL_MT_EN(2)
+#define M_PERFCTL_TCID(tcid)           ((tcid)   << 22)
+#define M_PERFCTL_WIDE                 (1      << 30)
+#define M_PERFCTL_MORE                 (1      << 31)
+#define M_PERFCTL_TC                   (1      << 30)

 
 #define M_PERFCTL_COUNT_EVENT_WHENEVER (M_PERFCTL_EXL |                \
                                        M_PERFCTL_KERNEL |              \
 
 #define M_PERFCTL_COUNT_EVENT_WHENEVER (M_PERFCTL_EXL |                \
                                        M_PERFCTL_KERNEL |              \


@@ -827,7 +827,7 @@ static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = {
        [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
        [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL },
        [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL },
        [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
        [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL },
        [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL },

-       [PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL  },
+       [PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL  },

        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL },
        [PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL },
        [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL },
        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL },
        [PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL },
        [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL },


@@ -1371,7 +1371,7 @@ static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
         (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 ||           \
         (r) == 176 || ((b) >= 50 && (b) <= 55) ||                      \
         ((b) >= 64 && (b) <= 67))
         (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 ||           \
         (r) == 176 || ((b) >= 50 && (b) <= 55) ||                      \
         ((b) >= 64 && (b) <= 67))

-#define IS_RANGE_V_34K_EVENT(r)        ((r) == 47)
+#define IS_RANGE_V_34K_EVENT(r) ((r) == 47)

 #endif
 
 /* 74K */
 #endif
 
 /* 74K */

diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 07dff54f2ce8b238e4b955082ed12bf9e2f1fd43..9dafed0581361c3f6141c1a60523a68caa397dcf 100644 (file)
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -1,7 +1,7 @@
 /*
  *  Copyright (C) 1995, 1996, 2001  Ralf Baechle
  *  Copyright (C) 2001, 2004  MIPS Technologies, Inc.
 /*
  *  Copyright (C) 1995, 1996, 2001  Ralf Baechle
  *  Copyright (C) 2001, 2004  MIPS Technologies, Inc.

- *  Copyright (C) 2004  Maciej W. Rozycki
+ *  Copyright (C) 2004 Maciej W. Rozycki

  */
 #include <linux/delay.h>
 #include <linux/kernel.h>
  */
 #include <linux/delay.h>
 #include <linux/kernel.h>

diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index a11c6f9fdd5e0f2e05b306936cb98464f88a130d..902e7803fcfa4a38c7ed8b47c611db290cd41931 100644 (file)
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -154,8 +154,8 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
                return 0;
        }
        *childregs = *regs;
                return 0;
        }
        *childregs = *regs;

-       childregs->regs[7] = 0; /* Clear error flag */
-       childregs->regs[2] = 0; /* Child gets zero as return value */
+       childregs->regs[7] = 0; /* Clear error flag */
+       childregs->regs[2] = 0; /* Child gets zero as return value */

        childregs->regs[29] = usp;
        ti->addr_limit = USER_DS;
 
        childregs->regs[29] = usp;
        ti->addr_limit = USER_DS;
 

diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 4812c6d916e4c5af7bf36f12aa7f1cdce4ad533f..9c6299c733a317ce5c975ce91b054297502ba960 100644 (file)
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -50,7 +50,7 @@ void ptrace_disable(struct task_struct *child)
 }
 
 /*
 }
 
 /*

- * Read a general register set.  We always use the 64-bit format, even
+ * Read a general register set.         We always use the 64-bit format, even

  * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
  * Registers are sign extended to fill the available space.
  */
  * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
  * Registers are sign extended to fill the available space.
  */


@@ -326,7 +326,7 @@ long arch_ptrace(struct task_struct *child, long request,
                case FPC_CSR:
                        tmp = child->thread.fpu.fcr31;
                        break;
                case FPC_CSR:
                        tmp = child->thread.fpu.fcr31;
                        break;

-               case FPC_EIR: { /* implementation / version register */
+               case FPC_EIR: { /* implementation / version register */

                        unsigned int flags;
 #ifdef CONFIG_MIPS_MT_SMTC
                        unsigned long irqflags;
                        unsigned int flags;
 #ifdef CONFIG_MIPS_MT_SMTC
                        unsigned long irqflags;


@@ -520,10 +520,10 @@ static inline int audit_arch(void)
 {
        int arch = EM_MIPS;
 #ifdef CONFIG_64BIT
 {
        int arch = EM_MIPS;
 #ifdef CONFIG_64BIT

-       arch |=  __AUDIT_ARCH_64BIT;
+       arch |=  __AUDIT_ARCH_64BIT;

 #endif
 #if defined(__LITTLE_ENDIAN)
 #endif
 #if defined(__LITTLE_ENDIAN)

-       arch |=  __AUDIT_ARCH_LE;
+       arch |=  __AUDIT_ARCH_LE;

 #endif
        return arch;
 }
 #endif
        return arch;
 }


@@ -546,7 +546,7 @@ asmlinkage void syscall_trace_enter(struct pt_regs *regs)
        /* The 0x80 provides a way for the tracing parent to distinguish
           between a syscall stop and SIGTRAP delivery */
        ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ?
        /* The 0x80 provides a way for the tracing parent to distinguish
           between a syscall stop and SIGTRAP delivery */
        ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ?

-                                0x80 : 0));
+                                0x80 : 0));

 
        /*
         * this isn't the same as continuing with a signal, but it will do
 
        /*
         * this isn't the same as continuing with a signal, but it will do


@@ -581,7 +581,7 @@ asmlinkage void syscall_trace_leave(struct pt_regs *regs)
        /* The 0x80 provides a way for the tracing parent to distinguish
           between a syscall stop and SIGTRAP delivery */
        ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ?
        /* The 0x80 provides a way for the tracing parent to distinguish
           between a syscall stop and SIGTRAP delivery */
        ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) ?

-                                0x80 : 0));
+                                0x80 : 0));

 
        /*
         * this isn't the same as continuing with a signal, but it will do
 
        /*
         * this isn't the same as continuing with a signal, but it will do

diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index a3b017815eff0bc3e8e918276de132b2fc336f84..9486055ba660319c415b7ec7affdd07b9eff887e 100644 (file)
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -124,7 +124,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
                case FPC_CSR:
                        tmp = child->thread.fpu.fcr31;
                        break;
                case FPC_CSR:
                        tmp = child->thread.fpu.fcr31;
                        break;

-               case FPC_EIR: { /* implementation / version register */
+               case FPC_EIR: { /* implementation / version register */

                        unsigned int flags;
 #ifdef CONFIG_MIPS_MT_SMTC
                        unsigned int irqflags;
                        unsigned int flags;
 #ifdef CONFIG_MIPS_MT_SMTC
                        unsigned int irqflags;

diff --git a/arch/mips/kernel/r2300_fpu.S b/arch/mips/kernel/r2300_fpu.S
index 61c8a0f2a60cdfbe39f4ec720cce23e4c8755456..f31063dbdaebcffe4521be0d04d045c726ba85aa 100644 (file)
--- a/arch/mips/kernel/r2300_fpu.S
+++ b/arch/mips/kernel/r2300_fpu.S
@@ -30,38 +30,38 @@
 LEAF(_save_fp_context)
        li      v0, 0                                   # assume success
        cfc1    t1,fcr31
 LEAF(_save_fp_context)
        li      v0, 0                                   # assume success
        cfc1    t1,fcr31

-       EX(swc1 $f0,(SC_FPREGS+0)(a0))
-       EX(swc1 $f1,(SC_FPREGS+8)(a0))
-       EX(swc1 $f2,(SC_FPREGS+16)(a0))
-       EX(swc1 $f3,(SC_FPREGS+24)(a0))
-       EX(swc1 $f4,(SC_FPREGS+32)(a0))
-       EX(swc1 $f5,(SC_FPREGS+40)(a0))
-       EX(swc1 $f6,(SC_FPREGS+48)(a0))
-       EX(swc1 $f7,(SC_FPREGS+56)(a0))
-       EX(swc1 $f8,(SC_FPREGS+64)(a0))
-       EX(swc1 $f9,(SC_FPREGS+72)(a0))
-       EX(swc1 $f10,(SC_FPREGS+80)(a0))
-       EX(swc1 $f11,(SC_FPREGS+88)(a0))
-       EX(swc1 $f12,(SC_FPREGS+96)(a0))
-       EX(swc1 $f13,(SC_FPREGS+104)(a0))
-       EX(swc1 $f14,(SC_FPREGS+112)(a0))
-       EX(swc1 $f15,(SC_FPREGS+120)(a0))
-       EX(swc1 $f16,(SC_FPREGS+128)(a0))
-       EX(swc1 $f17,(SC_FPREGS+136)(a0))
-       EX(swc1 $f18,(SC_FPREGS+144)(a0))
-       EX(swc1 $f19,(SC_FPREGS+152)(a0))
-       EX(swc1 $f20,(SC_FPREGS+160)(a0))
-       EX(swc1 $f21,(SC_FPREGS+168)(a0))
-       EX(swc1 $f22,(SC_FPREGS+176)(a0))
-       EX(swc1 $f23,(SC_FPREGS+184)(a0))
-       EX(swc1 $f24,(SC_FPREGS+192)(a0))
-       EX(swc1 $f25,(SC_FPREGS+200)(a0))
-       EX(swc1 $f26,(SC_FPREGS+208)(a0))
-       EX(swc1 $f27,(SC_FPREGS+216)(a0))
-       EX(swc1 $f28,(SC_FPREGS+224)(a0))
-       EX(swc1 $f29,(SC_FPREGS+232)(a0))
-       EX(swc1 $f30,(SC_FPREGS+240)(a0))
-       EX(swc1 $f31,(SC_FPREGS+248)(a0))
+       EX(swc1 $f0,(SC_FPREGS+0)(a0))
+       EX(swc1 $f1,(SC_FPREGS+8)(a0))
+       EX(swc1 $f2,(SC_FPREGS+16)(a0))
+       EX(swc1 $f3,(SC_FPREGS+24)(a0))
+       EX(swc1 $f4,(SC_FPREGS+32)(a0))
+       EX(swc1 $f5,(SC_FPREGS+40)(a0))
+       EX(swc1 $f6,(SC_FPREGS+48)(a0))
+       EX(swc1 $f7,(SC_FPREGS+56)(a0))
+       EX(swc1 $f8,(SC_FPREGS+64)(a0))
+       EX(swc1 $f9,(SC_FPREGS+72)(a0))
+       EX(swc1 $f10,(SC_FPREGS+80)(a0))
+       EX(swc1 $f11,(SC_FPREGS+88)(a0))
+       EX(swc1 $f12,(SC_FPREGS+96)(a0))
+       EX(swc1 $f13,(SC_FPREGS+104)(a0))
+       EX(swc1 $f14,(SC_FPREGS+112)(a0))
+       EX(swc1 $f15,(SC_FPREGS+120)(a0))
+       EX(swc1 $f16,(SC_FPREGS+128)(a0))
+       EX(swc1 $f17,(SC_FPREGS+136)(a0))
+       EX(swc1 $f18,(SC_FPREGS+144)(a0))
+       EX(swc1 $f19,(SC_FPREGS+152)(a0))
+       EX(swc1 $f20,(SC_FPREGS+160)(a0))
+       EX(swc1 $f21,(SC_FPREGS+168)(a0))
+       EX(swc1 $f22,(SC_FPREGS+176)(a0))
+       EX(swc1 $f23,(SC_FPREGS+184)(a0))
+       EX(swc1 $f24,(SC_FPREGS+192)(a0))
+       EX(swc1 $f25,(SC_FPREGS+200)(a0))
+       EX(swc1 $f26,(SC_FPREGS+208)(a0))
+       EX(swc1 $f27,(SC_FPREGS+216)(a0))
+       EX(swc1 $f28,(SC_FPREGS+224)(a0))
+       EX(swc1 $f29,(SC_FPREGS+232)(a0))
+       EX(swc1 $f30,(SC_FPREGS+240)(a0))
+       EX(swc1 $f31,(SC_FPREGS+248)(a0))

        EX(sw   t1,(SC_FPC_CSR)(a0))
        cfc1    t0,$0                           # implementation/version
        jr      ra
        EX(sw   t1,(SC_FPC_CSR)(a0))
        cfc1    t0,$0                           # implementation/version
        jr      ra


@@ -82,38 +82,38 @@ LEAF(_save_fp_context)
 LEAF(_restore_fp_context)
        li      v0, 0                                   # assume success
        EX(lw t0,(SC_FPC_CSR)(a0))
 LEAF(_restore_fp_context)
        li      v0, 0                                   # assume success
        EX(lw t0,(SC_FPC_CSR)(a0))

-       EX(lwc1 $f0,(SC_FPREGS+0)(a0))
-       EX(lwc1 $f1,(SC_FPREGS+8)(a0))
-       EX(lwc1 $f2,(SC_FPREGS+16)(a0))
-       EX(lwc1 $f3,(SC_FPREGS+24)(a0))
-       EX(lwc1 $f4,(SC_FPREGS+32)(a0))
-       EX(lwc1 $f5,(SC_FPREGS+40)(a0))
-       EX(lwc1 $f6,(SC_FPREGS+48)(a0))
-       EX(lwc1 $f7,(SC_FPREGS+56)(a0))
-       EX(lwc1 $f8,(SC_FPREGS+64)(a0))
-       EX(lwc1 $f9,(SC_FPREGS+72)(a0))
-       EX(lwc1 $f10,(SC_FPREGS+80)(a0))
-       EX(lwc1 $f11,(SC_FPREGS+88)(a0))
-       EX(lwc1 $f12,(SC_FPREGS+96)(a0))
-       EX(lwc1 $f13,(SC_FPREGS+104)(a0))
-       EX(lwc1 $f14,(SC_FPREGS+112)(a0))
-       EX(lwc1 $f15,(SC_FPREGS+120)(a0))
-       EX(lwc1 $f16,(SC_FPREGS+128)(a0))
-       EX(lwc1 $f17,(SC_FPREGS+136)(a0))
-       EX(lwc1 $f18,(SC_FPREGS+144)(a0))
-       EX(lwc1 $f19,(SC_FPREGS+152)(a0))
-       EX(lwc1 $f20,(SC_FPREGS+160)(a0))
-       EX(lwc1 $f21,(SC_FPREGS+168)(a0))
-       EX(lwc1 $f22,(SC_FPREGS+176)(a0))
-       EX(lwc1 $f23,(SC_FPREGS+184)(a0))
-       EX(lwc1 $f24,(SC_FPREGS+192)(a0))
-       EX(lwc1 $f25,(SC_FPREGS+200)(a0))
-       EX(lwc1 $f26,(SC_FPREGS+208)(a0))
-       EX(lwc1 $f27,(SC_FPREGS+216)(a0))
-       EX(lwc1 $f28,(SC_FPREGS+224)(a0))
-       EX(lwc1 $f29,(SC_FPREGS+232)(a0))
-       EX(lwc1 $f30,(SC_FPREGS+240)(a0))
-       EX(lwc1 $f31,(SC_FPREGS+248)(a0))
+       EX(lwc1 $f0,(SC_FPREGS+0)(a0))
+       EX(lwc1 $f1,(SC_FPREGS+8)(a0))
+       EX(lwc1 $f2,(SC_FPREGS+16)(a0))
+       EX(lwc1 $f3,(SC_FPREGS+24)(a0))
+       EX(lwc1 $f4,(SC_FPREGS+32)(a0))
+       EX(lwc1 $f5,(SC_FPREGS+40)(a0))
+       EX(lwc1 $f6,(SC_FPREGS+48)(a0))
+       EX(lwc1 $f7,(SC_FPREGS+56)(a0))
+       EX(lwc1 $f8,(SC_FPREGS+64)(a0))
+       EX(lwc1 $f9,(SC_FPREGS+72)(a0))
+       EX(lwc1 $f10,(SC_FPREGS+80)(a0))
+       EX(lwc1 $f11,(SC_FPREGS+88)(a0))
+       EX(lwc1 $f12,(SC_FPREGS+96)(a0))
+       EX(lwc1 $f13,(SC_FPREGS+104)(a0))
+       EX(lwc1 $f14,(SC_FPREGS+112)(a0))
+       EX(lwc1 $f15,(SC_FPREGS+120)(a0))
+       EX(lwc1 $f16,(SC_FPREGS+128)(a0))
+       EX(lwc1 $f17,(SC_FPREGS+136)(a0))
+       EX(lwc1 $f18,(SC_FPREGS+144)(a0))
+       EX(lwc1 $f19,(SC_FPREGS+152)(a0))
+       EX(lwc1 $f20,(SC_FPREGS+160)(a0))
+       EX(lwc1 $f21,(SC_FPREGS+168)(a0))
+       EX(lwc1 $f22,(SC_FPREGS+176)(a0))
+       EX(lwc1 $f23,(SC_FPREGS+184)(a0))
+       EX(lwc1 $f24,(SC_FPREGS+192)(a0))
+       EX(lwc1 $f25,(SC_FPREGS+200)(a0))
+       EX(lwc1 $f26,(SC_FPREGS+208)(a0))
+       EX(lwc1 $f27,(SC_FPREGS+216)(a0))
+       EX(lwc1 $f28,(SC_FPREGS+224)(a0))
+       EX(lwc1 $f29,(SC_FPREGS+232)(a0))
+       EX(lwc1 $f30,(SC_FPREGS+240)(a0))
+       EX(lwc1 $f31,(SC_FPREGS+248)(a0))

        jr      ra
         ctc1   t0,fcr31
        END(_restore_fp_context)
        jr      ra
         ctc1   t0,fcr31
        END(_restore_fp_context)

diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S
index 8d32d5a6b460a72b1d9e5b55538febb6e029e70e..5266c6ee2b3581219dd9f4f73be1d9ddb7c1a3e8 100644 (file)
--- a/arch/mips/kernel/r2300_switch.S
+++ b/arch/mips/kernel/r2300_switch.S
@@ -42,7 +42,7 @@
 
 /*
  * task_struct *resume(task_struct *prev, task_struct *next,
 
 /*
  * task_struct *resume(task_struct *prev, task_struct *next,

- *                     struct thread_info *next_ti, int usedfpu)
+ *                    struct thread_info *next_ti, int usedfpu)

  */
 LEAF(resume)
        mfc0    t1, CP0_STATUS
  */
 LEAF(resume)
        mfc0    t1, CP0_STATUS

diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 8decdfacb448c18540e85b8bc516ba39ecba38d9..5e51219990aa03d5617459c818b96748b787a510 100644 (file)
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -40,7 +40,7 @@
 
 /*
  * task_struct *resume(task_struct *prev, task_struct *next,
 
 /*
  * task_struct *resume(task_struct *prev, task_struct *next,

- *                     struct thread_info *next_ti, int usedfpu)
+ *                    struct thread_info *next_ti, int usedfpu)

  */
        .align  5
        LEAF(resume)
  */
        .align  5
        LEAF(resume)


@@ -53,7 +53,7 @@
         * check if we need to save FPU registers
         */
 
         * check if we need to save FPU registers
         */
 

-       beqz    a3, 1f
+       beqz    a3, 1f

 
        PTR_L   t3, TASK_THREAD_INFO(a0)
        /*
 
        PTR_L   t3, TASK_THREAD_INFO(a0)
        /*

diff --git a/arch/mips/kernel/relocate_kernel.S b/arch/mips/kernel/relocate_kernel.S
index 804ebb2c34a6c9cd556acf3e0048f974641eb32f..43d2d78d3287dfbfa52ad7fb1a52f6571d9deaa3 100644 (file)
--- a/arch/mips/kernel/relocate_kernel.S
+++ b/arch/mips/kernel/relocate_kernel.S
@@ -33,7 +33,7 @@ process_entry:
        b               process_entry
 
 1:
        b               process_entry
 
 1:

-       /* indirection page, update s0  */
+       /* indirection page, update s0  */

        and             s3, s2, 0x2
        beq             s3, zero, 1f
        and             s0, s2, ~0x2
        and             s3, s2, 0x2
        beq             s3, zero, 1f
        and             s0, s2, ~0x2


@@ -69,7 +69,7 @@ done:
           of kexec_flag.  */
 
        bal             1f
           of kexec_flag.  */
 
        bal             1f

- 1:    move            t1,ra;
+ 1:    move            t1,ra;

        PTR_LA          t2,1b
        PTR_LA          t0,kexec_flag
        PTR_SUB         t0,t0,t2;
        PTR_LA          t2,1b
        PTR_LA          t0,kexec_flag
        PTR_SUB         t0,t0,t2;


@@ -158,10 +158,10 @@ arg3:     PTR             0x0
  */
 secondary_kexec_args:
        EXPORT(secondary_kexec_args)
  */
 secondary_kexec_args:
        EXPORT(secondary_kexec_args)

-s_arg0:        PTR             0x0
-s_arg1:        PTR             0x0
-s_arg2:        PTR             0x0
-s_arg3:        PTR             0x0
+s_arg0: PTR            0x0
+s_arg1: PTR            0x0
+s_arg2: PTR            0x0
+s_arg3: PTR            0x0

        .size   secondary_kexec_args,PTRSIZE*4
 kexec_flag:
        LONG            0x1
        .size   secondary_kexec_args,PTRSIZE*4
 kexec_flag:
        LONG            0x1

diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c
index b8c18dcdd2c439999f981ee8edff808b8a06c0f5..ce72bfff5e29298c5c065bb59f0473295054443b 100644 (file)
--- a/arch/mips/kernel/rtlx.c
+++ b/arch/mips/kernel/rtlx.c
@@ -252,12 +252,12 @@ int rtlx_release(int index)
 
 unsigned int rtlx_read_poll(int index, int can_sleep)
 {
 
 unsigned int rtlx_read_poll(int index, int can_sleep)
 {

-       struct rtlx_channel *chan;
+       struct rtlx_channel *chan;

 
 

-       if (rtlx == NULL)
-               return 0;
+       if (rtlx == NULL)
+               return 0;

 
 

-       chan = &rtlx->channel[index];
+       chan = &rtlx->channel[index];

 
        /* data available to read? */
        if (chan->lx_read == chan->lx_write) {
 
        /* data available to read? */
        if (chan->lx_read == chan->lx_write) {


@@ -451,8 +451,8 @@ static ssize_t file_write(struct file *file, const char __user * buffer,
                        return -EAGAIN;
 
                __wait_event_interruptible(channel_wqs[minor].rt_queue,
                        return -EAGAIN;
 
                __wait_event_interruptible(channel_wqs[minor].rt_queue,

-                                          rtlx_write_poll(minor),
-                                          ret);
+                                          rtlx_write_poll(minor),
+                                          ret);

                if (ret)
                        return ret;
        }
                if (ret)
                        return ret;
        }


@@ -462,11 +462,11 @@ static ssize_t file_write(struct file *file, const char __user * buffer,
 
 static const struct file_operations rtlx_fops = {
        .owner =   THIS_MODULE,
 
 static const struct file_operations rtlx_fops = {
        .owner =   THIS_MODULE,

-       .open =    file_open,
+       .open =    file_open,

        .release = file_release,
        .write =   file_write,
        .release = file_release,
        .write =   file_write,

-       .read =    file_read,
-       .poll =    file_poll,
+       .read =    file_read,
+       .poll =    file_poll,

        .llseek =  noop_llseek,
 };
 
        .llseek =  noop_llseek,
 };
 

diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index d20a4bc9ed05c90191f82a120eb2648d75e2f846..988bc06ff96e1ba4eb950f553da56cf1505039ce 100644 (file)
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -24,7 +24,7 @@
 /* Highest syscall used of any syscall flavour */
 #define MAX_SYSCALL_NO __NR_O32_Linux + __NR_O32_Linux_syscalls
 
 /* Highest syscall used of any syscall flavour */
 #define MAX_SYSCALL_NO __NR_O32_Linux + __NR_O32_Linux_syscalls
 

-       .align  5
+       .align  5

 NESTED(handle_sys, PT_SIZE, sp)
        .set    noat
        SAVE_SOME
 NESTED(handle_sys, PT_SIZE, sp)
        .set    noat
        SAVE_SOME


@@ -54,7 +54,7 @@ stack_done:
        lw      t0, TI_FLAGS($28)       # syscall tracing enabled?
        li      t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT
        and     t0, t1
        lw      t0, TI_FLAGS($28)       # syscall tracing enabled?
        li      t1, _TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT
        and     t0, t1

-       bnez    t0, syscall_trace_entry # -> yes
+       bnez    t0, syscall_trace_entry # -> yes

 
        jalr    t2                      # Do The Real Thing (TM)
 
 
        jalr    t2                      # Do The Real Thing (TM)
 


@@ -126,8 +126,8 @@ stackargs:
        la      t1, 5f                  # load up to 3 arguments
        subu    t1, t3
 1:     lw      t5, 16(t0)              # argument #5 from usp
        la      t1, 5f                  # load up to 3 arguments
        subu    t1, t3
 1:     lw      t5, 16(t0)              # argument #5 from usp

-       .set    push
-       .set    noreorder
+       .set    push
+       .set    noreorder

        .set    nomacro
        jr      t1
         addiu  t1, 6f - 5f
        .set    nomacro
        jr      t1
         addiu  t1, 6f - 5f


@@ -205,7 +205,7 @@ illegal_syscall:
        jr      t2
        /* Unreached */
 
        jr      t2
        /* Unreached */
 

-einval:        li      v0, -ENOSYS
+einval: li     v0, -ENOSYS

        jr      ra
        END(sys_syscall)
 
        jr      ra
        END(sys_syscall)
 


@@ -354,7 +354,7 @@ einval:     li      v0, -ENOSYS
        sys     sys_ni_syscall          0       /* was create_module */
        sys     sys_init_module         5
        sys     sys_delete_module       1
        sys     sys_ni_syscall          0       /* was create_module */
        sys     sys_init_module         5
        sys     sys_delete_module       1

-       sys     sys_ni_syscall          0       /* 4130 was get_kernel_syms */
+       sys     sys_ni_syscall          0       /* 4130 was get_kernel_syms */

        sys     sys_quotactl            4
        sys     sys_getpgid             1
        sys     sys_fchdir              1
        sys     sys_quotactl            4
        sys     sys_getpgid             1
        sys     sys_fchdir              1


@@ -589,7 +589,7 @@ einval:     li      v0, -ENOSYS
        /* We pre-compute the number of _instruction_ bytes needed to
           load or store the arguments 6-8. Negative values are ignored. */
 
        /* We pre-compute the number of _instruction_ bytes needed to
           load or store the arguments 6-8. Negative values are ignored. */
 

-       .macro  sys function, nargs
+       .macro  sys function, nargs

        PTR     \function
        LONG    (\nargs << 2) - (5 << 2)
        .endm
        PTR     \function
        LONG    (\nargs << 2) - (5 << 2)
        .endm

diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index b64f642da073f7f7d48ab9a1d54a8f2e749032db..4c356b0093cf9d200e5947ae8bbdb8ca48ada6cf 100644 (file)
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -25,7 +25,7 @@
 #define handle_sys64 handle_sys
 #endif
 
 #define handle_sys64 handle_sys
 #endif
 

-       .align  5
+       .align  5

 NESTED(handle_sys64, PT_SIZE, sp)
 #if !defined(CONFIG_MIPS32_O32) && !defined(CONFIG_MIPS32_N32)
        /*
 NESTED(handle_sys64, PT_SIZE, sp)
 #if !defined(CONFIG_MIPS32_O32) && !defined(CONFIG_MIPS32_N32)
        /*


@@ -40,7 +40,7 @@ NESTED(handle_sys64, PT_SIZE, sp)
 #endif
 
        dsubu   t0, v0, __NR_64_Linux   # check syscall number
 #endif
 
        dsubu   t0, v0, __NR_64_Linux   # check syscall number

-       sltiu   t0, t0, __NR_64_Linux_syscalls + 1
+       sltiu   t0, t0, __NR_64_Linux_syscalls + 1

 #if !defined(CONFIG_MIPS32_O32) && !defined(CONFIG_MIPS32_N32)
        ld      t1, PT_EPC(sp)          # skip syscall on return
        daddiu  t1, 4                   # skip to next instruction
 #if !defined(CONFIG_MIPS32_O32) && !defined(CONFIG_MIPS32_N32)
        ld      t1, PT_EPC(sp)          # skip syscall on return
        daddiu  t1, 4                   # skip to next instruction


@@ -290,7 +290,7 @@ sys_call_table:
        PTR     sys_quotactl
        PTR     sys_ni_syscall                  /* was nfsservctl */
        PTR     sys_ni_syscall                  /* res. for getpmsg */
        PTR     sys_quotactl
        PTR     sys_ni_syscall                  /* was nfsservctl */
        PTR     sys_ni_syscall                  /* res. for getpmsg */

-       PTR     sys_ni_syscall                  /* 5175  for putpmsg */
+       PTR     sys_ni_syscall                  /* 5175  for putpmsg */

        PTR     sys_ni_syscall                  /* res. for afs_syscall */
        PTR     sys_ni_syscall                  /* res. for security */
        PTR     sys_gettid
        PTR     sys_ni_syscall                  /* res. for afs_syscall */
        PTR     sys_ni_syscall                  /* res. for security */
        PTR     sys_gettid

diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index c29ac197f44694821b3a411954a7d6861e0ba33c..30ef88b989af7c2eeec29bab073755760fc413e3 100644 (file)
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -22,7 +22,7 @@
 #define handle_sysn32 handle_sys
 #endif
 
 #define handle_sysn32 handle_sys
 #endif
 

-       .align  5
+       .align  5

 NESTED(handle_sysn32, PT_SIZE, sp)
 #ifndef CONFIG_MIPS32_O32
        .set    noat
 NESTED(handle_sysn32, PT_SIZE, sp)
 #ifndef CONFIG_MIPS32_O32
        .set    noat


@@ -33,7 +33,7 @@ NESTED(handle_sysn32, PT_SIZE, sp)
 #endif
 
        dsubu   t0, v0, __NR_N32_Linux  # check syscall number
 #endif
 
        dsubu   t0, v0, __NR_N32_Linux  # check syscall number

-       sltiu   t0, t0, __NR_N32_Linux_syscalls + 1
+       sltiu   t0, t0, __NR_N32_Linux_syscalls + 1

 
 #ifndef CONFIG_MIPS32_O32
        ld      t1, PT_EPC(sp)          # skip syscall on return
 
 #ifndef CONFIG_MIPS32_O32
        ld      t1, PT_EPC(sp)          # skip syscall on return


@@ -279,7 +279,7 @@ EXPORT(sysn32_call_table)
        PTR     sys_quotactl
        PTR     sys_ni_syscall                  /* was nfsservctl */
        PTR     sys_ni_syscall                  /* res. for getpmsg */
        PTR     sys_quotactl
        PTR     sys_ni_syscall                  /* was nfsservctl */
        PTR     sys_ni_syscall                  /* res. for getpmsg */

-       PTR     sys_ni_syscall                  /* 6175  for putpmsg */
+       PTR     sys_ni_syscall                  /* 6175  for putpmsg */

        PTR     sys_ni_syscall                  /* res. for afs_syscall */
        PTR     sys_ni_syscall                  /* res. for security */
        PTR     sys_gettid
        PTR     sys_ni_syscall                  /* res. for afs_syscall */
        PTR     sys_ni_syscall                  /* res. for security */
        PTR     sys_gettid


@@ -402,8 +402,8 @@ EXPORT(sysn32_call_table)
        PTR     compat_sys_rt_tgsigqueueinfo    /* 6295 */
        PTR     sys_perf_event_open
        PTR     sys_accept4
        PTR     compat_sys_rt_tgsigqueueinfo    /* 6295 */
        PTR     sys_perf_event_open
        PTR     sys_accept4

-       PTR     compat_sys_recvmmsg
-       PTR     sys_getdents64
+       PTR     compat_sys_recvmmsg
+       PTR     sys_getdents64

        PTR     sys_fanotify_init               /* 6300 */
        PTR     sys_fanotify_mark
        PTR     sys_prlimit64
        PTR     sys_fanotify_init               /* 6300 */
        PTR     sys_fanotify_mark
        PTR     sys_prlimit64

diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index cf3e75e466506bc6b73e371818712580bb9d7918..42e789562db4af0725d875a3923882f90d6ecdc0 100644 (file)
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -10,7 +10,7 @@
  *
  * Hairy, the userspace application uses a different argument passing
  * convention than the kernel, so we have to translate things from o32
  *
  * Hairy, the userspace application uses a different argument passing
  * convention than the kernel, so we have to translate things from o32

- * to ABI64 calling convention.  64-bit syscalls are also processed
+ * to ABI64 calling convention.         64-bit syscalls are also processed

  * here for now.
  */
 #include <linux/errno.h>
  * here for now.
  */
 #include <linux/errno.h>


@@ -24,7 +24,7 @@
 #include <asm/unistd.h>
 #include <asm/sysmips.h>
 
 #include <asm/unistd.h>
 #include <asm/sysmips.h>
 

-       .align  5
+       .align  5

 NESTED(handle_sys, PT_SIZE, sp)
        .set    noat
        SAVE_SOME
 NESTED(handle_sys, PT_SIZE, sp)
        .set    noat
        SAVE_SOME


@@ -185,7 +185,7 @@ LEAF(sys32_syscall)
        jr      t2
        /* Unreached */
 
        jr      t2
        /* Unreached */
 

-einval:        li      v0, -ENOSYS
+einval: li     v0, -ENOSYS

        jr      ra
        END(sys32_syscall)
 
        jr      ra
        END(sys32_syscall)
 


@@ -329,7 +329,7 @@ sys_call_table:
        PTR     sys_bdflush
        PTR     sys_sysfs                       /* 4135 */
        PTR     sys_32_personality
        PTR     sys_bdflush
        PTR     sys_sysfs                       /* 4135 */
        PTR     sys_32_personality

-       PTR     sys_ni_syscall                  /* for afs_syscall */
+       PTR     sys_ni_syscall                  /* for afs_syscall */

        PTR     sys_setfsuid
        PTR     sys_setfsgid
        PTR     sys_32_llseek                   /* 4140 */
        PTR     sys_setfsuid
        PTR     sys_setfsgid
        PTR     sys_32_llseek                   /* 4140 */


@@ -352,12 +352,12 @@ sys_call_table:
        PTR     sys_munlockall
        PTR     sys_sched_setparam
        PTR     sys_sched_getparam
        PTR     sys_munlockall
        PTR     sys_sched_setparam
        PTR     sys_sched_getparam

-       PTR     sys_sched_setscheduler          /* 4160 */
+       PTR     sys_sched_setscheduler          /* 4160 */

        PTR     sys_sched_getscheduler
        PTR     sys_sched_yield
        PTR     sys_sched_get_priority_max
        PTR     sys_sched_get_priority_min
        PTR     sys_sched_getscheduler
        PTR     sys_sched_yield
        PTR     sys_sched_get_priority_max
        PTR     sys_sched_get_priority_min

-       PTR     sys_32_sched_rr_get_interval    /* 4165 */
+       PTR     sys_32_sched_rr_get_interval    /* 4165 */

        PTR     compat_sys_nanosleep
        PTR     sys_mremap
        PTR     sys_accept
        PTR     compat_sys_nanosleep
        PTR     sys_mremap
        PTR     sys_accept


@@ -387,7 +387,7 @@ sys_call_table:
        PTR     sys_prctl
        PTR     sys32_rt_sigreturn
        PTR     sys_32_rt_sigaction
        PTR     sys_prctl
        PTR     sys32_rt_sigreturn
        PTR     sys_32_rt_sigaction

-       PTR     sys_32_rt_sigprocmask           /* 4195 */
+       PTR     sys_32_rt_sigprocmask           /* 4195 */

        PTR     sys_32_rt_sigpending
        PTR     compat_sys_rt_sigtimedwait
        PTR     sys_32_rt_sigqueueinfo
        PTR     sys_32_rt_sigpending
        PTR     compat_sys_rt_sigtimedwait
        PTR     sys_32_rt_sigqueueinfo

diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 8c41187801ce34d217b953ce7f4a94728fe050bb..653197e151d525e1f28d264906299bbc90df8c59 100644 (file)
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -8,7 +8,7 @@
  * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 01, 02, 03  Ralf Baechle
  * Copyright (C) 1996 Stoned Elipot
  * Copyright (C) 1999 Silicon Graphics, Inc.
  * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 01, 02, 03  Ralf Baechle
  * Copyright (C) 1996 Stoned Elipot
  * Copyright (C) 1999 Silicon Graphics, Inc.

- * Copyright (C) 2000, 2001, 2002, 2007  Maciej W. Rozycki
+ * Copyright (C) 2000, 2001, 2002, 2007         Maciej W. Rozycki

  */
 #include <linux/init.h>
 #include <linux/ioport.h>
  */
 #include <linux/init.h>
 #include <linux/ioport.h>


@@ -449,7 +449,7 @@ static void __init bootmem_init(void)
  * At this stage the bootmem allocator is ready to use.
  *
  * NOTE: historically plat_mem_setup did the entire platform initialization.
  * At this stage the bootmem allocator is ready to use.
  *
  * NOTE: historically plat_mem_setup did the entire platform initialization.

- *       This was rather impractical because it meant plat_mem_setup had to
+ *      This was rather impractical because it meant plat_mem_setup had to

  * get away without any kind of memory allocator.  To keep old code from
  * breaking plat_setup was just renamed to plat_setup and a second platform
  * initialization hook for anything else was introduced.
  * get away without any kind of memory allocator.  To keep old code from
  * breaking plat_setup was just renamed to plat_setup and a second platform
  * initialization hook for anything else was introduced.


@@ -469,7 +469,7 @@ static int __init early_parse_mem(char *p)
        if (usermem == 0) {
                boot_mem_map.nr_map = 0;
                usermem = 1;
        if (usermem == 0) {
                boot_mem_map.nr_map = 0;
                usermem = 1;

-       }
+       }

        start = 0;
        size = memparse(p, &p);
        if (*p == '@')
        start = 0;
        size = memparse(p, &p);
        if (*p == '@')


@@ -571,7 +571,7 @@ static void __init mips_parse_crashkernel(void)
                return;
 
        crashk_res.start = crash_base;
                return;
 
        crashk_res.start = crash_base;

-       crashk_res.end   = crash_base + crash_size - 1;
+       crashk_res.end   = crash_base + crash_size - 1;

 }
 
 static void __init request_crashkernel(struct resource *res)
 }
 
 static void __init request_crashkernel(struct resource *res)


@@ -585,7 +585,7 @@ static void __init request_crashkernel(struct resource *res)
                                crashk_res.start + 1) >> 20),
                        (unsigned long)(crashk_res.start  >> 20));
 }
                                crashk_res.start + 1) >> 20),
                        (unsigned long)(crashk_res.start  >> 20));
 }

-#else /* !defined(CONFIG_KEXEC)  */
+#else /* !defined(CONFIG_KEXEC)         */

 static void __init mips_parse_crashkernel(void)
 {
 }
 static void __init mips_parse_crashkernel(void)
 {
 }

diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index b6aa77035019bc4913468fbf551f21ef9e9898aa..0f57e06b7fdd9c8aaa34dfd7febdad763e8b9655 100644 (file)
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -445,7 +445,7 @@ give_sigsegv:
 #endif
 
 static int setup_rt_frame(void *sig_return, struct k_sigaction *ka,
 #endif
 
 static int setup_rt_frame(void *sig_return, struct k_sigaction *ka,

-                         struct pt_regs *regs, int signr, sigset_t *set,
+                         struct pt_regs *regs, int signr, sigset_t *set,

                          siginfo_t *info)
 {
        struct rt_sigframe __user *frame;
                          siginfo_t *info)
 {
        struct rt_sigframe __user *frame;


@@ -458,15 +458,15 @@ static int setup_rt_frame(void *sig_return, struct k_sigaction *ka,
        /* Create siginfo.  */
        err |= copy_siginfo_to_user(&frame->rs_info, info);
 
        /* Create siginfo.  */
        err |= copy_siginfo_to_user(&frame->rs_info, info);
 

-       /* Create the ucontext.  */
+       /* Create the ucontext.  */

        err |= __put_user(0, &frame->rs_uc.uc_flags);
        err |= __put_user(NULL, &frame->rs_uc.uc_link);
        err |= __put_user((void __user *)current->sas_ss_sp,
        err |= __put_user(0, &frame->rs_uc.uc_flags);
        err |= __put_user(NULL, &frame->rs_uc.uc_link);
        err |= __put_user((void __user *)current->sas_ss_sp,

-                         &frame->rs_uc.uc_stack.ss_sp);
+                         &frame->rs_uc.uc_stack.ss_sp);

        err |= __put_user(sas_ss_flags(regs->regs[29]),
        err |= __put_user(sas_ss_flags(regs->regs[29]),

-                         &frame->rs_uc.uc_stack.ss_flags);
+                         &frame->rs_uc.uc_stack.ss_flags);

        err |= __put_user(current->sas_ss_size,
        err |= __put_user(current->sas_ss_size,

-                         &frame->rs_uc.uc_stack.ss_size);
+                         &frame->rs_uc.uc_stack.ss_size);

        err |= setup_sigcontext(regs, &frame->rs_uc.uc_mcontext);
        err |= __copy_to_user(&frame->rs_uc.uc_sigmask, set, sizeof(*set));
 
        err |= setup_sigcontext(regs, &frame->rs_uc.uc_mcontext);
        err |= __copy_to_user(&frame->rs_uc.uc_sigmask, set, sizeof(*set));
 


@@ -506,7 +506,7 @@ struct mips_abi mips_abi = {
        .setup_frame    = setup_frame,
        .signal_return_offset = offsetof(struct mips_vdso, signal_trampoline),
 #endif
        .setup_frame    = setup_frame,
        .signal_return_offset = offsetof(struct mips_vdso, signal_trampoline),
 #endif

-       .setup_rt_frame = setup_rt_frame,
+       .setup_rt_frame = setup_rt_frame,

        .rt_signal_return_offset =
                offsetof(struct mips_vdso, rt_signal_trampoline),
        .restart        = __NR_restart_syscall
        .rt_signal_return_offset =
                offsetof(struct mips_vdso, rt_signal_trampoline),
        .restart        = __NR_restart_syscall


@@ -538,7 +538,7 @@ static void handle_signal(unsigned long sig, siginfo_t *info,
                        regs->cp0_epc -= 4;
                }
 
                        regs->cp0_epc -= 4;
                }
 

-               regs->regs[0] = 0;              /* Don't deal with this again.  */
+               regs->regs[0] = 0;              /* Don't deal with this again.  */

        }
 
        if (sig_uses_siginfo(ka))
        }
 
        if (sig_uses_siginfo(ka))


@@ -562,7 +562,7 @@ static void do_signal(struct pt_regs *regs)
 
        signr = get_signal_to_deliver(&info, &ka, regs, NULL);
        if (signr > 0) {
 
        signr = get_signal_to_deliver(&info, &ka, regs, NULL);
        if (signr > 0) {

-               /* Whee!  Actually deliver the signal.  */
+               /* Whee!  Actually deliver the signal.  */

                handle_signal(signr, &info, &ka, regs);
                return;
        }
                handle_signal(signr, &info, &ka, regs);
                return;
        }


@@ -583,7 +583,7 @@ static void do_signal(struct pt_regs *regs)
                        regs->cp0_epc -= 4;
                        break;
                }
                        regs->cp0_epc -= 4;
                        break;
                }

-               regs->regs[0] = 0;      /* Don't deal with this again.  */
+               regs->regs[0] = 0;      /* Don't deal with this again.  */

        }
 
        /*
        }
 
        /*

diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index da1b56a39ac77815b4989183fd07821286468dfe..cae0b0e42a53bd7d3ca1ab1bfaa3fa1300bee1cb 100644 (file)
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -48,7 +48,7 @@ extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user
 /*
  * Including <asm/unistd.h> would give use the 64-bit syscall numbers ...
  */
 /*
  * Including <asm/unistd.h> would give use the 64-bit syscall numbers ...
  */

-#define __NR_O32_restart_syscall        4253
+#define __NR_O32_restart_syscall       4253

 
 /* 32-bit compatibility types */
 
 
 /* 32-bit compatibility types */
 


@@ -69,11 +69,11 @@ typedef struct sigaltstack32 {
 } stack32_t;
 
 struct ucontext32 {
 } stack32_t;
 
 struct ucontext32 {

-       u32                 uc_flags;
-       s32                 uc_link;
-       stack32_t           uc_stack;
+       u32                 uc_flags;
+       s32                 uc_link;
+       stack32_t           uc_stack;

        struct sigcontext32 uc_mcontext;
        struct sigcontext32 uc_mcontext;

-       compat_sigset_t     uc_sigmask;   /* mask last for extensibility */
+       compat_sigset_t     uc_sigmask;   /* mask last for extensibility */

 };
 
 struct sigframe32 {
 };
 
 struct sigframe32 {


@@ -338,7 +338,7 @@ SYSCALL_DEFINE3(32_sigaction, long, sig, const struct sigaction32 __user *, act,
                        return -EFAULT;
                err |= __put_user(old_ka.sa.sa_flags, &oact->sa_flags);
                err |= __put_user((u32)(u64)old_ka.sa.sa_handler,
                        return -EFAULT;
                err |= __put_user(old_ka.sa.sa_flags, &oact->sa_flags);
                err |= __put_user((u32)(u64)old_ka.sa.sa_handler,

-                                 &oact->sa_handler);
+                                 &oact->sa_handler);

                err |= __put_user(old_ka.sa.sa_mask.sig[0], oact->sa_mask.sig);
                err |= __put_user(0, &oact->sa_mask.sig[1]);
                err |= __put_user(0, &oact->sa_mask.sig[2]);
                err |= __put_user(old_ka.sa.sa_mask.sig[0], oact->sa_mask.sig);
                err |= __put_user(0, &oact->sa_mask.sig[1]);
                err |= __put_user(0, &oact->sa_mask.sig[2]);


@@ -599,16 +599,16 @@ static int setup_rt_frame_32(void *sig_return, struct k_sigaction *ka,
        /* Convert (siginfo_t -> compat_siginfo_t) and copy to user. */
        err |= copy_siginfo_to_user32(&frame->rs_info, info);
 
        /* Convert (siginfo_t -> compat_siginfo_t) and copy to user. */
        err |= copy_siginfo_to_user32(&frame->rs_info, info);
 

-       /* Create the ucontext.  */
+       /* Create the ucontext.  */

        err |= __put_user(0, &frame->rs_uc.uc_flags);
        err |= __put_user(0, &frame->rs_uc.uc_link);
        sp = (int) (long) current->sas_ss_sp;
        err |= __put_user(sp,
        err |= __put_user(0, &frame->rs_uc.uc_flags);
        err |= __put_user(0, &frame->rs_uc.uc_link);
        sp = (int) (long) current->sas_ss_sp;
        err |= __put_user(sp,

-                         &frame->rs_uc.uc_stack.ss_sp);
+                         &frame->rs_uc.uc_stack.ss_sp);

        err |= __put_user(sas_ss_flags(regs->regs[29]),
        err |= __put_user(sas_ss_flags(regs->regs[29]),

-                         &frame->rs_uc.uc_stack.ss_flags);
+                         &frame->rs_uc.uc_stack.ss_flags);

        err |= __put_user(current->sas_ss_size,
        err |= __put_user(current->sas_ss_size,

-                         &frame->rs_uc.uc_stack.ss_size);
+                         &frame->rs_uc.uc_stack.ss_size);

        err |= setup_sigcontext32(regs, &frame->rs_uc.uc_mcontext);
        err |= __copy_conv_sigset_to_user(&frame->rs_uc.uc_sigmask, set);
 
        err |= setup_sigcontext32(regs, &frame->rs_uc.uc_mcontext);
        err |= __copy_conv_sigset_to_user(&frame->rs_uc.uc_sigmask, set);
 


@@ -650,7 +650,7 @@ struct mips_abi mips_abi_32 = {
        .setup_frame    = setup_frame_32,
        .signal_return_offset =
                offsetof(struct mips_vdso, o32_signal_trampoline),
        .setup_frame    = setup_frame_32,
        .signal_return_offset =
                offsetof(struct mips_vdso, o32_signal_trampoline),

-       .setup_rt_frame = setup_rt_frame_32,
+       .setup_rt_frame = setup_rt_frame_32,

        .rt_signal_return_offset =
                offsetof(struct mips_vdso, o32_rt_signal_trampoline),
        .restart        = __NR_O32_restart_syscall
        .rt_signal_return_offset =
                offsetof(struct mips_vdso, o32_rt_signal_trampoline),
        .restart        = __NR_O32_restart_syscall


@@ -690,7 +690,7 @@ SYSCALL_DEFINE4(32_rt_sigaction, int, sig,
                        return -EFAULT;
 
                err |= __put_user((u32)(u64)old_sa.sa.sa_handler,
                        return -EFAULT;
 
                err |= __put_user((u32)(u64)old_sa.sa.sa_handler,

-                                  &oact->sa_handler);
+                                  &oact->sa_handler);

                err |= __put_user(old_sa.sa.sa_flags, &oact->sa_flags);
                err |= put_sigset(&old_sa.sa.sa_mask, &oact->sa_mask);
                if (err)
                err |= __put_user(old_sa.sa.sa_flags, &oact->sa_flags);
                err |= put_sigset(&old_sa.sa.sa_mask, &oact->sa_mask);
                if (err)

diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c
index 3574c145511be486b0feb82177ced3c80679d180..7246e33721aef13c6021ce1974cf49f2284aa61f 100644 (file)
--- a/arch/mips/kernel/signal_n32.c
+++ b/arch/mips/kernel/signal_n32.c
@@ -59,11 +59,11 @@ typedef struct sigaltstack32 {
 } stack32_t;
 
 struct ucontextn32 {
 } stack32_t;
 
 struct ucontextn32 {

-       u32                 uc_flags;
-       s32                 uc_link;
-       stack32_t           uc_stack;
+       u32                 uc_flags;
+       s32                 uc_link;
+       stack32_t           uc_stack;

        struct sigcontext   uc_mcontext;
        struct sigcontext   uc_mcontext;

-       compat_sigset_t     uc_sigmask;   /* mask last for extensibility */
+       compat_sigset_t     uc_sigmask;   /* mask last for extensibility */

 };
 
 struct rt_sigframe_n32 {
 };
 
 struct rt_sigframe_n32 {


@@ -162,16 +162,16 @@ static int setup_rt_frame_n32(void *sig_return, struct k_sigaction *ka,
        /* Create siginfo.  */
        err |= copy_siginfo_to_user32(&frame->rs_info, info);
 
        /* Create siginfo.  */
        err |= copy_siginfo_to_user32(&frame->rs_info, info);
 

-       /* Create the ucontext.  */
+       /* Create the ucontext.  */

        err |= __put_user(0, &frame->rs_uc.uc_flags);
        err |= __put_user(0, &frame->rs_uc.uc_link);
        sp = (int) (long) current->sas_ss_sp;
        err |= __put_user(sp,
        err |= __put_user(0, &frame->rs_uc.uc_flags);
        err |= __put_user(0, &frame->rs_uc.uc_link);
        sp = (int) (long) current->sas_ss_sp;
        err |= __put_user(sp,

-                         &frame->rs_uc.uc_stack.ss_sp);
+                         &frame->rs_uc.uc_stack.ss_sp);

        err |= __put_user(sas_ss_flags(regs->regs[29]),
        err |= __put_user(sas_ss_flags(regs->regs[29]),

-                         &frame->rs_uc.uc_stack.ss_flags);
+                         &frame->rs_uc.uc_stack.ss_flags);

        err |= __put_user(current->sas_ss_size,
        err |= __put_user(current->sas_ss_size,

-                         &frame->rs_uc.uc_stack.ss_size);
+                         &frame->rs_uc.uc_stack.ss_size);

        err |= setup_sigcontext(regs, &frame->rs_uc.uc_mcontext);
        err |= __copy_conv_sigset_to_user(&frame->rs_uc.uc_sigmask, set);
 
        err |= setup_sigcontext(regs, &frame->rs_uc.uc_mcontext);
        err |= __copy_conv_sigset_to_user(&frame->rs_uc.uc_sigmask, set);
 


@@ -207,7 +207,7 @@ give_sigsegv:
 }
 
 struct mips_abi mips_abi_n32 = {
 }
 
 struct mips_abi mips_abi_n32 = {

-       .setup_rt_frame = setup_rt_frame_n32,
+       .setup_rt_frame = setup_rt_frame_n32,

        .rt_signal_return_offset =
                offsetof(struct mips_vdso, n32_rt_signal_trampoline),
        .restart        = __NR_N32_restart_syscall
        .rt_signal_return_offset =
                offsetof(struct mips_vdso, n32_rt_signal_trampoline),
        .restart        = __NR_N32_restart_syscall

diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c
index 06cd0c610f4475a3cfc03f6907e00542117fe2ba..c2e5d74739b49fa6dcd8be06dd6e51b7b71864e4 100644 (file)
--- a/arch/mips/kernel/smp-cmp.c
+++ b/arch/mips/kernel/smp-cmp.c
@@ -172,7 +172,7 @@ void __init cmp_smp_setup(void)
                if (amon_cpu_avail(i)) {
                        set_cpu_possible(i, true);
                        __cpu_number_map[i]     = ++ncpu;
                if (amon_cpu_avail(i)) {
                        set_cpu_possible(i, true);
                        __cpu_number_map[i]     = ++ncpu;

-                       __cpu_logical_map[ncpu] = i;
+                       __cpu_logical_map[ncpu] = i;

                }
        }
 
                }
        }
 

diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 2defa2bbdaa79e3a1af2e58c0a96237526314240..bfede063d96a52e3dd8f12aedf67f15468d7c3aa 100644 (file)
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -71,7 +71,7 @@ static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
                /* Record this as available CPU */
                set_cpu_possible(tc, true);
                __cpu_number_map[tc]    = ++ncpu;
                /* Record this as available CPU */
                set_cpu_possible(tc, true);
                __cpu_number_map[tc]    = ++ncpu;

-               __cpu_logical_map[ncpu] = tc;
+               __cpu_logical_map[ncpu] = tc;

        }
 
        /* Disable multi-threading with TC's */
        }
 
        /* Disable multi-threading with TC's */


@@ -215,7 +215,7 @@ static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle)
        write_tc_gpr_gp((unsigned long)gp);
 
        flush_icache_range((unsigned long)gp,
        write_tc_gpr_gp((unsigned long)gp);
 
        flush_icache_range((unsigned long)gp,

-                          (unsigned long)(gp + sizeof(struct thread_info)));
+                          (unsigned long)(gp + sizeof(struct thread_info)));

 
        /* finally out of configuration and into chaos */
        clear_c0_mvpcontrol(MVPCONTROL_VPC);
 
        /* finally out of configuration and into chaos */
        clear_c0_mvpcontrol(MVPCONTROL_VPC);

diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S
index 20938a4cb52d64991e7aa1f695a5aba7c80caac3..76016ac0a9c8818960e61f055ac47e4d55a9bdf2 100644 (file)
--- a/arch/mips/kernel/smtc-asm.S
+++ b/arch/mips/kernel/smtc-asm.S
@@ -65,7 +65,7 @@ FEXPORT(__smtc_ipi_vector)
 1:
        /*
         * The IPI sender has put some information on the anticipated
 1:
        /*
         * The IPI sender has put some information on the anticipated

-        * kernel stack frame.  If we were in user mode, this will be
+        * kernel stack frame.  If we were in user mode, this will be

         * built above the saved kernel SP.  If we were already in the
         * kernel, it will be built above the current CPU SP.
         *
         * built above the saved kernel SP.  If we were already in the
         * kernel, it will be built above the current CPU SP.
         *

diff --git a/arch/mips/kernel/smtc-proc.c b/arch/mips/kernel/smtc-proc.c
index 145771c0ed7a22be5f72584bfa0675f1c1078f70..aee7c8177b5df4a2e00cd24efad837f02a723921 100644 (file)
--- a/arch/mips/kernel/smtc-proc.c
+++ b/arch/mips/kernel/smtc-proc.c
@@ -35,7 +35,7 @@ static struct proc_dir_entry *smtc_stats;
 atomic_t smtc_fpu_recoveries;
 
 static int proc_read_smtc(char *page, char **start, off_t off,
 atomic_t smtc_fpu_recoveries;
 
 static int proc_read_smtc(char *page, char **start, off_t off,

-                          int count, int *eof, void *data)
+                         int count, int *eof, void *data)

 {
        int totalen = 0;
        int len;
 {
        int totalen = 0;
        int len;


@@ -68,7 +68,7 @@ static int proc_read_smtc(char *page, char **start, off_t off,
                page += len;
        }
        len = sprintf(page, "%d Recoveries of \"stolen\" FPU\n",
                page += len;
        }
        len = sprintf(page, "%d Recoveries of \"stolen\" FPU\n",

-                     atomic_read(&smtc_fpu_recoveries));
+                     atomic_read(&smtc_fpu_recoveries));

        totalen += len;
        page += len;
 
        totalen += len;
        page += len;
 


@@ -87,5 +87,5 @@ void init_smtc_stats(void)
        atomic_set(&smtc_fpu_recoveries, 0);
 
        smtc_stats = create_proc_read_entry("smtc", 0444, NULL,
        atomic_set(&smtc_fpu_recoveries, 0);
 
        smtc_stats = create_proc_read_entry("smtc", 0444, NULL,

-                                           proc_read_smtc, NULL);
+                                           proc_read_smtc, NULL);

 }
 }

diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 1d47843d3cc0211d3259930ef48596316afc2cfc..1c152a93dc7baee9a9620ca69a229f65feedcee2 100644 (file)
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -235,7 +235,7 @@ static void smtc_configure_tlb(void)
                    mips_ihb();
                    /* No need to un-Halt - that happens later anyway */
                    for (i=0; i < vpes; i++) {
                    mips_ihb();
                    /* No need to un-Halt - that happens later anyway */
                    for (i=0; i < vpes; i++) {

-                       write_tc_c0_tcbind(i);
+                       write_tc_c0_tcbind(i);

                        /*
                         * To be 100% sure we're really getting the right
                         * information, we exit the configuration state
                        /*
                         * To be 100% sure we're really getting the right
                         * information, we exit the configuration state


@@ -286,7 +286,7 @@ static void smtc_configure_tlb(void)
 
 /*
  * Incrementally build the CPU map out of constituent MIPS MT cores,
 
 /*
  * Incrementally build the CPU map out of constituent MIPS MT cores,

- * using the specified available VPEs and TCs.  Plaform code needs
+ * using the specified available VPEs and TCs. Plaform code needs

  * to ensure that each MIPS MT core invokes this routine on reset,
  * one at a time(!).
  *
  * to ensure that each MIPS MT core invokes this routine on reset,
  * one at a time(!).
  *


@@ -348,7 +348,7 @@ static void smtc_tc_setup(int vpe, int tc, int cpu)
        {
                /*
                 * FIXME: Multi-core SMTC hasn't been tested and the
        {
                /*
                 * FIXME: Multi-core SMTC hasn't been tested and the

-                *        maximum number of VPEs may change.
+                *        maximum number of VPEs may change.

                 */
                cp1contexts[0] = smtc_nconf1[0] - 1;
                cp1contexts[1] = smtc_nconf1[1];
                 */
                cp1contexts[0] = smtc_nconf1[0] - 1;
                cp1contexts[1] = smtc_nconf1[1];


@@ -761,9 +761,9 @@ void smtc_forward_irq(struct irq_data *d)
         * mask has been purged of bits corresponding to nonexistent and
         * offline "CPUs", and to TCs bound to VPEs other than the VPE
         * connected to the physical interrupt input for the interrupt
         * mask has been purged of bits corresponding to nonexistent and
         * offline "CPUs", and to TCs bound to VPEs other than the VPE
         * connected to the physical interrupt input for the interrupt

-        * in question.  Otherwise we have a nasty problem with interrupt
+        * in question.  Otherwise we have a nasty problem with interrupt

         * mask management.  This is best handled in non-performance-critical
         * mask management.  This is best handled in non-performance-critical

-        * platform IRQ affinity setting code,  to minimize interrupt-time
+        * platform IRQ affinity setting code,  to minimize interrupt-time

         * checks.
         */
 
         * checks.
         */
 


@@ -899,10 +899,10 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
                mips_ihb();
 
                /*
                mips_ihb();
 
                /*

-                * Inspect TCStatus - if IXMT is set, we have to queue
+                * Inspect TCStatus - if IXMT is set, we have to queue

                 * a message. Otherwise, we set up the "interrupt"
                 * of the other TC
                 * a message. Otherwise, we set up the "interrupt"
                 * of the other TC

-                */
+                */

                tcstatus = read_tc_c0_tcstatus();
 
                if ((tcstatus & TCSTATUS_IXMT) != 0) {
                tcstatus = read_tc_c0_tcstatus();
 
                if ((tcstatus & TCSTATUS_IXMT) != 0) {


@@ -964,7 +964,7 @@ static void post_direct_ipi(int cpu, struct smtc_ipi *pipi)
         * CU bit of Status is indicator that TC was
         * already running on a kernel stack...
         */
         * CU bit of Status is indicator that TC was
         * already running on a kernel stack...
         */

-       if (tcstatus & ST0_CU0)  {
+       if (tcstatus & ST0_CU0)  {

                /* Note that this "- 1" is pointer arithmetic */
                kstack = ((struct pt_regs *)read_tc_gpr_sp()) - 1;
        } else {
                /* Note that this "- 1" is pointer arithmetic */
                kstack = ((struct pt_regs *)read_tc_gpr_sp()) - 1;
        } else {


@@ -1288,7 +1288,7 @@ void smtc_idle_loop_hook(void)
                        for (tc = 0; tc < hook_ntcs; tc++) {
                                tcnoprog[tc] = 0;
                                clock_hang_reported[tc] = 0;
                        for (tc = 0; tc < hook_ntcs; tc++) {
                                tcnoprog[tc] = 0;
                                clock_hang_reported[tc] = 0;

-                       }
+                       }

                        for (vpe = 0; vpe < 2; vpe++)
                                for (im = 0; im < 8; im++)
                                        imstuckcount[vpe][im] = 0;
                        for (vpe = 0; vpe < 2; vpe++)
                                for (im = 0; im < 8; im++)
                                        imstuckcount[vpe][im] = 0;


@@ -1485,7 +1485,7 @@ static int halt_state_save[NR_CPUS];
 
 /*
  * To really, really be sure that nothing is being done
 
 /*
  * To really, really be sure that nothing is being done

- * by other TCs, halt them all.  This code assumes that
+ * by other TCs, halt them all.         This code assumes that

  * a DVPE has already been done, so while their Halted
  * state is theoretically architecturally unstable, in
  * practice, it's not going to change while we're looking
  * a DVPE has already been done, so while their Halted
  * state is theoretically architecturally unstable, in
  * practice, it's not going to change while we're looking

diff --git a/arch/mips/kernel/sync-r4k.c b/arch/mips/kernel/sync-r4k.c
index 7f1eca3858def1845dc98dd1264206be19159b01..1ff43d5ac2c4e56bd6b4cda1be5d442131691b9d 100644 (file)
--- a/arch/mips/kernel/sync-r4k.c
+++ b/arch/mips/kernel/sync-r4k.c
@@ -25,7 +25,7 @@ static atomic_t __cpuinitdata count_count_start = ATOMIC_INIT(0);
 static atomic_t __cpuinitdata count_count_stop = ATOMIC_INIT(0);
 static atomic_t __cpuinitdata count_reference = ATOMIC_INIT(0);
 
 static atomic_t __cpuinitdata count_count_stop = ATOMIC_INIT(0);
 static atomic_t __cpuinitdata count_reference = ATOMIC_INIT(0);
 

-#define COUNTON        100
+#define COUNTON 100

 #define NR_LOOPS 5
 
 void __cpuinit synchronise_count_master(int cpu)
 #define NR_LOOPS 5
 
 void __cpuinit synchronise_count_master(int cpu)

diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index 107307d583eb73d10151ec2d4ef64ae23d5e2788..d7feee0c27395a142c26bfde7ca48cfd676702b5 100644 (file)
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -41,9 +41,9 @@
 
 /*
  * For historic reasons the pipe(2) syscall on MIPS has an unusual calling
 
 /*
  * For historic reasons the pipe(2) syscall on MIPS has an unusual calling

- * convention.  It returns results in registers $v0 / $v1 which means there
+ * convention. It returns results in registers $v0 / $v1 which means there

  * is no need for it to do verify the validity of a userspace pointer
  * is no need for it to do verify the validity of a userspace pointer

- * argument.  Historically that used to be expensive in Linux.  These days
+ * argument.  Historically that used to be expensive in Linux. These days

  * the performance advantage is negligible.
  */
 asmlinkage int sysm_pipe(nabi_no_regargs volatile struct pt_regs regs)
  * the performance advantage is negligible.
  */
 asmlinkage int sysm_pipe(nabi_no_regargs volatile struct pt_regs regs)


@@ -124,7 +124,7 @@ _sys_clone(nabi_no_regargs struct pt_regs regs)
        child_tidptr = (int __user *) regs.regs[8];
 #endif
        return do_fork(clone_flags, newsp, 0,
        child_tidptr = (int __user *) regs.regs[8];
 #endif
        return do_fork(clone_flags, newsp, 0,

-                      parent_tidptr, child_tidptr);
+                      parent_tidptr, child_tidptr);

 }
 
 SYSCALL_DEFINE1(set_thread_area, unsigned long, addr)
 }
 
 SYSCALL_DEFINE1(set_thread_area, unsigned long, addr)

diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 99d73b72b00b763e537425d6d63d8bdd7c8ccdbb..9d686bf97b0e35a598dfe3c5711553b5148d8329 100644 (file)
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -5,8 +5,8 @@
  *
  * Common time service routines for MIPS machines.
  *
  *
  * Common time service routines for MIPS machines.
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */


@@ -62,8 +62,8 @@ EXPORT_SYMBOL(perf_irq);
  * time_init() - it does the following things.
  *
  * 1) plat_time_init() -
  * time_init() - it does the following things.
  *
  * 1) plat_time_init() -

- *     a) (optional) set up RTC routines,
- *      b) (optional) calibrate and set the mips_hpt_frequency
+ *     a) (optional) set up RTC routines,
+ *     b) (optional) calibrate and set the mips_hpt_frequency

  *         (only needed if you intended to use cpu counter as timer interrupt
  *          source)
  * 2) calculate a couple of cached variables for later usage
  *         (only needed if you intended to use cpu counter as timer interrupt
  *          source)
  * 2) calculate a couple of cached variables for later usage


@@ -75,7 +75,7 @@ unsigned int mips_hpt_frequency;
  * This function exists in order to cause an error due to a duplicate
  * definition if platform code should have its own implementation.  The hook
  * to use instead is plat_time_init.  plat_time_init does not receive the
  * This function exists in order to cause an error due to a duplicate
  * definition if platform code should have its own implementation.  The hook
  * to use instead is plat_time_init.  plat_time_init does not receive the

- * irqaction pointer argument anymore.  This is because any function which
+ * irqaction pointer argument anymore. This is because any function which

  * initializes an interrupt timer now takes care of its own request_irq rsp.
  * setup_irq calls and each clock_event_device should use its own
  * struct irqrequest.
  * initializes an interrupt timer now takes care of its own request_irq rsp.
  * setup_irq calls and each clock_event_device should use its own
  * struct irqrequest.


@@ -93,7 +93,7 @@ static __init int cpu_has_mfc0_count_bug(void)
        case CPU_R4000MC:
                /*
                 * V3.0 is documented as suffering from the mfc0 from count bug.
        case CPU_R4000MC:
                /*
                 * V3.0 is documented as suffering from the mfc0 from count bug.

-                * Afaik this is the last version of the R4000.  Later versions
+                * Afaik this is the last version of the R4000.  Later versions

                 * were marketed as R4400.
                 */
                return 1;
                 * were marketed as R4400.
                 */
                return 1;

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index e3a5f3ddab1abb8ed68c82b437170bc3107b7b06..08c07bdb7e6c50d6abeb25279092b277748eba1a 100644 (file)
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -164,7 +164,7 @@ static void show_stacktrace(struct task_struct *task,
        i = 0;
        while ((unsigned long) sp & (PAGE_SIZE - 1)) {
                if (i && ((i % (64 / field)) == 0))
        i = 0;
        while ((unsigned long) sp & (PAGE_SIZE - 1)) {
                if (i && ((i % (64 / field)) == 0))

-                       printk("\n       ");
+                       printk("\n       ");

                if (i > 39) {
                        printk(" ...");
                        break;
                if (i > 39) {
                        printk(" ...");
                        break;


@@ -279,7 +279,7 @@ static void __show_regs(const struct pt_regs *regs)
        printk("ra    : %0*lx %pS\n", field, regs->regs[31],
               (void *) regs->regs[31]);
 
        printk("ra    : %0*lx %pS\n", field, regs->regs[31],
               (void *) regs->regs[31]);
 

-       printk("Status: %08x    ", (uint32_t) regs->cp0_status);
+       printk("Status: %08x    ", (uint32_t) regs->cp0_status);

 
        if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
                if (regs->cp0_status & ST0_KUO)
 
        if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
                if (regs->cp0_status & ST0_KUO)


@@ -441,7 +441,7 @@ asmlinkage void do_be(struct pt_regs *regs)
        int data = regs->cp0_cause & 4;
        int action = MIPS_BE_FATAL;
 
        int data = regs->cp0_cause & 4;
        int action = MIPS_BE_FATAL;
 

-       /* XXX For now.  Fixme, this searches the wrong table ...  */
+       /* XXX For now.  Fixme, this searches the wrong table ...  */

        if (data && !user_mode(regs))
                fixup = search_dbe_tables(exception_epc(regs));
 
        if (data && !user_mode(regs))
                fixup = search_dbe_tables(exception_epc(regs));
 


@@ -739,7 +739,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
                current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
 
                /* Restore the hardware register state */
                current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
 
                /* Restore the hardware register state */

-               own_fpu(1);     /* Using the FPU again.  */
+               own_fpu(1);     /* Using the FPU again.  */

 
                /* If something went wrong, signal */
                process_fpemu_return(sig, fault_addr);
 
                /* If something went wrong, signal */
                process_fpemu_return(sig, fault_addr);


@@ -966,7 +966,7 @@ int cu2_notifier_call_chain(unsigned long val, void *v)
 }
 
 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
 }
 
 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,

-        void *data)
+       void *data)

 {
        struct pt_regs *regs = data;
 
 {
        struct pt_regs *regs = data;
 


@@ -974,7 +974,7 @@ static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
        default:
                die_if_kernel("Unhandled kernel unaligned access or invalid "
                              "instruction", regs);
        default:
                die_if_kernel("Unhandled kernel unaligned access or invalid "
                              "instruction", regs);

-               /* Fall through  */
+               /* Fall through  */

 
        case CU2_EXCEPTION:
                force_sig(SIGILL, current);
 
        case CU2_EXCEPTION:
                force_sig(SIGILL, current);


@@ -1029,10 +1029,10 @@ asmlinkage void do_cpu(struct pt_regs *regs)
                /*
                 * Old (MIPS I and MIPS II) processors will set this code
                 * for COP1X opcode instructions that replaced the original
                /*
                 * Old (MIPS I and MIPS II) processors will set this code
                 * for COP1X opcode instructions that replaced the original

-                * COP3 space.  We don't limit COP1 space instructions in
+                * COP3 space.  We don't limit COP1 space instructions in

                 * the emulator according to the CPU ISA, so we want to
                 * treat COP1X instructions consistently regardless of which
                 * the emulator according to the CPU ISA, so we want to
                 * treat COP1X instructions consistently regardless of which

-                * code the CPU chose.  Therefore we redirect this trap to
+                * code the CPU chose.  Therefore we redirect this trap to

                 * the FP emulator too.
                 *
                 * Then some newer FPU-less processors use this code
                 * the FP emulator too.
                 *
                 * Then some newer FPU-less processors use this code


@@ -1044,9 +1044,9 @@ asmlinkage void do_cpu(struct pt_regs *regs)
                /* Fall through.  */
 
        case 1:
                /* Fall through.  */
 
        case 1:

-               if (used_math())        /* Using the FPU again.  */
+               if (used_math())        /* Using the FPU again.  */

                        own_fpu(1);
                        own_fpu(1);

-               else {                  /* First time FPU user.  */
+               else {                  /* First time FPU user.  */

                        init_fpu();
                        set_used_math();
                }
                        init_fpu();
                        set_used_math();
                }


@@ -1114,7 +1114,7 @@ asmlinkage void do_mcheck(struct pt_regs *regs)
        show_regs(regs);
 
        if (multi_match) {
        show_regs(regs);
 
        if (multi_match) {

-               printk("Index   : %0x\n", read_c0_index());
+               printk("Index   : %0x\n", read_c0_index());

                printk("Pagemask: %0x\n", read_c0_pagemask());
                printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
                printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
                printk("Pagemask: %0x\n", read_c0_pagemask());
                printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
                printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());


@@ -1181,7 +1181,7 @@ asmlinkage void do_dsp(struct pt_regs *regs)
 asmlinkage void do_reserved(struct pt_regs *regs)
 {
        /*
 asmlinkage void do_reserved(struct pt_regs *regs)
 {
        /*

-        * Game over - no way to handle this if it ever occurs.  Most probably
+        * Game over - no way to handle this if it ever occurs.  Most probably

         * caused by a new unknown cpu type or after another deadly
         * hard/software error.
         */
         * caused by a new unknown cpu type or after another deadly
         * hard/software error.
         */


@@ -1705,7 +1705,7 @@ void __init trap_init(void)
 
 #if defined(CONFIG_KGDB)
        if (kgdb_early_setup)
 
 #if defined(CONFIG_KGDB)
        if (kgdb_early_setup)

-               return; /* Already done */
+               return; /* Already done */

 #endif
 
        if (cpu_has_veic || cpu_has_vint) {
 #endif
 
        if (cpu_has_veic || cpu_has_vint) {


@@ -1799,7 +1799,7 @@ void __init trap_init(void)
                 * The R6000 is the only R-series CPU that features a machine
                 * check exception (similar to the R4000 cache error) and
                 * unaligned ldc1/sdc1 exception.  The handlers have not been
                 * The R6000 is the only R-series CPU that features a machine
                 * check exception (similar to the R4000 cache error) and
                 * unaligned ldc1/sdc1 exception.  The handlers have not been

-                * written yet.  Well, anyway there is no R6000 machine on the
+                * written yet.  Well, anyway there is no R6000 machine on the

                 * current list of targets for Linux/MIPS.
                 * (Duh, crap, there is someone with a triple R6k machine)
                 */
                 * current list of targets for Linux/MIPS.
                 * (Duh, crap, there is someone with a triple R6k machine)
                 */

diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 9c58bdf58f23ba2b64b34dcb09f964e7cf3f95c5..6087a54c86a0dbc5e6e9a167659df9408a1dc3e1 100644 (file)
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -21,11 +21,11 @@
  *
  * For now I enable fixing of address errors by default to make life easier.
  * I however intend to disable this somewhen in the future when the alignment
  *
  * For now I enable fixing of address errors by default to make life easier.
  * I however intend to disable this somewhen in the future when the alignment

- * problems with user programs have been fixed.  For programmers this is the
+ * problems with user programs have been fixed.         For programmers this is the

  * right way to go.
  *
  * Fixing address errors is a per process option.  The option is inherited
  * right way to go.
  *
  * Fixing address errors is a per process option.  The option is inherited

- * across fork(2) and execve(2) calls.  If you really want to use the
+ * across fork(2) and execve(2) calls. If you really want to use the

  * option in your user programs - I discourage the use of the software
  * emulation strongly - use the following code in your userland stuff:
  *
  * option in your user programs - I discourage the use of the software
  * emulation strongly - use the following code in your userland stuff:
  *


@@ -43,34 +43,34 @@
  * #include <sys/sysmips.h>
  *
  * struct foo {
  * #include <sys/sysmips.h>
  *
  * struct foo {

- *         unsigned char bar[8];
+ *        unsigned char bar[8];

  * };
  *
  * main(int argc, char *argv[])
  * {
  * };
  *
  * main(int argc, char *argv[])
  * {

- *         struct foo x = {0, 1, 2, 3, 4, 5, 6, 7};
- *         unsigned int *p = (unsigned int *) (x.bar + 3);
- *         int i;
+ *        struct foo x = {0, 1, 2, 3, 4, 5, 6, 7};
+ *        unsigned int *p = (unsigned int *) (x.bar + 3);
+ *        int i;

  *
  *

- *         if (argc > 1)
- *                 sysmips(MIPS_FIXADE, atoi(argv[1]));
+ *        if (argc > 1)
+ *                sysmips(MIPS_FIXADE, atoi(argv[1]));

  *
  *

- *         printf("*p = %08lx\n", *p);
+ *        printf("*p = %08lx\n", *p);

  *
  *

- *         *p = 0xdeadface;
+ *        *p = 0xdeadface;

  *
  *

- *         for(i = 0; i <= 7; i++)
- *         printf("%02x ", x.bar[i]);
- *         printf("\n");
+ *        for(i = 0; i <= 7; i++)
+ *        printf("%02x ", x.bar[i]);
+ *        printf("\n");

  * }
  *
  * Coprocessor loads are not supported; I think this case is unimportant
  * in the practice.
  *
  * TODO: Handle ndc (attempted store to doubleword in uncached memory)
  * }
  *
  * Coprocessor loads are not supported; I think this case is unimportant
  * in the practice.
  *
  * TODO: Handle ndc (attempted store to doubleword in uncached memory)

- *       exception for the R6000.
- *       A store crossing a page boundary might be executed only partially.
- *       Undo the partial store in this case.
+ *      exception for the R6000.
+ *      A store crossing a page boundary might be executed only partially.
+ *      Undo the partial store in this case.

  */
 #include <linux/mm.h>
 #include <linux/signal.h>
  */
 #include <linux/mm.h>
 #include <linux/signal.h>


@@ -86,7 +86,7 @@
 #include <asm/inst.h>
 #include <asm/uaccess.h>
 
 #include <asm/inst.h>
 #include <asm/uaccess.h>
 

-#define STR(x)  __STR(x)
+#define STR(x) __STR(x)

 #define __STR(x)  #x
 
 enum {
 #define __STR(x)  #x
 
 enum {

diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 0a4336b803e9e15f4b6031824849e0ade3062002..05826d20a7923a47d06a7affb196f6388c6f1d70 100644 (file)
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -22,12 +22,12 @@ PHDRS {
 
 #ifdef CONFIG_32BIT
        #ifdef CONFIG_CPU_LITTLE_ENDIAN
 
 #ifdef CONFIG_32BIT
        #ifdef CONFIG_CPU_LITTLE_ENDIAN

-               jiffies  = jiffies_64;
+               jiffies  = jiffies_64;

        #else
        #else

-               jiffies  = jiffies_64 + 4;
+               jiffies  = jiffies_64 + 4;

        #endif
 #else
        #endif
 #else

-       jiffies  = jiffies_64;
+       jiffies  = jiffies_64;

 #endif
 
 SECTIONS
 #endif
 
 SECTIONS


@@ -139,7 +139,7 @@ SECTIONS
 
        /*
         * Force .bss to 64K alignment so that .bss..swapper_pg_dir
 
        /*
         * Force .bss to 64K alignment so that .bss..swapper_pg_dir

-        * gets that alignment.  .sbss should be empty, so there will be
+        * gets that alignment.  .sbss should be empty, so there will be

         * no holes after __init_end. */
        BSS_SECTION(0, 0x10000, 0)
 
         * no holes after __init_end. */
        BSS_SECTION(0, 0x10000, 0)
 

diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 147cec19621d7a433429e66433fdd993c2abd62e..32fc5d4a22e51e4782f79a5e44d4b7b4b68c91fe 100644 (file)
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -254,7 +254,7 @@ static void __maybe_unused dump_mtregs(void)
               val & MVPCONF0_PTC, (val & MVPCONF0_M) >> MVPCONF0_M_SHIFT);
 }
 
               val & MVPCONF0_PTC, (val & MVPCONF0_M) >> MVPCONF0_M_SHIFT);
 }
 

-/* Find some VPE program space  */
+/* Find some VPE program space */

 static void *alloc_progmem(unsigned long len)
 {
        void *addr;
 static void *alloc_progmem(unsigned long len)
 {
        void *addr;


@@ -292,7 +292,7 @@ static long get_offset(unsigned long *size, Elf_Shdr * sechdr)
 }
 
 /* Lay out the SHF_ALLOC sections in a way not dissimilar to how ld
 }
 
 /* Lay out the SHF_ALLOC sections in a way not dissimilar to how ld

-   might -- code, read-only data, read-write data, small data.  Tally
+   might -- code, read-only data, read-write data, small data. Tally

    sizes, and place the offsets into sh_entsize fields: high bit means it
    belongs in init. */
 static void layout_sections(struct module *mod, const Elf_Ehdr * hdr,
    sizes, and place the offsets into sh_entsize fields: high bit means it
    belongs in init. */
 static void layout_sections(struct module *mod, const Elf_Ehdr * hdr,


@@ -386,7 +386,7 @@ static int apply_r_mips_pc16(struct module *me, uint32_t *location,
 
        if( (rel > 32768) || (rel < -32768) ) {
                printk(KERN_DEBUG "VPE loader: "
 
        if( (rel > 32768) || (rel < -32768) ) {
                printk(KERN_DEBUG "VPE loader: "

-                      "apply_r_mips_pc16: relative address out of range 0x%x\n", rel);
+                      "apply_r_mips_pc16: relative address out of range 0x%x\n", rel);

                return -ENOEXEC;
        }
 
                return -ENOEXEC;
        }
 


@@ -458,7 +458,7 @@ static int apply_r_mips_lo16(struct module *me, uint32_t *location,
        Elf32_Addr val, vallo;
        struct mips_hi16 *l, *next;
 
        Elf32_Addr val, vallo;
        struct mips_hi16 *l, *next;
 

-       /* Sign extend the addend we extract from the lo insn.  */
+       /* Sign extend the addend we extract from the lo insn.  */

        vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000;
 
        if (mips_hi16_list != NULL) {
        vallo = ((insnlo & 0xffff) ^ 0x8000) - 0x8000;
 
        if (mips_hi16_list != NULL) {


@@ -470,7 +470,7 @@ static int apply_r_mips_lo16(struct module *me, uint32_t *location,
                        /*
                         * The value for the HI16 had best be the same.
                         */
                        /*
                         * The value for the HI16 had best be the same.
                         */

-                       if (v != l->value) {
+                       if (v != l->value) {

                                printk(KERN_DEBUG "VPE loader: "
                                       "apply_r_mips_lo16/hi16: \t"
                                       "inconsistent value information\n");
                                printk(KERN_DEBUG "VPE loader: "
                                       "apply_r_mips_lo16/hi16: \t"
                                       "inconsistent value information\n");


@@ -505,7 +505,7 @@ static int apply_r_mips_lo16(struct module *me, uint32_t *location,
        }
 
        /*
        }
 
        /*

-        * Ok, we're done with the HI16 relocs.  Now deal with the LO16.
+        * Ok, we're done with the HI16 relocs.  Now deal with the LO16.

         */
        val = v + vallo;
        insnlo = (insnlo & ~0xffff) | (val & 0xffff);
         */
        val = v + vallo;
        insnlo = (insnlo & ~0xffff) | (val & 0xffff);


@@ -579,7 +579,7 @@ static int apply_relocations(Elf32_Shdr *sechdrs,
                res = reloc_handlers[ELF32_R_TYPE(r_info)](me, location, v);
                if( res ) {
                        char *r = rstrs[ELF32_R_TYPE(r_info)];
                res = reloc_handlers[ELF32_R_TYPE(r_info)](me, location, v);
                if( res ) {
                        char *r = rstrs[ELF32_R_TYPE(r_info)];

-                       printk(KERN_WARNING "VPE loader: .text+0x%x "
+                       printk(KERN_WARNING "VPE loader: .text+0x%x "

                               "relocation type %s for symbol \"%s\" failed\n",
                               rel[i].r_offset, r ? r : "UNKNOWN",
                               strtab + sym->st_name);
                               "relocation type %s for symbol \"%s\" failed\n",
                               rel[i].r_offset, r ? r : "UNKNOWN",
                               strtab + sym->st_name);


@@ -772,7 +772,7 @@ static int vpe_run(struct vpe * v)
 
        /* Set up the XTC bit in vpeconf0 to point at our tc */
        write_vpe_c0_vpeconf0( (read_vpe_c0_vpeconf0() & ~(VPECONF0_XTC))
 
        /* Set up the XTC bit in vpeconf0 to point at our tc */
        write_vpe_c0_vpeconf0( (read_vpe_c0_vpeconf0() & ~(VPECONF0_XTC))

-                             | (t->index << VPECONF0_XTC_SHIFT));
+                             | (t->index << VPECONF0_XTC_SHIFT));

 
        back_to_back_c0_hazard();
 
 
        back_to_back_c0_hazard();
 


@@ -926,34 +926,34 @@ static int vpe_elfload(struct vpe * v)
                               secstrings + sechdrs[i].sh_name, sechdrs[i].sh_addr);
                }
 
                               secstrings + sechdrs[i].sh_name, sechdrs[i].sh_addr);
                }
 

-               /* Fix up syms, so that st_value is a pointer to location. */
-               simplify_symbols(sechdrs, symindex, strtab, secstrings,
-                                hdr->e_shnum, &mod);
-
-               /* Now do relocations. */
-               for (i = 1; i < hdr->e_shnum; i++) {
-                       const char *strtab = (char *)sechdrs[strindex].sh_addr;
-                       unsigned int info = sechdrs[i].sh_info;
-
-                       /* Not a valid relocation section? */
-                       if (info >= hdr->e_shnum)
-                               continue;
-
-                       /* Don't bother with non-allocated sections */
-                       if (!(sechdrs[info].sh_flags & SHF_ALLOC))
-                               continue;
-
-                       if (sechdrs[i].sh_type == SHT_REL)
-                               err = apply_relocations(sechdrs, strtab, symindex, i,
-                                                       &mod);
-                       else if (sechdrs[i].sh_type == SHT_RELA)
-                               err = apply_relocate_add(sechdrs, strtab, symindex, i,
-                                                        &mod);
-                       if (err < 0)
-                               return err;
-
-               }
-       } else {
+               /* Fix up syms, so that st_value is a pointer to location. */
+               simplify_symbols(sechdrs, symindex, strtab, secstrings,
+                                hdr->e_shnum, &mod);
+
+               /* Now do relocations. */
+               for (i = 1; i < hdr->e_shnum; i++) {
+                       const char *strtab = (char *)sechdrs[strindex].sh_addr;
+                       unsigned int info = sechdrs[i].sh_info;
+
+                       /* Not a valid relocation section? */
+                       if (info >= hdr->e_shnum)
+                               continue;
+
+                       /* Don't bother with non-allocated sections */
+                       if (!(sechdrs[info].sh_flags & SHF_ALLOC))
+                               continue;
+
+                       if (sechdrs[i].sh_type == SHT_REL)
+                               err = apply_relocations(sechdrs, strtab, symindex, i,
+                                                       &mod);
+                       else if (sechdrs[i].sh_type == SHT_RELA)
+                               err = apply_relocate_add(sechdrs, strtab, symindex, i,
+                                                        &mod);
+                       if (err < 0)
+                               return err;
+
+               }
+       } else {

                struct elf_phdr *phdr = (struct elf_phdr *) ((char *)hdr + hdr->e_phoff);
 
                for (i = 0; i < hdr->e_phnum; i++) {
                struct elf_phdr *phdr = (struct elf_phdr *) ((char *)hdr + hdr->e_phoff);
 
                for (i = 0; i < hdr->e_phnum; i++) {


@@ -968,16 +968,16 @@ static int vpe_elfload(struct vpe * v)
                }
 
                for (i = 0; i < hdr->e_shnum; i++) {
                }
 
                for (i = 0; i < hdr->e_shnum; i++) {

-                       /* Internal symbols and strings. */
-                       if (sechdrs[i].sh_type == SHT_SYMTAB) {
-                               symindex = i;
-                               strindex = sechdrs[i].sh_link;
-                               strtab = (char *)hdr + sechdrs[strindex].sh_offset;
-
-                               /* mark the symtab's address for when we try to find the
-                                  magic symbols */
-                               sechdrs[i].sh_addr = (size_t) hdr + sechdrs[i].sh_offset;
-                       }
+                       /* Internal symbols and strings. */
+                       if (sechdrs[i].sh_type == SHT_SYMTAB) {
+                               symindex = i;
+                               strindex = sechdrs[i].sh_link;
+                               strtab = (char *)hdr + sechdrs[strindex].sh_offset;
+
+                               /* mark the symtab's address for when we try to find the
+                                  magic symbols */
+                               sechdrs[i].sh_addr = (size_t) hdr + sechdrs[i].sh_offset;
+                       }

                }
        }
 
                }
        }
 


@@ -1049,7 +1049,7 @@ static int getcwd(char *buff, int size)
        return ret;
 }
 
        return ret;
 }
 

-/* checks VPE is unused and gets ready to load program  */
+/* checks VPE is unused and gets ready to load program */

 static int vpe_open(struct inode *inode, struct file *filp)
 {
        enum vpe_state state;
 static int vpe_open(struct inode *inode, struct file *filp)
 {
        enum vpe_state state;


@@ -1121,11 +1121,11 @@ static int vpe_release(struct inode *inode, struct file *filp)
                if (vpe_elfload(v) >= 0) {
                        vpe_run(v);
                } else {
                if (vpe_elfload(v) >= 0) {
                        vpe_run(v);
                } else {

-                       printk(KERN_WARNING "VPE loader: ELF load failed.\n");
+                       printk(KERN_WARNING "VPE loader: ELF load failed.\n");

                        ret = -ENOEXEC;
                }
        } else {
                        ret = -ENOEXEC;
                }
        } else {

-               printk(KERN_WARNING "VPE loader: only elf files are supported\n");
+               printk(KERN_WARNING "VPE loader: only elf files are supported\n");

                ret = -ENOEXEC;
        }
 
                ret = -ENOEXEC;
        }
 

diff --git a/arch/mips/kernel/watch.c b/arch/mips/kernel/watch.c
index c1540696803061d6c36cccfe6e96c94668932f4c..7726f6157d9e7b0aa48c8d7e7b051c86de9aea95 100644 (file)
--- a/arch/mips/kernel/watch.c
+++ b/arch/mips/kernel/watch.c
@@ -12,7 +12,7 @@
 #include <asm/watch.h>
 
 /*
 #include <asm/watch.h>
 
 /*

- * Install the watch registers for the current thread.  A maximum of
+ * Install the watch registers for the current thread. A maximum of

  * four registers are installed although the machine may have more.
  */
 void mips_install_watch_registers(void)
  * four registers are installed although the machine may have more.
  */
 void mips_install_watch_registers(void)


@@ -72,7 +72,7 @@ void mips_read_watch_registers(void)
  }
 
 /*
  }
 
 /*

- * Disable all watch registers.  Although only four registers are
+ * Disable all watch registers.         Although only four registers are

  * installed, all are cleared to eliminate the possibility of endless
  * looping in the watch handler.
  */
  * installed, all are cleared to eliminate the possibility of endless
  * looping in the watch handler.
  */

diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c
index ce2f129b081f8886d64968350a77b6f4f51bf45e..186fd3e44242425133318e7ea3cf30beaa6765b0 100644 (file)
--- a/arch/mips/lantiq/clk.c
+++ b/arch/mips/lantiq/clk.c
@@ -145,9 +145,9 @@ static inline u32 get_counter_resolution(void)
        u32 res;
 
        __asm__ __volatile__(
        u32 res;
 
        __asm__ __volatile__(

-               ".set   push\n"
-               ".set   mips32r2\n"
-               "rdhwr  %0, $3\n"
+               ".set   push\n"
+               ".set   mips32r2\n"
+               "rdhwr  %0, $3\n"

                ".set pop\n"
                : "=&r" (res)
                : /* no input */
                ".set pop\n"
                : "=&r" (res)
                : /* no input */

diff --git a/arch/mips/lantiq/dts/danube.dtsi b/arch/mips/lantiq/dts/danube.dtsi
index 3a4520f009cfcff8f5b87fe3d9316edcfc376f29..d4c59e003708e477f7b03ab9a8c845201c80c1e2 100644 (file)
--- a/arch/mips/lantiq/dts/danube.dtsi
+++ b/arch/mips/lantiq/dts/danube.dtsi
@@ -97,7 +97,7 @@
                        compatible = "lantiq,pci-xway";
                        bus-range = <0x0 0x0>;
                        ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000   /* pci memory */
                        compatible = "lantiq,pci-xway";
                        bus-range = <0x0 0x0>;
                        ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000   /* pci memory */

-                                 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */
+                                 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */

                        reg = <0x7000000 0x8000         /* config space */
                                0xE105400 0x400>;       /* pci bridge */
                };
                        reg = <0x7000000 0x8000         /* config space */
                                0xE105400 0x400>;       /* pci bridge */
                };

diff --git a/arch/mips/lantiq/dts/easy50712.dts b/arch/mips/lantiq/dts/easy50712.dts
index 68c17310bc820eacda6eba18728d303e733b0126..fac1f5b178ebe3c558ad369a9e1243340da04c80 100644 (file)
--- a/arch/mips/lantiq/dts/easy50712.dts
+++ b/arch/mips/lantiq/dts/easy50712.dts
@@ -103,7 +103,7 @@
                        lantiq,bus-clock = <33333333>;
                        interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                        interrupt-map = <
                        lantiq,bus-clock = <33333333>;
                        interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
                        interrupt-map = <

-                                0x7000 0 0 1 &icu0 29 1 // slot 14, irq 29
+                               0x7000 0 0 1 &icu0 29 1 // slot 14, irq 29

                        >;
                        gpios-reset = <&gpio 21 0>;
                        req-mask = <0x1>;               /* GNT1 */
                        >;
                        gpios-reset = <&gpio 21 0>;
                        req-mask = <0x1>;               /* GNT1 */

diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index a7935bf0fecbf789299a2547abb7b0b2e8677e2b..5323308aab3fb86b64ecfc1b7d5b9898082c89b8 100644 (file)
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -344,7 +344,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
        if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
                /* find out how many external irq sources we have */
                const __be32 *count = of_get_property(node,
        if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
                /* find out how many external irq sources we have */
                const __be32 *count = of_get_property(node,

-                                                       "lantiq,count", NULL);
+                                                       "lantiq,count", NULL);

 
                if (count)
                        exin_avail = *count;
 
                if (count)
                        exin_avail = *count;

diff --git a/arch/mips/lantiq/prom.h b/arch/mips/lantiq/prom.h
index a3fa1a2bfaae5accf32fc341d9a92b0df17438e7..8e07b5f28ef194c04667f4e5b3fa99893bf433c1 100644 (file)
--- a/arch/mips/lantiq/prom.h
+++ b/arch/mips/lantiq/prom.h
@@ -10,7 +10,7 @@
 #define _LTQ_PROM_H__
 
 #define LTQ_SYS_TYPE_LEN       0x100
 #define _LTQ_PROM_H__
 
 #define LTQ_SYS_TYPE_LEN       0x100

-#define LTQ_SYS_REV_LEN         0x10
+#define LTQ_SYS_REV_LEN                0x10

 
 struct ltq_soc_info {
        unsigned char *name;
 
 struct ltq_soc_info {
        unsigned char *name;

diff --git a/arch/mips/lasat/Makefile b/arch/mips/lasat/Makefile
index 9cc4e4db8b9932e14325803a793576dd90b50400..869bd3b37c17e0be329a7d6673ff463e8e6691d6 100644 (file)
--- a/arch/mips/lasat/Makefile
+++ b/arch/mips/lasat/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the LASAT specific kernel interface routines under Linux.
 #
 
 # Makefile for the LASAT specific kernel interface routines under Linux.
 #
 

-obj-y                          += reset.o setup.o prom.o lasat_board.o \
+obj-y                          += reset.o setup.o prom.o lasat_board.o \

                                   at93c.o interrupt.o serial.o
 
 obj-$(CONFIG_LASAT_SYSCTL)     += sysctl.o
                                   at93c.o interrupt.o serial.o
 
 obj-$(CONFIG_LASAT_SYSCTL)     += sysctl.o

diff --git a/arch/mips/lasat/ds1603.h b/arch/mips/lasat/ds1603.h
index 2da3704044fdde74d225c5d7090d5f7031663282..3e718b1cca025407b6034c851f2ffc389e8c7f94 100644 (file)
--- a/arch/mips/lasat/ds1603.h
+++ b/arch/mips/lasat/ds1603.h
@@ -25,7 +25,7 @@ void ds1603_enable(void);
 void ds1603_disable(void);
 void ds1603_init(struct ds_defs *);
 
 void ds1603_disable(void);
 void ds1603_init(struct ds_defs *);
 

-#define TRIMMER_DEFAULT        3
+#define TRIMMER_DEFAULT 3

 #define TRIMMER_DISABLE_RTC 0
 
 #endif
 #define TRIMMER_DISABLE_RTC 0
 
 #endif

diff --git a/arch/mips/lasat/image/Makefile b/arch/mips/lasat/image/Makefile
index 460626b6d62fc4cce318667032ccefa1f0de80aa..dfb509d21d8e544e4c552b7b222f901e90930aaa 100644 (file)
--- a/arch/mips/lasat/image/Makefile
+++ b/arch/mips/lasat/image/Makefile
@@ -28,7 +28,7 @@ $(obj)/head.o: $(obj)/head.S $(KERNEL_IMAGE)
 
 OBJECTS = head.o kImage.o
 
 
 OBJECTS = head.o kImage.o
 

-rom.sw:        $(obj)/rom.sw
+rom.sw: $(obj)/rom.sw

 rom.bin:       $(obj)/rom.bin
 
 $(obj)/rom.sw: $(obj)/rom.bin
 rom.bin:       $(obj)/rom.bin
 
 $(obj)/rom.sw: $(obj)/rom.bin

diff --git a/arch/mips/lasat/image/head.S b/arch/mips/lasat/image/head.S
index e0ecda92c40a86603293911e657b3a850ed3ade8..41babbe43a8e2b988f5fc465b0f5937b13b10f0a 100644 (file)
--- a/arch/mips/lasat/image/head.S
+++ b/arch/mips/lasat/image/head.S
@@ -7,7 +7,7 @@
 
        /* Magic words identifying a software image */
        .word   LASAT_K_MAGIC0_VAL
 
        /* Magic words identifying a software image */
        .word   LASAT_K_MAGIC0_VAL

-       .word   LASAT_K_MAGIC1_VAL
+       .word   LASAT_K_MAGIC1_VAL

 
        /* Image header version */
        .word   0x00000002
 
        /* Image header version */
        .word   0x00000002

diff --git a/arch/mips/lasat/picvue.c b/arch/mips/lasat/picvue.c
index d3d04c392e251f2d21a9ef6b5d5fb71ca7b784dd..7eb334892693db3fd5d5951f67fd23bd5552ed03 100644 (file)
--- a/arch/mips/lasat/picvue.c
+++ b/arch/mips/lasat/picvue.c
@@ -163,12 +163,12 @@ int pvc_program_cg(int charnum, u8 bitmap[BM_SIZE])
 }
 
 #define FUNC_SET_CMD   0x20
 }
 
 #define FUNC_SET_CMD   0x20

-#define  EIGHT_BYTE    (1 << 4)
-#define  FOUR_BYTE     0
-#define  TWO_LINES     (1 << 3)
-#define  ONE_LINE      0
-#define  LARGE_FONT    (1 << 2)
-#define  SMALL_FONT    0
+#define         EIGHT_BYTE     (1 << 4)
+#define         FOUR_BYTE      0
+#define         TWO_LINES      (1 << 3)
+#define         ONE_LINE       0
+#define         LARGE_FONT     (1 << 2)
+#define         SMALL_FONT     0

 
 static void pvc_funcset(u8 cmd)
 {
 
 static void pvc_funcset(u8 cmd)
 {


@@ -177,9 +177,9 @@ static void pvc_funcset(u8 cmd)
 }
 
 #define ENTRYMODE_CMD          0x4
 }
 
 #define ENTRYMODE_CMD          0x4

-#define  AUTO_INC              (1 << 1)
-#define  AUTO_DEC              0
-#define  CURSOR_FOLLOWS_DISP   (1 << 0)
+#define         AUTO_INC               (1 << 1)
+#define         AUTO_DEC               0
+#define         CURSOR_FOLLOWS_DISP    (1 << 0)

 
 static void pvc_entrymode(u8 cmd)
 {
 
 static void pvc_entrymode(u8 cmd)
 {


@@ -188,20 +188,20 @@ static void pvc_entrymode(u8 cmd)
 }
 
 #define DISP_CNT_CMD   0x08
 }
 
 #define DISP_CNT_CMD   0x08

-#define  DISP_OFF      0
-#define  DISP_ON       (1 << 2)
-#define  CUR_ON                (1 << 1)
-#define  CUR_BLINK     (1 << 0)
+#define         DISP_OFF       0
+#define         DISP_ON        (1 << 2)
+#define         CUR_ON         (1 << 1)
+#define         CUR_BLINK      (1 << 0)

 void pvc_dispcnt(u8 cmd)
 {
        pvc_write(DISP_CNT_CMD | (cmd & (DISP_ON|CUR_ON|CUR_BLINK)), MODE_INST);
 }
 
 #define MOVE_CMD       0x10
 void pvc_dispcnt(u8 cmd)
 {
        pvc_write(DISP_CNT_CMD | (cmd & (DISP_ON|CUR_ON|CUR_BLINK)), MODE_INST);
 }
 
 #define MOVE_CMD       0x10

-#define  DISPLAY       (1 << 3)
-#define  CURSOR                0
-#define  RIGHT         (1 << 2)
-#define  LEFT          0
+#define         DISPLAY        (1 << 3)
+#define         CURSOR         0
+#define         RIGHT          (1 << 2)
+#define         LEFT           0

 void pvc_move(u8 cmd)
 {
        pvc_write(MOVE_CMD | (cmd & (DISPLAY|RIGHT)), MODE_INST);
 void pvc_move(u8 cmd)
 {
        pvc_write(MOVE_CMD | (cmd & (DISPLAY|RIGHT)), MODE_INST);

diff --git a/arch/mips/lasat/picvue.h b/arch/mips/lasat/picvue.h
index 2f0757738fdb2d777c253426856fd58230b18d26..d0119fca3862208356a7a2d6d05f26c221972441 100644 (file)
--- a/arch/mips/lasat/picvue.h
+++ b/arch/mips/lasat/picvue.h
@@ -29,16 +29,16 @@ void pvc_dump_string(const unsigned char *str);
 int pvc_program_cg(int charnum, u8 bitmap[BM_SIZE]);
 
 void pvc_dispcnt(u8 cmd);
 int pvc_program_cg(int charnum, u8 bitmap[BM_SIZE]);
 
 void pvc_dispcnt(u8 cmd);

-#define  DISP_OFF      0
-#define  DISP_ON       (1 << 2)
-#define  CUR_ON                (1 << 1)
-#define  CUR_BLINK     (1 << 0)
+#define         DISP_OFF       0
+#define         DISP_ON        (1 << 2)
+#define         CUR_ON         (1 << 1)
+#define         CUR_BLINK      (1 << 0)

 
 void pvc_move(u8 cmd);
 
 void pvc_move(u8 cmd);

-#define  DISPLAY       (1 << 3)
-#define  CURSOR                0
-#define  RIGHT         (1 << 2)
-#define  LEFT          0
+#define         DISPLAY        (1 << 3)
+#define         CURSOR         0
+#define         RIGHT          (1 << 2)
+#define         LEFT           0

 
 void pvc_clear(void);
 void pvc_home(void);
 
 void pvc_clear(void);
 void pvc_home(void);

diff --git a/arch/mips/lasat/serial.c b/arch/mips/lasat/serial.c
index 5bcb6e89ab78755282d2e53e73d7d56a1577c9ce..2e5fbed8120674038e6c407a526654cf850606d5 100644 (file)
--- a/arch/mips/lasat/serial.c
+++ b/arch/mips/lasat/serial.c
@@ -1,7 +1,7 @@
 /*
  *  Registration of Lasat UART platform device.
  *
 /*
  *  Registration of Lasat UART platform device.
  *

- *  Copyright (C) 2007  Brian Murphy <brian@murphy.dk>
+ *  Copyright (C) 2007 Brian Murphy <brian@murphy.dk>

  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by

diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c
index d87ffd04cb0adfc1d10c824c1dd88c90b336c159..f27694fb2ad191467fe523ffbca2adbe7cb25eb6 100644 (file)
--- a/arch/mips/lasat/sysctl.c
+++ b/arch/mips/lasat/sysctl.c
@@ -134,8 +134,8 @@ int proc_lasat_ip(ctl_table *table, int write,
        } else {
                ip = *(unsigned int *)(table->data);
                sprintf(ipbuf, "%d.%d.%d.%d",
        } else {
                ip = *(unsigned int *)(table->data);
                sprintf(ipbuf, "%d.%d.%d.%d",

-                       (ip)       & 0xff,
-                       (ip >>  8) & 0xff,
+                       (ip)       & 0xff,
+                       (ip >>  8) & 0xff,

                        (ip >> 16) & 0xff,
                        (ip >> 24) & 0xff);
                len = strlen(ipbuf);
                        (ip >> 16) & 0xff,
                        (ip >> 24) & 0xff);
                len = strlen(ipbuf);

diff --git a/arch/mips/lib/bitops.c b/arch/mips/lib/bitops.c
index 239a9c957b026a446d045217d852e278a101ca18..81f1dcfdcab8c212ebbac6c5159291dc8b8e1162 100644 (file)
--- a/arch/mips/lib/bitops.c
+++ b/arch/mips/lib/bitops.c
@@ -56,7 +56,7 @@ EXPORT_SYMBOL(__mips_clear_bit);
 
 
 /**
 
 
 /**

- * __mips_change_bit - Toggle a bit in memory.  This is called by change_bit()
+ * __mips_change_bit - Toggle a bit in memory. This is called by change_bit()

  * if it cannot find a faster solution.
  * @nr: Bit to change
  * @addr: Address to start counting from
  * if it cannot find a faster solution.
  * @nr: Bit to change
  * @addr: Address to start counting from


@@ -155,7 +155,7 @@ EXPORT_SYMBOL(__mips_test_and_clear_bit);
 
 
 /**
 
 
 /**

- * __mips_test_and_change_bit - Change a bit and return its old value.  This is
+ * __mips_test_and_change_bit - Change a bit and return its old value. This is

  * called by test_and_change_bit() if it cannot find a faster solution.
  * @nr: Bit to change
  * @addr: Address to count from
  * called by test_and_change_bit() if it cannot find a faster solution.
  * @nr: Bit to change
  * @addr: Address to count from

diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index 6b876ca299eeb4d4d7f684a441e70158942968b1..507147aebd417d612633e1104b83fd8bff08cbce 100644 (file)
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -67,8 +67,8 @@
 #define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3)   \
        LOAD    _t0, (offset + UNIT(0))(src);                   \
        LOAD    _t1, (offset + UNIT(1))(src);                   \
 #define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3)   \
        LOAD    _t0, (offset + UNIT(0))(src);                   \
        LOAD    _t1, (offset + UNIT(1))(src);                   \

-       LOAD    _t2, (offset + UNIT(2))(src);                   \
-       LOAD    _t3, (offset + UNIT(3))(src);                   \
+       LOAD    _t2, (offset + UNIT(2))(src);                   \
+       LOAD    _t3, (offset + UNIT(3))(src);                   \

        ADDC(sum, _t0);                                         \
        ADDC(sum, _t1);                                         \
        ADDC(sum, _t2);                                         \
        ADDC(sum, _t0);                                         \
        ADDC(sum, _t1);                                         \
        ADDC(sum, _t2);                                         \


@@ -285,7 +285,7 @@ LEAF(csum_partial)
 1:
 #endif
        .set    reorder
 1:
 #endif
        .set    reorder

-       /* Add the passed partial csum.  */
+       /* Add the passed partial csum.  */

        ADDC32(sum, a2)
        jr      ra
        .set    noreorder
        ADDC32(sum, a2)
        jr      ra
        .set    noreorder


@@ -298,7 +298,7 @@ LEAF(csum_partial)
  *     csum_partial_copy_nocheck(src, dst, len, sum)
  *     __csum_partial_copy_user(src, dst, len, sum, errp)
  *
  *     csum_partial_copy_nocheck(src, dst, len, sum)
  *     __csum_partial_copy_user(src, dst, len, sum, errp)
  *

- * See "Spec" in memcpy.S for details.  Unlike __copy_user, all
+ * See "Spec" in memcpy.S for details. Unlike __copy_user, all

  * function in this file use the standard calling convention.
  */
 
  * function in this file use the standard calling convention.
  */
 


@@ -371,16 +371,16 @@ LEAF(csum_partial)
 
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 #define LDFIRST LOADR
 
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 #define LDFIRST LOADR

-#define LDREST  LOADL
+#define LDREST LOADL

 #define STFIRST STORER
 #define STFIRST STORER

-#define STREST  STOREL
+#define STREST STOREL

 #define SHIFT_DISCARD SLLV
 #define SHIFT_DISCARD_REVERT SRLV
 #else
 #define LDFIRST LOADL
 #define SHIFT_DISCARD SLLV
 #define SHIFT_DISCARD_REVERT SRLV
 #else
 #define LDFIRST LOADL

-#define LDREST  LOADR
+#define LDREST LOADR

 #define STFIRST STOREL
 #define STFIRST STOREL

-#define STREST  STORER
+#define STREST STORER

 #define SHIFT_DISCARD SRLV
 #define SHIFT_DISCARD_REVERT SLLV
 #endif
 #define SHIFT_DISCARD SRLV
 #define SHIFT_DISCARD_REVERT SLLV
 #endif


@@ -430,7 +430,7 @@ FEXPORT(csum_partial_copy_nocheck)
         * src and dst are aligned; need to compute rem
         */
 .Lboth_aligned:
         * src and dst are aligned; need to compute rem
         */
 .Lboth_aligned:

-        SRL    t0, len, LOG_NBYTES+3    # +3 for 8 units/iter
+        SRL    t0, len, LOG_NBYTES+3    # +3 for 8 units/iter

        beqz    t0, .Lcleanup_both_aligned # len < 8*NBYTES
         nop
        SUB     len, 8*NBYTES           # subtract here for bgez loop
        beqz    t0, .Lcleanup_both_aligned # len < 8*NBYTES
         nop
        SUB     len, 8*NBYTES           # subtract here for bgez loop


@@ -518,7 +518,7 @@ EXC(        STORE   t0, 0(dst),             .Ls_exc)
        /*
         * src and dst are aligned, need to copy rem bytes (rem < NBYTES)
         * A loop would do only a byte at a time with possible branch
        /*
         * src and dst are aligned, need to copy rem bytes (rem < NBYTES)
         * A loop would do only a byte at a time with possible branch

-        * mispredicts.  Can't do an explicit LOAD dst,mask,or,STORE
+        * mispredicts.  Can't do an explicit LOAD dst,mask,or,STORE

         * because can't assume read-access to dst.  Instead, use
         * STREST dst, which doesn't require read access to dst.
         *
         * because can't assume read-access to dst.  Instead, use
         * STREST dst, which doesn't require read access to dst.
         *


@@ -532,7 +532,7 @@ EXC(        STORE   t0, 0(dst),             .Ls_exc)
        li      bits, 8*NBYTES
        SLL     rem, len, 3     # rem = number of bits to keep
 EXC(   LOAD    t0, 0(src),             .Ll_exc)
        li      bits, 8*NBYTES
        SLL     rem, len, 3     # rem = number of bits to keep
 EXC(   LOAD    t0, 0(src),             .Ll_exc)

-       SUB     bits, bits, rem # bits = number of bits to discard
+       SUB     bits, bits, rem # bits = number of bits to discard

        SHIFT_DISCARD t0, t0, bits
 EXC(   STREST  t0, -1(t1),             .Ls_exc)
        SHIFT_DISCARD_REVERT t0, t0, bits
        SHIFT_DISCARD t0, t0, bits
 EXC(   STREST  t0, -1(t1),             .Ls_exc)
        SHIFT_DISCARD_REVERT t0, t0, bits


@@ -551,7 +551,7 @@ EXC(        STREST  t0, -1(t1),             .Ls_exc)
         * Set match = (src and dst have same alignment)
         */
 #define match rem
         * Set match = (src and dst have same alignment)
         */
 #define match rem

-EXC(   LDFIRST t3, FIRST(0)(src),      .Ll_exc)
+EXC(   LDFIRST t3, FIRST(0)(src),      .Ll_exc)

        ADD     t2, zero, NBYTES
 EXC(   LDREST  t3, REST(0)(src),       .Ll_exc_copy)
        SUB     t2, t2, t1      # t2 = number of bytes copied
        ADD     t2, zero, NBYTES
 EXC(   LDREST  t3, REST(0)(src),       .Ll_exc_copy)
        SUB     t2, t2, t1      # t2 = number of bytes copied


@@ -568,9 +568,9 @@ EXC(        STFIRST t3, FIRST(0)(dst),      .Ls_exc)
         ADD    src, src, t2
 
 .Lsrc_unaligned_dst_aligned:
         ADD    src, src, t2
 
 .Lsrc_unaligned_dst_aligned:

-       SRL     t0, len, LOG_NBYTES+2    # +2 for 4 units/iter
+       SRL     t0, len, LOG_NBYTES+2    # +2 for 4 units/iter

        beqz    t0, .Lcleanup_src_unaligned
        beqz    t0, .Lcleanup_src_unaligned

-        and    rem, len, (4*NBYTES-1)   # rem = len % 4*NBYTES
+        and    rem, len, (4*NBYTES-1)   # rem = len % 4*NBYTES

 1:
 /*
  * Avoid consecutive LD*'s to the same register since some mips
 1:
 /*
  * Avoid consecutive LD*'s to the same register since some mips


@@ -578,13 +578,13 @@ EXC(      STFIRST t3, FIRST(0)(dst),      .Ls_exc)
  * It's OK to load FIRST(N+1) before REST(N) because the two addresses
  * are to the same unit (unless src is aligned, but it's not).
  */
  * It's OK to load FIRST(N+1) before REST(N) because the two addresses
  * are to the same unit (unless src is aligned, but it's not).
  */

-EXC(   LDFIRST t0, FIRST(0)(src),      .Ll_exc)
-EXC(   LDFIRST t1, FIRST(1)(src),      .Ll_exc_copy)
-       SUB     len, len, 4*NBYTES
+EXC(   LDFIRST t0, FIRST(0)(src),      .Ll_exc)
+EXC(   LDFIRST t1, FIRST(1)(src),      .Ll_exc_copy)
+       SUB     len, len, 4*NBYTES

 EXC(   LDREST  t0, REST(0)(src),       .Ll_exc_copy)
 EXC(   LDREST  t1, REST(1)(src),       .Ll_exc_copy)
 EXC(   LDREST  t0, REST(0)(src),       .Ll_exc_copy)
 EXC(   LDREST  t1, REST(1)(src),       .Ll_exc_copy)

-EXC(   LDFIRST t2, FIRST(2)(src),      .Ll_exc_copy)
-EXC(   LDFIRST t3, FIRST(3)(src),      .Ll_exc_copy)
+EXC(   LDFIRST t2, FIRST(2)(src),      .Ll_exc_copy)
+EXC(   LDFIRST t3, FIRST(3)(src),      .Ll_exc_copy)

 EXC(   LDREST  t2, REST(2)(src),       .Ll_exc_copy)
 EXC(   LDREST  t3, REST(3)(src),       .Ll_exc_copy)
        ADD     src, src, 4*NBYTES
 EXC(   LDREST  t2, REST(2)(src),       .Ll_exc_copy)
 EXC(   LDREST  t3, REST(3)(src),       .Ll_exc_copy)
        ADD     src, src, 4*NBYTES


@@ -634,7 +634,7 @@ EXC(        STORE   t0, 0(dst),             .Ls_exc)
 #define SHIFT_INC -8
 #endif
        move    t2, zero        # partial word
 #define SHIFT_INC -8
 #endif
        move    t2, zero        # partial word

-       li      t3, SHIFT_START # shift
+       li      t3, SHIFT_START # shift

 /* use .Ll_exc_copy here to return correct sum on fault */
 #define COPY_BYTE(N)                   \
 EXC(   lbu     t0, N(src), .Ll_exc_copy);      \
 /* use .Ll_exc_copy here to return correct sum on fault */
 #define COPY_BYTE(N)                   \
 EXC(   lbu     t0, N(src), .Ll_exc_copy);      \


@@ -642,7 +642,7 @@ EXC(        lbu     t0, N(src), .Ll_exc_copy);      \
 EXC(   sb      t0, N(dst), .Ls_exc);   \
        SLLV    t0, t0, t3;             \
        addu    t3, SHIFT_INC;          \
 EXC(   sb      t0, N(dst), .Ls_exc);   \
        SLLV    t0, t0, t3;             \
        addu    t3, SHIFT_INC;          \

-       beqz    len, .Lcopy_bytes_done; \
+       beqz    len, .Lcopy_bytes_done; \

         or     t2, t0
 
        COPY_BYTE(0)
         or     t2, t0
 
        COPY_BYTE(0)

diff --git a/arch/mips/lib/delay.c b/arch/mips/lib/delay.c
index 288f7954988d06ef61cc94bbf29dfeab322796b8..44713af15a62bc60ebc53ffcbc9e73ad10d87380 100644 (file)
--- a/arch/mips/lib/delay.c
+++ b/arch/mips/lib/delay.c
@@ -36,7 +36,7 @@ EXPORT_SYMBOL(__delay);
  * Division by multiplication: you don't have to worry about
  * loss of precision.
  *
  * Division by multiplication: you don't have to worry about
  * loss of precision.
  *

- * Use only for very small delays ( < 1 msec).  Should probably use a
+ * Use only for very small delays ( < 1 msec). Should probably use a

  * lookup table, really, as the multiplications take much too long with
  * short delays.  This is a "reasonable" implementation, though (and the
  * first constant multiplications gets optimized away if the delay is
  * lookup table, really, as the multiplications take much too long with
  * short delays.  This is a "reasonable" implementation, though (and the
  * first constant multiplications gets optimized away if the delay is

diff --git a/arch/mips/lib/dump_tlb.c b/arch/mips/lib/dump_tlb.c
index a99c1d3fc56769dc91f58ce64e117e0eb8533b44..32b9f21bfd8562f37d8e51e1ad23908c320ad3e8 100644 (file)
--- a/arch/mips/lib/dump_tlb.c
+++ b/arch/mips/lib/dump_tlb.c
@@ -63,7 +63,7 @@ static void dump_tlb(int first, int last)
                tlb_read();
                BARRIER();
                pagemask = read_c0_pagemask();
                tlb_read();
                BARRIER();
                pagemask = read_c0_pagemask();

-               entryhi  = read_c0_entryhi();
+               entryhi  = read_c0_entryhi();

                entrylo0 = read_c0_entrylo0();
                entrylo1 = read_c0_entrylo1();
 
                entrylo0 = read_c0_entrylo0();
                entrylo1 = read_c0_entrylo1();
 

diff --git a/arch/mips/lib/memcpy.S b/arch/mips/lib/memcpy.S
index 65192c06781e6d876767e6110e2c104e5b0e7a08..c5c40dad0bbf6791d13da727b7262063b4511de0 100644 (file)
--- a/arch/mips/lib/memcpy.S
+++ b/arch/mips/lib/memcpy.S
@@ -156,15 +156,15 @@
 
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 #define LDFIRST LOADR
 
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 #define LDFIRST LOADR

-#define LDREST  LOADL
+#define LDREST LOADL

 #define STFIRST STORER
 #define STFIRST STORER

-#define STREST  STOREL
+#define STREST STOREL

 #define SHIFT_DISCARD SLLV
 #else
 #define LDFIRST LOADL
 #define SHIFT_DISCARD SLLV
 #else
 #define LDFIRST LOADL

-#define LDREST  LOADR
+#define LDREST LOADR

 #define STFIRST STOREL
 #define STFIRST STOREL

-#define STREST  STORER
+#define STREST STORER

 #define SHIFT_DISCARD SRLV
 #endif
 
 #define SHIFT_DISCARD SRLV
 #endif
 


@@ -235,7 +235,7 @@ __copy_user_common:
         * src and dst are aligned; need to compute rem
         */
 .Lboth_aligned:
         * src and dst are aligned; need to compute rem
         */
 .Lboth_aligned:

-        SRL    t0, len, LOG_NBYTES+3    # +3 for 8 units/iter
+        SRL    t0, len, LOG_NBYTES+3    # +3 for 8 units/iter

        beqz    t0, .Lcleanup_both_aligned # len < 8*NBYTES
         and    rem, len, (8*NBYTES-1)   # rem = len % (8*NBYTES)
        PREF(   0, 3*32(src) )
        beqz    t0, .Lcleanup_both_aligned # len < 8*NBYTES
         and    rem, len, (8*NBYTES-1)   # rem = len % (8*NBYTES)
        PREF(   0, 3*32(src) )


@@ -313,7 +313,7 @@ EXC(        STORE   t0, 0(dst),             .Ls_exc_p1u)
        /*
         * src and dst are aligned, need to copy rem bytes (rem < NBYTES)
         * A loop would do only a byte at a time with possible branch
        /*
         * src and dst are aligned, need to copy rem bytes (rem < NBYTES)
         * A loop would do only a byte at a time with possible branch

-        * mispredicts.  Can't do an explicit LOAD dst,mask,or,STORE
+        * mispredicts.  Can't do an explicit LOAD dst,mask,or,STORE

         * because can't assume read-access to dst.  Instead, use
         * STREST dst, which doesn't require read access to dst.
         *
         * because can't assume read-access to dst.  Instead, use
         * STREST dst, which doesn't require read access to dst.
         *


@@ -327,7 +327,7 @@ EXC(        STORE   t0, 0(dst),             .Ls_exc_p1u)
        li      bits, 8*NBYTES
        SLL     rem, len, 3     # rem = number of bits to keep
 EXC(   LOAD    t0, 0(src),             .Ll_exc)
        li      bits, 8*NBYTES
        SLL     rem, len, 3     # rem = number of bits to keep
 EXC(   LOAD    t0, 0(src),             .Ll_exc)

-       SUB     bits, bits, rem # bits = number of bits to discard
+       SUB     bits, bits, rem # bits = number of bits to discard

        SHIFT_DISCARD t0, t0, bits
 EXC(   STREST  t0, -1(t1),             .Ls_exc)
        jr      ra
        SHIFT_DISCARD t0, t0, bits
 EXC(   STREST  t0, -1(t1),             .Ls_exc)
        jr      ra


@@ -343,7 +343,7 @@ EXC(        STREST  t0, -1(t1),             .Ls_exc)
         * Set match = (src and dst have same alignment)
         */
 #define match rem
         * Set match = (src and dst have same alignment)
         */
 #define match rem

-EXC(   LDFIRST t3, FIRST(0)(src),      .Ll_exc)
+EXC(   LDFIRST t3, FIRST(0)(src),      .Ll_exc)

        ADD     t2, zero, NBYTES
 EXC(   LDREST  t3, REST(0)(src),       .Ll_exc_copy)
        SUB     t2, t2, t1      # t2 = number of bytes copied
        ADD     t2, zero, NBYTES
 EXC(   LDREST  t3, REST(0)(src),       .Ll_exc_copy)
        SUB     t2, t2, t1      # t2 = number of bytes copied


@@ -357,10 +357,10 @@ EXC(      STFIRST t3, FIRST(0)(dst),      .Ls_exc)
         ADD    src, src, t2
 
 .Lsrc_unaligned_dst_aligned:
         ADD    src, src, t2
 
 .Lsrc_unaligned_dst_aligned:

-       SRL     t0, len, LOG_NBYTES+2    # +2 for 4 units/iter
+       SRL     t0, len, LOG_NBYTES+2    # +2 for 4 units/iter

        PREF(   0, 3*32(src) )
        beqz    t0, .Lcleanup_src_unaligned
        PREF(   0, 3*32(src) )
        beqz    t0, .Lcleanup_src_unaligned

-        and    rem, len, (4*NBYTES-1)   # rem = len % 4*NBYTES
+        and    rem, len, (4*NBYTES-1)   # rem = len % 4*NBYTES

        PREF(   1, 3*32(dst) )
 1:
 /*
        PREF(   1, 3*32(dst) )
 1:
 /*


@@ -370,13 +370,13 @@ EXC(      STFIRST t3, FIRST(0)(dst),      .Ls_exc)
  * are to the same unit (unless src is aligned, but it's not).
  */
        R10KCBARRIER(0(ra))
  * are to the same unit (unless src is aligned, but it's not).
  */
        R10KCBARRIER(0(ra))

-EXC(   LDFIRST t0, FIRST(0)(src),      .Ll_exc)
-EXC(   LDFIRST t1, FIRST(1)(src),      .Ll_exc_copy)
-       SUB     len, len, 4*NBYTES
+EXC(   LDFIRST t0, FIRST(0)(src),      .Ll_exc)
+EXC(   LDFIRST t1, FIRST(1)(src),      .Ll_exc_copy)
+       SUB     len, len, 4*NBYTES

 EXC(   LDREST  t0, REST(0)(src),       .Ll_exc_copy)
 EXC(   LDREST  t1, REST(1)(src),       .Ll_exc_copy)
 EXC(   LDREST  t0, REST(0)(src),       .Ll_exc_copy)
 EXC(   LDREST  t1, REST(1)(src),       .Ll_exc_copy)

-EXC(   LDFIRST t2, FIRST(2)(src),      .Ll_exc_copy)
-EXC(   LDFIRST t3, FIRST(3)(src),      .Ll_exc_copy)
+EXC(   LDFIRST t2, FIRST(2)(src),      .Ll_exc_copy)
+EXC(   LDFIRST t3, FIRST(3)(src),      .Ll_exc_copy)

 EXC(   LDREST  t2, REST(2)(src),       .Ll_exc_copy)
 EXC(   LDREST  t3, REST(3)(src),       .Ll_exc_copy)
        PREF(   0, 9*32(src) )          # 0 is PREF_LOAD  (not streamed)
 EXC(   LDREST  t2, REST(2)(src),       .Ll_exc_copy)
 EXC(   LDREST  t3, REST(3)(src),       .Ll_exc_copy)
        PREF(   0, 9*32(src) )          # 0 is PREF_LOAD  (not streamed)


@@ -388,7 +388,7 @@ EXC(        STORE   t0, UNIT(0)(dst),       .Ls_exc_p4u)
 EXC(   STORE   t1, UNIT(1)(dst),       .Ls_exc_p3u)
 EXC(   STORE   t2, UNIT(2)(dst),       .Ls_exc_p2u)
 EXC(   STORE   t3, UNIT(3)(dst),       .Ls_exc_p1u)
 EXC(   STORE   t1, UNIT(1)(dst),       .Ls_exc_p3u)
 EXC(   STORE   t2, UNIT(2)(dst),       .Ls_exc_p2u)
 EXC(   STORE   t3, UNIT(3)(dst),       .Ls_exc_p1u)

-       PREF(   1, 9*32(dst) )          # 1 is PREF_STORE (not streamed)
+       PREF(   1, 9*32(dst) )          # 1 is PREF_STORE (not streamed)

        .set    reorder                         /* DADDI_WAR */
        ADD     dst, dst, 4*NBYTES
        bne     len, rem, 1b
        .set    reorder                         /* DADDI_WAR */
        ADD     dst, dst, 4*NBYTES
        bne     len, rem, 1b


@@ -502,7 +502,7 @@ EXC(        lb      t1, 0(src),     .Ll_exc)
 
 
 #define SEXC(n)                                                        \
 
 
 #define SEXC(n)                                                        \

-       .set    reorder;                        /* DADDI_WAR */ \
+       .set    reorder;                        /* DADDI_WAR */ \

 .Ls_exc_p ## n ## u:                                           \
        ADD     len, len, n*NBYTES;                             \
        jr      ra;                                             \
 .Ls_exc_p ## n ## u:                                           \
        ADD     len, len, n*NBYTES;                             \
        jr      ra;                                             \

diff --git a/arch/mips/lib/memset.S b/arch/mips/lib/memset.S
index 606c8a9efe3bb146930aca3b7c438f0095cbe066..053d3b0b0317b18d848b2b2419025ebb1f23db31 100644 (file)
--- a/arch/mips/lib/memset.S
+++ b/arch/mips/lib/memset.S
@@ -21,8 +21,8 @@
 
 #define EX(insn,reg,addr,handler)                      \
 9:     insn    reg, addr;                              \
 
 #define EX(insn,reg,addr,handler)                      \
 9:     insn    reg, addr;                              \

-       .section __ex_table,"a";                        \
-       PTR     9b, handler;                            \
+       .section __ex_table,"a";                        \
+       PTR     9b, handler;                            \

        .previous
 
        .macro  f_fill64 dst, offset, val, fixup
        .previous
 
        .macro  f_fill64 dst, offset, val, fixup

diff --git a/arch/mips/lib/r3k_dump_tlb.c b/arch/mips/lib/r3k_dump_tlb.c
index 9cee907975ae0f2f305e157d48a5e8c4e5f92669..91615c2ef0cf969baeff215ca3d8a627e3851d2f 100644 (file)
--- a/arch/mips/lib/r3k_dump_tlb.c
+++ b/arch/mips/lib/r3k_dump_tlb.c
@@ -30,7 +30,7 @@ static void dump_tlb(int first, int last)
                        "tlbr\n\t"
                        "nop\n\t"
                        ".set\treorder");
                        "tlbr\n\t"
                        "nop\n\t"
                        ".set\treorder");

-               entryhi  = read_c0_entryhi();
+               entryhi  = read_c0_entryhi();

                entrylo0 = read_c0_entrylo0();
 
                /* Unused entries have a virtual address of KSEG0.  */
                entrylo0 = read_c0_entrylo0();
 
                /* Unused entries have a virtual address of KSEG0.  */

diff --git a/arch/mips/lib/strncpy_user.S b/arch/mips/lib/strncpy_user.S
index 7201b2ff08c8be6356090b54ab42bb25ba48c9c7..bad5394875031ecb08e668a53b5bbca70649de95 100644 (file)
--- a/arch/mips/lib/strncpy_user.S
+++ b/arch/mips/lib/strncpy_user.S
@@ -23,7 +23,7 @@
 
 /*
  * Ugly special case have to check: we might get passed a user space
 
 /*
  * Ugly special case have to check: we might get passed a user space

- * pointer which wraps into the kernel space.  We don't deal with that.  If
+ * pointer which wraps into the kernel space.  We don't deal with that.         If

  * it happens at most some bytes of the exceptions handlers will be copied.
  */
 
  * it happens at most some bytes of the exceptions handlers will be copied.
  */
 

diff --git a/arch/mips/lib/strnlen_user.S b/arch/mips/lib/strnlen_user.S
index 64457162f7e0c1a564fd19140d3ce88d9f7ae121..beea03c8c0ce823130ab25b421f6874b5a2a13b8 100644 (file)
--- a/arch/mips/lib/strnlen_user.S
+++ b/arch/mips/lib/strnlen_user.S
@@ -21,9 +21,9 @@
  * maximum of a1 or 0 in case of error.
  *
  * Note: for performance reasons we deliberately accept that a user may
  * maximum of a1 or 0 in case of error.
  *
  * Note: for performance reasons we deliberately accept that a user may

- *       make strlen_user and strnlen_user access the first few KSEG0
- *       bytes.  There's nothing secret there.  On 64-bit accessing beyond
- *       the maximum is a tad hairier ...
+ *      make strlen_user and strnlen_user access the first few KSEG0
+ *      bytes.  There's nothing secret there.  On 64-bit accessing beyond
+ *      the maximum is a tad hairier ...

  */
 LEAF(__strnlen_user_asm)
        LONG_L          v0, TI_ADDR_LIMIT($28)  # pointer ok?
  */
 LEAF(__strnlen_user_asm)
        LONG_L          v0, TI_ADDR_LIMIT($28)  # pointer ok?

diff --git a/arch/mips/lib/uncached.c b/arch/mips/lib/uncached.c
index a6d1c77034d5ea351bd140c7ee78fd86cdf515dd..65e3dfc4e58555dec499212a293f2b721749eec1 100644 (file)
--- a/arch/mips/lib/uncached.c
+++ b/arch/mips/lib/uncached.c
@@ -4,7 +4,7 @@
  * for more details.
  *
  * Copyright (C) 2005 Thiemo Seufer
  * for more details.
  *
  * Copyright (C) 2005 Thiemo Seufer

- * Copyright (C) 2005  MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2005  MIPS Technologies, Inc. All rights reserved.

  *     Author: Maciej W. Rozycki <macro@mips.com>
  */
 
  *     Author: Maciej W. Rozycki <macro@mips.com>
  */
 

diff --git a/arch/mips/loongson/Makefile b/arch/mips/loongson/Makefile
index 2b76cb0fb07da0857ab91f45cb68ecef9fdf090e..0dc0055754cd0d96d7f94782e72ed1660ebcef8e 100644 (file)
--- a/arch/mips/loongson/Makefile
+++ b/arch/mips/loongson/Makefile
@@ -8,7 +8,7 @@ obj-$(CONFIG_MACH_LOONGSON) += common/
 # Lemote Fuloong mini-PC (Loongson 2E-based)
 #
 
 # Lemote Fuloong mini-PC (Loongson 2E-based)
 #
 

-obj-$(CONFIG_LEMOTE_FULOONG2E)  += fuloong-2e/
+obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/

 
 #
 # Lemote loongson2f family machines
 
 #
 # Lemote loongson2f family machines

diff --git a/arch/mips/loongson/common/bonito-irq.c b/arch/mips/loongson/common/bonito-irq.c
index f27d7ccca92acd148677b9a340fcb76ffc55991f..cc0e4fd548e64f46642c56eb38cea7b8d6480e7e 100644 (file)
--- a/arch/mips/loongson/common/bonito-irq.c
+++ b/arch/mips/loongson/common/bonito-irq.c
@@ -6,9 +6,9 @@
  * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
  * Author: Fuxin Zhang, zhangfx@lemote.com
  *
  * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
  * Author: Fuxin Zhang, zhangfx@lemote.com
  *

- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your

  *  option) any later version.
  */
 #include <linux/interrupt.h>
  *  option) any later version.
  */
 #include <linux/interrupt.h>

diff --git a/arch/mips/loongson/common/cmdline.c b/arch/mips/loongson/common/cmdline.c
index 353e1d2e41a525660be6be28338de00875e98938..72fed003a536d65e2676204753a6fa764f8e8b29 100644 (file)
--- a/arch/mips/loongson/common/cmdline.c
+++ b/arch/mips/loongson/common/cmdline.c
@@ -12,8 +12,8 @@
  * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/loongson/common/cs5536/cs5536_acc.c b/arch/mips/loongson/common/cs5536/cs5536_acc.c
index b3fd5eab6548cc07388304088314a1c7d790d5ca..ab4d6cc57384e8bc81da9d8791ffa1ce0335d671 100644 (file)
--- a/arch/mips/loongson/common/cs5536/cs5536_acc.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_acc.c
@@ -7,8 +7,8 @@
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/loongson/common/cs5536/cs5536_ehci.c b/arch/mips/loongson/common/cs5536/cs5536_ehci.c
index 5b5cbba699b3fc0238dabc1dc46878e18b14df84..ec2e360267a8e63fddbb2e737da0313889e23da3 100644 (file)
--- a/arch/mips/loongson/common/cs5536/cs5536_ehci.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_ehci.c
@@ -7,8 +7,8 @@
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/loongson/common/cs5536/cs5536_ide.c b/arch/mips/loongson/common/cs5536/cs5536_ide.c
index 681d1291a2c77bc6e7c350443f12af2512558961..a73414d9ee51fbde8198e792449275cbe5fbdf79 100644 (file)
--- a/arch/mips/loongson/common/cs5536/cs5536_ide.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_ide.c
@@ -7,8 +7,8 @@
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/loongson/common/cs5536/cs5536_isa.c b/arch/mips/loongson/common/cs5536/cs5536_isa.c
index 4d9f65abeaffcca0d50ac196594fd7620d2fa290..a6eb2e853d94174f258fd063cd673d7678af6c5c 100644 (file)
--- a/arch/mips/loongson/common/cs5536/cs5536_isa.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_isa.c
@@ -7,8 +7,8 @@
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
index 5d1f48fa1a527a22bde62471e8c9fd3321b11225..c639b9db0012cbee3df5a24e21063c5af9832694 100644 (file)
--- a/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_mfgpt.c
@@ -9,9 +9,9 @@
  *
  * Reference: AMD Geode(TM) CS5536 Companion Device Data Book
  *
  *
  * Reference: AMD Geode(TM) CS5536 Companion Device Data Book
  *

- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your

  *  option) any later version.
  */
 
  *  option) any later version.
  */
 

diff --git a/arch/mips/loongson/common/cs5536/cs5536_ohci.c b/arch/mips/loongson/common/cs5536/cs5536_ohci.c
index bdedf512baf79fb2e97888b2d3c1f756a8c3c705..f7c905e50dc415e21eb258b08a69cc61525bd67b 100644 (file)
--- a/arch/mips/loongson/common/cs5536/cs5536_ohci.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_ohci.c
@@ -7,8 +7,8 @@
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/loongson/common/cs5536/cs5536_pci.c b/arch/mips/loongson/common/cs5536/cs5536_pci.c
index 6dfeab11af08c1f1a048496839059d17384e145e..81bed9d1806192286bc21cf261a7fbc4fcb08f80 100644 (file)
--- a/arch/mips/loongson/common/cs5536/cs5536_pci.c
+++ b/arch/mips/loongson/common/cs5536/cs5536_pci.c
@@ -7,8 +7,8 @@
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * Copyright (C) 2009 Lemote, Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  *
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  *

diff --git a/arch/mips/loongson/common/early_printk.c b/arch/mips/loongson/common/early_printk.c
index a71736f004430fb595313bdeb184b506fb24afaf..ced461b39069747d9cc9b4b2c66d80c3a6a73e7c 100644 (file)
--- a/arch/mips/loongson/common/early_printk.c
+++ b/arch/mips/loongson/common/early_printk.c
@@ -4,9 +4,9 @@
  *  Copyright (c) 2009 Lemote Inc.
  *  Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  *  Copyright (c) 2009 Lemote Inc.
  *  Author: Wu Zhangjin, wuzhangjin@gmail.com
  *

- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your

  *  option) any later version.
  */
 #include <linux/serial_reg.h>
  *  option) any later version.
  */
 #include <linux/serial_reg.h>

diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c
index d93830ad6113619e9f50f4c368bf4cbefd083d2d..0a18fcf2d3723973d87288877bae8785e6c1b2be 100644 (file)
--- a/arch/mips/loongson/common/env.c
+++ b/arch/mips/loongson/common/env.c
@@ -12,8 +12,8 @@
  * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/loongson/common/gpio.c b/arch/mips/loongson/common/gpio.c
index e8a0ffa935b4c72fd63aa5894aa804bce138d13b..21869908aaa48a2862203c7fbf34bae3bc262d04 100644 (file)
--- a/arch/mips/loongson/common/gpio.c
+++ b/arch/mips/loongson/common/gpio.c
@@ -1,7 +1,7 @@
 /*
  *  STLS2F GPIO Support
  *
 /*
  *  STLS2F GPIO Support
  *

- *  Copyright (c) 2008 Richard Liu,  STMicroelectronics  <richard.liu@st.com>
+ *  Copyright (c) 2008 Richard Liu,  STMicroelectronics         <richard.liu@st.com>

  *  Copyright (c) 2008-2010 Arnaud Patard <apatard@mandriva.com>
  *
  *  This program is free software; you can redistribute it and/or modify
  *  Copyright (c) 2008-2010 Arnaud Patard <apatard@mandriva.com>
  *
  *  This program is free software; you can redistribute it and/or modify


@@ -123,13 +123,13 @@ static void ls2f_gpio_set_value(struct gpio_chip *chip,
 }
 
 static struct gpio_chip ls2f_chip = {
 }
 
 static struct gpio_chip ls2f_chip = {

-       .label                  = "ls2f",
-       .direction_input        = ls2f_gpio_direction_input,
-       .get                    = ls2f_gpio_get_value,
-       .direction_output       = ls2f_gpio_direction_output,
-       .set                    = ls2f_gpio_set_value,
-       .base                   = 0,
-       .ngpio                  = STLS2F_N_GPIO,
+       .label                  = "ls2f",
+       .direction_input        = ls2f_gpio_direction_input,
+       .get                    = ls2f_gpio_get_value,
+       .direction_output       = ls2f_gpio_direction_output,
+       .set                    = ls2f_gpio_set_value,
+       .base                   = 0,
+       .ngpio                  = STLS2F_N_GPIO,

 };
 
 static int __init ls2f_gpio_setup(void)
 };
 
 static int __init ls2f_gpio_setup(void)

diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c
index 19d341591254eb1df1061384791d494958f00565..ae7af1fd5d59612b66d3fdff7dd11e6cf54058d6 100644 (file)
--- a/arch/mips/loongson/common/init.c
+++ b/arch/mips/loongson/common/init.c
@@ -2,8 +2,8 @@
  * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/loongson/common/irq.c b/arch/mips/loongson/common/irq.c
index 5897471dedcada602d7e3ea720d1bf909e63d354..687003b19b4546b77e0752031c4fcf918c037454 100644 (file)
--- a/arch/mips/loongson/common/irq.c
+++ b/arch/mips/loongson/common/irq.c
@@ -2,9 +2,9 @@
  * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
  * Author: Fuxin Zhang, zhangfx@lemote.com
  *
  * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
  * Author: Fuxin Zhang, zhangfx@lemote.com
  *

- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your

  *  option) any later version.
  */
 #include <linux/delay.h>
  *  option) any later version.
  */
 #include <linux/delay.h>

diff --git a/arch/mips/loongson/common/machtype.c b/arch/mips/loongson/common/machtype.c
index 2efd5d9dee27192f8a0da79698eb79b5c6e9828c..4becd4f9ef2ea1a8d0e0c0301e5db0fcc40bacb7 100644 (file)
--- a/arch/mips/loongson/common/machtype.c
+++ b/arch/mips/loongson/common/machtype.c
@@ -4,8 +4,8 @@
  *
  * Copyright (c) 2009 Zhang Le <r0bertz@gentoo.org>
  *
  *
  * Copyright (c) 2009 Zhang Le <r0bertz@gentoo.org>
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */


@@ -19,15 +19,15 @@
 #define MACHTYPE_LEN 50
 
 static const char *system_types[] = {
 #define MACHTYPE_LEN 50
 
 static const char *system_types[] = {

-       [MACH_LOONGSON_UNKNOWN]         "unknown loongson machine",
-       [MACH_LEMOTE_FL2E]              "lemote-fuloong-2e-box",
-       [MACH_LEMOTE_FL2F]              "lemote-fuloong-2f-box",
-       [MACH_LEMOTE_ML2F7]             "lemote-mengloong-2f-7inches",
-       [MACH_LEMOTE_YL2F89]            "lemote-yeeloong-2f-8.9inches",
-       [MACH_DEXXON_GDIUM2F10]         "dexxon-gdium-2f",
+       [MACH_LOONGSON_UNKNOWN]         "unknown loongson machine",
+       [MACH_LEMOTE_FL2E]              "lemote-fuloong-2e-box",
+       [MACH_LEMOTE_FL2F]              "lemote-fuloong-2f-box",
+       [MACH_LEMOTE_ML2F7]             "lemote-mengloong-2f-7inches",
+       [MACH_LEMOTE_YL2F89]            "lemote-yeeloong-2f-8.9inches",
+       [MACH_DEXXON_GDIUM2F10]         "dexxon-gdium-2f",

        [MACH_LEMOTE_NAS]               "lemote-nas-2f",
        [MACH_LEMOTE_NAS]               "lemote-nas-2f",

-       [MACH_LEMOTE_LL2F]              "lemote-lynloong-2f",
-       [MACH_LOONGSON_END]             NULL,
+       [MACH_LEMOTE_LL2F]              "lemote-lynloong-2f",
+       [MACH_LOONGSON_END]             NULL,

 };
 
 const char *get_system_type(void)
 };
 
 const char *get_system_type(void)

diff --git a/arch/mips/loongson/common/mem.c b/arch/mips/loongson/common/mem.c
index 30eba60012056f7e547ed0cb1855cab2f51fe016..8626a42f5b948ead7c7e9ffc9518179f0cc29006 100644 (file)
--- a/arch/mips/loongson/common/mem.c
+++ b/arch/mips/loongson/common/mem.c
@@ -1,6 +1,6 @@
 /*
 /*

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/loongson/common/pci.c b/arch/mips/loongson/common/pci.c
index 31d8c5ecd16cec95a42e5cf8def476634f79ca3e..fa77844597211519300b4f38150b3c6331414913 100644 (file)
--- a/arch/mips/loongson/common/pci.c
+++ b/arch/mips/loongson/common/pci.c
@@ -2,9 +2,9 @@
  * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
  * Author: Fuxin Zhang, zhangfx@lemote.com
  *
  * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
  * Author: Fuxin Zhang, zhangfx@lemote.com
  *

- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your

  *  option) any later version.
  */
 #include <linux/pci.h>
  *  option) any later version.
  */
 #include <linux/pci.h>


@@ -13,25 +13,25 @@
 #include <loongson.h>
 
 static struct resource loongson_pci_mem_resource = {
 #include <loongson.h>
 
 static struct resource loongson_pci_mem_resource = {

-       .name   = "pci memory space",
-       .start  = LOONGSON_PCI_MEM_START,
-       .end    = LOONGSON_PCI_MEM_END,
-       .flags  = IORESOURCE_MEM,
+       .name   = "pci memory space",
+       .start  = LOONGSON_PCI_MEM_START,
+       .end    = LOONGSON_PCI_MEM_END,
+       .flags  = IORESOURCE_MEM,

 };
 
 static struct resource loongson_pci_io_resource = {
 };
 
 static struct resource loongson_pci_io_resource = {

-       .name   = "pci io space",
-       .start  = LOONGSON_PCI_IO_START,
-       .end    = IO_SPACE_LIMIT,
-       .flags  = IORESOURCE_IO,
+       .name   = "pci io space",
+       .start  = LOONGSON_PCI_IO_START,
+       .end    = IO_SPACE_LIMIT,
+       .flags  = IORESOURCE_IO,

 };
 
 static struct pci_controller  loongson_pci_controller = {
 };
 
 static struct pci_controller  loongson_pci_controller = {

-       .pci_ops        = &loongson_pci_ops,
-       .io_resource    = &loongson_pci_io_resource,
-       .mem_resource   = &loongson_pci_mem_resource,
-       .mem_offset     = 0x00000000UL,
-       .io_offset      = 0x00000000UL,
+       .pci_ops        = &loongson_pci_ops,
+       .io_resource    = &loongson_pci_io_resource,
+       .mem_resource   = &loongson_pci_mem_resource,
+       .mem_offset     = 0x00000000UL,
+       .io_offset      = 0x00000000UL,

 };
 
 static void __init setup_pcimap(void)
 };
 
 static void __init setup_pcimap(void)


@@ -42,7 +42,7 @@ static void __init setup_pcimap(void)
         * we set pcimap_lo[0,1,2] to map it to pci space[0M,64M], [320M,448M]
         *
         * pcimap: PCI_MAP2  PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0
         * we set pcimap_lo[0,1,2] to map it to pci space[0M,64M], [320M,448M]
         *
         * pcimap: PCI_MAP2  PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0

-        *           [<2G]   [384M,448M] [320M,384M] [0M,64M]
+        *           [<2G]   [384M,448M] [320M,384M] [0M,64M]

         */
        LOONGSON_PCIMAP = LOONGSON_PCIMAP_PCIMAP_2 |
                LOONGSON_PCIMAP_WIN(2, LOONGSON_PCILO2_BASE) |
         */
        LOONGSON_PCIMAP = LOONGSON_PCIMAP_PCIMAP_2 |
                LOONGSON_PCIMAP_WIN(2, LOONGSON_PCILO2_BASE) |

diff --git a/arch/mips/loongson/common/platform.c b/arch/mips/loongson/common/platform.c
index 502b059de42274d21ae94b3606cdb8a5cc39b5e9..0ed38321a9a270d80d43abd52cc1c9c105268989 100644 (file)
--- a/arch/mips/loongson/common/platform.c
+++ b/arch/mips/loongson/common/platform.c
@@ -2,8 +2,8 @@
  * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/loongson/common/reset.c b/arch/mips/loongson/common/reset.c
index 9e10d6225d9bca134931d2da11d0ba63da784972..35c8c64684941603f29c072478fd42b7401a7be8 100644 (file)
--- a/arch/mips/loongson/common/reset.c
+++ b/arch/mips/loongson/common/reset.c
@@ -1,6 +1,6 @@
 /*
 /*

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  *
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  *


@@ -26,9 +26,9 @@ static inline void loongson_reboot(void)
        func = (void *)ioremap_nocache(LOONGSON_BOOT_BASE, 4);
 
        __asm__ __volatile__(
        func = (void *)ioremap_nocache(LOONGSON_BOOT_BASE, 4);
 
        __asm__ __volatile__(

-       "       .set    noat                                            \n"
-       "       jr      %[func]                                         \n"
-       "       .set    at                                              \n"
+       "       .set    noat                                            \n"
+       "       jr      %[func]                                         \n"
+       "       .set    at                                              \n"

        : /* No outputs */
        : [func] "r" (func));
 #endif
        : /* No outputs */
        : [func] "r" (func));
 #endif

diff --git a/arch/mips/loongson/common/serial.c b/arch/mips/loongson/common/serial.c
index 7580873143c84df81f5e6d372de0db9d5ce23364..5f2b78ae97ccb574123827e7c24e999a09a741aa 100644 (file)
--- a/arch/mips/loongson/common/serial.c
+++ b/arch/mips/loongson/common/serial.c
@@ -39,15 +39,15 @@
 }
 
 static struct plat_serial8250_port uart8250_data[][2] = {
 }
 
 static struct plat_serial8250_port uart8250_data[][2] = {

-       [MACH_LOONGSON_UNKNOWN]         {},
-       [MACH_LEMOTE_FL2E]              {PORT(4), {} },
-       [MACH_LEMOTE_FL2F]              {PORT(3), {} },
-       [MACH_LEMOTE_ML2F7]             {PORT_M(3), {} },
-       [MACH_LEMOTE_YL2F89]            {PORT_M(3), {} },
-       [MACH_DEXXON_GDIUM2F10]         {PORT_M(3), {} },
-       [MACH_LEMOTE_NAS]               {PORT_M(3), {} },
-       [MACH_LEMOTE_LL2F]              {PORT(3), {} },
-       [MACH_LOONGSON_END]             {},
+       [MACH_LOONGSON_UNKNOWN]         {},
+       [MACH_LEMOTE_FL2E]              {PORT(4), {} },
+       [MACH_LEMOTE_FL2F]              {PORT(3), {} },
+       [MACH_LEMOTE_ML2F7]             {PORT_M(3), {} },
+       [MACH_LEMOTE_YL2F89]            {PORT_M(3), {} },
+       [MACH_DEXXON_GDIUM2F10]         {PORT_M(3), {} },
+       [MACH_LEMOTE_NAS]               {PORT_M(3), {} },
+       [MACH_LEMOTE_LL2F]              {PORT(3), {} },
+       [MACH_LOONGSON_END]             {},

 };
 
 static struct platform_device uart8250_device = {
 };
 
 static struct platform_device uart8250_device = {

diff --git a/arch/mips/loongson/common/setup.c b/arch/mips/loongson/common/setup.c
index 27d826bc71033d928c32b4fb8c06af3be0ccfa9b..8223f8acfd59b374a02e3b1cd36858f1b47c84b3 100644 (file)
--- a/arch/mips/loongson/common/setup.c
+++ b/arch/mips/loongson/common/setup.c
@@ -2,9 +2,9 @@
  * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
  * Author: Fuxin Zhang, zhangfx@lemote.com
  *
  * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
  * Author: Fuxin Zhang, zhangfx@lemote.com
  *

- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your

  *  option) any later version.
  */
 #include <linux/module.h>
  *  option) any later version.
  */
 #include <linux/module.h>

diff --git a/arch/mips/loongson/common/time.c b/arch/mips/loongson/common/time.c
index 9fdd01f6c56a008eb7af3110100fe0b5b84b8486..262a1f65b05e3638b430021352082b38ae6e5dc9 100644 (file)
--- a/arch/mips/loongson/common/time.c
+++ b/arch/mips/loongson/common/time.c
@@ -5,9 +5,9 @@
  * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *

- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your

  *  option) any later version.
  */
 #include <asm/mc146818-time.h>
  *  option) any later version.
  */
 #include <asm/mc146818-time.h>

diff --git a/arch/mips/loongson/common/uart_base.c b/arch/mips/loongson/common/uart_base.c
index d69ea54bc3d19a00fa4553cdbfa27dcf8272af81..e192ad021edc56cba24b8a90e0be2796fedcce84 100644 (file)
--- a/arch/mips/loongson/common/uart_base.c
+++ b/arch/mips/loongson/common/uart_base.c
@@ -2,8 +2,8 @@
  * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c
index 3cf1fef29f0e76cbdff9828b896b21d5c6b568d4..ef5ec8f3de5f2080588a41ec7ad8a495e4fa070c 100644 (file)
--- a/arch/mips/loongson/fuloong-2e/irq.c
+++ b/arch/mips/loongson/fuloong-2e/irq.c
@@ -2,9 +2,9 @@
  * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
  * Author: Fuxin Zhang, zhangfx@lemote.com
  *
  * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
  * Author: Fuxin Zhang, zhangfx@lemote.com
  *

- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your

  *  option) any later version.
  */
 #include <linux/interrupt.h>
  *  option) any later version.
  */
 #include <linux/interrupt.h>


@@ -48,9 +48,9 @@ static struct irqaction cascade_irqaction = {
 void __init mach_init_irq(void)
 {
        /* init all controller
 void __init mach_init_irq(void)
 {
        /* init all controller

-        *   0-15         ------> i8259 interrupt
-        *   16-23        ------> mips cpu interrupt
-        *   32-63        ------> bonito irq
+        *   0-15         ------> i8259 interrupt
+        *   16-23        ------> mips cpu interrupt
+        *   32-63        ------> bonito irq

         */
 
        /* most bonito irq should be level triggered */
         */
 
        /* most bonito irq should be level triggered */

diff --git a/arch/mips/loongson/fuloong-2e/reset.c b/arch/mips/loongson/fuloong-2e/reset.c
index bc39ec62c8c237828af2fb1397fc69f9dfd5921a..da4d2ae2a1f81a753bcbf76e3fb86da819f5cbc4 100644 (file)
--- a/arch/mips/loongson/fuloong-2e/reset.c
+++ b/arch/mips/loongson/fuloong-2e/reset.c
@@ -4,8 +4,8 @@
  * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/loongson/lemote-2f/ec_kb3310b.h b/arch/mips/loongson/lemote-2f/ec_kb3310b.h
index 1595a21b315bb50239e11ece02411c0a623bee6f..5a3f1860d4d2d85885cc865177729cb6e020180a 100644 (file)
--- a/arch/mips/loongson/lemote-2f/ec_kb3310b.h
+++ b/arch/mips/loongson/lemote-2f/ec_kb3310b.h
@@ -30,141 +30,141 @@ extern sci_handler yeeloong_report_lid_status;
  * 2, fill the PORT_LOW as EC register low part.
  * 3, fill the PORT_DATA as EC register write data or get the data from it.
  */
  * 2, fill the PORT_LOW as EC register low part.
  * 3, fill the PORT_DATA as EC register write data or get the data from it.
  */

-#define        EC_IO_PORT_HIGH 0x0381
-#define        EC_IO_PORT_LOW  0x0382
-#define        EC_IO_PORT_DATA 0x0383
+#define EC_IO_PORT_HIGH 0x0381
+#define EC_IO_PORT_LOW 0x0382
+#define EC_IO_PORT_DATA 0x0383

 
 /*
  * EC delay time is 500us for register and status access
  */
 
 /*
  * EC delay time is 500us for register and status access
  */

-#define        EC_REG_DELAY    500     /* unit : us */
-#define        EC_CMD_TIMEOUT  0x1000
+#define EC_REG_DELAY   500     /* unit : us */
+#define EC_CMD_TIMEOUT 0x1000

 
 /*
  * EC access port for SCI communication
  */
 
 /*
  * EC access port for SCI communication
  */

-#define        EC_CMD_PORT             0x66
-#define        EC_STS_PORT             0x66
-#define        EC_DAT_PORT             0x62
-#define        CMD_INIT_IDLE_MODE      0xdd
-#define        CMD_EXIT_IDLE_MODE      0xdf
-#define        CMD_INIT_RESET_MODE     0xd8
-#define        CMD_REBOOT_SYSTEM       0x8c
-#define        CMD_GET_EVENT_NUM       0x84
-#define        CMD_PROGRAM_PIECE       0xda
+#define EC_CMD_PORT            0x66
+#define EC_STS_PORT            0x66
+#define EC_DAT_PORT            0x62
+#define CMD_INIT_IDLE_MODE     0xdd
+#define CMD_EXIT_IDLE_MODE     0xdf
+#define CMD_INIT_RESET_MODE    0xd8
+#define CMD_REBOOT_SYSTEM      0x8c
+#define CMD_GET_EVENT_NUM      0x84
+#define CMD_PROGRAM_PIECE      0xda

 
 /* temperature & fan registers */
 
 /* temperature & fan registers */

-#define        REG_TEMPERATURE_VALUE   0xF458
-#define        REG_FAN_AUTO_MAN_SWITCH 0xF459
-#define        BIT_FAN_AUTO            0
-#define        BIT_FAN_MANUAL          1
-#define        REG_FAN_CONTROL         0xF4D2
-#define        BIT_FAN_CONTROL_ON      (1 << 0)
-#define        BIT_FAN_CONTROL_OFF     (0 << 0)
-#define        REG_FAN_STATUS          0xF4DA
-#define        BIT_FAN_STATUS_ON       (1 << 0)
-#define        BIT_FAN_STATUS_OFF      (0 << 0)
-#define        REG_FAN_SPEED_HIGH      0xFE22
-#define        REG_FAN_SPEED_LOW       0xFE23
-#define        REG_FAN_SPEED_LEVEL     0xF4CC
+#define REG_TEMPERATURE_VALUE  0xF458
+#define REG_FAN_AUTO_MAN_SWITCH 0xF459
+#define BIT_FAN_AUTO           0
+#define BIT_FAN_MANUAL         1
+#define REG_FAN_CONTROL                0xF4D2
+#define BIT_FAN_CONTROL_ON     (1 << 0)
+#define BIT_FAN_CONTROL_OFF    (0 << 0)
+#define REG_FAN_STATUS         0xF4DA
+#define BIT_FAN_STATUS_ON      (1 << 0)
+#define BIT_FAN_STATUS_OFF     (0 << 0)
+#define REG_FAN_SPEED_HIGH     0xFE22
+#define REG_FAN_SPEED_LOW      0xFE23
+#define REG_FAN_SPEED_LEVEL    0xF4CC

 /* fan speed divider */
 /* fan speed divider */

-#define        FAN_SPEED_DIVIDER       480000  /* (60*1000*1000/62.5/2)*/
+#define FAN_SPEED_DIVIDER      480000  /* (60*1000*1000/62.5/2)*/

 
 /* battery registers */
 
 /* battery registers */

-#define        REG_BAT_DESIGN_CAP_HIGH         0xF77D
-#define        REG_BAT_DESIGN_CAP_LOW          0xF77E
-#define        REG_BAT_FULLCHG_CAP_HIGH        0xF780
-#define        REG_BAT_FULLCHG_CAP_LOW         0xF781
-#define        REG_BAT_DESIGN_VOL_HIGH         0xF782
-#define        REG_BAT_DESIGN_VOL_LOW          0xF783
-#define        REG_BAT_CURRENT_HIGH            0xF784
-#define        REG_BAT_CURRENT_LOW             0xF785
-#define        REG_BAT_VOLTAGE_HIGH            0xF786
-#define        REG_BAT_VOLTAGE_LOW             0xF787
-#define        REG_BAT_TEMPERATURE_HIGH        0xF788
-#define        REG_BAT_TEMPERATURE_LOW         0xF789
-#define        REG_BAT_RELATIVE_CAP_HIGH       0xF492
-#define        REG_BAT_RELATIVE_CAP_LOW        0xF493
-#define        REG_BAT_VENDOR                  0xF4C4
-#define        FLAG_BAT_VENDOR_SANYO           0x01
-#define        FLAG_BAT_VENDOR_SIMPLO          0x02
-#define        REG_BAT_CELL_COUNT              0xF4C6
-#define        FLAG_BAT_CELL_3S1P              0x03
-#define        FLAG_BAT_CELL_3S2P              0x06
-#define        REG_BAT_CHARGE                  0xF4A2
-#define        FLAG_BAT_CHARGE_DISCHARGE       0x01
-#define        FLAG_BAT_CHARGE_CHARGE          0x02
-#define        FLAG_BAT_CHARGE_ACPOWER         0x00
-#define        REG_BAT_STATUS                  0xF4B0
-#define        BIT_BAT_STATUS_LOW              (1 << 5)
-#define        BIT_BAT_STATUS_DESTROY          (1 << 2)
-#define        BIT_BAT_STATUS_FULL             (1 << 1)
-#define        BIT_BAT_STATUS_IN               (1 << 0)
-#define        REG_BAT_CHARGE_STATUS           0xF4B1
-#define        BIT_BAT_CHARGE_STATUS_OVERTEMP  (1 << 2)
-#define        BIT_BAT_CHARGE_STATUS_PRECHG    (1 << 1)
-#define        REG_BAT_STATE                   0xF482
-#define        BIT_BAT_STATE_CHARGING          (1 << 1)
-#define        BIT_BAT_STATE_DISCHARGING       (1 << 0)
-#define        REG_BAT_POWER                   0xF440
-#define        BIT_BAT_POWER_S3                (1 << 2)
-#define        BIT_BAT_POWER_ON                (1 << 1)
-#define        BIT_BAT_POWER_ACIN              (1 << 0)
+#define REG_BAT_DESIGN_CAP_HIGH                0xF77D
+#define REG_BAT_DESIGN_CAP_LOW         0xF77E
+#define REG_BAT_FULLCHG_CAP_HIGH       0xF780
+#define REG_BAT_FULLCHG_CAP_LOW                0xF781
+#define REG_BAT_DESIGN_VOL_HIGH                0xF782
+#define REG_BAT_DESIGN_VOL_LOW         0xF783
+#define REG_BAT_CURRENT_HIGH           0xF784
+#define REG_BAT_CURRENT_LOW            0xF785
+#define REG_BAT_VOLTAGE_HIGH           0xF786
+#define REG_BAT_VOLTAGE_LOW            0xF787
+#define REG_BAT_TEMPERATURE_HIGH       0xF788
+#define REG_BAT_TEMPERATURE_LOW                0xF789
+#define REG_BAT_RELATIVE_CAP_HIGH      0xF492
+#define REG_BAT_RELATIVE_CAP_LOW       0xF493
+#define REG_BAT_VENDOR                 0xF4C4
+#define FLAG_BAT_VENDOR_SANYO          0x01
+#define FLAG_BAT_VENDOR_SIMPLO         0x02
+#define REG_BAT_CELL_COUNT             0xF4C6
+#define FLAG_BAT_CELL_3S1P             0x03
+#define FLAG_BAT_CELL_3S2P             0x06
+#define REG_BAT_CHARGE                 0xF4A2
+#define FLAG_BAT_CHARGE_DISCHARGE      0x01
+#define FLAG_BAT_CHARGE_CHARGE         0x02
+#define FLAG_BAT_CHARGE_ACPOWER                0x00
+#define REG_BAT_STATUS                 0xF4B0
+#define BIT_BAT_STATUS_LOW             (1 << 5)
+#define BIT_BAT_STATUS_DESTROY         (1 << 2)
+#define BIT_BAT_STATUS_FULL            (1 << 1)
+#define BIT_BAT_STATUS_IN              (1 << 0)
+#define REG_BAT_CHARGE_STATUS          0xF4B1
+#define BIT_BAT_CHARGE_STATUS_OVERTEMP (1 << 2)
+#define BIT_BAT_CHARGE_STATUS_PRECHG   (1 << 1)
+#define REG_BAT_STATE                  0xF482
+#define BIT_BAT_STATE_CHARGING         (1 << 1)
+#define BIT_BAT_STATE_DISCHARGING      (1 << 0)
+#define REG_BAT_POWER                  0xF440
+#define BIT_BAT_POWER_S3               (1 << 2)
+#define BIT_BAT_POWER_ON               (1 << 1)
+#define BIT_BAT_POWER_ACIN             (1 << 0)

 
 /* other registers */
 /* Audio: rd/wr */
 
 /* other registers */
 /* Audio: rd/wr */

-#define        REG_AUDIO_VOLUME        0xF46C
-#define        REG_AUDIO_MUTE          0xF4E7
-#define        REG_AUDIO_BEEP          0xF4D0
+#define REG_AUDIO_VOLUME       0xF46C
+#define REG_AUDIO_MUTE         0xF4E7
+#define REG_AUDIO_BEEP         0xF4D0

 /* USB port power or not: rd/wr */
 /* USB port power or not: rd/wr */

-#define        REG_USB0_FLAG           0xF461
-#define        REG_USB1_FLAG           0xF462
-#define        REG_USB2_FLAG           0xF463
-#define        BIT_USB_FLAG_ON         1
-#define        BIT_USB_FLAG_OFF        0
+#define REG_USB0_FLAG          0xF461
+#define REG_USB1_FLAG          0xF462
+#define REG_USB2_FLAG          0xF463
+#define BIT_USB_FLAG_ON                1
+#define BIT_USB_FLAG_OFF       0

 /* LID */
 /* LID */

-#define        REG_LID_DETECT          0xF4BD
-#define        BIT_LID_DETECT_ON       1
-#define        BIT_LID_DETECT_OFF      0
+#define REG_LID_DETECT         0xF4BD
+#define BIT_LID_DETECT_ON      1
+#define BIT_LID_DETECT_OFF     0

 /* CRT */
 /* CRT */

-#define        REG_CRT_DETECT          0xF4AD
-#define        BIT_CRT_DETECT_PLUG     1
-#define        BIT_CRT_DETECT_UNPLUG   0
+#define REG_CRT_DETECT         0xF4AD
+#define BIT_CRT_DETECT_PLUG    1
+#define BIT_CRT_DETECT_UNPLUG  0

 /* LCD backlight brightness adjust: 9 levels */
 /* LCD backlight brightness adjust: 9 levels */

-#define        REG_DISPLAY_BRIGHTNESS  0xF4F5
+#define REG_DISPLAY_BRIGHTNESS 0xF4F5

 /* Black screen Status */
 /* Black screen Status */

-#define        BIT_DISPLAY_LCD_ON      1
-#define        BIT_DISPLAY_LCD_OFF     0
+#define BIT_DISPLAY_LCD_ON     1
+#define BIT_DISPLAY_LCD_OFF    0

 /* LCD backlight control: off/restore */
 /* LCD backlight control: off/restore */

-#define        REG_BACKLIGHT_CTRL      0xF7BD
-#define        BIT_BACKLIGHT_ON        1
-#define        BIT_BACKLIGHT_OFF       0
+#define REG_BACKLIGHT_CTRL     0xF7BD
+#define BIT_BACKLIGHT_ON       1
+#define BIT_BACKLIGHT_OFF      0

 /* Reset the machine auto-clear: rd/wr */
 /* Reset the machine auto-clear: rd/wr */

-#define        REG_RESET               0xF4EC
-#define        BIT_RESET_ON            1
+#define REG_RESET              0xF4EC
+#define BIT_RESET_ON           1

 /* Light the led: rd/wr */
 /* Light the led: rd/wr */

-#define        REG_LED                 0xF4C8
-#define        BIT_LED_RED_POWER       (1 << 0)
-#define        BIT_LED_ORANGE_POWER    (1 << 1)
-#define        BIT_LED_GREEN_CHARGE    (1 << 2)
-#define        BIT_LED_RED_CHARGE      (1 << 3)
-#define        BIT_LED_NUMLOCK         (1 << 4)
+#define REG_LED                        0xF4C8
+#define BIT_LED_RED_POWER      (1 << 0)
+#define BIT_LED_ORANGE_POWER   (1 << 1)
+#define BIT_LED_GREEN_CHARGE   (1 << 2)
+#define BIT_LED_RED_CHARGE     (1 << 3)
+#define BIT_LED_NUMLOCK                (1 << 4)

 /* Test led mode, all led on/off */
 /* Test led mode, all led on/off */

-#define        REG_LED_TEST            0xF4C2
-#define        BIT_LED_TEST_IN         1
-#define        BIT_LED_TEST_OUT        0
+#define REG_LED_TEST           0xF4C2
+#define BIT_LED_TEST_IN                1
+#define BIT_LED_TEST_OUT       0

 /* Camera on/off */
 /* Camera on/off */

-#define        REG_CAMERA_STATUS       0xF46A
-#define        BIT_CAMERA_STATUS_ON    1
-#define        BIT_CAMERA_STATUS_OFF   0
-#define        REG_CAMERA_CONTROL      0xF7B7
-#define        BIT_CAMERA_CONTROL_OFF  0
-#define        BIT_CAMERA_CONTROL_ON   1
+#define REG_CAMERA_STATUS      0xF46A
+#define BIT_CAMERA_STATUS_ON   1
+#define BIT_CAMERA_STATUS_OFF  0
+#define REG_CAMERA_CONTROL     0xF7B7
+#define BIT_CAMERA_CONTROL_OFF 0
+#define BIT_CAMERA_CONTROL_ON  1

 /* Wlan Status */
 /* Wlan Status */

-#define        REG_WLAN                0xF4FA
-#define        BIT_WLAN_ON             1
-#define        BIT_WLAN_OFF            0
-#define        REG_DISPLAY_LCD         0xF79F
+#define REG_WLAN               0xF4FA
+#define BIT_WLAN_ON            1
+#define BIT_WLAN_OFF           0
+#define REG_DISPLAY_LCD                0xF79F

 
 /* SCI Event Number from EC */
 enum {
 
 /* SCI Event Number from EC */
 enum {

diff --git a/arch/mips/loongson/lemote-2f/irq.c b/arch/mips/loongson/lemote-2f/irq.c
index 14b081841b6b0d7ed2117917dc2306cfbf46ce0d..6f8682e44483dcfbcb51c1202096112922e05d35 100644 (file)
--- a/arch/mips/loongson/lemote-2f/irq.c
+++ b/arch/mips/loongson/lemote-2f/irq.c
@@ -2,9 +2,9 @@
  * Copyright (C) 2007 Lemote Inc.
  * Author: Fuxin Zhang, zhangfx@lemote.com
  *
  * Copyright (C) 2007 Lemote Inc.
  * Author: Fuxin Zhang, zhangfx@lemote.com
  *

- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your

  *  option) any later version.
  */
 
  *  option) any later version.
  */
 


@@ -18,10 +18,10 @@
 #include <loongson.h>
 #include <machine.h>
 
 #include <loongson.h>
 #include <machine.h>
 

-#define LOONGSON_TIMER_IRQ     (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
-#define LOONGSON_NORTH_BRIDGE_IRQ      (MIPS_CPU_IRQ_BASE + 6) /* bonito */
-#define LOONGSON_UART_IRQ      (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
-#define LOONGSON_SOUTH_BRIDGE_IRQ      (MIPS_CPU_IRQ_BASE + 2) /* i8259 */
+#define LOONGSON_TIMER_IRQ     (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
+#define LOONGSON_NORTH_BRIDGE_IRQ      (MIPS_CPU_IRQ_BASE + 6) /* bonito */
+#define LOONGSON_UART_IRQ      (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
+#define LOONGSON_SOUTH_BRIDGE_IRQ      (MIPS_CPU_IRQ_BASE + 2) /* i8259 */

 
 #define LOONGSON_INT_BIT_INT0          (1 << 11)
 #define LOONGSON_INT_BIT_INT1          (1 << 12)
 
 #define LOONGSON_INT_BIT_INT0          (1 << 11)
 #define LOONGSON_INT_BIT_INT1          (1 << 12)


@@ -108,9 +108,9 @@ struct irqaction cascade_irqaction = {
 void __init mach_init_irq(void)
 {
        /* init all controller
 void __init mach_init_irq(void)
 {
        /* init all controller

-        *   0-15         ------> i8259 interrupt
-        *   16-23        ------> mips cpu interrupt
-        *   32-63        ------> bonito irq
+        *   0-15         ------> i8259 interrupt
+        *   16-23        ------> mips cpu interrupt
+        *   32-63        ------> bonito irq

         */
 
        /* setup cs5536 as high level trigger */
         */
 
        /* setup cs5536 as high level trigger */

diff --git a/arch/mips/loongson/lemote-2f/machtype.c b/arch/mips/loongson/lemote-2f/machtype.c
index e860a2705c279ab480afb7b92d9e9cbe9838806e..b55e6eece5e06688730e2d55bca773eff5f432e9 100644 (file)
--- a/arch/mips/loongson/lemote-2f/machtype.c
+++ b/arch/mips/loongson/lemote-2f/machtype.c
@@ -2,8 +2,8 @@
  * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */


@@ -22,11 +22,11 @@ void __init mach_prom_init_machtype(void)
         * machines, this will help the users a lot.
         *
         * If no "machtype=" passed, get machine type from "PMON_VER=".
         * machines, this will help the users a lot.
         *
         * If no "machtype=" passed, get machine type from "PMON_VER=".

-        *      PMON_VER=LM8089         Lemote 8.9'' netbook
-        *               LM8101         Lemote 10.1'' netbook
-        *      (The above two netbooks have the same kernel support)
-        *               LM6XXX         Lemote FuLoong(2F) box series
-        *               LM9XXX         Lemote LynLoong PC series
+        *      PMON_VER=LM8089         Lemote 8.9'' netbook
+        *               LM8101         Lemote 10.1'' netbook
+        *      (The above two netbooks have the same kernel support)
+        *               LM6XXX         Lemote FuLoong(2F) box series
+        *               LM9XXX         Lemote LynLoong PC series

         */
        if (strstr(arcs_cmdline, "PMON_VER=LM")) {
                if (strstr(arcs_cmdline, "PMON_VER=LM8"))
         */
        if (strstr(arcs_cmdline, "PMON_VER=LM")) {
                if (strstr(arcs_cmdline, "PMON_VER=LM8"))

diff --git a/arch/mips/loongson/lemote-2f/reset.c b/arch/mips/loongson/lemote-2f/reset.c
index 36020a07e18036f001ad88ef2f216f96980ca9fd..90962a3a1731eca27f3b41c3dcdfa3567a9ad8e6 100644 (file)
--- a/arch/mips/loongson/lemote-2f/reset.c
+++ b/arch/mips/loongson/lemote-2f/reset.c
@@ -5,8 +5,8 @@
  * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *
  * Copyright (C) 2009 Lemote Inc.
  * Author: Wu Zhangjin, wuzhangjin@gmail.com
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */


@@ -90,9 +90,9 @@ void ml2f_reboot(void)
 #define EC_SHUTDOWN_IO_PORT_HIGH 0xff2d
 #define EC_SHUTDOWN_IO_PORT_LOW         0xff2e
 #define EC_SHUTDOWN_IO_PORT_DATA 0xff2f
 #define EC_SHUTDOWN_IO_PORT_HIGH 0xff2d
 #define EC_SHUTDOWN_IO_PORT_LOW         0xff2e
 #define EC_SHUTDOWN_IO_PORT_DATA 0xff2f

-#define REG_SHUTDOWN_HIGH        0xFC
-#define REG_SHUTDOWN_LOW         0x29
-#define BIT_SHUTDOWN_ON          (1 << 1)
+#define REG_SHUTDOWN_HIGH       0xFC
+#define REG_SHUTDOWN_LOW        0x29
+#define BIT_SHUTDOWN_ON                 (1 << 1)

 
 static void ml2f_shutdown(void)
 {
 
 static void ml2f_shutdown(void)
 {

diff --git a/arch/mips/loongson1/Platform b/arch/mips/loongson1/Platform
index 99bdefe627af49be8026004c087c6d4c13aced8b..11863441dea3348f2da81cd94ef98ecca1c4cacb 100644 (file)
--- a/arch/mips/loongson1/Platform
+++ b/arch/mips/loongson1/Platform
@@ -1,4 +1,4 @@
-cflags-$(CONFIG_CPU_LOONGSON1)  += \
+cflags-$(CONFIG_CPU_LOONGSON1) += \

        $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
        -Wa,-mips32r2 -Wa,--trap
 
        $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
        -Wa,-mips32r2 -Wa,--trap
 

diff --git a/arch/mips/loongson1/common/clock.c b/arch/mips/loongson1/common/clock.c
index 07133defa148dbbe2da9216a66fae3b09dabaefd..b4437f19c3d93e67b32da66385cd6ab17bd9d0cc 100644 (file)
--- a/arch/mips/loongson1/common/clock.c
+++ b/arch/mips/loongson1/common/clock.c
@@ -1,8 +1,8 @@
 /*
  * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
  *
 /*
  * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/loongson1/common/irq.c b/arch/mips/loongson1/common/irq.c
index 41bc8ffe7bba2d38465762ab6193200671c2e7f1..455a7704a90f98a73820e6fa691e991faa2baa60 100644 (file)
--- a/arch/mips/loongson1/common/irq.c
+++ b/arch/mips/loongson1/common/irq.c
@@ -1,8 +1,8 @@
 /*
  * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
  *
 /*
  * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/loongson1/common/platform.c b/arch/mips/loongson1/common/platform.c
index 69dad4cfaaf42a9d17b61004fc5805138d1f7a95..fdf8cb5987a45db021c3bd14aa0dfd8fc4761a0f 100644 (file)
--- a/arch/mips/loongson1/common/platform.c
+++ b/arch/mips/loongson1/common/platform.c
@@ -1,8 +1,8 @@
 /*
  * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
  *
 /*
  * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */


@@ -23,7 +23,7 @@
                .mapbase        = LS1X_UART ## _id ## _BASE,    \
                .irq            = LS1X_UART ## _id ## _IRQ,     \
                .iotype         = UPIO_MEM,                     \
                .mapbase        = LS1X_UART ## _id ## _BASE,    \
                .irq            = LS1X_UART ## _id ## _IRQ,     \
                .iotype         = UPIO_MEM,                     \

-               .flags          = UPF_IOREMAP | UPF_FIXED_TYPE, \
+               .flags          = UPF_IOREMAP | UPF_FIXED_TYPE, \

                .type           = PORT_16550A,                  \
        }
 
                .type           = PORT_16550A,                  \
        }
 

diff --git a/arch/mips/loongson1/common/prom.c b/arch/mips/loongson1/common/prom.c
index 1f8e49f9886d0e9fda4545bbd2e600b5d34d23bb..2dd9c5648d79d4b5463496589198322c272dbff3 100644 (file)
--- a/arch/mips/loongson1/common/prom.c
+++ b/arch/mips/loongson1/common/prom.c
@@ -3,8 +3,8 @@
  *
  * Modified from arch/mips/pnx833x/common/prom.c.
  *
  *
  * Modified from arch/mips/pnx833x/common/prom.c.
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/loongson1/common/reset.c b/arch/mips/loongson1/common/reset.c
index fb979a784ecad132ecb3445e3bdd35b8275801b6..d4f610f9604a27296a685ea1455bbd18717b48be 100644 (file)
--- a/arch/mips/loongson1/common/reset.c
+++ b/arch/mips/loongson1/common/reset.c
@@ -1,8 +1,8 @@
 /*
  * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
  *
 /*
  * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/loongson1/common/setup.c b/arch/mips/loongson1/common/setup.c
index 62128cc27e68360dda9eb70b9035f7b9b5e3edb8..62f41afee241e7a4df305725bac9659c0a796bea 100644 (file)
--- a/arch/mips/loongson1/common/setup.c
+++ b/arch/mips/loongson1/common/setup.c
@@ -1,8 +1,8 @@
 /*
  * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
  *
 /*
  * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/loongson1/ls1b/board.c b/arch/mips/loongson1/ls1b/board.c
index 1fbd5264f667594efbc923fa2e428213d6bbd242..b26b10dac70af59c6e1a021e34f4aa77014f97f2 100644 (file)
--- a/arch/mips/loongson1/ls1b/board.c
+++ b/arch/mips/loongson1/ls1b/board.c
@@ -1,8 +1,8 @@
 /*
  * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
  *
 /*
  * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com>
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 47c77e7ffbf89102a07c19e900e29e4dd4cf510b..afb5a0bcf7a5a524c4fe75450be559e8402c68d4 100644 (file)
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -169,7 +169,7 @@ static int isBranchInstr(mips_instruction * i)
 
 /*
  * In the Linux kernel, we support selection of FPR format on the
 
 /*
  * In the Linux kernel, we support selection of FPR format on the

- * basis of the Status.FR bit.  If an FPU is not present, the FR bit
+ * basis of the Status.FR bit. If an FPU is not present, the FR bit

  * is hardwired to zero, which would imply a 32-bit FPU even for
  * 64-bit CPUs so we rather look at TIF_32BIT_REGS.
  * FPU emu is slow and bulky and optimizing this function offers fairly
  * is hardwired to zero, which would imply a 32-bit FPU even for
  * 64-bit CPUs so we rather look at TIF_32BIT_REGS.
  * FPU emu is slow and bulky and optimizing this function offers fairly


@@ -234,7 +234,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
        if (xcp->cp0_cause & CAUSEF_BD) {
                /*
                 * The instruction to be emulated is in a branch delay slot
        if (xcp->cp0_cause & CAUSEF_BD) {
                /*
                 * The instruction to be emulated is in a branch delay slot

-                * which means that we have to  emulate the branch instruction
+                * which means that we have to  emulate the branch instruction

                 * BEFORE we do the cop1 instruction.
                 *
                 * This branch could be a COP1 branch, but in that case we
                 * BEFORE we do the cop1 instruction.
                 *
                 * This branch could be a COP1 branch, but in that case we


@@ -1335,8 +1335,8 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                else {
                        /*
                         * The 'ieee754_csr' is an alias of
                else {
                        /*
                         * The 'ieee754_csr' is an alias of

-                        * ctx->fcr31.  No need to copy ctx->fcr31 to
-                        * ieee754_csr.  But ieee754_csr.rm is ieee
+                        * ctx->fcr31.  No need to copy ctx->fcr31 to
+                        * ieee754_csr.  But ieee754_csr.rm is ieee

                         * library modes. (not mips rounding mode)
                         */
                        /* convert to ieee library modes */
                         * library modes. (not mips rounding mode)
                         */
                        /* convert to ieee library modes */

diff --git a/arch/mips/math-emu/dp_add.c b/arch/mips/math-emu/dp_add.c
index b422fcad852a33811d7564d78f3ae3ed9b329e62..c57c8adc42c46aed52bfa6599b48f66b919080d0 100644 (file)
--- a/arch/mips/math-emu/dp_add.c
+++ b/arch/mips/math-emu/dp_add.c
@@ -153,7 +153,7 @@ ieee754dp ieee754dp_add(ieee754dp x, ieee754dp y)
                xe = xe;
                xs = xs;
 
                xe = xe;
                xs = xs;
 

-               if (xm >> (DP_MBITS + 1 + 3)) { /* carry out */
+               if (xm >> (DP_MBITS + 1 + 3)) { /* carry out */

                        xm = XDPSRS1(xm);
                        xe++;
                }
                        xm = XDPSRS1(xm);
                        xe++;
                }

diff --git a/arch/mips/math-emu/dp_sqrt.c b/arch/mips/math-emu/dp_sqrt.c
index a2a51b87ae8fba962c3a4d0cecdb9173a4e52720..b874d60a942bd0fde028acd1c82f64546ee701a5 100644 (file)
--- a/arch/mips/math-emu/dp_sqrt.c
+++ b/arch/mips/math-emu/dp_sqrt.c
@@ -87,7 +87,7 @@ ieee754dp ieee754dp_sqrt(ieee754dp x)
        if (xe > 512) {         /* x > 2**-512? */
                xe -= 512;      /* x = x / 2**512 */
                scalx += 256;
        if (xe > 512) {         /* x > 2**-512? */
                xe -= 512;      /* x = x / 2**512 */
                scalx += 256;

-       } else if (xe < -512) { /* x < 2**-512? */
+       } else if (xe < -512) { /* x < 2**-512? */

                xe += 512;      /* x = x * 2**512 */
                scalx -= 256;
        }
                xe += 512;      /* x = x * 2**512 */
                scalx -= 256;
        }


@@ -108,13 +108,13 @@ ieee754dp ieee754dp_sqrt(ieee754dp x)
        y.bits &= 0xffffffff00000000LL;
 
        /* triple to almost 56 sig. bits: y ~= sqrt(x) to within 1 ulp */
        y.bits &= 0xffffffff00000000LL;
 
        /* triple to almost 56 sig. bits: y ~= sqrt(x) to within 1 ulp */

-       /* t=y*y; z=t;  pt[n0]+=0x00100000; t+=z; z=(x-z)*y; */
+       /* t=y*y; z=t;  pt[n0]+=0x00100000; t+=z; z=(x-z)*y; */

        z = t = ieee754dp_mul(y, y);
        t.parts.bexp += 0x001;
        t = ieee754dp_add(t, z);
        z = ieee754dp_mul(ieee754dp_sub(x, z), y);
 
        z = t = ieee754dp_mul(y, y);
        t.parts.bexp += 0x001;
        t = ieee754dp_add(t, z);
        z = ieee754dp_mul(ieee754dp_sub(x, z), y);
 

-       /* t=z/(t+x) ;  pt[n0]+=0x00100000; y+=t; */
+       /* t=z/(t+x) ;  pt[n0]+=0x00100000; y+=t; */

        t = ieee754dp_div(z, ieee754dp_add(t, x));
        t.parts.bexp += 0x001;
        y = ieee754dp_add(y, t);
        t = ieee754dp_div(z, ieee754dp_add(t, x));
        t.parts.bexp += 0x001;
        y = ieee754dp_add(y, t);

diff --git a/arch/mips/math-emu/dp_sub.c b/arch/mips/math-emu/dp_sub.c
index 0de098cbc77bee6dde427f6a7796e314c348b27e..91e0a4b5cbc76ebad10302781fcf753d09bec6dd 100644 (file)
--- a/arch/mips/math-emu/dp_sub.c
+++ b/arch/mips/math-emu/dp_sub.c
@@ -158,7 +158,7 @@ ieee754dp ieee754dp_sub(ieee754dp x, ieee754dp y)
                xe = xe;
                xs = xs;
 
                xe = xe;
                xs = xs;
 

-               if (xm >> (DP_MBITS + 1 + 3)) { /* carry out */
+               if (xm >> (DP_MBITS + 1 + 3)) { /* carry out */

                        xm = XDPSRS1(xm);       /* shift preserving sticky */
                        xe++;
                }
                        xm = XDPSRS1(xm);       /* shift preserving sticky */
                        xe++;
                }

diff --git a/arch/mips/math-emu/ieee754.c b/arch/mips/math-emu/ieee754.c
index 30554e1c67b40d3fb093ea2d97ab680f1ac6f60b..0015cf1989dad3f87e823a0f6b2d1261c123c7ff 100644 (file)
--- a/arch/mips/math-emu/ieee754.c
+++ b/arch/mips/math-emu/ieee754.c
@@ -56,21 +56,21 @@
 #endif
 
 const struct ieee754dp_konst __ieee754dp_spcvals[] = {
 #endif
 
 const struct ieee754dp_konst __ieee754dp_spcvals[] = {

-       DPSTR(0, DP_EMIN - 1 + DP_EBIAS, 0, 0), /* + zero   */
-       DPSTR(1, DP_EMIN - 1 + DP_EBIAS, 0, 0), /* - zero   */
+       DPSTR(0, DP_EMIN - 1 + DP_EBIAS, 0, 0), /* + zero   */
+       DPSTR(1, DP_EMIN - 1 + DP_EBIAS, 0, 0), /* - zero   */

        DPSTR(0, DP_EBIAS, 0, 0),       /* + 1.0   */
        DPSTR(1, DP_EBIAS, 0, 0),       /* - 1.0   */
        DPSTR(0, 3 + DP_EBIAS, 0x40000, 0),     /* + 10.0   */
        DPSTR(1, 3 + DP_EBIAS, 0x40000, 0),     /* - 10.0   */
        DPSTR(0, DP_EBIAS, 0, 0),       /* + 1.0   */
        DPSTR(1, DP_EBIAS, 0, 0),       /* - 1.0   */
        DPSTR(0, 3 + DP_EBIAS, 0x40000, 0),     /* + 10.0   */
        DPSTR(1, 3 + DP_EBIAS, 0x40000, 0),     /* - 10.0   */

-       DPSTR(0, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* + infinity */
-       DPSTR(1, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* - infinity */
+       DPSTR(0, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* + infinity */
+       DPSTR(1, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* - infinity */

        DPSTR(0, DP_EMAX+1+DP_EBIAS, 0x7FFFF, 0xFFFFFFFF), /* + indef quiet Nan */
        DPSTR(0, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF),      /* + max */
        DPSTR(1, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF),      /* - max */
        DPSTR(0, DP_EMIN + DP_EBIAS, 0, 0),     /* + min normal */
        DPSTR(1, DP_EMIN + DP_EBIAS, 0, 0),     /* - min normal */
        DPSTR(0, DP_EMAX+1+DP_EBIAS, 0x7FFFF, 0xFFFFFFFF), /* + indef quiet Nan */
        DPSTR(0, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF),      /* + max */
        DPSTR(1, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF),      /* - max */
        DPSTR(0, DP_EMIN + DP_EBIAS, 0, 0),     /* + min normal */
        DPSTR(1, DP_EMIN + DP_EBIAS, 0, 0),     /* - min normal */

-       DPSTR(0, DP_EMIN - 1 + DP_EBIAS, 0, 1), /* + min denormal */
-       DPSTR(1, DP_EMIN - 1 + DP_EBIAS, 0, 1), /* - min denormal */
+       DPSTR(0, DP_EMIN - 1 + DP_EBIAS, 0, 1), /* + min denormal */
+       DPSTR(1, DP_EMIN - 1 + DP_EBIAS, 0, 1), /* - min denormal */

        DPSTR(0, 31 + DP_EBIAS, 0, 0),  /* + 1.0e31 */
        DPSTR(0, 63 + DP_EBIAS, 0, 0),  /* + 1.0e63 */
 };
        DPSTR(0, 31 + DP_EBIAS, 0, 0),  /* + 1.0e31 */
        DPSTR(0, 63 + DP_EBIAS, 0, 0),  /* + 1.0e63 */
 };


@@ -84,9 +84,9 @@ const struct ieee754sp_konst __ieee754sp_spcvals[] = {
        SPSTR(1, 3 + SP_EBIAS, 0x200000),       /* - 10.0   */
        SPSTR(0, SP_EMAX + 1 + SP_EBIAS, 0),    /* + infinity */
        SPSTR(1, SP_EMAX + 1 + SP_EBIAS, 0),    /* - infinity */
        SPSTR(1, 3 + SP_EBIAS, 0x200000),       /* - 10.0   */
        SPSTR(0, SP_EMAX + 1 + SP_EBIAS, 0),    /* + infinity */
        SPSTR(1, SP_EMAX + 1 + SP_EBIAS, 0),    /* - infinity */

-       SPSTR(0, SP_EMAX+1+SP_EBIAS, 0x3FFFFF),     /* + indef quiet Nan  */
-       SPSTR(0, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* + max normal */
-       SPSTR(1, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* - max normal */
+       SPSTR(0, SP_EMAX+1+SP_EBIAS, 0x3FFFFF),     /* + indef quiet Nan  */
+       SPSTR(0, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* + max normal */
+       SPSTR(1, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* - max normal */

        SPSTR(0, SP_EMIN + SP_EBIAS, 0),        /* + min normal */
        SPSTR(1, SP_EMIN + SP_EBIAS, 0),        /* - min normal */
        SPSTR(0, SP_EMIN - 1 + SP_EBIAS, 1),    /* + min denormal */
        SPSTR(0, SP_EMIN + SP_EBIAS, 0),        /* + min normal */
        SPSTR(1, SP_EMIN + SP_EBIAS, 0),        /* - min normal */
        SPSTR(0, SP_EMIN - 1 + SP_EBIAS, 1),    /* + min denormal */

diff --git a/arch/mips/math-emu/ieee754dp.c b/arch/mips/math-emu/ieee754dp.c
index 080b5ca03fc684430969c7995847ddefa464f86a..068e56be8de91227c3ec8c65ca2d5c785e3c2360 100644 (file)
--- a/arch/mips/math-emu/ieee754dp.c
+++ b/arch/mips/math-emu/ieee754dp.c
@@ -116,7 +116,7 @@ static u64 get_rounding(int sn, u64 xm)
                                xm += 0x8;
                        break;
                case IEEE754_RD:        /* toward -Infinity */
                                xm += 0x8;
                        break;
                case IEEE754_RD:        /* toward -Infinity */

-                       if (sn) /* ?? */
+                       if (sn) /* ?? */

                                xm += 0x8;
                        break;
                }
                                xm += 0x8;
                        break;
                }

diff --git a/arch/mips/math-emu/ieee754int.h b/arch/mips/math-emu/ieee754int.h
index 2a7d43f4f161c07b4a9f6d85cca363d545fe7d85..4b6c6fb353047e1b9b7185a0cda2e7e95b866d51 100644 (file)
--- a/arch/mips/math-emu/ieee754int.h
+++ b/arch/mips/math-emu/ieee754int.h
@@ -56,7 +56,7 @@
 
 #define CLPAIR(x, y)   ((x)*6+(y))
 
 
 #define CLPAIR(x, y)   ((x)*6+(y))
 

-#define CLEARCX        \
+#define CLEARCX \

   (ieee754_csr.cx = 0)
 
 #define SETCX(x) \
   (ieee754_csr.cx = 0)
 
 #define SETCX(x) \

diff --git a/arch/mips/math-emu/ieee754sp.c b/arch/mips/math-emu/ieee754sp.c
index 271d00d6113a5d35d68032f7358a46f7549008da..15d1e36cfe64a26c62b10a78133cd9a8415ff9ae 100644 (file)
--- a/arch/mips/math-emu/ieee754sp.c
+++ b/arch/mips/math-emu/ieee754sp.c
@@ -117,7 +117,7 @@ static unsigned get_rounding(int sn, unsigned xm)
                                xm += 0x8;
                        break;
                case IEEE754_RD:        /* toward -Infinity */
                                xm += 0x8;
                        break;
                case IEEE754_RD:        /* toward -Infinity */

-                       if (sn) /* ?? */
+                       if (sn) /* ?? */

                                xm += 0x8;
                        break;
                }
                                xm += 0x8;
                        break;
                }

diff --git a/arch/mips/math-emu/ieee754xcpt.c b/arch/mips/math-emu/ieee754xcpt.c
index b99a693c05afc0f78d6d21524e6ab99536e4a62d..967167116ae8110bf7c6fd281e71d8a89a4888b9 100644 (file)
--- a/arch/mips/math-emu/ieee754xcpt.c
+++ b/arch/mips/math-emu/ieee754xcpt.c
@@ -25,7 +25,7 @@
  *  Added preprocessor hacks to map to Linux kernel diagnostics.
  *
  *  Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  *  Added preprocessor hacks to map to Linux kernel diagnostics.
  *
  *  Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com

- *  Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *  Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.

  *************************************************************************/
 
 #include <linux/kernel.h>
  *************************************************************************/
 
 #include <linux/kernel.h>

diff --git a/arch/mips/math-emu/kernel_linkage.c b/arch/mips/math-emu/kernel_linkage.c
index 52e6c58c8de1d88b12d80b6bac2872cc54bb72f6..1c586575fe172c2283846da91dc5d9910b52f0c2 100644 (file)
--- a/arch/mips/math-emu/kernel_linkage.c
+++ b/arch/mips/math-emu/kernel_linkage.c
@@ -1,6 +1,6 @@
 /*
  *  Kevin D. Kissell, kevink@mips and Carsten Langgaard, carstenl@mips.com
 /*
  *  Kevin D. Kissell, kevink@mips and Carsten Langgaard, carstenl@mips.com

- *  Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
+ *  Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.

  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as

diff --git a/arch/mips/math-emu/sp_add.c b/arch/mips/math-emu/sp_add.c
index ae1a327ccac0dc585490f6af7ff65248c3230311..c446e64637e212d3a852bc0ccb3a9e8671436f20 100644 (file)
--- a/arch/mips/math-emu/sp_add.c
+++ b/arch/mips/math-emu/sp_add.c
@@ -148,7 +148,7 @@ ieee754sp ieee754sp_add(ieee754sp x, ieee754sp y)
                xe = xe;
                xs = xs;
 
                xe = xe;
                xs = xs;
 

-               if (xm >> (SP_MBITS + 1 + 3)) { /* carry out */
+               if (xm >> (SP_MBITS + 1 + 3)) { /* carry out */

                        SPXSRSX1();
                }
        } else {
                        SPXSRSX1();
                }
        } else {

diff --git a/arch/mips/math-emu/sp_mul.c b/arch/mips/math-emu/sp_mul.c
index 2722a2570ea4f7b4e4952163a47977563994a0f1..fa4675cf2aad13d2deef5b4d86f6c059d1fdb1ec 100644 (file)
--- a/arch/mips/math-emu/sp_mul.c
+++ b/arch/mips/math-emu/sp_mul.c
@@ -131,7 +131,7 @@ ieee754sp ieee754sp_mul(ieee754sp x, ieee754sp y)
                        hrm = hxm * hym;        /* 16 * 16 => 32 */
 
                        {
                        hrm = hxm * hym;        /* 16 * 16 => 32 */
 
                        {

-                               unsigned t = lxm * hym; /* 16 * 16 => 32 */
+                               unsigned t = lxm * hym; /* 16 * 16 => 32 */

                                {
                                        unsigned at = lrm + (t << 16);
                                        hrm += at < lrm;
                                {
                                        unsigned at = lrm + (t << 16);
                                        hrm += at < lrm;


@@ -141,7 +141,7 @@ ieee754sp ieee754sp_mul(ieee754sp x, ieee754sp y)
                        }
 
                        {
                        }
 
                        {

-                               unsigned t = hxm * lym; /* 16 * 16 => 32 */
+                               unsigned t = hxm * lym; /* 16 * 16 => 32 */

                                {
                                        unsigned at = lrm + (t << 16);
                                        hrm += at < lrm;
                                {
                                        unsigned at = lrm + (t << 16);
                                        hrm += at < lrm;

diff --git a/arch/mips/math-emu/sp_sub.c b/arch/mips/math-emu/sp_sub.c
index 886ed5bcfefb58e4d26d210334f200d34188d386..e595c6f3d0bb9d4e3711eecb002635d38af45209 100644 (file)
--- a/arch/mips/math-emu/sp_sub.c
+++ b/arch/mips/math-emu/sp_sub.c
@@ -153,7 +153,7 @@ ieee754sp ieee754sp_sub(ieee754sp x, ieee754sp y)
                xe = xe;
                xs = xs;
 
                xe = xe;
                xs = xs;
 

-               if (xm >> (SP_MBITS + 1 + 3)) { /* carry out */
+               if (xm >> (SP_MBITS + 1 + 3)) { /* carry out */

                        SPXSRSX1();     /* shift preserving sticky */
                }
        } else {
                        SPXSRSX1();     /* shift preserving sticky */
                }
        } else {

diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 90ceb963aaf13b61822ee8252dca372feec17fe3..1dcec30ad1c43b7c5e6e06c61f5c46cf04df7eac 100644 (file)
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -16,9 +16,9 @@ obj-$(CONFIG_CPU_R3000)               += c-r3k.o tlb-r3k.o
 obj-$(CONFIG_CPU_R8000)                += c-r4k.o cex-gen.o tlb-r8k.o
 obj-$(CONFIG_CPU_SB1)          += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o
 obj-$(CONFIG_CPU_TX39XX)       += c-tx39.o tlb-r3k.o
 obj-$(CONFIG_CPU_R8000)                += c-r4k.o cex-gen.o tlb-r8k.o
 obj-$(CONFIG_CPU_SB1)          += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o
 obj-$(CONFIG_CPU_TX39XX)       += c-tx39.o tlb-r3k.o

-obj-$(CONFIG_CPU_CAVIUM_OCTEON)        += c-octeon.o cex-oct.o tlb-r4k.o
+obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o

 
 obj-$(CONFIG_IP22_CPU_SCACHE)  += sc-ip22.o
 
 obj-$(CONFIG_IP22_CPU_SCACHE)  += sc-ip22.o

-obj-$(CONFIG_R5000_CPU_SCACHE)  += sc-r5k.o
-obj-$(CONFIG_RM7000_CPU_SCACHE)        += sc-rm7k.o
+obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
+obj-$(CONFIG_RM7000_CPU_SCACHE) += sc-rm7k.o

 obj-$(CONFIG_MIPS_CPU_SCACHE)  += sc-mips.o
 obj-$(CONFIG_MIPS_CPU_SCACHE)  += sc-mips.o

diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
index 6ec04daf423112903669ea98eb7e2b41dfd931c0..8557fb55286321fe0af21e67ea212212d4c294da 100644 (file)
--- a/arch/mips/mm/c-octeon.c
+++ b/arch/mips/mm/c-octeon.c
@@ -106,7 +106,7 @@ static void octeon_flush_icache_all(void)
  * Called to flush all memory associated with a memory
  * context.
  *
  * Called to flush all memory associated with a memory
  * context.
  *

- * @mm:     Memory context to flush
+ * @mm:            Memory context to flush

  */
 static void octeon_flush_cache_mm(struct mm_struct *mm)
 {
  */
 static void octeon_flush_cache_mm(struct mm_struct *mm)
 {

diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c
index 031c4c2cdf2e0144df401bcb13b3cb9fec28e2a0..704dc735a59dfcd1cc368197730f6f279c2ea845 100644 (file)
--- a/arch/mips/mm/c-r3k.c
+++ b/arch/mips/mm/c-r3k.c
@@ -119,7 +119,7 @@ static void r3k_flush_icache_range(unsigned long start, unsigned long end)
        write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC);
 
        for (i = 0; i < size; i += 0x080) {
        write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC);
 
        for (i = 0; i < size; i += 0x080) {

-               asm(    "sb\t$0, 0x000(%0)\n\t"
+               asm(    "sb\t$0, 0x000(%0)\n\t"

                        "sb\t$0, 0x004(%0)\n\t"
                        "sb\t$0, 0x008(%0)\n\t"
                        "sb\t$0, 0x00c(%0)\n\t"
                        "sb\t$0, 0x004(%0)\n\t"
                        "sb\t$0, 0x008(%0)\n\t"
                        "sb\t$0, 0x00c(%0)\n\t"


@@ -176,7 +176,7 @@ static void r3k_flush_dcache_range(unsigned long start, unsigned long end)
        write_c0_status((ST0_ISC|flags)&~ST0_IEC);
 
        for (i = 0; i < size; i += 0x080) {
        write_c0_status((ST0_ISC|flags)&~ST0_IEC);
 
        for (i = 0; i < size; i += 0x080) {

-               asm(    "sb\t$0, 0x000(%0)\n\t"
+               asm(    "sb\t$0, 0x000(%0)\n\t"

                        "sb\t$0, 0x004(%0)\n\t"
                        "sb\t$0, 0x008(%0)\n\t"
                        "sb\t$0, 0x00c(%0)\n\t"
                        "sb\t$0, 0x004(%0)\n\t"
                        "sb\t$0, 0x008(%0)\n\t"
                        "sb\t$0, 0x00c(%0)\n\t"


@@ -285,13 +285,13 @@ static void r3k_flush_cache_sigtramp(unsigned long addr)
        write_c0_status(flags&~ST0_IEC);
 
        /* Fill the TLB to avoid an exception with caches isolated. */
        write_c0_status(flags&~ST0_IEC);
 
        /* Fill the TLB to avoid an exception with caches isolated. */

-       asm(    "lw\t$0, 0x000(%0)\n\t"
+       asm(    "lw\t$0, 0x000(%0)\n\t"

                "lw\t$0, 0x004(%0)\n\t"
                : : "r" (addr) );
 
        write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC);
 
                "lw\t$0, 0x004(%0)\n\t"
                : : "r" (addr) );
 
        write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC);
 

-       asm(    "sb\t$0, 0x000(%0)\n\t"
+       asm(    "sb\t$0, 0x000(%0)\n\t"

                "sb\t$0, 0x004(%0)\n\t"
                : : "r" (addr) );
 
                "sb\t$0, 0x004(%0)\n\t"
                : : "r" (addr) );
 

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 0f7d788e88106fafa98e824d8b6d22f0bdcd2067..d45f8e28b4705909c4efdb7083367bdfb9124c45 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -160,7 +160,7 @@ static void __cpuinit r4k_blast_dcache_setup(void)
                "1:\n\t" \
                )
 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
                "1:\n\t" \
                )
 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */

-#define CACHE32_UNROLL32_ALIGN2        JUMP_TO_ALIGN(11)
+#define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)

 
 static inline void blast_r4600_v1_icache32(void)
 {
 
 static inline void blast_r4600_v1_icache32(void)
 {


@@ -177,7 +177,7 @@ static inline void tx49_blast_icache32(void)
        unsigned long end = start + current_cpu_data.icache.waysize;
        unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
        unsigned long ws_end = current_cpu_data.icache.ways <<
        unsigned long end = start + current_cpu_data.icache.waysize;
        unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
        unsigned long ws_end = current_cpu_data.icache.ways <<

-                              current_cpu_data.icache.waybit;
+                              current_cpu_data.icache.waybit;

        unsigned long ws, addr;
 
        CACHE32_UNROLL32_ALIGN2;
        unsigned long ws, addr;
 
        CACHE32_UNROLL32_ALIGN2;


@@ -208,7 +208,7 @@ static inline void tx49_blast_icache32_page_indexed(unsigned long page)
        unsigned long end = start + PAGE_SIZE;
        unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
        unsigned long ws_end = current_cpu_data.icache.ways <<
        unsigned long end = start + PAGE_SIZE;
        unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
        unsigned long ws_end = current_cpu_data.icache.ways <<

-                              current_cpu_data.icache.waybit;
+                              current_cpu_data.icache.waybit;

        unsigned long ws, addr;
 
        CACHE32_UNROLL32_ALIGN2;
        unsigned long ws, addr;
 
        CACHE32_UNROLL32_ALIGN2;


@@ -637,7 +637,7 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
                         * for the cache instruction on MIPS processors and
                         * some processors, among them the RM5200 and RM7000
                         * QED processors will throw an address error for cache
                         * for the cache instruction on MIPS processors and
                         * some processors, among them the RM5200 and RM7000
                         * QED processors will throw an address error for cache

-                        * hit ops with insufficient alignment.  Solved by
+                        * hit ops with insufficient alignment.  Solved by

                         * aligning the address to cache line size.
                         */
                        blast_inv_scache_range(addr, addr + size);
                         * aligning the address to cache line size.
                         */
                        blast_inv_scache_range(addr, addr + size);


@@ -864,7 +864,7 @@ static void __cpuinit probe_pcache(void)
                icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
                c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
                c->icache.ways = 1;
                icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
                c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
                c->icache.ways = 1;

-               c->icache.waybit = 0;   /* doesn't matter */
+               c->icache.waybit = 0;   /* doesn't matter */

 
                dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
                c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 
                dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
                c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);


@@ -923,7 +923,7 @@ static void __cpuinit probe_pcache(void)
                icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
                c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
                c->icache.ways = 1;
                icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
                c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
                c->icache.ways = 1;

-               c->icache.waybit = 0;   /* doesn't matter */
+               c->icache.waybit = 0;   /* doesn't matter */

 
                dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
                c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 
                dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
                c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);


@@ -986,8 +986,8 @@ static void __cpuinit probe_pcache(void)
                c->icache.ways = 1 + ((config1 >> 16) & 7);
 
                icache_size = c->icache.sets *
                c->icache.ways = 1 + ((config1 >> 16) & 7);
 
                icache_size = c->icache.sets *

-                             c->icache.ways *
-                             c->icache.linesz;
+                             c->icache.ways *
+                             c->icache.linesz;

                c->icache.waybit = __ffs(icache_size/c->icache.ways);
 
                if (config & 0x8)               /* VI bit */
                c->icache.waybit = __ffs(icache_size/c->icache.ways);
 
                if (config & 0x8)               /* VI bit */


@@ -1006,8 +1006,8 @@ static void __cpuinit probe_pcache(void)
                c->dcache.ways = 1 + ((config1 >> 7) & 7);
 
                dcache_size = c->dcache.sets *
                c->dcache.ways = 1 + ((config1 >> 7) & 7);
 
                dcache_size = c->dcache.sets *

-                             c->dcache.ways *
-                             c->dcache.linesz;
+                             c->dcache.ways *
+                             c->dcache.linesz;

                c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
 
                c->options |= MIPS_CPU_PREFETCH;
                c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
 
                c->options |= MIPS_CPU_PREFETCH;


@@ -1016,7 +1016,7 @@ static void __cpuinit probe_pcache(void)
 
        /*
         * Processor configuration sanity check for the R4000SC erratum
 
        /*
         * Processor configuration sanity check for the R4000SC erratum

-        * #5.  With page sizes larger than 32kB there is no possibility
+        * #5.  With page sizes larger than 32kB there is no possibility

         * to get a VCE exception anymore so we don't care about this
         * misconfiguration.  The case is rather theoretical anyway;
         * presumably no vendor is shipping his hardware in the "bad"
         * to get a VCE exception anymore so we don't care about this
         * misconfiguration.  The case is rather theoretical anyway;
         * presumably no vendor is shipping his hardware in the "bad"


@@ -1088,7 +1088,7 @@ static void __cpuinit probe_pcache(void)
                break;
        }
 
                break;
        }
 

-#ifdef  CONFIG_CPU_LOONGSON2
+#ifdef CONFIG_CPU_LOONGSON2

        /*
         * LOONGSON2 has 4 way icache, but when using indexed cache op,
         * one op will act on all 4 ways
        /*
         * LOONGSON2 has 4 way icache, but when using indexed cache op,
         * one op will act on all 4 ways


@@ -1228,7 +1228,7 @@ static void __cpuinit setup_scache(void)
 #ifdef CONFIG_R5000_CPU_SCACHE
                r5k_sc_init();
 #endif
 #ifdef CONFIG_R5000_CPU_SCACHE
                r5k_sc_init();
 #endif

-                return;
+               return;

 
        case CPU_RM7000:
 #ifdef CONFIG_RM7000_CPU_SCACHE
 
        case CPU_RM7000:
 #ifdef CONFIG_RM7000_CPU_SCACHE

diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index 87d23cada6d6d055efd41d3bf5fc486f5ec9db1a..ba9da270289fa9924a01df6a819989a6a23a19e6 100644 (file)
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -33,9 +33,9 @@ extern int r3k_have_wired_reg;        /* in r3k-tlb.c */
 /* This sequence is required to ensure icache is disabled immediately */
 #define TX39_STOP_STREAMING() \
 __asm__ __volatile__( \
 /* This sequence is required to ensure icache is disabled immediately */
 #define TX39_STOP_STREAMING() \
 __asm__ __volatile__( \

-       ".set    push\n\t" \
-       ".set    noreorder\n\t" \
-       "b       1f\n\t" \
+       ".set    push\n\t" \
+       ".set    noreorder\n\t" \
+       "b       1f\n\t" \

        "nop\n\t" \
        "1:\n\t" \
        ".set pop" \
        "nop\n\t" \
        "1:\n\t" \
        ".set pop" \


@@ -361,7 +361,7 @@ void __cpuinit tx39_cache_init(void)
                /* TX39/H core (writethru direct-map cache) */
                __flush_cache_vmap      = tx39__flush_cache_vmap;
                __flush_cache_vunmap    = tx39__flush_cache_vunmap;
                /* TX39/H core (writethru direct-map cache) */
                __flush_cache_vmap      = tx39__flush_cache_vmap;
                __flush_cache_vunmap    = tx39__flush_cache_vunmap;

-               flush_cache_all = tx39h_flush_icache_all;
+               flush_cache_all = tx39h_flush_icache_all;

                __flush_cache_all       = tx39h_flush_icache_all;
                flush_cache_mm          = (void *) tx39h_flush_icache_all;
                flush_cache_range       = (void *) tx39h_flush_icache_all;
                __flush_cache_all       = tx39h_flush_icache_all;
                flush_cache_mm          = (void *) tx39h_flush_icache_all;
                flush_cache_range       = (void *) tx39h_flush_icache_all;


@@ -409,8 +409,8 @@ void __cpuinit tx39_cache_init(void)
                _dma_cache_inv = tx39_dma_cache_inv;
 
                shm_align_mask = max_t(unsigned long,
                _dma_cache_inv = tx39_dma_cache_inv;
 
                shm_align_mask = max_t(unsigned long,

-                                      (dcache_size / current_cpu_data.dcache.ways) - 1,
-                                      PAGE_SIZE - 1);
+                                      (dcache_size / current_cpu_data.dcache.ways) - 1,
+                                      PAGE_SIZE - 1);

 
                break;
        }
 
                break;
        }

diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c
index 3571090ba17816e332a2843d6aee478131154932..576add33bf5bf1ae19af08a9605959b89e62f123 100644 (file)
--- a/arch/mips/mm/cerr-sb1.c
+++ b/arch/mips/mm/cerr-sb1.c
@@ -27,7 +27,7 @@
 
 /*
  * We'd like to dump the L2_ECC_TAG register on errors, but errata make
 
 /*
  * We'd like to dump the L2_ECC_TAG register on errors, but errata make

- * that unsafe... So for now we don't.  (BCM1250/BCM112x erratum SOC-48.)
+ * that unsafe... So for now we don't. (BCM1250/BCM112x erratum SOC-48.)

  */
 #undef DUMP_L2_ECC_TAG_ON_ERROR
 
  */
 #undef DUMP_L2_ECC_TAG_ON_ERROR
 


@@ -48,7 +48,7 @@
 #define CP0_CERRI_EXTERNAL     (1 << 26)
 
 #define CP0_CERRI_IDX_VALID(c) (!((c) & CP0_CERRI_EXTERNAL))
 #define CP0_CERRI_EXTERNAL     (1 << 26)
 
 #define CP0_CERRI_IDX_VALID(c) (!((c) & CP0_CERRI_EXTERNAL))

-#define CP0_CERRI_DATA         (CP0_CERRI_DATA_PARITY)
+#define CP0_CERRI_DATA        (CP0_CERRI_DATA_PARITY)

 
 #define CP0_CERRD_MULTIPLE     (1 << 31)
 #define CP0_CERRD_TAG_STATE    (1 << 30)
 
 #define CP0_CERRD_MULTIPLE     (1 << 31)
 #define CP0_CERRD_TAG_STATE    (1 << 30)


@@ -56,8 +56,8 @@
 #define CP0_CERRD_DATA_SBE     (1 << 28)
 #define CP0_CERRD_DATA_DBE     (1 << 27)
 #define CP0_CERRD_EXTERNAL     (1 << 26)
 #define CP0_CERRD_DATA_SBE     (1 << 28)
 #define CP0_CERRD_DATA_DBE     (1 << 27)
 #define CP0_CERRD_EXTERNAL     (1 << 26)

-#define CP0_CERRD_LOAD         (1 << 25)
-#define CP0_CERRD_STORE        (1 << 24)
+#define CP0_CERRD_LOAD        (1 << 25)
+#define CP0_CERRD_STORE               (1 << 24)

 #define CP0_CERRD_FILLWB       (1 << 23)
 #define CP0_CERRD_COHERENCY    (1 << 22)
 #define CP0_CERRD_DUPTAG       (1 << 21)
 #define CP0_CERRD_FILLWB       (1 << 23)
 #define CP0_CERRD_COHERENCY    (1 << 22)
 #define CP0_CERRD_DUPTAG       (1 << 21)


@@ -69,10 +69,10 @@
    (CP0_CERRD_LOAD | CP0_CERRD_STORE | CP0_CERRD_FILLWB | CP0_CERRD_COHERENCY | CP0_CERRD_DUPTAG)
 #define CP0_CERRD_TYPES \
    (CP0_CERRD_TAG_STATE | CP0_CERRD_TAG_ADDRESS | CP0_CERRD_DATA_SBE | CP0_CERRD_DATA_DBE | CP0_CERRD_EXTERNAL)
    (CP0_CERRD_LOAD | CP0_CERRD_STORE | CP0_CERRD_FILLWB | CP0_CERRD_COHERENCY | CP0_CERRD_DUPTAG)
 #define CP0_CERRD_TYPES \
    (CP0_CERRD_TAG_STATE | CP0_CERRD_TAG_ADDRESS | CP0_CERRD_DATA_SBE | CP0_CERRD_DATA_DBE | CP0_CERRD_EXTERNAL)

-#define CP0_CERRD_DATA         (CP0_CERRD_DATA_SBE | CP0_CERRD_DATA_DBE)
+#define CP0_CERRD_DATA        (CP0_CERRD_DATA_SBE | CP0_CERRD_DATA_DBE)

 
 

-static uint32_t        extract_ic(unsigned short addr, int data);
-static uint32_t        extract_dc(unsigned short addr, int data);
+static uint32_t extract_ic(unsigned short addr, int data);
+static uint32_t extract_dc(unsigned short addr, int data);

 
 static inline void breakout_errctl(unsigned int val)
 {
 
 static inline void breakout_errctl(unsigned int val)
 {


@@ -209,11 +209,11 @@ asmlinkage void sb1_cache_error(void)
          "=r" (dpahi), "=r" (dpalo), "=r" (eepc));
 
        cerr_dpa = (((uint64_t)dpahi) << 32) | dpalo;
          "=r" (dpahi), "=r" (dpalo), "=r" (eepc));
 
        cerr_dpa = (((uint64_t)dpahi) << 32) | dpalo;

-       printk(" c0_errorepc ==   %08x\n", eepc);
-       printk(" c0_errctl   ==   %08x", errctl);
+       printk(" c0_errorepc ==   %08x\n", eepc);
+       printk(" c0_errctl   ==   %08x", errctl);

        breakout_errctl(errctl);
        if (errctl & CP0_ERRCTL_ICACHE) {
        breakout_errctl(errctl);
        if (errctl & CP0_ERRCTL_ICACHE) {

-               printk(" c0_cerr_i   ==   %08x", cerr_i);
+               printk(" c0_cerr_i   ==   %08x", cerr_i);

                breakout_cerri(cerr_i);
                if (CP0_CERRI_IDX_VALID(cerr_i)) {
                        /* Check index of EPC, allowing for delay slot */
                breakout_cerri(cerr_i);
                if (CP0_CERRI_IDX_VALID(cerr_i)) {
                        /* Check index of EPC, allowing for delay slot */


@@ -229,7 +229,7 @@ asmlinkage void sb1_cache_error(void)
                }
        }
        if (errctl & CP0_ERRCTL_DCACHE) {
                }
        }
        if (errctl & CP0_ERRCTL_DCACHE) {

-               printk(" c0_cerr_d   ==   %08x", cerr_d);
+               printk(" c0_cerr_d   ==   %08x", cerr_d);

                breakout_cerrd(cerr_d);
                if (CP0_CERRD_DPA_VALID(cerr_d)) {
                        printk(" c0_cerr_dpa == %010llx\n", cerr_dpa);
                breakout_cerrd(cerr_d);
                if (CP0_CERRD_DPA_VALID(cerr_d)) {
                        printk(" c0_cerr_dpa == %010llx\n", cerr_dpa);


@@ -256,7 +256,7 @@ asmlinkage void sb1_cache_error(void)
        /*
         * Calling panic() when a fatal cache error occurs scrambles the
         * state of the system (and the cache), making it difficult to
        /*
         * Calling panic() when a fatal cache error occurs scrambles the
         * state of the system (and the cache), making it difficult to

-        * investigate after the fact.  However, if you just stall the CPU,
+        * investigate after the fact.  However, if you just stall the CPU,

         * the other CPU may keep on running, which is typically very
         * undesirable.
         */
         * the other CPU may keep on running, which is typically very
         * undesirable.
         */


@@ -411,7 +411,7 @@ static uint32_t extract_ic(unsigned short addr, int data)
                                "       dmfc0  $1, $28, 1\n\t"
                                "       dsrl32 %1, $1, 0 \n\t"
                                "       sll    %2, $1, 0 \n\t"
                                "       dmfc0  $1, $28, 1\n\t"
                                "       dsrl32 %1, $1, 0 \n\t"
                                "       sll    %2, $1, 0 \n\t"

-                               "       .set    pop         \n"
+                               "       .set    pop         \n"

                                : "=r" (datahi), "=r" (insta), "=r" (instb)
                                : "r" ((way << 13) | addr | (offset << 3)));
                                predecode = (datahi >> 8) & 0xff;
                                : "=r" (datahi), "=r" (insta), "=r" (instb)
                                : "r" ((way << 13) | addr | (offset << 3)));
                                predecode = (datahi >> 8) & 0xff;


@@ -441,8 +441,8 @@ static uint8_t dc_ecc(uint64_t dword)
 {
        uint64_t t;
        uint32_t w;
 {
        uint64_t t;
        uint32_t w;

-       uint8_t  p;
-       int      i;
+       uint8_t  p;
+       int      i;

 
        p = 0;
        for (i = 7; i >= 0; i--)
 
        p = 0;
        for (i = 7; i >= 0; i--)

diff --git a/arch/mips/mm/cex-gen.S b/arch/mips/mm/cex-gen.S
index e743622fd24d2e913cb65d7c566341331e3b548f..45dff5cd4b8e7a0278442acee6818a47bd72eb76 100644 (file)
--- a/arch/mips/mm/cex-gen.S
+++ b/arch/mips/mm/cex-gen.S
@@ -14,17 +14,17 @@
 #include <asm/stackframe.h>
 
 /*
 #include <asm/stackframe.h>
 
 /*

- * Game over.  Go to the button.  Press gently.  Swear where allowed by
+ * Game over.  Go to the button.  Press gently.         Swear where allowed by

  * legislation.
  */
        LEAF(except_vec2_generic)
        .set    noreorder
        .set    noat
  * legislation.
  */
        LEAF(except_vec2_generic)
        .set    noreorder
        .set    noat

-       .set    mips0
+       .set    mips0

        /*
         * This is a very bad place to be.  Our cache error
         * detection has triggered.  If we have write-back data
        /*
         * This is a very bad place to be.  Our cache error
         * detection has triggered.  If we have write-back data

-        * in the cache, we may not be able to recover.  As a
+        * in the cache, we may not be able to recover.  As a

         * first-order desperate measure, turn off KSEG0 cacheing.
         */
        mfc0    k0,CP0_CONFIG
         * first-order desperate measure, turn off KSEG0 cacheing.
         */
        mfc0    k0,CP0_CONFIG

diff --git a/arch/mips/mm/cex-oct.S b/arch/mips/mm/cex-oct.S
index 3db8553fcd3442d190d0aa5a03890cc13337e85a..9029092aa740df636c2be53033ae3c3399c337ee 100644 (file)
--- a/arch/mips/mm/cex-oct.S
+++ b/arch/mips/mm/cex-oct.S
@@ -18,7 +18,7 @@
  */
        LEAF(except_vec2_octeon)
 
  */
        LEAF(except_vec2_octeon)
 

-       .set    push
+       .set    push

        .set    mips64r2
        .set    noreorder
        .set    noat
        .set    mips64r2
        .set    noreorder
        .set    noat


@@ -27,19 +27,19 @@
        /* due to an errata we need to read the COP0 CacheErr (Dcache)
         * before any cache/DRAM access  */
 
        /* due to an errata we need to read the COP0 CacheErr (Dcache)
         * before any cache/DRAM access  */
 

-       rdhwr   k0, $0        /* get core_id */
-       PTR_LA  k1, cache_err_dcache
-       sll     k0, k0, 3
+       rdhwr   k0, $0        /* get core_id */
+       PTR_LA  k1, cache_err_dcache
+       sll     k0, k0, 3

        PTR_ADDU k1, k0, k1    /* k1 = &cache_err_dcache[core_id] */
 
        PTR_ADDU k1, k0, k1    /* k1 = &cache_err_dcache[core_id] */
 

-       dmfc0   k0, CP0_CACHEERR, 1
-       sd      k0, (k1)
-       dmtc0   $0, CP0_CACHEERR, 1
+       dmfc0   k0, CP0_CACHEERR, 1
+       sd      k0, (k1)
+       dmtc0   $0, CP0_CACHEERR, 1

 
 

-        /* check whether this is a nested exception */
-       mfc0    k1, CP0_STATUS
-       andi    k1, k1, ST0_EXL
-       beqz    k1, 1f
+       /* check whether this is a nested exception */
+       mfc0    k1, CP0_STATUS
+       andi    k1, k1, ST0_EXL
+       beqz    k1, 1f

         nop
        j       cache_parity_error_octeon_non_recoverable
         nop
         nop
        j       cache_parity_error_octeon_non_recoverable
         nop


@@ -48,22 +48,22 @@
 1:     j       handle_cache_err
         nop
 
 1:     j       handle_cache_err
         nop
 

-       .set    pop
+       .set    pop

        END(except_vec2_octeon)
 
  /* We need to jump to handle_cache_err so that the previous handler
   * can fit within 0x80 bytes. We also move from 0xFFFFFFFFAXXXXXXX
        END(except_vec2_octeon)
 
  /* We need to jump to handle_cache_err so that the previous handler
   * can fit within 0x80 bytes. We also move from 0xFFFFFFFFAXXXXXXX

-  * space (uncached) to the 0xFFFFFFFF8XXXXXXX space (cached).  */
+  * space (uncached) to the 0xFFFFFFFF8XXXXXXX space (cached). */

        LEAF(handle_cache_err)
        LEAF(handle_cache_err)

-       .set    push
-        .set    noreorder
-        .set    noat
+       .set    push
+       .set    noreorder
+       .set    noat

 
        SAVE_ALL
        KMODE
 
        SAVE_ALL
        KMODE

-       jal     cache_parity_error_octeon_recoverable
+       jal     cache_parity_error_octeon_recoverable

        nop
        nop

-       j       ret_from_exception
+       j       ret_from_exception

        nop
 
        .set pop
        nop
 
        .set pop

diff --git a/arch/mips/mm/cex-sb1.S b/arch/mips/mm/cex-sb1.S
index 89c412bc4b640ee3ce7418d80a6f559be5e9f53e..fe1d887e8d7056f9471ed54c0f57bafd89bcfe33 100644 (file)
--- a/arch/mips/mm/cex-sb1.S
+++ b/arch/mips/mm/cex-sb1.S
@@ -24,9 +24,9 @@
 #include <asm/cacheops.h>
 #include <asm/sibyte/board.h>
 
 #include <asm/cacheops.h>
 #include <asm/sibyte/board.h>
 

-#define C0_ERRCTL     $26             /* CP0: Error info */
-#define C0_CERR_I     $27             /* CP0: Icache error */
-#define C0_CERR_D     $27,1           /* CP0: Dcache error */
+#define C0_ERRCTL     $26            /* CP0: Error info */
+#define C0_CERR_I     $27            /* CP0: Icache error */
+#define C0_CERR_D     $27,1          /* CP0: Dcache error */

 
        /*
         * Based on SiByte sample software cache-err/cerr.S
 
        /*
         * Based on SiByte sample software cache-err/cerr.S


@@ -88,7 +88,7 @@ attempt_recovery:
        /*
         * k0 has C0_ERRCTL << 1, which puts 'DC' at bit 31.  Any
         * Dcache errors we can recover from will take more extensive
        /*
         * k0 has C0_ERRCTL << 1, which puts 'DC' at bit 31.  Any
         * Dcache errors we can recover from will take more extensive

-        * processing.  For now, they are considered "unrecoverable".
+        * processing.  For now, they are considered "unrecoverable".

         * Note that 'DC' becoming set (outside of ERL mode) will
         * cause 'IC' to clear; so if there's an Icache error, we'll
         * only find out about it if we recover from this error and
         * Note that 'DC' becoming set (outside of ERL mode) will
         * cause 'IC' to clear; so if there's an Icache error, we'll
         * only find out about it if we recover from this error and

diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 3fab2046c8a430d762ca800b905672fadc5e4572..f9ef83829a523fd65803b3f5b2c8fdfe77e31a8f 100644 (file)
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -4,7 +4,7 @@
  * for more details.
  *
  * Copyright (C) 2000  Ani Joshi <ajoshi@unixbox.com>
  * for more details.
  *
  * Copyright (C) 2000  Ani Joshi <ajoshi@unixbox.com>

- * Copyright (C) 2000, 2001, 06  Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) 2000, 2001, 06         Ralf Baechle <ralf@linux-mips.org>

  * swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
  */
 
  * swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
  */
 

diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c
index ddcec1e1a0cd256df9db44404686a42a31e58947..0fead53d1c26b261affa89d00c1fa06844f9e602 100644 (file)
--- a/arch/mips/mm/fault.c
+++ b/arch/mips/mm/fault.c
@@ -52,7 +52,7 @@ asmlinkage void __kprobes do_page_fault(struct pt_regs *regs, unsigned long writ
 
 #ifdef CONFIG_KPROBES
        /*
 
 #ifdef CONFIG_KPROBES
        /*

-        * This is to notify the fault handler of the kprobes.  The
+        * This is to notify the fault handler of the kprobes.  The

         * exception code is redundant as it is also carried in REGS,
         * but we pass it anyhow.
         */
         * exception code is redundant as it is also carried in REGS,
         * but we pass it anyhow.
         */


@@ -216,7 +216,7 @@ bad_area_nosemaphore:
        }
 
 no_context:
        }
 
 no_context:

-       /* Are we prepared to handle this kernel fault?  */
+       /* Are we prepared to handle this kernel fault?  */

        if (fixup_exception(regs)) {
                current->thread.cp0_baduaddr = address;
                return;
        if (fixup_exception(regs)) {
                current->thread.cp0_baduaddr = address;
                return;

diff --git a/arch/mips/mm/gup.c b/arch/mips/mm/gup.c
index dcfd573871c142348c4fa790bfcbd3dcc0c50879..d4ea5c9c4a93add70ec6e33b1efce8ab5b810c54 100644 (file)
--- a/arch/mips/mm/gup.c
+++ b/arch/mips/mm/gup.c
@@ -249,7 +249,7 @@ int __get_user_pages_fast(unsigned long start, int nr_pages, int write,
  * @nr_pages:  number of pages from start to pin
  * @write:     whether pages will be written to
  * @pages:     array that receives pointers to the pages pinned.
  * @nr_pages:  number of pages from start to pin
  * @write:     whether pages will be written to
  * @pages:     array that receives pointers to the pages pinned.

- *             Should be at least nr_pages long.
+ *             Should be at least nr_pages long.

  *
  * Attempt to pin user pages in memory without taking mm->mmap_sem.
  * If not successful, it will fall back to taking the lock and
  *
  * Attempt to pin user pages in memory without taking mm->mmap_sem.
  * If not successful, it will fall back to taking the lock and

diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index be9acb2b959d4d125752dd564b1c3c0831b7e458..67929251286c983597492db0cb5ca08ceb944ee0 100644 (file)
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -66,7 +66,7 @@
 
 /*
  * We have up to 8 empty zeroed pages so we can map one of the right colour
 
 /*
  * We have up to 8 empty zeroed pages so we can map one of the right colour

- * when needed.  This is necessary only on R4000 / R4400 SC and MC versions
+ * when needed.         This is necessary only on R4000 / R4400 SC and MC versions

  * where we have to avoid VCED / VECI exceptions for good performance at
  * any price.  Since page is never written to after the initialization we
  * don't have to care about aliases on other CPUs.
  * where we have to avoid VCED / VECI exceptions for good performance at
  * any price.  Since page is never written to after the initialization we
  * don't have to care about aliases on other CPUs.


@@ -380,7 +380,7 @@ void __init mem_init(void)
        high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
 
        totalram_pages += free_all_bootmem();
        high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
 
        totalram_pages += free_all_bootmem();

-       totalram_pages -= setup_zero_pages();   /* Setup zeroed pages.  */
+       totalram_pages -= setup_zero_pages();   /* Setup zeroed pages.  */

 
        reservedpages = ram = 0;
        for (tmp = 0; tmp < max_low_pfn; tmp++)
 
        reservedpages = ram = 0;
        for (tmp = 0; tmp < max_low_pfn; tmp++)

diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c
index cacfd31e8ec9d1121c86e81feb35fac4344a9a3b..7f840bc08abf189693a3ff4044c83f2ea0875992 100644 (file)
--- a/arch/mips/mm/ioremap.c
+++ b/arch/mips/mm/ioremap.c
@@ -22,7 +22,7 @@ static inline void remap_area_pte(pte_t * pte, unsigned long address,
        phys_t end;
        unsigned long pfn;
        pgprot_t pgprot = __pgprot(_PAGE_GLOBAL | _PAGE_PRESENT | __READABLE
        phys_t end;
        unsigned long pfn;
        pgprot_t pgprot = __pgprot(_PAGE_GLOBAL | _PAGE_PRESENT | __READABLE

-                                  | __WRITEABLE | flags);
+                                  | __WRITEABLE | flags);

 
        address &= ~PMD_MASK;
        end = address + size;
 
        address &= ~PMD_MASK;
        end = address + size;


@@ -185,7 +185,7 @@ void __iounmap(const volatile void __iomem *addr)
        if (!p)
                printk(KERN_ERR "iounmap: bad address %p\n", addr);
 
        if (!p)
                printk(KERN_ERR "iounmap: bad address %p\n", addr);
 

-        kfree(p);
+       kfree(p);

 }
 
 EXPORT_SYMBOL(__ioremap);
 }
 
 EXPORT_SYMBOL(__ioremap);

diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index 8e666c55f4d47c432a58402ff5b80efa04d81288..a29fba55b53e79c8d7399d67f101356379f20c73 100644 (file)
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -271,7 +271,7 @@ void __cpuinit build_clear_page(void)
                uasm_i_lui(&buf, AT, 0xa000);
 
        off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size)
                uasm_i_lui(&buf, AT, 0xa000);
 
        off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size)

-                               * cache_line_size : 0;
+                               * cache_line_size : 0;

        while (off) {
                build_clear_pref(&buf, -off);
                off -= cache_line_size;
        while (off) {
                build_clear_pref(&buf, -off);
                off -= cache_line_size;


@@ -417,13 +417,13 @@ void __cpuinit build_copy_page(void)
                uasm_i_lui(&buf, AT, 0xa000);
 
        off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) *
                uasm_i_lui(&buf, AT, 0xa000);
 
        off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) *

-                               cache_line_size : 0;
+                               cache_line_size : 0;

        while (off) {
                build_copy_load_pref(&buf, -off);
                off -= cache_line_size;
        }
        off = cache_line_size ? min(8, pref_bias_copy_store / cache_line_size) *
        while (off) {
                build_copy_load_pref(&buf, -off);
                off -= cache_line_size;
        }
        off = cache_line_size ? min(8, pref_bias_copy_store / cache_line_size) *

-                               cache_line_size : 0;
+                               cache_line_size : 0;

        while (off) {
                build_copy_store_pref(&buf, -off);
                off -= cache_line_size;
        while (off) {
                build_copy_store_pref(&buf, -off);
                off -= cache_line_size;

diff --git a/arch/mips/mm/pgtable-64.c b/arch/mips/mm/pgtable-64.c
index ee331bbd8f8aa13c263b8aa31c6bfdbab75e1101..e8adc0069d66f17fcc6e27915fa1d5eb8e8258a6 100644 (file)
--- a/arch/mips/mm/pgtable-64.c
+++ b/arch/mips/mm/pgtable-64.c
@@ -24,7 +24,7 @@ void pgd_init(unsigned long page)
        entry = (unsigned long)invalid_pmd_table;
 #endif
 
        entry = (unsigned long)invalid_pmd_table;
 #endif
 

-       p = (unsigned long *) page;
+       p = (unsigned long *) page;

        end = p + PTRS_PER_PGD;
 
        do {
        end = p + PTRS_PER_PGD;
 
        do {


@@ -45,7 +45,7 @@ void pmd_init(unsigned long addr, unsigned long pagetable)
 {
        unsigned long *p, *end;
 
 {
        unsigned long *p, *end;
 

-       p = (unsigned long *) addr;
+       p = (unsigned long *) addr;

        end = p + PTRS_PER_PMD;
 
        do {
        end = p + PTRS_PER_PMD;
 
        do {

diff --git a/arch/mips/mm/sc-ip22.c b/arch/mips/mm/sc-ip22.c
index 1eb708ef75ff47cfa4ad8ff8acaca83fa5fdb1a3..c6aaed934d536ff9bddacb1a65aee337585c4af7 100644 (file)
--- a/arch/mips/mm/sc-ip22.c
+++ b/arch/mips/mm/sc-ip22.c
@@ -159,7 +159,7 @@ static inline int __init indy_sc_probe(void)
 }
 
 /* XXX Check with wje if the Indy caches can differenciate between
 }
 
 /* XXX Check with wje if the Indy caches can differenciate between

-   writeback + invalidate and just invalidate.  */
+   writeback + invalidate and just invalidate. */

 static struct bcache_ops indy_sc_ops = {
        .bc_enable = indy_sc_enable,
        .bc_disable = indy_sc_disable,
 static struct bcache_ops indy_sc_ops = {
        .bc_enable = indy_sc_enable,
        .bc_disable = indy_sc_disable,

diff --git a/arch/mips/mm/sc-r5k.c b/arch/mips/mm/sc-r5k.c
index 8d90ff25b1235880332dec654f03fb45b7f77b56..8bc67720e145f5ab6b7b91718b45c88baf924238 100644 (file)
--- a/arch/mips/mm/sc-r5k.c
+++ b/arch/mips/mm/sc-r5k.c
@@ -58,7 +58,7 @@ static void r5k_dma_cache_inv_sc(unsigned long addr, unsigned long size)
 
 static void r5k_sc_enable(void)
 {
 
 static void r5k_sc_enable(void)
 {

-        unsigned long flags;
+       unsigned long flags;

 
        local_irq_save(flags);
        set_c0_config(R5K_CONF_SE);
 
        local_irq_save(flags);
        set_c0_config(R5K_CONF_SE);


@@ -68,7 +68,7 @@ static void r5k_sc_enable(void)
 
 static void r5k_sc_disable(void)
 {
 
 static void r5k_sc_disable(void)
 {

-        unsigned long flags;
+       unsigned long flags;

 
        local_irq_save(flags);
        blast_r5000_scache();
 
        local_irq_save(flags);
        blast_r5000_scache();

diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 2a7c9725b2a3b704a1028b2ec10a357495357c52..493131c81a29b9a1c45bf44a000596ccdf17035f 100644 (file)
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -424,7 +424,7 @@ void __cpuinit tlb_init(void)
                write_c0_pagegrain(pg);
        }
 
                write_c0_pagegrain(pg);
        }
 

-        /* From this point on the ARC firmware is dead.  */
+       /* From this point on the ARC firmware is dead.  */

        local_flush_tlb_all();
 
        /* Did I tell you that ARC SUCKS?  */
        local_flush_tlb_all();
 
        /* Did I tell you that ARC SUCKS?  */

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 1c8ac49ec72cabc7bc66583012bb3d21ac270a7c..36b9bd89c799d89af027d95331dbbae03834c60b 100644 (file)
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -5,8 +5,8 @@
  *
  * Synthesize TLB refill handlers at runtime.
  *
  *
  * Synthesize TLB refill handlers at runtime.
  *

- * Copyright (C) 2004, 2005, 2006, 2008  Thiemo Seufer
- * Copyright (C) 2005, 2007, 2008, 2009  Maciej W. Rozycki
+ * Copyright (C) 2004, 2005, 2006, 2008         Thiemo Seufer
+ * Copyright (C) 2005, 2007, 2008, 2009         Maciej W. Rozycki

  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
  * Copyright (C) 2008, 2009 Cavium Networks, Inc.
  * Copyright (C) 2011  MIPS Technologies, Inc.
  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
  * Copyright (C) 2008, 2009 Cavium Networks, Inc.
  * Copyright (C) 2011  MIPS Technologies, Inc.


@@ -212,7 +212,7 @@ static void __cpuinit uasm_bgezl_label(struct uasm_label **l,
 /*
  * pgtable bits are assigned dynamically depending on processor feature
  * and statically based on kernel configuration.  This spits out the actual
 /*
  * pgtable bits are assigned dynamically depending on processor feature
  * and statically based on kernel configuration.  This spits out the actual

- * values the kernel is using.  Required to make sense from disassembled
+ * values the kernel is using. Required to make sense from disassembled

  * TLB exception handlers.
  */
 static void output_pgtable_bits_defines(void)
  * TLB exception handlers.
  */
 static void output_pgtable_bits_defines(void)


@@ -464,8 +464,8 @@ static u32 final_handler[64] __cpuinitdata;
  * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
  * 2. A timing hazard exists for the TLBP instruction.
  *
  * From the IDT errata for the QED RM5230 (Nevada), processor revision 1.0:
  * 2. A timing hazard exists for the TLBP instruction.
  *

- *      stalling_instruction
- *      TLBP
+ *     stalling_instruction
+ *     TLBP

  *
  * The JTLB is being read for the TLBP throughout the stall generated by the
  * previous instruction. This is not really correct as the stalling instruction
  *
  * The JTLB is being read for the TLBP throughout the stall generated by the
  * previous instruction. This is not really correct as the stalling instruction


@@ -476,7 +476,7 @@ static u32 final_handler[64] __cpuinitdata;
  * The software work-around is to not allow the instruction preceding the TLBP
  * to stall - make it an NOP or some other instruction guaranteed not to stall.
  *
  * The software work-around is to not allow the instruction preceding the TLBP
  * to stall - make it an NOP or some other instruction guaranteed not to stall.
  *

- * Errata 2 will not be fixed.  This errata is also on the R5000.
+ * Errata 2 will not be fixed. This errata is also on the R5000.

  *
  * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
  */
  *
  * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
  */


@@ -748,7 +748,7 @@ static __cpuinit void build_huge_update_entries(u32 **p,
         */
        small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
 
         */
        small_sequence = (HPAGE_SIZE >> 7) < 0x10000;
 

-       /* We can clobber tmp.  It isn't used after this.*/
+       /* We can clobber tmp.  It isn't used after this.*/

        if (!small_sequence)
                uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
 
        if (!small_sequence)
                uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16));
 


@@ -830,12 +830,12 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
                /* Clear lower 23 bits of context. */
                uasm_i_dins(p, ptr, 0, 0, 23);
 
                /* Clear lower 23 bits of context. */
                uasm_i_dins(p, ptr, 0, 0, 23);
 

-               /* 1 0  1 0 1  << 6  xkphys cached */
+               /* 1 0  1 0 1  << 6  xkphys cached */

                uasm_i_ori(p, ptr, ptr, 0x540);
                uasm_i_drotr(p, ptr, ptr, 11);
        }
 #elif defined(CONFIG_SMP)
                uasm_i_ori(p, ptr, ptr, 0x540);
                uasm_i_drotr(p, ptr, ptr, 11);
        }
 #elif defined(CONFIG_SMP)

-# ifdef  CONFIG_MIPS_MT_SMTC
+# ifdef         CONFIG_MIPS_MT_SMTC

        /*
         * SMTC uses TCBind value as "CPU" index
         */
        /*
         * SMTC uses TCBind value as "CPU" index
         */


@@ -955,7 +955,7 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
 
        /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
 #ifdef CONFIG_SMP
 
        /* 32 bit SMP has smp_processor_id() stored in CONTEXT. */
 #ifdef CONFIG_SMP

-#ifdef  CONFIG_MIPS_MT_SMTC
+#ifdef CONFIG_MIPS_MT_SMTC

        /*
         * SMTC uses TCBind value as "CPU" index
         */
        /*
         * SMTC uses TCBind value as "CPU" index
         */


@@ -965,7 +965,7 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
 #else
        /*
         * smp_processor_id() << 3 is stored in CONTEXT.
 #else
        /*
         * smp_processor_id() << 3 is stored in CONTEXT.

-         */
+        */

        uasm_i_mfc0(p, ptr, C0_CONTEXT);
        UASM_i_LA_mostly(p, tmp, pgdc);
        uasm_i_srl(p, ptr, ptr, 23);
        uasm_i_mfc0(p, ptr, C0_CONTEXT);
        UASM_i_LA_mostly(p, tmp, pgdc);
        uasm_i_srl(p, ptr, ptr, 23);


@@ -1153,7 +1153,7 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
 
        if (pgd_reg == -1) {
                vmalloc_branch_delay_filled = 1;
 
        if (pgd_reg == -1) {
                vmalloc_branch_delay_filled = 1;

-               /* 1 0  1 0 1  << 6  xkphys cached */
+               /* 1 0  1 0 1  << 6  xkphys cached */

                uasm_i_ori(p, ptr, ptr, 0x540);
                uasm_i_drotr(p, ptr, ptr, 11);
        }
                uasm_i_ori(p, ptr, ptr, 0x540);
                uasm_i_drotr(p, ptr, ptr, 11);
        }


@@ -1171,9 +1171,9 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
        uasm_l_vmalloc_done(l, *p);
 
        /*
        uasm_l_vmalloc_done(l, *p);
 
        /*

-        *                         tmp          ptr
-        * fall-through case =   badvaddr  *pgd_current
-        * vmalloc case      =   badvaddr  swapper_pg_dir
+        *                         tmp          ptr
+        * fall-through case =   badvaddr  *pgd_current
+        * vmalloc case      =   badvaddr  swapper_pg_dir

         */
 
        if (vmalloc_branch_delay_filled)
         */
 
        if (vmalloc_branch_delay_filled)


@@ -1212,7 +1212,7 @@ build_fast_tlb_refill_handler (u32 **p, struct uasm_label **l,
        uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);
        /*
         * The in the LWX case we don't want to do the load in the
        uasm_il_bbit1(p, r, scratch, ilog2(_PAGE_HUGE), label_tlb_huge_update);
        /*
         * The in the LWX case we don't want to do the load in the

-        * delay slot.  It cannot issue in the same cycle and may be
+        * delay slot.  It cannot issue in the same cycle and may be

         * speculative and unneeded.
         */
        if (use_lwx_insns())
         * speculative and unneeded.
         */
        if (use_lwx_insns())

diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index 39b89105622790c986724809e9cce50f3a8de6a4..942ff6c2eba27ac256d812c64a1b5752b164f712 100644 (file)
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -7,7 +7,7 @@
  * support a subset of instructions, and does not try to hide pipeline
  * effects like branch delay slots.
  *
  * support a subset of instructions, and does not try to hide pipeline
  * effects like branch delay slots.
  *

- * Copyright (C) 2004, 2005, 2006, 2008  Thiemo Seufer
+ * Copyright (C) 2004, 2005, 2006, 2008         Thiemo Seufer

  * Copyright (C) 2005, 2007  Maciej W. Rozycki
  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
  */
  * Copyright (C) 2005, 2007  Maciej W. Rozycki
  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
  */


@@ -119,30 +119,30 @@ static struct insn insn_table[] __uasminitdata = {
        { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE },
        { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE },
        { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
        { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE },
        { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE },
        { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },

-       { insn_jal,  M(jal_op, 0, 0, 0, 0, 0),  JIMM },
+       { insn_jal,  M(jal_op, 0, 0, 0, 0, 0),  JIMM },

        { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
        { insn_jr,  M(spec_op, 0, 0, 0, 0, jr_op),  RS },
        { insn_ld,  M(ld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
        { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },
        { insn_j,  M(j_op, 0, 0, 0, 0, 0),  JIMM },
        { insn_jr,  M(spec_op, 0, 0, 0, 0, jr_op),  RS },
        { insn_ld,  M(ld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
        { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },

-       { insn_lld,  M(lld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+       { insn_lld,  M(lld_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },

        { insn_ll,  M(ll_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
        { insn_ll,  M(ll_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },

-       { insn_lui,  M(lui_op, 0, 0, 0, 0, 0),  RT | SIMM },
+       { insn_lui,  M(lui_op, 0, 0, 0, 0, 0),  RT | SIMM },

        { insn_lw,  M(lw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
        { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
        { insn_mfc0,  M(cop0_op, mfc_op, 0, 0, 0, 0),  RT | RD | SET},
        { insn_mtc0,  M(cop0_op, mtc_op, 0, 0, 0, 0),  RT | RD | SET},
        { insn_lw,  M(lw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
        { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
        { insn_mfc0,  M(cop0_op, mfc_op, 0, 0, 0, 0),  RT | RD | SET},
        { insn_mtc0,  M(cop0_op, mtc_op, 0, 0, 0, 0),  RT | RD | SET},

-       { insn_ori,  M(ori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
+       { insn_ori,  M(ori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },

        { insn_or,  M(spec_op, 0, 0, 0, 0, or_op),  RS | RT | RD },
        { insn_pref,  M(pref_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
        { insn_rfe,  M(cop0_op, cop_op, 0, 0, 0, rfe_op),  0 },
        { insn_rotr,  M(spec_op, 1, 0, 0, 0, srl_op),  RT | RD | RE },
        { insn_or,  M(spec_op, 0, 0, 0, 0, or_op),  RS | RT | RD },
        { insn_pref,  M(pref_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
        { insn_rfe,  M(cop0_op, cop_op, 0, 0, 0, rfe_op),  0 },
        { insn_rotr,  M(spec_op, 1, 0, 0, 0, srl_op),  RT | RD | RE },

-       { insn_scd,  M(scd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
+       { insn_scd,  M(scd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },

        { insn_sc,  M(sc_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
        { insn_sd,  M(sd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
        { insn_sll,  M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE },
        { insn_sra,  M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE },
        { insn_srl,  M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE },
        { insn_sc,  M(sc_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
        { insn_sd,  M(sd_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
        { insn_sll,  M(spec_op, 0, 0, 0, 0, sll_op),  RT | RD | RE },
        { insn_sra,  M(spec_op, 0, 0, 0, 0, sra_op),  RT | RD | RE },
        { insn_srl,  M(spec_op, 0, 0, 0, 0, srl_op),  RT | RD | RE },

-       { insn_subu,  M(spec_op, 0, 0, 0, 0, subu_op),  RS | RT | RD },
+       { insn_subu,  M(spec_op, 0, 0, 0, 0, subu_op),  RS | RT | RD },

        { insn_sw,  M(sw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
        { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
        { insn_tlbp,  M(cop0_op, cop_op, 0, 0, 0, tlbp_op),  0 },
        { insn_sw,  M(sw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
        { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
        { insn_tlbp,  M(cop0_op, cop_op, 0, 0, 0, tlbp_op),  0 },


@@ -345,7 +345,7 @@ Ip_u2u1msbu3(op)                                    \
 }                                                      \
 UASM_EXPORT_SYMBOL(uasm_i##op);
 
 }                                                      \
 UASM_EXPORT_SYMBOL(uasm_i##op);
 

-#define I_u2u1msbdu3(op)                               \
+#define I_u2u1msbdu3(op)                               \

 Ip_u2u1msbu3(op)                                       \
 {                                                      \
        build_insn(buf, insn##op, b, a, d-1, c);        \
 Ip_u2u1msbu3(op)                                       \
 {                                                      \
        build_insn(buf, insn##op, b, a, d-1, c);        \

diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c
index 469d9b0cee6dd16f80d402d5cce6ae73d8ca245e..1e4784458016eb73a417283777f2b9b9d5117ae4 100644 (file)
--- a/arch/mips/mti-malta/malta-amon.c
+++ b/arch/mips/mti-malta/malta-amon.c
@@ -70,12 +70,12 @@ void amon_cpu_start(int cpu,
        launch->sp = sp;
        launch->a0 = a0;
 
        launch->sp = sp;
        launch->a0 = a0;
 

-       smp_wmb();              /* Target must see parameters before go */
+       smp_wmb();              /* Target must see parameters before go */

        launch->flags |= LAUNCH_FGO;
        launch->flags |= LAUNCH_FGO;

-       smp_wmb();              /* Target must see go before we poll  */
+       smp_wmb();              /* Target must see go before we poll  */

 
        while ((launch->flags & LAUNCH_FGONE) == 0)
                ;
 
        while ((launch->flags & LAUNCH_FGONE) == 0)
                ;

-       smp_rmb();      /* Target will be updating flags soon */
+       smp_rmb();      /* Target will be updating flags soon */

        pr_debug("launch: cpu%d gone!\n", cpu);
 }
        pr_debug("launch: cpu%d gone!\n", cpu);
 }

diff --git a/arch/mips/mti-malta/malta-cmdline.c b/arch/mips/mti-malta/malta-cmdline.c
index 1871c30ed2eb778bc8109b163b686f2b4e0595c5..5576a306a145da81465270d5ed7a60bbb86322b1 100644 (file)
--- a/arch/mips/mti-malta/malta-cmdline.c
+++ b/arch/mips/mti-malta/malta-cmdline.c
@@ -46,7 +46,7 @@ void  __init prom_init_cmdline(void)
 
        cp = &(arcs_cmdline[0]);
        while(actr < prom_argc) {
 
        cp = &(arcs_cmdline[0]);
        while(actr < prom_argc) {

-               strcpy(cp, prom_argv(actr));
+               strcpy(cp, prom_argv(actr));

                cp += strlen(prom_argv(actr));
                *cp++ = ' ';
                actr++;
                cp += strlen(prom_argv(actr));
                *cp++ = ' ';
                actr++;

diff --git a/arch/mips/mti-malta/malta-display.c b/arch/mips/mti-malta/malta-display.c
index 7c8828fcb0ad40adc26415a30d92a447ef2ed467..9bc58a24e80a637307e13058eab6d54eacf91c88 100644 (file)
--- a/arch/mips/mti-malta/malta-display.c
+++ b/arch/mips/mti-malta/malta-display.c
@@ -37,10 +37,10 @@ void mips_display_message(const char *str)
                display = ioremap(ASCII_DISPLAY_POS_BASE, 16*sizeof(int));
 
        for (i = 0; i <= 14; i=i+2) {
                display = ioremap(ASCII_DISPLAY_POS_BASE, 16*sizeof(int));
 
        for (i = 0; i <= 14; i=i+2) {

-                if (*str)
-                        __raw_writel(*str++, display + i);
+                if (*str)
+                        __raw_writel(*str++, display + i);

                 else
                 else

-                        __raw_writel(' ', display + i);
+                        __raw_writel(' ', display + i);

        }
 }
 
        }
 }
 

diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c
index 27a6cdb36e3787be065553f823c408e2f2601a0c..c2cbce9e435e8ffc74d25a9cfff61acbc38dc1b4 100644 (file)
--- a/arch/mips/mti-malta/malta-init.c
+++ b/arch/mips/mti-malta/malta-init.c
@@ -1,5 +1,5 @@
 /*
 /*

- * Copyright (C) 1999, 2000, 2004, 2005  MIPS Technologies, Inc.
+ * Copyright (C) 1999, 2000, 2004, 2005         MIPS Technologies, Inc.

  *     All rights reserved.
  *     Authors: Carsten Langgaard <carstenl@mips.com>
  *              Maciej W. Rozycki <macro@mips.com>
  *     All rights reserved.
  *     Authors: Carsten Langgaard <carstenl@mips.com>
  *              Maciej W. Rozycki <macro@mips.com>


@@ -110,20 +110,20 @@ static inline void str2eaddr(unsigned char *ea, unsigned char *str)
 
 int get_ethernet_addr(char *ethernet_addr)
 {
 
 int get_ethernet_addr(char *ethernet_addr)
 {

-        char *ethaddr_str;
+       char *ethaddr_str;

 
 

-        ethaddr_str = prom_getenv("ethaddr");
+       ethaddr_str = prom_getenv("ethaddr");

        if (!ethaddr_str) {
        if (!ethaddr_str) {

-               printk("ethaddr not set in boot prom\n");
+               printk("ethaddr not set in boot prom\n");

                return -1;
        }
        str2eaddr(ethernet_addr, ethaddr_str);
 
        if (init_debug > 1) {
                return -1;
        }
        str2eaddr(ethernet_addr, ethaddr_str);
 
        if (init_debug > 1) {

-               int i;
+               int i;

                printk("get_ethernet_addr: ");
                printk("get_ethernet_addr: ");

-               for (i=0; i<5; i++)
-                       printk("%02x:", (unsigned char)*(ethernet_addr+i));
+               for (i=0; i<5; i++)
+                       printk("%02x:", (unsigned char)*(ethernet_addr+i));

                printk("%02x\n", *(ethernet_addr+i));
        }
 
                printk("%02x\n", *(ethernet_addr+i));
        }
 

diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index 647b863831840a1da098c1c2f43d5e46018f53ae..e364af70e6cf5cc255a9be51ca569d7cb911dbf0 100644 (file)
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -84,10 +84,10 @@ static inline int mips_pcibios_iack(void)
 
                /* Flush Bonito register block */
                (void) BONITO_PCIMAP_CFG;
 
                /* Flush Bonito register block */
                (void) BONITO_PCIMAP_CFG;

-               iob();    /* sync */
+               iob();    /* sync */

 
                irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
 
                irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);

-               iob();    /* sync */
+               iob();    /* sync */

                irq &= 0xff;
                BONITO_PCIMAP_CFG = 0;
                break;
                irq &= 0xff;
                BONITO_PCIMAP_CFG = 0;
                break;


@@ -136,7 +136,7 @@ static void malta_ipi_irqdispatch(void)
 
        irq = gic_get_int();
        if (irq < 0)
 
        irq = gic_get_int();
        if (irq < 0)

-               return;  /* interrupt has already been cleared */
+               return;  /* interrupt has already been cleared */

 
        do_IRQ(MIPS_GIC_IRQ_BASE + irq);
 }
 
        do_IRQ(MIPS_GIC_IRQ_BASE + irq);
 }


@@ -149,7 +149,7 @@ static void corehi_irqdispatch(void)
        struct pt_regs *regs = get_irq_regs();
 
        printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n");
        struct pt_regs *regs = get_irq_regs();
 
        printk(KERN_EMERG "CoreHI interrupt, shouldn't happen, we die here!\n");

-       printk(KERN_EMERG "epc   : %08lx\nStatus: %08lx\n"
+       printk(KERN_EMERG "epc   : %08lx\nStatus: %08lx\n"

                        "Cause : %08lx\nbadVaddr : %08lx\n",
                        regs->cp0_epc, regs->cp0_status,
                        regs->cp0_cause, regs->cp0_badvaddr);
                        "Cause : %08lx\nbadVaddr : %08lx\n",
                        regs->cp0_epc, regs->cp0_status,
                        regs->cp0_cause, regs->cp0_badvaddr);


@@ -249,20 +249,20 @@ static inline unsigned int irq_ffs(unsigned int pending)
  * on hardware interrupt 0 (MIPS IRQ 2)) like:
  *
  *     MIPS IRQ        Source
  * on hardware interrupt 0 (MIPS IRQ 2)) like:
  *
  *     MIPS IRQ        Source

- *      --------        ------
- *             0       Software (ignored)
- *             1        Software (ignored)
- *             2        Combined hardware interrupt (hw0)
- *             3        Hardware (ignored)
- *             4        Hardware (ignored)
- *             5        Hardware (ignored)
- *             6        Hardware (ignored)
- *             7        R4k timer (what we use)
+ *     --------        ------
+ *            0        Software (ignored)
+ *            1        Software (ignored)
+ *            2        Combined hardware interrupt (hw0)
+ *            3        Hardware (ignored)
+ *            4        Hardware (ignored)
+ *            5        Hardware (ignored)
+ *            6        Hardware (ignored)
+ *            7        R4k timer (what we use)

  *
  * We handle the IRQ according to _our_ priority which is:
  *
  *
  * We handle the IRQ according to _our_ priority which is:
  *

- * Highest ----     R4k Timer
- * Lowest  ----     Combined hardware interrupt
+ * Highest ----            R4k Timer
+ * Lowest  ----            Combined hardware interrupt

  *
  * then we just return, if multiple IRQs are pending then we will just take
  * another exception, big deal.
  *
  * then we just return, if multiple IRQs are pending then we will just take
  * another exception, big deal.


@@ -396,7 +396,7 @@ static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap);
 
 static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
        { X, X,            X,           X,              0 },
 
 static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
        { X, X,            X,           X,              0 },

-       { X, X,            X,           X,              0 },
+       { X, X,            X,           X,              0 },

        { X, X,            X,           X,              0 },
        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
        { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
        { X, X,            X,           X,              0 },
        { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
        { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },


@@ -410,7 +410,7 @@ static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = {
        { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
        { 0, GIC_CPU_NMI,  GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
        { 0, GIC_CPU_NMI,  GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
        { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
        { 0, GIC_CPU_NMI,  GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },
        { 0, GIC_CPU_NMI,  GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT },

-       { X, X,            X,           X,              0 },
+       { X, X,            X,           X,              0 },

        /* The remainder of this table is initialised by fill_ipi_map */
 };
 #undef X
        /* The remainder of this table is initialised by fill_ipi_map */
 };
 #undef X


@@ -634,7 +634,7 @@ void malta_be_init(void)
 
 static char *tr[8] = {
        "mem",  "gcr",  "gic",  "mmio",
 
 static char *tr[8] = {
        "mem",  "gcr",  "gic",  "mmio",

-       "0x04", "0x05", "0x06", "0x07"
+       "0x04", "0x05", "0x06", "0x07"

 };
 
 static char *mcmd[32] = {
 };
 
 static char *mcmd[32] = {


@@ -673,10 +673,10 @@ static char *mcmd[32] = {
 };
 
 static char *core[8] = {
 };
 
 static char *core[8] = {

-       "Invalid/OK",   "Invalid/Data",
+       "Invalid/OK",   "Invalid/Data",

        "Shared/OK",    "Shared/Data",
        "Modified/OK",  "Modified/Data",
        "Shared/OK",    "Shared/Data",
        "Modified/OK",  "Modified/Data",

-       "Exclusive/OK", "Exclusive/Data"
+       "Exclusive/OK", "Exclusive/Data"

 };
 
 static char *causes[32] = {
 };
 
 static char *causes[32] = {

diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c
index a96d281f9221257cd17017a8e779c88020f96c9b..f3d43aa023a9c9215dc06334204c1f82e122ef73 100644 (file)
--- a/arch/mips/mti-malta/malta-memory.c
+++ b/arch/mips/mti-malta/malta-memory.c
@@ -47,7 +47,7 @@ static char *mtypes[3] = {
 };
 #endif
 
 };
 #endif
 

-/* determined physical memory size, not overridden by command line args  */
+/* determined physical memory size, not overridden by command line args         */

 unsigned long physical_memsize = 0L;
 
 static struct prom_pmemblock * __init prom_getmdesc(void)
 unsigned long physical_memsize = 0L;
 
 static struct prom_pmemblock * __init prom_getmdesc(void)


@@ -158,7 +158,7 @@ void __init prom_meminit(void)
                size = p->size;
 
                add_memory_region(base, size, type);
                size = p->size;
 
                add_memory_region(base, size, type);

-                p++;
+               p++;

        }
 }
 
        }
 }
 

diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c
index 2147cb34e705a2dca85355aa529c03ca878744a6..37134ddfeaa5d43b26ac482e251523a42e404741 100644 (file)
--- a/arch/mips/mti-malta/malta-pci.c
+++ b/arch/mips/mti-malta/malta-pci.c
@@ -1,5 +1,5 @@
 /*
 /*

- * Copyright (C) 1999, 2000, 2004, 2005  MIPS Technologies, Inc.
+ * Copyright (C) 1999, 2000, 2004, 2005         MIPS Technologies, Inc.

  *     All rights reserved.
  *     Authors: Carsten Langgaard <carstenl@mips.com>
  *              Maciej W. Rozycki <macro@mips.com>
  *     All rights reserved.
  *     Authors: Carsten Langgaard <carstenl@mips.com>
  *              Maciej W. Rozycki <macro@mips.com>


@@ -127,7 +127,7 @@ void __init mips_pcibios_init(void)
                        map = map1;
                }
                mask = ~(start ^ end);
                        map = map1;
                }
                mask = ~(start ^ end);

-                /* We don't support remapping with a discontiguous mask.  */
+               /* We don't support remapping with a discontiguous mask.  */

                BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
                       mask != ~((mask & -mask) - 1));
                gt64120_mem_resource.start = start;
                BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
                       mask != ~((mask & -mask) - 1));
                gt64120_mem_resource.start = start;


@@ -144,7 +144,7 @@ void __init mips_pcibios_init(void)
                map = GT_READ(GT_PCI0IOREMAP_OFS);
                end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
                mask = ~(start ^ end);
                map = GT_READ(GT_PCI0IOREMAP_OFS);
                end = (end & GT_PCI_HD_MSK) | (start & ~GT_PCI_HD_MSK);
                mask = ~(start ^ end);

-                /* We don't support remapping with a discontiguous mask.  */
+               /* We don't support remapping with a discontiguous mask.  */

                BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
                       mask != ~((mask & -mask) - 1));
                gt64120_io_resource.start = map & mask;
                BUG_ON((start & GT_PCI_HD_MSK) != (map & GT_PCI_HD_MSK) &&
                       mask != ~((mask & -mask) - 1));
                gt64120_io_resource.start = map & mask;

diff --git a/arch/mips/mti-malta/malta-platform.c b/arch/mips/mti-malta/malta-platform.c
index 74732177851c31843add1f2259dab3233932726a..132f8663825e4b29da00e44b48b32407cfba871b 100644 (file)
--- a/arch/mips/mti-malta/malta-platform.c
+++ b/arch/mips/mti-malta/malta-platform.c
@@ -93,7 +93,7 @@ static struct mtd_partition malta_mtd_partitions[] = {
                .mask_flags =   MTD_WRITEABLE
        }, {
                .name =         "User FS",
                .mask_flags =   MTD_WRITEABLE
        }, {
                .name =         "User FS",

-               .offset =       0x100000,
+               .offset =       0x100000,

                .size =         0x2e0000
        }, {
                .name =         "Board Config",
                .size =         0x2e0000
        }, {
                .name =         "Board Config",

diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index 2e28f653f66d1b582b9d0ca89c389aaaa1b18ca8..200f64df2c9b492bf6ec948ff03bbfee864f59fa 100644 (file)
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -78,9 +78,9 @@ const char *get_system_type(void)
 }
 
 #if defined(CONFIG_MIPS_MT_SMTC)
 }
 
 #if defined(CONFIG_MIPS_MT_SMTC)

-const char display_string[] = "       SMTC LINUX ON MALTA       ";
+const char display_string[] = "              SMTC LINUX ON MALTA       ";

 #else
 #else

-const char display_string[] = "        LINUX ON MALTA       ";
+const char display_string[] = "               LINUX ON MALTA       ";

 #endif /* CONFIG_MIPS_MT_SMTC */
 
 #ifdef CONFIG_BLK_DEV_FD
 #endif /* CONFIG_MIPS_MT_SMTC */
 
 #ifdef CONFIG_BLK_DEV_FD

diff --git a/arch/mips/mti-malta/malta-smtc.c b/arch/mips/mti-malta/malta-smtc.c
index 1efc8c3944860d29a6861231ad5bcacd5e917a99..becbf47506a59a0face9b35ba5ec7900e75e2d72 100644 (file)
--- a/arch/mips/mti-malta/malta-smtc.c
+++ b/arch/mips/mti-malta/malta-smtc.c
@@ -126,7 +126,7 @@ int plat_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
         * to the CPU daughterboard, and on the CoreFPGA2/3 34K models,
         * that signal is brought to IP2 of both VPEs. To avoid racing
         * concurrent interrupt service events, IP2 is enabled only on
         * to the CPU daughterboard, and on the CoreFPGA2/3 34K models,
         * that signal is brought to IP2 of both VPEs. To avoid racing
         * concurrent interrupt service events, IP2 is enabled only on

-        * one VPE, by convention VPE0.  So long as no bits are ever
+        * one VPE, by convention VPE0.  So long as no bits are ever

         * cleared in the affinity mask, there will never be any
         * interrupt forwarding.  But as soon as a program or operator
         * sets affinity for one of the related IRQs, we need to make
         * cleared in the affinity mask, there will never be any
         * interrupt forwarding.  But as soon as a program or operator
         * sets affinity for one of the related IRQs, we need to make

diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index 115f5bc0600332c25291483b0d451b4d7da07f0d..8607b0dd29f69c46d4cb2b8ca3c52a6e527aecd5 100644 (file)
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -95,7 +95,7 @@ static unsigned int __init estimate_cpu_frequency(void)
            (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
                count *= 2;
 
            (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
                count *= 2;
 

-       count += 5000;    /* round */
+       count += 5000;    /* round */

        count -= count%10000;
 
        return count;
        count -= count%10000;
 
        return count;


@@ -146,15 +146,15 @@ void __init plat_time_init(void)
 {
        unsigned int est_freq;
 
 {
        unsigned int est_freq;
 

-        /* Set Data mode - binary. */
-        CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
+       /* Set Data mode - binary. */
+       CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);

 
        est_freq = estimate_cpu_frequency();
 
        printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
               (est_freq%1000000)*100/1000000);
 
 
        est_freq = estimate_cpu_frequency();
 
        printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
               (est_freq%1000000)*100/1000000);
 

-        cpu_khz = est_freq / 1000;
+       cpu_khz = est_freq / 1000;

 
        mips_scroll_message();
 #ifdef CONFIG_I8253            /* Only Malta has a PIT */
 
        mips_scroll_message();
 #ifdef CONFIG_I8253            /* Only Malta has a PIT */

diff --git a/arch/mips/mti-sead3/leds-sead3.c b/arch/mips/mti-sead3/leds-sead3.c
index 3db832a818d5dd3971241adcb5bda73c91f98531..322148c353ed65065bd146f05de3ce27198382ca 100644 (file)
--- a/arch/mips/mti-sead3/leds-sead3.c
+++ b/arch/mips/mti-sead3/leds-sead3.c
@@ -33,12 +33,12 @@ static void sead3_fled_set(struct led_classdev *led_cdev,
 
 static struct led_classdev sead3_pled = {
        .name           = "sead3::pled",
 
 static struct led_classdev sead3_pled = {
        .name           = "sead3::pled",

-       .brightness_set = sead3_pled_set,
+       .brightness_set = sead3_pled_set,

 };
 
 static struct led_classdev sead3_fled = {
        .name           = "sead3::fled",
 };
 
 static struct led_classdev sead3_fled = {
        .name           = "sead3::fled",

-       .brightness_set = sead3_fled_set,
+       .brightness_set = sead3_fled_set,

 };
 
 #ifdef CONFIG_PM
 };
 
 #ifdef CONFIG_PM

diff --git a/arch/mips/mti-sead3/sead3-console.c b/arch/mips/mti-sead3/sead3-console.c
index b36739108a0fe15cd9d1ce0dd165b53adee1890b..2ddef19a9adc891b898188f8fae38e692309073a 100644 (file)
--- a/arch/mips/mti-sead3/sead3-console.c
+++ b/arch/mips/mti-sead3/sead3-console.c
@@ -10,8 +10,8 @@
 #include <linux/serial_reg.h>
 #include <linux/io.h>
 
 #include <linux/serial_reg.h>
 #include <linux/io.h>
 

-#define SEAD_UART1_REGS_BASE    0xbf000800   /* ttyS1 = DB9 port */
-#define SEAD_UART0_REGS_BASE    0xbf000900   /* ttyS0 = USB port   */
+#define SEAD_UART1_REGS_BASE   0xbf000800   /* ttyS1 = DB9 port */
+#define SEAD_UART0_REGS_BASE   0xbf000900   /* ttyS0 = USB port   */

 #define PORT(base_addr, offset) ((unsigned int __iomem *)(base_addr+(offset)*4))
 
 static char console_port = 1;
 #define PORT(base_addr, offset) ((unsigned int __iomem *)(base_addr+(offset)*4))
 
 static char console_port = 1;

diff --git a/arch/mips/mti-sead3/sead3-display.c b/arch/mips/mti-sead3/sead3-display.c
index 8308c7fc188ad154b41d53de0a733a0f319211c5..e389326cfa423add03614ec7baa10b1ed529c7e2 100644 (file)
--- a/arch/mips/mti-sead3/sead3-display.c
+++ b/arch/mips/mti-sead3/sead3-display.c
@@ -21,7 +21,7 @@ static unsigned int max_display_count;
 #define LCD_SETDDRAM                   0x80
 #define LCD_IR_BF                      0x80
 
 #define LCD_SETDDRAM                   0x80
 #define LCD_IR_BF                      0x80
 

-const char display_string[] = "               LINUX ON SEAD3               ";
+const char display_string[] = "                      LINUX ON SEAD3               ";

 
 static void scroll_display_message(unsigned long data);
 static DEFINE_TIMER(mips_scroll_timer, scroll_display_message, HZ, 0);
 
 static void scroll_display_message(unsigned long data);
 static DEFINE_TIMER(mips_scroll_timer, scroll_display_message, HZ, 0);

diff --git a/arch/mips/mti-sead3/sead3-i2c-drv.c b/arch/mips/mti-sead3/sead3-i2c-drv.c
index 7aa2225e75b907e0d77b7ed0d1a4f5d66120cba2..1f787a6a78788f806d3555da3be283b5f13b6931 100644 (file)
--- a/arch/mips/mti-sead3/sead3-i2c-drv.c
+++ b/arch/mips/mti-sead3/sead3-i2c-drv.c
@@ -13,32 +13,32 @@
 #include <linux/platform_device.h>
 
 #define PIC32_I2CxCON          0x0000
 #include <linux/platform_device.h>
 
 #define PIC32_I2CxCON          0x0000

-#define  PIC32_I2CCON_ON       (1<<15)
-#define  PIC32_I2CCON_ACKDT    (1<<5)
-#define  PIC32_I2CCON_ACKEN    (1<<4)
-#define  PIC32_I2CCON_RCEN     (1<<3)
-#define  PIC32_I2CCON_PEN      (1<<2)
-#define  PIC32_I2CCON_RSEN     (1<<1)
-#define  PIC32_I2CCON_SEN      (1<<0)
+#define         PIC32_I2CCON_ON        (1<<15)
+#define         PIC32_I2CCON_ACKDT     (1<<5)
+#define         PIC32_I2CCON_ACKEN     (1<<4)
+#define         PIC32_I2CCON_RCEN      (1<<3)
+#define         PIC32_I2CCON_PEN       (1<<2)
+#define         PIC32_I2CCON_RSEN      (1<<1)
+#define         PIC32_I2CCON_SEN       (1<<0)

 #define PIC32_I2CxCONCLR       0x0004
 #define PIC32_I2CxCONSET       0x0008
 #define PIC32_I2CxSTAT         0x0010
 #define PIC32_I2CxSTATCLR      0x0014
 #define PIC32_I2CxCONCLR       0x0004
 #define PIC32_I2CxCONSET       0x0008
 #define PIC32_I2CxSTAT         0x0010
 #define PIC32_I2CxSTATCLR      0x0014

-#define  PIC32_I2CSTAT_ACKSTAT (1<<15)
-#define  PIC32_I2CSTAT_TRSTAT  (1<<14)
-#define  PIC32_I2CSTAT_BCL     (1<<10)
-#define  PIC32_I2CSTAT_IWCOL   (1<<7)
-#define  PIC32_I2CSTAT_I2COV   (1<<6)
+#define         PIC32_I2CSTAT_ACKSTAT  (1<<15)
+#define         PIC32_I2CSTAT_TRSTAT   (1<<14)
+#define         PIC32_I2CSTAT_BCL      (1<<10)
+#define         PIC32_I2CSTAT_IWCOL    (1<<7)
+#define         PIC32_I2CSTAT_I2COV    (1<<6)

 #define PIC32_I2CxBRG          0x0040
 #define PIC32_I2CxTRN          0x0050
 #define PIC32_I2CxRCV          0x0060
 
 static DEFINE_SPINLOCK(pic32_bus_lock);
 
 #define PIC32_I2CxBRG          0x0040
 #define PIC32_I2CxTRN          0x0050
 #define PIC32_I2CxRCV          0x0060
 
 static DEFINE_SPINLOCK(pic32_bus_lock);
 

-static void __iomem *bus_xfer   = (void __iomem *)0xbf000600;
+static void __iomem *bus_xfer  = (void __iomem *)0xbf000600;

 static void __iomem *bus_status = (void __iomem *)0xbf000060;
 
 static void __iomem *bus_status = (void __iomem *)0xbf000060;
 

-#define DELAY()        udelay(100)
+#define DELAY() udelay(100)

 
 static inline unsigned int ioready(void)
 {
 
 static inline unsigned int ioready(void)
 {

diff --git a/arch/mips/mti-sead3/sead3-net.c b/arch/mips/mti-sead3/sead3-net.c
index 04d704df609847d3527027d4512f993797a9da44..dd11e7eb771c139c8483a97e97eee4e4052bbeaa 100644 (file)
--- a/arch/mips/mti-sead3/sead3-net.c
+++ b/arch/mips/mti-sead3/sead3-net.c
@@ -19,8 +19,8 @@ static struct smsc911x_platform_config sead3_smsc911x_data = {
 
 struct resource sead3_net_resourcess[] = {
        {
 
 struct resource sead3_net_resourcess[] = {
        {

-               .start                  = 0x1f010000,
-               .end                    = 0x1f01ffff,
+               .start                  = 0x1f010000,
+               .end                    = 0x1f01ffff,

                .flags                  = IORESOURCE_MEM
        },
        {
                .flags                  = IORESOURCE_MEM
        },
        {

diff --git a/arch/mips/mti-sead3/sead3-pic32-bus.c b/arch/mips/mti-sead3/sead3-pic32-bus.c
index 9f0d89bc800e519a9210d37cc4e44889a28ce332..eb2bf936d102b3a410a419bf341493d4177108dc 100644 (file)
--- a/arch/mips/mti-sead3/sead3-pic32-bus.c
+++ b/arch/mips/mti-sead3/sead3-pic32-bus.c
@@ -17,16 +17,16 @@
 #define PIC32_SYSRD    0x02
 #define PIC32_WR       0x10
 #define PIC32_SYSWR    0x20
 #define PIC32_SYSRD    0x02
 #define PIC32_WR       0x10
 #define PIC32_SYSWR    0x20

-#define PIC32_IRQ_CLR   0x40
+#define PIC32_IRQ_CLR  0x40

 #define PIC32_STATUS   0x80
 
 #define PIC32_STATUS   0x80
 

-#define DELAY()        udelay(100)     /* FIXME: needed? */
+#define DELAY() udelay(100)    /* FIXME: needed? */

 
 /* spinlock to ensure atomic access to PIC32 */
 static DEFINE_SPINLOCK(pic32_bus_lock);
 
 /* FIXME: io_remap these */
 
 /* spinlock to ensure atomic access to PIC32 */
 static DEFINE_SPINLOCK(pic32_bus_lock);
 
 /* FIXME: io_remap these */

-static void __iomem *bus_xfer   = (void __iomem *)0xbf000600;
+static void __iomem *bus_xfer  = (void __iomem *)0xbf000600;

 static void __iomem *bus_status = (void __iomem *)0xbf000060;
 
 static inline unsigned int ioready(void)
 static void __iomem *bus_status = (void __iomem *)0xbf000060;
 
 static inline unsigned int ioready(void)

diff --git a/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c b/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c
index 514675ed0cde2e27e216da96dffe160c61588290..b921e5ec507cb2d5946d130c2434c5f00f4ed9dc 100644 (file)
--- a/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c
+++ b/arch/mips/mti-sead3/sead3-pic32-i2c-drv.c
@@ -19,40 +19,40 @@
 #define PIC32_I2CxCONCLR       0x0004
 #define PIC32_I2CxCONSET       0x0008
 #define PIC32_I2CxCONINV       0x000C
 #define PIC32_I2CxCONCLR       0x0004
 #define PIC32_I2CxCONSET       0x0008
 #define PIC32_I2CxCONINV       0x000C

-#define  I2CCON_ON             (1<<15)
-#define  I2CCON_FRZ            (1<<14)
-#define  I2CCON_SIDL           (1<<13)
-#define  I2CCON_SCLREL         (1<<12)
-#define  I2CCON_STRICT         (1<<11)
-#define  I2CCON_A10M           (1<<10)
-#define  I2CCON_DISSLW         (1<<9)
-#define  I2CCON_SMEN           (1<<8)
-#define  I2CCON_GCEN           (1<<7)
-#define  I2CCON_STREN          (1<<6)
-#define  I2CCON_ACKDT          (1<<5)
-#define  I2CCON_ACKEN          (1<<4)
-#define  I2CCON_RCEN           (1<<3)
-#define  I2CCON_PEN            (1<<2)
-#define  I2CCON_RSEN           (1<<1)
-#define  I2CCON_SEN            (1<<0)
+#define         I2CCON_ON              (1<<15)
+#define         I2CCON_FRZ             (1<<14)
+#define         I2CCON_SIDL            (1<<13)
+#define         I2CCON_SCLREL          (1<<12)
+#define         I2CCON_STRICT          (1<<11)
+#define         I2CCON_A10M            (1<<10)
+#define         I2CCON_DISSLW          (1<<9)
+#define         I2CCON_SMEN            (1<<8)
+#define         I2CCON_GCEN            (1<<7)
+#define         I2CCON_STREN           (1<<6)
+#define         I2CCON_ACKDT           (1<<5)
+#define         I2CCON_ACKEN           (1<<4)
+#define         I2CCON_RCEN            (1<<3)
+#define         I2CCON_PEN             (1<<2)
+#define         I2CCON_RSEN            (1<<1)
+#define         I2CCON_SEN             (1<<0)

 
 #define PIC32_I2CxSTAT         0x0010
 #define PIC32_I2CxSTATCLR      0x0014
 #define PIC32_I2CxSTATSET      0x0018
 #define PIC32_I2CxSTATINV      0x001C
 
 #define PIC32_I2CxSTAT         0x0010
 #define PIC32_I2CxSTATCLR      0x0014
 #define PIC32_I2CxSTATSET      0x0018
 #define PIC32_I2CxSTATINV      0x001C

-#define  I2CSTAT_ACKSTAT       (1<<15)
-#define  I2CSTAT_TRSTAT                (1<<14)
-#define  I2CSTAT_BCL           (1<<10)
-#define  I2CSTAT_GCSTAT                (1<<9)
-#define  I2CSTAT_ADD10         (1<<8)
-#define  I2CSTAT_IWCOL         (1<<7)
-#define  I2CSTAT_I2COV         (1<<6)
-#define  I2CSTAT_DA            (1<<5)
-#define  I2CSTAT_P             (1<<4)
-#define  I2CSTAT_S             (1<<3)
-#define  I2CSTAT_RW            (1<<2)
-#define  I2CSTAT_RBF           (1<<1)
-#define  I2CSTAT_TBF           (1<<0)
+#define         I2CSTAT_ACKSTAT        (1<<15)
+#define         I2CSTAT_TRSTAT         (1<<14)
+#define         I2CSTAT_BCL            (1<<10)
+#define         I2CSTAT_GCSTAT         (1<<9)
+#define         I2CSTAT_ADD10          (1<<8)
+#define         I2CSTAT_IWCOL          (1<<7)
+#define         I2CSTAT_I2COV          (1<<6)
+#define         I2CSTAT_DA             (1<<5)
+#define         I2CSTAT_P              (1<<4)
+#define         I2CSTAT_S              (1<<3)
+#define         I2CSTAT_RW             (1<<2)
+#define         I2CSTAT_RBF            (1<<1)
+#define         I2CSTAT_TBF            (1<<0)

 
 #define PIC32_I2CxADD          0x0020
 #define PIC32_I2CxADDCLR       0x0024
 
 #define PIC32_I2CxADD          0x0020
 #define PIC32_I2CxADDCLR       0x0024

diff --git a/arch/mips/mti-sead3/sead3-time.c b/arch/mips/mti-sead3/sead3-time.c
index 048e781a17a0eacc08ce4c906c120619ecf2a6eb..239e4e32757fc566f8fb96b4366806531ba87aa7 100644 (file)
--- a/arch/mips/mti-sead3/sead3-time.c
+++ b/arch/mips/mti-sead3/sead3-time.c
@@ -43,11 +43,11 @@ static unsigned int __init estimate_cpu_frequency(void)
 
        local_irq_save(flags);
 
 
        local_irq_save(flags);
 

-       orig = readl(status_reg) & 0x2;               /* get original sample */
+       orig = readl(status_reg) & 0x2;               /* get original sample */

        /* wait for transition */
        while ((readl(status_reg) & 0x2) == orig)
                ;
        /* wait for transition */
        while ((readl(status_reg) & 0x2) == orig)
                ;

-       orig = orig ^ 0x2;                            /* flip the bit */
+       orig = orig ^ 0x2;                            /* flip the bit */

 
        write_c0_count(0);
 
 
        write_c0_count(0);
 


@@ -56,7 +56,7 @@ static unsigned int __init estimate_cpu_frequency(void)
                /* wait for transition */
                while ((readl(status_reg) & 0x2) == orig)
                        ;
                /* wait for transition */
                while ((readl(status_reg) & 0x2) == orig)
                        ;

-               orig = orig ^ 0x2;                            /* flip the bit */
+               orig = orig ^ 0x2;                            /* flip the bit */

                tick++;
        }
 
                tick++;
        }
 


@@ -71,7 +71,7 @@ static unsigned int __init estimate_cpu_frequency(void)
                (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
                freq *= 2;
 
                (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
                freq *= 2;
 

-       freq += 5000;        /* rounding */
+       freq += 5000;        /* rounding */

        freq -= freq%10000;
 
        return freq ;
        freq -= freq%10000;
 
        return freq ;

diff --git a/arch/mips/netlogic/Platform b/arch/mips/netlogic/Platform
index cdfc9abbbb7bc3905fbd0f8211ba74fa5d06f0dc..fb8eb4c0c6ec869110bf1375b5ccbc461e3bed67 100644 (file)
--- a/arch/mips/netlogic/Platform
+++ b/arch/mips/netlogic/Platform
@@ -13,5 +13,5 @@ cflags-$(CONFIG_CPU_XLP)      += $(call cc-option,-march=xlp,-march=mips64r2)
 #
 # NETLOGIC processor support
 #
 #
 # NETLOGIC processor support
 #

-platform-$(CONFIG_NLM_COMMON)          += netlogic/
-load-$(CONFIG_NLM_COMMON)      += 0xffffffff80100000
+platform-$(CONFIG_NLM_COMMON)  += netlogic/
+load-$(CONFIG_NLM_COMMON)      += 0xffffffff80100000

diff --git a/arch/mips/netlogic/common/irq.c b/arch/mips/netlogic/common/irq.c
index 00dcc7a2bc5a5d912a60274e36958af8a1ba86d9..780832e391ff04b93548427df93d45f81c312ec6 100644 (file)
--- a/arch/mips/netlogic/common/irq.c
+++ b/arch/mips/netlogic/common/irq.c
@@ -69,7 +69,7 @@
 #else
 #define SMP_IRQ_MASK   0
 #endif
 #else
 #define SMP_IRQ_MASK   0
 #endif

-#define PERCPU_IRQ_MASK        (SMP_IRQ_MASK | (1ull << IRQ_TIMER) | \
+#define PERCPU_IRQ_MASK (SMP_IRQ_MASK | (1ull << IRQ_TIMER) | \

                                (1ull << IRQ_FMN))
 
 struct nlm_pic_irq {
                                (1ull << IRQ_FMN))
 
 struct nlm_pic_irq {


@@ -107,7 +107,7 @@ static void xlp_pic_mask_ack(struct irq_data *d)
        struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
        uint64_t mask = 1ull << pd->picirq;
 
        struct nlm_pic_irq *pd = irq_data_get_irq_handler_data(d);
        uint64_t mask = 1ull << pd->picirq;
 

-       write_c0_eirr(mask);            /* ack by writing EIRR */
+       write_c0_eirr(mask);            /* ack by writing EIRR */

 }
 
 static void xlp_pic_unmask(struct irq_data *d)
 }
 
 static void xlp_pic_unmask(struct irq_data *d)

diff --git a/arch/mips/netlogic/common/smpboot.S b/arch/mips/netlogic/common/smpboot.S
index a0b74874bebeb2d66f36d21461948ead8f7bf7d6..280ff5855ef74ccc9deae6c5c364ea0343fa889f 100644 (file)
--- a/arch/mips/netlogic/common/smpboot.S
+++ b/arch/mips/netlogic/common/smpboot.S
@@ -49,12 +49,12 @@
 #include <asm/netlogic/xlp-hal/sys.h>
 #include <asm/netlogic/xlp-hal/cpucontrol.h>
 
 #include <asm/netlogic/xlp-hal/sys.h>
 #include <asm/netlogic/xlp-hal/cpucontrol.h>
 

-#define        CP0_EBASE       $15
+#define CP0_EBASE      $15

 #define SYS_CPU_COHERENT_BASE(node)    CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
                        XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
                        SYS_CPU_NONCOHERENT_MODE * 4
 
 #define SYS_CPU_COHERENT_BASE(node)    CKSEG1ADDR(XLP_DEFAULT_IO_BASE) + \
                        XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + \
                        SYS_CPU_NONCOHERENT_MODE * 4
 

-#define        XLP_AX_WORKAROUND       /* enable Ax silicon workarounds */
+#define XLP_AX_WORKAROUND      /* enable Ax silicon workarounds */

 
 /* Enable XLP features and workarounds in the LSU */
 .macro xlp_config_lsu
 
 /* Enable XLP features and workarounds in the LSU */
 .macro xlp_config_lsu


@@ -85,7 +85,7 @@
        li      t0, LSU_DEBUG_DATA0
        li      t1, LSU_DEBUG_ADDR
        li      t2, 0           /* index */
        li      t0, LSU_DEBUG_DATA0
        li      t1, LSU_DEBUG_ADDR
        li      t2, 0           /* index */

-       li      t3, 0x1000      /* loop count */
+       li      t3, 0x1000      /* loop count */

 1:
        sll     v0, t2, 5
        mtcr    zero, t0
 1:
        sll     v0, t2, 5
        mtcr    zero, t0


@@ -134,7 +134,7 @@ FEXPORT(nlm_reset_entry)
        and     k1, k0, k1
        beqz    k1, 1f          /* go to real reset entry */
        nop
        and     k1, k0, k1
        beqz    k1, 1f          /* go to real reset entry */
        nop

-       li      k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */
+       li      k1, CKSEG1ADDR(RESET_DATA_PHYS) /* NMI */

        ld      k0, BOOT_NMI_HANDLER(k1)
        jr      k0
        nop
        ld      k0, BOOT_NMI_HANDLER(k1)
        jr      k0
        nop


@@ -235,7 +235,7 @@ EXPORT(nlm_reset_entry_end)
 
 FEXPORT(xlp_boot_core0_siblings)       /* "Master" cpu starts from here */
        xlp_config_lsu
 
 FEXPORT(xlp_boot_core0_siblings)       /* "Master" cpu starts from here */
        xlp_config_lsu

-       dmtc0   sp, $4, 2               /* SP saved in UserLocal */
+       dmtc0   sp, $4, 2               /* SP saved in UserLocal */

        SAVE_ALL
        sync
        /* find the location to which nlm_boot_siblings was relocated */
        SAVE_ALL
        sync
        /* find the location to which nlm_boot_siblings was relocated */


@@ -301,13 +301,13 @@ NESTED(nlm_rmiboot_preboot, 16, sp)
         */
        li      t0, 0x400
        mfcr    t1, t0
         */
        li      t0, 0x400
        mfcr    t1, t0

-       li      t2, 6           /* XLR thread mode mask */
+       li      t2, 6           /* XLR thread mode mask */

        nor     t3, t2, zero
        and     t2, t1, t2      /* t2 - current thread mode */
        li      v0, CKSEG1ADDR(RESET_DATA_PHYS)
        lw      v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */
        sll     v1, 1
        nor     t3, t2, zero
        and     t2, t1, t2      /* t2 - current thread mode */
        li      v0, CKSEG1ADDR(RESET_DATA_PHYS)
        lw      v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */
        sll     v1, 1

-       beq     v1, t2, 1f      /* same as request value */
+       beq     v1, t2, 1f      /* same as request value */

        nop                     /* nothing to do */
 
        and     t2, t1, t3      /* mask out old thread mode */
        nop                     /* nothing to do */
 
        and     t2, t1, t3      /* mask out old thread mode */

diff --git a/arch/mips/netlogic/dts/xlp_evp.dts b/arch/mips/netlogic/dts/xlp_evp.dts
index e14f4230806427bfb481d4e46d7a757cd2c82114..7628b5464fc76161bf84f5192221b2e9716c1478 100644 (file)
--- a/arch/mips/netlogic/dts/xlp_evp.dts
+++ b/arch/mips/netlogic/dts/xlp_evp.dts
@@ -20,7 +20,7 @@
                #address-cells = <2>;
                #size-cells = <1>;
                compatible = "simple-bus";
                #address-cells = <2>;
                #size-cells = <1>;
                compatible = "simple-bus";

-               ranges = <0 0  0 0x18000000  0x04000000   // PCIe CFG
+               ranges = <0 0  0 0x18000000  0x04000000   // PCIe CFG

                          1 0  0 0x16000000  0x01000000>; // GBU chipselects
 
                serial0: serial@30000 {
                          1 0  0 0x16000000  0x01000000>; // GBU chipselects
 
                serial0: serial@30000 {

diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c
index 529e74742d9fc370590f6898c82c79044367cd07..c68fd4026104b7ed4db04d21ae8d86753fa71266 100644 (file)
--- a/arch/mips/netlogic/xlp/nlm_hal.c
+++ b/arch/mips/netlogic/xlp/nlm_hal.c
@@ -111,8 +111,8 @@ unsigned int nlm_get_core_frequency(int node, int core)
        dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
        pll_divf = ((rstval >> 10) & 0x7f) + 1;
        pll_divr = ((rstval >> 8)  & 0x3) + 1;
        dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
        pll_divf = ((rstval >> 10) & 0x7f) + 1;
        pll_divr = ((rstval >> 8)  & 0x3) + 1;

-       ext_div  = ((rstval >> 30) & 0x3) + 1;
-       dfs_div  = ((dfsval >> (core * 4)) & 0xf) + 1;
+       ext_div  = ((rstval >> 30) & 0x3) + 1;
+       dfs_div  = ((dfsval >> (core * 4)) & 0xf) + 1;

 
        num = 800000000ULL * pll_divf;
        denom = 3 * pll_divr * ext_div * dfs_div;
 
        num = 800000000ULL * pll_divf;
        denom = 3 * pll_divr * ext_div * dfs_div;

diff --git a/arch/mips/netlogic/xlp/usb-init.c b/arch/mips/netlogic/xlp/usb-init.c
index dbe083a93538b2079806ce587eab66e0c117ebbc..1d0b66c62fd1beed8f4f601a380170bcb16c17df 100644 (file)
--- a/arch/mips/netlogic/xlp/usb-init.c
+++ b/arch/mips/netlogic/xlp/usb-init.c
@@ -52,7 +52,7 @@ static void nlm_usb_intr_en(int node, int port)
        port_addr = nlm_get_usb_regbase(node, port);
        val = nlm_read_usb_reg(port_addr, USB_INT_EN);
        val = USB_CTRL_INTERRUPT_EN  | USB_OHCI_INTERRUPT_EN |
        port_addr = nlm_get_usb_regbase(node, port);
        val = nlm_read_usb_reg(port_addr, USB_INT_EN);
        val = USB_CTRL_INTERRUPT_EN  | USB_OHCI_INTERRUPT_EN |

-               USB_OHCI_INTERRUPT1_EN | USB_CTRL_INTERRUPT_EN  |
+               USB_OHCI_INTERRUPT1_EN | USB_CTRL_INTERRUPT_EN  |

                USB_OHCI_INTERRUPT_EN | USB_OHCI_INTERRUPT2_EN;
        nlm_write_usb_reg(port_addr, USB_INT_EN, val);
 }
                USB_OHCI_INTERRUPT_EN | USB_OHCI_INTERRUPT2_EN;
        nlm_write_usb_reg(port_addr, USB_INT_EN, val);
 }

diff --git a/arch/mips/netlogic/xlr/fmn-config.c b/arch/mips/netlogic/xlr/fmn-config.c
index bed2cffa10083e41f94a5c27cb1572bb74c33a5e..f5bddf95bf244fab013b4511a84412756d5245f4 100644 (file)
--- a/arch/mips/netlogic/xlr/fmn-config.c
+++ b/arch/mips/netlogic/xlr/fmn-config.c
@@ -164,8 +164,8 @@ static void setup_cpu_fmninfo(struct xlr_fmn_info *cpu, int num_core)
        int i, j;
 
        for (i = 0; i < num_core; i++) {
        int i, j;
 
        for (i = 0; i < num_core; i++) {

-               cpu[i].start_stn_id     = (8 * i);
-               cpu[i].end_stn_id       = (8 * i + 8);
+               cpu[i].start_stn_id     = (8 * i);
+               cpu[i].end_stn_id       = (8 * i + 8);

 
                for (j = cpu[i].start_stn_id; j < cpu[i].end_stn_id; j++)
                        xlr_board_fmn_config.bucket_size[j] = 32;
 
                for (j = cpu[i].start_stn_id; j < cpu[i].end_stn_id; j++)
                        xlr_board_fmn_config.bucket_size[j] = 32;

diff --git a/arch/mips/netlogic/xlr/platform-flash.c b/arch/mips/netlogic/xlr/platform-flash.c
index 340ab1601c4292f739db3ed6838b80b35e2935af..6d3c727e0ef8477deab2d4049c027938af09d72b 100644 (file)
--- a/arch/mips/netlogic/xlr/platform-flash.c
+++ b/arch/mips/netlogic/xlr/platform-flash.c
@@ -36,7 +36,7 @@ static struct mtd_partition xlr_nor_parts[] = {
        {
                .name = "User FS",
                .offset = 0x800000,
        {
                .name = "User FS",
                .offset = 0x800000,

-               .size   = MTDPART_SIZ_FULL,
+               .size   = MTDPART_SIZ_FULL,

        }
 };
 
        }
 };
 


@@ -46,13 +46,13 @@ static struct mtd_partition xlr_nor_parts[] = {
 static struct mtd_partition xlr_nand_parts[] = {
        {
                .name   = "Root Filesystem",
 static struct mtd_partition xlr_nand_parts[] = {
        {
                .name   = "Root Filesystem",

-               .offset = 64 * 64 * 2048,
+               .offset = 64 * 64 * 2048,

                .size   = 432 * 64 * 2048,
        },
        {
                .name   = "Home Filesystem",
                .size   = 432 * 64 * 2048,
        },
        {
                .name   = "Home Filesystem",

-               .offset = MTDPART_OFS_APPEND,
-               .size   = MTDPART_SIZ_FULL,
+               .offset = MTDPART_OFS_APPEND,
+               .size   = MTDPART_SIZ_FULL,

        },
 };
 
        },
 };
 


@@ -74,8 +74,8 @@ static struct platform_device xlr_nor_dev = {
        .dev    = {
                .platform_data  = &xlr_nor_data,
        },
        .dev    = {
                .platform_data  = &xlr_nor_data,
        },

-       .num_resources  = ARRAY_SIZE(xlr_nor_res),
-       .resource       = xlr_nor_res,
+       .num_resources  = ARRAY_SIZE(xlr_nor_res),
+       .resource       = xlr_nor_res,

 };
 
 const char *xlr_part_probes[] = { "cmdlinepart", NULL };
 };
 
 const char *xlr_part_probes[] = { "cmdlinepart", NULL };

diff --git a/arch/mips/netlogic/xlr/platform.c b/arch/mips/netlogic/xlr/platform.c
index 507230eeb7685e9292eb533e7932441db11e92e0..e287277d32b097658250d656f11b3c8eacc9fe6d 100644 (file)
--- a/arch/mips/netlogic/xlr/platform.c
+++ b/arch/mips/netlogic/xlr/platform.c
@@ -162,18 +162,18 @@ int xls_platform_usb_init(void)
        nlm_write_reg(usb_mmio, 50, 0x1f000000);
 
        /* Enable ports */
        nlm_write_reg(usb_mmio, 50, 0x1f000000);
 
        /* Enable ports */

-       nlm_write_reg(usb_mmio,  1, 0x07000500);
+       nlm_write_reg(usb_mmio,  1, 0x07000500);

 
        val = nlm_read_reg(gpio_mmio, 21);
        if (((val >> 22) & 0x01) == 0) {
                pr_info("Detected USB Device mode - Not supported!\n");
 
        val = nlm_read_reg(gpio_mmio, 21);
        if (((val >> 22) & 0x01) == 0) {
                pr_info("Detected USB Device mode - Not supported!\n");

-               nlm_write_reg(usb_mmio,  0, 0x01000000);
+               nlm_write_reg(usb_mmio,  0, 0x01000000);

                return 0;
        }
 
        pr_info("Detected USB Host mode - Adding XLS USB devices.\n");
        /* Clear reset, host mode */
                return 0;
        }
 
        pr_info("Detected USB Host mode - Adding XLS USB devices.\n");
        /* Clear reset, host mode */

-       nlm_write_reg(usb_mmio,  0, 0x02000000);
+       nlm_write_reg(usb_mmio,  0, 0x02000000);

 
        /* Memory resource for various XLS usb ports */
        usb_mmio = nlm_mmio_base(NETLOGIC_IO_USB_0_OFFSET);
 
        /* Memory resource for various XLS usb ports */
        usb_mmio = nlm_mmio_base(NETLOGIC_IO_USB_0_OFFSET);


@@ -221,8 +221,8 @@ static struct resource i2c_resources[] = {
 };
 
 static struct platform_device nlm_xlr_i2c_1 = {
 };
 
 static struct platform_device nlm_xlr_i2c_1 = {

-       .name           = "xlr-i2cbus",
-       .id             = 1,
+       .name           = "xlr-i2cbus",
+       .id             = 1,

        .num_resources  = 1,
        .resource       = i2c_resources,
 };
        .num_resources  = 1,
        .resource       = i2c_resources,
 };

diff --git a/arch/mips/netlogic/xlr/setup.c b/arch/mips/netlogic/xlr/setup.c
index c5ce6992ac4c7086aea4167a7460723a5d0cb7be..f088efb8fe4cc1af593fa07f78dc920cb76a05b5 100644 (file)
--- a/arch/mips/netlogic/xlr/setup.c
+++ b/arch/mips/netlogic/xlr/setup.c
@@ -163,7 +163,7 @@ static void prom_add_memory(void)
 {
        struct nlm_boot_mem_map *bootm;
        u64 start, size;
 {
        struct nlm_boot_mem_map *bootm;
        u64 start, size;

-       u64 pref_backup = 512;  /* avoid pref walking beyond end */
+       u64 pref_backup = 512;  /* avoid pref walking beyond end */

        int i;
 
        bootm = (void *)(long)nlm_prom_info.psb_mem_map;
        int i;
 
        bootm = (void *)(long)nlm_prom_info.psb_mem_map;

diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index e32db1ff02c7ee4020f7d5e1c199f966bfc585ed..56f2cf221c7d8411693e1cd25b2a9a975a255eb8 100644 (file)
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -27,10 +27,10 @@ static int op_mips_setup(void)
        /* Pre-compute the values to stuff in the hardware registers.  */
        model->reg_setup(ctr);
 
        /* Pre-compute the values to stuff in the hardware registers.  */
        model->reg_setup(ctr);
 

-       /* Configure the registers on all cpus.  */
+       /* Configure the registers on all cpus.  */

        on_each_cpu(model->cpu_setup, NULL, 1);
 
        on_each_cpu(model->cpu_setup, NULL, 1);
 

-        return 0;
+       return 0;

 }
 
 static int op_mips_create_files(struct super_block *sb, struct dentry *root)
 }
 
 static int op_mips_create_files(struct super_block *sb, struct dentry *root)


@@ -110,7 +110,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
 
        ops->create_files       = op_mips_create_files;
        ops->setup              = op_mips_setup;
 
        ops->create_files       = op_mips_create_files;
        ops->setup              = op_mips_setup;

-       //ops->shutdown         = op_mips_shutdown;
+       //ops->shutdown         = op_mips_shutdown;

        ops->start              = op_mips_start;
        ops->stop               = op_mips_stop;
        ops->cpu_type           = lmodel->cpu_type;
        ops->start              = op_mips_start;
        ops->stop               = op_mips_stop;
        ops->cpu_type           = lmodel->cpu_type;

diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c
index 60d3ea602118bbbbba97a9c2ceb28f4c043a870e..b249ec0bebb2ad52ae6b886e81195af44ae5c2b3 100644 (file)
--- a/arch/mips/oprofile/op_model_loongson2.c
+++ b/arch/mips/oprofile/op_model_loongson2.c
@@ -18,13 +18,13 @@
 
 #define LOONGSON2_CPU_TYPE     "mips/loongson2"
 
 
 #define LOONGSON2_CPU_TYPE     "mips/loongson2"
 

-#define LOONGSON2_PERFCNT_OVERFLOW             (1ULL   << 31)
+#define LOONGSON2_PERFCNT_OVERFLOW             (1ULL   << 31)

 
 #define LOONGSON2_PERFCTRL_EXL                 (1UL    <<  0)
 
 #define LOONGSON2_PERFCTRL_EXL                 (1UL    <<  0)

-#define LOONGSON2_PERFCTRL_KERNEL              (1UL    <<  1)
-#define LOONGSON2_PERFCTRL_SUPERVISOR          (1UL    <<  2)
-#define LOONGSON2_PERFCTRL_USER                        (1UL    <<  3)
-#define LOONGSON2_PERFCTRL_ENABLE              (1UL    <<  4)
+#define LOONGSON2_PERFCTRL_KERNEL              (1UL    <<  1)
+#define LOONGSON2_PERFCTRL_SUPERVISOR          (1UL    <<  2)
+#define LOONGSON2_PERFCTRL_USER                        (1UL    <<  3)
+#define LOONGSON2_PERFCTRL_ENABLE              (1UL    <<  4)

 #define LOONGSON2_PERFCTRL_EVENT(idx, event) \
        (((event) & 0x0f) << ((idx) ? 9 : 5))
 
 #define LOONGSON2_PERFCTRL_EVENT(idx, event) \
        (((event) & 0x0f) << ((idx) ? 9 : 5))
 

diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 786254630403ab62e02dde6197038f3b976cc9e4..1cfab95755b96bcf0297bc993a804a4a3b2b5c83 100644 (file)
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -14,25 +14,25 @@
 
 #include "op_impl.h"
 
 
 #include "op_impl.h"
 

-#define M_PERFCTL_EXL                  (1UL      <<  0)
-#define M_PERFCTL_KERNEL               (1UL      <<  1)
-#define M_PERFCTL_SUPERVISOR           (1UL      <<  2)
-#define M_PERFCTL_USER                 (1UL      <<  3)
-#define M_PERFCTL_INTERRUPT_ENABLE     (1UL      <<  4)
+#define M_PERFCTL_EXL                  (1UL      <<  0)
+#define M_PERFCTL_KERNEL               (1UL      <<  1)
+#define M_PERFCTL_SUPERVISOR           (1UL      <<  2)
+#define M_PERFCTL_USER                 (1UL      <<  3)
+#define M_PERFCTL_INTERRUPT_ENABLE     (1UL      <<  4)

 #define M_PERFCTL_EVENT(event)         (((event) & 0x3ff)  << 5)
 #define M_PERFCTL_EVENT(event)         (((event) & 0x3ff)  << 5)

-#define M_PERFCTL_VPEID(vpe)           ((vpe)    << 16)
+#define M_PERFCTL_VPEID(vpe)           ((vpe)    << 16)

 #define M_PERFCTL_MT_EN(filter)                ((filter) << 20)
 #define M_PERFCTL_MT_EN(filter)                ((filter) << 20)

-#define    M_TC_EN_ALL                 M_PERFCTL_MT_EN(0)
-#define    M_TC_EN_VPE                 M_PERFCTL_MT_EN(1)
-#define    M_TC_EN_TC                  M_PERFCTL_MT_EN(2)
-#define M_PERFCTL_TCID(tcid)           ((tcid)   << 22)
-#define M_PERFCTL_WIDE                 (1UL      << 30)
-#define M_PERFCTL_MORE                 (1UL      << 31)
+#define           M_TC_EN_ALL                  M_PERFCTL_MT_EN(0)
+#define           M_TC_EN_VPE                  M_PERFCTL_MT_EN(1)
+#define           M_TC_EN_TC                   M_PERFCTL_MT_EN(2)
+#define M_PERFCTL_TCID(tcid)           ((tcid)   << 22)
+#define M_PERFCTL_WIDE                 (1UL      << 30)
+#define M_PERFCTL_MORE                 (1UL      << 31)

 
 

-#define M_COUNTER_OVERFLOW             (1UL      << 31)
+#define M_COUNTER_OVERFLOW             (1UL      << 31)

 
 /* Netlogic XLR specific, count events in all threads in a core */
 
 /* Netlogic XLR specific, count events in all threads in a core */

-#define M_PERFCTL_COUNT_ALL_THREADS    (1UL      << 13)
+#define M_PERFCTL_COUNT_ALL_THREADS    (1UL      << 13)

 
 static int (*save_perf_irq)(void);
 
 
 static int (*save_perf_irq)(void);
 


@@ -143,7 +143,7 @@ static struct mipsxx_register_config {
        unsigned int counter[4];
 } reg;
 
        unsigned int counter[4];
 } reg;
 

-/* Compute all of the registers in preparation for enabling profiling.  */
+/* Compute all of the registers in preparation for enabling profiling. */

 
 static void mipsxx_reg_setup(struct op_counter_config *ctr)
 {
 
 static void mipsxx_reg_setup(struct op_counter_config *ctr)
 {


@@ -159,7 +159,7 @@ static void mipsxx_reg_setup(struct op_counter_config *ctr)
                        continue;
 
                reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) |
                        continue;
 
                reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) |

-                                M_PERFCTL_INTERRUPT_ENABLE;
+                                M_PERFCTL_INTERRUPT_ENABLE;

                if (ctr[i].kernel)
                        reg.control[i] |= M_PERFCTL_KERNEL;
                if (ctr[i].user)
                if (ctr[i].kernel)
                        reg.control[i] |= M_PERFCTL_KERNEL;
                if (ctr[i].user)


@@ -172,7 +172,7 @@ static void mipsxx_reg_setup(struct op_counter_config *ctr)
        }
 }
 
        }
 }
 

-/* Program all of the registers in preparation for enabling profiling.  */
+/* Program all of the registers in preparation for enabling profiling. */

 
 static void mipsxx_cpu_setup(void *args)
 {
 
 static void mipsxx_cpu_setup(void *args)
 {

diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 998554f37a176c62dc6b8a4d628b72bc80856740..2cb1d315d22507adefe32873747afad3e5fdaf30 100644 (file)
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -54,10 +54,10 @@ obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
 obj-$(CONFIG_ZAO_CAPCELLA)     += fixup-capcella.o
 obj-$(CONFIG_WR_PPMC)          += fixup-wrppmc.o
 obj-$(CONFIG_MIKROTIK_RB532)   += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
 obj-$(CONFIG_ZAO_CAPCELLA)     += fixup-capcella.o
 obj-$(CONFIG_WR_PPMC)          += fixup-wrppmc.o
 obj-$(CONFIG_MIKROTIK_RB532)   += pci-rc32434.o ops-rc32434.o fixup-rc32434.o

-obj-$(CONFIG_CPU_CAVIUM_OCTEON)        += pci-octeon.o pcie-octeon.o
+obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o

 obj-$(CONFIG_CPU_XLR)          += pci-xlr.o
 obj-$(CONFIG_CPU_XLP)          += pci-xlp.o
 
 ifdef CONFIG_PCI_MSI
 obj-$(CONFIG_CPU_XLR)          += pci-xlr.o
 obj-$(CONFIG_CPU_XLP)          += pci-xlp.o
 
 ifdef CONFIG_PCI_MSI

-obj-$(CONFIG_CPU_CAVIUM_OCTEON)        += msi-octeon.o
+obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o

 endif
 endif

diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index 9553b14002dda51a757cf06ccb0bca5483b86c1a..a138e8ee5cfcf7bb8c2025202ea3e728c4240476 100644 (file)
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -94,14 +94,14 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev)
         * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
         *
         * On all machines prior to Q2, we had the STOP line disconnected
         * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
         *
         * On all machines prior to Q2, we had the STOP line disconnected

-        * from Galileo to VIA on PCI.  The new Galileo does not function
+        * from Galileo to VIA on PCI.  The new Galileo does not function

         * correctly unless we have it connected.
         *
         * Therefore we must set the disconnect/retry cycle values to
         * something sensible when using the new Galileo.
         */
 
         * correctly unless we have it connected.
         *
         * Therefore we must set the disconnect/retry cycle values to
         * something sensible when using the new Galileo.
         */
 

-       printk(KERN_INFO "Galileo: revision %u\n", dev->revision);
+       printk(KERN_INFO "Galileo: revision %u\n", dev->revision);

 
 #if 0
        if (dev->revision >= 0x10) {
 
 #if 0
        if (dev->revision >= 0x10) {


@@ -149,30 +149,30 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
         qube_raq_via_board_id_fixup);
 
 static char irq_tab_qube1[] __initdata = {
         qube_raq_via_board_id_fixup);
 
 static char irq_tab_qube1[] __initdata = {

-  [COBALT_PCICONF_CPU]     = 0,
-  [COBALT_PCICONF_ETH0]    = QUBE1_ETH0_IRQ,
+  [COBALT_PCICONF_CPU]    = 0,
+  [COBALT_PCICONF_ETH0]           = QUBE1_ETH0_IRQ,

   [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
   [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,

-  [COBALT_PCICONF_VIA]     = 0,
+  [COBALT_PCICONF_VIA]    = 0,

   [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
   [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,

-  [COBALT_PCICONF_ETH1]    = 0
+  [COBALT_PCICONF_ETH1]           = 0

 };
 
 static char irq_tab_cobalt[] __initdata = {
 };
 
 static char irq_tab_cobalt[] __initdata = {

-  [COBALT_PCICONF_CPU]     = 0,
-  [COBALT_PCICONF_ETH0]    = ETH0_IRQ,
+  [COBALT_PCICONF_CPU]    = 0,
+  [COBALT_PCICONF_ETH0]           = ETH0_IRQ,

   [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
   [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,

-  [COBALT_PCICONF_VIA]     = 0,
+  [COBALT_PCICONF_VIA]    = 0,

   [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
   [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,

-  [COBALT_PCICONF_ETH1]    = ETH1_IRQ
+  [COBALT_PCICONF_ETH1]           = ETH1_IRQ

 };
 
 static char irq_tab_raq2[] __initdata = {
 };
 
 static char irq_tab_raq2[] __initdata = {

-  [COBALT_PCICONF_CPU]     = 0,
-  [COBALT_PCICONF_ETH0]    = ETH0_IRQ,
+  [COBALT_PCICONF_CPU]    = 0,
+  [COBALT_PCICONF_ETH0]           = ETH0_IRQ,

   [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,
   [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,

-  [COBALT_PCICONF_VIA]     = 0,
+  [COBALT_PCICONF_VIA]    = 0,

   [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
   [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,

-  [COBALT_PCICONF_ETH1]    = ETH1_IRQ
+  [COBALT_PCICONF_ETH1]           = ETH1_IRQ

 };
 
 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 };
 
 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)

diff --git a/arch/mips/pci/fixup-emma2rh.c b/arch/mips/pci/fixup-emma2rh.c
index beaec32b02e54f3b77a2a3d01dbb0fdb5526e674..19caf775c20645ada7f1bbc86777c2bd45b23246 100644 (file)
--- a/arch/mips/pci/fixup-emma2rh.c
+++ b/arch/mips/pci/fixup-emma2rh.c
@@ -42,7 +42,7 @@
  *
  */
 
  *
  */
 

-#define        MAX_SLOT_NUM 10
+#define MAX_SLOT_NUM 10

 static unsigned char irq_map[][5] __initdata = {
        [3] = {0, MARKEINS_PCI_IRQ_INTB, MARKEINS_PCI_IRQ_INTC,
               MARKEINS_PCI_IRQ_INTD, 0,},
 static unsigned char irq_map[][5] __initdata = {
        [3] = {0, MARKEINS_PCI_IRQ_INTB, MARKEINS_PCI_IRQ_INTC,
               MARKEINS_PCI_IRQ_INTD, 0,},

diff --git a/arch/mips/pci/fixup-fuloong2e.c b/arch/mips/pci/fixup-fuloong2e.c
index 63ab4a042cd6e4a4f5dec5f0beafb548000b6e0d..50da773faedee8fc5850480857ea5e36a78f24c0 100644 (file)
--- a/arch/mips/pci/fixup-fuloong2e.c
+++ b/arch/mips/pci/fixup-fuloong2e.c
@@ -6,9 +6,9 @@
  * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
  * Author: Fuxin Zhang, zhangfx@lemote.com
  *
  * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
  * Author: Fuxin Zhang, zhangfx@lemote.com
  *

- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  This program is free software; you can redistribute         it and/or modify it
+ *  under  the terms of         the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your

  *  option) any later version.
  */
 #include <linux/init.h>
  *  option) any later version.
  */
 #include <linux/init.h>


@@ -152,7 +152,7 @@ static void loongson2e_686b_func1_fixup(struct pci_dev *pdev)
        /* disable read prefetch/write post buffers */
        pci_write_config_byte(pdev, 0x41, 0x02);
 
        /* disable read prefetch/write post buffers */
        pci_write_config_byte(pdev, 0x41, 0x02);
 

-       /* use 3/4 as fifo thresh hold  */
+       /* use 3/4 as fifo thresh hold  */

        pci_write_config_byte(pdev, 0x43, 0x0a);
        pci_write_config_byte(pdev, 0x44, 0x00);
 
        pci_write_config_byte(pdev, 0x43, 0x0a);
        pci_write_config_byte(pdev, 0x44, 0x00);
 

diff --git a/arch/mips/pci/fixup-ip32.c b/arch/mips/pci/fixup-ip32.c
index 190fffd08d3e495a1cd42e6e0ebbdd2e3081045a..133685e215ee6a2f02a5a244e04e08464543273d 100644 (file)
--- a/arch/mips/pci/fixup-ip32.c
+++ b/arch/mips/pci/fixup-ip32.c
@@ -22,13 +22,13 @@
 #define INTC   MACEPCI_SHARED1_IRQ
 #define INTD   MACEPCI_SHARED2_IRQ
 static char irq_tab_mace[][5] __initdata = {
 #define INTC   MACEPCI_SHARED1_IRQ
 #define INTD   MACEPCI_SHARED2_IRQ
 static char irq_tab_mace[][5] __initdata = {

-      /* Dummy  INT#A  INT#B  INT#C  INT#D */
-       {0,         0,     0,     0,     0}, /* This is placeholder row - never used */
-       {0,     SCSI0, SCSI0, SCSI0, SCSI0},
-       {0,     SCSI1, SCSI1, SCSI1, SCSI1},
-       {0,     INTA0,  INTB,  INTC,  INTD},
-       {0,     INTA1,  INTC,  INTD,  INTB},
-       {0,     INTA2,  INTD,  INTB,  INTC},
+      /* Dummy INT#A  INT#B  INT#C  INT#D */
+       {0,         0,     0,     0,     0}, /* This is placeholder row - never used */
+       {0,     SCSI0, SCSI0, SCSI0, SCSI0},
+       {0,     SCSI1, SCSI1, SCSI1, SCSI1},
+       {0,     INTA0,  INTB,  INTC,  INTD},
+       {0,     INTA1,  INTC,  INTD,  INTB},
+       {0,     INTA2,  INTD,  INTB,  INTC},

 };
 
 
 };
 
 

diff --git a/arch/mips/pci/fixup-lemote2f.c b/arch/mips/pci/fixup-lemote2f.c
index 519daaebb5da6cae81e4fedd5ea76a557f8fc464..95ab9a1bd0107384a3faa8e45c9f2872f7c561df 100644 (file)
--- a/arch/mips/pci/fixup-lemote2f.c
+++ b/arch/mips/pci/fixup-lemote2f.c
@@ -31,7 +31,7 @@
 
 /* all the pci device has the PCIA pin, check the datasheet. */
 static char irq_tab[][5] __initdata = {
 
 /* all the pci device has the PCIA pin, check the datasheet. */
 static char irq_tab[][5] __initdata = {

-       /*      INTA    INTB    INTC    INTD */
+       /*      INTA    INTB    INTC    INTD */

        {0, 0, 0, 0, 0},        /*  11: Unused */
        {0, 0, 0, 0, 0},        /*  12: Unused */
        {0, 0, 0, 0, 0},        /*  13: Unused */
        {0, 0, 0, 0, 0},        /*  11: Unused */
        {0, 0, 0, 0, 0},        /*  12: Unused */
        {0, 0, 0, 0, 0},        /*  13: Unused */


@@ -69,15 +69,15 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
                case 2:
                        pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
                                              CS5536_IDE_INTR);
                case 2:
                        pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
                                              CS5536_IDE_INTR);

-                       return CS5536_IDE_INTR; /*  for IDE */
+                       return CS5536_IDE_INTR; /*  for IDE */

                case 3:
                        pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
                                              CS5536_ACC_INTR);
                case 3:
                        pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
                                              CS5536_ACC_INTR);

-                       return CS5536_ACC_INTR; /*  for AUDIO */
-               case 4: /*  for OHCI */
-               case 5: /*  for EHCI */
-               case 6: /*  for UDC */
-               case 7: /*  for OTG */
+                       return CS5536_ACC_INTR; /*  for AUDIO */
+               case 4: /*  for OHCI */
+               case 5: /*  for EHCI */
+               case 6: /*  for UDC */
+               case 7: /*  for OTG */

                        pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
                                              CS5536_USB_INTR);
                        return CS5536_USB_INTR;
                        pci_write_config_byte(dev, PCI_INTERRUPT_LINE,
                                              CS5536_USB_INTR);
                        return CS5536_USB_INTR;

diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c
index 75d03f6be3bde7fcc59cb65e45518384560ae5cf..07ada7f8441ead44606e732f179a9d2dc4d0e00e 100644 (file)
--- a/arch/mips/pci/fixup-malta.c
+++ b/arch/mips/pci/fixup-malta.c
@@ -12,7 +12,7 @@ static char pci_irq[5] = {
 };
 
 static char irq_tab[][5] __initdata = {
 };
 
 static char irq_tab[][5] __initdata = {

-       /*      INTA    INTB    INTC    INTD */
+       /*      INTA    INTB    INTC    INTD */

        {0,     0,      0,      0,      0 },    /*  0: GT64120 PCI bridge */
        {0,     0,      0,      0,      0 },    /*  1: Unused */
        {0,     0,      0,      0,      0 },    /*  2: Unused */
        {0,     0,      0,      0,      0 },    /*  0: GT64120 PCI bridge */
        {0,     0,      0,      0,      0 },    /*  1: Unused */
        {0,     0,      0,      0,      0 },    /*  2: Unused */


@@ -23,7 +23,7 @@ static char irq_tab[][5] __initdata = {
        {0,     0,      0,      0,      0 },    /*  7: Unused */
        {0,     0,      0,      0,      0 },    /*  8: Unused */
        {0,     0,      0,      0,      0 },    /*  9: Unused */
        {0,     0,      0,      0,      0 },    /*  7: Unused */
        {0,     0,      0,      0,      0 },    /*  8: Unused */
        {0,     0,      0,      0,      0 },    /*  9: Unused */

-       {0,     0,      0,      0,      PCID }, /* 10: PIIX4 USB */
+       {0,     0,      0,      0,      PCID }, /* 10: PIIX4 USB */

        {0,     PCIB,   0,      0,      0 },    /* 11: AMD 79C973 Ethernet */
        {0,     PCIC,   0,      0,      0 },    /* 12: Crystal 4281 Sound */
        {0,     0,      0,      0,      0 },    /* 13: Unused */
        {0,     PCIB,   0,      0,      0 },    /* 11: AMD 79C973 Ethernet */
        {0,     PCIC,   0,      0,      0 },    /* 12: Crystal 4281 Sound */
        {0,     0,      0,      0,      0 },    /* 13: Unused */


@@ -31,9 +31,9 @@ static char irq_tab[][5] __initdata = {
        {0,     0,      0,      0,      0 },    /* 15: Unused */
        {0,     0,      0,      0,      0 },    /* 16: Unused */
        {0,     0,      0,      0,      0 },    /* 17: Bonito/SOC-it PCI Bridge*/
        {0,     0,      0,      0,      0 },    /* 15: Unused */
        {0,     0,      0,      0,      0 },    /* 16: Unused */
        {0,     0,      0,      0,      0 },    /* 17: Bonito/SOC-it PCI Bridge*/

-       {0,     PCIA,   PCIB,   PCIC,   PCID }, /* 18: PCI Slot 1 */
-       {0,     PCIB,   PCIC,   PCID,   PCIA }, /* 19: PCI Slot 2 */
-       {0,     PCIC,   PCID,   PCIA,   PCIB }, /* 20: PCI Slot 3 */
+       {0,     PCIA,   PCIB,   PCIC,   PCID }, /* 18: PCI Slot 1 */
+       {0,     PCIB,   PCIC,   PCID,   PCIA }, /* 19: PCI Slot 2 */
+       {0,     PCIC,   PCID,   PCIA,   PCIB }, /* 20: PCI Slot 3 */

        {0,     PCID,   PCIA,   PCIB,   PCIC }  /* 21: PCI Slot 4 */
 };
 
        {0,     PCID,   PCIA,   PCIB,   PCIC }  /* 21: PCI Slot 4 */
 };
 


@@ -54,8 +54,8 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev)
 {
        unsigned char reg_val;
        static int piixirqmap[16] = {  /* PIIX PIRQC[A:D] irq mappings */
 {
        unsigned char reg_val;
        static int piixirqmap[16] = {  /* PIIX PIRQC[A:D] irq mappings */

-               0,  0,  0,  3,
-               4,  5,  6,  7,
+               0,  0,  0,  3,
+               4,  5,  6,  7,

                0,  9, 10, 11,
                12, 0, 14, 15
        };
                0,  9, 10, 11,
                12, 0, 14, 15
        };

diff --git a/arch/mips/pci/fixup-pmcmsp.c b/arch/mips/pci/fixup-pmcmsp.c
index 65735b1b7665b08291fc11f30f0fcac66e5ef522..fab405c21c2f76f856af004fab4e88e68f81cef2 100644 (file)
--- a/arch/mips/pci/fixup-pmcmsp.c
+++ b/arch/mips/pci/fixup-pmcmsp.c
@@ -48,117 +48,117 @@
 #if defined(CONFIG_PMC_MSP7120_GW)
 /* Garibaldi Board IRQ wiring to PCI slots */
 static char irq_tab[][5] __initdata = {
 #if defined(CONFIG_PMC_MSP7120_GW)
 /* Garibaldi Board IRQ wiring to PCI slots */
 static char irq_tab[][5] __initdata = {

-       /* INTA    INTB    INTC    INTD */
-       {0,     0,      0,      0,      0 },    /*    (AD[0]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[1]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[2]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[3]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[4]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[5]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[6]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[7]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[8]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[9]): Unused */
-       {0,     0,      0,      0,      0 },    /*  0 (AD[10]): Unused */
-       {0,     0,      0,      0,      0 },    /*  1 (AD[11]): Unused */
-       {0,     0,      0,      0,      0 },    /*  2 (AD[12]): Unused */
-       {0,     0,      0,      0,      0 },    /*  3 (AD[13]): Unused */
-       {0,     0,      0,      0,      0 },    /*  4 (AD[14]): Unused */
-       {0,     0,      0,      0,      0 },    /*  5 (AD[15]): Unused */
-       {0,     0,      0,      0,      0 },    /*  6 (AD[16]): Unused */
-       {0,     0,      0,      0,      0 },    /*  7 (AD[17]): Unused */
-       {0,     0,      0,      0,      0 },    /*  8 (AD[18]): Unused */
-       {0,     0,      0,      0,      0 },    /*  9 (AD[19]): Unused */
-       {0,     0,      0,      0,      0 },    /* 10 (AD[20]): Unused */
-       {0,     0,      0,      0,      0 },    /* 11 (AD[21]): Unused */
-       {0,     0,      0,      0,      0 },    /* 12 (AD[22]): Unused */
-       {0,     0,      0,      0,      0 },    /* 13 (AD[23]): Unused */
-       {0,     0,      0,      0,      0 },    /* 14 (AD[24]): Unused */
-       {0,     0,      0,      0,      0 },    /* 15 (AD[25]): Unused */
-       {0,     0,      0,      0,      0 },    /* 16 (AD[26]): Unused */
-       {0,     0,      0,      0,      0 },    /* 17 (AD[27]): Unused */
-       {0,     IRQ4,   IRQ4,   0,      0 },    /* 18 (AD[28]): slot 0 */
-       {0,     0,      0,      0,      0 },    /* 19 (AD[29]): Unused */
-       {0,     IRQ5,   IRQ5,   0,      0 },    /* 20 (AD[30]): slot 1 */
-       {0,     IRQ6,   IRQ6,   0,      0 }     /* 21 (AD[31]): slot 2 */
+       /* INTA    INTB    INTC    INTD */
+       {0,     0,      0,      0,      0 },    /*    (AD[0]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[1]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[2]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[3]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[4]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[5]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[6]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[7]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[8]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[9]): Unused */
+       {0,     0,      0,      0,      0 },    /*  0 (AD[10]): Unused */
+       {0,     0,      0,      0,      0 },    /*  1 (AD[11]): Unused */
+       {0,     0,      0,      0,      0 },    /*  2 (AD[12]): Unused */
+       {0,     0,      0,      0,      0 },    /*  3 (AD[13]): Unused */
+       {0,     0,      0,      0,      0 },    /*  4 (AD[14]): Unused */
+       {0,     0,      0,      0,      0 },    /*  5 (AD[15]): Unused */
+       {0,     0,      0,      0,      0 },    /*  6 (AD[16]): Unused */
+       {0,     0,      0,      0,      0 },    /*  7 (AD[17]): Unused */
+       {0,     0,      0,      0,      0 },    /*  8 (AD[18]): Unused */
+       {0,     0,      0,      0,      0 },    /*  9 (AD[19]): Unused */
+       {0,     0,      0,      0,      0 },    /* 10 (AD[20]): Unused */
+       {0,     0,      0,      0,      0 },    /* 11 (AD[21]): Unused */
+       {0,     0,      0,      0,      0 },    /* 12 (AD[22]): Unused */
+       {0,     0,      0,      0,      0 },    /* 13 (AD[23]): Unused */
+       {0,     0,      0,      0,      0 },    /* 14 (AD[24]): Unused */
+       {0,     0,      0,      0,      0 },    /* 15 (AD[25]): Unused */
+       {0,     0,      0,      0,      0 },    /* 16 (AD[26]): Unused */
+       {0,     0,      0,      0,      0 },    /* 17 (AD[27]): Unused */
+       {0,     IRQ4,   IRQ4,   0,      0 },    /* 18 (AD[28]): slot 0 */
+       {0,     0,      0,      0,      0 },    /* 19 (AD[29]): Unused */
+       {0,     IRQ5,   IRQ5,   0,      0 },    /* 20 (AD[30]): slot 1 */
+       {0,     IRQ6,   IRQ6,   0,      0 }     /* 21 (AD[31]): slot 2 */

 };
 
 #elif defined(CONFIG_PMC_MSP7120_EVAL)
 
 /* MSP7120 Eval Board IRQ wiring to PCI slots */
 static char irq_tab[][5] __initdata = {
 };
 
 #elif defined(CONFIG_PMC_MSP7120_EVAL)
 
 /* MSP7120 Eval Board IRQ wiring to PCI slots */
 static char irq_tab[][5] __initdata = {

-       /* INTA    INTB    INTC    INTD */
-       {0,     0,      0,      0,      0 },    /*    (AD[0]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[1]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[2]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[3]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[4]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[5]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[6]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[7]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[8]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[9]): Unused */
-       {0,     0,      0,      0,      0 },    /*  0 (AD[10]): Unused */
-       {0,     0,      0,      0,      0 },    /*  1 (AD[11]): Unused */
-       {0,     0,      0,      0,      0 },    /*  2 (AD[12]): Unused */
-       {0,     0,      0,      0,      0 },    /*  3 (AD[13]): Unused */
-       {0,     0,      0,      0,      0 },    /*  4 (AD[14]): Unused */
-       {0,     0,      0,      0,      0 },    /*  5 (AD[15]): Unused */
-       {0,     IRQ6,   IRQ6,   0,      0 },    /*  6 (AD[16]): slot 3 (mini) */
-       {0,     IRQ5,   IRQ5,   0,      0 },    /*  7 (AD[17]): slot 2 (mini) */
-       {0,     IRQ4,   IRQ4,   IRQ4,   IRQ4},  /*  8 (AD[18]): slot 0 (PCI) */
-       {0,     IRQ5,   IRQ5,   IRQ5,   IRQ5},  /*  9 (AD[19]): slot 1 (PCI) */
-       {0,     0,      0,      0,      0 },    /* 10 (AD[20]): Unused */
-       {0,     0,      0,      0,      0 },    /* 11 (AD[21]): Unused */
-       {0,     0,      0,      0,      0 },    /* 12 (AD[22]): Unused */
-       {0,     0,      0,      0,      0 },    /* 13 (AD[23]): Unused */
-       {0,     0,      0,      0,      0 },    /* 14 (AD[24]): Unused */
-       {0,     0,      0,      0,      0 },    /* 15 (AD[25]): Unused */
-       {0,     0,      0,      0,      0 },    /* 16 (AD[26]): Unused */
-       {0,     0,      0,      0,      0 },    /* 17 (AD[27]): Unused */
-       {0,     0,      0,      0,      0 },    /* 18 (AD[28]): Unused */
-       {0,     0,      0,      0,      0 },    /* 19 (AD[29]): Unused */
-       {0,     0,      0,      0,      0 },    /* 20 (AD[30]): Unused */
-       {0,     0,      0,      0,      0 }     /* 21 (AD[31]): Unused */
+       /* INTA    INTB    INTC    INTD */
+       {0,     0,      0,      0,      0 },    /*    (AD[0]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[1]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[2]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[3]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[4]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[5]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[6]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[7]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[8]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[9]): Unused */
+       {0,     0,      0,      0,      0 },    /*  0 (AD[10]): Unused */
+       {0,     0,      0,      0,      0 },    /*  1 (AD[11]): Unused */
+       {0,     0,      0,      0,      0 },    /*  2 (AD[12]): Unused */
+       {0,     0,      0,      0,      0 },    /*  3 (AD[13]): Unused */
+       {0,     0,      0,      0,      0 },    /*  4 (AD[14]): Unused */
+       {0,     0,      0,      0,      0 },    /*  5 (AD[15]): Unused */
+       {0,     IRQ6,   IRQ6,   0,      0 },    /*  6 (AD[16]): slot 3 (mini) */
+       {0,     IRQ5,   IRQ5,   0,      0 },    /*  7 (AD[17]): slot 2 (mini) */
+       {0,     IRQ4,   IRQ4,   IRQ4,   IRQ4},  /*  8 (AD[18]): slot 0 (PCI) */
+       {0,     IRQ5,   IRQ5,   IRQ5,   IRQ5},  /*  9 (AD[19]): slot 1 (PCI) */
+       {0,     0,      0,      0,      0 },    /* 10 (AD[20]): Unused */
+       {0,     0,      0,      0,      0 },    /* 11 (AD[21]): Unused */
+       {0,     0,      0,      0,      0 },    /* 12 (AD[22]): Unused */
+       {0,     0,      0,      0,      0 },    /* 13 (AD[23]): Unused */
+       {0,     0,      0,      0,      0 },    /* 14 (AD[24]): Unused */
+       {0,     0,      0,      0,      0 },    /* 15 (AD[25]): Unused */
+       {0,     0,      0,      0,      0 },    /* 16 (AD[26]): Unused */
+       {0,     0,      0,      0,      0 },    /* 17 (AD[27]): Unused */
+       {0,     0,      0,      0,      0 },    /* 18 (AD[28]): Unused */
+       {0,     0,      0,      0,      0 },    /* 19 (AD[29]): Unused */
+       {0,     0,      0,      0,      0 },    /* 20 (AD[30]): Unused */
+       {0,     0,      0,      0,      0 }     /* 21 (AD[31]): Unused */

 };
 
 #else
 
 /* Unknown board -- don't assign any IRQs */
 static char irq_tab[][5] __initdata = {
 };
 
 #else
 
 /* Unknown board -- don't assign any IRQs */
 static char irq_tab[][5] __initdata = {

-       /* INTA    INTB    INTC    INTD */
-       {0,     0,      0,      0,      0 },    /*    (AD[0]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[1]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[2]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[3]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[4]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[5]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[6]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[7]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[8]): Unused */
-       {0,     0,      0,      0,      0 },    /*    (AD[9]): Unused */
-       {0,     0,      0,      0,      0 },    /*  0 (AD[10]): Unused */
-       {0,     0,      0,      0,      0 },    /*  1 (AD[11]): Unused */
-       {0,     0,      0,      0,      0 },    /*  2 (AD[12]): Unused */
-       {0,     0,      0,      0,      0 },    /*  3 (AD[13]): Unused */
-       {0,     0,      0,      0,      0 },    /*  4 (AD[14]): Unused */
-       {0,     0,      0,      0,      0 },    /*  5 (AD[15]): Unused */
-       {0,     0,      0,      0,      0 },    /*  6 (AD[16]): Unused */
-       {0,     0,      0,      0,      0 },    /*  7 (AD[17]): Unused */
-       {0,     0,      0,      0,      0 },    /*  8 (AD[18]): Unused */
-       {0,     0,      0,      0,      0 },    /*  9 (AD[19]): Unused */
-       {0,     0,      0,      0,      0 },    /* 10 (AD[20]): Unused */
-       {0,     0,      0,      0,      0 },    /* 11 (AD[21]): Unused */
-       {0,     0,      0,      0,      0 },    /* 12 (AD[22]): Unused */
-       {0,     0,      0,      0,      0 },    /* 13 (AD[23]): Unused */
-       {0,     0,      0,      0,      0 },    /* 14 (AD[24]): Unused */
-       {0,     0,      0,      0,      0 },    /* 15 (AD[25]): Unused */
-       {0,     0,      0,      0,      0 },    /* 16 (AD[26]): Unused */
-       {0,     0,      0,      0,      0 },    /* 17 (AD[27]): Unused */
-       {0,     0,      0,      0,      0 },    /* 18 (AD[28]): Unused */
-       {0,     0,      0,      0,      0 },    /* 19 (AD[29]): Unused */
-       {0,     0,      0,      0,      0 },    /* 20 (AD[30]): Unused */
-       {0,     0,      0,      0,      0 }     /* 21 (AD[31]): Unused */
+       /* INTA    INTB    INTC    INTD */
+       {0,     0,      0,      0,      0 },    /*    (AD[0]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[1]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[2]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[3]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[4]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[5]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[6]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[7]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[8]): Unused */
+       {0,     0,      0,      0,      0 },    /*    (AD[9]): Unused */
+       {0,     0,      0,      0,      0 },    /*  0 (AD[10]): Unused */
+       {0,     0,      0,      0,      0 },    /*  1 (AD[11]): Unused */
+       {0,     0,      0,      0,      0 },    /*  2 (AD[12]): Unused */
+       {0,     0,      0,      0,      0 },    /*  3 (AD[13]): Unused */
+       {0,     0,      0,      0,      0 },    /*  4 (AD[14]): Unused */
+       {0,     0,      0,      0,      0 },    /*  5 (AD[15]): Unused */
+       {0,     0,      0,      0,      0 },    /*  6 (AD[16]): Unused */
+       {0,     0,      0,      0,      0 },    /*  7 (AD[17]): Unused */
+       {0,     0,      0,      0,      0 },    /*  8 (AD[18]): Unused */
+       {0,     0,      0,      0,      0 },    /*  9 (AD[19]): Unused */
+       {0,     0,      0,      0,      0 },    /* 10 (AD[20]): Unused */
+       {0,     0,      0,      0,      0 },    /* 11 (AD[21]): Unused */
+       {0,     0,      0,      0,      0 },    /* 12 (AD[22]): Unused */
+       {0,     0,      0,      0,      0 },    /* 13 (AD[23]): Unused */
+       {0,     0,      0,      0,      0 },    /* 14 (AD[24]): Unused */
+       {0,     0,      0,      0,      0 },    /* 15 (AD[25]): Unused */
+       {0,     0,      0,      0,      0 },    /* 16 (AD[26]): Unused */
+       {0,     0,      0,      0,      0 },    /* 17 (AD[27]): Unused */
+       {0,     0,      0,      0,      0 },    /* 18 (AD[28]): Unused */
+       {0,     0,      0,      0,      0 },    /* 19 (AD[29]): Unused */
+       {0,     0,      0,      0,      0 },    /* 20 (AD[30]): Unused */
+       {0,     0,      0,      0,      0 }     /* 21 (AD[31]): Unused */

 };
 #endif
 
 };
 #endif
 


@@ -168,14 +168,14 @@ static char irq_tab[][5] __initdata = {
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Perform platform specific device initialization at
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Perform platform specific device initialization at

- *               pci_enable_device() time.
- *               None are needed for the MSP7120 PCI Controller.
+ *              pci_enable_device() time.
+ *              None are needed for the MSP7120 PCI Controller.

  *
  *

- *  INPUTS:      dev     - structure describing the PCI device
+ *  INPUTS:     dev     - structure describing the PCI device

  *
  *

- *  OUTPUTS:     none
+ *  OUTPUTS:    none

  *
  *

- *  RETURNS:     PCIBIOS_SUCCESSFUL
+ *  RETURNS:    PCIBIOS_SUCCESSFUL

  *
  ****************************************************************************/
 int pcibios_plat_dev_init(struct pci_dev *dev)
  *
  ****************************************************************************/
 int pcibios_plat_dev_init(struct pci_dev *dev)


@@ -190,16 +190,16 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
  *
  *  DESCRIPTION: Perform board supplied PCI IRQ mapping routine.
  *
  *
  *  DESCRIPTION: Perform board supplied PCI IRQ mapping routine.
  *

- *  INPUTS:      dev     - unused
- *               slot    - PCI slot. Identified by which bit of the AD[] bus
- *                         drives the IDSEL line. AD[10] is 0, AD[31] is
- *                         slot 21.
- *               pin     - numbered using the scheme of the PCI_INTERRUPT_PIN
- *                         field of the config header.
+ *  INPUTS:     dev     - unused
+ *              slot    - PCI slot. Identified by which bit of the AD[] bus
+ *                        drives the IDSEL line. AD[10] is 0, AD[31] is
+ *                        slot 21.
+ *              pin     - numbered using the scheme of the PCI_INTERRUPT_PIN
+ *                        field of the config header.

  *
  *

- *  OUTPUTS:     none
+ *  OUTPUTS:    none

  *
  *

- *  RETURNS:     IRQ number
+ *  RETURNS:    IRQ number

  *
  ****************************************************************************/
 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  *
  ****************************************************************************/
 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)

diff --git a/arch/mips/pci/fixup-sni.c b/arch/mips/pci/fixup-sni.c
index 5c8a79bb26613a23cdbffd6319d6d90d3dee59dc..f67ebeeb42000bb5d4d73961d6bcc4d632375298 100644 (file)
--- a/arch/mips/pci/fixup-sni.c
+++ b/arch/mips/pci/fixup-sni.c
@@ -41,12 +41,12 @@
  * Logic CL-GD5434 VGA is device 3.
  */
 static char irq_tab_rm200[8][5] __initdata = {
  * Logic CL-GD5434 VGA is device 3.
  */
 static char irq_tab_rm200[8][5] __initdata = {

-       /*       INTA  INTB  INTC  INTD */
-       {     0,    0,    0,    0,    0 },      /* EISA bridge */
+       /*       INTA  INTB  INTC  INTD */
+       {     0,    0,    0,    0,    0 },      /* EISA bridge */

        {  SCSI, SCSI, SCSI, SCSI, SCSI },      /* SCSI */
        {  SCSI, SCSI, SCSI, SCSI, SCSI },      /* SCSI */

-       {   ETH,  ETH,  ETH,  ETH,  ETH },      /* Ethernet */
+       {   ETH,  ETH,  ETH,  ETH,  ETH },      /* Ethernet */

        {  INTB, INTB, INTB, INTB, INTB },      /* VGA */
        {  INTB, INTB, INTB, INTB, INTB },      /* VGA */

-       {     0,    0,    0,    0,    0 },      /* Unused */
+       {     0,    0,    0,    0,    0 },      /* Unused */

        {     0, INTB, INTC, INTD, INTA },      /* Slot 2 */
        {     0, INTC, INTD, INTA, INTB },      /* Slot 3 */
        {     0, INTD, INTA, INTB, INTC },      /* Slot 4 */
        {     0, INTB, INTC, INTD, INTA },      /* Slot 2 */
        {     0, INTC, INTD, INTA, INTB },      /* Slot 3 */
        {     0, INTD, INTA, INTB, INTC },      /* Slot 4 */


@@ -58,20 +58,20 @@ static char irq_tab_rm200[8][5] __initdata = {
  * The VGA card is optional for RM300 systems.
  */
 static char irq_tab_rm300d[8][5] __initdata = {
  * The VGA card is optional for RM300 systems.
  */
 static char irq_tab_rm300d[8][5] __initdata = {

-       /*       INTA  INTB  INTC  INTD */
-       {     0,    0,    0,    0,    0 },      /* EISA bridge */
+       /*       INTA  INTB  INTC  INTD */
+       {     0,    0,    0,    0,    0 },      /* EISA bridge */

        {  SCSI, SCSI, SCSI, SCSI, SCSI },      /* SCSI */
        {     0, INTC, INTD, INTA, INTB },      /* Slot 1 */
        {  INTB, INTB, INTB, INTB, INTB },      /* VGA */
        {  SCSI, SCSI, SCSI, SCSI, SCSI },      /* SCSI */
        {     0, INTC, INTD, INTA, INTB },      /* Slot 1 */
        {  INTB, INTB, INTB, INTB, INTB },      /* VGA */

-       {     0,    0,    0,    0,    0 },      /* Unused */
+       {     0,    0,    0,    0,    0 },      /* Unused */

        {     0, INTB, INTC, INTD, INTA },      /* Slot 2 */
        {     0, INTC, INTD, INTA, INTB },      /* Slot 3 */
        {     0, INTD, INTA, INTB, INTC },      /* Slot 4 */
 };
 
 static char irq_tab_rm300e[5][5] __initdata = {
        {     0, INTB, INTC, INTD, INTA },      /* Slot 2 */
        {     0, INTC, INTD, INTA, INTB },      /* Slot 3 */
        {     0, INTD, INTA, INTB, INTC },      /* Slot 4 */
 };
 
 static char irq_tab_rm300e[5][5] __initdata = {

-       /*       INTA  INTB  INTC  INTD */
-       {     0,    0,    0,    0,    0 },      /* HOST bridge */
+       /*       INTA  INTB  INTC  INTD */
+       {     0,    0,    0,    0,    0 },      /* HOST bridge */

        {  SCSI, SCSI, SCSI, SCSI, SCSI },      /* SCSI */
        {     0, INTC, INTD, INTA, INTB },      /* Bridge/i960 */
        {     0, INTD, INTA, INTB, INTC },      /* Slot 1 */
        {  SCSI, SCSI, SCSI, SCSI, SCSI },      /* SCSI */
        {     0, INTC, INTD, INTA, INTB },      /* Bridge/i960 */
        {     0, INTD, INTA, INTB, INTC },      /* Slot 1 */


@@ -97,30 +97,30 @@ static char irq_tab_rm300e[5][5] __initdata = {
 #define INTD   PCIT_IRQ_INTD
 
 static char irq_tab_pcit[13][5] __initdata = {
 #define INTD   PCIT_IRQ_INTD
 
 static char irq_tab_pcit[13][5] __initdata = {

-       /*       INTA  INTB  INTC  INTD */
-       {     0,     0,     0,     0,     0 },  /* HOST bridge */
+       /*       INTA  INTB  INTC  INTD */
+       {     0,     0,     0,     0,     0 },  /* HOST bridge */

        { SCSI0, SCSI0, SCSI0, SCSI0, SCSI0 },  /* SCSI */
        { SCSI1, SCSI1, SCSI1, SCSI1, SCSI1 },  /* SCSI */
        { SCSI0, SCSI0, SCSI0, SCSI0, SCSI0 },  /* SCSI */
        { SCSI1, SCSI1, SCSI1, SCSI1, SCSI1 },  /* SCSI */

-       {   ETH,   ETH,   ETH,   ETH,   ETH },  /* Ethernet */
-       {     0,  INTA,  INTB,  INTC,  INTD },  /* PCI-PCI bridge */
-       {     0,     0,     0,     0,     0 },  /* Unused */
-       {     0,     0,     0,     0,     0 },  /* Unused */
-       {     0,     0,     0,     0,     0 },  /* Unused */
-       {     0,  INTA,  INTB,  INTC,  INTD },  /* Slot 1 */
-       {     0,  INTB,  INTC,  INTD,  INTA },  /* Slot 2 */
-       {     0,  INTC,  INTD,  INTA,  INTB },  /* Slot 3 */
-       {     0,  INTD,  INTA,  INTB,  INTC },  /* Slot 4 */
-       {     0,  INTA,  INTB,  INTC,  INTD },  /* Slot 5 */
+       {   ETH,   ETH,   ETH,   ETH,   ETH },  /* Ethernet */
+       {     0,  INTA,  INTB,  INTC,  INTD },  /* PCI-PCI bridge */
+       {     0,     0,     0,     0,     0 },  /* Unused */
+       {     0,     0,     0,     0,     0 },  /* Unused */
+       {     0,     0,     0,     0,     0 },  /* Unused */
+       {     0,  INTA,  INTB,  INTC,  INTD },  /* Slot 1 */
+       {     0,  INTB,  INTC,  INTD,  INTA },  /* Slot 2 */
+       {     0,  INTC,  INTD,  INTA,  INTB },  /* Slot 3 */
+       {     0,  INTD,  INTA,  INTB,  INTC },  /* Slot 4 */
+       {     0,  INTA,  INTB,  INTC,  INTD },  /* Slot 5 */

 };
 
 static char irq_tab_pcit_cplus[13][5] __initdata = {
 };
 
 static char irq_tab_pcit_cplus[13][5] __initdata = {

-       /*       INTA  INTB  INTC  INTD */
-       {     0,     0,     0,     0,     0 },  /* HOST bridge */
-       {     0,  INTB,  INTC,  INTD,  INTA },  /* PCI Slot 9 */
-       {     0,     0,     0,     0,     0 },  /* PCI-EISA */
-       {     0,     0,     0,     0,     0 },  /* Unused */
-       {     0,  INTA,  INTB,  INTC,  INTD },  /* PCI-PCI bridge */
-       {     0,  INTB,  INTC,  INTD,  INTA },  /* fixup */
+       /*       INTA  INTB  INTC  INTD */
+       {     0,     0,     0,     0,     0 },  /* HOST bridge */
+       {     0,  INTB,  INTC,  INTD,  INTA },  /* PCI Slot 9 */
+       {     0,     0,     0,     0,     0 },  /* PCI-EISA */
+       {     0,     0,     0,     0,     0 },  /* Unused */
+       {     0,  INTA,  INTB,  INTC,  INTD },  /* PCI-PCI bridge */
+       {     0,  INTB,  INTC,  INTD,  INTA },  /* fixup */

 };
 
 static inline int is_rm300_revd(void)
 };
 
 static inline int is_rm300_revd(void)


@@ -146,18 +146,18 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
                }
                return irq_tab_pcit_cplus[slot][pin];
        case SNI_BRD_PCI_TOWER:
                }
                return irq_tab_pcit_cplus[slot][pin];
        case SNI_BRD_PCI_TOWER:

-               return irq_tab_pcit[slot][pin];
+               return irq_tab_pcit[slot][pin];

 
        case SNI_BRD_PCI_MTOWER:
 
        case SNI_BRD_PCI_MTOWER:

-               if (is_rm300_revd())
-                       return irq_tab_rm300d[slot][pin];
-               /* fall through */
+               if (is_rm300_revd())
+                       return irq_tab_rm300d[slot][pin];
+               /* fall through */

 
        case SNI_BRD_PCI_DESKTOP:
 
        case SNI_BRD_PCI_DESKTOP:

-               return irq_tab_rm200[slot][pin];
+               return irq_tab_rm200[slot][pin];

 
        case SNI_BRD_PCI_MTOWER_CPLUS:
 
        case SNI_BRD_PCI_MTOWER_CPLUS:

-               return irq_tab_rm300e[slot][pin];
+               return irq_tab_rm300e[slot][pin];

        }
 
        return 0;
        }
 
        return 0;

diff --git a/arch/mips/pci/fixup-tb0219.c b/arch/mips/pci/fixup-tb0219.c
index 8084b17d44066a3f1ca658902f4b191939c91d84..d0b0083fbd278a529209d41c7259e645d2c37f6c 100644 (file)
--- a/arch/mips/pci/fixup-tb0219.c
+++ b/arch/mips/pci/fixup-tb0219.c
@@ -1,7 +1,7 @@
 /*
  *  fixup-tb0219.c, The TANBAC TB0219 specific PCI fixups.
  *
 /*
  *  fixup-tb0219.c, The TANBAC TB0219 specific PCI fixups.
  *

- *  Copyright (C) 2003  Megasolution Inc. <matsu@megasolution.jp>
+ *  Copyright (C) 2003 Megasolution Inc. <matsu@megasolution.jp>

  *  Copyright (C) 2004-2005  Yoichi Yuasa <yuasa@linux-mips.org>
  *
  *  This program is free software; you can redistribute it and/or modify
  *  Copyright (C) 2004-2005  Yoichi Yuasa <yuasa@linux-mips.org>
  *
  *  This program is free software; you can redistribute it and/or modify

diff --git a/arch/mips/pci/fixup-tb0287.c b/arch/mips/pci/fixup-tb0287.c
index 2fe29db4372595d5393ab11b38c8ac3f0fff466d..8c5039ed75d74c40df1b739ad37edf177dfad5bf 100644 (file)
--- a/arch/mips/pci/fixup-tb0287.c
+++ b/arch/mips/pci/fixup-tb0287.c
@@ -1,7 +1,7 @@
 /*
  *  fixup-tb0287.c, The TANBAC TB0287 specific PCI fixups.
  *
 /*
  *  fixup-tb0287.c, The TANBAC TB0287 specific PCI fixups.
  *

- *  Copyright (C) 2005  Yoichi Yuasa <yuasa@linux-mips.org>
+ *  Copyright (C) 2005 Yoichi Yuasa <yuasa@linux-mips.org>

  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by

diff --git a/arch/mips/pci/fixup-wrppmc.c b/arch/mips/pci/fixup-wrppmc.c
index 3d277549d5dfa1ccf620730e582868d34de8939d..29737edd121fe2fcd89f0c573eacf0a8cf487390 100644 (file)
--- a/arch/mips/pci/fixup-wrppmc.c
+++ b/arch/mips/pci/fixup-wrppmc.c
@@ -20,7 +20,7 @@
 #define PCI_SLOT_MAXNR 32 /* Each PCI bus has 32 physical slots */
 
 static char pci_irq_tab[PCI_SLOT_MAXNR][5] __initdata = {
 #define PCI_SLOT_MAXNR 32 /* Each PCI bus has 32 physical slots */
 
 static char pci_irq_tab[PCI_SLOT_MAXNR][5] __initdata = {

-       /* 0    INTA   INTB   INTC   INTD */
+       /* 0    INTA   INTB   INTC   INTD */

        [0] = {0, 0, 0, 0, 0},          /* Slot 0: GT64120 PCI bridge */
        [6] = {0, WRPPMC_PCI_INTA_IRQ, 0, 0, 0},
 };
        [0] = {0, 0, 0, 0, 0},          /* Slot 0: GT64120 PCI bridge */
        [6] = {0, WRPPMC_PCI_INTA_IRQ, 0, 0, 0},
 };

diff --git a/arch/mips/pci/ops-bcm63xx.c b/arch/mips/pci/ops-bcm63xx.c
index 4a156629e958168c2060ff6d40af2ffe72c29980..6144bb337e4466929b0cf9519fbb18c6383f5124 100644 (file)
--- a/arch/mips/pci/ops-bcm63xx.c
+++ b/arch/mips/pci/ops-bcm63xx.c
@@ -174,8 +174,8 @@ static int bcm63xx_pci_write(struct pci_bus *bus, unsigned int devfn,
 }
 
 struct pci_ops bcm63xx_pci_ops = {
 }
 
 struct pci_ops bcm63xx_pci_ops = {

-       .read   = bcm63xx_pci_read,
-       .write  = bcm63xx_pci_write
+       .read   = bcm63xx_pci_read,
+       .write  = bcm63xx_pci_write

 };
 
 #ifdef CONFIG_CARDBUS
 };
 
 #ifdef CONFIG_CARDBUS


@@ -370,8 +370,8 @@ static int bcm63xx_cb_read(struct pci_bus *bus, unsigned int devfn,
                return fake_cb_bridge_read(where, size, val);
        }
 
                return fake_cb_bridge_read(where, size, val);
        }
 

-       /* a  configuration  cycle for  the  device  behind the  cardbus
-        * bridge is  actually done as a  type 0 cycle  on the primary
+       /* a  configuration  cycle for  the  device  behind the  cardbus
+        * bridge is  actually done as a  type 0 cycle  on the primary

         * bus. This means that only  one device can be on the cardbus
         * bus */
        if (fake_cb_bridge_regs.bus_assigned &&
         * bus. This means that only  one device can be on the cardbus
         * bus */
        if (fake_cb_bridge_regs.bus_assigned &&


@@ -403,8 +403,8 @@ static int bcm63xx_cb_write(struct pci_bus *bus, unsigned int devfn,
 }
 
 struct pci_ops bcm63xx_cb_ops = {
 }
 
 struct pci_ops bcm63xx_cb_ops = {

-       .read   = bcm63xx_cb_read,
-       .write   = bcm63xx_cb_write,
+       .read   = bcm63xx_cb_read,
+       .write   = bcm63xx_cb_write,

 };
 
 /*
 };
 
 /*


@@ -523,6 +523,6 @@ static int bcm63xx_pcie_write(struct pci_bus *bus, unsigned int devfn,
 
 
 struct pci_ops bcm63xx_pcie_ops = {
 
 
 struct pci_ops bcm63xx_pcie_ops = {

-       .read   = bcm63xx_pcie_read,
-       .write  = bcm63xx_pcie_write
+       .read   = bcm63xx_pcie_read,
+       .write  = bcm63xx_pcie_write

 };
 };

diff --git a/arch/mips/pci/ops-bonito64.c b/arch/mips/pci/ops-bonito64.c
index 1b3e03f20c5466dea11954462fbc1b8291e6ee40..830352e3aeda71174ade994531e51f48a03e0781 100644 (file)
--- a/arch/mips/pci/ops-bonito64.c
+++ b/arch/mips/pci/ops-bonito64.c
@@ -26,7 +26,7 @@
 
 #include <asm/mips-boards/bonito64.h>
 
 
 #include <asm/mips-boards/bonito64.h>
 

-#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_READ         0

 #define PCI_ACCESS_WRITE 1
 
 #define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset))
 #define PCI_ACCESS_WRITE 1
 
 #define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset))


@@ -137,7 +137,7 @@ static int bonito64_pcibios_write(struct pci_bus *bus, unsigned int devfn,
                data = val;
        else {
                if (bonito64_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
                data = val;
        else {
                if (bonito64_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,

-                                              where, &data))
+                                              where, &data))

                        return -1;
 
                if (size == 1)
                        return -1;
 
                if (size == 1)

diff --git a/arch/mips/pci/ops-gt64xxx_pci0.c b/arch/mips/pci/ops-gt64xxx_pci0.c
index 3d896c5f413f77a8e030a1214c79918d95e1a7ba..effcbda9f528d507a533916a36583ee8eba85c97 100644 (file)
--- a/arch/mips/pci/ops-gt64xxx_pci0.c
+++ b/arch/mips/pci/ops-gt64xxx_pci0.c
@@ -23,21 +23,21 @@
 
 #include <asm/gt64120.h>
 
 
 #include <asm/gt64120.h>
 

-#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_READ         0

 #define PCI_ACCESS_WRITE 1
 
 /*
  *  PCI configuration cycle AD bus definition
  */
 /* Type 0 */
 #define PCI_ACCESS_WRITE 1
 
 /*
  *  PCI configuration cycle AD bus definition
  */
 /* Type 0 */

-#define PCI_CFG_TYPE0_REG_SHF           0
-#define PCI_CFG_TYPE0_FUNC_SHF          8
+#define PCI_CFG_TYPE0_REG_SHF          0
+#define PCI_CFG_TYPE0_FUNC_SHF         8

 
 /* Type 1 */
 
 /* Type 1 */

-#define PCI_CFG_TYPE1_REG_SHF           0
-#define PCI_CFG_TYPE1_FUNC_SHF          8
-#define PCI_CFG_TYPE1_DEV_SHF           11
-#define PCI_CFG_TYPE1_BUS_SHF           16
+#define PCI_CFG_TYPE1_REG_SHF          0
+#define PCI_CFG_TYPE1_FUNC_SHF         8
+#define PCI_CFG_TYPE1_DEV_SHF          11
+#define PCI_CFG_TYPE1_BUS_SHF          16

 
 static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
                struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
 
 static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
                struct pci_bus *bus, unsigned int devfn, int where, u32 * data)


@@ -50,7 +50,7 @@ static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
 
        /* Clear cause register bits */
        GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
 
        /* Clear cause register bits */
        GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |

-                                    GT_INTRCAUSE_TARABORT0_BIT));
+                                    GT_INTRCAUSE_TARABORT0_BIT));

 
        /* Setup address */
        GT_WRITE(GT_PCI0_CFGADDR_OFS,
 
        /* Setup address */
        GT_WRITE(GT_PCI0_CFGADDR_OFS,


@@ -87,7 +87,7 @@ static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type,
 
                /* Clear bits */
                GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
 
                /* Clear bits */
                GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |

-                                            GT_INTRCAUSE_TARABORT0_BIT));
+                                            GT_INTRCAUSE_TARABORT0_BIT));

 
                return -1;
        }
 
                return -1;
        }


@@ -106,7 +106,7 @@ static int gt64xxx_pci0_pcibios_read(struct pci_bus *bus, unsigned int devfn,
        u32 data = 0;
 
        if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
        u32 data = 0;
 
        if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,

-                                              where, &data))
+                                              where, &data))

                return PCIBIOS_DEVICE_NOT_FOUND;
 
        if (size == 1)
                return PCIBIOS_DEVICE_NOT_FOUND;
 
        if (size == 1)


@@ -128,7 +128,7 @@ static int gt64xxx_pci0_pcibios_write(struct pci_bus *bus, unsigned int devfn,
                data = val;
        else {
                if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus,
                data = val;
        else {
                if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus,

-                                                      devfn, where, &data))
+                                                      devfn, where, &data))

                        return PCIBIOS_DEVICE_NOT_FOUND;
 
                if (size == 1)
                        return PCIBIOS_DEVICE_NOT_FOUND;
 
                if (size == 1)


@@ -140,7 +140,7 @@ static int gt64xxx_pci0_pcibios_write(struct pci_bus *bus, unsigned int devfn,
        }
 
        if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
        }
 
        if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,

-                                              where, &data))
+                                              where, &data))

                return PCIBIOS_DEVICE_NOT_FOUND;
 
        return PCIBIOS_SUCCESSFUL;
                return PCIBIOS_DEVICE_NOT_FOUND;
 
        return PCIBIOS_SUCCESSFUL;

diff --git a/arch/mips/pci/ops-lantiq.c b/arch/mips/pci/ops-lantiq.c
index 1f2afb55cc7117576e791ff0114f7feaf817e9e3..16e7c2526d7756fd0a47380724d0fd112f44b904 100644 (file)
--- a/arch/mips/pci/ops-lantiq.c
+++ b/arch/mips/pci/ops-lantiq.c
@@ -23,7 +23,7 @@
 #define LTQ_PCI_CFG_DEVNUM_SHF 11
 #define LTQ_PCI_CFG_FUNNUM_SHF 8
 
 #define LTQ_PCI_CFG_DEVNUM_SHF 11
 #define LTQ_PCI_CFG_FUNNUM_SHF 8
 

-#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_READ         0

 #define PCI_ACCESS_WRITE 1
 
 static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus,
 #define PCI_ACCESS_WRITE 1
 
 static int ltq_pci_config_access(unsigned char access_type, struct pci_bus *bus,

diff --git a/arch/mips/pci/ops-loongson2.c b/arch/mips/pci/ops-loongson2.c
index afd221122d222722d355c6723547ae3657853c5f..98254afa0287f6bfcfb0a3bddece6b670a4db5f5 100644 (file)
--- a/arch/mips/pci/ops-loongson2.c
+++ b/arch/mips/pci/ops-loongson2.c
@@ -24,7 +24,7 @@
 #include <cs5536/cs5536.h>
 #endif
 
 #include <cs5536/cs5536.h>
 #endif
 

-#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_READ         0

 #define PCI_ACCESS_WRITE 1
 
 #define CFG_SPACE_REG(offset) \
 #define PCI_ACCESS_WRITE 1
 
 #define CFG_SPACE_REG(offset) \

diff --git a/arch/mips/pci/ops-msc.c b/arch/mips/pci/ops-msc.c
index 5d9fbb0f4670b85d43366b7cfa5ee97b08f2d9d5..92a8543361bb867a3d932ddedcbcf2a1d0fc8eba 100644 (file)
--- a/arch/mips/pci/ops-msc.c
+++ b/arch/mips/pci/ops-msc.c
@@ -1,8 +1,8 @@
 /*
 /*

- * Copyright (C) 1999, 2000, 2004, 2005  MIPS Technologies, Inc.
+ * Copyright (C) 1999, 2000, 2004, 2005         MIPS Technologies, Inc.

  *    All rights reserved.
  *    Authors: Carsten Langgaard <carstenl@mips.com>
  *    All rights reserved.
  *    Authors: Carsten Langgaard <carstenl@mips.com>

- *             Maciej W. Rozycki <macro@mips.com>
+ *            Maciej W. Rozycki <macro@mips.com>

  * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
  *
  *  This program is free software; you can distribute it and/or modify it
  * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
  *
  *  This program is free software; you can distribute it and/or modify it


@@ -28,21 +28,21 @@
 
 #include <asm/mips-boards/msc01_pci.h>
 
 
 #include <asm/mips-boards/msc01_pci.h>
 

-#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_READ         0

 #define PCI_ACCESS_WRITE 1
 
 /*
  *  PCI configuration cycle AD bus definition
  */
 /* Type 0 */
 #define PCI_ACCESS_WRITE 1
 
 /*
  *  PCI configuration cycle AD bus definition
  */
 /* Type 0 */

-#define PCI_CFG_TYPE0_REG_SHF           0
-#define PCI_CFG_TYPE0_FUNC_SHF          8
+#define PCI_CFG_TYPE0_REG_SHF          0
+#define PCI_CFG_TYPE0_FUNC_SHF         8

 
 /* Type 1 */
 
 /* Type 1 */

-#define PCI_CFG_TYPE1_REG_SHF           0
-#define PCI_CFG_TYPE1_FUNC_SHF          8
-#define PCI_CFG_TYPE1_DEV_SHF           11
-#define PCI_CFG_TYPE1_BUS_SHF           16
+#define PCI_CFG_TYPE1_REG_SHF          0
+#define PCI_CFG_TYPE1_FUNC_SHF         8
+#define PCI_CFG_TYPE1_DEV_SHF          11
+#define PCI_CFG_TYPE1_BUS_SHF          16

 
 static int msc_pcibios_config_access(unsigned char access_type,
        struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
 
 static int msc_pcibios_config_access(unsigned char access_type,
        struct pci_bus *bus, unsigned int devfn, int where, u32 * data)


@@ -97,7 +97,7 @@ static int msc_pcibios_read(struct pci_bus *bus, unsigned int devfn,
                return PCIBIOS_BAD_REGISTER_NUMBER;
 
        if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
                return PCIBIOS_BAD_REGISTER_NUMBER;
 
        if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,

-                                     &data))
+                                     &data))

                return -1;
 
        if (size == 1)
                return -1;
 
        if (size == 1)


@@ -124,7 +124,7 @@ static int msc_pcibios_write(struct pci_bus *bus, unsigned int devfn,
                data = val;
        else {
                if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
                data = val;
        else {
                if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,

-                                             where, &data))
+                                             where, &data))

                        return -1;
 
                if (size == 1)
                        return -1;
 
                if (size == 1)

diff --git a/arch/mips/pci/ops-nile4.c b/arch/mips/pci/ops-nile4.c
index 99929cf88419a58183b0b39827f8cc10aad762c3..499e35c3eb3575337f9826700ab4b83fc8ad042b 100644 (file)
--- a/arch/mips/pci/ops-nile4.c
+++ b/arch/mips/pci/ops-nile4.c
@@ -6,7 +6,7 @@
 #include <asm/lasat/lasat.h>
 #include <asm/nile4.h>
 
 #include <asm/lasat/lasat.h>
 #include <asm/nile4.h>
 

-#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_READ         0

 #define PCI_ACCESS_WRITE 1
 
 #define LO(reg) (reg / 4)
 #define PCI_ACCESS_WRITE 1
 
 #define LO(reg) (reg / 4)

diff --git a/arch/mips/pci/ops-pmcmsp.c b/arch/mips/pci/ops-pmcmsp.c
index 389bf669d56e7d4a9cf4b4c04c537537bc0b3cc0..d0b6f8399b075eaf768c8fad5d95f20711b87a16 100644 (file)
--- a/arch/mips/pci/ops-pmcmsp.c
+++ b/arch/mips/pci/ops-pmcmsp.c
@@ -9,8 +9,8 @@
  * Much of the code is derived from the original DDB5074 port by
  * Geert Uytterhoeven <geert@sonycom.com>
  *
  * Much of the code is derived from the original DDB5074 port by
  * Geert Uytterhoeven <geert@sonycom.com>
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  *
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  *


@@ -57,18 +57,18 @@ static void pci_proc_init(void);
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Prints the count of how many times each PCI
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Prints the count of how many times each PCI

- *               interrupt has asserted. Can be invoked by the
- *               /proc filesystem.
+ *              interrupt has asserted. Can be invoked by the
+ *              /proc filesystem.

  *
  *

- *  INPUTS:      page    - part of STDOUT calculation
- *               off     - part of STDOUT calculation
- *               count   - part of STDOUT calculation
- *               data    - unused
+ *  INPUTS:     page    - part of STDOUT calculation
+ *              off     - part of STDOUT calculation
+ *              count   - part of STDOUT calculation
+ *              data    - unused

  *
  *

- *  OUTPUTS:     start   - new start location
- *               eof     - end of file pointer
+ *  OUTPUTS:    start   - new start location
+ *              eof     - end of file pointer

  *
  *

- *  RETURNS:     len     - STDOUT length
+ *  RETURNS:    len     - STDOUT length

  *
  ****************************************************************************/
 static int read_msp_pci_counts(char *page, char **start, off_t off,
  *
  ****************************************************************************/
 static int read_msp_pci_counts(char *page, char **start, off_t off,


@@ -106,21 +106,21 @@ static int read_msp_pci_counts(char *page, char **start, off_t off,
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Generates a configuration write cycle for debug purposes.
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Generates a configuration write cycle for debug purposes.

- *               The IDSEL line asserted and location and data written are
- *               immaterial. Just want to be able to prove that a
- *               configuration write can be correctly generated on the
- *               PCI bus.  Intent is that this function by invocable from
- *               the /proc filesystem.
+ *              The IDSEL line asserted and location and data written are
+ *              immaterial. Just want to be able to prove that a
+ *              configuration write can be correctly generated on the
+ *              PCI bus.  Intent is that this function by invocable from
+ *              the /proc filesystem.

  *
  *

- *  INPUTS:      page    - part of STDOUT calculation
- *               off     - part of STDOUT calculation
- *               count   - part of STDOUT calculation
- *               data    - unused
+ *  INPUTS:     page    - part of STDOUT calculation
+ *              off     - part of STDOUT calculation
+ *              count   - part of STDOUT calculation
+ *              data    - unused

  *
  *

- *  OUTPUTS:     start   - new start location
- *               eof     - end of file pointer
+ *  OUTPUTS:    start   - new start location
+ *              eof     - end of file pointer

  *
  *

- *  RETURNS:     len     - STDOUT length
+ *  RETURNS:    len     - STDOUT length

  *
  ****************************************************************************/
 static int gen_pci_cfg_wr(char *page, char **start, off_t off,
  *
  ****************************************************************************/
 static int gen_pci_cfg_wr(char *page, char **start, off_t off,


@@ -190,11 +190,11 @@ static int gen_pci_cfg_wr(char *page, char **start, off_t off,
  *
  *  DESCRIPTION: Create entries in the /proc filesystem for debug access.
  *
  *
  *  DESCRIPTION: Create entries in the /proc filesystem for debug access.
  *

- *  INPUTS:      none
+ *  INPUTS:     none

  *
  *

- *  OUTPUTS:     none
+ *  OUTPUTS:    none

  *
  *

- *  RETURNS:     none
+ *  RETURNS:    none

  *
  ****************************************************************************/
 static void pci_proc_init(void)
  *
  ****************************************************************************/
 static void pci_proc_init(void)


@@ -214,44 +214,44 @@ static DEFINE_SPINLOCK(bpci_lock);
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Defines the address range that pciauto() will use to
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Defines the address range that pciauto() will use to

- *               assign to the I/O BARs of PCI devices.
- *
- *               Use the start and end addresses of the MSP7120 PCI Host
- *               Controller I/O space, in the form that they appear on the
- *               PCI bus AFTER MSP7120 has performed address translation.
- *
- *               For I/O accesses, MSP7120 ignores OATRAN and maps I/O
- *               accesses into the bottom 0xFFF region of address space,
- *               so that is the range to put into the pci_io_resource
- *               struct.
- *
- *               In MSP4200, the start address was 0x04 instead of the
- *              expected 0x00. Will just assume there was a good reason
- *              for this!
- *
- *  NOTES:       Linux, by default, will assign I/O space to the lowest
- *               region of address space. Since MSP7120 and Linux,
- *               by default, have no offset in between how they map, the
- *               io_offset element of pci_controller struct should be set
- *               to zero.
+ *              assign to the I/O BARs of PCI devices.
+ *
+ *              Use the start and end addresses of the MSP7120 PCI Host
+ *              Controller I/O space, in the form that they appear on the
+ *              PCI bus AFTER MSP7120 has performed address translation.
+ *
+ *              For I/O accesses, MSP7120 ignores OATRAN and maps I/O
+ *              accesses into the bottom 0xFFF region of address space,
+ *              so that is the range to put into the pci_io_resource
+ *              struct.
+ *
+ *              In MSP4200, the start address was 0x04 instead of the
+ *              expected 0x00. Will just assume there was a good reason
+ *              for this!
+ *
+ *  NOTES:      Linux, by default, will assign I/O space to the lowest
+ *              region of address space. Since MSP7120 and Linux,
+ *              by default, have no offset in between how they map, the
+ *              io_offset element of pci_controller struct should be set
+ *              to zero.

  *  ELEMENTS:
  *  ELEMENTS:

- *    name       - String used for a meaningful name.
+ *    name      - String used for a meaningful name.

  *
  *

- *    start      - Start address of MSP7120's I/O space, as MSP7120 presents
- *                 the address on the PCI bus.
+ *    start     - Start address of MSP7120's I/O space, as MSP7120 presents
+ *                the address on the PCI bus.

  *
  *

- *    end        - End address of MSP7120's I/O space, as MSP7120 presents
- *                 the address on the PCI bus.
+ *    end       - End address of MSP7120's I/O space, as MSP7120 presents
+ *                the address on the PCI bus.

  *
  *

- *    flags      - Attributes indicating the type of resource. In this case,
- *                 indicate I/O space.
+ *    flags     - Attributes indicating the type of resource. In this case,
+ *                indicate I/O space.

  *
  ****************************************************************************/
 static struct resource pci_io_resource = {
        .name   = "pci IO space",
        .start  = 0x04,
        .end    = 0x0FFF,
  *
  ****************************************************************************/
 static struct resource pci_io_resource = {
        .name   = "pci IO space",
        .start  = 0x04,
        .end    = 0x0FFF,

-       .flags  = IORESOURCE_IO /* I/O space */
+       .flags  = IORESOURCE_IO /* I/O space */

 };
 
 /*****************************************************************************
 };
 
 /*****************************************************************************


@@ -260,26 +260,26 @@ static struct resource pci_io_resource = {
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Defines the address range that pciauto() will use to
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Defines the address range that pciauto() will use to

- *               assign to the memory BARs of PCI devices.
+ *              assign to the memory BARs of PCI devices.

  *
  *

- *               The .start and .end values are dependent upon how address
- *               translation is performed by the OATRAN regiser.
+ *              The .start and .end values are dependent upon how address
+ *              translation is performed by the OATRAN regiser.

  *
  *

- *               The values to use for .start and .end are the values
- *               in the form they appear on the PCI bus AFTER MSP7120 has
- *               performed OATRAN address translation.
+ *              The values to use for .start and .end are the values
+ *              in the form they appear on the PCI bus AFTER MSP7120 has
+ *              performed OATRAN address translation.

  *
  *  ELEMENTS:
  *
  *  ELEMENTS:

- *    name       - String used for a meaningful name.
+ *    name      - String used for a meaningful name.

  *
  *

- *    start      - Start address of MSP7120's memory space, as MSP7120 presents
- *                 the address on the PCI bus.
+ *    start     - Start address of MSP7120's memory space, as MSP7120 presents
+ *                the address on the PCI bus.

  *
  *

- *    end        - End address of MSP7120's memory space, as MSP7120 presents
- *                 the address on the PCI bus.
+ *    end       - End address of MSP7120's memory space, as MSP7120 presents
+ *                the address on the PCI bus.

  *
  *

- *    flags      - Attributes indicating the type of resource. In this case,
- *                 indicate memory space.
+ *    flags     - Attributes indicating the type of resource. In this case,
+ *                indicate memory space.

  *
  ****************************************************************************/
 static struct resource pci_mem_resource = {
  *
  ****************************************************************************/
 static struct resource pci_mem_resource = {


@@ -295,17 +295,17 @@ static struct resource pci_mem_resource = {
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: PCI status interrupt handler. Updates the count of how
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: PCI status interrupt handler. Updates the count of how

- *               many times each status bit has been set, then clears
- *               the status bits. If the appropriate macros are defined,
- *               these counts can be viewed via the /proc filesystem.
+ *              many times each status bit has been set, then clears
+ *              the status bits. If the appropriate macros are defined,
+ *              these counts can be viewed via the /proc filesystem.

  *
  *

- *  INPUTS:      irq     - unused
- *               dev_id  - unused
- *               pt_regs - unused
+ *  INPUTS:     irq     - unused
+ *              dev_id  - unused
+ *              pt_regs - unused

  *
  *

- *  OUTPUTS:     none
+ *  OUTPUTS:    none

  *
  *

- *  RETURNS:     PCIBIOS_SUCCESSFUL  - success
+ *  RETURNS:    PCIBIOS_SUCCESSFUL  - success

  *
  ****************************************************************************/
 static irqreturn_t bpci_interrupt(int irq, void *dev_id)
  *
  ****************************************************************************/
 static irqreturn_t bpci_interrupt(int irq, void *dev_id)


@@ -335,41 +335,41 @@ static irqreturn_t bpci_interrupt(int irq, void *dev_id)
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Performs a PCI configuration access (rd or wr), then
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Performs a PCI configuration access (rd or wr), then

- *               checks that the access succeeded by querying MSP7120's
- *               PCI status bits.
+ *              checks that the access succeeded by querying MSP7120's
+ *              PCI status bits.

  *
  *  INPUTS:
  *
  *  INPUTS:

- *               access_type  - kind of PCI configuration cycle to perform
- *                              (read or write). Legal values are
- *                              PCI_ACCESS_WRITE and PCI_ACCESS_READ.
- *
- *               bus          - pointer to the bus number of the device to
- *                              be targeted for the configuration cycle.
- *                              The only element of the pci_bus structure
- *                              used is bus->number. This argument determines
- *                              if the configuration access will be Type 0 or
- *                              Type 1. Since MSP7120 assumes itself to be the
- *                              PCI Host, any non-zero bus->number generates
- *                              a Type 1 access.
- *
- *               devfn        - this is an 8-bit field. The lower three bits
- *                              specify the function number of the device to
- *                              be targeted for the configuration cycle, with
- *                              all three-bit combinations being legal. The
- *                              upper five bits specify the device number,
- *                              with legal values being 10 to 31.
- *
- *               where        - address within the Configuration Header
- *                              space to access.
- *
- *               data         - for write accesses, contains the data to
- *                              write.
+ *              access_type  - kind of PCI configuration cycle to perform
+ *                             (read or write). Legal values are
+ *                             PCI_ACCESS_WRITE and PCI_ACCESS_READ.
+ *
+ *              bus          - pointer to the bus number of the device to
+ *                             be targeted for the configuration cycle.
+ *                             The only element of the pci_bus structure
+ *                             used is bus->number. This argument determines
+ *                             if the configuration access will be Type 0 or
+ *                             Type 1. Since MSP7120 assumes itself to be the
+ *                             PCI Host, any non-zero bus->number generates
+ *                             a Type 1 access.
+ *
+ *              devfn        - this is an 8-bit field. The lower three bits
+ *                             specify the function number of the device to
+ *                             be targeted for the configuration cycle, with
+ *                             all three-bit combinations being legal. The
+ *                             upper five bits specify the device number,
+ *                             with legal values being 10 to 31.
+ *
+ *              where        - address within the Configuration Header
+ *                             space to access.
+ *
+ *              data         - for write accesses, contains the data to
+ *                             write.

  *
  *  OUTPUTS:
  *
  *  OUTPUTS:

- *               data         - for read accesses, contains the value read.
+ *              data         - for read accesses, contains the value read.

  *
  *

- *  RETURNS:     PCIBIOS_SUCCESSFUL  - success
- *               -1                  - access failure
+ *  RETURNS:    PCIBIOS_SUCCESSFUL  - success
+ *              -1                  - access failure

  *
  ****************************************************************************/
 int msp_pcibios_config_access(unsigned char access_type,
  *
  ****************************************************************************/
 int msp_pcibios_config_access(unsigned char access_type,


@@ -429,7 +429,7 @@ int msp_pcibios_config_access(unsigned char access_type,
         * for this Block Copy, called Block Copy 0 Fault (BC0F) and
         * Block Copy 1 Fault (BC1F). MSP4200 and MSP7120 don't have this
         * dedicated Block Copy block, so these two interrupts are now
         * for this Block Copy, called Block Copy 0 Fault (BC0F) and
         * Block Copy 1 Fault (BC1F). MSP4200 and MSP7120 don't have this
         * dedicated Block Copy block, so these two interrupts are now

-        * marked reserved. In case the  Block Copy is resurrected in a
+        * marked reserved. In case the  Block Copy is resurrected in a

         * future design, maintain the code that treats these two interrupts
         * specially.
         *
         * future design, maintain the code that treats these two interrupts
         * specially.
         *


@@ -439,7 +439,7 @@ int msp_pcibios_config_access(unsigned char access_type,
        preg->if_status = ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F);
 
        /* Setup address that is to appear on PCI bus */
        preg->if_status = ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F);
 
        /* Setup address that is to appear on PCI bus */

-       preg->config_addr = BPCI_CFGADDR_ENABLE |
+       preg->config_addr = BPCI_CFGADDR_ENABLE |

                (bus_num << BPCI_CFGADDR_BUSNUM_SHF) |
                (dev_fn << BPCI_CFGADDR_FUNCTNUM_SHF) |
                (where & 0xFC);
                (bus_num << BPCI_CFGADDR_BUSNUM_SHF) |
                (dev_fn << BPCI_CFGADDR_FUNCTNUM_SHF) |
                (where & 0xFC);


@@ -494,21 +494,21 @@ int msp_pcibios_config_access(unsigned char access_type,
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Read a byte from PCI configuration address spac
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Read a byte from PCI configuration address spac

- *               Since the hardware can't address 8 bit chunks
- *               directly, read a 32-bit chunk, then mask off extraneous
- *               bits.
+ *              Since the hardware can't address 8 bit chunks
+ *              directly, read a 32-bit chunk, then mask off extraneous
+ *              bits.

  *
  *

- *  INPUTS       bus    - structure containing attributes for the PCI bus
- *                        that the read is destined for.
- *               devfn  - device/function combination that the read is
- *                        destined for.
- *               where  - register within the Configuration Header space
- *                        to access.
+ *  INPUTS      bus    - structure containing attributes for the PCI bus
+ *                       that the read is destined for.
+ *              devfn  - device/function combination that the read is
+ *                       destined for.
+ *              where  - register within the Configuration Header space
+ *                       to access.

  *
  *

- *  OUTPUTS      val    - read data
+ *  OUTPUTS     val    - read data

  *
  *

- *  RETURNS:     PCIBIOS_SUCCESSFUL  - success
- *               -1                  - read access failure
+ *  RETURNS:    PCIBIOS_SUCCESSFUL  - success
+ *              -1                  - read access failure

  *
  ****************************************************************************/
 static int
  *
  ****************************************************************************/
 static int


@@ -541,22 +541,22 @@ msp_pcibios_read_config_byte(struct pci_bus *bus,
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Read a word (16 bits) from PCI configuration address space.
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Read a word (16 bits) from PCI configuration address space.

- *               Since the hardware can't address 16 bit chunks
- *               directly, read a 32-bit chunk, then mask off extraneous
- *               bits.
+ *              Since the hardware can't address 16 bit chunks
+ *              directly, read a 32-bit chunk, then mask off extraneous
+ *              bits.

  *
  *

- *  INPUTS       bus    - structure containing attributes for the PCI bus
- *                        that the read is destined for.
- *               devfn  - device/function combination that the read is
- *                        destined for.
- *               where  - register within the Configuration Header space
- *                        to access.
+ *  INPUTS      bus    - structure containing attributes for the PCI bus
+ *                       that the read is destined for.
+ *              devfn  - device/function combination that the read is
+ *                       destined for.
+ *              where  - register within the Configuration Header space
+ *                       to access.

  *
  *

- *  OUTPUTS      val    - read data
+ *  OUTPUTS     val    - read data

  *
  *

- *  RETURNS:     PCIBIOS_SUCCESSFUL           - success
- *               PCIBIOS_BAD_REGISTER_NUMBER  - bad register address
- *               -1                           - read access failure
+ *  RETURNS:    PCIBIOS_SUCCESSFUL           - success
+ *              PCIBIOS_BAD_REGISTER_NUMBER  - bad register address
+ *              -1                           - read access failure

  *
  ****************************************************************************/
 static int
  *
  ****************************************************************************/
 static int


@@ -600,20 +600,20 @@ msp_pcibios_read_config_word(struct pci_bus *bus,
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Read a double word (32 bits) from PCI configuration
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Read a double word (32 bits) from PCI configuration

- *               address space.
+ *              address space.

  *
  *

- *  INPUTS       bus    - structure containing attributes for the PCI bus
- *                        that the read is destined for.
- *               devfn  - device/function combination that the read is
- *                        destined for.
- *               where  - register within the Configuration Header space
- *                        to access.
+ *  INPUTS      bus    - structure containing attributes for the PCI bus
+ *                       that the read is destined for.
+ *              devfn  - device/function combination that the read is
+ *                       destined for.
+ *              where  - register within the Configuration Header space
+ *                       to access.

  *
  *

- *  OUTPUTS      val    - read data
+ *  OUTPUTS     val    - read data

  *
  *

- *  RETURNS:     PCIBIOS_SUCCESSFUL           - success
- *               PCIBIOS_BAD_REGISTER_NUMBER  - bad register address
- *               -1                           - read access failure
+ *  RETURNS:    PCIBIOS_SUCCESSFUL           - success
+ *              PCIBIOS_BAD_REGISTER_NUMBER  - bad register address
+ *              -1                           - read access failure

  *
  ****************************************************************************/
 static int
  *
  ****************************************************************************/
 static int


@@ -652,21 +652,21 @@ msp_pcibios_read_config_dword(struct pci_bus *bus,
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Write a byte to PCI configuration address space.
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Write a byte to PCI configuration address space.

- *               Since the hardware can't address 8 bit chunks
- *               directly, a read-modify-write is performed.
+ *              Since the hardware can't address 8 bit chunks
+ *              directly, a read-modify-write is performed.

  *
  *

- *  INPUTS       bus    - structure containing attributes for the PCI bus
- *                        that the write is destined for.
- *               devfn  - device/function combination that the write is
- *                        destined for.
- *               where  - register within the Configuration Header space
- *                        to access.
- *               val    - value to write
+ *  INPUTS      bus    - structure containing attributes for the PCI bus
+ *                       that the write is destined for.
+ *              devfn  - device/function combination that the write is
+ *                       destined for.
+ *              where  - register within the Configuration Header space
+ *                       to access.
+ *              val    - value to write

  *
  *

- *  OUTPUTS      none
+ *  OUTPUTS     none

  *
  *

- *  RETURNS:     PCIBIOS_SUCCESSFUL  - success
- *               -1                  - write access failure
+ *  RETURNS:    PCIBIOS_SUCCESSFUL  - success
+ *              -1                  - write access failure

  *
  ****************************************************************************/
 static int
  *
  ****************************************************************************/
 static int


@@ -700,22 +700,22 @@ msp_pcibios_write_config_byte(struct pci_bus *bus,
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Write a word (16-bits) to PCI configuration address space.
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Write a word (16-bits) to PCI configuration address space.

- *               Since the hardware can't address 16 bit chunks
- *               directly, a read-modify-write is performed.
+ *              Since the hardware can't address 16 bit chunks
+ *              directly, a read-modify-write is performed.

  *
  *

- *  INPUTS       bus    - structure containing attributes for the PCI bus
- *                        that the write is destined for.
- *               devfn  - device/function combination that the write is
- *                        destined for.
- *               where  - register within the Configuration Header space
- *                        to access.
- *               val    - value to write
+ *  INPUTS      bus    - structure containing attributes for the PCI bus
+ *                       that the write is destined for.
+ *              devfn  - device/function combination that the write is
+ *                       destined for.
+ *              where  - register within the Configuration Header space
+ *                       to access.
+ *              val    - value to write

  *
  *

- *  OUTPUTS      none
+ *  OUTPUTS     none

  *
  *

- *  RETURNS:     PCIBIOS_SUCCESSFUL           - success
- *               PCIBIOS_BAD_REGISTER_NUMBER  - bad register address
- *               -1                           - write access failure
+ *  RETURNS:    PCIBIOS_SUCCESSFUL           - success
+ *              PCIBIOS_BAD_REGISTER_NUMBER  - bad register address
+ *              -1                           - write access failure

  *
  ****************************************************************************/
 static int
  *
  ****************************************************************************/
 static int


@@ -753,21 +753,21 @@ msp_pcibios_write_config_word(struct pci_bus *bus,
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Write a double word (32-bits) to PCI configuration address
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Write a double word (32-bits) to PCI configuration address

- *               space.
+ *              space.

  *
  *

- *  INPUTS       bus    - structure containing attributes for the PCI bus
- *                        that the write is destined for.
- *               devfn  - device/function combination that the write is
- *                        destined for.
- *               where  - register within the Configuration Header space
- *                        to access.
- *               val    - value to write
+ *  INPUTS      bus    - structure containing attributes for the PCI bus
+ *                       that the write is destined for.
+ *              devfn  - device/function combination that the write is
+ *                       destined for.
+ *              where  - register within the Configuration Header space
+ *                       to access.
+ *              val    - value to write

  *
  *

- *  OUTPUTS      none
+ *  OUTPUTS     none

  *
  *

- *  RETURNS:     PCIBIOS_SUCCESSFUL           - success
- *               PCIBIOS_BAD_REGISTER_NUMBER  - bad register address
- *               -1                           - write access failure
+ *  RETURNS:    PCIBIOS_SUCCESSFUL           - success
+ *              PCIBIOS_BAD_REGISTER_NUMBER  - bad register address
+ *              -1                           - write access failure

  *
  ****************************************************************************/
 static int
  *
  ****************************************************************************/
 static int


@@ -794,22 +794,22 @@ msp_pcibios_write_config_dword(struct pci_bus *bus,
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Interface the PCI configuration read request with
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Interface the PCI configuration read request with

- *               the appropriate function, based on how many bytes
- *               the read request is.
+ *              the appropriate function, based on how many bytes
+ *              the read request is.

  *
  *

- *  INPUTS       bus    - structure containing attributes for the PCI bus
- *                        that the write is destined for.
- *               devfn  - device/function combination that the write is
- *                        destined for.
- *               where  - register within the Configuration Header space
- *                        to access.
- *               size   - in units of bytes, should be 1, 2, or 4.
+ *  INPUTS      bus    - structure containing attributes for the PCI bus
+ *                       that the write is destined for.
+ *              devfn  - device/function combination that the write is
+ *                       destined for.
+ *              where  - register within the Configuration Header space
+ *                       to access.
+ *              size   - in units of bytes, should be 1, 2, or 4.

  *
  *

- *  OUTPUTS      val    - value read, with any extraneous bytes masked
- *                        to zero.
+ *  OUTPUTS     val    - value read, with any extraneous bytes masked
+ *                       to zero.

  *
  *

- *  RETURNS:     PCIBIOS_SUCCESSFUL   - success
- *               -1                   - failure
+ *  RETURNS:    PCIBIOS_SUCCESSFUL   - success
+ *              -1                   - failure

  *
  ****************************************************************************/
 int
  *
  ****************************************************************************/
 int


@@ -845,22 +845,22 @@ msp_pcibios_read_config(struct pci_bus *bus,
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Interface the PCI configuration write request with
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Interface the PCI configuration write request with

- *               the appropriate function, based on how many bytes
- *               the read request is.
+ *              the appropriate function, based on how many bytes
+ *              the read request is.

  *
  *

- *  INPUTS       bus    - structure containing attributes for the PCI bus
- *                        that the write is destined for.
- *               devfn  - device/function combination that the write is
- *                        destined for.
- *               where  - register within the Configuration Header space
- *                        to access.
- *               size   - in units of bytes, should be 1, 2, or 4.
- *               val    - value to write
+ *  INPUTS      bus    - structure containing attributes for the PCI bus
+ *                       that the write is destined for.
+ *              devfn  - device/function combination that the write is
+ *                       destined for.
+ *              where  - register within the Configuration Header space
+ *                       to access.
+ *              size   - in units of bytes, should be 1, 2, or 4.
+ *              val    - value to write

  *
  *

- *  OUTPUTS:     none
+ *  OUTPUTS:    none

  *
  *

- *  RETURNS:     PCIBIOS_SUCCESSFUL   - success
- *               -1                   - failure
+ *  RETURNS:    PCIBIOS_SUCCESSFUL   - success
+ *              -1                   - failure

  *
  ****************************************************************************/
 int
  *
  ****************************************************************************/
 int


@@ -897,11 +897,11 @@ msp_pcibios_write_config(struct pci_bus *bus,
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: structure to abstract the hardware specific PCI
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: structure to abstract the hardware specific PCI

- *               configuration accesses.
+ *              configuration accesses.

  *
  *  ELEMENTS:
  *
  *  ELEMENTS:

- *    read      - function for Linux to generate PCI Configuration reads.
- *    write     - function for Linux to generate PCI Configuration writes.
+ *    read     - function for Linux to generate PCI Configuration reads.
+ *    write    - function for Linux to generate PCI Configuration writes.

  *
  ****************************************************************************/
 struct pci_ops msp_pci_ops = {
  *
  ****************************************************************************/
 struct pci_ops msp_pci_ops = {


@@ -917,27 +917,27 @@ struct pci_ops msp_pci_ops = {
  *  Describes the attributes of the MSP7120 PCI Host Controller
  *
  *  ELEMENTS:
  *  Describes the attributes of the MSP7120 PCI Host Controller
  *
  *  ELEMENTS:

- *    pci_ops      - abstracts the hardware specific PCI configuration
- *                   accesses.
+ *    pci_ops     - abstracts the hardware specific PCI configuration
+ *                  accesses.

  *
  *    mem_resource - address range pciauto() uses to assign to PCI device
  *
  *    mem_resource - address range pciauto() uses to assign to PCI device

- *                   memory BARs.
+ *                  memory BARs.

  *
  *    mem_offset   - offset between how MSP7120 outbound PCI memory
  *
  *    mem_offset   - offset between how MSP7120 outbound PCI memory

- *                   transaction addresses appear on the PCI bus and how Linux
- *                   wants to configure memory BARs of the PCI devices.
- *                   MSP7120 does nothing funky, so just set to zero.
+ *                  transaction addresses appear on the PCI bus and how Linux
+ *                  wants to configure memory BARs of the PCI devices.
+ *                  MSP7120 does nothing funky, so just set to zero.

  *
  *    io_resource  - address range pciauto() uses to assign to PCI device
  *
  *    io_resource  - address range pciauto() uses to assign to PCI device

- *                   I/O BARs.
+ *                  I/O BARs.

  *
  *

- *    io_offset    - offset between how MSP7120 outbound PCI I/O
- *                   transaction addresses appear on the PCI bus and how
- *                   Linux defaults to configure I/O BARs of the PCI devices.
- *                   MSP7120 maps outbound I/O accesses into the bottom
- *                   bottom 4K of PCI address space (and ignores OATRAN).
- *                   Since the Linux default is to configure I/O BARs to the
- *                   bottom 4K, no special offset is needed. Just set to zero.
+ *    io_offset           - offset between how MSP7120 outbound PCI I/O
+ *                  transaction addresses appear on the PCI bus and how
+ *                  Linux defaults to configure I/O BARs of the PCI devices.
+ *                  MSP7120 maps outbound I/O accesses into the bottom
+ *                  bottom 4K of PCI address space (and ignores OATRAN).
+ *                  Since the Linux default is to configure I/O BARs to the
+ *                  bottom 4K, no special offset is needed. Just set to zero.

  *
  ****************************************************************************/
 static struct pci_controller msp_pci_controller = {
  *
  ****************************************************************************/
 static struct pci_controller msp_pci_controller = {


@@ -955,7 +955,7 @@ static struct pci_controller msp_pci_controller = {
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Initialize the PCI Host Controller and register it with
  *  _________________________________________________________________________
  *
  *  DESCRIPTION: Initialize the PCI Host Controller and register it with

- *               Linux so Linux can seize control of the PCI bus.
+ *              Linux so Linux can seize control of the PCI bus.

  *
  ****************************************************************************/
 void __init msp_pci_init(void)
  *
  ****************************************************************************/
 void __init msp_pci_init(void)


@@ -979,7 +979,7 @@ void __init msp_pci_init(void)
        *(unsigned long *)QFLUSH_REG_1 = 3;
 
        /* Configure PCI Host Controller. */
        *(unsigned long *)QFLUSH_REG_1 = 3;
 
        /* Configure PCI Host Controller. */

-       preg->if_status = ~0;           /* Clear cause register bits */
+       preg->if_status = ~0;           /* Clear cause register bits */

        preg->config_addr = 0;          /* Clear config access */
        preg->oatran    = MSP_PCI_OATRAN; /* PCI outbound addr translation */
        preg->if_mask   = 0xF8BF87C0;   /* Enable all PCI status interrupts */
        preg->config_addr = 0;          /* Clear config access */
        preg->oatran    = MSP_PCI_OATRAN; /* PCI outbound addr translation */
        preg->if_mask   = 0xF8BF87C0;   /* Enable all PCI status interrupts */

diff --git a/arch/mips/pci/ops-rc32434.c b/arch/mips/pci/ops-rc32434.c
index d1f8fa210ca119ef13245c54b195e47f63247648..7c7182e2350a362371658eaeb20ff6229c2d12bf 100644 (file)
--- a/arch/mips/pci/ops-rc32434.c
+++ b/arch/mips/pci/ops-rc32434.c
@@ -35,7 +35,7 @@
 #include <asm/mach-rc32434/rc32434.h>
 #include <asm/mach-rc32434/pci.h>
 
 #include <asm/mach-rc32434/rc32434.h>
 #include <asm/mach-rc32434/pci.h>
 

-#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_READ         0

 #define PCI_ACCESS_WRITE 1
 
 
 #define PCI_ACCESS_WRITE 1
 
 

diff --git a/arch/mips/pci/ops-sni.c b/arch/mips/pci/ops-sni.c
index 97ed25b92edfbee1414425ea217351c60c28e115..35daa7fe65713bee6e8bc1debea9d1e5eb515a30 100644 (file)
--- a/arch/mips/pci/ops-sni.c
+++ b/arch/mips/pci/ops-sni.c
@@ -14,8 +14,8 @@
 
 /*
  * It seems that on the RM200 only lower 3 bits of the 5 bit PCI device
 
 /*
  * It seems that on the RM200 only lower 3 bits of the 5 bit PCI device

- * address are decoded.  We therefore manually have to reject attempts at
- * reading outside this range.  Being on the paranoid side we only do this
+ * address are decoded.         We therefore manually have to reject attempts at
+ * reading outside this range. Being on the paranoid side we only do this

  * test for bus 0 and hope forwarding and decoding work properly for any
  * subordinated busses.
  *
  * test for bus 0 and hope forwarding and decoding work properly for any
  * subordinated busses.
  *


@@ -31,8 +31,8 @@ static int set_config_address(unsigned int busno, unsigned int devfn, int reg)
 
        *(volatile u32 *)PCIMT_CONFIG_ADDRESS =
                 ((busno    & 0xff) << 16) |
 
        *(volatile u32 *)PCIMT_CONFIG_ADDRESS =
                 ((busno    & 0xff) << 16) |

-                ((devfn    & 0xff) <<  8) |
-                 (reg      & 0xfc);
+                ((devfn    & 0xff) <<  8) |
+                 (reg      & 0xfc);

 
        return PCIBIOS_SUCCESSFUL;
 }
 
        return PCIBIOS_SUCCESSFUL;
 }

diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c
index 0d69d6f4ea44f72ec828c972e5d49a2d6c34902a..3d5df514d024aea51fb48553d25472cdcd1c8833 100644 (file)
--- a/arch/mips/pci/ops-tx4927.c
+++ b/arch/mips/pci/ops-tx4927.c
@@ -2,16 +2,16 @@
  * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc.
  *
  * Based on linux/arch/mips/pci/ops-tx4938.c,
  * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc.
  *
  * Based on linux/arch/mips/pci/ops-tx4938.c,

- *          linux/arch/mips/pci/fixup-rbtx4938.c,
- *          linux/arch/mips/txx9/rbtx4938/setup.c,
+ *         linux/arch/mips/pci/fixup-rbtx4938.c,
+ *         linux/arch/mips/txx9/rbtx4938/setup.c,

  *         and RBTX49xx patch from CELF patch archive.
  *
  * 2003-2005 (c) MontaVista Software, Inc.
  * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
  * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
  *
  *         and RBTX49xx patch from CELF patch archive.
  *
  * 2003-2005 (c) MontaVista Software, Inc.
  * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
  * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/pci/ops-vr41xx.c b/arch/mips/pci/ops-vr41xx.c
index 28962a7c66066140865072556c741441ee9b2fd8..551128c7d927ec6d940a5c3e79c1fa6190b42ac1 100644 (file)
--- a/arch/mips/pci/ops-vr41xx.c
+++ b/arch/mips/pci/ops-vr41xx.c
@@ -33,7 +33,7 @@
 #define PCICONFAREG    (void __iomem *)KSEG1ADDR(0x0f000c18)
 
 static inline int set_pci_configuration_address(unsigned char number,
 #define PCICONFAREG    (void __iomem *)KSEG1ADDR(0x0f000c18)
 
 static inline int set_pci_configuration_address(unsigned char number,

-                                                unsigned int devfn, int where)
+                                               unsigned int devfn, int where)

 {
        if (number == 0) {
                /*
 {
        if (number == 0) {
                /*


@@ -59,7 +59,7 @@ static inline int set_pci_configuration_address(unsigned char number,
 }
 
 static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
 }
 
 static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,

-                           int size, uint32_t *val)
+                          int size, uint32_t *val)

 {
        uint32_t data;
 
 {
        uint32_t data;
 


@@ -87,7 +87,7 @@ static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
 }
 
 static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
 }
 
 static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,

-                            int size, uint32_t val)
+                           int size, uint32_t val)

 {
        uint32_t data;
        int shift;
 {
        uint32_t data;
        int shift;

diff --git a/arch/mips/pci/pci-alchemy.c b/arch/mips/pci/pci-alchemy.c
index c4ea6cc55f946c9fe144c4225160be5e74b587ca..38a80c83fd6743c1a2e025d83b7f02d02c2f6bd5 100644 (file)
--- a/arch/mips/pci/pci-alchemy.c
+++ b/arch/mips/pci/pci-alchemy.c
@@ -29,7 +29,7 @@
 #define PCI_ACCESS_WRITE       1
 
 struct alchemy_pci_context {
 #define PCI_ACCESS_WRITE       1
 
 struct alchemy_pci_context {

-       struct pci_controller alchemy_pci_ctrl; /* leave as first member! */
+       struct pci_controller alchemy_pci_ctrl; /* leave as first member! */

        void __iomem *regs;                     /* ctrl base */
        /* tools for wired entry for config space access */
        unsigned long last_elo0;
        void __iomem *regs;                     /* ctrl base */
        /* tools for wired entry for config space access */
        unsigned long last_elo0;


@@ -381,7 +381,7 @@ static int alchemy_pci_probe(struct platform_device *pdev)
 
        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        if (!r) {
 
        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        if (!r) {

-               dev_err(&pdev->dev, "no  pcictl ctrl regs resource\n");
+               dev_err(&pdev->dev, "no  pcictl ctrl regs resource\n");

                ret = -ENODEV;
                goto out1;
        }
                ret = -ENODEV;
                goto out1;
        }


@@ -482,7 +482,7 @@ out:
 
 static struct platform_driver alchemy_pcictl_driver = {
        .probe          = alchemy_pci_probe,
 
 static struct platform_driver alchemy_pcictl_driver = {
        .probe          = alchemy_pci_probe,

-       .driver = {
+       .driver = {

                .name   = "alchemy-pci",
                .owner  = THIS_MODULE,
        },
                .name   = "alchemy-pci",
                .owner  = THIS_MODULE,
        },

diff --git a/arch/mips/pci/pci-ar724x.c b/arch/mips/pci/pci-ar724x.c
index c11c75be2d7e06ab0b1232c35926a8ec3c5ba574..279585d6eca054b525fc500b553d6e5058348606 100644 (file)
--- a/arch/mips/pci/pci-ar724x.c
+++ b/arch/mips/pci/pci-ar724x.c
@@ -177,22 +177,22 @@ static struct pci_ops ar724x_pci_ops = {
 };
 
 static struct resource ar724x_io_resource = {
 };
 
 static struct resource ar724x_io_resource = {

-       .name   = "PCI IO space",
-       .start  = 0,
-       .end    = 0,
-       .flags  = IORESOURCE_IO,
+       .name   = "PCI IO space",
+       .start  = 0,
+       .end    = 0,
+       .flags  = IORESOURCE_IO,

 };
 
 static struct resource ar724x_mem_resource = {
 };
 
 static struct resource ar724x_mem_resource = {

-       .name   = "PCI memory space",
-       .start  = AR724X_PCI_MEM_BASE,
-       .end    = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
-       .flags  = IORESOURCE_MEM,
+       .name   = "PCI memory space",
+       .start  = AR724X_PCI_MEM_BASE,
+       .end    = AR724X_PCI_MEM_BASE + AR724X_PCI_MEM_SIZE - 1,
+       .flags  = IORESOURCE_MEM,

 };
 
 static struct pci_controller ar724x_pci_controller = {
 };
 
 static struct pci_controller ar724x_pci_controller = {

-       .pci_ops        = &ar724x_pci_ops,
-       .io_resource    = &ar724x_io_resource,
+       .pci_ops        = &ar724x_pci_ops,
+       .io_resource    = &ar724x_io_resource,

        .mem_resource   = &ar724x_mem_resource,
 };
 
        .mem_resource   = &ar724x_mem_resource,
 };
 

diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
index 37b52dc3d27e808cfad0498904a98b729755d4ed..e2e69e1e9fe14fac77226b2f857db6d1b09b054e 100644 (file)
--- a/arch/mips/pci/pci-bcm1480.c
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -54,8 +54,8 @@
 
 static void *cfg_space;
 
 
 static void *cfg_space;
 

-#define PCI_BUS_ENABLED        1
-#define PCI_DEVICE_MODE        2
+#define PCI_BUS_ENABLED 1
+#define PCI_DEVICE_MODE 2

 
 static int bcm1480_bus_status;
 
 
 static int bcm1480_bus_status;
 


@@ -194,7 +194,7 @@ struct pci_controller bcm1480_controller = {
        .pci_ops        = &bcm1480_pci_ops,
        .mem_resource   = &bcm1480_mem_resource,
        .io_resource    = &bcm1480_io_resource,
        .pci_ops        = &bcm1480_pci_ops,
        .mem_resource   = &bcm1480_mem_resource,
        .io_resource    = &bcm1480_io_resource,

-       .io_offset      = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES,
+       .io_offset      = A_BCM1480_PHYS_PCI_IO_MATCH_BYTES,

 };
 
 
 };
 
 


@@ -227,7 +227,7 @@ static int __init bcm1480_pcibios_init(void)
                                             PCI_COMMAND));
                if (!(cmdreg & PCI_COMMAND_MASTER)) {
                        printk
                                             PCI_COMMAND));
                if (!(cmdreg & PCI_COMMAND_MASTER)) {
                        printk

-                           ("PCI: Skipping PCI probe.  Bus is not initialized.\n");
+                           ("PCI: Skipping PCI probe.  Bus is not initialized.\n");

                        iounmap(cfg_space);
                        return 1; /* XXX */
                }
                        iounmap(cfg_space);
                        return 1; /* XXX */
                }

diff --git a/arch/mips/pci/pci-bcm1480ht.c b/arch/mips/pci/pci-bcm1480ht.c
index 50cc6e9e8240857f95021854345ea234653ce6a2..1263c5e7dbe12d4acc0e38051d4ba12bff9cc98e 100644 (file)
--- a/arch/mips/pci/pci-bcm1480ht.c
+++ b/arch/mips/pci/pci-bcm1480ht.c
@@ -53,8 +53,8 @@
 
 static void *ht_cfg_space;
 
 
 static void *ht_cfg_space;
 

-#define PCI_BUS_ENABLED        1
-#define PCI_DEVICE_MODE        2
+#define PCI_BUS_ENABLED 1
+#define PCI_DEVICE_MODE 2

 
 static int bcm1480ht_bus_status;
 
 
 static int bcm1480ht_bus_status;
 


@@ -191,7 +191,7 @@ struct pci_controller bcm1480ht_controller = {
        .io_resource    = &bcm1480ht_io_resource,
        .index          = 1,
        .get_busno      = bcm1480ht_pcibios_get_busno,
        .io_resource    = &bcm1480ht_io_resource,
        .index          = 1,
        .get_busno      = bcm1480ht_pcibios_get_busno,

-       .io_offset      = A_BCM1480_PHYS_HT_IO_MATCH_BYTES,
+       .io_offset      = A_BCM1480_PHYS_HT_IO_MATCH_BYTES,

 };
 
 static int __init bcm1480ht_pcibios_init(void)
 };
 
 static int __init bcm1480ht_pcibios_init(void)

diff --git a/arch/mips/pci/pci-bcm47xx.c b/arch/mips/pci/pci-bcm47xx.c
index c682468010c518788a6f1c42fb2535476152ca9d..76f16eaed0ad3e9851d854d940e871c8c5f69aa9 100644 (file)
--- a/arch/mips/pci/pci-bcm47xx.c
+++ b/arch/mips/pci/pci-bcm47xx.c
@@ -91,7 +91,7 @@ static int bcm47xx_pcibios_plat_dev_init_bcma(struct pci_dev *dev)
 int pcibios_plat_dev_init(struct pci_dev *dev)
 {
 #ifdef CONFIG_BCM47XX_SSB
 int pcibios_plat_dev_init(struct pci_dev *dev)
 {
 #ifdef CONFIG_BCM47XX_SSB

-       if (bcm47xx_bus_type ==  BCM47XX_BUS_TYPE_SSB)
+       if (bcm47xx_bus_type ==  BCM47XX_BUS_TYPE_SSB)

                return bcm47xx_pcibios_plat_dev_init_ssb(dev);
        else
 #endif
                return bcm47xx_pcibios_plat_dev_init_ssb(dev);
        else
 #endif

diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index ca179b6ff39b374e0743f76815775972e29e15c0..88e781c6b5bab274b53f76c55b7f51c2356b1bc6 100644 (file)
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -25,21 +25,21 @@
 int bcm63xx_pci_enabled;
 
 static struct resource bcm_pci_mem_resource = {
 int bcm63xx_pci_enabled;
 
 static struct resource bcm_pci_mem_resource = {

-       .name   = "bcm63xx PCI memory space",
-       .start  = BCM_PCI_MEM_BASE_PA,
-       .end    = BCM_PCI_MEM_END_PA,
-       .flags  = IORESOURCE_MEM
+       .name   = "bcm63xx PCI memory space",
+       .start  = BCM_PCI_MEM_BASE_PA,
+       .end    = BCM_PCI_MEM_END_PA,
+       .flags  = IORESOURCE_MEM

 };
 
 static struct resource bcm_pci_io_resource = {
 };
 
 static struct resource bcm_pci_io_resource = {

-       .name   = "bcm63xx PCI IO space",
-       .start  = BCM_PCI_IO_BASE_PA,
+       .name   = "bcm63xx PCI IO space",
+       .start  = BCM_PCI_IO_BASE_PA,

 #ifdef CONFIG_CARDBUS
 #ifdef CONFIG_CARDBUS

-       .end    = BCM_PCI_IO_HALF_PA,
+       .end    = BCM_PCI_IO_HALF_PA,

 #else
 #else

-       .end    = BCM_PCI_IO_END_PA,
+       .end    = BCM_PCI_IO_END_PA,

 #endif
 #endif

-       .flags  = IORESOURCE_IO
+       .flags  = IORESOURCE_IO

 };
 
 struct pci_controller bcm63xx_controller = {
 };
 
 struct pci_controller bcm63xx_controller = {


@@ -55,17 +55,17 @@ struct pci_controller bcm63xx_controller = {
  */
 #ifdef CONFIG_CARDBUS
 static struct resource bcm_cb_mem_resource = {
  */
 #ifdef CONFIG_CARDBUS
 static struct resource bcm_cb_mem_resource = {

-       .name   = "bcm63xx Cardbus memory space",
-       .start  = BCM_CB_MEM_BASE_PA,
-       .end    = BCM_CB_MEM_END_PA,
-       .flags  = IORESOURCE_MEM
+       .name   = "bcm63xx Cardbus memory space",
+       .start  = BCM_CB_MEM_BASE_PA,
+       .end    = BCM_CB_MEM_END_PA,
+       .flags  = IORESOURCE_MEM

 };
 
 static struct resource bcm_cb_io_resource = {
 };
 
 static struct resource bcm_cb_io_resource = {

-       .name   = "bcm63xx Cardbus IO space",
-       .start  = BCM_PCI_IO_HALF_PA + 1,
-       .end    = BCM_PCI_IO_END_PA,
-       .flags  = IORESOURCE_IO
+       .name   = "bcm63xx Cardbus IO space",
+       .start  = BCM_PCI_IO_HALF_PA + 1,
+       .end    = BCM_PCI_IO_END_PA,
+       .flags  = IORESOURCE_IO

 };
 
 struct pci_controller bcm63xx_cb_controller = {
 };
 
 struct pci_controller bcm63xx_cb_controller = {


@@ -76,17 +76,17 @@ struct pci_controller bcm63xx_cb_controller = {
 #endif
 
 static struct resource bcm_pcie_mem_resource = {
 #endif
 
 static struct resource bcm_pcie_mem_resource = {

-       .name   = "bcm63xx PCIe memory space",
-       .start  = BCM_PCIE_MEM_BASE_PA,
-       .end    = BCM_PCIE_MEM_END_PA,
-       .flags  = IORESOURCE_MEM,
+       .name   = "bcm63xx PCIe memory space",
+       .start  = BCM_PCIE_MEM_BASE_PA,
+       .end    = BCM_PCIE_MEM_END_PA,
+       .flags  = IORESOURCE_MEM,

 };
 
 static struct resource bcm_pcie_io_resource = {
 };
 
 static struct resource bcm_pcie_io_resource = {

-       .name   = "bcm63xx PCIe IO space",
-       .start  = 0,
-       .end    = 0,
-       .flags  = 0,
+       .name   = "bcm63xx PCIe IO space",
+       .start  = 0,
+       .end    = 0,
+       .flags  = 0,

 };
 
 struct pci_controller bcm63xx_pcie_controller = {
 };
 
 struct pci_controller bcm63xx_pcie_controller = {


@@ -111,7 +111,7 @@ static void bcm63xx_int_cfg_writel(u32 val, u32 reg)
        u32 tmp;
 
        tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
        u32 tmp;
 
        tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;

-       tmp |=  MPI_PCICFGCTL_WRITEEN_MASK;
+       tmp |=  MPI_PCICFGCTL_WRITEEN_MASK;

        bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
        bcm_mpi_writel(val, MPI_PCICFGDATA_REG);
 }
        bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG);
        bcm_mpi_writel(val, MPI_PCICFGDATA_REG);
 }


@@ -211,7 +211,7 @@ static int __init bcm63xx_register_pci(void)
         * first bytes to access it from CPU.
         *
         * this means that  no io access from CPU  should happen while
         * first bytes to access it from CPU.
         *
         * this means that  no io access from CPU  should happen while

-        * we do a configuration cycle,  but there's no way we can add
+        * we do a configuration cycle,  but there's no way we can add

         * a spinlock for each io access, so this is currently kind of
         * broken on SMP.
         */
         * a spinlock for each io access, so this is currently kind of
         * broken on SMP.
         */


@@ -244,9 +244,9 @@ static int __init bcm63xx_register_pci(void)
        bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG);
 #endif
 
        bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG);
 #endif
 

-       /* setup local bus  to PCI access (IO memory),  we have only 1
-        * IO window  for both PCI  and cardbus, but it  cannot handle
-        * both  at the  same time,  assume standard  PCI for  now, if
+       /* setup local bus  to PCI access (IO memory),  we have only 1
+        * IO window  for both PCI  and cardbus, but it  cannot handle
+        * both  at the  same time,  assume standard  PCI for  now, if

         * cardbus card has  IO zone, PCI fixup will  change window to
         * cardbus */
        val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK;
         * cardbus card has  IO zone, PCI fixup will  change window to
         * cardbus */
        val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK;


@@ -284,7 +284,7 @@ static int __init bcm63xx_register_pci(void)
                bcm_mpi_writel(0, MPI_SP1_RANGE_REG);
        }
 
                bcm_mpi_writel(0, MPI_SP1_RANGE_REG);
        }
 

-       /* change  host bridge  retry  counter to  infinite number  of
+       /* change  host bridge  retry  counter to  infinite number  of

         * retry,  needed for  some broadcom  wifi cards  with Silicon
         * Backplane bus where access to srom seems very slow  */
        val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS);
         * retry,  needed for  some broadcom  wifi cards  with Silicon
         * Backplane bus where access to srom seems very slow  */
        val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS);

diff --git a/arch/mips/pci/pci-bcm63xx.h b/arch/mips/pci/pci-bcm63xx.h
index e6736d558ac746ea7125d831c8644479ca464c91..ffab4da7bd00eee6b899bbee8bf311b6d2a4276e 100644 (file)
--- a/arch/mips/pci/pci-bcm63xx.h
+++ b/arch/mips/pci/pci-bcm63xx.h
@@ -7,7 +7,7 @@
 #include <bcm63xx_dev_pci.h>
 
 /*
 #include <bcm63xx_dev_pci.h>
 
 /*

- * Cardbus shares  the PCI bus, but has  no IDSEL, so a  special id is
+ * Cardbus shares  the PCI bus, but has         no IDSEL, so a  special id is

  * reserved for it.  If you have a standard PCI device at this id, you
  * need to change the following definition.
  */
  * reserved for it.  If you have a standard PCI device at this id, you
  * need to change the following definition.
  */

diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index 7f4f49b09b5b90ba62b1cae28685066b11063ff2..6eb65e44d9e4a36ef94e6967c22acb648dc7b3d0 100644 (file)
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -30,7 +30,7 @@
 
 /*
  * XXX: No kmalloc available when we do our crosstalk scan,
 
 /*
  * XXX: No kmalloc available when we do our crosstalk scan,

- *     we should try to move it later in the boot process.
+ *     we should try to move it later in the boot process.

  */
 static struct bridge_controller bridges[MAX_PCI_BUSSES];
 
  */
 static struct bridge_controller bridges[MAX_PCI_BUSSES];
 


@@ -103,7 +103,7 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
         * swap pio's to pci mem and io space (big windows)
         */
        bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP |
         * swap pio's to pci mem and io space (big windows)
         */
        bridge->b_wid_control |= BRIDGE_CTRL_IO_SWAP |

-                                BRIDGE_CTRL_MEM_SWAP;
+                                BRIDGE_CTRL_MEM_SWAP;

 #ifdef CONFIG_PAGE_SIZE_4KB
        bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
 #else /* 16kB or larger */
 #ifdef CONFIG_PAGE_SIZE_4KB
        bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
 #else /* 16kB or larger */


@@ -123,7 +123,7 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid)
                bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR;
                bc->pci_int[slot] = -1;
        }
                bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR;
                bc->pci_int[slot] = -1;
        }

-       bridge->b_wid_tflush;     /* wait until Bridge PIO complete */
+       bridge->b_wid_tflush;     /* wait until Bridge PIO complete */

 
        bc->base = bridge;
 
 
        bc->base = bridge;
 


@@ -184,7 +184,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
 }
 
 /*
 }
 
 /*

- * Device might live on a subordinate PCI bus.  XXX Walk up the chain of buses
+ * Device might live on a subordinate PCI bus. XXX Walk up the chain of buses

  * to find the slot number in sense of the bridge device register.
  * XXX This also means multiple devices might rely on conflicting bridge
  * settings.
  * to find the slot number in sense of the bridge device register.
  * XXX This also means multiple devices might rely on conflicting bridge
  * settings.

diff --git a/arch/mips/pci/pci-ip32.c b/arch/mips/pci/pci-ip32.c
index 532b561b44425d5fa58c951b0bbce8d25b2069eb..b1e061f7fdc7115a08b168afd49e0e4af9816a72 100644 (file)
--- a/arch/mips/pci/pci-ip32.c
+++ b/arch/mips/pci/pci-ip32.c
@@ -18,9 +18,9 @@
 
 /*
  * Handle errors from the bridge.  This includes master and target aborts,
 
 /*
  * Handle errors from the bridge.  This includes master and target aborts,

- * various command and address errors, and the interrupt test.  This gets
- * registered on the bridge error irq.  It's conceivable that some of these
- * conditions warrant a panic.  Anybody care to say which ones?
+ * various command and address errors, and the interrupt test. This gets
+ * registered on the bridge error irq. It's conceivable that some of these
+ * conditions warrant a panic. Anybody care to say which ones?

  */
 static irqreturn_t macepci_error(int irq, void *dev)
 {
  */
 static irqreturn_t macepci_error(int irq, void *dev)
 {

diff --git a/arch/mips/pci/pci-lasat.c b/arch/mips/pci/pci-lasat.c
index a98e543a514ab016e1f815e68fc572bc755f12fb..40d2797d2bc43b255edd050cf17d270cdbc4325d 100644 (file)
--- a/arch/mips/pci/pci-lasat.c
+++ b/arch/mips/pci/pci-lasat.c
@@ -51,15 +51,15 @@ static int __init lasat_pci_setup(void)
 
 arch_initcall(lasat_pci_setup);
 
 
 arch_initcall(lasat_pci_setup);
 

-#define LASAT_IRQ_ETH1   (LASAT_IRQ_BASE + 0)
-#define LASAT_IRQ_ETH0   (LASAT_IRQ_BASE + 1)
-#define LASAT_IRQ_HDC    (LASAT_IRQ_BASE + 2)
-#define LASAT_IRQ_COMP   (LASAT_IRQ_BASE + 3)
-#define LASAT_IRQ_HDLC   (LASAT_IRQ_BASE + 4)
-#define LASAT_IRQ_PCIA   (LASAT_IRQ_BASE + 5)
-#define LASAT_IRQ_PCIB   (LASAT_IRQ_BASE + 6)
-#define LASAT_IRQ_PCIC   (LASAT_IRQ_BASE + 7)
-#define LASAT_IRQ_PCID   (LASAT_IRQ_BASE + 8)
+#define LASAT_IRQ_ETH1  (LASAT_IRQ_BASE + 0)
+#define LASAT_IRQ_ETH0  (LASAT_IRQ_BASE + 1)
+#define LASAT_IRQ_HDC   (LASAT_IRQ_BASE + 2)
+#define LASAT_IRQ_COMP  (LASAT_IRQ_BASE + 3)
+#define LASAT_IRQ_HDLC  (LASAT_IRQ_BASE + 4)
+#define LASAT_IRQ_PCIA  (LASAT_IRQ_BASE + 5)
+#define LASAT_IRQ_PCIB  (LASAT_IRQ_BASE + 6)
+#define LASAT_IRQ_PCIC  (LASAT_IRQ_BASE + 7)
+#define LASAT_IRQ_PCID  (LASAT_IRQ_BASE + 8)

 
 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
 
 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {


@@ -69,13 +69,13 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
        case 3:
                return LASAT_IRQ_PCIA + (((slot-1) + (pin-1)) % 4);
        case 4:
        case 3:
                return LASAT_IRQ_PCIA + (((slot-1) + (pin-1)) % 4);
        case 4:

-               return LASAT_IRQ_ETH1;   /* Ethernet 1 (LAN 2) */
+               return LASAT_IRQ_ETH1;   /* Ethernet 1 (LAN 2) */

        case 5:
        case 5:

-               return LASAT_IRQ_ETH0;   /* Ethernet 0 (LAN 1) */
+               return LASAT_IRQ_ETH0;   /* Ethernet 0 (LAN 1) */

        case 6:
        case 6:

-               return LASAT_IRQ_HDC;    /* IDE controller */
+               return LASAT_IRQ_HDC;    /* IDE controller */

        default:
        default:

-               return 0xff;            /* Illegal */
+               return 0xff;            /* Illegal */

        }
 
        return -1;
        }
 
        return -1;

diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index 5b5ed76c6f47a811676e5026f0c1b2843482005b..95c2ea815cacc4c6962025086fd4de4bcc0ef4a9 100644 (file)
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -30,8 +30,8 @@
  * addresses. Use PCI endian swapping 1 so no address swapping is
  * necessary. The Linux io routines will endian swap the data.
  */
  * addresses. Use PCI endian swapping 1 so no address swapping is
  * necessary. The Linux io routines will endian swap the data.
  */

-#define OCTEON_PCI_IOSPACE_BASE     0x80011a0400000000ull
-#define OCTEON_PCI_IOSPACE_SIZE     (1ull<<32)
+#define OCTEON_PCI_IOSPACE_BASE            0x80011a0400000000ull
+#define OCTEON_PCI_IOSPACE_SIZE            (1ull<<32)

 
 /* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */
 #define OCTEON_PCI_MEMSPACE_OFFSET  (0x00011b0000000000ull)
 
 /* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */
 #define OCTEON_PCI_MEMSPACE_OFFSET  (0x00011b0000000000ull)


@@ -68,10 +68,10 @@ enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
  *
  * @dev:    The Linux PCI device structure for the device to map
  * @slot:   The slot number for this device on __BUS 0__. Linux
  *
  * @dev:    The Linux PCI device structure for the device to map
  * @slot:   The slot number for this device on __BUS 0__. Linux

- *               enumerates through all the bridges and figures out the
- *               slot on Bus 0 where this device eventually hooks to.
+ *              enumerates through all the bridges and figures out the
+ *              slot on Bus 0 where this device eventually hooks to.

  * @pin:    The PCI interrupt pin read from the device, then swizzled
  * @pin:    The PCI interrupt pin read from the device, then swizzled

- *               as it goes through each bridge.
+ *              as it goes through each bridge.

  * Returns Interrupt number for the device
  */
 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  * Returns Interrupt number for the device
  */
 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)


@@ -120,8 +120,8 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
        /* Enable the PCIe normal error reporting */
        config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
        config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */
        /* Enable the PCIe normal error reporting */
        config = PCI_EXP_DEVCTL_CERE; /* Correctable Error Reporting */
        config |= PCI_EXP_DEVCTL_NFERE; /* Non-Fatal Error Reporting */

-       config |= PCI_EXP_DEVCTL_FERE;  /* Fatal Error Reporting */
-       config |= PCI_EXP_DEVCTL_URRE;  /* Unsupported Request */
+       config |= PCI_EXP_DEVCTL_FERE;  /* Fatal Error Reporting */
+       config |= PCI_EXP_DEVCTL_URRE;  /* Unsupported Request */

        pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config);
 
        /* Find the Advanced Error Reporting capability */
        pcie_capability_set_word(dev, PCI_EXP_DEVCTL, config);
 
        /* Find the Advanced Error Reporting capability */


@@ -226,10 +226,10 @@ const char *octeon_get_pci_interrupts(void)
  *
  * @dev:    The Linux PCI device structure for the device to map
  * @slot:   The slot number for this device on __BUS 0__. Linux
  *
  * @dev:    The Linux PCI device structure for the device to map
  * @slot:   The slot number for this device on __BUS 0__. Linux

- *               enumerates through all the bridges and figures out the
- *               slot on Bus 0 where this device eventually hooks to.
+ *              enumerates through all the bridges and figures out the
+ *              slot on Bus 0 where this device eventually hooks to.

  * @pin:    The PCI interrupt pin read from the device, then swizzled
  * @pin:    The PCI interrupt pin read from the device, then swizzled

- *               as it goes through each bridge.
+ *              as it goes through each bridge.

  * Returns Interrupt number for the device
  */
 int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,
  * Returns Interrupt number for the device
  */
 int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,


@@ -404,8 +404,8 @@ static void octeon_pci_initialize(void)
                ctl_status_2.s.bb1_siz = 1;  /* BAR1 is 2GB */
                ctl_status_2.s.bb_ca = 1;    /* Don't use L2 with big bars */
                ctl_status_2.s.bb_es = 1;    /* Big bar in byte swap mode */
                ctl_status_2.s.bb1_siz = 1;  /* BAR1 is 2GB */
                ctl_status_2.s.bb_ca = 1;    /* Don't use L2 with big bars */
                ctl_status_2.s.bb_es = 1;    /* Big bar in byte swap mode */

-               ctl_status_2.s.bb1 = 1;      /* BAR1 is big */
-               ctl_status_2.s.bb0 = 1;      /* BAR0 is big */
+               ctl_status_2.s.bb1 = 1;      /* BAR1 is big */
+               ctl_status_2.s.bb0 = 1;      /* BAR0 is big */

        }
 
        octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32);
        }
 
        octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32);


@@ -446,7 +446,7 @@ static void octeon_pci_initialize(void)
                 * count. [1..31] and 0=32.  NOTE: If the user
                 * programs these bits beyond the Designed Maximum
                 * outstanding count, then the designed maximum table
                 * count. [1..31] and 0=32.  NOTE: If the user
                 * programs these bits beyond the Designed Maximum
                 * outstanding count, then the designed maximum table

-                * depth will be used instead.  No additional
+                * depth will be used instead.  No additional

                 * Deferred/Split transactions will be accepted if
                 * this outstanding maximum count is
                 * reached. Furthermore, no additional deferred/split
                 * Deferred/Split transactions will be accepted if
                 * this outstanding maximum count is
                 * reached. Furthermore, no additional deferred/split


@@ -456,7 +456,7 @@ static void octeon_pci_initialize(void)
                cfg19.s.tdomc = 4;
                /*
                 * Master Deferred Read Request Outstanding Max Count
                cfg19.s.tdomc = 4;
                /*
                 * Master Deferred Read Request Outstanding Max Count

-                * (PCI only).  CR4C[26:24] Max SAC cycles MAX DAC
+                * (PCI only).  CR4C[26:24] Max SAC cycles MAX DAC

                 * cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101
                 * 5 2 110 6 3 111 7 3 For example, if these bits are
                 * programmed to 100, the core can support 2 DAC
                 * cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101
                 * 5 2 110 6 3 111 7 3 For example, if these bits are
                 * programmed to 100, the core can support 2 DAC


@@ -550,7 +550,7 @@ static void octeon_pci_initialize(void)
 
        /*
         * Affects PCI performance when OCTEON services reads to its
 
        /*
         * Affects PCI performance when OCTEON services reads to its

-        * BAR1/BAR2. Refer to Section 10.6.1.  The recommended values are
+        * BAR1/BAR2. Refer to Section 10.6.1.  The recommended values are

         * 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and
         * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700,
         * these values need to be changed so they won't possibly prefetch off
         * 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and
         * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700,
         * these values need to be changed so they won't possibly prefetch off

diff --git a/arch/mips/pci/pci-rc32434.c b/arch/mips/pci/pci-rc32434.c
index 5f3a69cebad1d51554052bec403279972d5023ee..b128cb973ebe6163ef5b3f8fa5704f1fc943a18f 100644 (file)
--- a/arch/mips/pci/pci-rc32434.c
+++ b/arch/mips/pci/pci-rc32434.c
@@ -33,7 +33,7 @@
 #include <asm/mach-rc32434/rc32434.h>
 #include <asm/mach-rc32434/pci.h>
 
 #include <asm/mach-rc32434/rc32434.h>
 #include <asm/mach-rc32434/pci.h>
 

-#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_READ         0

 #define PCI_ACCESS_WRITE 1
 
 /* define an unsigned array for the PCI registers */
 #define PCI_ACCESS_WRITE 1
 
 /* define an unsigned array for the PCI registers */


@@ -82,11 +82,11 @@ extern struct pci_ops rc32434_pci_ops;
 #define PCI_MEM2_START (PCI_ADDR_START + CPUTOPCI_MEM_WIN)
 #define PCI_MEM2_END   (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)  - 1)
 #define PCI_IO1_START  (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN))
 #define PCI_MEM2_START (PCI_ADDR_START + CPUTOPCI_MEM_WIN)
 #define PCI_MEM2_END   (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)  - 1)
 #define PCI_IO1_START  (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN))

-#define PCI_IO1_END                                                    \
+#define PCI_IO1_END                                                    \

        (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN - 1)
 #define PCI_IO2_START                                                  \
        (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN)
        (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN - 1)
 #define PCI_IO2_START                                                  \
        (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN)

-#define PCI_IO2_END                                                    \
+#define PCI_IO2_END                                                    \

        (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) - 1)
 
 struct pci_controller rc32434_controller2;
        (PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) - 1)
 
 struct pci_controller rc32434_controller2;

diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c
index dd97f3a83baa26f0c42daddb9a70dfad278f30fd..cdefcc4cb8d448c36b3bd4a52f448e3288ae32f9 100644 (file)
--- a/arch/mips/pci/pci-sb1250.c
+++ b/arch/mips/pci/pci-sb1250.c
@@ -55,9 +55,9 @@
 
 static void *cfg_space;
 
 
 static void *cfg_space;
 

-#define PCI_BUS_ENABLED        1
-#define LDT_BUS_ENABLED        2
-#define PCI_DEVICE_MODE        4
+#define PCI_BUS_ENABLED 1
+#define LDT_BUS_ENABLED 2
+#define PCI_DEVICE_MODE 4

 
 static int sb1250_bus_status;
 
 
 static int sb1250_bus_status;
 


@@ -239,7 +239,7 @@ static int __init sb1250_pcibios_init(void)
                               PCI_COMMAND));
                if (!(cmdreg & PCI_COMMAND_MASTER)) {
                        printk
                               PCI_COMMAND));
                if (!(cmdreg & PCI_COMMAND_MASTER)) {
                        printk

-                           ("PCI: Skipping PCI probe.  Bus is not initialized.\n");
+                           ("PCI: Skipping PCI probe.  Bus is not initialized.\n");

                        iounmap(cfg_space);
                        return 0;
                }
                        iounmap(cfg_space);
                        return 0;
                }

diff --git a/arch/mips/pci/pci-vr41xx.c b/arch/mips/pci/pci-vr41xx.c
index 444b8d8004ad392d34dd69e3f63006365396df43..157c7715b7c8e92d125d3292f9de1775ca61d892 100644 (file)
--- a/arch/mips/pci/pci-vr41xx.c
+++ b/arch/mips/pci/pci-vr41xx.c
@@ -69,17 +69,17 @@ static struct pci_target_address_window pci_target_window1 = {
 };
 
 static struct resource pci_mem_resource = {
 };
 
 static struct resource pci_mem_resource = {

-       .name   = "PCI Memory resources",
-       .start  = PCI_MEM_RESOURCE_START,
-       .end    = PCI_MEM_RESOURCE_END,
-       .flags  = IORESOURCE_MEM,
+       .name   = "PCI Memory resources",
+       .start  = PCI_MEM_RESOURCE_START,
+       .end    = PCI_MEM_RESOURCE_END,
+       .flags  = IORESOURCE_MEM,

 };
 
 static struct resource pci_io_resource = {
 };
 
 static struct resource pci_io_resource = {

-       .name   = "PCI I/O resources",
-       .start  = PCI_IO_RESOURCE_START,
-       .end    = PCI_IO_RESOURCE_END,
-       .flags  = IORESOURCE_IO,
+       .name   = "PCI I/O resources",
+       .start  = PCI_IO_RESOURCE_START,
+       .end    = PCI_IO_RESOURCE_END,
+       .flags  = IORESOURCE_IO,

 };
 
 static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = {
 };
 
 static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = {


@@ -97,7 +97,7 @@ static struct pci_controller_unit_setup vr41xx_pci_controller_unit_setup = {
 };
 
 static struct pci_controller vr41xx_pci_controller = {
 };
 
 static struct pci_controller vr41xx_pci_controller = {

-       .pci_ops        = &vr41xx_pci_ops,
+       .pci_ops        = &vr41xx_pci_ops,

        .mem_resource   = &pci_mem_resource,
        .io_resource    = &pci_io_resource,
 };
        .mem_resource   = &pci_mem_resource,
        .io_resource    = &pci_io_resource,
 };


@@ -148,7 +148,7 @@ static int __init vr41xx_pciu_init(void)
        else if ((vtclock / 2) < pci_clock_max)
                pciu_write(PCICLKSELREG, HALF_VTCLOCK);
        else if (current_cpu_data.processor_id >= PRID_VR4131_REV2_1 &&
        else if ((vtclock / 2) < pci_clock_max)
                pciu_write(PCICLKSELREG, HALF_VTCLOCK);
        else if (current_cpu_data.processor_id >= PRID_VR4131_REV2_1 &&

-                (vtclock / 3) < pci_clock_max)
+                (vtclock / 3) < pci_clock_max)

                pciu_write(PCICLKSELREG, ONE_THIRD_VTCLOCK);
        else if ((vtclock / 4) < pci_clock_max)
                pciu_write(PCICLKSELREG, QUARTER_VTCLOCK);
                pciu_write(PCICLKSELREG, ONE_THIRD_VTCLOCK);
        else if ((vtclock / 4) < pci_clock_max)
                pciu_write(PCICLKSELREG, QUARTER_VTCLOCK);


@@ -281,7 +281,7 @@ static int __init vr41xx_pciu_init(void)
        pciu_write(PCIAPCNTREG, val);
 
        pciu_write(COMMANDREG, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
        pciu_write(PCIAPCNTREG, val);
 
        pciu_write(COMMANDREG, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |

-                              PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
+                              PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |

                               PCI_COMMAND_SERR);
 
        /* Clear bus error */
                               PCI_COMMAND_SERR);
 
        /* Clear bus error */

diff --git a/arch/mips/pci/pci-vr41xx.h b/arch/mips/pci/pci-vr41xx.h
index 6b1ae2eb1c065bc3b5b547ec6ff6258e14f05926..e6b4a1b969f7774539406600d657ae272a6b631a 100644 (file)
--- a/arch/mips/pci/pci-vr41xx.h
+++ b/arch/mips/pci/pci-vr41xx.h
@@ -1,7 +1,7 @@
 /*
  *  pci-vr41xx.h, Include file for PCI Control Unit of the NEC VR4100 series.
  *
 /*
  *  pci-vr41xx.h, Include file for PCI Control Unit of the NEC VR4100 series.
  *

- *  Copyright (C) 2002  MontaVista Software Inc.
+ *  Copyright (C) 2002 MontaVista Software Inc.

  *    Author: Yoichi Yuasa <source@mvista.com>
  *  Copyright (C) 2004-2005  Yoichi Yuasa <yuasa@linux-mips.org>
  *
  *    Author: Yoichi Yuasa <source@mvista.com>
  *  Copyright (C) 2004-2005  Yoichi Yuasa <yuasa@linux-mips.org>
  *

diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c
index 140557a20488fdcb049013de83cc66043a83e205..ad55f2cfeec14d7ee35b11be37b1f3c2d00b96c3 100644 (file)
--- a/arch/mips/pci/pci-xlp.c
+++ b/arch/mips/pci/pci-xlp.c
@@ -55,7 +55,7 @@
 
 static void *pci_config_base;
 
 
 static void *pci_config_base;
 

-#define        pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))
+#define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off))

 
 /* PCI ops */
 static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
 
 /* PCI ops */
 static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,


@@ -135,26 +135,26 @@ struct pci_ops nlm_pci_ops = {
 };
 
 static struct resource nlm_pci_mem_resource = {
 };
 
 static struct resource nlm_pci_mem_resource = {

-       .name           = "XLP PCI MEM",
-       .start          = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
-       .end            = 0xdfffffffUL,
-       .flags          = IORESOURCE_MEM,
+       .name           = "XLP PCI MEM",
+       .start          = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
+       .end            = 0xdfffffffUL,
+       .flags          = IORESOURCE_MEM,

 };
 
 static struct resource nlm_pci_io_resource = {
 };
 
 static struct resource nlm_pci_io_resource = {

-       .name           = "XLP IO MEM",
-       .start          = 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */
-       .end            = 0x17ffffffUL,
-       .flags          = IORESOURCE_IO,
+       .name           = "XLP IO MEM",
+       .start          = 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */
+       .end            = 0x17ffffffUL,
+       .flags          = IORESOURCE_IO,

 };
 
 struct pci_controller nlm_pci_controller = {
 };
 
 struct pci_controller nlm_pci_controller = {

-       .index          = 0,
-       .pci_ops        = &nlm_pci_ops,
-       .mem_resource   = &nlm_pci_mem_resource,
-       .mem_offset     = 0x00000000UL,
-       .io_resource    = &nlm_pci_io_resource,
-       .io_offset      = 0x00000000UL,
+       .index          = 0,
+       .pci_ops        = &nlm_pci_ops,
+       .mem_resource   = &nlm_pci_mem_resource,
+       .mem_offset     = 0x00000000UL,
+       .io_resource    = &nlm_pci_io_resource,
+       .io_offset      = 0x00000000UL,

 };
 
 static int get_irq_vector(const struct pci_dev *dev)
 };
 
 static int get_irq_vector(const struct pci_dev *dev)


@@ -232,7 +232,7 @@ static int __init pcibios_init(void)
        pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20);
 
        /* Extend IO port for memory mapped io */
        pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20);
 
        /* Extend IO port for memory mapped io */

-       ioport_resource.start =  0;
+       ioport_resource.start =  0;

        ioport_resource.end   = ~0;
 
        xlp_enable_pci_bswap();
        ioport_resource.end   = ~0;
 
        xlp_enable_pci_bswap();

diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c
index 0c18ccc79623d7d6cefe35b03a7ba36c232d1c8b..4427abbd48b547a606fbe47a6d6bf7e5497b2bd7 100644 (file)
--- a/arch/mips/pci/pci-xlr.c
+++ b/arch/mips/pci/pci-xlr.c
@@ -56,7 +56,7 @@
 
 static void *pci_config_base;
 
 
 static void *pci_config_base;
 

-#define        pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off))
+#define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off))

 
 /* PCI ops */
 static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,
 
 /* PCI ops */
 static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn,


@@ -136,26 +136,26 @@ struct pci_ops nlm_pci_ops = {
 };
 
 static struct resource nlm_pci_mem_resource = {
 };
 
 static struct resource nlm_pci_mem_resource = {

-       .name           = "XLR PCI MEM",
-       .start          = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
-       .end            = 0xdfffffffUL,
-       .flags          = IORESOURCE_MEM,
+       .name           = "XLR PCI MEM",
+       .start          = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */
+       .end            = 0xdfffffffUL,
+       .flags          = IORESOURCE_MEM,

 };
 
 static struct resource nlm_pci_io_resource = {
 };
 
 static struct resource nlm_pci_io_resource = {

-       .name           = "XLR IO MEM",
-       .start          = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */
-       .end            = 0x100fffffUL,
-       .flags          = IORESOURCE_IO,
+       .name           = "XLR IO MEM",
+       .start          = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */
+       .end            = 0x100fffffUL,
+       .flags          = IORESOURCE_IO,

 };
 
 struct pci_controller nlm_pci_controller = {
 };
 
 struct pci_controller nlm_pci_controller = {

-       .index          = 0,
-       .pci_ops        = &nlm_pci_ops,
-       .mem_resource   = &nlm_pci_mem_resource,
-       .mem_offset     = 0x00000000UL,
-       .io_resource    = &nlm_pci_io_resource,
-       .io_offset      = 0x00000000UL,
+       .index          = 0,
+       .pci_ops        = &nlm_pci_ops,
+       .mem_resource   = &nlm_pci_mem_resource,
+       .mem_offset     = 0x00000000UL,
+       .io_resource    = &nlm_pci_io_resource,
+       .io_offset      = 0x00000000UL,

 };
 
 /*
 };
 
 /*


@@ -259,7 +259,7 @@ int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
                MSI_ADDR_REDIRECTION_CPU;
 
        msg.data = MSI_DATA_TRIGGER_EDGE |
                MSI_ADDR_REDIRECTION_CPU;
 
        msg.data = MSI_DATA_TRIGGER_EDGE |

-               MSI_DATA_LEVEL_ASSERT    |
+               MSI_DATA_LEVEL_ASSERT    |

                MSI_DATA_DELIVERY_FIXED;
 
        ret = irq_set_msi_desc(irq, desc);
                MSI_DATA_DELIVERY_FIXED;
 
        ret = irq_set_msi_desc(irq, desc);


@@ -344,7 +344,7 @@ static int __init pcibios_init(void)
        pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20);
 
        /* Extend IO port for memory mapped io */
        pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20);
 
        /* Extend IO port for memory mapped io */

-       ioport_resource.start =  0;
+       ioport_resource.start =  0;

        ioport_resource.end   = ~0;
 
        set_io_port_base(CKSEG1);
        ioport_resource.end   = ~0;
 
        set_io_port_base(CKSEG1);

diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index a1843448fad38de52d8a53316ade498a8a7bd5b8..e8a14a6514cfe84ee8fcf780089ec155d106d5c4 100644 (file)
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -1,6 +1,6 @@
 /*
 /*

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  *
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  *

diff --git a/arch/mips/pci/pcie-octeon.c b/arch/mips/pci/pcie-octeon.c
index fdb4d558c0cc0d0b40332d6e38b37c33bc8a3169..5e36c33e5543fbc2c8a3227ab7dbf6b287f8931a 100644 (file)
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -43,7 +43,7 @@ union cvmx_pcie_address {
                uint64_t upper:2;       /* Normally 2 for XKPHYS */
                uint64_t reserved_49_61:13;     /* Must be zero */
                uint64_t io:1;  /* 1 for IO space access */
                uint64_t upper:2;       /* Normally 2 for XKPHYS */
                uint64_t reserved_49_61:13;     /* Must be zero */
                uint64_t io:1;  /* 1 for IO space access */

-               uint64_t did:5; /* PCIe DID = 3 */
+               uint64_t did:5; /* PCIe DID = 3 */

                uint64_t subdid:3;      /* PCIe SubDID = 1 */
                uint64_t reserved_36_39:4;      /* Must be zero */
                uint64_t es:2;  /* Endian swap = 1 */
                uint64_t subdid:3;      /* PCIe SubDID = 1 */
                uint64_t reserved_36_39:4;      /* Must be zero */
                uint64_t es:2;  /* Endian swap = 1 */


@@ -74,7 +74,7 @@ union cvmx_pcie_address {
                uint64_t upper:2;       /* Normally 2 for XKPHYS */
                uint64_t reserved_49_61:13;     /* Must be zero */
                uint64_t io:1;  /* 1 for IO space access */
                uint64_t upper:2;       /* Normally 2 for XKPHYS */
                uint64_t reserved_49_61:13;     /* Must be zero */
                uint64_t io:1;  /* 1 for IO space access */

-               uint64_t did:5; /* PCIe DID = 3 */
+               uint64_t did:5; /* PCIe DID = 3 */

                uint64_t subdid:3;      /* PCIe SubDID = 2 */
                uint64_t reserved_36_39:4;      /* Must be zero */
                uint64_t es:2;  /* Endian swap = 1 */
                uint64_t subdid:3;      /* PCIe SubDID = 2 */
                uint64_t reserved_36_39:4;      /* Must be zero */
                uint64_t es:2;  /* Endian swap = 1 */


@@ -85,7 +85,7 @@ union cvmx_pcie_address {
                uint64_t upper:2;       /* Normally 2 for XKPHYS */
                uint64_t reserved_49_61:13;     /* Must be zero */
                uint64_t io:1;  /* 1 for IO space access */
                uint64_t upper:2;       /* Normally 2 for XKPHYS */
                uint64_t reserved_49_61:13;     /* Must be zero */
                uint64_t io:1;  /* 1 for IO space access */

-               uint64_t did:5; /* PCIe DID = 3 */
+               uint64_t did:5; /* PCIe DID = 3 */

                uint64_t subdid:3;      /* PCIe SubDID = 3-6 */
                uint64_t reserved_36_39:4;      /* Must be zero */
                uint64_t address:36;    /* PCIe Mem address */
                uint64_t subdid:3;      /* PCIe SubDID = 3-6 */
                uint64_t reserved_36_39:4;      /* Must be zero */
                uint64_t address:36;    /* PCIe Mem address */


@@ -166,7 +166,7 @@ static inline uint64_t cvmx_pcie_get_mem_size(int pcie_port)
  * Read a PCIe config space register indirectly. This is used for
  * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
  *
  * Read a PCIe config space register indirectly. This is used for
  * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
  *

- * @pcie_port:  PCIe port to read from
+ * @pcie_port: PCIe port to read from

  * @cfg_offset: Address to read
  *
  * Returns Value read
  * @cfg_offset: Address to read
  *
  * Returns Value read


@@ -194,9 +194,9 @@ static uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
  * Write a PCIe config space register indirectly. This is used for
  * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
  *
  * Write a PCIe config space register indirectly. This is used for
  * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
  *

- * @pcie_port:  PCIe port to write to
+ * @pcie_port: PCIe port to write to

  * @cfg_offset: Address to write
  * @cfg_offset: Address to write

- * @val:        Value to write
+ * @val:       Value to write

  */
 static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
                                 uint32_t val)
  */
 static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
                                 uint32_t val)


@@ -222,7 +222,7 @@ static void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset,
  * @pcie_port: PCIe port to access
  * @bus:       Sub bus
  * @dev:       Device ID
  * @pcie_port: PCIe port to access
  * @bus:       Sub bus
  * @dev:       Device ID

- * @fn:        Device sub function
+ * @fn:               Device sub function

  * @reg:       Register to access
  *
  * Returns 64bit Octeon IO address
  * @reg:       Register to access
  *
  * Returns 64bit Octeon IO address


@@ -259,7 +259,7 @@ static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus,
  * @pcie_port: PCIe port the device is on
  * @bus:       Sub bus
  * @dev:       Device ID
  * @pcie_port: PCIe port the device is on
  * @bus:       Sub bus
  * @dev:       Device ID

- * @fn:        Device sub function
+ * @fn:               Device sub function

  * @reg:       Register to access
  *
  * Returns Result of the read
  * @reg:       Register to access
  *
  * Returns Result of the read


@@ -281,7 +281,7 @@ static uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev,
  * @pcie_port: PCIe port the device is on
  * @bus:       Sub bus
  * @dev:       Device ID
  * @pcie_port: PCIe port the device is on
  * @bus:       Sub bus
  * @dev:       Device ID

- * @fn:        Device sub function
+ * @fn:               Device sub function

  * @reg:       Register to access
  *
  * Returns Result of the read
  * @reg:       Register to access
  *
  * Returns Result of the read


@@ -303,7 +303,7 @@ static uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev,
  * @pcie_port: PCIe port the device is on
  * @bus:       Sub bus
  * @dev:       Device ID
  * @pcie_port: PCIe port the device is on
  * @bus:       Sub bus
  * @dev:       Device ID

- * @fn:        Device sub function
+ * @fn:               Device sub function

  * @reg:       Register to access
  *
  * Returns Result of the read
  * @reg:       Register to access
  *
  * Returns Result of the read


@@ -325,7 +325,7 @@ static uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev,
  * @pcie_port: PCIe port the device is on
  * @bus:       Sub bus
  * @dev:       Device ID
  * @pcie_port: PCIe port the device is on
  * @bus:       Sub bus
  * @dev:       Device ID

- * @fn:        Device sub function
+ * @fn:               Device sub function

  * @reg:       Register to access
  * @val:       Value to write
  */
  * @reg:       Register to access
  * @val:       Value to write
  */


@@ -344,7 +344,7 @@ static void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn,
  * @pcie_port: PCIe port the device is on
  * @bus:       Sub bus
  * @dev:       Device ID
  * @pcie_port: PCIe port the device is on
  * @bus:       Sub bus
  * @dev:       Device ID

- * @fn:        Device sub function
+ * @fn:               Device sub function

  * @reg:       Register to access
  * @val:       Value to write
  */
  * @reg:       Register to access
  * @val:       Value to write
  */


@@ -363,7 +363,7 @@ static void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn,
  * @pcie_port: PCIe port the device is on
  * @bus:       Sub bus
  * @dev:       Device ID
  * @pcie_port: PCIe port the device is on
  * @bus:       Sub bus
  * @dev:       Device ID

- * @fn:        Device sub function
+ * @fn:               Device sub function

  * @reg:       Register to access
  * @val:       Value to write
  */
  * @reg:       Register to access
  * @val:       Value to write
  */


@@ -883,14 +883,14 @@ retry:
 
        /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
        npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
 
        /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
        npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);

-       npei_mem_access_ctl.s.max_word = 0;     /* Allow 16 words to combine */
-       npei_mem_access_ctl.s.timer = 127;      /* Wait up to 127 cycles for more data */
+       npei_mem_access_ctl.s.max_word = 0;     /* Allow 16 words to combine */
+       npei_mem_access_ctl.s.timer = 127;      /* Wait up to 127 cycles for more data */

        cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
 
        /* Setup Mem access SubDIDs */
        mem_access_subid.u64 = 0;
        mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
        cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
 
        /* Setup Mem access SubDIDs */
        mem_access_subid.u64 = 0;
        mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */

-       mem_access_subid.s.nmerge = 1;  /* Due to an errata on pass 1 chips, no merging is allowed. */
+       mem_access_subid.s.nmerge = 1;  /* Due to an errata on pass 1 chips, no merging is allowed. */

        mem_access_subid.s.esr = 1;     /* Endian-swap for Reads. */
        mem_access_subid.s.esw = 1;     /* Endian-swap for Writes. */
        mem_access_subid.s.nsr = 0;     /* Enable Snooping for Reads. Octeon doesn't care, but devices might want this more conservative setting */
        mem_access_subid.s.esr = 1;     /* Endian-swap for Reads. */
        mem_access_subid.s.esw = 1;     /* Endian-swap for Writes. */
        mem_access_subid.s.nsr = 0;     /* Enable Snooping for Reads. Octeon doesn't care, but devices might want this more conservative setting */


@@ -926,7 +926,7 @@ retry:
 
        bar1_index.u32 = 0;
        bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
 
        bar1_index.u32 = 0;
        bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);

-       bar1_index.s.ca = 1;       /* Not Cached */
+       bar1_index.s.ca = 1;       /* Not Cached */

        bar1_index.s.end_swp = 1;  /* Endian Swap mode */
        bar1_index.s.addr_v = 1;   /* Valid entry */
 
        bar1_index.s.end_swp = 1;  /* Endian Swap mode */
        bar1_index.s.addr_v = 1;   /* Valid entry */
 


@@ -1342,11 +1342,11 @@ static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
        /* Setup Mem access SubDIDs */
        mem_access_subid.u64 = 0;
        mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */
        /* Setup Mem access SubDIDs */
        mem_access_subid.u64 = 0;
        mem_access_subid.s.port = pcie_port; /* Port the request is sent to. */

-       mem_access_subid.s.nmerge = 0;  /* Allow merging as it works on CN6XXX. */
-       mem_access_subid.s.esr = 1;     /* Endian-swap for Reads. */
-       mem_access_subid.s.esw = 1;     /* Endian-swap for Writes. */
-       mem_access_subid.s.wtype = 0;   /* "No snoop" and "Relaxed ordering" are not set */
-       mem_access_subid.s.rtype = 0;   /* "No snoop" and "Relaxed ordering" are not set */
+       mem_access_subid.s.nmerge = 0;  /* Allow merging as it works on CN6XXX. */
+       mem_access_subid.s.esr = 1;     /* Endian-swap for Reads. */
+       mem_access_subid.s.esw = 1;     /* Endian-swap for Writes. */
+       mem_access_subid.s.wtype = 0;   /* "No snoop" and "Relaxed ordering" are not set */
+       mem_access_subid.s.rtype = 0;   /* "No snoop" and "Relaxed ordering" are not set */

        /* PCIe Adddress Bits <63:34>. */
        if (OCTEON_IS_MODEL(OCTEON_CN68XX))
                mem_access_subid.cn68xx.ba = 0;
        /* PCIe Adddress Bits <63:34>. */
        if (OCTEON_IS_MODEL(OCTEON_CN68XX))
                mem_access_subid.cn68xx.ba = 0;


@@ -1409,7 +1409,7 @@ static int __cvmx_pcie_rc_initialize_gen2(int pcie_port)
 
        bar1_index.u64 = 0;
        bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);
 
        bar1_index.u64 = 0;
        bar1_index.s.addr_idx = (CVMX_PCIE_BAR1_PHYS_BASE >> 22);

-       bar1_index.s.ca = 1;       /* Not Cached */
+       bar1_index.s.ca = 1;       /* Not Cached */

        bar1_index.s.end_swp = 1;  /* Endian Swap mode */
        bar1_index.s.addr_v = 1;   /* Valid entry */
 
        bar1_index.s.end_swp = 1;  /* Endian Swap mode */
        bar1_index.s.addr_v = 1;   /* Valid entry */
 


@@ -1458,10 +1458,10 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
  *
  * @dev:    The Linux PCI device structure for the device to map
  * @slot:   The slot number for this device on __BUS 0__. Linux
  *
  * @dev:    The Linux PCI device structure for the device to map
  * @slot:   The slot number for this device on __BUS 0__. Linux

- *               enumerates through all the bridges and figures out the
- *               slot on Bus 0 where this device eventually hooks to.
+ *              enumerates through all the bridges and figures out the
+ *              slot on Bus 0 where this device eventually hooks to.

  * @pin:    The PCI interrupt pin read from the device, then swizzled
  * @pin:    The PCI interrupt pin read from the device, then swizzled

- *               as it goes through each bridge.
+ *              as it goes through each bridge.

  * Returns Interrupt number for the device
  */
 int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
  * Returns Interrupt number for the device
  */
 int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,


@@ -1503,7 +1503,7 @@ int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
        return pin - 1 + OCTEON_IRQ_PCI_INT0;
 }
 
        return pin - 1 + OCTEON_IRQ_PCI_INT0;
 }
 

-static  void set_cfg_read_retry(u32 retry_cnt)
+static void set_cfg_read_retry(u32 retry_cnt)

 {
        union cvmx_pemx_ctl_status pemx_ctl;
        pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));
 {
        union cvmx_pemx_ctl_status pemx_ctl;
        pemx_ctl.u64 = cvmx_read_csr(CVMX_PEMX_CTL_STATUS(1));


@@ -1931,7 +1931,7 @@ static int __init octeon_pcie_setup(void)
                        OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
                        sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0));
                        if (sriox_status_reg.s.srio) {
                        OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
                        sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(0));
                        if (sriox_status_reg.s.srio) {

-                               srio_war15205 += 1;      /* Port is SRIO */
+                               srio_war15205 += 1;      /* Port is SRIO */

                                port = 0;
                        }
                }
                                port = 0;
                        }
                }


@@ -2004,7 +2004,7 @@ static int __init octeon_pcie_setup(void)
                        OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
                        sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1));
                        if (sriox_status_reg.s.srio) {
                        OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_0)) {
                        sriox_status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(1));
                        if (sriox_status_reg.s.srio) {

-                               srio_war15205 += 1;      /* Port is SRIO */
+                               srio_war15205 += 1;      /* Port is SRIO */

                                port = 1;
                        }
                }
                                port = 1;
                        }
                }

diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq.c b/arch/mips/pmc-sierra/msp71xx/msp_irq.c
index d3c3d81757a538ea13ee3ab56942d1aeea00df3c..9da5619c00a527eed0e524b6d92b03d05ddb20df 100644 (file)
--- a/arch/mips/pmc-sierra/msp71xx/msp_irq.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq.c
@@ -41,9 +41,9 @@ static inline void sec_int_dispatch(void)  { do_IRQ(MSP_INT_SEC);  }
 
 /*
  * The PMC-Sierra MSP interrupts are arranged in a 3 level cascaded
 
 /*
  * The PMC-Sierra MSP interrupts are arranged in a 3 level cascaded

- * hierarchical system.  The first level are the direct MIPS interrupts
+ * hierarchical system.         The first level are the direct MIPS interrupts

  * and are assigned the interrupt range 0-7.  The second level is the SLM
  * and are assigned the interrupt range 0-7.  The second level is the SLM

- * interrupt controller and is assigned the range 8-39.  The third level
+ * interrupt controller and is assigned the range 8-39.         The third level

  * comprises the Peripherial block, the PCI block, the PCI MSI block and
  * the SLP.  The PCI interrupts and the SLP errors are handled by the
  * relevant subsystems so the core interrupt code needs only concern
  * comprises the Peripherial block, the PCI block, the PCI MSI block and
  * the SLP.  The PCI interrupts and the SLP errors are handled by the
  * relevant subsystems so the core interrupt code needs only concern

diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
index 2e6f7cab24c12fb1babd90b1e53517378e38e2a1..e49b499f66db48de480dcf780f7760a3a442313d 100644 (file)
--- a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
@@ -3,8 +3,8 @@
  *
  * This file define the irq handler for MSP CIC subsystem interrupts.
  *
  *
  * This file define the irq handler for MSP CIC subsystem interrupts.
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */


@@ -171,7 +171,7 @@ void __init msp_cic_irq_init(void)
        /* Mask/clear interrupts. */
        *CIC_VPE0_MSK_REG = 0x00000000;
        *CIC_VPE1_MSK_REG = 0x00000000;
        /* Mask/clear interrupts. */
        *CIC_VPE0_MSK_REG = 0x00000000;
        *CIC_VPE1_MSK_REG = 0x00000000;

-       *CIC_STS_REG      = 0xFFFFFFFF;
+       *CIC_STS_REG      = 0xFFFFFFFF;

        /*
        * The MSP7120 RG and EVBD boards use IRQ[6:4] for PCI.
        * These inputs map to EXT_INT_POL[6:4] inside the CIC.
        /*
        * The MSP7120 RG and EVBD boards use IRQ[6:4] for PCI.
        * These inputs map to EXT_INT_POL[6:4] inside the CIC.

diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c
index 598b6a66b97031a92262b6db52fed6086e00e361..d1fd530479d46f3b3a245fd844d15bb45a94c988 100644 (file)
--- a/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_per.c
@@ -3,8 +3,8 @@
  *
  * This file define the irq handler for MSP PER subsystem interrupts.
  *
  *
  * This file define the irq handler for MSP PER subsystem interrupts.
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
index 83a1c5eae3f8103c09e07fb1f3fbc2ebe000300c..5f66a76311c3e670d910f219707453316a1f42b7 100644 (file)
--- a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
@@ -4,8 +4,8 @@
  * Copyright 2005-2006 PMC-Sierra, Inc, derived from irq_cpu.c
  * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
  *
  * Copyright 2005-2006 PMC-Sierra, Inc, derived from irq_cpu.c
  * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/pmc-sierra/msp71xx/msp_pci.c b/arch/mips/pmc-sierra/msp71xx/msp_pci.c
index f764fe7748d6fb9376f251bf2ad4ba02c0bd742c..428dea23c35ceca8dbef824d4b02caa52abb9de7 100644 (file)
--- a/arch/mips/pmc-sierra/msp71xx/msp_pci.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_pci.c
@@ -36,7 +36,7 @@ static int __init msp_pci_setup(void)
 #if 0 /* Linux 2.6 initialization code to be completed */
        if (getdeviceid() & DEV_ID_SINGLE_PC) {
                /* If single card mode */
 #if 0 /* Linux 2.6 initialization code to be completed */
        if (getdeviceid() & DEV_ID_SINGLE_PC) {
                /* If single card mode */

-               slmRegs *sreg = (slmRegs *) SREG_BASE;
+               slmRegs *sreg = (slmRegs *) SREG_BASE;

 
                sreg->single_pc_enable = SINGLE_PCCARD;
        }
 
                sreg->single_pc_enable = SINGLE_PCCARD;
        }

diff --git a/arch/mips/pmc-sierra/msp71xx/msp_prom.c b/arch/mips/pmc-sierra/msp71xx/msp_prom.c
index db00deb59b9c678732983efe955bfe1d2c80a5cc..0edb89a6351610480833ee81d5e996b45ee3ea45 100644 (file)
--- a/arch/mips/pmc-sierra/msp71xx/msp_prom.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_prom.c
@@ -99,7 +99,7 @@ static inline int str2eaddr(unsigned char *ea, unsigned char *str)
                }
        }
 
                }
        }
 

-       if (index == 5) {
+       if (index == 5) {

                ea[index++] = num;
                return 0;
        } else
                ea[index++] = num;
                return 0;
        } else


@@ -285,7 +285,7 @@ EXPORT_SYMBOL(identify_revision);
 char *prom_getenv(char *env_name)
 {
        /*
 char *prom_getenv(char *env_name)
 {
        /*

-        * Return a pointer to the given environment variable.  prom_envp
+        * Return a pointer to the given environment variable.  prom_envp

         * points to a null terminated array of pointers to variables.
         * Environment variables are stored in the form of "memsize=64"
         */
         * points to a null terminated array of pointers to variables.
         * Environment variables are stored in the form of "memsize=64"
         */

diff --git a/arch/mips/pmc-sierra/msp71xx/msp_serial.c b/arch/mips/pmc-sierra/msp71xx/msp_serial.c
index a1c7c7da233696c2dd5851aa25ef0523bbe5933d..d304be22b963fb3a3aa40fab95129123b323eb73 100644 (file)
--- a/arch/mips/pmc-sierra/msp71xx/msp_serial.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_serial.c
@@ -90,8 +90,8 @@ static int msp_serial_handle_irq(struct uart_port *p)
 
 void __init msp_serial_setup(void)
 {
 
 void __init msp_serial_setup(void)
 {

-       char    *s;
-       char    *endp;
+       char    *s;
+       char    *endp;

        struct uart_port up;
        unsigned int uartclk;
 
        struct uart_port up;
        unsigned int uartclk;
 


@@ -104,19 +104,19 @@ void __init msp_serial_setup(void)
        ppfinit("UART clock set to %d\n", uartclk);
 
        /* Initialize first serial port */
        ppfinit("UART clock set to %d\n", uartclk);
 
        /* Initialize first serial port */

-       up.mapbase      = MSP_UART0_BASE;
-       up.membase      = ioremap_nocache(up.mapbase, MSP_UART_REG_LEN);
-       up.irq          = MSP_INT_UART0;
-       up.uartclk      = uartclk;
-       up.regshift     = 2;
-       up.iotype       = UPIO_MEM;
-       up.flags        = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
-       up.type         = PORT_16550A;
-       up.line         = 0;
+       up.mapbase      = MSP_UART0_BASE;
+       up.membase      = ioremap_nocache(up.mapbase, MSP_UART_REG_LEN);
+       up.irq          = MSP_INT_UART0;
+       up.uartclk      = uartclk;
+       up.regshift     = 2;
+       up.iotype       = UPIO_MEM;
+       up.flags        = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
+       up.type         = PORT_16550A;
+       up.line         = 0;

        up.serial_out   = msp_serial_out;
        up.serial_in    = msp_serial_in;
        up.handle_irq   = msp_serial_handle_irq;
        up.serial_out   = msp_serial_out;
        up.serial_in    = msp_serial_in;
        up.handle_irq   = msp_serial_handle_irq;

-       up.private_data = kzalloc(sizeof(struct msp_uart_data), GFP_KERNEL);
+       up.private_data = kzalloc(sizeof(struct msp_uart_data), GFP_KERNEL);

        if (!up.private_data) {
                pr_err("failed to allocate uart private data\n");
                return;
        if (!up.private_data) {
                pr_err("failed to allocate uart private data\n");
                return;


@@ -142,10 +142,10 @@ void __init msp_serial_setup(void)
                        return; /* No second serial port, good-bye. */
        }
 
                        return; /* No second serial port, good-bye. */
        }
 

-       up.mapbase      = MSP_UART1_BASE;
-       up.membase      = ioremap_nocache(up.mapbase, MSP_UART_REG_LEN);
-       up.irq          = MSP_INT_UART1;
-       up.line         = 1;
+       up.mapbase      = MSP_UART1_BASE;
+       up.membase      = ioremap_nocache(up.mapbase, MSP_UART_REG_LEN);
+       up.irq          = MSP_INT_UART1;
+       up.line         = 1;

        up.private_data         = (void*)UART1_STATUS_REG;
        if (early_serial_setup(&up)) {
                kfree(up.private_data);
        up.private_data         = (void*)UART1_STATUS_REG;
        if (early_serial_setup(&up)) {
                kfree(up.private_data);

diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c
index 7a834b2f8a5f0b9dcaaad87672eff98d42d906b3..1651cfdbfe7b1303c03b629171190e8df013ad16 100644 (file)
--- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c
@@ -4,8 +4,8 @@
  * Copyright 2005-2007 PMC-Sierra, Inc,
  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
  *
  * Copyright 2005-2007 PMC-Sierra, Inc,
  * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */


@@ -168,7 +168,7 @@ void __init prom_init(void)
        family = identify_family();
        revision = identify_revision();
 
        family = identify_family();
        revision = identify_revision();
 

-       switch (family) {
+       switch (family) {

        case FAMILY_FPGA:
                if (FPGA_IS_MSP4200(revision)) {
                        /* Old-style revision ID */
        case FAMILY_FPGA:
                if (FPGA_IS_MSP4200(revision)) {
                        /* Old-style revision ID */


@@ -219,7 +219,7 @@ void __init prom_init(void)
 
        /*
         * Sub-system setup follows.
 
        /*
         * Sub-system setup follows.

-        * Setup functions can  either be called here or using the
+        * Setup functions can  either be called here or using the

         * subsys_initcall mechanism (i.e. see msp_pci_setup). The
         * order in which they are called can be changed by using the
         * link order in arch/mips/pmc-sierra/msp71xx/Makefile.
         * subsys_initcall mechanism (i.e. see msp_pci_setup). The
         * order in which they are called can be changed by using the
         * link order in arch/mips/pmc-sierra/msp71xx/Makefile.

diff --git a/arch/mips/pmc-sierra/msp71xx/msp_time.c b/arch/mips/pmc-sierra/msp71xx/msp_time.c
index 8b42f307a7a7c10f0ea886cf1a28744cf895329a..8f12ecc55ace5daf90eed56a53c9c489b2ca427f 100644 (file)
--- a/arch/mips/pmc-sierra/msp71xx/msp_time.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_time.c
@@ -45,7 +45,7 @@ static int tim_installed;
 
 void __init plat_time_init(void)
 {
 
 void __init plat_time_init(void)
 {

-       char    *endp, *s;
+       char    *endp, *s;

        unsigned long cpu_rate = 0;
 
        if (cpu_rate == 0) {
        unsigned long cpu_rate = 0;
 
        if (cpu_rate == 0) {

diff --git a/arch/mips/pmc-sierra/msp71xx/msp_usb.c b/arch/mips/pmc-sierra/msp71xx/msp_usb.c
index 9a1aef89bd4c827d3dc88e9a6b2c23561747e6ad..4dab915696e7749e8743b0bf2b5b21c47e09a102 100644 (file)
--- a/arch/mips/pmc-sierra/msp71xx/msp_usb.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_usb.c
@@ -40,14 +40,14 @@
 #if defined(CONFIG_USB_EHCI_HCD)
 static struct resource msp_usbhost0_resources[] = {
        [0] = { /* EHCI-HS operational and capabilities registers */
 #if defined(CONFIG_USB_EHCI_HCD)
 static struct resource msp_usbhost0_resources[] = {
        [0] = { /* EHCI-HS operational and capabilities registers */

-               .start  = MSP_USB0_HS_START,
-               .end    = MSP_USB0_HS_END,
-               .flags  = IORESOURCE_MEM,
+               .start  = MSP_USB0_HS_START,
+               .end    = MSP_USB0_HS_END,
+               .flags  = IORESOURCE_MEM,

        },
        [1] = {
        },
        [1] = {

-               .start  = MSP_INT_USB,
-               .end    = MSP_INT_USB,
-               .flags  = IORESOURCE_IRQ,
+               .start  = MSP_INT_USB,
+               .end    = MSP_INT_USB,
+               .flags  = IORESOURCE_IRQ,

        },
        [2] = { /* MSBus-to-AMBA bridge register space */
                .start  = MSP_USB0_MAB_START,
        },
        [2] = { /* MSBus-to-AMBA bridge register space */
                .start  = MSP_USB0_MAB_START,


@@ -71,8 +71,8 @@ static struct mspusb_device msp_usbhost0_device = {
                        .dma_mask = &msp_usbhost0_dma_mask,
                        .coherent_dma_mask = 0xffffffffUL,
                },
                        .dma_mask = &msp_usbhost0_dma_mask,
                        .coherent_dma_mask = 0xffffffffUL,
                },

-               .num_resources  = ARRAY_SIZE(msp_usbhost0_resources),
-               .resource       = msp_usbhost0_resources,
+               .num_resources  = ARRAY_SIZE(msp_usbhost0_resources),
+               .resource       = msp_usbhost0_resources,

        },
 };
 
        },
 };
 


@@ -121,14 +121,14 @@ static struct mspusb_device msp_usbhost1_device = {
 #if defined(CONFIG_USB_GADGET)
 static struct resource msp_usbdev0_resources[] = {
        [0] = { /* EHCI-HS operational and capabilities registers */
 #if defined(CONFIG_USB_GADGET)
 static struct resource msp_usbdev0_resources[] = {
        [0] = { /* EHCI-HS operational and capabilities registers */

-               .start  = MSP_USB0_HS_START,
-               .end    = MSP_USB0_HS_END,
-               .flags  = IORESOURCE_MEM,
+               .start  = MSP_USB0_HS_START,
+               .end    = MSP_USB0_HS_END,
+               .flags  = IORESOURCE_MEM,

        },
        [1] = {
        },
        [1] = {

-               .start  = MSP_INT_USB,
-               .end    = MSP_INT_USB,
-               .flags  = IORESOURCE_IRQ,
+               .start  = MSP_INT_USB,
+               .end    = MSP_INT_USB,
+               .flags  = IORESOURCE_IRQ,

        },
        [2] = { /* MSBus-to-AMBA bridge register space */
                .start  = MSP_USB0_MAB_START,
        },
        [2] = { /* MSBus-to-AMBA bridge register space */
                .start  = MSP_USB0_MAB_START,


@@ -153,22 +153,22 @@ static struct mspusb_device msp_usbdev0_device = {
                        .dma_mask = &msp_usbdev_dma_mask,
                        .coherent_dma_mask = 0xffffffffUL,
                },
                        .dma_mask = &msp_usbdev_dma_mask,
                        .coherent_dma_mask = 0xffffffffUL,
                },

-               .num_resources  = ARRAY_SIZE(msp_usbdev0_resources),
-               .resource       = msp_usbdev0_resources,
+               .num_resources  = ARRAY_SIZE(msp_usbdev0_resources),
+               .resource       = msp_usbdev0_resources,

        },
 };
 
 #ifdef CONFIG_MSP_HAS_DUAL_USB
 static struct resource msp_usbdev1_resources[] = {
        [0] = { /* EHCI-HS operational and capabilities registers */
        },
 };
 
 #ifdef CONFIG_MSP_HAS_DUAL_USB
 static struct resource msp_usbdev1_resources[] = {
        [0] = { /* EHCI-HS operational and capabilities registers */

-               .start  = MSP_USB1_HS_START,
-               .end    = MSP_USB1_HS_END,
-               .flags  = IORESOURCE_MEM,
+               .start  = MSP_USB1_HS_START,
+               .end    = MSP_USB1_HS_END,
+               .flags  = IORESOURCE_MEM,

        },
        [1] = {
        },
        [1] = {

-               .start  = MSP_INT_USB,
-               .end    = MSP_INT_USB,
-               .flags  = IORESOURCE_IRQ,
+               .start  = MSP_INT_USB,
+               .end    = MSP_INT_USB,
+               .flags  = IORESOURCE_IRQ,

        },
        [2] = { /* MSBus-to-AMBA bridge register space */
                .start  = MSP_USB1_MAB_START,
        },
        [2] = { /* MSBus-to-AMBA bridge register space */
                .start  = MSP_USB1_MAB_START,


@@ -191,8 +191,8 @@ static struct mspusb_device msp_usbdev1_device = {
                        .dma_mask = &msp_usbdev_dma_mask,
                        .coherent_dma_mask = 0xffffffffUL,
                },
                        .dma_mask = &msp_usbdev_dma_mask,
                        .coherent_dma_mask = 0xffffffffUL,
                },

-               .num_resources  = ARRAY_SIZE(msp_usbdev1_resources),
-               .resource       = msp_usbdev1_resources,
+               .num_resources  = ARRAY_SIZE(msp_usbdev1_resources),
+               .resource       = msp_usbdev1_resources,

        },
 };
 
        },
 };
 


@@ -211,7 +211,7 @@ static int __init msp_usb_setup(void)
        /*
         * Could this perhaps be integrated into the "features" env var?
         * Use the features key "U", and follow with "H" for host-mode,
        /*
         * Could this perhaps be integrated into the "features" env var?
         * Use the features key "U", and follow with "H" for host-mode,

-        * "D" for device-mode.  If it works for Ethernet, why not USB...
+        * "D" for device-mode.  If it works for Ethernet, why not USB...

         *  -- hammtrev, 2007/03/22
         */
        snprintf((char *)&envstr[0], sizeof(envstr), "usbmode");
         *  -- hammtrev, 2007/03/22
         */
        snprintf((char *)&envstr[0], sizeof(envstr), "usbmode");


@@ -237,7 +237,7 @@ static int __init msp_usb_setup(void)
 #endif
 #else
                ppfinit("%s: echi_hcd not supported\n", __FILE__);
 #endif
 #else
                ppfinit("%s: echi_hcd not supported\n", __FILE__);

-#endif  /* CONFIG_USB_EHCI_HCD */
+#endif /* CONFIG_USB_EHCI_HCD */

        } else {
 #if defined(CONFIG_USB_GADGET)
                /* get device mode structure */
        } else {
 #if defined(CONFIG_USB_GADGET)
                /* get device mode structure */


@@ -251,7 +251,7 @@ static int __init msp_usb_setup(void)
 #endif
 #else
                ppfinit("%s: usb_gadget not supported\n", __FILE__);
 #endif
 #else
                ppfinit("%s: usb_gadget not supported\n", __FILE__);

-#endif  /* CONFIG_USB_GADGET */
+#endif /* CONFIG_USB_GADGET */

        }
        /* add device */
        platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs));
        }
        /* add device */
        platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs));

diff --git a/arch/mips/pnx833x/Platform b/arch/mips/pnx833x/Platform
index 7e6ec4dbc8ddb16b769f90b02601e4625a1ad162..794526caab125e0592796e81164f2fc82c3a5d2d 100644 (file)
--- a/arch/mips/pnx833x/Platform
+++ b/arch/mips/pnx833x/Platform
@@ -1,5 +1,5 @@
 # NXP STB225
 platform-$(CONFIG_SOC_PNX833X) += pnx833x/
 # NXP STB225
 platform-$(CONFIG_SOC_PNX833X) += pnx833x/

-cflags-$(CONFIG_SOC_PNX833X)    += -Iarch/mips/include/asm/mach-pnx833x
+cflags-$(CONFIG_SOC_PNX833X)   += -Iarch/mips/include/asm/mach-pnx833x

 load-$(CONFIG_NXP_STB220)      += 0xffffffff80001000
 load-$(CONFIG_NXP_STB225)      += 0xffffffff80001000
 load-$(CONFIG_NXP_STB220)      += 0xffffffff80001000
 load-$(CONFIG_NXP_STB225)      += 0xffffffff80001000

diff --git a/arch/mips/pnx833x/common/interrupts.c b/arch/mips/pnx833x/common/interrupts.c
index a86d5d5fceb0c81f6a129d8cc9ce58fa1c448036..a4a90596c0ad4a2d30113972abcee14b7bea85ab 100644 (file)
--- a/arch/mips/pnx833x/common/interrupts.c
+++ b/arch/mips/pnx833x/common/interrupts.c
@@ -35,64 +35,64 @@ static int mips_cpu_timer_irq;
 static const unsigned int irq_prio[PNX833X_PIC_NUM_IRQ] =
 {
     0, /* unused */
 static const unsigned int irq_prio[PNX833X_PIC_NUM_IRQ] =
 {
     0, /* unused */

-    4, /* PNX833X_PIC_I2C0_INT                 1 */
-    4, /* PNX833X_PIC_I2C1_INT                 2 */
-    1, /* PNX833X_PIC_UART0_INT                3 */
-    1, /* PNX833X_PIC_UART1_INT                4 */
-    6, /* PNX833X_PIC_TS_IN0_DV_INT            5 */
-    6, /* PNX833X_PIC_TS_IN0_DMA_INT           6 */
-    7, /* PNX833X_PIC_GPIO_INT                 7 */
-    4, /* PNX833X_PIC_AUDIO_DEC_INT            8 */
-    5, /* PNX833X_PIC_VIDEO_DEC_INT            9 */
-    4, /* PNX833X_PIC_CONFIG_INT              10 */
-    4, /* PNX833X_PIC_AOI_INT                 11 */
-    9, /* PNX833X_PIC_SYNC_INT                12 */
-    9, /* PNX8335_PIC_SATA_INT                13 */
-    4, /* PNX833X_PIC_OSD_INT                 14 */
-    9, /* PNX833X_PIC_DISP1_INT               15 */
-    4, /* PNX833X_PIC_DEINTERLACER_INT        16 */
-    9, /* PNX833X_PIC_DISPLAY2_INT            17 */
-    4, /* PNX833X_PIC_VC_INT                  18 */
-    4, /* PNX833X_PIC_SC_INT                  19 */
-    9, /* PNX833X_PIC_IDE_INT                 20 */
-    9, /* PNX833X_PIC_IDE_DMA_INT             21 */
-    6, /* PNX833X_PIC_TS_IN1_DV_INT           22 */
-    6, /* PNX833X_PIC_TS_IN1_DMA_INT          23 */
-    4, /* PNX833X_PIC_SGDX_DMA_INT            24 */
-    4, /* PNX833X_PIC_TS_OUT_INT              25 */
-    4, /* PNX833X_PIC_IR_INT                  26 */
-    3, /* PNX833X_PIC_VMSP1_INT               27 */
-    3, /* PNX833X_PIC_VMSP2_INT               28 */
-    4, /* PNX833X_PIC_PIBC_INT                29 */
-    4, /* PNX833X_PIC_TS_IN0_TRD_INT          30 */
-    4, /* PNX833X_PIC_SGDX_TPD_INT            31 */
-    5, /* PNX833X_PIC_USB_INT                 32 */
-    4, /* PNX833X_PIC_TS_IN1_TRD_INT          33 */
-    4, /* PNX833X_PIC_CLOCK_INT               34 */
-    4, /* PNX833X_PIC_SGDX_PARSER_INT         35 */
-    4, /* PNX833X_PIC_VMSP_DMA_INT            36 */
+    4, /* PNX833X_PIC_I2C0_INT                1 */
+    4, /* PNX833X_PIC_I2C1_INT                2 */
+    1, /* PNX833X_PIC_UART0_INT                       3 */
+    1, /* PNX833X_PIC_UART1_INT                       4 */
+    6, /* PNX833X_PIC_TS_IN0_DV_INT           5 */
+    6, /* PNX833X_PIC_TS_IN0_DMA_INT          6 */
+    7, /* PNX833X_PIC_GPIO_INT                7 */
+    4, /* PNX833X_PIC_AUDIO_DEC_INT           8 */
+    5, /* PNX833X_PIC_VIDEO_DEC_INT           9 */
+    4, /* PNX833X_PIC_CONFIG_INT             10 */
+    4, /* PNX833X_PIC_AOI_INT                11 */
+    9, /* PNX833X_PIC_SYNC_INT               12 */
+    9, /* PNX8335_PIC_SATA_INT               13 */
+    4, /* PNX833X_PIC_OSD_INT                14 */
+    9, /* PNX833X_PIC_DISP1_INT                      15 */
+    4, /* PNX833X_PIC_DEINTERLACER_INT       16 */
+    9, /* PNX833X_PIC_DISPLAY2_INT           17 */
+    4, /* PNX833X_PIC_VC_INT                 18 */
+    4, /* PNX833X_PIC_SC_INT                 19 */
+    9, /* PNX833X_PIC_IDE_INT                20 */
+    9, /* PNX833X_PIC_IDE_DMA_INT            21 */
+    6, /* PNX833X_PIC_TS_IN1_DV_INT          22 */
+    6, /* PNX833X_PIC_TS_IN1_DMA_INT         23 */
+    4, /* PNX833X_PIC_SGDX_DMA_INT           24 */
+    4, /* PNX833X_PIC_TS_OUT_INT             25 */
+    4, /* PNX833X_PIC_IR_INT                 26 */
+    3, /* PNX833X_PIC_VMSP1_INT                      27 */
+    3, /* PNX833X_PIC_VMSP2_INT                      28 */
+    4, /* PNX833X_PIC_PIBC_INT               29 */
+    4, /* PNX833X_PIC_TS_IN0_TRD_INT         30 */
+    4, /* PNX833X_PIC_SGDX_TPD_INT           31 */
+    5, /* PNX833X_PIC_USB_INT                32 */
+    4, /* PNX833X_PIC_TS_IN1_TRD_INT         33 */
+    4, /* PNX833X_PIC_CLOCK_INT                      34 */
+    4, /* PNX833X_PIC_SGDX_PARSER_INT        35 */
+    4, /* PNX833X_PIC_VMSP_DMA_INT           36 */

 #if defined(CONFIG_SOC_PNX8335)
 #if defined(CONFIG_SOC_PNX8335)

-    4, /* PNX8335_PIC_MIU_INT                 37 */
-    4, /* PNX8335_PIC_AVCHIP_IRQ_INT          38 */
-    9, /* PNX8335_PIC_SYNC_HD_INT             39 */
-    9, /* PNX8335_PIC_DISP_HD_INT             40 */
-    9, /* PNX8335_PIC_DISP_SCALER_INT         41 */
-    4, /* PNX8335_PIC_OSD_HD1_INT             42 */
-    4, /* PNX8335_PIC_DTL_WRITER_Y_INT        43 */
-    4, /* PNX8335_PIC_DTL_WRITER_C_INT        44 */
+    4, /* PNX8335_PIC_MIU_INT                37 */
+    4, /* PNX8335_PIC_AVCHIP_IRQ_INT         38 */
+    9, /* PNX8335_PIC_SYNC_HD_INT            39 */
+    9, /* PNX8335_PIC_DISP_HD_INT            40 */
+    9, /* PNX8335_PIC_DISP_SCALER_INT        41 */
+    4, /* PNX8335_PIC_OSD_HD1_INT            42 */
+    4, /* PNX8335_PIC_DTL_WRITER_Y_INT       43 */
+    4, /* PNX8335_PIC_DTL_WRITER_C_INT       44 */

     4, /* PNX8335_PIC_DTL_EMULATOR_Y_IR_INT   45 */
     4, /* PNX8335_PIC_DTL_EMULATOR_C_IR_INT   46 */
     4, /* PNX8335_PIC_DTL_EMULATOR_Y_IR_INT   45 */
     4, /* PNX8335_PIC_DTL_EMULATOR_C_IR_INT   46 */

-    4, /* PNX8335_PIC_DENC_TTX_INT            47 */
-    4, /* PNX8335_PIC_MMI_SIF0_INT            48 */
-    4, /* PNX8335_PIC_MMI_SIF1_INT            49 */
-    4, /* PNX8335_PIC_MMI_CDMMU_INT           50 */
-    4, /* PNX8335_PIC_PIBCS_INT               51 */
-   12, /* PNX8335_PIC_ETHERNET_INT            52 */
-    3, /* PNX8335_PIC_VMSP1_0_INT             53 */
-    3, /* PNX8335_PIC_VMSP1_1_INT             54 */
-    4, /* PNX8335_PIC_VMSP1_DMA_INT           55 */
-    4, /* PNX8335_PIC_TDGR_DE_INT             56 */
-    4, /* PNX8335_PIC_IR1_IRQ_INT             57 */
+    4, /* PNX8335_PIC_DENC_TTX_INT           47 */
+    4, /* PNX8335_PIC_MMI_SIF0_INT           48 */
+    4, /* PNX8335_PIC_MMI_SIF1_INT           49 */
+    4, /* PNX8335_PIC_MMI_CDMMU_INT          50 */
+    4, /* PNX8335_PIC_PIBCS_INT                      51 */
+   12, /* PNX8335_PIC_ETHERNET_INT           52 */
+    3, /* PNX8335_PIC_VMSP1_0_INT            53 */
+    3, /* PNX8335_PIC_VMSP1_1_INT            54 */
+    4, /* PNX8335_PIC_VMSP1_DMA_INT          55 */
+    4, /* PNX8335_PIC_TDGR_DE_INT            56 */
+    4, /* PNX8335_PIC_IR1_IRQ_INT            57 */

 #endif
 };
 
 #endif
 };
 

diff --git a/arch/mips/pnx833x/common/platform.c b/arch/mips/pnx833x/common/platform.c
index 05a1d922cd60871ef226cc792a448c0d2f295793..d22dc0d6f28922e0f6beefbc2cabad28da0d70e1 100644 (file)
--- a/arch/mips/pnx833x/common/platform.c
+++ b/arch/mips/pnx833x/common/platform.c
@@ -6,7 +6,7 @@
  *    Daniel Laird <daniel.j.laird@nxp.com>
  *
  *  Based on software written by:
  *    Daniel Laird <daniel.j.laird@nxp.com>
  *
  *  Based on software written by:

- *      Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
+ *     Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.

  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by


@@ -42,7 +42,7 @@
 #include <irq-mapping.h>
 #include <pnx833x.h>
 
 #include <irq-mapping.h>
 #include <pnx833x.h>
 

-static u64 uart_dmamask     = DMA_BIT_MASK(32);
+static u64 uart_dmamask            = DMA_BIT_MASK(32);

 
 static struct resource pnx833x_uart_resources[] = {
        [0] = {
 
 static struct resource pnx833x_uart_resources[] = {
        [0] = {


@@ -69,7 +69,7 @@ static struct resource pnx833x_uart_resources[] = {
 
 struct pnx8xxx_port pnx8xxx_ports[] = {
        [0] = {
 
 struct pnx8xxx_port pnx8xxx_ports[] = {
        [0] = {

-               .port   = {
+               .port   = {

                        .type           = PORT_PNX8XXX,
                        .iotype         = UPIO_MEM,
                        .membase        = (void __iomem *)PNX833X_UART0_PORTS_START,
                        .type           = PORT_PNX8XXX,
                        .iotype         = UPIO_MEM,
                        .membase        = (void __iomem *)PNX833X_UART0_PORTS_START,


@@ -82,7 +82,7 @@ struct pnx8xxx_port pnx8xxx_ports[] = {
                },
        },
        [1] = {
                },
        },
        [1] = {

-               .port   = {
+               .port   = {

                        .type           = PORT_PNX8XXX,
                        .iotype         = UPIO_MEM,
                        .membase        = (void __iomem *)PNX833X_UART1_PORTS_START,
                        .type           = PORT_PNX8XXX,
                        .iotype         = UPIO_MEM,
                        .membase        = (void __iomem *)PNX833X_UART1_PORTS_START,


@@ -108,7 +108,7 @@ static struct platform_device pnx833x_uart_device = {
        .resource       = pnx833x_uart_resources,
 };
 
        .resource       = pnx833x_uart_resources,
 };
 

-static u64 ehci_dmamask     = DMA_BIT_MASK(32);
+static u64 ehci_dmamask            = DMA_BIT_MASK(32);

 
 static struct resource pnx833x_usb_ehci_resources[] = {
        [0] = {
 
 static struct resource pnx833x_usb_ehci_resources[] = {
        [0] = {


@@ -183,7 +183,7 @@ static struct platform_device pnx833x_i2c0_device = {
        .dev = {
                .platform_data = &pnx833x_i2c_dev[0],
        },
        .dev = {
                .platform_data = &pnx833x_i2c_dev[0],
        },

-       .num_resources  = ARRAY_SIZE(pnx833x_i2c0_resources),
+       .num_resources  = ARRAY_SIZE(pnx833x_i2c0_resources),

        .resource       = pnx833x_i2c0_resources,
 };
 
        .resource       = pnx833x_i2c0_resources,
 };
 


@@ -193,7 +193,7 @@ static struct platform_device pnx833x_i2c1_device = {
        .dev = {
                .platform_data = &pnx833x_i2c_dev[1],
        },
        .dev = {
                .platform_data = &pnx833x_i2c_dev[1],
        },

-       .num_resources  = ARRAY_SIZE(pnx833x_i2c1_resources),
+       .num_resources  = ARRAY_SIZE(pnx833x_i2c1_resources),

        .resource       = pnx833x_i2c1_resources,
 };
 #endif
        .resource       = pnx833x_i2c1_resources,
 };
 #endif


@@ -217,7 +217,7 @@ static struct platform_device pnx833x_ethernet_device = {
        .name = "ip3902-eth",
        .id   = -1,
        .dev  = {
        .name = "ip3902-eth",
        .id   = -1,
        .dev  = {

-               .dma_mask          = &ethernet_dmamask,
+               .dma_mask          = &ethernet_dmamask,

                .coherent_dma_mask = DMA_BIT_MASK(32),
        },
        .num_resources = ARRAY_SIZE(pnx833x_ethernet_resources),
                .coherent_dma_mask = DMA_BIT_MASK(32),
        },
        .num_resources = ARRAY_SIZE(pnx833x_ethernet_resources),


@@ -238,8 +238,8 @@ static struct resource pnx833x_sata_resources[] = {
 };
 
 static struct platform_device pnx833x_sata_device = {
 };
 
 static struct platform_device pnx833x_sata_device = {

-       .name          = "pnx833x-sata",
-       .id            = -1,
+       .name          = "pnx833x-sata",
+       .id            = -1,

        .num_resources = ARRAY_SIZE(pnx833x_sata_resources),
        .resource      = pnx833x_sata_resources,
 };
        .num_resources = ARRAY_SIZE(pnx833x_sata_resources),
        .resource      = pnx833x_sata_resources,
 };


@@ -265,7 +265,7 @@ static struct platform_nand_data pnx833x_flash_nand_data = {
                .chip_delay             = 25,
        },
        .ctrl = {
                .chip_delay             = 25,
        },
        .ctrl = {

-               .cmd_ctrl               = pnx833x_flash_nand_cmd_ctrl
+               .cmd_ctrl               = pnx833x_flash_nand_cmd_ctrl

        }
 };
 
        }
 };
 


@@ -274,17 +274,17 @@ static struct platform_nand_data pnx833x_flash_nand_data = {
  * 12 bytes more seems to be the standard that allows for NAND access.
  */
 static struct resource pnx833x_flash_nand_resource = {
  * 12 bytes more seems to be the standard that allows for NAND access.
  */
 static struct resource pnx833x_flash_nand_resource = {

-       .start  = PNX8335_NAND_BASE,
-       .end    = PNX8335_NAND_BASE + 12,
-       .flags  = IORESOURCE_MEM,
+       .start  = PNX8335_NAND_BASE,
+       .end    = PNX8335_NAND_BASE + 12,
+       .flags  = IORESOURCE_MEM,

 };
 
 static struct platform_device pnx833x_flash_nand = {
 };
 
 static struct platform_device pnx833x_flash_nand = {

-       .name           = "gen_nand",
-       .id                     = -1,
+       .name           = "gen_nand",
+       .id                     = -1,

        .num_resources  = 1,
        .resource           = &pnx833x_flash_nand_resource,
        .num_resources  = 1,
        .resource           = &pnx833x_flash_nand_resource,

-       .dev            = {
+       .dev            = {

                .platform_data = &pnx833x_flash_nand_data,
        },
 };
                .platform_data = &pnx833x_flash_nand_data,
        },
 };

diff --git a/arch/mips/pnx833x/common/prom.c b/arch/mips/pnx833x/common/prom.c
index 29969f90a6b0f5ac715943ee356704c5eb9f5012..dfafdd732ca164b8508b3d3816ec10555582bfc0 100644 (file)
--- a/arch/mips/pnx833x/common/prom.c
+++ b/arch/mips/pnx833x/common/prom.c
@@ -6,7 +6,7 @@
  *    Daniel Laird <daniel.j.laird@nxp.com>
  *
  *  Based on software written by:
  *    Daniel Laird <daniel.j.laird@nxp.com>
  *
  *  Based on software written by:

- *      Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
+ *     Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.

  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by

diff --git a/arch/mips/pnx833x/common/reset.c b/arch/mips/pnx833x/common/reset.c
index e0ea96d29fde9fd6d64dca041dda2b8143823306..5cc9a9b3601c498389bb10f0432d86b1ddd8648d 100644 (file)
--- a/arch/mips/pnx833x/common/reset.c
+++ b/arch/mips/pnx833x/common/reset.c
@@ -6,7 +6,7 @@
  *    Daniel Laird <daniel.j.laird@nxp.com>
  *
  *  Based on software written by:
  *    Daniel Laird <daniel.j.laird@nxp.com>
  *
  *  Based on software written by:

- *      Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
+ *     Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.

  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by

diff --git a/arch/mips/pnx833x/common/setup.c b/arch/mips/pnx833x/common/setup.c
index e51fbc4b644d64392a48f79561ec45cd357d897e..99b4d94236cc50d56726a35949e11a24573ce561 100644 (file)
--- a/arch/mips/pnx833x/common/setup.c
+++ b/arch/mips/pnx833x/common/setup.c
@@ -6,7 +6,7 @@
  *    Daniel Laird <daniel.j.laird@nxp.com>
  *
  *  Based on software written by:
  *    Daniel Laird <daniel.j.laird@nxp.com>
  *
  *  Based on software written by:

- *      Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
+ *     Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.

  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by

diff --git a/arch/mips/pnx833x/stb22x/board.c b/arch/mips/pnx833x/stb22x/board.c
index 4b328ac430509b73095b24eb806a80003e7124ab..2ac5203438d8ee604b22e09018fd422b34c19355 100644 (file)
--- a/arch/mips/pnx833x/stb22x/board.c
+++ b/arch/mips/pnx833x/stb22x/board.c
@@ -6,7 +6,7 @@
  *    Daniel Laird <daniel.j.laird@nxp.com>
  *
  *  Based on software written by:
  *    Daniel Laird <daniel.j.laird@nxp.com>
  *
  *  Based on software written by:

- *      Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.
+ *     Nikita Youshchenko <yoush@debian.org>, based on PNX8550 code.

  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by

diff --git a/arch/mips/power/cpu.c b/arch/mips/power/cpu.c
index 26a6ef19d71fe6b40a7056445c650ef0ac3776e2..521e5963df05f4f67038f52dd3b321851fa0e551 100644 (file)
--- a/arch/mips/power/cpu.c
+++ b/arch/mips/power/cpu.c
@@ -5,7 +5,7 @@
  *
  * Copyright (C) 2009 Lemote Inc.
  * Author: Hu Hongbing <huhb@lemote.com>
  *
  * Copyright (C) 2009 Lemote Inc.
  * Author: Hu Hongbing <huhb@lemote.com>

- *         Wu Zhangjin <wuzhangjin@gmail.com>
+ *        Wu Zhangjin <wuzhangjin@gmail.com>

  */
 #include <asm/suspend.h>
 #include <asm/fpu.h>
  */
 #include <asm/suspend.h>
 #include <asm/fpu.h>

diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S
index 61e2558a2dcb9414a35a51ad2deecc29d7554cc7..7e0277a1048f0e7659a4e3f1e0f824be7e68cd3a 100644 (file)
--- a/arch/mips/power/hibernate.S
+++ b/arch/mips/power/hibernate.S
@@ -5,7 +5,7 @@
  *
  * Copyright (C) 2009 Lemote Inc.
  * Author: Hu Hongbing <huhb@lemote.com>
  *
  * Copyright (C) 2009 Lemote Inc.
  * Author: Hu Hongbing <huhb@lemote.com>

- *         Wu Zhangjin <wuzhangjin@gmail.com>
+ *        Wu Zhangjin <wuzhangjin@gmail.com>

  */
 #include <asm/asm-offsets.h>
 #include <asm/regdef.h>
  */
 #include <asm/asm-offsets.h>
 #include <asm/regdef.h>

diff --git a/arch/mips/powertv/asic/asic-calliope.c b/arch/mips/powertv/asic/asic-calliope.c
index 7773f3d956b0cdc914ab82cb7c2fd79664c558f8..2f539b43f56b09f2981eb82047fe3012bbb5a27c 100644 (file)
--- a/arch/mips/powertv/asic/asic-calliope.c
+++ b/arch/mips/powertv/asic/asic-calliope.c
@@ -17,10 +17,10 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *

- * Author:       Ken Eppinett
- *               David Schleef <ds@schleef.org>
+ * Author:      Ken Eppinett
+ *              David Schleef <ds@schleef.org>

  *
  *

- * Description:  Defines the platform resources for the SA settop.
+ * Description:         Defines the platform resources for the SA settop.

  */
 
 #include <linux/init.h>
  */
 
 #include <linux/init.h>


@@ -90,12 +90,12 @@ const struct register_map calliope_register_map __initconst = {
        .usb2_stbus_mess_size = {.phys = CALLIOPE_ADDR(0x9BFF04)},
        .usb2_stbus_chunk_size = {.phys = CALLIOPE_ADDR(0x9BFF08)},
 
        .usb2_stbus_mess_size = {.phys = CALLIOPE_ADDR(0x9BFF04)},
        .usb2_stbus_chunk_size = {.phys = CALLIOPE_ADDR(0x9BFF08)},
 

-       .pcie_regs = {.phys = 0x000000},        /* -doesn't exist- */
+       .pcie_regs = {.phys = 0x000000},        /* -doesn't exist- */

        .tim_ch = {.phys = CALLIOPE_ADDR(0xA02C10)},
        .tim_cl = {.phys = CALLIOPE_ADDR(0xA02C14)},
        .gpio_dout = {.phys = CALLIOPE_ADDR(0xA02c20)},
        .gpio_din = {.phys = CALLIOPE_ADDR(0xA02c24)},
        .gpio_dir = {.phys = CALLIOPE_ADDR(0xA02c2C)},
        .watchdog = {.phys = CALLIOPE_ADDR(0xA02c30)},
        .tim_ch = {.phys = CALLIOPE_ADDR(0xA02C10)},
        .tim_cl = {.phys = CALLIOPE_ADDR(0xA02C14)},
        .gpio_dout = {.phys = CALLIOPE_ADDR(0xA02c20)},
        .gpio_din = {.phys = CALLIOPE_ADDR(0xA02c24)},
        .gpio_dir = {.phys = CALLIOPE_ADDR(0xA02c2C)},
        .watchdog = {.phys = CALLIOPE_ADDR(0xA02c30)},

-       .front_panel = {.phys = 0x000000},      /* -not used- */
+       .front_panel = {.phys = 0x000000},      /* -not used- */

 };
 };

diff --git a/arch/mips/powertv/asic/asic-cronus.c b/arch/mips/powertv/asic/asic-cronus.c
index da076db7b7ed2fd572d6429231b370e381a10e69..7f8f3429b35a8dae0e28a332fb4d74a79e2a5db4 100644 (file)
--- a/arch/mips/powertv/asic/asic-cronus.c
+++ b/arch/mips/powertv/asic/asic-cronus.c
@@ -17,10 +17,10 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *

- * Author:       Ken Eppinett
- *               David Schleef <ds@schleef.org>
+ * Author:      Ken Eppinett
+ *              David Schleef <ds@schleef.org>

  *
  *

- * Description:  Defines the platform resources for the SA settop.
+ * Description:         Defines the platform resources for the SA settop.

  */
 
 #include <linux/init.h>
  */
 
 #include <linux/init.h>

diff --git a/arch/mips/powertv/asic/asic-gaia.c b/arch/mips/powertv/asic/asic-gaia.c
index 47683b370e748da98a21860ce04424e8f8459b36..1265b49012e65aaa486d9a1c63ffa13df99b40df 100644 (file)
--- a/arch/mips/powertv/asic/asic-gaia.c
+++ b/arch/mips/powertv/asic/asic-gaia.c
@@ -17,7 +17,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *

- * Author:       David VomLehn
+ * Author:      David VomLehn

  */
 
 #include <linux/init.h>
  */
 
 #include <linux/init.h>

diff --git a/arch/mips/powertv/asic/asic-zeus.c b/arch/mips/powertv/asic/asic-zeus.c
index 6ff4b10f09dab4e4c3ba35242db83654315df0ab..14e7de137e03ab92196cab71a824ddf03bb2fd10 100644 (file)
--- a/arch/mips/powertv/asic/asic-zeus.c
+++ b/arch/mips/powertv/asic/asic-zeus.c
@@ -17,10 +17,10 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *

- * Author:       Ken Eppinett
- *               David Schleef <ds@schleef.org>
+ * Author:      Ken Eppinett
+ *              David Schleef <ds@schleef.org>

  *
  *

- * Description:  Defines the platform resources for the SA settop.
+ * Description:         Defines the platform resources for the SA settop.

  */
 
 #include <linux/init.h>
  */
 
 #include <linux/init.h>

diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c
index bce1872249bab6b4fba83950354078919451f37e..d38b095fd0d045a1f103eff45f9ad3f9278bb903 100644 (file)
--- a/arch/mips/powertv/asic/asic_devices.c
+++ b/arch/mips/powertv/asic/asic_devices.c
@@ -1,6 +1,6 @@
 /*
  *
 /*
  *

- * Description:  Defines the platform resources for Gaia-based settops.
+ * Description:         Defines the platform resources for Gaia-based settops.

  *
  * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
  *
  *
  * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
  *


@@ -90,12 +90,12 @@ struct resource asic_resource = {
 
 /*
  * Allow override of bootloader-specified model
 
 /*
  * Allow override of bootloader-specified model

- * Returns zero on success, a negative errno value on failure.  This parameter
+ * Returns zero on success, a negative errno value on failure. This parameter

  * allows overriding of the bootloader-specified model.
  */
 static char __initdata cmdline[COMMAND_LINE_SIZE];
 
  * allows overriding of the bootloader-specified model.
  */
 static char __initdata cmdline[COMMAND_LINE_SIZE];
 

-#define        FORCEFAMILY_PARAM       "forcefamily"
+#define FORCEFAMILY_PARAM      "forcefamily"

 
 /*
  * check_forcefamily - check for, and parse, forcefamily command line parameter
 
 /*
  * check_forcefamily - check for, and parse, forcefamily command line parameter


@@ -486,7 +486,7 @@ static void __init pmem_setup_resource(void)
                resource->start = phys_to_dma(pmemaddr - 0x80000000);
                resource->end = resource->start + pmemlen - 1;
 
                resource->start = phys_to_dma(pmemaddr - 0x80000000);
                resource->end = resource->start + pmemlen - 1;
 

-               pr_info("persistent memory: start=0x%x  end=0x%x\n",
+               pr_info("persistent memory: start=0x%x  end=0x%x\n",

                        resource->start, resource->end);
        }
 }
                        resource->start, resource->end);
        }
 }

diff --git a/arch/mips/powertv/asic/asic_int.c b/arch/mips/powertv/asic/asic_int.c
index 99d82e10000bfd493df1d232d2a7c5337e8adb31..f44cd9295cae8bac57c8ad6470182af10f81ae09 100644 (file)
--- a/arch/mips/powertv/asic/asic_int.c
+++ b/arch/mips/powertv/asic/asic_int.c
@@ -2,7 +2,7 @@
  * Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
  * Copyright (C) 2001 Ralf Baechle
  * Carsten Langgaard, carstenl@mips.com
  * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
  * Copyright (C) 2001 Ralf Baechle

- * Portions copyright (C) 2009  Cisco Systems, Inc.
+ * Portions copyright (C) 2009 Cisco Systems, Inc.

  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as
  *
  *  This program is free software; you can distribute it and/or modify it
  *  under the terms of the GNU General Public License (Version 2) as


@@ -64,7 +64,7 @@ static void asic_irqdispatch(void)
 
        irq = get_int();
        if (irq < 0)
 
        irq = get_int();
        if (irq < 0)

-               return;  /* interrupt has already been cleared */
+               return;  /* interrupt has already been cleared */

 
        do_IRQ(irq);
 }
 
        do_IRQ(irq);
 }

diff --git a/arch/mips/powertv/asic/irq_asic.c b/arch/mips/powertv/asic/irq_asic.c
index fa9ae9584710087a89c98f8c984bb1b03d5b95ae..9344902dc58658cc4a7e4237e19585f59f7329ab 100644 (file)
--- a/arch/mips/powertv/asic/irq_asic.c
+++ b/arch/mips/powertv/asic/irq_asic.c
@@ -5,8 +5,8 @@
  * Modified from arch/mips/kernel/irq-rm7000.c:
  * Copyright (C) 2003 Ralf Baechle
  *
  * Modified from arch/mips/kernel/irq-rm7000.c:
  * Copyright (C) 2003 Ralf Baechle
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/powertv/asic/prealloc-calliope.c b/arch/mips/powertv/asic/prealloc-calliope.c
index 3fc5d46687a9ac93e7e81be5528dae205330ebfd..98dc51650577442c77f54de3817b4d05bd01d612 100644 (file)
--- a/arch/mips/powertv/asic/prealloc-calliope.c
+++ b/arch/mips/powertv/asic/prealloc-calliope.c
@@ -17,8 +17,8 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *

- * Author:       Ken Eppinett
- *               David Schleef <ds@schleef.org>
+ * Author:      Ken Eppinett
+ *              David Schleef <ds@schleef.org>

  */
 
 #include <linux/init.h>
  */
 
 #include <linux/init.h>


@@ -153,7 +153,7 @@ struct resource non_dvr_calliope_resources[] __initdata =
         * End of Resource marker
         */
        {
         * End of Resource marker
         */
        {

-               .flags  = 0,
+               .flags  = 0,

        },
 };
 
        },
 };
 


@@ -260,7 +260,7 @@ struct resource non_dvr_vze_calliope_resources[] __initdata =
         * End of Resource marker
         */
        {
         * End of Resource marker
         */
        {

-               .flags  = 0,
+               .flags  = 0,

        },
 };
 
        },
 };
 


@@ -380,6 +380,6 @@ struct resource non_dvr_vzf_calliope_resources[] __initdata =
         * End of Resource marker
         */
        {
         * End of Resource marker
         */
        {

-               .flags  = 0,
+               .flags  = 0,

        },
 };
        },
 };

diff --git a/arch/mips/powertv/asic/prealloc-cronus.c b/arch/mips/powertv/asic/prealloc-cronus.c
index c532b50521ec5e25d2e37e521caa2fb2f5a4730a..7c6ce75969357eeea546d2cecea41553e70966d3 100644 (file)
--- a/arch/mips/powertv/asic/prealloc-cronus.c
+++ b/arch/mips/powertv/asic/prealloc-cronus.c
@@ -17,8 +17,8 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *

- * Author:       Ken Eppinett
- *               David Schleef <ds@schleef.org>
+ * Author:      Ken Eppinett
+ *              David Schleef <ds@schleef.org>

  */
 
 #include <linux/init.h>
  */
 
 #include <linux/init.h>


@@ -78,7 +78,7 @@ struct resource dvr_cronus_resources[] __initdata =
         *
         *  This memory area is used for allocating buffers for Video decoding
         *  purposes.  Allocation/De-allocation within this buffer is managed
         *
         *  This memory area is used for allocating buffers for Video decoding
         *  purposes.  Allocation/De-allocation within this buffer is managed

-        *  by the STAVMEM driver of the STAPI.  They could be Decimated
+        *  by the STAVMEM driver of the STAPI.  They could be Decimated

         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
         *  video decoding purposes, for any video decoders on Zeus.
         */
         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
         *  video decoding purposes, for any video decoders on Zeus.
         */


@@ -185,7 +185,7 @@ struct resource dvr_cronus_resources[] __initdata =
         * End of Resource marker
         */
        {
         * End of Resource marker
         */
        {

-               .flags  = 0,
+               .flags  = 0,

        },
 };
 
        },
 };
 


@@ -241,7 +241,7 @@ struct resource non_dvr_cronus_resources[] __initdata =
         *
         *  This memory area is used for allocating buffers for Video decoding
         *  purposes.  Allocation/De-allocation within this buffer is managed
         *
         *  This memory area is used for allocating buffers for Video decoding
         *  purposes.  Allocation/De-allocation within this buffer is managed

-        *  by the STAVMEM driver of the STAPI.  They could be Decimated
+        *  by the STAVMEM driver of the STAPI.  They could be Decimated

         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
         *  video decoding purposes, for any video decoders on Zeus.
         */
         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
         *  video decoding purposes, for any video decoders on Zeus.
         */


@@ -335,6 +335,6 @@ struct resource non_dvr_cronus_resources[] __initdata =
         * End of Resource marker
         */
        {
         * End of Resource marker
         */
        {

-               .flags  = 0,
+               .flags  = 0,

        },
 };
        },
 };

diff --git a/arch/mips/powertv/asic/prealloc-cronuslite.c b/arch/mips/powertv/asic/prealloc-cronuslite.c
index b5537e49e7f5d92d5d7816bf9768487c802afc81..a7937ba7b4c020f85361cd0c10c572e5617eecc2 100644 (file)
--- a/arch/mips/powertv/asic/prealloc-cronuslite.c
+++ b/arch/mips/powertv/asic/prealloc-cronuslite.c
@@ -17,8 +17,8 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *

- * Author:       Ken Eppinett
- *               David Schleef <ds@schleef.org>
+ * Author:      Ken Eppinett
+ *              David Schleef <ds@schleef.org>

  */
 
 #include <linux/init.h>
  */
 
 #include <linux/init.h>


@@ -65,7 +65,7 @@ struct resource non_dvr_cronuslite_resources[] __initdata =
         *
         *  This memory area is used for allocating buffers for Video decoding
         *  purposes.  Allocation/De-allocation within this buffer is managed
         *
         *  This memory area is used for allocating buffers for Video decoding
         *  purposes.  Allocation/De-allocation within this buffer is managed

-        *  by the STAVMEM driver of the STAPI.  They could be Decimated
+        *  by the STAVMEM driver of the STAPI.  They could be Decimated

         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
         *  video decoding purposes, for any video decoders on Zeus.
         */
         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
         *  video decoding purposes, for any video decoders on Zeus.
         */


@@ -169,6 +169,6 @@ struct resource non_dvr_cronuslite_resources[] __initdata =
         * End of Resource marker
         */
        {
         * End of Resource marker
         */
        {

-               .flags  = 0,
+               .flags  = 0,

        },
 };
        },
 };

diff --git a/arch/mips/powertv/asic/prealloc-gaia.c b/arch/mips/powertv/asic/prealloc-gaia.c
index 8ac8c7aeb98646df7972791e799b786da8169db6..2303bbfe6b82dc56b0a631a8c9ba1c009b07ab77 100644 (file)
--- a/arch/mips/powertv/asic/prealloc-gaia.c
+++ b/arch/mips/powertv/asic/prealloc-gaia.c
@@ -17,7 +17,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *

- * Author:       David VomLehn
+ * Author:      David VomLehn

  */
 
 #include <linux/init.h>
  */
 
 #include <linux/init.h>


@@ -33,22 +33,22 @@ struct resource dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
-               .start  = 0x24000000,
-               .end    = 0x241FFFFF,           /* 2MiB */
-               .flags  = IORESOURCE_MEM,
+               .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
+               .start  = 0x24000000,
+               .end    = 0x241FFFFF,           /* 2MiB */
+               .flags  = IORESOURCE_MEM,

        },
        {
        },
        {

-               .name   = "ST231aMonitor",      /* 8KiB block ST231a monitor */
-               .start  = 0x24200000,
-               .end    = 0x24201FFF,
-               .flags  = IORESOURCE_MEM,
+               .name   = "ST231aMonitor",      /* 8KiB block ST231a monitor */
+               .start  = 0x24200000,
+               .end    = 0x24201FFF,
+               .flags  = IORESOURCE_MEM,

        },
        {
        },
        {

-               .name   = "MediaMemory1",
-               .start  = 0x24202000,
-               .end    = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
-               .flags  = IORESOURCE_MEM,
+               .name   = "MediaMemory1",
+               .start  = 0x24202000,
+               .end    = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+               .flags  = IORESOURCE_MEM,

        },
        /*
         *
        },
        /*
         *


@@ -56,22 +56,22 @@ struct resource dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "ST231bImage",        /* Delta-Mu 2 image and ram */
-               .start  = 0x60000000,
-               .end    = 0x601FFFFF,           /* 2MiB */
-               .flags  = IORESOURCE_IO,
+               .name   = "ST231bImage",        /* Delta-Mu 2 image and ram */
+               .start  = 0x60000000,
+               .end    = 0x601FFFFF,           /* 2MiB */
+               .flags  = IORESOURCE_IO,

        },
        {
        },
        {

-               .name   = "ST231bMonitor",      /* 8KiB block ST231b monitor */
-               .start  = 0x60200000,
-               .end    = 0x60201FFF,
-               .flags  = IORESOURCE_IO,
+               .name   = "ST231bMonitor",      /* 8KiB block ST231b monitor */
+               .start  = 0x60200000,
+               .end    = 0x60201FFF,
+               .flags  = IORESOURCE_IO,

        },
        {
        },
        {

-               .name   = "MediaMemory2",
-               .start  = 0x60202000,
-               .end    = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
-               .flags  = IORESOURCE_IO,
+               .name   = "MediaMemory2",
+               .start  = 0x60202000,
+               .end    = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+               .flags  = IORESOURCE_IO,

        },
        /*
         *
        },
        /*
         *


@@ -87,28 +87,28 @@ struct resource dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "DSP_Image_Buff",
-               .start  = 0x00000000,
-               .end    = 0x000FFFFF,
-               .flags  = IORESOURCE_MEM,
+               .name   = "DSP_Image_Buff",
+               .start  = 0x00000000,
+               .end    = 0x000FFFFF,
+               .flags  = IORESOURCE_MEM,

        },
        {
        },
        {

-               .name   = "ADSC_CPU_PCM_Buff",
-               .start  = 0x00000000,
-               .end    = 0x00009FFF,
-               .flags  = IORESOURCE_MEM,
+               .name   = "ADSC_CPU_PCM_Buff",
+               .start  = 0x00000000,
+               .end    = 0x00009FFF,
+               .flags  = IORESOURCE_MEM,

        },
        {
        },
        {

-               .name   = "ADSC_AUX_Buff",
-               .start  = 0x00000000,
-               .end    = 0x00003FFF,
-               .flags  = IORESOURCE_MEM,
+               .name   = "ADSC_AUX_Buff",
+               .start  = 0x00000000,
+               .end    = 0x00003FFF,
+               .flags  = IORESOURCE_MEM,

        },
        {
        },
        {

-               .name   = "ADSC_Main_Buff",
-               .start  = 0x00000000,
-               .end    = 0x00003FFF,
-               .flags  = IORESOURCE_MEM,
+               .name   = "ADSC_Main_Buff",
+               .start  = 0x00000000,
+               .end    = 0x00003FFF,
+               .flags  = IORESOURCE_MEM,

        },
        /*
         *
        },
        /*
         *


@@ -119,16 +119,16 @@ struct resource dvr_gaia_resources[] __initdata = {
         * Arbitrary Based Buffers:
         *  This memory area is used for allocating buffers for Video decoding
         *  purposes.  Allocation/De-allocation within this buffer is managed
         * Arbitrary Based Buffers:
         *  This memory area is used for allocating buffers for Video decoding
         *  purposes.  Allocation/De-allocation within this buffer is managed

-        *  by the STAVMEM driver of the STAPI.  They could be Decimated
+        *  by the STAVMEM driver of the STAPI.  They could be Decimated

         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
         *  video decoding purposes, for any video decoders on Zeus.
         *
         */
        {
         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
         *  video decoding purposes, for any video decoders on Zeus.
         *
         */
        {

-               .name   = "AVMEMPartition0",
-               .start  = 0x63580000,
-               .end    = 0x64180000 - 1,  /* 12 MB total */
-               .flags  = IORESOURCE_IO,
+               .name   = "AVMEMPartition0",
+               .start  = 0x63580000,
+               .end    = 0x64180000 - 1,  /* 12 MB total */
+               .flags  = IORESOURCE_IO,

        },
        /*
         *
        },
        /*
         *


@@ -141,10 +141,10 @@ struct resource dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "Docsis",
-               .start  = 0x62000000,
-               .end    = 0x62700000 - 1,       /* 7 MB total */
-               .flags  = IORESOURCE_IO,
+               .name   = "Docsis",
+               .start  = 0x62000000,
+               .end    = 0x62700000 - 1,       /* 7 MB total */
+               .flags  = IORESOURCE_IO,

        },
        /*
         *
        },
        /*
         *


@@ -157,10 +157,10 @@ struct resource dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "GraphicsHeap",
-               .start  = 0x62700000,
-               .end    = 0x63500000 - 1,       /* 14 MB total */
-               .flags  = IORESOURCE_IO,
+               .name   = "GraphicsHeap",
+               .start  = 0x62700000,
+               .end    = 0x63500000 - 1,       /* 14 MB total */
+               .flags  = IORESOURCE_IO,

        },
        /*
         *
        },
        /*
         *


@@ -173,10 +173,10 @@ struct resource dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "MulticomSHM",
-               .start  = 0x26000000,
-               .end    = 0x26020000 - 1,
-               .flags  = IORESOURCE_MEM,
+               .name   = "MulticomSHM",
+               .start  = 0x26000000,
+               .end    = 0x26020000 - 1,
+               .flags  = IORESOURCE_MEM,

        },
        /*
         *
        },
        /*
         *


@@ -189,10 +189,10 @@ struct resource dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "BMM_Buffer",
-               .start  = 0x00000000,
-               .end    = 0x00280000 - 1,
-               .flags  = IORESOURCE_MEM,
+               .name   = "BMM_Buffer",
+               .start  = 0x00000000,
+               .end    = 0x00280000 - 1,
+               .flags  = IORESOURCE_MEM,

        },
        /*
         *
        },
        /*
         *


@@ -205,10 +205,10 @@ struct resource dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "DisplayBins0",
-               .start  = 0x00000000,
-               .end    = 0x00000FFF,           /* 4 KB total */
-               .flags  = IORESOURCE_MEM,
+               .name   = "DisplayBins0",
+               .start  = 0x00000000,
+               .end    = 0x00000FFF,           /* 4 KB total */
+               .flags  = IORESOURCE_MEM,

        },
        /*
         *
        },
        /*
         *


@@ -221,10 +221,10 @@ struct resource dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "DisplayBins1",
-               .start  = 0x64AD4000,
-               .end    = 0x64AD5000 - 1,  /* 4 KB total */
-               .flags  = IORESOURCE_IO,
+               .name   = "DisplayBins1",
+               .start  = 0x64AD4000,
+               .end    = 0x64AD5000 - 1,  /* 4 KB total */
+               .flags  = IORESOURCE_IO,

        },
        /*
         *
        },
        /*
         *


@@ -237,11 +237,11 @@ struct resource dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "ITFS",
-               .start  = 0x64180000,
+               .name   = "ITFS",
+               .start  = 0x64180000,

                /* 815,104 bytes each for 2 ITFS partitions. */
                /* 815,104 bytes each for 2 ITFS partitions. */

-               .end    = 0x6430DFFF,
-               .flags  = IORESOURCE_IO,
+               .end    = 0x6430DFFF,
+               .flags  = IORESOURCE_IO,

        },
        /*
         *
        },
        /*
         *


@@ -254,17 +254,17 @@ struct resource dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "AvfsDmaMem",
-               .start  = 0x6430E000,
+               .name   = "AvfsDmaMem",
+               .start  = 0x6430E000,

                /* (945K * 8) = (128K *3) 5 playbacks / 3 server */
                /* (945K * 8) = (128K *3) 5 playbacks / 3 server */

-               .end    = 0x64AD0000 - 1,
-               .flags  = IORESOURCE_IO,
+               .end    = 0x64AD0000 - 1,
+               .flags  = IORESOURCE_IO,

        },
        {
        },
        {

-               .name   = "AvfsFileSys",
-               .start  = 0x64AD0000,
-               .end    = 0x64AD1000 - 1,  /* 4K */
-               .flags  = IORESOURCE_IO,
+               .name   = "AvfsFileSys",
+               .start  = 0x64AD0000,
+               .end    = 0x64AD1000 - 1,  /* 4K */
+               .flags  = IORESOURCE_IO,

        },
        /*
         *
        },
        /*
         *


@@ -277,10 +277,10 @@ struct resource dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "SmartCardInfo",
-               .start  = 0x64AD1000,
-               .end    = 0x64AD3800 - 1,
-               .flags  = IORESOURCE_IO,
+               .name   = "SmartCardInfo",
+               .start  = 0x64AD1000,
+               .end    = 0x64AD3800 - 1,
+               .flags  = IORESOURCE_IO,

        },
        /*
         *
        },
        /*
         *


@@ -290,22 +290,22 @@ struct resource dvr_gaia_resources[] __initdata = {
         *         NP IPC - must be video bank 2
         */
        {
         *         NP IPC - must be video bank 2
         */
        {

-               .name   = "NP_Reset_Vector",
-               .start  = 0x27c00000,
-               .end    = 0x27c01000 - 1,
-               .flags  = IORESOURCE_MEM,
+               .name   = "NP_Reset_Vector",
+               .start  = 0x27c00000,
+               .end    = 0x27c01000 - 1,
+               .flags  = IORESOURCE_MEM,

        },
        {
        },
        {

-               .name   = "NP_Image",
-               .start  = 0x27020000,
-               .end    = 0x27060000 - 1,
-               .flags  = IORESOURCE_MEM,
+               .name   = "NP_Image",
+               .start  = 0x27020000,
+               .end    = 0x27060000 - 1,
+               .flags  = IORESOURCE_MEM,

        },
        {
        },
        {

-               .name   = "NP_IPC",
-               .start  = 0x63500000,
-               .end    = 0x63580000 - 1,
-               .flags  = IORESOURCE_IO,
+               .name   = "NP_IPC",
+               .start  = 0x63500000,
+               .end    = 0x63580000 - 1,
+               .flags  = IORESOURCE_IO,

        },
        /*
         * Add other resources here
        },
        /*
         * Add other resources here


@@ -323,22 +323,22 @@ struct resource non_dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
-               .start  = 0x24000000,
-               .end    = 0x241FFFFF,           /* 2MiB */
-               .flags  = IORESOURCE_MEM,
+               .name   = "ST231aImage",        /* Delta-Mu 1 image and ram */
+               .start  = 0x24000000,
+               .end    = 0x241FFFFF,           /* 2MiB */
+               .flags  = IORESOURCE_MEM,

        },
        {
        },
        {

-               .name   = "ST231aMonitor",      /* 8KiB block ST231a monitor */
-               .start  = 0x24200000,
-               .end    = 0x24201FFF,
-               .flags  = IORESOURCE_MEM,
+               .name   = "ST231aMonitor",      /* 8KiB block ST231a monitor */
+               .start  = 0x24200000,
+               .end    = 0x24201FFF,
+               .flags  = IORESOURCE_MEM,

        },
        {
        },
        {

-               .name   = "MediaMemory1",
-               .start  = 0x24202000,
-               .end    = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
-               .flags  = IORESOURCE_MEM,
+               .name   = "MediaMemory1",
+               .start  = 0x24202000,
+               .end    = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+               .flags  = IORESOURCE_MEM,

        },
        /*
         *
        },
        /*
         *


@@ -346,22 +346,22 @@ struct resource non_dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "ST231bImage",        /* Delta-Mu 2 image and ram */
-               .start  = 0x60000000,
-               .end    = 0x601FFFFF,           /* 2MiB */
-               .flags  = IORESOURCE_IO,
+               .name   = "ST231bImage",        /* Delta-Mu 2 image and ram */
+               .start  = 0x60000000,
+               .end    = 0x601FFFFF,           /* 2MiB */
+               .flags  = IORESOURCE_IO,

        },
        {
        },
        {

-               .name   = "ST231bMonitor",      /* 8KiB block ST231b monitor */
-               .start  = 0x60200000,
-               .end    = 0x60201FFF,
-               .flags  = IORESOURCE_IO,
+               .name   = "ST231bMonitor",      /* 8KiB block ST231b monitor */
+               .start  = 0x60200000,
+               .end    = 0x60201FFF,
+               .flags  = IORESOURCE_IO,

        },
        {
        },
        {

-               .name   = "MediaMemory2",
-               .start  = 0x60202000,
-               .end    = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
-               .flags  = IORESOURCE_IO,
+               .name   = "MediaMemory2",
+               .start  = 0x60202000,
+               .end    = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */
+               .flags  = IORESOURCE_IO,

        },
        /*
         *
        },
        /*
         *


@@ -377,28 +377,28 @@ struct resource non_dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "DSP_Image_Buff",
-               .start  = 0x00000000,
-               .end    = 0x000FFFFF,
-               .flags  = IORESOURCE_MEM,
+               .name   = "DSP_Image_Buff",
+               .start  = 0x00000000,
+               .end    = 0x000FFFFF,
+               .flags  = IORESOURCE_MEM,

        },
        {
        },
        {

-               .name   = "ADSC_CPU_PCM_Buff",
-               .start  = 0x00000000,
-               .end    = 0x00009FFF,
-               .flags  = IORESOURCE_MEM,
+               .name   = "ADSC_CPU_PCM_Buff",
+               .start  = 0x00000000,
+               .end    = 0x00009FFF,
+               .flags  = IORESOURCE_MEM,

        },
        {
        },
        {

-               .name   = "ADSC_AUX_Buff",
-               .start  = 0x00000000,
-               .end    = 0x00003FFF,
-               .flags  = IORESOURCE_MEM,
+               .name   = "ADSC_AUX_Buff",
+               .start  = 0x00000000,
+               .end    = 0x00003FFF,
+               .flags  = IORESOURCE_MEM,

        },
        {
        },
        {

-               .name   = "ADSC_Main_Buff",
-               .start  = 0x00000000,
-               .end    = 0x00003FFF,
-               .flags  = IORESOURCE_MEM,
+               .name   = "ADSC_Main_Buff",
+               .start  = 0x00000000,
+               .end    = 0x00003FFF,
+               .flags  = IORESOURCE_MEM,

        },
        /*
         *
        },
        /*
         *


@@ -409,16 +409,16 @@ struct resource non_dvr_gaia_resources[] __initdata = {
         * Arbitrary Based Buffers:
         *  This memory area is used for allocating buffers for Video decoding
         *  purposes.  Allocation/De-allocation within this buffer is managed
         * Arbitrary Based Buffers:
         *  This memory area is used for allocating buffers for Video decoding
         *  purposes.  Allocation/De-allocation within this buffer is managed

-        *  by the STAVMEM driver of the STAPI.  They could be Decimated
+        *  by the STAVMEM driver of the STAPI.  They could be Decimated

         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
         *  video decoding purposes, for any video decoders on Zeus.
         *
         */
        {
         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
         *  video decoding purposes, for any video decoders on Zeus.
         *
         */
        {

-               .name   = "AVMEMPartition0",
-               .start  = 0x63580000,
-               .end    = 0x64180000 - 1,  /* 12 MB total */
-               .flags  = IORESOURCE_IO,
+               .name   = "AVMEMPartition0",
+               .start  = 0x63580000,
+               .end    = 0x64180000 - 1,  /* 12 MB total */
+               .flags  = IORESOURCE_IO,

        },
        /*
         *
        },
        /*
         *


@@ -431,10 +431,10 @@ struct resource non_dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "Docsis",
-               .start  = 0x62000000,
-               .end    = 0x62700000 - 1,       /* 7 MB total */
-               .flags  = IORESOURCE_IO,
+               .name   = "Docsis",
+               .start  = 0x62000000,
+               .end    = 0x62700000 - 1,       /* 7 MB total */
+               .flags  = IORESOURCE_IO,

        },
        /*
         *
        },
        /*
         *


@@ -447,10 +447,10 @@ struct resource non_dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "GraphicsHeap",
-               .start  = 0x62700000,
-               .end    = 0x63500000 - 1,       /* 14 MB total */
-               .flags  = IORESOURCE_IO,
+               .name   = "GraphicsHeap",
+               .start  = 0x62700000,
+               .end    = 0x63500000 - 1,       /* 14 MB total */
+               .flags  = IORESOURCE_IO,

        },
        /*
         *
        },
        /*
         *


@@ -463,10 +463,10 @@ struct resource non_dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "MulticomSHM",
-               .start  = 0x26000000,
-               .end    = 0x26020000 - 1,
-               .flags  = IORESOURCE_MEM,
+               .name   = "MulticomSHM",
+               .start  = 0x26000000,
+               .end    = 0x26020000 - 1,
+               .flags  = IORESOURCE_MEM,

        },
        /*
         *
        },
        /*
         *


@@ -479,10 +479,10 @@ struct resource non_dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "BMM_Buffer",
-               .start  = 0x00000000,
-               .end    = 0x000AA000 - 1,
-               .flags  = IORESOURCE_MEM,
+               .name   = "BMM_Buffer",
+               .start  = 0x00000000,
+               .end    = 0x000AA000 - 1,
+               .flags  = IORESOURCE_MEM,

        },
        /*
         *
        },
        /*
         *


@@ -495,10 +495,10 @@ struct resource non_dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "DisplayBins0",
-               .start  = 0x00000000,
-               .end    = 0x00000FFF,           /* 4 KB total */
-               .flags  = IORESOURCE_MEM,
+               .name   = "DisplayBins0",
+               .start  = 0x00000000,
+               .end    = 0x00000FFF,           /* 4 KB total */
+               .flags  = IORESOURCE_MEM,

        },
        /*
         *
        },
        /*
         *


@@ -511,10 +511,10 @@ struct resource non_dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "DisplayBins1",
-               .start  = 0x64AD4000,
-               .end    = 0x64AD5000 - 1,  /* 4 KB total */
-               .flags  = IORESOURCE_IO,
+               .name   = "DisplayBins1",
+               .start  = 0x64AD4000,
+               .end    = 0x64AD5000 - 1,  /* 4 KB total */
+               .flags  = IORESOURCE_IO,

        },
        /*
         *
        },
        /*
         *


@@ -523,10 +523,10 @@ struct resource non_dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "AvfsDmaMem",
-               .start  = 0x6430E000,
-               .end    = 0x645D2C00 - 1,  /* 945K * 3 for playback */
-               .flags  = IORESOURCE_IO,
+               .name   = "AvfsDmaMem",
+               .start  = 0x6430E000,
+               .end    = 0x645D2C00 - 1,  /* 945K * 3 for playback */
+               .flags  = IORESOURCE_IO,

        },
        /*
         *
        },
        /*
         *


@@ -539,10 +539,10 @@ struct resource non_dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "DiagPersistentMemory",
-               .start  = 0x00000000,
-               .end    = 0x10000 - 1,
-               .flags  = IORESOURCE_MEM,
+               .name   = "DiagPersistentMemory",
+               .start  = 0x00000000,
+               .end    = 0x10000 - 1,
+               .flags  = IORESOURCE_MEM,

        },
        /*
         *
        },
        /*
         *


@@ -555,10 +555,10 @@ struct resource non_dvr_gaia_resources[] __initdata = {
         *
         */
        {
         *
         */
        {

-               .name   = "SmartCardInfo",
-               .start  = 0x64AD1000,
-               .end    = 0x64AD3800 - 1,
-               .flags  = IORESOURCE_IO,
+               .name   = "SmartCardInfo",
+               .start  = 0x64AD1000,
+               .end    = 0x64AD3800 - 1,
+               .flags  = IORESOURCE_IO,

        },
        /*
         *
        },
        /*
         *


@@ -568,22 +568,22 @@ struct resource non_dvr_gaia_resources[] __initdata = {
         *         NP IPC - must be video bank 2
         */
        {
         *         NP IPC - must be video bank 2
         */
        {

-               .name   = "NP_Reset_Vector",
-               .start  = 0x27c00000,
-               .end    = 0x27c01000 - 1,
-               .flags  = IORESOURCE_MEM,
+               .name   = "NP_Reset_Vector",
+               .start  = 0x27c00000,
+               .end    = 0x27c01000 - 1,
+               .flags  = IORESOURCE_MEM,

        },
        {
        },
        {

-               .name   = "NP_Image",
-               .start  = 0x27020000,
-               .end    = 0x27060000 - 1,
-               .flags  = IORESOURCE_MEM,
+               .name   = "NP_Image",
+               .start  = 0x27020000,
+               .end    = 0x27060000 - 1,
+               .flags  = IORESOURCE_MEM,

        },
        {
        },
        {

-               .name   = "NP_IPC",
-               .start  = 0x63500000,
-               .end    = 0x63580000 - 1,
-               .flags  = IORESOURCE_IO,
+               .name   = "NP_IPC",
+               .start  = 0x63500000,
+               .end    = 0x63580000 - 1,
+               .flags  = IORESOURCE_IO,

        },
        { },
 };
        },
        { },
 };

diff --git a/arch/mips/powertv/asic/prealloc-zeus.c b/arch/mips/powertv/asic/prealloc-zeus.c
index 96480a2395c0c5ccc41c38cb512dd2b85544615e..6e76f09c68d65d4725953d7c6b87870863c374f1 100644 (file)
--- a/arch/mips/powertv/asic/prealloc-zeus.c
+++ b/arch/mips/powertv/asic/prealloc-zeus.c
@@ -17,8 +17,8 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *

- * Author:       Ken Eppinett
- *               David Schleef <ds@schleef.org>
+ * Author:      Ken Eppinett
+ *              David Schleef <ds@schleef.org>

  */
 
 #include <linux/init.h>
  */
 
 #include <linux/init.h>


@@ -78,7 +78,7 @@ struct resource dvr_zeus_resources[] __initdata =
         *
         *  This memory area is used for allocating buffers for Video decoding
         *  purposes.  Allocation/De-allocation within this buffer is managed
         *
         *  This memory area is used for allocating buffers for Video decoding
         *  purposes.  Allocation/De-allocation within this buffer is managed

-        *  by the STAVMEM driver of the STAPI.  They could be Decimated
+        *  by the STAVMEM driver of the STAPI.  They could be Decimated

         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
         *  video decoding purposes, for any video decoders on Zeus.
         */
         *  Picture Buffers, Intermediate Buffers, as deemed necessary for
         *  video decoding purposes, for any video decoders on Zeus.
         */


@@ -175,7 +175,7 @@ struct resource dvr_zeus_resources[] __initdata =
         * End of Resource marker
         */
        {
         * End of Resource marker
         */
        {

-               .flags  = 0,
+               .flags  = 0,

        },
 };
 
        },
 };
 


@@ -299,6 +299,6 @@ struct resource non_dvr_zeus_resources[] __initdata =
         * End of Resource marker
         */
        {
         * End of Resource marker
         */
        {

-               .flags  = 0,
+               .flags  = 0,

        },
 };
        },
 };

diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c
index c6979353980bd895be6846687575f6bdca837d33..5bd9d8f468cc3582ab02114ff272b833d8893565 100644 (file)
--- a/arch/mips/powertv/init.c
+++ b/arch/mips/powertv/init.c
@@ -1,5 +1,5 @@
 /*
 /*

- * Copyright (C) 1999, 2000, 2004, 2005  MIPS Technologies, Inc.
+ * Copyright (C) 1999, 2000, 2004, 2005         MIPS Technologies, Inc.

  *     All rights reserved.
  *     Authors: Carsten Langgaard <carstenl@mips.com>
  *              Maciej W. Rozycki <macro@mips.com>
  *     All rights reserved.
  *     Authors: Carsten Langgaard <carstenl@mips.com>
  *              Maciej W. Rozycki <macro@mips.com>

diff --git a/arch/mips/powertv/ioremap.c b/arch/mips/powertv/ioremap.c
index a77c6f62fe238ccf4e33c6b6784865c2d3a7d2a6..d060478aab037a91becb84c42a5532b11e565637 100644 (file)
--- a/arch/mips/powertv/ioremap.c
+++ b/arch/mips/powertv/ioremap.c
@@ -19,9 +19,9 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *

- * Author:       David VomLehn <dvomlehn@cisco.com>
+ * Author:      David VomLehn <dvomlehn@cisco.com>

  *
  *

- * Description:  Defines the platform resources for the SA settop.
+ * Description:         Defines the platform resources for the SA settop.

  *
  * NOTE: The bootloader allocates persistent memory at an address which is
  * 16 MiB below the end of the highest address in KSEG0. All fixed
  *
  * NOTE: The bootloader allocates persistent memory at an address which is
  * 16 MiB below the end of the highest address in KSEG0. All fixed

diff --git a/arch/mips/powertv/memory.c b/arch/mips/powertv/memory.c
index fb3d29660c42d601eff8b2b9cdba37f7a2fad68d..6e5f1bdc59b5fa77215803d8e919b55afe3c081d 100644 (file)
--- a/arch/mips/powertv/memory.c
+++ b/arch/mips/powertv/memory.c
@@ -60,7 +60,7 @@ unsigned long ptv_memsize;
  * struct low_mem_reserved - Items in low memory that are reserved
  * @start:     Physical address of item
  * @size:      Size, in bytes, of this item
  * struct low_mem_reserved - Items in low memory that are reserved
  * @start:     Physical address of item
  * @size:      Size, in bytes, of this item

- * @is_aliased:        True if this is RAM aliased from another location. If false,
+ * @is_aliased: True if this is RAM aliased from another location. If false,

  *             it is something other than aliased RAM and the RAM in the
  *             unaliased address is still visible outside of low memory.
  */
  *             it is something other than aliased RAM and the RAM in the
  *             unaliased address is still visible outside of low memory.
  */

diff --git a/arch/mips/powertv/powertv-usb.c b/arch/mips/powertv/powertv-usb.c
index b0e2afa89395383cc73cde140fbf52c04432575e..d845eace58e9c5c93f517ad19d5292fde73b9795 100644 (file)
--- a/arch/mips/powertv/powertv-usb.c
+++ b/arch/mips/powertv/powertv-usb.c
@@ -1,7 +1,7 @@
 /*
  *                             powertv-usb.c
  *
 /*
  *                             powertv-usb.c
  *

- * Description:  ASIC-specific USB device setup and shutdown
+ * Description:         ASIC-specific USB device setup and shutdown

  *
  * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
  * Copyright (C) 2009 Cisco Systems, Inc.
  *
  * Copyright (C) 2005-2009 Scientific-Atlanta, Inc.
  * Copyright (C) 2009 Cisco Systems, Inc.


@@ -20,8 +20,8 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  *

- * Author:       Ken Eppinett
- *               David Schleef <ds@schleef.org>
+ * Author:      Ken Eppinett
+ *              David Schleef <ds@schleef.org>

  *
  * NOTE: The bootloader allocates persistent memory at an address which is
  * 16 MiB below the end of the highest address in KSEG0. All fixed
  *
  * NOTE: The bootloader allocates persistent memory at an address which is
  * 16 MiB below the end of the highest address in KSEG0. All fixed


@@ -70,15 +70,15 @@
 #define MCC2_GMII_RX2_CLOCK_SELECT     (1 << 16)
 
 #define ETHER_CLK_CONFIG       (MCC2_GMII_GCLK_TO_PAD |        \
 #define MCC2_GMII_RX2_CLOCK_SELECT     (1 << 16)
 
 #define ETHER_CLK_CONFIG       (MCC2_GMII_GCLK_TO_PAD |        \

-                                MCC2_ETHER125_0_CLOCK_SELECT | \
+                                MCC2_ETHER125_0_CLOCK_SELECT | \

                                 MCC2_RMII_0_CLOCK_SELECT |     \
                                 MCC2_GMII_TX0_CLOCK_SELECT |   \
                                 MCC2_GMII_RX0_CLOCK_SELECT |   \
                                 MCC2_RMII_0_CLOCK_SELECT |     \
                                 MCC2_GMII_TX0_CLOCK_SELECT |   \
                                 MCC2_GMII_RX0_CLOCK_SELECT |   \

-                                MCC2_ETHER125_1_CLOCK_SELECT | \
+                                MCC2_ETHER125_1_CLOCK_SELECT | \

                                 MCC2_RMII_1_CLOCK_SELECT |     \
                                 MCC2_GMII_TX1_CLOCK_SELECT |   \
                                 MCC2_GMII_RX1_CLOCK_SELECT |   \
                                 MCC2_RMII_1_CLOCK_SELECT |     \
                                 MCC2_GMII_TX1_CLOCK_SELECT |   \
                                 MCC2_GMII_RX1_CLOCK_SELECT |   \

-                                MCC2_ETHER125_2_CLOCK_SELECT | \
+                                MCC2_ETHER125_2_CLOCK_SELECT | \

                                 MCC2_RMII_2_CLOCK_SELECT |     \
                                 MCC2_GMII_TX2_CLOCK_SELECT |   \
                                 MCC2_GMII_RX2_CLOCK_SELECT)
                                 MCC2_RMII_2_CLOCK_SELECT |     \
                                 MCC2_GMII_TX2_CLOCK_SELECT |   \
                                 MCC2_GMII_RX2_CLOCK_SELECT)


@@ -98,9 +98,9 @@
 
 #define QAM_FS_DISABLE_DIVIDE_BY_3             (1 << 5)
 #define QAM_FS_ENABLE_PROGRAM                  (1 << 4)
 
 #define QAM_FS_DISABLE_DIVIDE_BY_3             (1 << 5)
 #define QAM_FS_ENABLE_PROGRAM                  (1 << 4)

-#define        QAM_FS_ENABLE_OUTPUT                    (1 << 3)
-#define        QAM_FS_SELECT_TEST_BYPASS               (1 << 2)
-#define        QAM_FS_DISABLE_DIGITAL_STANDBY          (1 << 1)
+#define QAM_FS_ENABLE_OUTPUT                   (1 << 3)
+#define QAM_FS_SELECT_TEST_BYPASS              (1 << 2)
+#define QAM_FS_DISABLE_DIGITAL_STANDBY         (1 << 1)

 #define QAM_FS_CHOOSE_FS                       (1 << 0)
 
 /* Definitions for fs432x4a_ctl register */
 #define QAM_FS_CHOOSE_FS                       (1 << 0)
 
 /* Definitions for fs432x4a_ctl register */


@@ -142,14 +142,14 @@
 static struct resource ehci_resources[] = {
        {
                .parent = &asic_resource,
 static struct resource ehci_resources[] = {
        {
                .parent = &asic_resource,

-               .start  = 0,
-               .end    = 0xff,
-               .flags  = IORESOURCE_MEM,
+               .start  = 0,
+               .end    = 0xff,
+               .flags  = IORESOURCE_MEM,

        },
        {
        },
        {

-               .start  = irq_usbehci,
-               .end    = irq_usbehci,
-               .flags  = IORESOURCE_IRQ,
+               .start  = irq_usbehci,
+               .end    = irq_usbehci,
+               .flags  = IORESOURCE_IRQ,

        },
 };
 
        },
 };
 


@@ -169,14 +169,14 @@ static struct platform_device ehci_device = {
 static struct resource ohci_resources[] = {
        {
                .parent = &asic_resource,
 static struct resource ohci_resources[] = {
        {
                .parent = &asic_resource,

-               .start  = 0,
-               .end    = 0xff,
-               .flags  = IORESOURCE_MEM,
+               .start  = 0,
+               .end    = 0xff,
+               .flags  = IORESOURCE_MEM,

        },
        {
        },
        {

-               .start  = irq_usbohci,
-               .end    = irq_usbohci,
-               .flags  = IORESOURCE_IRQ,
+               .start  = irq_usbohci,
+               .end    = irq_usbohci,
+               .flags  = IORESOURCE_IRQ,

        },
 };
 
        },
 };
 


@@ -207,9 +207,9 @@ static DEFINE_SPINLOCK(usb_regs_lock);
  *
  * QAM frequency selection code, which affects the frequency at which USB
  * runs. The frequency is calculated as:
  *
  * QAM frequency selection code, which affects the frequency at which USB
  * runs. The frequency is calculated as:

- *                             2^15 * ndiv * Fin
+ *                            2^15 * ndiv * Fin

  * Fout = ------------------------------------------------------------
  * Fout = ------------------------------------------------------------

- *        (sdiv * (ipe * (1 + md/32) - (ipe - 2^15)*(1 + (md + 1)/32)))
+ *       (sdiv * (ipe * (1 + md/32) - (ipe - 2^15)*(1 + (md + 1)/32)))

  * where:
  * Fin         54 MHz
  * ndiv                QAM_FS_NSDIV_54MHZ ? 8 : 16
  * where:
  * Fin         54 MHz
  * ndiv                QAM_FS_NSDIV_54MHZ ? 8 : 16

diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c
index 716e9a12f0e77a0c85f492d3cf760ce41059690a..3af00b2a26ee97a7b98cfd95f8704e97e3383734 100644 (file)
--- a/arch/mips/rb532/devices.c
+++ b/arch/mips/rb532/devices.c
@@ -215,9 +215,9 @@ static struct resource rb532_wdt_res[] = {
 };
 
 static struct platform_device rb532_wdt = {
 };
 
 static struct platform_device rb532_wdt = {

-       .name           = "rc32434_wdt",
-       .id             = -1,
-       .resource       = rb532_wdt_res,
+       .name           = "rc32434_wdt",
+       .id             = -1,
+       .resource       = rb532_wdt_res,

        .num_resources  = ARRAY_SIZE(rb532_wdt_res),
 };
 
        .num_resources  = ARRAY_SIZE(rb532_wdt_res),
 };
 


@@ -235,8 +235,8 @@ static struct plat_serial8250_port rb532_uart_res[] = {
 };
 
 static struct platform_device rb532_uart = {
 };
 
 static struct platform_device rb532_uart = {

-       .name              = "serial8250",
-       .id                = PLAT8250_DEV_PLATFORM,
+       .name              = "serial8250",
+       .id                = PLAT8250_DEV_PLATFORM,

        .dev.platform_data = &rb532_uart_res,
 };
 
        .dev.platform_data = &rb532_uart_res,
 };
 


@@ -273,7 +273,7 @@ static void __init parse_mac_addr(char *macstr)
 
 
 /* NAND definitions */
 
 
 /* NAND definitions */

-#define NAND_CHIP_DELAY        25
+#define NAND_CHIP_DELAY 25

 
 static void __init rb532_nand_setup(void)
 {
 
 static void __init rb532_nand_setup(void)
 {

diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c
index 6ec41df3cb99f22e96683c2c3b563af8ee7eee51..a18007613c30f3234d37499c3d8dbeef9aefcbff 100644 (file)
--- a/arch/mips/rb532/gpio.c
+++ b/arch/mips/rb532/gpio.c
@@ -44,10 +44,10 @@ struct rb532_gpio_chip {
 
 static struct resource rb532_gpio_reg0_res[] = {
        {
 
 static struct resource rb532_gpio_reg0_res[] = {
        {

-               .name   = "gpio_reg0",
-               .start  = REGBASE + GPIOBASE,
-               .end    = REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1,
-               .flags  = IORESOURCE_MEM,
+               .name   = "gpio_reg0",
+               .start  = REGBASE + GPIOBASE,
+               .end    = REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1,
+               .flags  = IORESOURCE_MEM,

        }
 };
 
        }
 };
 

diff --git a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c
index f298430cff0716d8bce3aba7f6410e72b005b86c..3a431e802bbc903a57215dfee953a0ae1febfc84 100644 (file)
--- a/arch/mips/rb532/irq.c
+++ b/arch/mips/rb532/irq.c
@@ -21,7 +21,7 @@
  *
  * Copyright 2002 MontaVista Software Inc.
  * Author: MontaVista Software, Inc.
  *
  * Copyright 2002 MontaVista Software Inc.
  * Author: MontaVista Software, Inc.

- *              stevel@mvista.com or source@mvista.com
+ *             stevel@mvista.com or source@mvista.com

  */
 
 #include <linux/bitops.h>
  */
 
 #include <linux/bitops.h>


@@ -51,7 +51,7 @@ struct intr_group {
        volatile u32 *base_addr;
 };
 
        volatile u32 *base_addr;
 };
 

-#define RC32434_NR_IRQS  (GROUP4_IRQ_BASE + 32)
+#define RC32434_NR_IRQS         (GROUP4_IRQ_BASE + 32)

 
 #if (NR_IRQS < RC32434_NR_IRQS)
 #error Too little irqs defined. Did you override <asm/irq.h> ?
 
 #if (NR_IRQS < RC32434_NR_IRQS)
 #error Too little irqs defined. Did you override <asm/irq.h> ?

diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c
index 4a6057b35b9d55765f89d25705d98318ddb6d6a9..a0a79222ce0ba8fec882a0fce7c8bf4652c99109 100644 (file)
--- a/arch/mips/sgi-ip22/ip22-eisa.c
+++ b/arch/mips/sgi-ip22/ip22-eisa.c
@@ -2,7 +2,7 @@
  * Basic EISA bus support for the SGI Indigo-2.
  *
  * (C) 2002 Pascal Dameme <netinet@freesurf.fr>
  * Basic EISA bus support for the SGI Indigo-2.
  *
  * (C) 2002 Pascal Dameme <netinet@freesurf.fr>

- *      and Marc Zyngier <mzyngier@freesurf.fr>
+ *     and Marc Zyngier <mzyngier@freesurf.fr>

  *
  * This code is released under both the GPL version 2 and BSD
  * licenses.  Either license may be used.
  *
  * This code is released under both the GPL version 2 and BSD
  * licenses.  Either license may be used.


@@ -40,13 +40,13 @@
 
 /* I2 has four EISA slots. */
 #define IP22_EISA_MAX_SLOTS      4
 
 /* I2 has four EISA slots. */
 #define IP22_EISA_MAX_SLOTS      4

-#define EISA_MAX_IRQ             16
+#define EISA_MAX_IRQ            16

 
 

-#define EIU_MODE_REG     0x0001ffc0
-#define EIU_STAT_REG     0x0001ffc4
-#define EIU_PREMPT_REG   0x0001ffc8
-#define EIU_QUIET_REG    0x0001ffcc
-#define EIU_INTRPT_ACK   0x00010004
+#define EIU_MODE_REG    0x0001ffc0
+#define EIU_STAT_REG    0x0001ffc4
+#define EIU_PREMPT_REG  0x0001ffc8
+#define EIU_QUIET_REG   0x0001ffcc
+#define EIU_INTRPT_ACK  0x00010004

 
 static char __init *decode_eisa_sig(unsigned long addr)
 {
 
 static char __init *decode_eisa_sig(unsigned long addr)
 {

diff --git a/arch/mips/sgi-ip22/ip22-gio.c b/arch/mips/sgi-ip22/ip22-gio.c
index f5ebc092aed59d1a58bbf655e8f85af58b4fac99..ab0e379dc7e08dc7403753812e3c160570b3ebc5 100644 (file)
--- a/arch/mips/sgi-ip22/ip22-gio.c
+++ b/arch/mips/sgi-ip22/ip22-gio.c
@@ -15,7 +15,7 @@ static struct bus_type gio_bus_type;
 
 static struct {
        const char *name;
 
 static struct {
        const char *name;

-       __u8       id;
+       __u8       id;

 } gio_name_table[] = {
        { .name = "SGI Impact", .id = 0x10 },
        { .name = "Phobos G160", .id = 0x35 },
 } gio_name_table[] = {
        { .name = "SGI Impact", .id = 0x10 },
        { .name = "Phobos G160", .id = 0x35 },


@@ -376,15 +376,15 @@ static void ip22_check_gio(int slotno, unsigned long addr)
 }
 
 static struct bus_type gio_bus_type = {
 }
 
 static struct bus_type gio_bus_type = {

-       .name      = "gio",
+       .name      = "gio",

        .dev_attrs = gio_dev_attrs,
        .dev_attrs = gio_dev_attrs,

-       .match     = gio_bus_match,
-       .probe     = gio_device_probe,
-       .remove    = gio_device_remove,
+       .match     = gio_bus_match,
+       .probe     = gio_device_probe,
+       .remove    = gio_device_remove,

        .suspend   = gio_device_suspend,
        .suspend   = gio_device_suspend,

-       .resume    = gio_device_resume,
+       .resume    = gio_device_resume,

        .shutdown  = gio_device_shutdown,
        .shutdown  = gio_device_shutdown,

-       .uevent    = gio_device_uevent,
+       .uevent    = gio_device_uevent,

 };
 
 static struct resource gio_bus_resource = {
 };
 
 static struct resource gio_bus_resource = {

diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index 3f2b7633f946a6bbe020d80f4643ad253789da82..3db64d51798ddb4afd1fd3893a270c954db0a921 100644 (file)
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -1,12 +1,12 @@
 /*
  * ip22-int.c: Routines for generic manipulation of the INT[23] ASIC
 /*
  * ip22-int.c: Routines for generic manipulation of the INT[23] ASIC

- *             found on INDY and Indigo2 workstations.
+ *            found on INDY and Indigo2 workstations.

  *
  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  * Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org)
  * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu)
  *
  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  * Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org)
  * Copyright (C) 1999 Andrew R. Baker (andrewb@uab.edu)

- *                    - Indigo2 changes
- *                    - Interrupt handling fixes
+ *                   - Indigo2 changes
+ *                   - Interrupt handling fixes

  * Copyright (C) 2001, 2003 Ladislav Michl (ladis@linux-mips.org)
  */
 #include <linux/types.h>
  * Copyright (C) 2001, 2003 Ladislav Michl (ladis@linux-mips.org)
  */
 #include <linux/types.h>


@@ -195,24 +195,24 @@ extern void indy_8254timer_irq(void);
  * at all) like:
  *
  *     MIPS IRQ        Source
  * at all) like:
  *
  *     MIPS IRQ        Source

- *      --------        ------
- *             0       Software (ignored)
- *             1        Software (ignored)
- *             2        Local IRQ level zero
- *             3        Local IRQ level one
- *             4        8254 Timer zero
- *             5        8254 Timer one
- *             6        Bus Error
- *             7        R4k timer (what we use)
+ *     --------        ------
+ *            0        Software (ignored)
+ *            1        Software (ignored)
+ *            2        Local IRQ level zero
+ *            3        Local IRQ level one
+ *            4        8254 Timer zero
+ *            5        8254 Timer one
+ *            6        Bus Error
+ *            7        R4k timer (what we use)

  *
  * We handle the IRQ according to _our_ priority which is:
  *
  *
  * We handle the IRQ according to _our_ priority which is:
  *

- * Highest ----     R4k Timer
- *                  Local IRQ zero
- *                  Local IRQ one
- *                  Bus Error
- *                  8254 Timer zero
- * Lowest  ----     8254 Timer one
+ * Highest ----            R4k Timer
+ *                 Local IRQ zero
+ *                 Local IRQ one
+ *                 Bus Error
+ *                 8254 Timer zero
+ * Lowest  ----            8254 Timer one

  *
  * then we just return, if multiple IRQs are pending then we will just take
  * another exception, big deal.
  *
  * then we just return, if multiple IRQs are pending then we will just take
  * another exception, big deal.

diff --git a/arch/mips/sgi-ip22/ip22-mc.c b/arch/mips/sgi-ip22/ip22-mc.c
index 75ada8a9713b355e4ae6a841a44fde5dff84731e..7cec0a4e527d86df5f7e57d51f38ef5a1e059999 100644 (file)
--- a/arch/mips/sgi-ip22/ip22-mc.c
+++ b/arch/mips/sgi-ip22/ip22-mc.c
@@ -121,22 +121,22 @@ void __init sgimc_init(void)
         */
 
        /* Step 0: Make sure we turn off the watchdog in case it's
         */
 
        /* Step 0: Make sure we turn off the watchdog in case it's

-        *         still running (which might be the case after a
-        *         soft reboot).
+        *         still running (which might be the case after a
+        *         soft reboot).

         */
        tmp = sgimc->cpuctrl0;
        tmp &= ~SGIMC_CCTRL0_WDOG;
        sgimc->cpuctrl0 = tmp;
 
        /* Step 1: The CPU/GIO error status registers will not latch
         */
        tmp = sgimc->cpuctrl0;
        tmp &= ~SGIMC_CCTRL0_WDOG;
        sgimc->cpuctrl0 = tmp;
 
        /* Step 1: The CPU/GIO error status registers will not latch

-        *         up a new error status until the register has been
-        *         cleared by the cpu.  These status registers are
-        *         cleared by writing any value to them.
+        *         up a new error status until the register has been
+        *         cleared by the cpu.  These status registers are
+        *         cleared by writing any value to them.

         */
        sgimc->cstat = sgimc->gstat = 0;
 
        /* Step 2: Enable all parity checking in cpu control register
         */
        sgimc->cstat = sgimc->gstat = 0;
 
        /* Step 2: Enable all parity checking in cpu control register

-        *         zero.
+        *         zero.

         */
        /* don't touch parity settings for IP28 */
        tmp = sgimc->cpuctrl0;
         */
        /* don't touch parity settings for IP28 */
        tmp = sgimc->cpuctrl0;


@@ -147,7 +147,7 @@ void __init sgimc_init(void)
        sgimc->cpuctrl0 = tmp;
 
        /* Step 3: Setup the MC write buffer depth, this is controlled
        sgimc->cpuctrl0 = tmp;
 
        /* Step 3: Setup the MC write buffer depth, this is controlled

-        *         in cpu control register 1 in the lower 4 bits.
+        *         in cpu control register 1 in the lower 4 bits.

         */
        tmp = sgimc->cpuctrl1;
        tmp &= ~0xf;
         */
        tmp = sgimc->cpuctrl1;
        tmp &= ~0xf;


@@ -155,26 +155,26 @@ void __init sgimc_init(void)
        sgimc->cpuctrl1 = tmp;
 
        /* Step 4: Initialize the RPSS divider register to run as fast
        sgimc->cpuctrl1 = tmp;
 
        /* Step 4: Initialize the RPSS divider register to run as fast

-        *         as it can correctly operate.  The register is laid
-        *         out as follows:
+        *         as it can correctly operate.  The register is laid
+        *         out as follows:

         *
         *

-        *         ----------------------------------------
-        *         |  RESERVED  |   INCREMENT   | DIVIDER |
-        *         ----------------------------------------
-        *          31        16 15            8 7       0
+        *         ----------------------------------------
+        *         |  RESERVED  |   INCREMENT   | DIVIDER |
+        *         ----------------------------------------
+        *          31        16 15            8 7       0

         *
         *

-        *         DIVIDER determines how often a 'tick' happens,
-        *         INCREMENT determines by how the RPSS increment
-        *         registers value increases at each 'tick'. Thus,
-        *         for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101
+        *         DIVIDER determines how often a 'tick' happens,
+        *         INCREMENT determines by how the RPSS increment
+        *         registers value increases at each 'tick'. Thus,
+        *         for IP22 we get INCREMENT=1, DIVIDER=1 == 0x101

         */
        sgimc->divider = 0x101;
 
        /* Step 5: Initialize GIO64 arbitrator configuration register.
         *
         * NOTE: HPC init code in sgihpc_init() must run before us because
         */
        sgimc->divider = 0x101;
 
        /* Step 5: Initialize GIO64 arbitrator configuration register.
         *
         * NOTE: HPC init code in sgihpc_init() must run before us because

-        *       we need to know Guiness vs. FullHouse and the board
-        *       revision on this machine. You have been warned.
+        *       we need to know Guiness vs. FullHouse and the board
+        *       revision on this machine. You have been warned.

         */
 
        /* First the basic invariants across all GIO64 implementations. */
         */
 
        /* First the basic invariants across all GIO64 implementations. */


@@ -187,18 +187,18 @@ void __init sgimc_init(void)
                if (SGIOC_SYSID_BOARDREV(sgioc->sysid) < 2) {
                        tmp |= SGIMC_GIOPAR_HPC264;     /* 2nd HPC at 64bits */
                        tmp |= SGIMC_GIOPAR_PLINEEXP0;  /* exp0 pipelines */
                if (SGIOC_SYSID_BOARDREV(sgioc->sysid) < 2) {
                        tmp |= SGIMC_GIOPAR_HPC264;     /* 2nd HPC at 64bits */
                        tmp |= SGIMC_GIOPAR_PLINEEXP0;  /* exp0 pipelines */

-                       tmp |= SGIMC_GIOPAR_MASTEREXP1; /* exp1 masters */
+                       tmp |= SGIMC_GIOPAR_MASTEREXP1; /* exp1 masters */

                        tmp |= SGIMC_GIOPAR_RTIMEEXP0;  /* exp0 is realtime */
                } else {
                        tmp |= SGIMC_GIOPAR_HPC264;     /* 2nd HPC 64bits */
                        tmp |= SGIMC_GIOPAR_PLINEEXP0;  /* exp[01] pipelined */
                        tmp |= SGIMC_GIOPAR_PLINEEXP1;
                        tmp |= SGIMC_GIOPAR_RTIMEEXP0;  /* exp0 is realtime */
                } else {
                        tmp |= SGIMC_GIOPAR_HPC264;     /* 2nd HPC 64bits */
                        tmp |= SGIMC_GIOPAR_PLINEEXP0;  /* exp[01] pipelined */
                        tmp |= SGIMC_GIOPAR_PLINEEXP1;

-                       tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */
+                       tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA masters */

                }
        } else {
                /* Guiness specific settings. */
                tmp |= SGIMC_GIOPAR_EISA64;     /* MC talks to EISA at 64bits */
                }
        } else {
                /* Guiness specific settings. */
                tmp |= SGIMC_GIOPAR_EISA64;     /* MC talks to EISA at 64bits */

-               tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA bus can act as master */
+               tmp |= SGIMC_GIOPAR_MASTEREISA; /* EISA bus can act as master */

        }
        sgimc->giopar = tmp;    /* poof */
 
        }
        sgimc->giopar = tmp;    /* poof */
 

diff --git a/arch/mips/sgi-ip22/ip22-nvram.c b/arch/mips/sgi-ip22/ip22-nvram.c
index 0177566475d4cd42ae3a68d2eb1c73a4c39789c9..e077036a676a506f1fb52cf3678eed2776be94ae 100644 (file)
--- a/arch/mips/sgi-ip22/ip22-nvram.c
+++ b/arch/mips/sgi-ip22/ip22-nvram.c
@@ -14,11 +14,11 @@
 #define EEPROM_WRITE   0xa000  /* serial memory write */
 #define EEPROM_WRALL   0x8800  /* write all registers */
 #define EEPROM_WDS     0x8000  /* disable all programming */
 #define EEPROM_WRITE   0xa000  /* serial memory write */
 #define EEPROM_WRALL   0x8800  /* write all registers */
 #define EEPROM_WDS     0x8000  /* disable all programming */

-#define        EEPROM_PRREAD   0xc000  /* read protect register */
-#define        EEPROM_PREN     0x9800  /* enable protect register mode */
-#define        EEPROM_PRCLEAR  0xffff  /* clear protect register */
-#define        EEPROM_PRWRITE  0xa000  /* write protect register */
-#define        EEPROM_PRDS     0x8000  /* disable protect register, forever */
+#define EEPROM_PRREAD  0xc000  /* read protect register */
+#define EEPROM_PREN    0x9800  /* enable protect register mode */
+#define EEPROM_PRCLEAR 0xffff  /* clear protect register */
+#define EEPROM_PRWRITE 0xa000  /* write protect register */
+#define EEPROM_PRDS    0x8000  /* disable protect register, forever */

 
 #define EEPROM_EPROT   0x01    /* Protect register enable */
 #define EEPROM_CSEL    0x02    /* Chip select */
 
 #define EEPROM_EPROT   0x01    /* Protect register enable */
 #define EEPROM_CSEL    0x02    /* Chip select */


@@ -27,7 +27,7 @@
 #define EEPROM_DATI    0x10    /* Data in */
 
 /* We need to use these functions early... */
 #define EEPROM_DATI    0x10    /* Data in */
 
 /* We need to use these functions early... */

-#define delay()        ({                                              \
+#define delay() ({                                             \

        int x;                                                  \
        for (x=0; x<100000; x++) __asm__ __volatile__(""); })
 
        int x;                                                  \
        for (x=0; x<100000; x++) __asm__ __volatile__(""); })
 


@@ -35,7 +35,7 @@
        __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr);     \
        __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr);     \
        __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr);    \
        __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr);     \
        __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr);     \
        __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr);    \

-       delay();                                                \
+       delay();                                                \

        __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr);      \
        __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
 
        __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr);      \
        __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
 


@@ -46,7 +46,7 @@
        __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr);     \
        __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
 
        __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr);     \
        __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
 

-#define        BITS_IN_COMMAND 11
+#define BITS_IN_COMMAND 11

 /*
  * clock in the nvram command and the register number. For the
  * national semiconductor nv ram chip the op code is 3 bits and
 /*
  * clock in the nvram command and the register number. For the
  * national semiconductor nv ram chip the op code is 3 bits and

diff --git a/arch/mips/sgi-ip22/ip22-platform.c b/arch/mips/sgi-ip22/ip22-platform.c
index 698904daf901d17a921ae5c3c24effa85706fb6a..a14fd32b76bdae03383e19e35ae71e663da1c802 100644 (file)
--- a/arch/mips/sgi-ip22/ip22-platform.c
+++ b/arch/mips/sgi-ip22/ip22-platform.c
@@ -137,7 +137,7 @@ static int __init sgiseeq_devinit(void)
 
        eth0_pd.hpc = hpc3c0;
        eth0_pd.irq = SGI_ENET_IRQ;
 
        eth0_pd.hpc = hpc3c0;
        eth0_pd.irq = SGI_ENET_IRQ;

-#define EADDR_NVOFS     250
+#define EADDR_NVOFS    250

        for (i = 0; i < 3; i++) {
                unsigned short tmp = ip22_nvram_read(EADDR_NVOFS / 2 + i);
 
        for (i = 0; i < 3; i++) {
                unsigned short tmp = ip22_nvram_read(EADDR_NVOFS / 2 + i);
 


@@ -155,17 +155,17 @@ static int __init sgiseeq_devinit(void)
                return 0;
 
        sgimc->giopar |= SGIMC_GIOPAR_MASTEREXP1 | SGIMC_GIOPAR_EXP164 |
                return 0;
 
        sgimc->giopar |= SGIMC_GIOPAR_MASTEREXP1 | SGIMC_GIOPAR_EXP164 |

-                        SGIMC_GIOPAR_HPC264;
+                        SGIMC_GIOPAR_HPC264;

        hpc3c1->pbus_piocfg[0][0] = 0x3ffff;
        /* interrupt/config register on Challenge S Mezz board */
        hpc3c1->pbus_extregs[0][0] = 0x30;
 
        eth1_pd.hpc = hpc3c1;
        eth1_pd.irq = SGI_GIO_0_IRQ;
        hpc3c1->pbus_piocfg[0][0] = 0x3ffff;
        /* interrupt/config register on Challenge S Mezz board */
        hpc3c1->pbus_extregs[0][0] = 0x30;
 
        eth1_pd.hpc = hpc3c1;
        eth1_pd.irq = SGI_GIO_0_IRQ;

-#define EADDR_NVOFS     250
+#define EADDR_NVOFS    250

        for (i = 0; i < 3; i++) {
                unsigned short tmp = ip22_eeprom_read(&hpc3c1->eeprom,
        for (i = 0; i < 3; i++) {
                unsigned short tmp = ip22_eeprom_read(&hpc3c1->eeprom,

-                                                     EADDR_NVOFS / 2 + i);
+                                                     EADDR_NVOFS / 2 + i);

 
                eth1_pd.mac[2 * i]     = tmp >> 8;
                eth1_pd.mac[2 * i + 1] = tmp & 0xff;
 
                eth1_pd.mac[2 * i]     = tmp >> 8;
                eth1_pd.mac[2 * i + 1] = tmp & 0xff;

diff --git a/arch/mips/sgi-ip22/ip22-reset.c b/arch/mips/sgi-ip22/ip22-reset.c
index 20363d29cb5831aea5cf5277f2234ce6f21e1615..063c2dd31e72856fdf83391ddff0721240df6f1b 100644 (file)
--- a/arch/mips/sgi-ip22/ip22-reset.c
+++ b/arch/mips/sgi-ip22/ip22-reset.c
@@ -101,7 +101,7 @@ static void debounce(unsigned long data)
        del_timer(&debounce_timer);
        if (sgint->istat1 & SGINT_ISTAT1_PWR) {
                /* Interrupt still being sent. */
        del_timer(&debounce_timer);
        if (sgint->istat1 & SGINT_ISTAT1_PWR) {
                /* Interrupt still being sent. */

-               debounce_timer.expires = jiffies + (HZ / 20); /* 0.05s  */
+               debounce_timer.expires = jiffies + (HZ / 20); /* 0.05s  */

                add_timer(&debounce_timer);
 
                sgioc->panel = SGIOC_PANEL_POWERON | SGIOC_PANEL_POWERINTR |
                add_timer(&debounce_timer);
 
                sgioc->panel = SGIOC_PANEL_POWERON | SGIOC_PANEL_POWERINTR |


@@ -166,7 +166,7 @@ static irqreturn_t panel_int(int irq, void *dev_id)
 }
 
 static int panic_event(struct notifier_block *this, unsigned long event,
 }
 
 static int panic_event(struct notifier_block *this, unsigned long event,

-                      void *ptr)
+                     void *ptr)

 {
        if (machine_state & MACHINE_PANICED)
                return NOTIFY_DONE;
 {
        if (machine_state & MACHINE_PANICED)
                return NOTIFY_DONE;

diff --git a/arch/mips/sgi-ip22/ip28-berr.c b/arch/mips/sgi-ip22/ip28-berr.c
index 0626555fd1a377eb9d5c1b200207d80ab2baf8db..3f47346608d72b97e0392e2581c6180ab07ceba9 100644 (file)
--- a/arch/mips/sgi-ip22/ip28-berr.c
+++ b/arch/mips/sgi-ip22/ip28-berr.c
@@ -136,14 +136,14 @@ static void save_and_clear_buserr(void)
        hpc3.scsi[1].cbp   = hpc3c0->scsi_chan1.cbptr;
        hpc3.scsi[1].ndptr = hpc3c0->scsi_chan1.ndptr;
 
        hpc3.scsi[1].cbp   = hpc3c0->scsi_chan1.cbptr;
        hpc3.scsi[1].ndptr = hpc3c0->scsi_chan1.ndptr;
 

-       hpc3.ethrx.addr  = (unsigned long)&hpc3c0->ethregs.rx_cbptr;
-       hpc3.ethrx.ctrl  = hpc3c0->ethregs.rx_ctrl; /* HPC3_ERXCTRL_ACTIVE ? */
-       hpc3.ethrx.cbp   = hpc3c0->ethregs.rx_cbptr;
+       hpc3.ethrx.addr  = (unsigned long)&hpc3c0->ethregs.rx_cbptr;
+       hpc3.ethrx.ctrl  = hpc3c0->ethregs.rx_ctrl; /* HPC3_ERXCTRL_ACTIVE ? */
+       hpc3.ethrx.cbp   = hpc3c0->ethregs.rx_cbptr;

        hpc3.ethrx.ndptr = hpc3c0->ethregs.rx_ndptr;
 
        hpc3.ethrx.ndptr = hpc3c0->ethregs.rx_ndptr;
 

-       hpc3.ethtx.addr  = (unsigned long)&hpc3c0->ethregs.tx_cbptr;
-       hpc3.ethtx.ctrl  = hpc3c0->ethregs.tx_ctrl; /* HPC3_ETXCTRL_ACTIVE ? */
-       hpc3.ethtx.cbp   = hpc3c0->ethregs.tx_cbptr;
+       hpc3.ethtx.addr  = (unsigned long)&hpc3c0->ethregs.tx_cbptr;
+       hpc3.ethtx.ctrl  = hpc3c0->ethregs.tx_ctrl; /* HPC3_ETXCTRL_ACTIVE ? */
+       hpc3.ethtx.cbp   = hpc3c0->ethregs.tx_cbptr;

        hpc3.ethtx.ndptr = hpc3c0->ethregs.tx_ndptr;
 
        for (i = 0; i < 8; ++i) {
        hpc3.ethtx.ndptr = hpc3c0->ethregs.tx_ndptr;
 
        for (i = 0; i < 8; ++i) {


@@ -196,11 +196,11 @@ static void print_cache_tags(void)
                        scb | (1 << 12)*i);
        }
        i = read_c0_config();
                        scb | (1 << 12)*i);
        }
        i = read_c0_config();

-       scb = i & (1 << 13) ? 7:6;      /* scblksize = 2^[7..6] */
+       scb = i & (1 << 13) ? 7:6;      /* scblksize = 2^[7..6] */

        scw = ((i >> 16) & 7) + 19 - 1; /* scwaysize = 2^[24..19] / 2 */
 
        i = ((1 << scw) - 1) & ~((1 << scb) - 1);
        scw = ((i >> 16) & 7) + 19 - 1; /* scwaysize = 2^[24..19] / 2 */
 
        i = ((1 << scw) - 1) & ~((1 << scb) - 1);

-       printk(KERN_ERR "S: 0: %08x %08x, 1: %08x %08x  (PA[%u:%u] %05x)\n",
+       printk(KERN_ERR "S: 0: %08x %08x, 1: %08x %08x  (PA[%u:%u] %05x)\n",

                cache_tags.tags[0][0].hi, cache_tags.tags[0][0].lo,
                cache_tags.tags[0][1].hi, cache_tags.tags[0][1].lo,
                scw-1, scb, i & (unsigned)cache_tags.err_addr);
                cache_tags.tags[0][0].hi, cache_tags.tags[0][0].lo,
                cache_tags.tags[0][1].hi, cache_tags.tags[0][1].lo,
                scw-1, scb, i & (unsigned)cache_tags.err_addr);

diff --git a/arch/mips/sgi-ip27/ip27-berr.c b/arch/mips/sgi-ip27/ip27-berr.c
index 04cebadc2b3cf41bece15fdf87af92e4f1dfef0b..692778da9e76505dd3297b15afd3e72a65dc2b6f 100644 (file)
--- a/arch/mips/sgi-ip27/ip27-berr.c
+++ b/arch/mips/sgi-ip27/ip27-berr.c
@@ -39,7 +39,7 @@ static void dump_hub_information(unsigned long errst0, unsigned long errst1)
 
        printk("Hub has valid error information:\n");
        if (errst0 & PI_ERR_ST0_OVERRUN_MASK)
 
        printk("Hub has valid error information:\n");
        if (errst0 & PI_ERR_ST0_OVERRUN_MASK)

-               printk("Overrun is set.  Error stack may contain additional "
+               printk("Overrun is set.  Error stack may contain additional "

                       "information.\n");
        printk("Hub error address is %08lx\n",
               (errst0 & PI_ERR_ST0_ADDR_MASK) >> (PI_ERR_ST0_ADDR_SHFT - 3));
                       "information.\n");
        printk("Hub error address is %08lx\n",
               (errst0 & PI_ERR_ST0_ADDR_MASK) >> (PI_ERR_ST0_ADDR_SHFT - 3));


@@ -85,7 +85,7 @@ void __init ip27_be_init(void)
        board_be_handler = ip27_be_handler;
 
        LOCAL_HUB_S(PI_ERR_INT_PEND,
        board_be_handler = ip27_be_handler;
 
        LOCAL_HUB_S(PI_ERR_INT_PEND,

-                   cpu ? PI_ERR_CLEAR_ALL_B : PI_ERR_CLEAR_ALL_A);
+                   cpu ? PI_ERR_CLEAR_ALL_B : PI_ERR_CLEAR_ALL_A);

        LOCAL_HUB_S(PI_ERR_INT_MASK_A + cpuoff, 0);
        LOCAL_HUB_S(PI_ERR_STACK_ADDR_A + cpuoff, 0);
        LOCAL_HUB_S(PI_ERR_STACK_SIZE, 0);      /* Disable error stack */
        LOCAL_HUB_S(PI_ERR_INT_MASK_A + cpuoff, 0);
        LOCAL_HUB_S(PI_ERR_STACK_ADDR_A + cpuoff, 0);
        LOCAL_HUB_S(PI_ERR_STACK_SIZE, 0);      /* Disable error stack */

diff --git a/arch/mips/sgi-ip27/ip27-hubio.c b/arch/mips/sgi-ip27/ip27-hubio.c
index cd0d5b06cd8385dc9c73d89bcd0fa6691a78622e..328ceb3c86ec00bfc8b18f82689dc24d32fade0e 100644 (file)
--- a/arch/mips/sgi-ip27/ip27-hubio.c
+++ b/arch/mips/sgi-ip27/ip27-hubio.c
@@ -17,11 +17,11 @@
 static int force_fire_and_forget = 1;
 
 /**
 static int force_fire_and_forget = 1;
 
 /**

- * hub_pio_map  -  establish a HUB PIO mapping
+ * hub_pio_map -  establish a HUB PIO mapping

  *
  * @hub:       hub to perform PIO mapping on
  * @widget:    widget ID to perform PIO mapping for
  *
  * @hub:       hub to perform PIO mapping on
  * @widget:    widget ID to perform PIO mapping for

- * @xtalk_addr:        xtalk_address that needs to be mapped
+ * @xtalk_addr: xtalk_address that needs to be mapped

  * @size:      size of the PIO mapping
  *
  **/
  * @size:      size of the PIO mapping
  *
  **/


@@ -78,8 +78,8 @@ unsigned long hub_pio_map(cnodeid_t cnode, xwidgetnum_t widget,
 /*
  * hub_setup_prb(nasid, prbnum, credits, conveyor)
  *
 /*
  * hub_setup_prb(nasid, prbnum, credits, conveyor)
  *

- *     Put a PRB into fire-and-forget mode if conveyor isn't set.  Otherwise,
- *     put it into conveyor belt mode with the specified number of credits.
+ *     Put a PRB into fire-and-forget mode if conveyor isn't set.  Otherwise,
+ *     put it into conveyor belt mode with the specified number of credits.

  */
 static void hub_setup_prb(nasid_t nasid, int prbnum, int credits)
 {
  */
 static void hub_setup_prb(nasid_t nasid, int prbnum, int credits)
 {


@@ -125,12 +125,12 @@ static void hub_setup_prb(nasid_t nasid, int prbnum, int credits)
  * so we turn off access to all widgets for the duration of the function.
  *
  * XXX - This code should really check what kind of widget we're talking
  * so we turn off access to all widgets for the duration of the function.
  *
  * XXX - This code should really check what kind of widget we're talking

- * to.  Bridges can only handle three requests, but XG will do more.
+ * to. Bridges can only handle three requests, but XG will do more.

  * How many can crossbow handle to widget 0?  We're assuming 1.
  *
  * XXX - There is a bug in the crossbow that link reset PIOs do not
  * return write responses.  The easiest solution to this problem is to
  * How many can crossbow handle to widget 0?  We're assuming 1.
  *
  * XXX - There is a bug in the crossbow that link reset PIOs do not
  * return write responses.  The easiest solution to this problem is to

- * leave widget 0 (xbow) in fire-and-forget mode at all times.  This
+ * leave widget 0 (xbow) in fire-and-forget mode at all times. This

  * only affects pio's to xbow registers, which should be rare.
  **/
 static void hub_set_piomode(nasid_t nasid)
  * only affects pio's to xbow registers, which should be rare.
  **/
 static void hub_set_piomode(nasid_t nasid)


@@ -167,7 +167,7 @@ static void hub_set_piomode(nasid_t nasid)
 }
 
 /*
 }
 
 /*

- * hub_pio_init  -  PIO-related hub initialization
+ * hub_pio_init         -  PIO-related hub initialization

  *
  * @hub:       hubinfo structure for our hub
  */
  *
  * @hub:       hubinfo structure for our hub
  */

diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c
index 923c080f77bdf7ef9452cf3063e334cf196010b7..d41b1c6fb0329a2ee6ca7c8b139632c685369dd2 100644 (file)
--- a/arch/mips/sgi-ip27/ip27-init.c
+++ b/arch/mips/sgi-ip27/ip27-init.c
@@ -151,7 +151,7 @@ nasid_t
 get_nasid(void)
 {
        return (nasid_t)((LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_NODEID_MASK)
 get_nasid(void)
 {
        return (nasid_t)((LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_NODEID_MASK)

-                        >> NSRI_NODEID_SHFT);
+                        >> NSRI_NODEID_SHFT);

 }
 
 /*
 }
 
 /*

diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index 69a939ae65e42faacc698d98b310901fad476f85..2315cfeb268790a1b02fbe86575fab7b526d222b 100644 (file)
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -62,7 +62,7 @@ extern int irq_to_slot[];
  * from the irq value
  */
 #define IRQ_TO_BRIDGE(i)               irq_to_bridge[(i)]
  * from the irq value
  */
 #define IRQ_TO_BRIDGE(i)               irq_to_bridge[(i)]

-#define        SLOT_FROM_PCI_IRQ(i)            irq_to_slot[i]
+#define SLOT_FROM_PCI_IRQ(i)           irq_to_slot[i]

 
 static inline int alloc_level(int cpu, int irq)
 {
 
 static inline int alloc_level(int cpu, int irq)
 {


@@ -281,11 +281,11 @@ static unsigned int startup_bridge_irq(struct irq_data *d)
        device |= (pin << (pin*3));
        bridge->b_int_device = device;
 
        device |= (pin << (pin*3));
        bridge->b_int_device = device;
 

-        bridge->b_wid_tflush;
+       bridge->b_wid_tflush;

 
        intr_connect_level(cpu, swlevel);
 
 
        intr_connect_level(cpu, swlevel);
 

-        return 0;       /* Never anything pending.  */
+       return 0;       /* Never anything pending.  */

 }
 
 /* Shutdown one of the (PCI ...) IRQs routes over a bridge.  */
 }
 
 /* Shutdown one of the (PCI ...) IRQs routes over a bridge.  */

diff --git a/arch/mips/sgi-ip27/ip27-memory.c b/arch/mips/sgi-ip27/ip27-memory.c
index cd8fcab6b054e7f6c7293b5c10cd503fc85aab45..3505d08ff2fdd8297848f823b068466331bf9b0a 100644 (file)
--- a/arch/mips/sgi-ip27/ip27-memory.c
+++ b/arch/mips/sgi-ip27/ip27-memory.c
@@ -31,8 +31,8 @@
 #include <asm/sn/sn_private.h>
 
 
 #include <asm/sn/sn_private.h>
 
 

-#define SLOT_PFNSHIFT           (SLOT_SHIFT - PAGE_SHIFT)
-#define PFN_NASIDSHFT           (NASID_SHFT - PAGE_SHIFT)
+#define SLOT_PFNSHIFT          (SLOT_SHIFT - PAGE_SHIFT)
+#define PFN_NASIDSHFT          (NASID_SHFT - PAGE_SHIFT)

 
 struct node_data *__node_data[MAX_COMPACT_NODES];
 
 
 struct node_data *__node_data[MAX_COMPACT_NODES];
 


@@ -43,7 +43,7 @@ static int fine_mode;
 static int is_fine_dirmode(void)
 {
        return (((LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_REGIONSIZE_MASK)
 static int is_fine_dirmode(void)
 {
        return (((LOCAL_HUB_L(NI_STATUS_REV_ID) & NSRI_REGIONSIZE_MASK)

-               >> NSRI_REGIONSIZE_SHFT) & REGIONSIZE_FINE);
+               >> NSRI_REGIONSIZE_SHFT) & REGIONSIZE_FINE);

 }
 
 static hubreg_t get_region(cnodeid_t cnode)
 }
 
 static hubreg_t get_region(cnodeid_t cnode)


@@ -66,7 +66,7 @@ static void gen_region_mask(hubreg_t *region_mask)
        }
 }
 
        }
 }
 

-#define        rou_rflag       rou_flags
+#define rou_rflag      rou_flags

 
 static int router_distance;
 
 
 static int router_distance;
 


@@ -412,7 +412,7 @@ static void __init node_mem_init(cnodeid_t node)
        slot_freepfn += PFN_UP(sizeof(struct pglist_data) +
                               sizeof(struct hub_data));
 
        slot_freepfn += PFN_UP(sizeof(struct pglist_data) +
                               sizeof(struct hub_data));
 

-       bootmap_size = init_bootmem_node(NODE_DATA(node), slot_freepfn,
+       bootmap_size = init_bootmem_node(NODE_DATA(node), slot_freepfn,

                                        start_pfn, end_pfn);
        free_bootmem_with_active_regions(node, end_pfn);
        reserve_bootmem_node(NODE_DATA(node), slot_firstpfn << PAGE_SHIFT,
                                        start_pfn, end_pfn);
        free_bootmem_with_active_regions(node, end_pfn);
        reserve_bootmem_node(NODE_DATA(node), slot_firstpfn << PAGE_SHIFT,


@@ -422,7 +422,7 @@ static void __init node_mem_init(cnodeid_t node)
 }
 
 /*
 }
 
 /*

- * A node with nothing.  We use it to avoid any special casing in
+ * A node with nothing.         We use it to avoid any special casing in

  * cpumask_of_node
  */
 static struct node_data null_node = {
  * cpumask_of_node
  */
 static struct node_data null_node = {

diff --git a/arch/mips/sgi-ip27/ip27-nmi.c b/arch/mips/sgi-ip27/ip27-nmi.c
index 005c29ed419a2110820d3982824ba40eef4182b3..a2358b44420c5ae27b4254f4cba8248ab3c2c2c7 100644 (file)
--- a/arch/mips/sgi-ip27/ip27-nmi.c
+++ b/arch/mips/sgi-ip27/ip27-nmi.c
@@ -54,7 +54,7 @@ void install_cpu_nmi_handler(int slice)
 void nmi_cpu_eframe_save(nasid_t nasid, int slice)
 {
        struct reg_struct *nr;
 void nmi_cpu_eframe_save(nasid_t nasid, int slice)
 {
        struct reg_struct *nr;

-       int             i;
+       int             i;

 
        /* Get the pointer to the current cpu's register set. */
        nr = (struct reg_struct *)
 
        /* Get the pointer to the current cpu's register set. */
        nr = (struct reg_struct *)


@@ -86,12 +86,12 @@ void nmi_cpu_eframe_save(nasid_t nasid, int slice)
        printk("%s\n", print_tainted());
        printk("ErrEPC: %016lx %pS\n", nr->error_epc, (void *) nr->error_epc);
        printk("ra    : %016lx %pS\n", nr->gpr[31], (void *) nr->gpr[31]);
        printk("%s\n", print_tainted());
        printk("ErrEPC: %016lx %pS\n", nr->error_epc, (void *) nr->error_epc);
        printk("ra    : %016lx %pS\n", nr->gpr[31], (void *) nr->gpr[31]);

-       printk("Status: %08lx         ", nr->sr);
+       printk("Status: %08lx         ", nr->sr);

 
        if (nr->sr & ST0_KX)
                printk("KX ");
        if (nr->sr & ST0_SX)
 
        if (nr->sr & ST0_KX)
                printk("KX ");
        if (nr->sr & ST0_SX)

-               printk("SX      ");
+               printk("SX      ");

        if (nr->sr & ST0_UX)
                printk("UX ");
 
        if (nr->sr & ST0_UX)
                printk("UX ");
 

diff --git a/arch/mips/sgi-ip27/ip27-reset.c b/arch/mips/sgi-ip27/ip27-reset.c
index f347bc6b7954b837d077a6a79a061a64db7ab143..ac37e54b3d5e7454fc2c78daf88008655d6b8870 100644 (file)
--- a/arch/mips/sgi-ip27/ip27-reset.c
+++ b/arch/mips/sgi-ip27/ip27-reset.c
@@ -29,7 +29,7 @@ void machine_restart(char *command) __attribute__((noreturn));
 void machine_halt(void) __attribute__((noreturn));
 void machine_power_off(void) __attribute__((noreturn));
 
 void machine_halt(void) __attribute__((noreturn));
 void machine_power_off(void) __attribute__((noreturn));
 

-#define noreturn while(1);                             /* Silence gcc.  */
+#define noreturn while(1);                             /* Silence gcc.  */

 
 /* XXX How to pass the reboot command to the firmware??? */
 static void ip27_machine_restart(char *command)
 
 /* XXX How to pass the reboot command to the firmware??? */
 static void ip27_machine_restart(char *command)

diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c
index 735b43bf8f82eebc8eec907c925b800cf49c544e..f94638141b20ef18f465e36a8a587374693ad67b 100644 (file)
--- a/arch/mips/sgi-ip27/ip27-smp.c
+++ b/arch/mips/sgi-ip27/ip27-smp.c
@@ -191,7 +191,7 @@ static void __init ip27_cpus_done(void)
 }
 
 /*
 }
 
 /*

- * Launch a slave into smp_bootstrap().  It doesn't take an argument, and we
+ * Launch a slave into smp_bootstrap().         It doesn't take an argument, and we

  * set sp to the kernel stack of the newly created idle process, gp to the proc
  * struct so that current_thread_info() will work.
  */
  * set sp to the kernel stack of the newly created idle process, gp to the proc
  * struct so that current_thread_info() will work.
  */


@@ -219,7 +219,7 @@ static void __init ip27_smp_setup(void)
 
        /*
         * Assumption to be fixed: we're always booted on logical / physical
 
        /*
         * Assumption to be fixed: we're always booted on logical / physical

-        * processor 0.  While we're always running on logical processor 0
+        * processor 0.  While we're always running on logical processor 0

         * this still means this is physical processor zero; it might for
         * example be disabled in the firmware.
         */
         * this still means this is physical processor zero; it might for
         * example be disabled in the firmware.
         */

diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index 13cfeab50528e7bdef1e384784ac9b6f7c19f699..fff58ac176f36328914c06801234f1f31c38389c 100644 (file)
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -117,8 +117,8 @@ void __cpuinit hub_rt_clock_event_init(void)
        cd->name                = name;
        cd->features            = CLOCK_EVT_FEAT_ONESHOT;
        clockevent_set_clock(cd, CYCLES_PER_SEC);
        cd->name                = name;
        cd->features            = CLOCK_EVT_FEAT_ONESHOT;
        clockevent_set_clock(cd, CYCLES_PER_SEC);

-       cd->max_delta_ns        = clockevent_delta2ns(0xfffffffffffff, cd);
-       cd->min_delta_ns        = clockevent_delta2ns(0x300, cd);
+       cd->max_delta_ns        = clockevent_delta2ns(0xfffffffffffff, cd);
+       cd->min_delta_ns        = clockevent_delta2ns(0x300, cd);

        cd->rating              = 200;
        cd->irq                 = irq;
        cd->cpumask             = cpumask_of(cpu);
        cd->rating              = 200;
        cd->irq                 = irq;
        cd->cpumask             = cpumask_of(cpu);


@@ -153,7 +153,7 @@ static cycle_t hub_rt_read(struct clocksource *cs)
 
 struct clocksource hub_rt_clocksource = {
        .name   = "HUB-RT",
 
 struct clocksource hub_rt_clocksource = {
        .name   = "HUB-RT",

-       .rating = 200,
+       .rating = 200,

        .read   = hub_rt_read,
        .mask   = CLOCKSOURCE_MASK(52),
        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
        .read   = hub_rt_read,
        .mask   = CLOCKSOURCE_MASK(52),
        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,

diff --git a/arch/mips/sgi-ip27/ip27-xtalk.c b/arch/mips/sgi-ip27/ip27-xtalk.c
index 5e871e75a8d9c3cabd975b4495199d4dbbba079d..a4df7d0f6f12d0811ba457207d4db35d9afbb194 100644 (file)
--- a/arch/mips/sgi-ip27/ip27-xtalk.c
+++ b/arch/mips/sgi-ip27/ip27-xtalk.c
@@ -17,15 +17,15 @@
 #include <asm/xtalk/xtalk.h>
 
 
 #include <asm/xtalk/xtalk.h>
 
 

-#define XBOW_WIDGET_PART_NUM    0x0
-#define XXBOW_WIDGET_PART_NUM   0xd000  /* Xbow in Xbridge */
-#define BASE_XBOW_PORT         8     /* Lowest external port */
+#define XBOW_WIDGET_PART_NUM   0x0
+#define XXBOW_WIDGET_PART_NUM  0xd000  /* Xbow in Xbridge */
+#define BASE_XBOW_PORT         8     /* Lowest external port */

 
 extern int bridge_probe(nasid_t nasid, int widget, int masterwid);
 
 static int __cpuinit probe_one_port(nasid_t nasid, int widget, int masterwid)
 {
 
 extern int bridge_probe(nasid_t nasid, int widget, int masterwid);
 
 static int __cpuinit probe_one_port(nasid_t nasid, int widget, int masterwid)
 {

-       widgetreg_t             widget_id;
+       widgetreg_t             widget_id;

        xwidget_part_num_t      partnum;
 
        widget_id = *(volatile widgetreg_t *)
        xwidget_part_num_t      partnum;
 
        widget_id = *(volatile widgetreg_t *)


@@ -102,10 +102,10 @@ static int __cpuinit xbow_probe(nasid_t nasid)
 
 void __cpuinit xtalk_probe_node(cnodeid_t nid)
 {
 
 void __cpuinit xtalk_probe_node(cnodeid_t nid)
 {

-       volatile u64            hubreg;
-       nasid_t                 nasid;
+       volatile u64            hubreg;
+       nasid_t                 nasid;

        xwidget_part_num_t      partnum;
        xwidget_part_num_t      partnum;

-       widgetreg_t             widget_id;
+       widgetreg_t             widget_id;

 
        nasid = COMPACT_TO_NASID_NODEID(nid);
        hubreg = REMOTE_HUB_L(nasid, IIO_LLP_CSR);
 
        nasid = COMPACT_TO_NASID_NODEID(nid);
        hubreg = REMOTE_HUB_L(nasid, IIO_LLP_CSR);


@@ -115,7 +115,7 @@ void __cpuinit xtalk_probe_node(cnodeid_t nid)
                return;
 
        widget_id = *(volatile widgetreg_t *)
                return;
 
        widget_id = *(volatile widgetreg_t *)

-                       (RAW_NODE_SWIN_BASE(nasid, 0x0) + WIDGET_ID);
+                      (RAW_NODE_SWIN_BASE(nasid, 0x0) + WIDGET_ID);

        partnum = XWIDGET_PART_NUM(widget_id);
 
        printk(KERN_INFO "Cpu %d, Nasid 0x%x: partnum 0x%x is ",
        partnum = XWIDGET_PART_NUM(widget_id);
 
        printk(KERN_INFO "Cpu %d, Nasid 0x%x: partnum 0x%x is ",

diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index e7d5054de8c8cf0d1408d8b5ca31c4db96000d64..e0c7d9e142fa8c3c8b68f86c5990eae2d07506b5 100644 (file)
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -173,7 +173,7 @@ static struct irq_chip crime_edge_interrupt = {
 
 /*
  * This is for MACE PCI interrupts.  We can decrease bus traffic by masking
 
 /*
  * This is for MACE PCI interrupts.  We can decrease bus traffic by masking

- * as close to the source as possible.  This also means we can take the
+ * as close to the source as possible. This also means we can take the

  * next chunk of the CRIME register in one piece.
  */
 
  * next chunk of the CRIME register in one piece.
  */
 


@@ -271,11 +271,11 @@ static void disable_maceisa_irq(struct irq_data *d)
        unsigned int crime_int = 0;
 
        maceisa_mask &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ));
        unsigned int crime_int = 0;
 
        maceisa_mask &= ~(1 << (d->irq - MACEISA_AUDIO_SW_IRQ));

-        if (!(maceisa_mask & MACEISA_AUDIO_INT))
+       if (!(maceisa_mask & MACEISA_AUDIO_INT))

                crime_int |= MACE_AUDIO_INT;
                crime_int |= MACE_AUDIO_INT;

-        if (!(maceisa_mask & MACEISA_MISC_INT))
+       if (!(maceisa_mask & MACEISA_MISC_INT))

                crime_int |= MACE_MISC_INT;
                crime_int |= MACE_MISC_INT;

-        if (!(maceisa_mask & MACEISA_SUPERIO_INT))
+       if (!(maceisa_mask & MACEISA_SUPERIO_INT))

                crime_int |= MACE_SUPERIO_INT;
        crime_mask &= ~crime_int;
        crime->imask = crime_mask;
                crime_int |= MACE_SUPERIO_INT;
        crime_mask &= ~crime_int;
        crime->imask = crime_mask;

diff --git a/arch/mips/sibyte/Platform b/arch/mips/sibyte/Platform
index 911dfe39c631b3fe4f22ff5f1fb220c5ad27f27d..d03a07516f838cd8aabf2563348b9c25d0c7434e 100644 (file)
--- a/arch/mips/sibyte/Platform
+++ b/arch/mips/sibyte/Platform
@@ -9,7 +9,7 @@ platform-$(CONFIG_SIBYTE_BCM1x80)       += sibyte/
 #
 # Sibyte SB1250 / BCM1480 family of SOCs
 #
 #
 # Sibyte SB1250 / BCM1480 family of SOCs
 #

-cflags-$(CONFIG_SIBYTE_BCM112X)        +=                                      \
+cflags-$(CONFIG_SIBYTE_BCM112X) +=                                     \

                -I$(srctree)/arch/mips/include/asm/mach-sibyte          \
                -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
 
                -I$(srctree)/arch/mips/include/asm/mach-sibyte          \
                -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
 


@@ -18,11 +18,11 @@ cflags-$(CONFIG_SIBYTE_SB1250)      +=                                      \
                -I$(srctree)/arch/mips/include/asm/mach-sibyte          \
                -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
 
                -I$(srctree)/arch/mips/include/asm/mach-sibyte          \
                -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1250_112x_ALL
 

-cflags-$(CONFIG_SIBYTE_BCM1x55)        +=                                      \
+cflags-$(CONFIG_SIBYTE_BCM1x55) +=                                     \

                -I$(srctree)/arch/mips/include/asm/mach-sibyte          \
                -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
 
                -I$(srctree)/arch/mips/include/asm/mach-sibyte          \
                -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
 

-cflags-$(CONFIG_SIBYTE_BCM1x80)        +=                                      \
+cflags-$(CONFIG_SIBYTE_BCM1x80) +=                                     \

                -I$(srctree)/arch/mips/include/asm/mach-sibyte          \
                -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
 
                -I$(srctree)/arch/mips/include/asm/mach-sibyte          \
                -DSIBYTE_HDR_FEATURES=SIBYTE_HDR_FMASK_1480_ALL
 

diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 215713e1f3c4a80eb250992404e91da070d11e4a..09d6e16a70f14f0b294f99a4b193862cfde8dcca 100644 (file)
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -283,10 +283,10 @@ void __init arch_init_irq(void)
        for (cpu = 0; cpu < 4; cpu++) {
                __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
                                                 (K_BCM1480_INT_MBOX_0_0 << 3)));
        for (cpu = 0; cpu < 4; cpu++) {
                __raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
                                                 (K_BCM1480_INT_MBOX_0_0 << 3)));

-        }
+       }

 
 
 
 

-       /* Clear the mailboxes.  The firmware may leave them dirty */
+       /* Clear the mailboxes.  The firmware may leave them dirty */

        for (cpu = 0; cpu < 4; cpu++) {
                __raw_writeq(0xffffffffffffffffULL,
                             IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU)));
        for (cpu = 0; cpu < 4; cpu++) {
                __raw_writeq(0xffffffffffffffffULL,
                             IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU)));


@@ -307,7 +307,7 @@ void __init arch_init_irq(void)
 
        /*
         * Note that the timer interrupts are also mapped, but this is
 
        /*
         * Note that the timer interrupts are also mapped, but this is

-        * done in bcm1480_time_init().  Also, the profiling driver
+        * done in bcm1480_time_init().  Also, the profiling driver

         * does its own management of IP7.
         */
 
         * does its own management of IP7.
         */
 


@@ -325,7 +325,7 @@ static inline void dispatch_ip2(void)
 
        /*
         * Default...we've hit an IP[2] interrupt, which means we've got to
 
        /*
         * Default...we've hit an IP[2] interrupt, which means we've got to

-        * check the 1480 interrupt registers to figure out what to do.  Need
+        * check the 1480 interrupt registers to figure out what to do.  Need

         * to detect which CPU we're on, now that smp_affinity is supported.
         */
        base = A_BCM1480_IMR_MAPPER(cpu);
         * to detect which CPU we're on, now that smp_affinity is supported.
         */
        base = A_BCM1480_IMR_MAPPER(cpu);

diff --git a/arch/mips/sibyte/common/cfe.c b/arch/mips/sibyte/common/cfe.c
index 6343011e9902d05060851fa2b6dfa6b4a0a66766..588e1806a1a387a96b5d47686dcb58f0c84b18fc 100644 (file)
--- a/arch/mips/sibyte/common/cfe.c
+++ b/arch/mips/sibyte/common/cfe.c
@@ -127,8 +127,8 @@ static __init void prom_meminit(void)
                                if ((initrd_pstart > addr) &&
                                    (initrd_pstart < (addr + size))) {
                                        add_memory_region(addr,
                                if ((initrd_pstart > addr) &&
                                    (initrd_pstart < (addr + size))) {
                                        add_memory_region(addr,

-                                                         initrd_pstart - addr,
-                                                         BOOT_MEM_RAM);
+                                                         initrd_pstart - addr,
+                                                         BOOT_MEM_RAM);

                                        rd_flag = 1;
                                }
                                if ((initrd_pend > addr) &&
                                        rd_flag = 1;
                                }
                                if ((initrd_pend > addr) &&


@@ -195,7 +195,7 @@ static int __init initrd_setup(char *str)
 
        /*
         *Initrd location comes in the form "<hex size of ramdisk in bytes>@<location in memory>"
 
        /*
         *Initrd location comes in the form "<hex size of ramdisk in bytes>@<location in memory>"

-        *  e.g. initrd=3abfd@80010000.  This is set up by the loader.
+        *  e.g. initrd=3abfd@80010000.  This is set up by the loader.

         */
        for (tmp = str; *tmp != '@'; tmp++) {
                if (!*tmp) {
         */
        for (tmp = str; *tmp != '@'; tmp++) {
                if (!*tmp) {


@@ -244,7 +244,7 @@ void __init prom_init(void)
        int *prom_vec = (int *) fw_arg3;
 
        _machine_restart   = cfe_linux_restart;
        int *prom_vec = (int *) fw_arg3;
 
        _machine_restart   = cfe_linux_restart;

-       _machine_halt      = cfe_linux_halt;
+       _machine_halt      = cfe_linux_halt;

        pm_power_off = cfe_linux_halt;
 
        /*
        pm_power_off = cfe_linux_halt;
 
        /*


@@ -299,7 +299,7 @@ void __init prom_init(void)
 #ifdef CONFIG_BLK_DEV_INITRD
        {
                char *ptr;
 #ifdef CONFIG_BLK_DEV_INITRD
        {
                char *ptr;

-               /* Need to find out early whether we've got an initrd.  So scan
+               /* Need to find out early whether we've got an initrd.  So scan

                   the list looking now */
                for (ptr = arcs_cmdline; *ptr; ptr++) {
                        while (*ptr == ' ') {
                   the list looking now */
                for (ptr = arcs_cmdline; *ptr; ptr++) {
                        while (*ptr == ' ') {

diff --git a/arch/mips/sibyte/common/sb_tbprof.c b/arch/mips/sibyte/common/sb_tbprof.c
index e8c4538c5f610d83040db526ceff7b2a4087b5e0..2188b39a1251a9191409150a65b5650cda527655 100644 (file)
--- a/arch/mips/sibyte/common/sb_tbprof.c
+++ b/arch/mips/sibyte/common/sb_tbprof.c
@@ -152,7 +152,7 @@ static u64 tb_period;
 
 static void arm_tb(void)
 {
 
 static void arm_tb(void)
 {

-        u64 scdperfcnt;
+       u64 scdperfcnt;

        u64 next = (1ULL << 40) - tb_period;
        u64 tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
 
        u64 next = (1ULL << 40) - tb_period;
        u64 tb_options = M_SCD_TRACE_CFG_FREEZE_FULL;
 


@@ -257,8 +257,8 @@ static irqreturn_t sbprof_pc_intr(int irq, void *dev_id)
 
 /*
  * Requires: Already called zclk_timer_init with a value that won't
 
 /*
  * Requires: Already called zclk_timer_init with a value that won't

- *           saturate 40 bits.  No subsequent use of SCD performance counters
- *           or trace buffer.
+ *          saturate 40 bits.  No subsequent use of SCD performance counters
+ *          or trace buffer.

  */
 
 static int sbprof_zbprof_start(struct file *filp)
  */
 
 static int sbprof_zbprof_start(struct file *filp)


@@ -288,8 +288,8 @@ static int sbprof_zbprof_start(struct file *filp)
 
        /*
         * We grab this interrupt to prevent others from trying to use
 
        /*
         * We grab this interrupt to prevent others from trying to use

-         * it, even though we don't want to service the interrupts
-         * (they only feed into the trace-on-interrupt mechanism)
+        * it, even though we don't want to service the interrupts
+        * (they only feed into the trace-on-interrupt mechanism)

         */
        if (request_irq(K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) {
                free_irq(K_INT_TRACE_FREEZE, &sbp);
         */
        if (request_irq(K_INT_PERF_CNT, sbprof_pc_intr, 0, DEVNAME " scd perfcnt", &sbp)) {
                free_irq(K_INT_TRACE_FREEZE, &sbp);


@@ -298,7 +298,7 @@ static int sbprof_zbprof_start(struct file *filp)
 
        /*
         * I need the core to mask these, but the interrupt mapper to
 
        /*
         * I need the core to mask these, but the interrupt mapper to

-        *  pass them through.  I am exploiting my knowledge that
+        *  pass them through.  I am exploiting my knowledge that

         *  cp0_status masks out IP[5]. krw
         */
 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
         *  cp0_status masks out IP[5]. krw
         */
 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)


@@ -328,7 +328,7 @@ static int sbprof_zbprof_start(struct file *filp)
        __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
 
        /* Initialize Trace Event 0-7 */
        __raw_writeq(0, IOADDR(A_ADDR_TRAP_CFG_3));
 
        /* Initialize Trace Event 0-7 */

-       /*                              when interrupt  */
+       /*                              when interrupt  */

        __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
        __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
        __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));
        __raw_writeq(M_SCD_TREVT_INTERRUPT, IOADDR(A_SCD_TRACE_EVENT_0));
        __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_1));
        __raw_writeq(0, IOADDR(A_SCD_TRACE_EVENT_2));


@@ -479,7 +479,7 @@ static ssize_t sbprof_tb_read(struct file *filp, char *buf,
                        return err;
                }
                pr_debug(DEVNAME ": read from sample %d, %d bytes\n",
                        return err;
                }
                pr_debug(DEVNAME ": read from sample %d, %d bytes\n",

-                        cur_sample, cur_count);
+                        cur_sample, cur_count);

                size -= cur_count;
                sample_left -= cur_count;
                if (!sample_left) {
                size -= cur_count;
                sample_left -= cur_count;
                if (!sample_left) {


@@ -540,7 +540,7 @@ static const struct file_operations sbprof_tb_fops = {
        .open           = sbprof_tb_open,
        .release        = sbprof_tb_release,
        .read           = sbprof_tb_read,
        .open           = sbprof_tb_open,
        .release        = sbprof_tb_release,
        .read           = sbprof_tb_read,

-       .unlocked_ioctl = sbprof_tb_ioctl,
+       .unlocked_ioctl = sbprof_tb_ioctl,

        .compat_ioctl   = sbprof_tb_ioctl,
        .mmap           = NULL,
        .llseek         = default_llseek,
        .compat_ioctl   = sbprof_tb_ioctl,
        .mmap           = NULL,
        .llseek         = default_llseek,

diff --git a/arch/mips/sibyte/sb1250/bus_watcher.c b/arch/mips/sibyte/sb1250/bus_watcher.c
index 86e6e54dd15d37b953defddb068e70183bb6788b..e651105b3f0bbc328f12a4aa5c81b052464b7e40 100644 (file)
--- a/arch/mips/sibyte/sb1250/bus_watcher.c
+++ b/arch/mips/sibyte/sb1250/bus_watcher.c
@@ -71,7 +71,7 @@ static void print_summary(uint32_t status, uint32_t l2_err,
  * already been destructively read out of the registers.
  *
  * notes: this is currently used by the cache error handler
  * already been destructively read out of the registers.
  *
  * notes: this is currently used by the cache error handler

- *        should provide locking against the interrupt handler
+ *       should provide locking against the interrupt handler

  */
 void check_bus_watcher(void)
 {
  */
 void check_bus_watcher(void)
 {


@@ -119,7 +119,7 @@ static int bw_print_buffer(char *page, struct bw_stats_struct *stats)
                       (int)G_SCD_BERR_RID(stats->status),
                       (int)G_SCD_BERR_DCODE(stats->status));
        /* XXXKW indicate multiple errors between printings, or stats
                       (int)G_SCD_BERR_RID(stats->status),
                       (int)G_SCD_BERR_DCODE(stats->status));
        /* XXXKW indicate multiple errors between printings, or stats

-           collection (or both)? */
+          collection (or both)? */

        if (stats->status & M_SCD_BERR_MULTERRS)
                len += sprintf(page+len, "Multiple errors observed since last check.\n");
        if (stats->status_printed) {
        if (stats->status & M_SCD_BERR_MULTERRS)
                len += sprintf(page+len, "Multiple errors observed since last check.\n");
        if (stats->status_printed) {


@@ -168,7 +168,7 @@ static void create_proc_decoder(struct bw_stats_struct *stats)
  * sibyte_bw_int - handle bus watcher interrupts and accumulate counts
  *
  * notes: possible re-entry due to multiple sources
  * sibyte_bw_int - handle bus watcher interrupts and accumulate counts
  *
  * notes: possible re-entry due to multiple sources

- *        should check/indicate saturation
+ *       should check/indicate saturation

  */
 static irqreturn_t sibyte_bw_int(int irq, void *data)
 {
  */
 static irqreturn_t sibyte_bw_int(int irq, void *data)
 {

diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 340aaf626659991494d242fc01dbdebb0efda839..fca0cdb99509a3484e11c022a9e4ec00bfda8dd8 100644 (file)
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -264,7 +264,7 @@ void __init arch_init_irq(void)
                     IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
                            (K_INT_MBOX_0 << 3)));
 
                     IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
                            (K_INT_MBOX_0 << 3)));
 

-       /* Clear the mailboxes.  The firmware may leave them dirty */
+       /* Clear the mailboxes.  The firmware may leave them dirty */

        __raw_writeq(0xffffffffffffffffULL,
                     IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
        __raw_writeq(0xffffffffffffffffULL,
        __raw_writeq(0xffffffffffffffffULL,
                     IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
        __raw_writeq(0xffffffffffffffffULL,


@@ -277,7 +277,7 @@ void __init arch_init_irq(void)
 
        /*
         * Note that the timer interrupts are also mapped, but this is
 
        /*
         * Note that the timer interrupts are also mapped, but this is

-        * done in sb1250_time_init().  Also, the profiling driver
+        * done in sb1250_time_init().  Also, the profiling driver

         * does its own management of IP7.
         */
 
         * does its own management of IP7.
         */
 


@@ -294,7 +294,7 @@ static inline void dispatch_ip2(void)
 
        /*
         * Default...we've hit an IP[2] interrupt, which means we've got to
 
        /*
         * Default...we've hit an IP[2] interrupt, which means we've got to

-        * check the 1250 interrupt registers to figure out what to do.  Need
+        * check the 1250 interrupt registers to figure out what to do.  Need

         * to detect which CPU we're on, now that smp_affinity is supported.
         */
        mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,
         * to detect which CPU we're on, now that smp_affinity is supported.
         */
        mask = __raw_readq(IOADDR(A_IMR_REGISTER(cpu,


@@ -323,7 +323,7 @@ asmlinkage void plat_irq_dispatch(void)
        if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
                do_IRQ(MIPS_CPU_IRQ_BASE + 7);
        else if (pending & CAUSEF_IP4)
        if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
                do_IRQ(MIPS_CPU_IRQ_BASE + 7);
        else if (pending & CAUSEF_IP4)

-               do_IRQ(K_INT_TIMER_0 + cpu);    /* sb1250_timer_interrupt() */
+               do_IRQ(K_INT_TIMER_0 + cpu);    /* sb1250_timer_interrupt() */

 
 #ifdef CONFIG_SMP
        else if (pending & CAUSEF_IP3)
 
 #ifdef CONFIG_SMP
        else if (pending & CAUSEF_IP3)

diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c
index 92da3155ce074ac16840c715fde220946a13b4fd..a14bd4cb0bc0cd70fd2468b0cea55ad5ba9da091 100644 (file)
--- a/arch/mips/sibyte/sb1250/setup.c
+++ b/arch/mips/sibyte/sb1250/setup.c
@@ -203,8 +203,8 @@ void __init sb1250_setup(void)
        case K_SYS_REVISION_BCM1250_PASS1:
 #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
                printk("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, "
        case K_SYS_REVISION_BCM1250_PASS1:
 #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS
                printk("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, "

-                           "and the kernel doesn't have the proper "
-                           "workarounds compiled in. @@@@\n");
+                           "and the kernel doesn't have the proper "
+                           "workarounds compiled in. @@@@\n");

                bad_config = 1;
 #endif
                break;
                bad_config = 1;
 #endif
                break;


@@ -213,28 +213,28 @@ void __init sb1250_setup(void)
 #if !defined(CONFIG_SB1_PASS_2_WORKAROUNDS) || \
     !defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS)
                printk("@@@@ This is a BCM1250 A3-A10 board, and the "
 #if !defined(CONFIG_SB1_PASS_2_WORKAROUNDS) || \
     !defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS)
                printk("@@@@ This is a BCM1250 A3-A10 board, and the "

-                           "kernel doesn't have the proper workarounds "
-                           "compiled in. @@@@\n");
+                           "kernel doesn't have the proper workarounds "
+                           "compiled in. @@@@\n");

                bad_config = 1;
 #endif
 #ifdef CONFIG_CPU_HAS_PREFETCH
                printk("@@@@ Prefetches may be enabled in this kernel, "
                bad_config = 1;
 #endif
 #ifdef CONFIG_CPU_HAS_PREFETCH
                printk("@@@@ Prefetches may be enabled in this kernel, "

-                           "but are buggy on this board.  @@@@\n");
+                           "but are buggy on this board.  @@@@\n");

                bad_config = 1;
 #endif
                break;
        case K_SYS_REVISION_BCM1250_PASS2_2:
 #ifndef CONFIG_SB1_PASS_2_WORKAROUNDS
                printk("@@@@ This is a BCM1250 B1/B2. board, and the "
                bad_config = 1;
 #endif
                break;
        case K_SYS_REVISION_BCM1250_PASS2_2:
 #ifndef CONFIG_SB1_PASS_2_WORKAROUNDS
                printk("@@@@ This is a BCM1250 B1/B2. board, and the "

-                           "kernel doesn't have the proper workarounds "
-                           "compiled in. @@@@\n");
+                           "kernel doesn't have the proper workarounds "
+                           "compiled in. @@@@\n");

                bad_config = 1;
 #endif
 #if defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) || \
     !defined(CONFIG_CPU_HAS_PREFETCH)
                printk("@@@@ This is a BCM1250 B1/B2, but the kernel is "
                bad_config = 1;
 #endif
 #if defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) || \
     !defined(CONFIG_CPU_HAS_PREFETCH)
                printk("@@@@ This is a BCM1250 B1/B2, but the kernel is "

-                           "conservatively configured for an 'A' stepping. "
-                           "@@@@\n");
+                           "conservatively configured for an 'A' stepping. "
+                           "@@@@\n");

 #endif
                break;
        default:
 #endif
                break;
        default:

diff --git a/arch/mips/sibyte/swarm/platform.c b/arch/mips/sibyte/swarm/platform.c
index 097335262fb3f3abad4f5850636ee03d67e2c5a5..9480c14ec66a3d5f7f95dff566b7517d38de492a 100644 (file)
--- a/arch/mips/sibyte/swarm/platform.c
+++ b/arch/mips/sibyte/swarm/platform.c
@@ -13,7 +13,7 @@
 
 #define DRV_NAME       "pata-swarm"
 
 
 #define DRV_NAME       "pata-swarm"
 

-#define SWARM_IDE_SHIFT        5
+#define SWARM_IDE_SHIFT 5

 #define SWARM_IDE_BASE 0x1f0
 #define SWARM_IDE_CTRL 0x3f6
 
 #define SWARM_IDE_BASE 0x1f0
 #define SWARM_IDE_CTRL 0x3f6
 


@@ -123,7 +123,7 @@ static int __init sb1250_device_init(void)
        case K_SYS_SOC_TYPE_BCM1120:
        case K_SYS_SOC_TYPE_BCM1125:
        case K_SYS_SOC_TYPE_BCM1125H:
        case K_SYS_SOC_TYPE_BCM1120:
        case K_SYS_SOC_TYPE_BCM1125:
        case K_SYS_SOC_TYPE_BCM1125H:

-       case K_SYS_SOC_TYPE_BCM1250_ALT2:       /* Hybrid */
+       case K_SYS_SOC_TYPE_BCM1250_ALT2:       /* Hybrid */

                ret = platform_add_devices(sb1250_devs, 2);
                break;
        case K_SYS_SOC_TYPE_BCM1x55:
                ret = platform_add_devices(sb1250_devs, 2);
                break;
        case K_SYS_SOC_TYPE_BCM1x55:

diff --git a/arch/mips/sibyte/swarm/rtc_xicor1241.c b/arch/mips/sibyte/swarm/rtc_xicor1241.c
index 4438b2195c4475d8f1b659422d354de78d07e132..178a824b28d4fdb7a889f02d79ae0258f1f90faa 100644 (file)
--- a/arch/mips/sibyte/swarm/rtc_xicor1241.c
+++ b/arch/mips/sibyte/swarm/rtc_xicor1241.c
@@ -4,8 +4,8 @@
  * Copyright (C) 2002 MontaVista Software Inc.
  * Author: jsun@mvista.com or jsun@junsun.net
  *
  * Copyright (C) 2002 MontaVista Software Inc.
  * Author: jsun@mvista.com or jsun@junsun.net
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */


@@ -28,15 +28,15 @@
  * Register bits
  */
 
  * Register bits
  */
 

-#define X1241REG_SR_BAT        0x80            /* currently on battery power */
+#define X1241REG_SR_BAT 0x80           /* currently on battery power */

 #define X1241REG_SR_RWEL 0x04          /* r/w latch is enabled, can write RTC */
 #define X1241REG_SR_WEL 0x02           /* r/w latch is unlocked, can enable r/w now */
 #define X1241REG_SR_RTCF 0x01          /* clock failed */
 #define X1241REG_BL_BP2 0x80           /* block protect 2 */
 #define X1241REG_BL_BP1 0x40           /* block protect 1 */
 #define X1241REG_BL_BP0 0x20           /* block protect 0 */
 #define X1241REG_SR_RWEL 0x04          /* r/w latch is enabled, can write RTC */
 #define X1241REG_SR_WEL 0x02           /* r/w latch is unlocked, can enable r/w now */
 #define X1241REG_SR_RTCF 0x01          /* clock failed */
 #define X1241REG_BL_BP2 0x80           /* block protect 2 */
 #define X1241REG_BL_BP1 0x40           /* block protect 1 */
 #define X1241REG_BL_BP0 0x20           /* block protect 0 */

-#define X1241REG_BL_WD1        0x10
-#define X1241REG_BL_WD0        0x08
+#define X1241REG_BL_WD1 0x10
+#define X1241REG_BL_WD0 0x08

 #define X1241REG_HR_MIL 0x80           /* military time format */
 
 /*
 #define X1241REG_HR_MIL 0x80           /* military time format */
 
 /*


@@ -61,50 +61,50 @@
 
 static int xicor_read(uint8_t addr)
 {
 
 static int xicor_read(uint8_t addr)
 {

-        while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-                ;
+       while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+               ;

 
        __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
        __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA));
        __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
                     SMB_CSR(R_SMB_START));
 
 
        __raw_writeq((addr >> 8) & 0x7, SMB_CSR(R_SMB_CMD));
        __raw_writeq(addr & 0xff, SMB_CSR(R_SMB_DATA));
        __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR2BYTE,
                     SMB_CSR(R_SMB_START));
 

-        while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-                ;
+       while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+               ;

 
        __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
                     SMB_CSR(R_SMB_START));
 
 
        __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_RD1BYTE,
                     SMB_CSR(R_SMB_START));
 

-        while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-                ;
+       while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+               ;

 
 

-        if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
-                /* Clear error bit by writing a 1 */
-                __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
-                return -1;
-        }
+       if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
+               /* Clear error bit by writing a 1 */
+               __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
+               return -1;
+       }

 
        return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
 }
 
 static int xicor_write(uint8_t addr, int b)
 {
 
        return (__raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff);
 }
 
 static int xicor_write(uint8_t addr, int b)
 {

-        while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-                ;
+       while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+               ;

 
        __raw_writeq(addr, SMB_CSR(R_SMB_CMD));
        __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
        __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
                     SMB_CSR(R_SMB_START));
 
 
        __raw_writeq(addr, SMB_CSR(R_SMB_CMD));
        __raw_writeq((addr & 0xff) | ((b & 0xff) << 8), SMB_CSR(R_SMB_DATA));
        __raw_writeq(V_SMB_ADDR(X1241_CCR_ADDRESS) | V_SMB_TT_WR3BYTE,
                     SMB_CSR(R_SMB_START));
 

-        while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
-                ;
+       while (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_BUSY)
+               ;

 
 

-        if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
-                /* Clear error bit by writing a 1 */
-                __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
-                return -1;
-        } else {
+       if (__raw_readq(SMB_CSR(R_SMB_STATUS)) & M_SMB_ERROR) {
+               /* Clear error bit by writing a 1 */
+               __raw_writeq(M_SMB_ERROR, SMB_CSR(R_SMB_STATUS));
+               return -1;
+       } else {

                return 0;
        }
 }
                return 0;
        }
 }

diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c
index 9cb9d43a3a0e6341809f79825ce229423c7acf0d..e250f099374dc64891fa1b42fc05519f14e458b3 100644 (file)
--- a/arch/mips/sni/a20r.c
+++ b/arch/mips/sni/a20r.c
@@ -41,17 +41,17 @@ static struct platform_device a20r_serial8250_device = {
 };
 
 static struct resource a20r_ds1216_rsrc[] = {
 };
 
 static struct resource a20r_ds1216_rsrc[] = {

-        {
-                .start = 0x1c081ffc,
-                .end   = 0x1c081fff,
-                .flags = IORESOURCE_MEM
-        }
+       {
+               .start = 0x1c081ffc,
+               .end   = 0x1c081fff,
+               .flags = IORESOURCE_MEM
+       }

 };
 
 static struct platform_device a20r_ds1216_device = {
 };
 
 static struct platform_device a20r_ds1216_device = {

-        .name           = "rtc-ds1216",
-        .num_resources  = ARRAY_SIZE(a20r_ds1216_rsrc),
-        .resource       = a20r_ds1216_rsrc
+       .name           = "rtc-ds1216",
+       .num_resources  = ARRAY_SIZE(a20r_ds1216_rsrc),
+       .resource       = a20r_ds1216_rsrc

 };
 
 static struct resource snirm_82596_rsrc[] = {
 };
 
 static struct resource snirm_82596_rsrc[] = {


@@ -76,14 +76,14 @@ static struct resource snirm_82596_rsrc[] = {
                .flags = IORESOURCE_IRQ
        },
        {
                .flags = IORESOURCE_IRQ
        },
        {

-               .flags = 0x01                /* 16bit mpu port access */
+               .flags = 0x01                /* 16bit mpu port access */

        }
 };
 
 static struct platform_device snirm_82596_pdev = {
        }
 };
 
 static struct platform_device snirm_82596_pdev = {

-       .name           = "snirm_82596",
-       .num_resources  = ARRAY_SIZE(snirm_82596_rsrc),
-       .resource       = snirm_82596_rsrc
+       .name           = "snirm_82596",
+       .num_resources  = ARRAY_SIZE(snirm_82596_rsrc),
+       .resource       = snirm_82596_rsrc

 };
 
 static struct resource snirm_53c710_rsrc[] = {
 };
 
 static struct resource snirm_53c710_rsrc[] = {


@@ -100,9 +100,9 @@ static struct resource snirm_53c710_rsrc[] = {
 };
 
 static struct platform_device snirm_53c710_pdev = {
 };
 
 static struct platform_device snirm_53c710_pdev = {

-       .name           = "snirm_53c710",
-       .num_resources  = ARRAY_SIZE(snirm_53c710_rsrc),
-       .resource       = snirm_53c710_rsrc
+       .name           = "snirm_53c710",
+       .num_resources  = ARRAY_SIZE(snirm_53c710_rsrc),
+       .resource       = snirm_53c710_rsrc

 };
 
 static struct resource sc26xx_rsrc[] = {
 };
 
 static struct resource sc26xx_rsrc[] = {


@@ -171,7 +171,7 @@ static u32 a20r_ack_hwint(void)
        "       addiu   %1, -1                  \n"
        "       sw      $1, 0(%0)               \n"
        "       sync                            \n"
        "       addiu   %1, -1                  \n"
        "       sw      $1, 0(%0)               \n"
        "       sync                            \n"

-               ".set   pop                     \n"
+               ".set   pop                     \n"

        :
        : "Jr" (PCIMT_UCONF), "Jr" (0xbc000000));
        write_c0_status(status);
        :
        : "Jr" (PCIMT_UCONF), "Jr" (0xbc000000));
        write_c0_status(status);


@@ -236,13 +236,13 @@ static int __init snirm_a20r_setup_devinit(void)
        switch (sni_brd_type) {
        case SNI_BRD_TOWER_OASIC:
        case SNI_BRD_MINITOWER:
        switch (sni_brd_type) {
        case SNI_BRD_TOWER_OASIC:
        case SNI_BRD_MINITOWER:

-               platform_device_register(&snirm_82596_pdev);
-               platform_device_register(&snirm_53c710_pdev);
-               platform_device_register(&sc26xx_pdev);
-               platform_device_register(&a20r_serial8250_device);
-               platform_device_register(&a20r_ds1216_device);
+               platform_device_register(&snirm_82596_pdev);
+               platform_device_register(&snirm_53c710_pdev);
+               platform_device_register(&sc26xx_pdev);
+               platform_device_register(&a20r_serial8250_device);
+               platform_device_register(&a20r_ds1216_device);

                sni_eisa_root_init();
                sni_eisa_root_init();

-               break;
+               break;

        }
        return 0;
 }
        }
        return 0;
 }

diff --git a/arch/mips/sni/eisa.c b/arch/mips/sni/eisa.c
index 6827feb4de9671b7ef72201e55bff0abdffa6329..179b5d556ad2b0edd80232332b18ab29eec09f9e 100644 (file)
--- a/arch/mips/sni/eisa.c
+++ b/arch/mips/sni/eisa.c
@@ -22,7 +22,7 @@ static struct platform_device eisa_root_dev = {
 };
 
 static struct eisa_root_device eisa_bus_root = {
 };
 
 static struct eisa_root_device eisa_bus_root = {

-       .dev           = &eisa_root_dev.dev,
+       .dev           = &eisa_root_dev.dev,

        .bus_base_addr = 0,
        .res           = &ioport_resource,
        .slots         = EISA_MAX_SLOTS,
        .bus_base_addr = 0,
        .res           = &ioport_resource,
        .slots         = EISA_MAX_SLOTS,

diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c
index 5a4ec75382e2eb301e302b5ab658a42ed565a56d..ac61b90bcc66f2cf26b9792444598835cecfdc85 100644 (file)
--- a/arch/mips/sni/irq.c
+++ b/arch/mips/sni/irq.c
@@ -58,25 +58,25 @@ void __init arch_init_irq(void)
        case SNI_BRD_10NEW:
        case SNI_BRD_TOWER_OASIC:
        case SNI_BRD_MINITOWER:
        case SNI_BRD_10NEW:
        case SNI_BRD_TOWER_OASIC:
        case SNI_BRD_MINITOWER:

-               sni_a20r_irq_init();
-               break;
+               sni_a20r_irq_init();
+               break;

 
        case SNI_BRD_PCI_TOWER:
 
        case SNI_BRD_PCI_TOWER:

-               sni_pcit_irq_init();
-               break;
+               sni_pcit_irq_init();
+               break;

 
        case SNI_BRD_PCI_TOWER_CPLUS:
 
        case SNI_BRD_PCI_TOWER_CPLUS:

-               sni_pcit_cplus_irq_init();
-               break;
+               sni_pcit_cplus_irq_init();
+               break;

 
        case SNI_BRD_RM200:
 
        case SNI_BRD_RM200:

-               sni_rm200_irq_init();
-               break;
+               sni_rm200_irq_init();
+               break;

 
        case SNI_BRD_PCI_MTOWER:
        case SNI_BRD_PCI_DESKTOP:
        case SNI_BRD_PCI_MTOWER_CPLUS:
 
        case SNI_BRD_PCI_MTOWER:
        case SNI_BRD_PCI_DESKTOP:
        case SNI_BRD_PCI_MTOWER_CPLUS:

-               sni_pcimt_irq_init();
-               break;
+               sni_pcimt_irq_init();
+               break;

        }
 }
        }
 }

diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index cdb1417fba594feb5f9455c06f6b9123a8734dad..cec4b8ca143817c7c74c422dfa644166359bf420 100644 (file)
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -60,7 +60,7 @@ static inline void sni_pcimt_detect(void)
        p += sprintf(p, "%s PCI", (csmsr & 0x80) ? "RM200" : "RM300");
        if ((csmsr & 0x80) == 0)
                p += sprintf(p, ", board revision %s",
        p += sprintf(p, "%s PCI", (csmsr & 0x80) ? "RM200" : "RM300");
        if ((csmsr & 0x80) == 0)
                p += sprintf(p, ", board revision %s",

-                            (csmsr & 0x20) ? "D" : "C");
+                            (csmsr & 0x20) ? "D" : "C");

        asic = csmsr & 0x80;
        asic = (csmsr & 0x08) ? asic : !asic;
        p += sprintf(p, ", ASIC PCI Rev %s", asic ? "1.0" : "1.1");
        asic = csmsr & 0x80;
        asic = (csmsr & 0x08) ? asic : !asic;
        p += sprintf(p, ", ASIC PCI Rev %s", asic ? "1.0" : "1.1");


@@ -91,22 +91,22 @@ static struct platform_device pcimt_serial8250_device = {
 };
 
 static struct resource pcimt_cmos_rsrc[] = {
 };
 
 static struct resource pcimt_cmos_rsrc[] = {

-        {
-                .start = 0x70,
-                .end   = 0x71,
-                .flags = IORESOURCE_IO
-        },
-        {
-                .start = 8,
-                .end   = 8,
-                .flags = IORESOURCE_IRQ
-        }
+       {
+               .start = 0x70,
+               .end   = 0x71,
+               .flags = IORESOURCE_IO
+       },
+       {
+               .start = 8,
+               .end   = 8,
+               .flags = IORESOURCE_IRQ
+       }

 };
 
 static struct platform_device pcimt_cmos_device = {
 };
 
 static struct platform_device pcimt_cmos_device = {

-        .name           = "rtc_cmos",
-        .num_resources  = ARRAY_SIZE(pcimt_cmos_rsrc),
-        .resource       = pcimt_cmos_rsrc
+       .name           = "rtc_cmos",
+       .num_resources  = ARRAY_SIZE(pcimt_cmos_rsrc),
+       .resource       = pcimt_cmos_rsrc

 };
 
 
 };
 
 


@@ -191,7 +191,7 @@ static struct pci_controller sni_controller = {
        .mem_offset     = 0x00000000UL,
        .io_resource    = &sni_io_resource,
        .io_offset      = 0x00000000UL,
        .mem_offset     = 0x00000000UL,
        .io_resource    = &sni_io_resource,
        .io_offset      = 0x00000000UL,

-       .io_map_base    = SNI_PORT_BASE
+       .io_map_base    = SNI_PORT_BASE

 };
 
 static void enable_pcimt_irq(struct irq_data *d)
 };
 
 static void enable_pcimt_irq(struct irq_data *d)


@@ -319,9 +319,9 @@ static int __init snirm_pcimt_setup_devinit(void)
        case SNI_BRD_PCI_MTOWER:
        case SNI_BRD_PCI_DESKTOP:
        case SNI_BRD_PCI_MTOWER_CPLUS:
        case SNI_BRD_PCI_MTOWER:
        case SNI_BRD_PCI_DESKTOP:
        case SNI_BRD_PCI_MTOWER_CPLUS:

-               platform_device_register(&pcimt_serial8250_device);
-               platform_device_register(&pcimt_cmos_device);
-               break;
+               platform_device_register(&pcimt_serial8250_device);
+               platform_device_register(&pcimt_cmos_device);
+               break;

        }
 
        return 0;
        }
 
        return 0;

diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index b5246373d16bde19b832d49f2acb02b395ab2622..7cddd03d1fea794b5bbdd236761ccdc2e5b6b510 100644 (file)
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -59,22 +59,22 @@ static struct platform_device pcit_cplus_serial8250_device = {
 };
 
 static struct resource pcit_cmos_rsrc[] = {
 };
 
 static struct resource pcit_cmos_rsrc[] = {

-        {
-                .start = 0x70,
-                .end   = 0x71,
-                .flags = IORESOURCE_IO
-        },
-        {
-                .start = 8,
-                .end   = 8,
-                .flags = IORESOURCE_IRQ
-        }
+       {
+               .start = 0x70,
+               .end   = 0x71,
+               .flags = IORESOURCE_IO
+       },
+       {
+               .start = 8,
+               .end   = 8,
+               .flags = IORESOURCE_IRQ
+       }

 };
 
 static struct platform_device pcit_cmos_device = {
 };
 
 static struct platform_device pcit_cmos_device = {

-        .name           = "rtc_cmos",
-        .num_resources  = ARRAY_SIZE(pcit_cmos_rsrc),
-        .resource       = pcit_cmos_rsrc
+       .name           = "rtc_cmos",
+       .num_resources  = ARRAY_SIZE(pcit_cmos_rsrc),
+       .resource       = pcit_cmos_rsrc

 };
 
 static struct platform_device pcit_pcspeaker_pdev = {
 };
 
 static struct platform_device pcit_pcspeaker_pdev = {


@@ -153,7 +153,7 @@ static struct pci_controller sni_pcit_controller = {
        .mem_offset     = 0x00000000UL,
        .io_resource    = &sni_io_resource,
        .io_offset      = 0x00000000UL,
        .mem_offset     = 0x00000000UL,
        .io_resource    = &sni_io_resource,
        .io_offset      = 0x00000000UL,

-       .io_map_base    = SNI_PORT_BASE
+       .io_map_base    = SNI_PORT_BASE

 };
 
 static void enable_pcit_irq(struct irq_data *d)
 };
 
 static void enable_pcit_irq(struct irq_data *d)


@@ -272,16 +272,16 @@ static int __init snirm_pcit_setup_devinit(void)
 {
        switch (sni_brd_type) {
        case SNI_BRD_PCI_TOWER:
 {
        switch (sni_brd_type) {
        case SNI_BRD_PCI_TOWER:

-               platform_device_register(&pcit_serial8250_device);
-               platform_device_register(&pcit_cmos_device);
+               platform_device_register(&pcit_serial8250_device);
+               platform_device_register(&pcit_cmos_device);

                platform_device_register(&pcit_pcspeaker_pdev);
                platform_device_register(&pcit_pcspeaker_pdev);

-               break;
+               break;

 
        case SNI_BRD_PCI_TOWER_CPLUS:
 
        case SNI_BRD_PCI_TOWER_CPLUS:

-               platform_device_register(&pcit_cplus_serial8250_device);
-               platform_device_register(&pcit_cmos_device);
+               platform_device_register(&pcit_cplus_serial8250_device);
+               platform_device_register(&pcit_cmos_device);

                platform_device_register(&pcit_pcspeaker_pdev);
                platform_device_register(&pcit_pcspeaker_pdev);

-               break;
+               break;

        }
        return 0;
 }
        }
        return 0;
 }

diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index 3ab5b5d25b0acca9aeeb2c3306a38af4b8637d89..a046b302623e0dd43d42fc425f58dec843c80db6 100644 (file)
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -48,17 +48,17 @@ static struct platform_device rm200_serial8250_device = {
 };
 
 static struct resource rm200_ds1216_rsrc[] = {
 };
 
 static struct resource rm200_ds1216_rsrc[] = {

-        {
-                .start = 0x1cd41ffc,
-                .end   = 0x1cd41fff,
-                .flags = IORESOURCE_MEM
-        }
+       {
+               .start = 0x1cd41ffc,
+               .end   = 0x1cd41fff,
+               .flags = IORESOURCE_MEM
+       }

 };
 
 static struct platform_device rm200_ds1216_device = {
 };
 
 static struct platform_device rm200_ds1216_device = {

-        .name           = "rtc-ds1216",
-        .num_resources  = ARRAY_SIZE(rm200_ds1216_rsrc),
-        .resource       = rm200_ds1216_rsrc
+       .name           = "rtc-ds1216",
+       .num_resources  = ARRAY_SIZE(rm200_ds1216_rsrc),
+       .resource       = rm200_ds1216_rsrc

 };
 
 static struct resource snirm_82596_rm200_rsrc[] = {
 };
 
 static struct resource snirm_82596_rm200_rsrc[] = {


@@ -88,9 +88,9 @@ static struct resource snirm_82596_rm200_rsrc[] = {
 };
 
 static struct platform_device snirm_82596_rm200_pdev = {
 };
 
 static struct platform_device snirm_82596_rm200_pdev = {

-       .name           = "snirm_82596",
-       .num_resources  = ARRAY_SIZE(snirm_82596_rm200_rsrc),
-       .resource       = snirm_82596_rm200_rsrc
+       .name           = "snirm_82596",
+       .num_resources  = ARRAY_SIZE(snirm_82596_rm200_rsrc),
+       .resource       = snirm_82596_rm200_rsrc

 };
 
 static struct resource snirm_53c710_rm200_rsrc[] = {
 };
 
 static struct resource snirm_53c710_rm200_rsrc[] = {


@@ -107,9 +107,9 @@ static struct resource snirm_53c710_rm200_rsrc[] = {
 };
 
 static struct platform_device snirm_53c710_rm200_pdev = {
 };
 
 static struct platform_device snirm_53c710_rm200_pdev = {

-       .name           = "snirm_53c710",
-       .num_resources  = ARRAY_SIZE(snirm_53c710_rm200_rsrc),
-       .resource       = snirm_53c710_rm200_rsrc
+       .name           = "snirm_53c710",
+       .num_resources  = ARRAY_SIZE(snirm_53c710_rm200_rsrc),
+       .resource       = snirm_53c710_rm200_rsrc

 };
 
 static int __init snirm_setup_devinit(void)
 };
 
 static int __init snirm_setup_devinit(void)


@@ -134,9 +134,9 @@ device_initcall(snirm_setup_devinit);
  */
 
 static DEFINE_RAW_SPINLOCK(sni_rm200_i8259A_lock);
  */
 
 static DEFINE_RAW_SPINLOCK(sni_rm200_i8259A_lock);

-#define PIC_CMD    0x00
-#define PIC_IMR    0x01
-#define PIC_ISR    PIC_CMD
+#define PIC_CMD           0x00
+#define PIC_IMR           0x01
+#define PIC_ISR           PIC_CMD

 #define PIC_POLL   PIC_ISR
 #define PIC_OCW3   PIC_ISR
 
 #define PIC_POLL   PIC_ISR
 #define PIC_OCW3   PIC_ISR
 


@@ -421,8 +421,8 @@ void __init sni_rm200_i8259_irqs(void)
 }
 
 
 }
 
 

-#define SNI_RM200_INT_STAT_REG  CKSEG1ADDR(0xbc000000)
-#define SNI_RM200_INT_ENA_REG   CKSEG1ADDR(0xbc080000)
+#define SNI_RM200_INT_STAT_REG CKSEG1ADDR(0xbc000000)
+#define SNI_RM200_INT_ENA_REG  CKSEG1ADDR(0xbc080000)

 
 #define SNI_RM200_INT_START  24
 #define SNI_RM200_INT_END    28
 
 #define SNI_RM200_INT_START  24
 #define SNI_RM200_INT_END    28

diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c
index 2e9c283b8e688a4907ad8ff674d0d14870beab67..5b09b3544edd156583603d37e3575669f6211fd2 100644 (file)
--- a/arch/mips/sni/setup.c
+++ b/arch/mips/sni/setup.c
@@ -204,23 +204,23 @@ void __init plat_mem_setup(void)
        case SNI_BRD_10NEW:
        case SNI_BRD_TOWER_OASIC:
        case SNI_BRD_MINITOWER:
        case SNI_BRD_10NEW:
        case SNI_BRD_TOWER_OASIC:
        case SNI_BRD_MINITOWER:

-               sni_a20r_init();
-               break;
+               sni_a20r_init();
+               break;

 
        case SNI_BRD_PCI_TOWER:
        case SNI_BRD_PCI_TOWER_CPLUS:
 
        case SNI_BRD_PCI_TOWER:
        case SNI_BRD_PCI_TOWER_CPLUS:

-               sni_pcit_init();
+               sni_pcit_init();

                break;
 
        case SNI_BRD_RM200:
                break;
 
        case SNI_BRD_RM200:

-               sni_rm200_init();
-               break;
+               sni_rm200_init();
+               break;

 
        case SNI_BRD_PCI_MTOWER:
        case SNI_BRD_PCI_DESKTOP:
        case SNI_BRD_PCI_MTOWER_CPLUS:
 
        case SNI_BRD_PCI_MTOWER:
        case SNI_BRD_PCI_DESKTOP:
        case SNI_BRD_PCI_MTOWER_CPLUS:

-               sni_pcimt_init();
-               break;
+               sni_pcimt_init();
+               break;

        }
 
        _machine_restart = sni_machine_restart;
        }
 
        _machine_restart = sni_machine_restart;


@@ -247,16 +247,16 @@ static void quirk_cirrus_ram_size(struct pci_dev *dev)
         */
        pci_read_config_word(dev, PCI_COMMAND, &cmd);
        if ((cmd & (PCI_COMMAND_IO|PCI_COMMAND_MEMORY))
         */
        pci_read_config_word(dev, PCI_COMMAND, &cmd);
        if ((cmd & (PCI_COMMAND_IO|PCI_COMMAND_MEMORY))

-               == (PCI_COMMAND_IO|PCI_COMMAND_MEMORY)) {
-               vga_wseq(NULL, CL_SEQR6, 0x12); /* unlock all extension registers */
+               == (PCI_COMMAND_IO|PCI_COMMAND_MEMORY)) {
+               vga_wseq(NULL, CL_SEQR6, 0x12); /* unlock all extension registers */

                vga_wseq(NULL, CL_SEQRF, 0x18);
        }
 }
 
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_5434_8,
                vga_wseq(NULL, CL_SEQRF, 0x18);
        }
 }
 
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_5434_8,

-                        quirk_cirrus_ram_size);
+                       quirk_cirrus_ram_size);

 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_5436,
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_5436,

-                        quirk_cirrus_ram_size);
+                       quirk_cirrus_ram_size);

 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_5446,
 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CIRRUS_5446,

-                        quirk_cirrus_ram_size);
+                       quirk_cirrus_ram_size);

 #endif
 #endif

diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c
index 494c9e7847aa173bd2ff7c395cb538385106ba9b..cf8ec568b9dfad3eb820826cfd1ae7ddfcf096a2 100644 (file)
--- a/arch/mips/sni/time.c
+++ b/arch/mips/sni/time.c
@@ -10,12 +10,12 @@
 #include <asm/time.h>
 #include <asm-generic/rtc.h>
 
 #include <asm/time.h>
 #include <asm-generic/rtc.h>
 

-#define SNI_CLOCK_TICK_RATE     3686400
-#define SNI_COUNTER2_DIV        64
-#define SNI_COUNTER0_DIV        ((SNI_CLOCK_TICK_RATE / SNI_COUNTER2_DIV) / HZ)
+#define SNI_CLOCK_TICK_RATE    3686400
+#define SNI_COUNTER2_DIV       64
+#define SNI_COUNTER0_DIV       ((SNI_CLOCK_TICK_RATE / SNI_COUNTER2_DIV) / HZ)

 
 static void a20r_set_mode(enum clock_event_mode mode,
 
 static void a20r_set_mode(enum clock_event_mode mode,

-                          struct clock_event_device *evt)
+                         struct clock_event_device *evt)

 {
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:
 {
        switch (mode) {
        case CLOCK_EVT_MODE_PERIODIC:


@@ -33,14 +33,14 @@ static void a20r_set_mode(enum clock_event_mode mode,
                *(volatile u8 *)(A20R_PT_CLOCK_BASE +  8) = SNI_COUNTER2_DIV >> 8;
                wmb();
 
                *(volatile u8 *)(A20R_PT_CLOCK_BASE +  8) = SNI_COUNTER2_DIV >> 8;
                wmb();
 

-                break;
-        case CLOCK_EVT_MODE_ONESHOT:
-        case CLOCK_EVT_MODE_UNUSED:
-        case CLOCK_EVT_MODE_SHUTDOWN:
-                break;
-        case CLOCK_EVT_MODE_RESUME:
-                break;
-        }
+               break;
+       case CLOCK_EVT_MODE_ONESHOT:
+       case CLOCK_EVT_MODE_UNUSED:
+       case CLOCK_EVT_MODE_SHUTDOWN:
+               break;
+       case CLOCK_EVT_MODE_RESUME:
+               break;
+       }

 }
 
 static struct clock_event_device a20r_clockevent_device = {
 }
 
 static struct clock_event_device a20r_clockevent_device = {


@@ -82,15 +82,15 @@ static void __init sni_a20r_timer_setup(void)
        struct irqaction *action = &a20r_irqaction;
        unsigned int cpu = smp_processor_id();
 
        struct irqaction *action = &a20r_irqaction;
        unsigned int cpu = smp_processor_id();
 

-       cd->cpumask             = cpumask_of(cpu);
+       cd->cpumask             = cpumask_of(cpu);

        clockevents_register_device(cd);
        action->dev_id = cd;
        setup_irq(SNI_A20R_IRQ_TIMER, &a20r_irqaction);
 }
 
        clockevents_register_device(cd);
        action->dev_id = cd;
        setup_irq(SNI_A20R_IRQ_TIMER, &a20r_irqaction);
 }
 

-#define SNI_8254_TICK_RATE        1193182UL
+#define SNI_8254_TICK_RATE       1193182UL

 
 

-#define SNI_8254_TCSAMP_COUNTER   ((SNI_8254_TICK_RATE / HZ) + 255)
+#define SNI_8254_TCSAMP_COUNTER          ((SNI_8254_TICK_RATE / HZ) + 255)

 
 static __init unsigned long dosample(void)
 {
 
 static __init unsigned long dosample(void)
 {

diff --git a/arch/mips/txx9/Platform b/arch/mips/txx9/Platform
index a801abbe138b129bc3b2ea63e15215ec5589b7d3..a176d1fd579917dae91f030c4bad87871b57929e 100644 (file)
--- a/arch/mips/txx9/Platform
+++ b/arch/mips/txx9/Platform
@@ -6,5 +6,5 @@ cflags-$(CONFIG_MACH_TX39XX)    +=                                      \
 cflags-$(CONFIG_MACH_TX49XX)   +=                                      \
                 -I$(srctree)/arch/mips/include/asm/mach-tx49xx
 
 cflags-$(CONFIG_MACH_TX49XX)   +=                                      \
                 -I$(srctree)/arch/mips/include/asm/mach-tx49xx
 

-load-$(CONFIG_MACH_TX39XX)      += 0xffffffff80050000
-load-$(CONFIG_MACH_TX49XX)      += 0xffffffff80100000
+load-$(CONFIG_MACH_TX39XX)     += 0xffffffff80050000
+load-$(CONFIG_MACH_TX49XX)     += 0xffffffff80100000

diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c
index 7e3ac5782da433003a3d8d59f0ef4f1d8e43a5fe..ed8e702d448e90baef5981145b52ab33bd5b1a54 100644 (file)
--- a/arch/mips/txx9/generic/irq_tx4927.c
+++ b/arch/mips/txx9/generic/irq_tx4927.c
@@ -2,7 +2,7 @@
  * Common tx4927 irq handler
  *
  * Author: MontaVista Software, Inc.
  * Common tx4927 irq handler
  *
  * Author: MontaVista Software, Inc.

- *         source@mvista.com
+ *        source@mvista.com

  *
  *  under the terms of the GNU General Public License as published by the
  *  Free Software Foundation; either version 2 of the License, or (at your
  *
  *  under the terms of the GNU General Public License as published by the
  *  Free Software Foundation; either version 2 of the License, or (at your

diff --git a/arch/mips/txx9/generic/irq_tx4939.c b/arch/mips/txx9/generic/irq_tx4939.c
index 6b067dbd2ae1bc5d5e2d1a45cd81c380745b4ff7..0d7267e81a8c76d9e34ffad24a09aaaff9aeebbb 100644 (file)
--- a/arch/mips/txx9/generic/irq_tx4939.c
+++ b/arch/mips/txx9/generic/irq_tx4939.c
@@ -5,8 +5,8 @@
  *
  * Copyright 2001, 2003-2005 MontaVista Software Inc.
  * Author: MontaVista Software, Inc.
  *
  * Copyright 2001, 2003-2005 MontaVista Software Inc.
  * Author: MontaVista Software, Inc.

- *         ahennessy@mvista.com
- *         source@mvista.com
+ *        ahennessy@mvista.com
+ *        source@mvista.com

  * Copyright (C) 2000-2001,2005-2007 Toshiba Corporation
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * Copyright (C) 2000-2001,2005-2007 Toshiba Corporation
  *
  * This file is subject to the terms and conditions of the GNU General Public

diff --git a/arch/mips/txx9/generic/mem_tx4927.c b/arch/mips/txx9/generic/mem_tx4927.c
index 70f9626f8227bacc296c600e444441392f8c9ba4..deea2ceae8a76db70ff0d7c85c6dcc7257a3a5e0 100644 (file)
--- a/arch/mips/txx9/generic/mem_tx4927.c
+++ b/arch/mips/txx9/generic/mem_tx4927.c
@@ -2,7 +2,7 @@
  * common tx4927 memory interface
  *
  * Author: MontaVista Software, Inc.
  * common tx4927 memory interface
  *
  * Author: MontaVista Software, Inc.

- *         source@mvista.com
+ *        source@mvista.com

  *
  * Copyright 2001-2002 MontaVista Software Inc.
  *
  *
  * Copyright 2001-2002 MontaVista Software Inc.
  *

diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c
index ce8f8b9b930cabf88df93cf8da95df820436cd51..28713274e0ccfed086667422a5fcfe4dd924ae9f 100644 (file)
--- a/arch/mips/txx9/generic/pci.c
+++ b/arch/mips/txx9/generic/pci.c
@@ -2,7 +2,7 @@
  * linux/arch/mips/txx9/pci.c
  *
  * Based on linux/arch/mips/txx9/rbtx4927/setup.c,
  * linux/arch/mips/txx9/pci.c
  *
  * Based on linux/arch/mips/txx9/rbtx4927/setup.c,

- *          linux/arch/mips/txx9/rbtx4938/setup.c,
+ *         linux/arch/mips/txx9/rbtx4938/setup.c,

  *         and RBTX49xx patch from CELF patch archive.
  *
  * Copyright 2001-2005 MontaVista Software Inc.
  *         and RBTX49xx patch from CELF patch archive.
  *
  * Copyright 2001-2005 MontaVista Software Inc.


@@ -107,7 +107,7 @@ int txx9_pci_mem_high __initdata;
 
 /*
  * allocate pci_controller and resources.
 
 /*
  * allocate pci_controller and resources.

- * mem_base, io_base: physical address.  0 for auto assignment.
+ * mem_base, io_base: physical address.         0 for auto assignment.

  * mem_size and io_size means max size on auto assignment.
  * pcic must be &txx9_primary_pcic or NULL.
  */
  * mem_size and io_size means max size on auto assignment.
  * pcic must be &txx9_primary_pcic or NULL.
  */

diff --git a/arch/mips/txx9/generic/setup_tx3927.c b/arch/mips/txx9/generic/setup_tx3927.c
index 9505d58454c884af631e0ad812bb6267f71de6e9..110e05c3eb8fb638c1b75dbeb68db81d96a26e50 100644 (file)
--- a/arch/mips/txx9/generic/setup_tx3927.c
+++ b/arch/mips/txx9/generic/setup_tx3927.c
@@ -132,6 +132,6 @@ void __init tx3927_mtd_init(int ch)
        unsigned long size = txx9_ce_res[ch].end - start + 1;
 
        if (!(tx3927_romcptr->cr[ch] & 0x8))
        unsigned long size = txx9_ce_res[ch].end - start + 1;
 
        if (!(tx3927_romcptr->cr[ch] & 0x8))

-               return; /* disabled */
+               return; /* disabled */

        txx9_physmap_flash_init(ch, start, size, &pdata);
 }
        txx9_physmap_flash_init(ch, start, size, &pdata);
 }

diff --git a/arch/mips/txx9/generic/setup_tx4927.c b/arch/mips/txx9/generic/setup_tx4927.c
index 3418b2a90f7ec3e7265b3ccb1c8241c5ba77f7de..e714d6ce9a824e8c24b81278e57a0a426b2f796f 100644 (file)
--- a/arch/mips/txx9/generic/setup_tx4927.c
+++ b/arch/mips/txx9/generic/setup_tx4927.c
@@ -250,7 +250,7 @@ void __init tx4927_mtd_init(int ch)
        unsigned long size = txx9_ce_res[ch].end - start + 1;
 
        if (!(TX4927_EBUSC_CR(ch) & 0x8))
        unsigned long size = txx9_ce_res[ch].end - start + 1;
 
        if (!(TX4927_EBUSC_CR(ch) & 0x8))

-               return; /* disabled */
+               return; /* disabled */

        txx9_physmap_flash_init(ch, start, size, &pdata);
 }
 
        txx9_physmap_flash_init(ch, start, size, &pdata);
 }
 

diff --git a/arch/mips/txx9/generic/setup_tx4938.c b/arch/mips/txx9/generic/setup_tx4938.c
index eb20801102396283aebb1b618e336b95ff3d94f8..0a3bf2dfaba1cc8dc9350abfe9090c944e297e17 100644 (file)
--- a/arch/mips/txx9/generic/setup_tx4938.c
+++ b/arch/mips/txx9/generic/setup_tx4938.c
@@ -329,7 +329,7 @@ void __init tx4938_mtd_init(int ch)
        unsigned long size = txx9_ce_res[ch].end - start + 1;
 
        if (!(TX4938_EBUSC_CR(ch) & 0x8))
        unsigned long size = txx9_ce_res[ch].end - start + 1;
 
        if (!(TX4938_EBUSC_CR(ch) & 0x8))

-               return; /* disabled */
+               return; /* disabled */

        txx9_physmap_flash_init(ch, start, size, &pdata);
 }
 
        txx9_physmap_flash_init(ch, start, size, &pdata);
 }
 

diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c
index 5ff7a9584daf4d4c9cc1fa9c14ae126319a0279d..729a50991780f7e6aceb022012e4278993c5a6a7 100644 (file)
--- a/arch/mips/txx9/generic/setup_tx4939.c
+++ b/arch/mips/txx9/generic/setup_tx4939.c
@@ -301,7 +301,7 @@ void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask)
        unsigned int ch_mask = 0;
        __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
 
        unsigned int ch_mask = 0;
        __u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
 

-       cts_mask |= ~1; /* only SIO0 have RTS/CTS */
+       cts_mask |= ~1; /* only SIO0 have RTS/CTS */

        if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO0)
                cts_mask |= 1 << 0; /* disable SIO0 RTS/CTS by PCFG setting */
        if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2)
        if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO0)
                cts_mask |= 1 << 0; /* disable SIO0 RTS/CTS by PCFG setting */
        if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2)


@@ -378,7 +378,7 @@ void __init tx4939_mtd_init(int ch)
        unsigned long size = txx9_ce_res[ch].end - start + 1;
 
        if (!(TX4939_EBUSC_CR(ch) & 0x8))
        unsigned long size = txx9_ce_res[ch].end - start + 1;
 
        if (!(TX4939_EBUSC_CR(ch) & 0x8))

-               return; /* disabled */
+               return; /* disabled */

        txx9_physmap_flash_init(ch, start, size, &pdata);
 }
 
        txx9_physmap_flash_init(ch, start, size, &pdata);
 }
 

diff --git a/arch/mips/txx9/generic/smsc_fdc37m81x.c b/arch/mips/txx9/generic/smsc_fdc37m81x.c
index 8ebc3848f3ac86e2b194b745aabe5a1099a40105..f98baa6263d244253d69916644dda4051df10a1b 100644 (file)
--- a/arch/mips/txx9/generic/smsc_fdc37m81x.c
+++ b/arch/mips/txx9/generic/smsc_fdc37m81x.c
@@ -18,40 +18,40 @@
 /* Common Registers */
 #define SMSC_FDC37M81X_CONFIG_INDEX  0x00
 #define SMSC_FDC37M81X_CONFIG_DATA   0x01
 /* Common Registers */
 #define SMSC_FDC37M81X_CONFIG_INDEX  0x00
 #define SMSC_FDC37M81X_CONFIG_DATA   0x01

-#define SMSC_FDC37M81X_CONF          0x02
-#define SMSC_FDC37M81X_INDEX         0x03
-#define SMSC_FDC37M81X_DNUM          0x07
-#define SMSC_FDC37M81X_DID           0x20
-#define SMSC_FDC37M81X_DREV          0x21
-#define SMSC_FDC37M81X_PCNT          0x22
-#define SMSC_FDC37M81X_PMGT          0x23
-#define SMSC_FDC37M81X_OSC           0x24
-#define SMSC_FDC37M81X_CONFPA0       0x26
-#define SMSC_FDC37M81X_CONFPA1       0x27
-#define SMSC_FDC37M81X_TEST4         0x2B
-#define SMSC_FDC37M81X_TEST5         0x2C
-#define SMSC_FDC37M81X_TEST1         0x2D
-#define SMSC_FDC37M81X_TEST2         0x2E
-#define SMSC_FDC37M81X_TEST3         0x2F
+#define SMSC_FDC37M81X_CONF         0x02
+#define SMSC_FDC37M81X_INDEX        0x03
+#define SMSC_FDC37M81X_DNUM         0x07
+#define SMSC_FDC37M81X_DID          0x20
+#define SMSC_FDC37M81X_DREV         0x21
+#define SMSC_FDC37M81X_PCNT         0x22
+#define SMSC_FDC37M81X_PMGT         0x23
+#define SMSC_FDC37M81X_OSC          0x24
+#define SMSC_FDC37M81X_CONFPA0      0x26
+#define SMSC_FDC37M81X_CONFPA1      0x27
+#define SMSC_FDC37M81X_TEST4        0x2B
+#define SMSC_FDC37M81X_TEST5        0x2C
+#define SMSC_FDC37M81X_TEST1        0x2D
+#define SMSC_FDC37M81X_TEST2        0x2E
+#define SMSC_FDC37M81X_TEST3        0x2F

 
 /* Logical device numbers */
 
 /* Logical device numbers */

-#define SMSC_FDC37M81X_FDD           0x00
-#define SMSC_FDC37M81X_SERIAL1       0x04
-#define SMSC_FDC37M81X_SERIAL2       0x05
-#define SMSC_FDC37M81X_KBD           0x07
+#define SMSC_FDC37M81X_FDD          0x00
+#define SMSC_FDC37M81X_SERIAL1      0x04
+#define SMSC_FDC37M81X_SERIAL2      0x05
+#define SMSC_FDC37M81X_KBD          0x07

 
 /* Logical device Config Registers */
 
 /* Logical device Config Registers */

-#define SMSC_FDC37M81X_ACTIVE        0x30
+#define SMSC_FDC37M81X_ACTIVE       0x30

 #define SMSC_FDC37M81X_BASEADDR0     0x60
 #define SMSC_FDC37M81X_BASEADDR1     0x61
 #define SMSC_FDC37M81X_BASEADDR0     0x60
 #define SMSC_FDC37M81X_BASEADDR1     0x61

-#define SMSC_FDC37M81X_INT           0x70
-#define SMSC_FDC37M81X_INT2          0x72
-#define SMSC_FDC37M81X_MODE          0xF0
+#define SMSC_FDC37M81X_INT          0x70
+#define SMSC_FDC37M81X_INT2         0x72
+#define SMSC_FDC37M81X_MODE         0xF0

 
 /* Chip Config Values */
 #define SMSC_FDC37M81X_CONFIG_ENTER  0x55
 #define SMSC_FDC37M81X_CONFIG_EXIT   0xaa
 
 /* Chip Config Values */
 #define SMSC_FDC37M81X_CONFIG_ENTER  0x55
 #define SMSC_FDC37M81X_CONFIG_EXIT   0xaa

-#define SMSC_FDC37M81X_CHIP_ID       0x4d
+#define SMSC_FDC37M81X_CHIP_ID      0x4d

 
 static unsigned long g_smsc_fdc37m81x_base;
 
 
 static unsigned long g_smsc_fdc37m81x_base;
 

diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c
index 6c22c496090b10ae249e90664dc7d1ad70350cf6..3f48292c9c6c97771d7a6d676126872cff712858 100644 (file)
--- a/arch/mips/txx9/rbtx4927/irq.c
+++ b/arch/mips/txx9/rbtx4927/irq.c
@@ -2,7 +2,7 @@
  * Toshiba RBTX4927 specific interrupt handlers
  *
  * Author: MontaVista Software, Inc.
  * Toshiba RBTX4927 specific interrupt handlers
  *
  * Author: MontaVista Software, Inc.

- *         source@mvista.com
+ *        source@mvista.com

  *
  * Copyright 2001-2002 MontaVista Software Inc.
  *
  *
  * Copyright 2001-2002 MontaVista Software Inc.
  *

diff --git a/arch/mips/txx9/rbtx4927/prom.c b/arch/mips/txx9/rbtx4927/prom.c
index cc97c6a6011b0109a67e92c559d9d262e39a17e7..fe6d0b54763fc2605167575b22b5f55ac2132e15 100644 (file)
--- a/arch/mips/txx9/rbtx4927/prom.c
+++ b/arch/mips/txx9/rbtx4927/prom.c
@@ -2,7 +2,7 @@
  * rbtx4927 specific prom routines
  *
  * Author: MontaVista Software, Inc.
  * rbtx4927 specific prom routines
  *
  * Author: MontaVista Software, Inc.

- *         source@mvista.com
+ *        source@mvista.com

  *
  * Copyright 2001-2002 MontaVista Software Inc.
  *
  *
  * Copyright 2001-2002 MontaVista Software Inc.
  *

diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
index b15adfc2d7264e81271147759f80096c1624b2ac..3c516ef625e57d2da5aee577917dd1e5d1ee318b 100644 (file)
--- a/arch/mips/txx9/rbtx4927/setup.c
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -2,7 +2,7 @@
  * Toshiba rbtx4927 specific setup
  *
  * Author: MontaVista Software, Inc.
  * Toshiba rbtx4927 specific setup
  *
  * Author: MontaVista Software, Inc.

- *         source@mvista.com
+ *        source@mvista.com

  *
  * Copyright 2001-2002 MontaVista Software Inc.
  *
  *
  * Copyright 2001-2002 MontaVista Software Inc.
  *

diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c
index d6e70dab3bd3b064e052850ae2c72aad8e1768b2..c9afd05020e06ceac14c2f2c92d8b3ae50f05a30 100644 (file)
--- a/arch/mips/txx9/rbtx4938/setup.c
+++ b/arch/mips/txx9/rbtx4938/setup.c
@@ -107,10 +107,10 @@ static void __init rbtx4938_pci_setup(void)
 /* SPI support */
 
 /* chip select for SPI devices */
 /* SPI support */
 
 /* chip select for SPI devices */

-#define        SEEPROM1_CS     7       /* PIO7 */
-#define        SEEPROM2_CS     0       /* IOC */
-#define        SEEPROM3_CS     1       /* IOC */
-#define        SRTC_CS 2       /* IOC */
+#define SEEPROM1_CS    7       /* PIO7 */
+#define SEEPROM2_CS    0       /* IOC */
+#define SEEPROM3_CS    1       /* IOC */
+#define SRTC_CS 2      /* IOC */

 #define SPI_BUSNO      0
 
 static int __init rbtx4938_ethaddr_init(void)
 #define SPI_BUSNO      0
 
 static int __init rbtx4938_ethaddr_init(void)

diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c
index e15641d930922403743cec832774bc347dd06511..2da5f25f98bc5a37869429f790fbf47bb35159ed 100644 (file)
--- a/arch/mips/txx9/rbtx4939/setup.c
+++ b/arch/mips/txx9/rbtx4939/setup.c
@@ -243,7 +243,7 @@ static int __init rbtx4939_led_probe(struct platform_device *pdev)
 }
 
 static struct platform_driver rbtx4939_led_driver = {
 }
 
 static struct platform_driver rbtx4939_led_driver = {

-       .driver  = {
+       .driver  = {

                .name = "rbtx4939-led",
                .owner = THIS_MODULE,
        },
                .name = "rbtx4939-led",
                .owner = THIS_MODULE,
        },


@@ -337,7 +337,7 @@ static void rbtx4939_flash_copy_from(struct map_info *map, void *to,
                shift = bdipsw & 3;
                while (len) {
                        curlen = min_t(unsigned long, len,
                shift = bdipsw & 3;
                while (len) {
                        curlen = min_t(unsigned long, len,

-                                    0x400000 - (from & (0x400000 - 1)));
+                                    0x400000 - (from & (0x400000 - 1)));

                        memcpy(to,
                               (void *)((from & ~0xc00000) |
                                        ((((from >> 22) + shift) & 3) << 22)),
                        memcpy(to,
                               (void *)((from & ~0xc00000) |
                                        ((((from >> 22) + shift) & 3) << 22)),

diff --git a/arch/mips/vr41xx/common/bcu.c b/arch/mips/vr41xx/common/bcu.c
index 6346c59c9f9d96d361396944c4e40e4fb20052e6..ff7d1c66cf824f40a61bd23ac2086a963577872e 100644 (file)
--- a/arch/mips/vr41xx/common/bcu.c
+++ b/arch/mips/vr41xx/common/bcu.c
@@ -1,7 +1,7 @@
 /*
  *  bcu.c, Bus Control Unit routines for the NEC VR4100 series.
  *
 /*
  *  bcu.c, Bus Control Unit routines for the NEC VR4100 series.
  *

- *  Copyright (C) 2002  MontaVista Software Inc.
+ *  Copyright (C) 2002 MontaVista Software Inc.

  *    Author: Yoichi Yuasa <source@mvista.com>
  *  Copyright (C) 2003-2005  Yoichi Yuasa <yuasa@linux-mips.org>
  *
  *    Author: Yoichi Yuasa <source@mvista.com>
  *  Copyright (C) 2003-2005  Yoichi Yuasa <yuasa@linux-mips.org>
  *


@@ -176,7 +176,7 @@ static inline unsigned long calculate_vtclock(uint16_t clkspeed, unsigned long p
 }
 
 static inline unsigned long calculate_tclock(uint16_t clkspeed, unsigned long pclock,
 }
 
 static inline unsigned long calculate_tclock(uint16_t clkspeed, unsigned long pclock,

-                                             unsigned long vtclock)
+                                            unsigned long vtclock)

 {
        unsigned long tclock = 0;
 
 {
        unsigned long tclock = 0;
 

diff --git a/arch/mips/vr41xx/common/cmu.c b/arch/mips/vr41xx/common/cmu.c
index 8ba7d04a5ec58e4b05cf1d792eb766698b66e850..05302bfdd1144bc4a768a2c0b26fbd94c9fbf0ec 100644 (file)
--- a/arch/mips/vr41xx/common/cmu.c
+++ b/arch/mips/vr41xx/common/cmu.c
@@ -217,24 +217,24 @@ static int __init vr41xx_cmu_init(void)
        unsigned long start, size;
 
        switch (current_cpu_type()) {
        unsigned long start, size;
 
        switch (current_cpu_type()) {

-        case CPU_VR4111:
-        case CPU_VR4121:
+       case CPU_VR4111:
+       case CPU_VR4121:

                start = CMU_TYPE1_BASE;
                size = CMU_TYPE1_SIZE;
                start = CMU_TYPE1_BASE;
                size = CMU_TYPE1_SIZE;

-                break;
-        case CPU_VR4122:
-        case CPU_VR4131:
+               break;
+       case CPU_VR4122:
+       case CPU_VR4131:

                start = CMU_TYPE2_BASE;
                size = CMU_TYPE2_SIZE;
                break;
                start = CMU_TYPE2_BASE;
                size = CMU_TYPE2_SIZE;
                break;

-        case CPU_VR4133:
+       case CPU_VR4133:

                start = CMU_TYPE3_BASE;
                size = CMU_TYPE3_SIZE;
                start = CMU_TYPE3_BASE;
                size = CMU_TYPE3_SIZE;

-                break;
+               break;

        default:
                panic("Unexpected CPU of NEC VR4100 series");
                break;
        default:
                panic("Unexpected CPU of NEC VR4100 series");
                break;

-        }
+       }

 
        if (request_mem_region(start, size, "CMU") == NULL)
                return -EBUSY;
 
        if (request_mem_region(start, size, "CMU") == NULL)
                return -EBUSY;

diff --git a/arch/mips/vr41xx/common/giu.c b/arch/mips/vr41xx/common/giu.c
index b32b3bc604410b39ce602575c9acfbddfce13afe..32cc8d66b34eb526f79626eaa3ac343ebadd608c 100644 (file)
--- a/arch/mips/vr41xx/common/giu.c
+++ b/arch/mips/vr41xx/common/giu.c
@@ -1,7 +1,7 @@
 /*
  *  NEC VR4100 series GIU platform device.
  *
 /*
  *  NEC VR4100 series GIU platform device.
  *

- *  Copyright (C) 2007  Yoichi Yuasa <yuasa@linux-mips.org>
+ *  Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>

  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by

diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c
index a39ef3207d7148d96351e7ea23cb385bbdd8f05f..41e873bc84747ecd05679585ea9cfdaaf2e9c3c0 100644 (file)
--- a/arch/mips/vr41xx/common/icu.c
+++ b/arch/mips/vr41xx/common/icu.c
@@ -49,11 +49,11 @@ static unsigned char sysint1_assign[16] = {
 static unsigned char sysint2_assign[16] = {
        2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
 
 static unsigned char sysint2_assign[16] = {
        2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
 

-#define ICU1_TYPE1_BASE        0x0b000080UL
-#define ICU2_TYPE1_BASE        0x0b000200UL
+#define ICU1_TYPE1_BASE 0x0b000080UL
+#define ICU2_TYPE1_BASE 0x0b000200UL

 
 

-#define ICU1_TYPE2_BASE        0x0f000080UL
-#define ICU2_TYPE2_BASE        0x0f0000a0UL
+#define ICU1_TYPE2_BASE 0x0f000080UL
+#define ICU2_TYPE2_BASE 0x0f0000a0UL

 
 #define ICU1_SIZE      0x20
 #define ICU2_SIZE      0x1c
 
 #define ICU1_SIZE      0x20
 #define ICU2_SIZE      0x1c

diff --git a/arch/mips/vr41xx/common/pmu.c b/arch/mips/vr41xx/common/pmu.c
index 9fbf5f0d1faf3499a878ff3d529103754cbc5444..70a3f90131d82af9d67bac9ff2d8d206812dde6b 100644 (file)
--- a/arch/mips/vr41xx/common/pmu.c
+++ b/arch/mips/vr41xx/common/pmu.c
@@ -74,7 +74,7 @@ static inline void software_reset(void)
                change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
                flush_cache_all();
                write_c0_wired(0);
                change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
                flush_cache_all();
                write_c0_wired(0);

-               __asm__("jr     %0"::"r"(0xbfc00000));
+               __asm__("jr     %0"::"r"(0xbfc00000));

                break;
        }
 }
                break;
        }
 }

diff --git a/arch/mips/vr41xx/common/rtc.c b/arch/mips/vr41xx/common/rtc.c
index 76e3e8af7c96e7c5975e7d328be1297f101f881a..c1e3d200920e8ca5d48c3b676291bdf1720adb79 100644 (file)
--- a/arch/mips/vr41xx/common/rtc.c
+++ b/arch/mips/vr41xx/common/rtc.c
@@ -1,7 +1,7 @@
 /*
  *  NEC VR4100 series RTC platform device.
  *
 /*
  *  NEC VR4100 series RTC platform device.
  *

- *  Copyright (C) 2007  Yoichi Yuasa <yuasa@linux-mips.org>
+ *  Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>

  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by

diff --git a/arch/mips/vr41xx/common/type.c b/arch/mips/vr41xx/common/type.c
index ff841422b6389317567054761990d7d39ff4cb3b..45836a92b7a1c05d550b7422ffc56025e391e2ee 100644 (file)
--- a/arch/mips/vr41xx/common/type.c
+++ b/arch/mips/vr41xx/common/type.c
@@ -1,7 +1,7 @@
 /*
  *  type.c, System type for NEC VR4100 series.
  *
 /*
  *  type.c, System type for NEC VR4100 series.
  *

- *  Copyright (C) 2005  Yoichi Yuasa <yuasa@linux-mips.org>
+ *  Copyright (C) 2005 Yoichi Yuasa <yuasa@linux-mips.org>

  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by

diff --git a/arch/mips/wrppmc/Platform b/arch/mips/wrppmc/Platform
index e758645e9681939626d9241c10aba3646802fe6f..dc78b25b95fe3b741f26d7c8793811c7e1e6fa33 100644 (file)
--- a/arch/mips/wrppmc/Platform
+++ b/arch/mips/wrppmc/Platform
@@ -2,6 +2,6 @@
 # Wind River PPMC Board (4KC + GT64120)
 #
 platform-$(CONFIG_WR_PPMC)     += wrppmc/
 # Wind River PPMC Board (4KC + GT64120)
 #
 platform-$(CONFIG_WR_PPMC)     += wrppmc/

-cflags-$(CONFIG_WR_PPMC)       +=                                      \
+cflags-$(CONFIG_WR_PPMC)       +=                                      \

                -I$(srctree)/arch/mips/include/asm/mach-wrppmc
 load-$(CONFIG_WR_PPMC)         += 0xffffffff80100000
                -I$(srctree)/arch/mips/include/asm/mach-wrppmc
 load-$(CONFIG_WR_PPMC)         += 0xffffffff80100000

diff --git a/arch/mips/wrppmc/irq.c b/arch/mips/wrppmc/irq.c
index c6e706274db4364f859de5d9a091e3ba61d45c3d..f237bf4d5c3a12dc7cfdec02f370f2775bff047b 100644 (file)
--- a/arch/mips/wrppmc/irq.c
+++ b/arch/mips/wrppmc/irq.c
@@ -4,8 +4,8 @@
  * Copyright (C) 2006, Wind River System Inc.
  * Author: Rongkai.Zhan, <rongkai.zhan@windriver.com>
  *
  * Copyright (C) 2006, Wind River System Inc.
  * Author: Rongkai.Zhan, <rongkai.zhan@windriver.com>
  *

- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
+ * This program is free software; you can redistribute it and/or modify it
+ * under  the terms of the GNU General  Public License as published by the

  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */
  * Free Software Foundation;  either version 2 of the  License, or (at your
  * option) any later version.
  */

diff --git a/arch/mips/wrppmc/serial.c b/arch/mips/wrppmc/serial.c
index 6f9d0858f596e1ad53445c051a057b0cad348b22..83f0f7d05187a73ff346dd1feac18bb34bea3d54 100644 (file)
--- a/arch/mips/wrppmc/serial.c
+++ b/arch/mips/wrppmc/serial.c
@@ -1,7 +1,7 @@
 /*
  *  Registration of WRPPMC UART platform device.
  *
 /*
  *  Registration of WRPPMC UART platform device.
  *

- *  Copyright (C) 2007  Yoichi Yuasa <yuasa@linux-mips.org>
+ *  Copyright (C) 2007 Yoichi Yuasa <yuasa@linux-mips.org>

  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by