MIPS, clk: move jz4740 clock suspend, resume functions to jz4740-cgu

The jz4740-cgu driver already has access to the CGU, so it makes sense
to move the few remaining accesses to the CGU from arch/mips/jz4740
there too. Move the jz4740_clock_{suspend,resume} functions there for
such consistency. The arch/mips/jz4740/clock.c file now contains nothing
more of use & so is removed.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10158/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/mach-jz4740/clock.h b/arch/mips/include/asm/mach-jz4740/clock.h
index 01d846845f530f3e7328d0f639b4bea11c35b96c..16659cd76d4e7caa863e7ebeadd19ccb6b06392c 100644 (file)
--- a/arch/mips/include/asm/mach-jz4740/clock.h
+++ b/arch/mips/include/asm/mach-jz4740/clock.h
@@ -20,8 +20,6 @@ enum jz4740_wait_mode {
        JZ4740_WAIT_MODE_SLEEP,
 };
 
-int jz4740_clock_init(void);
-
 void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode);
 
 void jz4740_clock_udc_enable_auto_suspend(void);

diff --git a/arch/mips/jz4740/Makefile b/arch/mips/jz4740/Makefile
index fdb12efc54a15a436859a7a9b4aed8d57db9860d..7636432af6eeaf6bf3b66ee42a80f432a07e5b61 100644 (file)
--- a/arch/mips/jz4740/Makefile
+++ b/arch/mips/jz4740/Makefile
@@ -5,7 +5,7 @@
 # Object file lists.
 
 obj-y += prom.o time.o reset.o setup.o \
-       gpio.o clock.o platform.o timer.o serial.o
+       gpio.o platform.o timer.o serial.o
 
 # board specific support
 

diff --git a/arch/mips/jz4740/clock.c b/arch/mips/jz4740/clock.c
deleted file mode 100644 (file)
index 2a10829..0000000
--- a/arch/mips/jz4740/clock.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
- *  JZ4740 SoC clock support
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under  the terms of the GNU General         Public License as published by the
- *  Free Software Foundation;  either version 2 of the License, or (at your
- *  option) any later version.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/clk-provider.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/list.h>
-#include <linux/err.h>
-
-#include <asm/mach-jz4740/clock.h>
-#include <asm/mach-jz4740/base.h>
-
-#include "clock.h"
-
-#define JZ_REG_CLOCK_PLL       0x10
-#define JZ_REG_CLOCK_GATE      0x20
-
-#define JZ_CLOCK_GATE_UART0    BIT(0)
-#define JZ_CLOCK_GATE_TCU      BIT(1)
-#define JZ_CLOCK_GATE_DMAC     BIT(12)
-
-#define JZ_CLOCK_PLL_STABLE            BIT(10)
-#define JZ_CLOCK_PLL_ENABLED           BIT(8)
-
-static void __iomem *jz_clock_base;
-
-static uint32_t jz_clk_reg_read(int reg)
-{
-       return readl(jz_clock_base + reg);
-}
-
-static void jz_clk_reg_set_bits(int reg, uint32_t mask)
-{
-       uint32_t val;
-
-       val = readl(jz_clock_base + reg);
-       val |= mask;
-       writel(val, jz_clock_base + reg);
-}
-
-static void jz_clk_reg_clear_bits(int reg, uint32_t mask)
-{
-       uint32_t val;
-
-       val = readl(jz_clock_base + reg);
-       val &= ~mask;
-       writel(val, jz_clock_base + reg);
-}
-
-void jz4740_clock_suspend(void)
-{
-       jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE,
-               JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
-
-       jz_clk_reg_clear_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
-}
-
-void jz4740_clock_resume(void)
-{
-       uint32_t pll;
-
-       jz_clk_reg_set_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
-
-       do {
-               pll = jz_clk_reg_read(JZ_REG_CLOCK_PLL);
-       } while (!(pll & JZ_CLOCK_PLL_STABLE));
-
-       jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE,
-               JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
-}
-
-int jz4740_clock_init(void)
-{
-       jz_clock_base = ioremap(JZ4740_CPM_BASE_ADDR, 0x100);
-       if (!jz_clock_base)
-               return -EBUSY;
-
-       return 0;
-}

diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c
index be9b0a3a5c405dede68f1451f91025d4a4f2de94..917255368db8f42dc046fba3242ae15b464089e1 100644 (file)
--- a/arch/mips/jz4740/time.c
+++ b/arch/mips/jz4740/time.c
@@ -120,7 +120,6 @@ void __init plat_time_init(void)
        struct clk *ext_clk;
 
        of_clk_init(NULL);
-       jz4740_clock_init();
        jz4740_timer_init();
 
        ext_clk = clk_get(NULL, "ext");

diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index 0e692ed632e58e7413b0f26c2c8c8747b4e645df..305a26c2a800ec621806f7cf9df71bf66e881bb3 100644 (file)
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -264,3 +264,40 @@ void jz4740_clock_udc_enable_auto_suspend(void)
        writel(clkgr, cgu->base + CGU_REG_CLKGR);
 }
 EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend);
+
+#define JZ_CLOCK_GATE_UART0    BIT(0)
+#define JZ_CLOCK_GATE_TCU      BIT(1)
+#define JZ_CLOCK_GATE_DMAC     BIT(12)
+
+void jz4740_clock_suspend(void)
+{
+       uint32_t clkgr, cppcr;
+
+       clkgr = readl(cgu->base + CGU_REG_CLKGR);
+       clkgr |= JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0;
+       writel(clkgr, cgu->base + CGU_REG_CLKGR);
+
+       cppcr = readl(cgu->base + CGU_REG_CPPCR);
+       cppcr &= ~BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.enable_bit);
+       writel(cppcr, cgu->base + CGU_REG_CPPCR);
+}
+
+void jz4740_clock_resume(void)
+{
+       uint32_t clkgr, cppcr, stable;
+
+       cppcr = readl(cgu->base + CGU_REG_CPPCR);
+       cppcr |= BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.enable_bit);
+       writel(cppcr, cgu->base + CGU_REG_CPPCR);
+
+       stable = BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.stable_bit);
+       do {
+               cppcr = readl(cgu->base + CGU_REG_CPPCR);
+       } while (!(cppcr & stable));
+
+       clkgr = readl(cgu->base + CGU_REG_CLKGR);
+       clkgr &= ~JZ_CLOCK_GATE_TCU;
+       clkgr &= ~JZ_CLOCK_GATE_DMAC;
+       clkgr &= ~JZ_CLOCK_GATE_UART0;
+       writel(clkgr, cgu->base + CGU_REG_CLKGR);
+}