MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu

The jz4740-cgu driver already has access to the CGU, so it makes sense
to move the few remaining accesses to the CGU from arch/mips/jz4740
there too. Move jz4740_clock_set_wait_mode for such consistency.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/10153/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/jz4740/clock.c b/arch/mips/jz4740/clock.c
index dedee7cfb26569b9db94083c808478da7dd288d2..90b44d728cbd110c4526cb8041c7b7eae9913211 100644 (file)
--- a/arch/mips/jz4740/clock.c
+++ b/arch/mips/jz4740/clock.c
@@ -28,7 +28,6 @@
 
 #include "clock.h"
 
-#define JZ_REG_CLOCK_LOW_POWER 0x04
 #define JZ_REG_CLOCK_PLL       0x10
 #define JZ_REG_CLOCK_GATE      0x20
 
@@ -40,9 +39,6 @@
 #define JZ_CLOCK_PLL_STABLE            BIT(10)
 #define JZ_CLOCK_PLL_ENABLED           BIT(8)
 
-#define JZ_CLOCK_LOW_POWER_MODE_DOZE BIT(2)
-#define JZ_CLOCK_LOW_POWER_MODE_SLEEP BIT(0)
-
 static void __iomem *jz_clock_base;
 
 static uint32_t jz_clk_reg_read(int reg)
@@ -68,18 +64,6 @@ static void jz_clk_reg_clear_bits(int reg, uint32_t mask)
        writel(val, jz_clock_base + reg);
 }
 
-void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode)
-{
-       switch (mode) {
-       case JZ4740_WAIT_MODE_IDLE:
-               jz_clk_reg_clear_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP);
-               break;
-       case JZ4740_WAIT_MODE_SLEEP:
-               jz_clk_reg_set_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP);
-               break;
-       }
-}
-
 void jz4740_clock_udc_disable_auto_suspend(void)
 {
        jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);

diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index d5bb7a39219e6612ba2c0f759c582976cd45d178..0209ed6d412a9960a21f1b19c2d68fdf0724a6b2 100644 (file)
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -19,10 +19,12 @@
 #include <linux/delay.h>
 #include <linux/of.h>
 #include <dt-bindings/clock/jz4740-cgu.h>
+#include <asm/mach-jz4740/clock.h>
 #include "cgu.h"
 
 /* CGU register offsets */
 #define CGU_REG_CPCCR          0x00
+#define CGU_REG_LCR            0x04
 #define CGU_REG_CPPCR          0x10
 #define CGU_REG_SCR            0x24
 #define CGU_REG_I2SCDR         0x60
@@ -42,6 +44,9 @@
 #define PLLCTL_BYPASS          (1 << 9)
 #define PLLCTL_ENABLE          (1 << 8)
 
+/* bits within the LCR register */
+#define LCR_SLEEP              (1 << 0)
+
 static struct ingenic_cgu *cgu;
 
 static const s8 pll_od_encoding[4] = {
@@ -220,3 +225,20 @@ static void __init jz4740_cgu_init(struct device_node *np)
                pr_err("%s: failed to register CGU Clocks\n", __func__);
 }
 CLK_OF_DECLARE(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);
+
+void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode)
+{
+       uint32_t lcr = readl(cgu->base + CGU_REG_LCR);
+
+       switch (mode) {
+       case JZ4740_WAIT_MODE_IDLE:
+               lcr &= ~LCR_SLEEP;
+               break;
+
+       case JZ4740_WAIT_MODE_SLEEP:
+               lcr |= LCR_SLEEP;
+               break;
+       }
+
+       writel(lcr, cgu->base + CGU_REG_LCR);
+}