MIPS: Refactor dumping of TLB registers for r3k/r4k
authorJames Hogan <james.hogan@imgtec.com>
Wed, 15 Jul 2015 15:17:43 +0000 (16:17 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Thu, 3 Sep 2015 10:07:45 +0000 (12:07 +0200)
The TLB registers are dumped in a couble of places:
 - sysrq_tlbdump_single() - when dumping TLB state.
 - do_mcheck() - in response to a machine check error.

The main TLB registers also differ between r3k and r4k, but r4k appears
to be assumed.

Refactor this code into a dump_tlb_regs() function, implemented for both
r3k and r4k, and used by both of the above functions.

Fixes: d1e9a4f54735 ("MIPS: Add SysRq operation to dump TLBs on all CPUs")
Suggested-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10721/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/tlbdebug.h
arch/mips/kernel/sysrq.c
arch/mips/kernel/traps.c
arch/mips/lib/dump_tlb.c
arch/mips/lib/r3k_dump_tlb.c
arch/mips/mm/tlb-r3k.c

index bb8f5c29c3d9f9a5e0c72c4497993fec46fcfae2..3a25a8780ac76b9d420ca66c2b319674c5c8932a 100644 (file)
@@ -11,6 +11,7 @@
 /*
  * TLB debugging functions:
  */
+extern void dump_tlb_regs(void);
 extern void dump_tlb_all(void);
 
 #endif /* __ASM_TLBDEBUG_H */
index 5b539f5fc9d9d6a5d6d48d2bf5ea8aed1b78d8ea..5f055393092dec3ac7704a22e72e672c08a22029 100644 (file)
@@ -21,24 +21,12 @@ static DEFINE_SPINLOCK(show_lock);
 
 static void sysrq_tlbdump_single(void *dummy)
 {
-       const int field = 2 * sizeof(unsigned long);
        unsigned long flags;
 
        spin_lock_irqsave(&show_lock, flags);
 
        pr_info("CPU%d:\n", smp_processor_id());
-       pr_info("Index  : %0x\n", read_c0_index());
-       pr_info("Pagemask: %0x\n", read_c0_pagemask());
-       pr_info("EntryHi : %0*lx\n", field, read_c0_entryhi());
-       pr_info("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
-       pr_info("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
-       pr_info("Wired   : %0x\n", read_c0_wired());
-       pr_info("Pagegrain: %0x\n", read_c0_pagegrain());
-       if (cpu_has_htw) {
-               pr_info("PWField : %0*lx\n", field, read_c0_pwfield());
-               pr_info("PWSize  : %0*lx\n", field, read_c0_pwsize());
-               pr_info("PWCtl   : %0x\n", read_c0_pwctl());
-       }
+       dump_tlb_regs();
        pr_info("\n");
        dump_tlb_all();
        pr_info("\n");
index 01da120d75c44a352b7b8ea58bf954a0a56add58..da0b3189fe88350304f24eaee6db8f35a0545a28 100644 (file)
@@ -1523,7 +1523,6 @@ asmlinkage void do_watch(struct pt_regs *regs)
 
 asmlinkage void do_mcheck(struct pt_regs *regs)
 {
-       const int field = 2 * sizeof(unsigned long);
        int multi_match = regs->cp0_status & ST0_TS;
        enum ctx_state prev_state;
        mm_segment_t old_fs = get_fs();
@@ -1532,19 +1531,8 @@ asmlinkage void do_mcheck(struct pt_regs *regs)
        show_regs(regs);
 
        if (multi_match) {
-               pr_err("Index   : %0x\n", read_c0_index());
-               pr_err("Pagemask: %0x\n", read_c0_pagemask());
-               pr_err("EntryHi : %0*lx\n", field, read_c0_entryhi());
-               pr_err("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
-               pr_err("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
-               pr_err("Wired   : %0x\n", read_c0_wired());
-               pr_err("Pagegrain: %0x\n", read_c0_pagegrain());
-               if (cpu_has_htw) {
-                       pr_err("PWField : %0*lx\n", field, read_c0_pwfield());
-                       pr_err("PWSize  : %0*lx\n", field, read_c0_pwsize());
-                       pr_err("PWCtl   : %0x\n", read_c0_pwctl());
-               }
-               pr_err("\n");
+               dump_tlb_regs();
+               pr_info("\n");
                dump_tlb_all();
        }
 
index 167f35634709b885d734778e85ec5896c07eba0d..519ededbf9a4cc4d6879fdb9856e2076e2506e2f 100644 (file)
 #include <asm/pgtable.h>
 #include <asm/tlbdebug.h>
 
+void dump_tlb_regs(void)
+{
+       const int field = 2 * sizeof(unsigned long);
+
+       pr_info("Index    : %0x\n", read_c0_index());
+       pr_info("PageMask : %0x\n", read_c0_pagemask());
+       pr_info("EntryHi  : %0*lx\n", field, read_c0_entryhi());
+       pr_info("EntryLo0 : %0*lx\n", field, read_c0_entrylo0());
+       pr_info("EntryLo1 : %0*lx\n", field, read_c0_entrylo1());
+       pr_info("Wired    : %0x\n", read_c0_wired());
+       pr_info("PageGrain: %0x\n", read_c0_pagegrain());
+       if (cpu_has_htw) {
+               pr_info("PWField  : %0*lx\n", field, read_c0_pwfield());
+               pr_info("PWSize   : %0*lx\n", field, read_c0_pwsize());
+               pr_info("PWCtl    : %0x\n", read_c0_pwctl());
+       }
+}
+
 static inline const char *msk2str(unsigned int mask)
 {
        switch (mask) {
index 8e0d3cff8ae4481b104733019fe71be0c5c640a1..cfcbb5218b5951bbfaf661f99dec5da5c710c6bf 100644 (file)
 #include <asm/pgtable.h>
 #include <asm/tlbdebug.h>
 
+extern int r3k_have_wired_reg;
+
+void dump_tlb_regs(void)
+{
+       pr_info("Index    : %0x\n", read_c0_index());
+       pr_info("EntryHi  : %0lx\n", read_c0_entryhi());
+       pr_info("EntryLo  : %0lx\n", read_c0_entrylo0());
+       if (r3k_have_wired_reg)
+               pr_info("Wired    : %0x\n", read_c0_wired());
+}
+
 static void dump_tlb(int first, int last)
 {
        int     i;
index 2b75b8f880ed1f50df9429d758d2b4d5cf624cd2..b4f366f7c0f57ae86a5cf601d75c81cda7ee2acd 100644 (file)
@@ -36,7 +36,7 @@ extern void build_tlb_refill_handler(void);
                "nop\n\t"               \
                ".set   pop\n\t")
 
-static int r3k_have_wired_reg;                 /* Should be in cpu_data? */
+int r3k_have_wired_reg;                        /* Should be in cpu_data? */
 
 /* TLB operations. */
 static void local_flush_tlb_from(int entry)