Merge tag 'sunxi-clk-for-3.13' of https://github.com/mripard/linux into clk-next...

Allwinner sunXi SoCs clock changes

Those are mostly random fixes, except for one patch to the composite
clock that adds support for automatic reparenting.

Conflicts:
	drivers/clk/sunxi/clk-sunxi.c

diff --cc drivers/clk/sunxi/clk-sunxi.c
index 9bbd035145409b9908ca25fecfd412d5e7345840,9665cb8d023878231c0fa5beeffe198c3ba4f5cc..98fec4e4baa76ed5a0077ae57834da8e47c80626
--- 1/drivers/clk/sunxi/clk-sunxi.c
--- 2/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@@ -616,8 -623,36 +622,33 @@@ static void __init of_sunxi_table_clock
        }
  }
  
- static void __init sunxi_init_clocks(struct device_node *np)
+ /**
+  * System clock protection
+  *
+  * By enabling these critical clocks, we prevent their accidental gating
+  * by the framework
+  */
+ static void __init sunxi_clock_protect(void)
+ {
+       struct clk *clk;
+ 
+       /* memory bus clock - sun5i+ */
+       clk = clk_get(NULL, "mbus");
+       if (!IS_ERR(clk)) {
+               clk_prepare_enable(clk);
+               clk_put(clk);
+       }
+ 
+       /* DDR clock - sun4i+ */
+       clk = clk_get(NULL, "pll5_ddr");
+       if (!IS_ERR(clk)) {
+               clk_prepare_enable(clk);
+               clk_put(clk);
+       }
+ }
+ 
 -void __init sunxi_init_clocks(void)
++static void __init sunxi_init_clocks(void)
  {
 -      /* Register all the simple and basic clocks on DT */
 -      of_clk_init(NULL);
 -
        /* Register factor clocks */
        of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
  
@@@ -629,9 -664,7 +660,12 @@@
  
        /* Register gate clocks */
        of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
+ 
+       /* Enable core system clocks */
+       sunxi_clock_protect();
  }
 +CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks);
 +CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks);
 +CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sunxi_init_clocks);
 +CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sunxi_init_clocks);
 +CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sunxi_init_clocks);