Merge branches 'iommu/fixes', 'x86/vt-d', 'x86/amd', 'ppc/pamu', 'core' and 'arm...

diff --cc Documentation/kernel-parameters.txt
Simple merge

diff --cc drivers/iommu/amd_iommu.c
index 98f555dafb55c8edc32393919ee48140d024b184,c6f3c7e046840d4b6de11c9c3c06c91e25f14431,a7f6b04eaa5e6dca676e13b386716ea6a97a28a7,685f2821333af28273343cfacf6d897a68f804ec,b287ca33833df792350baad6f82fefbe1494e038..1d84be17ff2167253d0df115f1ff6ead90657666
--- 1/drivers/iommu/amd_iommu.c
--- 2/drivers/iommu/amd_iommu.c
--- 3/drivers/iommu/amd_iommu.c
--- 4/drivers/iommu/amd_iommu.c
--- 5/drivers/iommu/amd_iommu.c
+++ b/drivers/iommu/amd_iommu.c
@@@@@@ -807,13 -786,39 -807,13 -802,13 -807,13 +781,39 @@@@@@ static void iommu_poll_ppr_log(struct a
     
     irqreturn_t amd_iommu_int_thread(int irq, void *data)
     {
- ---   struct amd_iommu *iommu;
+ +++   struct amd_iommu *iommu = (struct amd_iommu *) data;
+ +++   u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
     
- ---   for_each_iommu(iommu) {
- ---           iommu_poll_events(iommu);
- ---           iommu_poll_ppr_log(iommu);
- ---   }
+ +++   while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
+ +++           /* Enable EVT and PPR interrupts again */
+ +++           writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
+ +++                   iommu->mmio_base + MMIO_STATUS_OFFSET);
+  + 
+ +++           if (status & MMIO_STATUS_EVT_INT_MASK) {
+ +++                   pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
+ +++                   iommu_poll_events(iommu);
+ +++           }
+ + +
+ +++           if (status & MMIO_STATUS_PPR_INT_MASK) {
+ +++                   pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
+ +++                   iommu_poll_ppr_log(iommu);
+ +++           }
  +++
+ +++           /*
+ +++            * Hardware bug: ERBT1312
+ +++            * When re-enabling interrupt (by writing 1
+ +++            * to clear the bit), the hardware might also try to set
+ +++            * the interrupt bit in the event status register.
+ +++            * In this scenario, the bit will be set, and disable
+ +++            * subsequent interrupts.
+ +++            *
+ +++            * Workaround: The IOMMU driver should read back the
+ +++            * status register and check if the interrupt bits are cleared.
+ +++            * If not, driver will need to go through the interrupt handler
+ +++            * again and re-clear the bits
+ +++            */
+ +++           status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
+ +++   }
        return IRQ_HANDLED;
     }
     

diff --cc drivers/iommu/intel-iommu.c
Simple merge

diff --cc drivers/iommu/iommu.c
Simple merge

diff --cc drivers/iommu/irq_remapping.c
Simple merge

diff --cc drivers/iommu/tegra-gart.c
Simple merge

diff --cc drivers/iommu/tegra-smmu.c
Simple merge

diff --cc include/linux/iommu.h
Simple merge