Merge tag 'topic/i915-hda-componentized-2015-01-12' into drm-intel-next-queued
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 12 Jan 2015 22:07:46 +0000 (23:07 +0100)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 12 Jan 2015 22:07:46 +0000 (23:07 +0100)
Conflicts:
drivers/gpu/drm/i915/intel_runtime_pm.c

Separate branch so that Takashi can also pull just this refactoring
into sound-next.

Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
17 files changed:
1  2 
Documentation/DocBook/drm.tmpl
drivers/gpu/drm/drm_crtc.c
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/i915/i915_drv.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_gem.c
drivers/gpu/drm/i915/i915_gem_context.c
drivers/gpu/drm/i915/i915_gem_execbuffer.c
drivers/gpu/drm/i915/i915_irq.c
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/i915_suspend.c
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_drv.h
drivers/gpu/drm/i915/intel_pm.c
drivers/gpu/drm/i915/intel_ringbuffer.c
drivers/gpu/drm/i915/intel_runtime_pm.c
include/drm/drm_crtc.h

Simple merge
Simple merge
Simple merge
Simple merge
Simple merge
index 3f6ca46a1dfec4e6f7d9b8905059f0fc25fd37cf,c11603b4cf1dc035d792a47bb3e58334e52382d9..9f430f77a52026345defa1d372bbb607a7e8f0a8
@@@ -1217,10 -1228,11 +1221,11 @@@ int __i915_wait_request(struct drm_i915
  
        WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
  
 -      if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
 +      if (i915_gem_request_completed(req, true))
                return 0;
  
-       timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0;
+       timeout_expire = timeout ?
+               jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0;
  
        if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
                gen6_rps_boost(dev_priv);
Simple merge
index 0cb0067af4bb546a03cb322615d7f5733a0dd4f8,172de3b3433b20b57d7e57f31ad63d3daa09bba3..0f32fd1a9d1017e8bef2377b8fd1f1c47ecf65fa
  #define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
  #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
                               (pipe) == PIPE_B ? (b) : (c))
 +#define _PORT3(port, a, b, c) ((port) == PORT_A ? (a) : \
 +                             (port) == PORT_B ? (b) : (c))
  
- #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
- #define _MASKED_BIT_DISABLE(a) ((a) << 16)
+ #define _MASKED_FIELD(mask, value) ({                                    \
+       if (__builtin_constant_p(mask))                                    \
+               BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
+       if (__builtin_constant_p(value))                                   \
+               BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
+       if (__builtin_constant_p(mask) && __builtin_constant_p(value))     \
+               BUILD_BUG_ON_MSG((value) & ~(mask),                        \
+                                "Incorrect value for mask");              \
+       (mask) << 16 | (value); })
+ #define _MASKED_BIT_ENABLE(a) ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
+ #define _MASKED_BIT_DISABLE(a)        (_MASKED_FIELD((a), 0))
  
  /* PCI config space */
  
Simple merge
Simple merge
index 588b618ab668fc699153bcc5f655d4ec6d1a8bf6,e88fd5d12f05b21b470aa8b1175b701ff91647b7..1043a1e3a5698878a1bfcc08bb6a6edd2b6e25ad
@@@ -873,8 -872,11 +873,10 @@@ void intel_fb_obj_flush(struct drm_i915
  void intel_init_audio(struct drm_device *dev);
  void intel_audio_codec_enable(struct intel_encoder *encoder);
  void intel_audio_codec_disable(struct intel_encoder *encoder);
+ void i915_audio_component_init(struct drm_i915_private *dev_priv);
+ void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
  
  /* intel_display.c */
 -const char *intel_output_name(int output);
  bool intel_has_pending_fb_unpin(struct drm_device *dev);
  int intel_pch_rawclk(struct drm_device *dev);
  void intel_mark_busy(struct drm_device *dev);
index 091860432f01e003232812cfb82b3e4ba32c08b3,964b28e3c6303e5db6ecd5458c42b90b27cdd11f..3ba446a69ecd3f953e0a417230fbd6dbc2a9d3a3
@@@ -5970,12 -6716,8 +5980,12 @@@ static void haswell_init_clock_gating(s
         * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
         */
        I915_WRITE(GEN7_GT_MODE,
-                  GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
+                  _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
  
 +      /* WaSampleCChickenBitEnable:hsw */
 +      I915_WRITE(HALF_SLICE_CHICKEN3,
 +                 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
 +
        /* WaSwitchSolVfFArbitrationPriority:hsw */
        I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
  
index 3cad32a80108f3bc8059dbe4d5f9c8f9513a8ff0,c7bc93d28d84ec4356c0c5f5c4e4cd67296df709..12a36f0ca53d61e589d708d37e3791bfd4d8625e
@@@ -710,24 -703,8 +713,24 @@@ static int intel_ring_workarounds_emit(
        return 0;
  }
  
 +static int intel_rcs_ctx_init(struct intel_engine_cs *ring,
 +                            struct intel_context *ctx)
 +{
 +      int ret;
 +
 +      ret = intel_ring_workarounds_emit(ring, ctx);
 +      if (ret != 0)
 +              return ret;
 +
 +      ret = i915_gem_render_state_init(ring);
 +      if (ret)
 +              DRM_ERROR("init render state: %d\n", ret);
 +
 +      return ret;
 +}
 +
  static int wa_add(struct drm_i915_private *dev_priv,
-                 const u32 addr, const u32 val, const u32 mask)
+                 const u32 addr, const u32 mask, const u32 val)
  {
        const u32 idx = dev_priv->workarounds.count;
  
Simple merge