Fix various .c/.h typos in comments (no code changes).
Signed-off-by: Matt LaPlante <kernel1@cyberdogtech.com>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
/*!*****************************************************************************
*!
-*! Implements an interface for i2c compatible eeproms to run under linux.
-*! Supports 2k, 8k(?) and 16k. Uses adaptive timing adjustents by
+*! Implements an interface for i2c compatible eeproms to run under Linux.
+*! Supports 2k, 8k(?) and 16k. Uses adaptive timing adjustments by
*! Johan.Adolfsson@axis.com
*!
*! Probing results:
*! Revision 1.8 2001/06/15 13:24:29 jonashg
*! * Added verification of pointers from userspace in read and write.
*! * Made busy counter volatile.
-*! * Added define for inital write delay.
+*! * Added define for initial write delay.
*! * Removed warnings by using loff_t instead of unsigned long.
*!
*! Revision 1.7 2001/06/14 15:26:54 jonashg
*! Update Port B register and shadow even when running with hardware support
*! to avoid glitches when reading bits
*! Never set direction to out in i2c_inbyte
-*! Removed incorrect clock togling at end of i2c_inbyte
+*! Removed incorrect clock toggling at end of i2c_inbyte
*!
*! Revision 1.8 2002/08/13 06:31:53 starvik
*! Made SDA and SCL line configurable
*!
*! Revision 1.2 2002/11/19 14:35:24 starvik
*! Changes from linux 2.4
-*! Changed struct initializer syntax to the currently prefered notation
+*! Changed struct initializer syntax to the currently preferred notation
*!
*! Revision 1.1 2001/12/17 13:59:27 bjornw
*! Initial revision
** If a device prefetches beyond the end of a valid pdir entry, it will cause
** a hard failure, ie. MCA. Version 3.0 and later of the zx1 LBA should
** disconnect on 4k boundaries and prevent such issues. If the device is
-** particularly agressive, this option will keep the entire pdir valid such
+** particularly aggressive, this option will keep the entire pdir valid such
** that prefetching will hit a valid address. This could severely impact
** error containment, and is therefore off by default. The page that is
** used for spill-over is poisoned, so that should help debugging somewhat.
/*
** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up
-** (or rather not merge) DMA's into managable chunks.
+** (or rather not merge) DMAs into manageable chunks.
** On parisc, this is more of the software/tuning constraint
-** rather than the HW. I/O MMU allocation alogorithms can be
-** faster with smaller size is (to some degree).
+** rather than the HW. I/O MMU allocation algorithms can be
+** faster with smaller sizes (to some degree).
*/
#define DMA_CHUNK_SIZE (BITS_PER_LONG*iovp_size)
/* ======================================================================= */
/*
-** Depending on <base> scan the MMU, Data or Instrction side
+** Depending on <base> scan the MMU, Data or Instruction side
** looking for a valid mapping matching Eaddr & asid.
** Return -1 if not found or the TLB id entry otherwise.
** Note: it works only for 4k pages!
** | R | NZ | 5-bit exponent | 9-bit mantissa |
** +----+----+------------------+-------------------------------+
**
-** R = reserverd (written as 0)
+** R = reserved (written as 0)
** NZ = 0 if 0 cells/sec; 1 otherwise
**
** if NZ = 1, rate = 1.mmmmmmmmm x 2^(eeeee) cells/sec
**
** Packet is an actual packet structure to be filled in with the packet
** information associated with the command. You need to fill in everything,
-** as the command processore doesn't process the command packet in any way.
+** as the command processor doesn't process the command packet in any way.
**
** The PreFuncP is called before the packet is enqueued on the host rup.
** PreFuncP is called as (*PreFuncP)(PreArg, CmdBlkP);. PreFuncP must
** which value will be written into memory.
** Call with op set to zero means that the RAM will not be read and checked
** before it is written.
-** Call with op not zero, and the RAM will be read and compated with val[op-1]
+** Call with op not zero and the RAM will be read and compared with val[op-1]
** to check that the data from the previous phase was retained.
*/
** command bit set onto the port. The command bit is in the len field,
** and gets ORed in with the actual byte count.
**
-** When you send a packet with the command bit set, then the first
-** data byte ( data[0] ) is interpretted as the command to execute.
+** When you send a packet with the command bit set the first
+** data byte (data[0]) is interpreted as the command to execute.
** It also governs what data structure overlay should accompany the packet.
** Commands are defined in cirrus/cirrus.h
**
**
** Most commands do not use the remaining bytes in the data array. The
** exceptions are OPEN MOPEN and CONFIG. (NB. As with the SI CONFIG and
-** OPEN are currently analagous). With these three commands the following
+** OPEN are currently analogous). With these three commands the following
** 11 data bytes are all used to pass config information such as baud rate etc.
** The fields are also defined in cirrus.h. Some contain straightforward
** information such as the transmit XON character. Two contain the transmit and
/*
** Get ATAPI_FORMAT_UNIT progress indication.
**
-** Userland gives a pointer to an int. The int is set to a progresss
+** Userland gives a pointer to an int. The int is set to a progress
** indicator 0-65536, with 65536=100%.
**
** If the drive does not support format progress indication, we just check
/*
** Cleanup function will be called for master adapter only
-** this is garanteed by design: cleanup callback is set
+** this is guaranteed by design: cleanup callback is set
** by master adapter only
*/
static int diva_4bri_cleanup_adapter(diva_os_xdi_adapter_t * a)
/*
* include Genero generated HFC-4S/8S header file hfc48scu.h
-* for comlete register description. This will define _HFC48SCU_H_
+* for complete register description. This will define _HFC48SCU_H_
* to prevent redefinitions
*/
/* New design (By Emard)
** this rps1 code will copy internal HS event to GPIO3 pin.
-** GPIO3 is in budget-patch hardware connectd to port B VSYNC
+** GPIO3 is in budget-patch hardware connected to port B VSYNC
** HS is an internal event of 7146, accessible with RPS
** and temporarily raised high every n lines
** (n in defined in the RPS_THRESH1 counter threshold)
** I think HS is raised high on the beginning of the n-th line
** and remains high until this n-th line that triggered
-** it is completely received. When the receiption of n-th line
+** it is completely received. When the reception of n-th line
** ends, HS is lowered.
** To transmit data over DMA, 7146 needs changing state at
** hardware debug note: a working budget card (including budget patch)
** with vpeirq() interrupt setup in mode "0x90" (every 64K) will
** generate 3 interrupts per 25-Hz DMA frame of 2*188*512 bytes
-** and that means 3*25=75 Hz of interrupt freqency, as seen by
+** and that means 3*25=75 Hz of interrupt frequency, as seen by
** watch cat /proc/interrupts
**
** If this frequency is 3x lower (and data received in the DMA
** this means VSYNC line is not connected in the hardware.
** (check soldering pcb and pins)
** The same behaviour of missing VSYNC can be duplicated on budget
-** cards, by seting DD1_INIT trigger mode 7 in 3rd nibble.
+** cards, by setting DD1_INIT trigger mode 7 in 3rd nibble.
*/
// Setup RPS1 "program" (p35)
* the literal in the instruction before the code is loaded, the
* driver can change the algorithm.
*
-* INTDELAY - This loads the dead-man timer with its inital value.
+* INTDELAY - This loads the dead-man timer with its initial value.
* When this timer expires the interrupt is asserted, and the
* timer is reset each time a new packet is received. (see
* BUNDLEMAX below to set the limit on number of chained packets)
*
* hw - Struct containing variables accessed by shared code
*
-* Sets bit 15 of the MII Control regiser
+* Sets bit 15 of the MII Control register
******************************************************************************/
int32_t
e1000_phy_reset(struct e1000_hw *hw)
/*
** Interim definition of SK_DRV_TIMER placed in this file until
-** common modules have boon finallized
+** common modules have been finalized
*/
#define SK_DRV_TIMER 11
#define SK_DRV_MODERATION_TIMER 1
/*******************************************************************************
** Function : SkDimDisplayModerationSettings
-** Description : Displays the current settings regaring interrupt moderation
+** Description : Displays the current settings regarding interrupt moderation
** Programmer : Ralph Roesler
** Last Modified: 22-mar-03
** Returns : void (!)
/*******************************************************************************
** Function : DisableIntMod()
-** Description : Disbles the interrupt moderation independent of what inter-
+** Description : Disables the interrupt moderation independent of what inter-
** rupts are running or not
** Programmer : Ralph Roesler
** Last Modified: 23-mar-03
}
/*
-* handling the beaconing responces. if we get different QoS setting
-* of the network from the the associated setting adjust the QoS
+* handling the beaconing responses. if we get different QoS setting
+* off the network from the associated setting, adjust the QoS
* setting
*/
static int ipw_qos_association_resp(struct ipw_priv *priv,
** This bit tells U2 to do R/M/W for partial cachelines. "Streaming"
** data can avoid this if the mapping covers full cache lines.
** o STOP_MOST is needed for atomicity across cachelines.
-** Apperently only "some EISA devices" need this.
+** Apparently only "some EISA devices" need this.
** Using CONFIG_ISA is hack. Only the IOA with EISA under it needs
** to use this hint iff the EISA devices needs this feature.
** According to the U2 ERS, STOP_MOST enabled pages hurt performance.
**
** PA Firmware
** -----------
-** PA-RISC platforms have two fundementally different types of firmware.
+** PA-RISC platforms have two fundamentally different types of firmware.
** For PCI devices, "Legacy" PDC initializes the "INTERRUPT_LINE" register
** and BARs similar to a traditional PC BIOS.
** The newer "PAT" firmware supports PDC calls which return tables.
-** PAT firmware only initializes PCI Console and Boot interface.
-** With these tables, the OS can progam all other PCI devices.
+** PAT firmware only initializes the PCI Console and Boot interface.
+** With these tables, the OS can program all other PCI devices.
**
** One such PAT PDC call returns the "Interrupt Routing Table" (IRT).
** The IRT maps each PCI slot's INTA-D "output" line to an I/O SAPIC
*
* Action: issue a READ command to HPC
*
-* Input: pslot - can not be NULL for READ_ALLSTAT
+* Input: pslot - cannot be NULL for READ_ALLSTAT
* pstatus - can be NULL for READ_ALLSTAT
*
* Return 0 or error codes
#define CLAW_COMPLETE 0xff /* flag to indicate i/o completed */
/*-----------------------------------------------------*
-* CLAW control comand code *
+* CLAW control command code *
*------------------------------------------------------*/
#define SYSTEM_VALIDATE_REQUEST 0x01 /* System Validate request */
* The host accesses this scratch in a different manner from the
* central sequencer. The sequencer has to use CSEQ registers CSCRPAGE
* and CMnSCRPAGE to access the scratch memory. A flat mapping of the
- * scratch memory is avaliable for software convenience and to prevent
+ * scratch memory is available for software convenience and to prevent
* corruption while the sequencer is running. This memory is mapped
* onto addresses 800h - BFFh, total of 400h bytes.
*
#define OCM_INIT_DIR_ENTRIES 5
/***************************************************************************
-* OCM dircetory default
+* OCM directory default
***************************************************************************/
static struct asd_ocm_dir OCMDirInit =
{
};
/***************************************************************************
-* OCM dircetory Entries default
+* OCM directory Entries default
***************************************************************************/
static struct asd_ocm_dir_ent OCMDirEntriesInit[OCM_INIT_DIR_ENTRIES] =
{
** power of 2 cache line size.
** Enhanced in linux-2.3.44 to provide a memory pool
** per pcidev to support dynamic dma mapping. (I would
-** have preferred a real bus astraction, btw).
+** have preferred a real bus abstraction, btw).
**
**==========================================================
*/
** The first four bytes (scr_st[4]) are used inside the script by
** "COPY" commands.
** Because source and destination must have the same alignment
-** in a DWORD, the fields HAVE to be at the choosen offsets.
+** in a DWORD, the fields HAVE to be at the chosen offsets.
** xerr_st 0 (0x34) scratcha
** sync_st 1 (0x05) sxfer
** wide_st 3 (0x03) scntl3
** the DSA (data structure address) register points
** to this substructure of the ccb.
** This substructure contains the header with
-** the script-processor-changable data and
+** the script-processor-changeable data and
** data blocks for the indirect move commands.
**
**----------------------------------------------------------
/*
** This CCB has been skipped by the NCR.
-** Queue it in the correponding unit queue.
+** Queue it in the corresponding unit queue.
*/
static void ncr_ccb_skipped(struct ncb *np, struct ccb *cp)
{
**
** In normal cases, interrupt conditions occur one at a
** time. The ncr is able to stack in some extra registers
-** other interrupts that will occurs after the first one.
-** But severall interrupts may occur at the same time.
+** other interrupts that will occur after the first one.
+** But, several interrupts may occur at the same time.
**
** We probably should only try to deal with the normal
** case, but it seems that multiple interrupts occur in
** The host status field is set to HS_NEGOTIATE to mark this
** situation.
**
-** If the target doesn't answer this message immidiately
+** If the target doesn't answer this message immediately
** (as required by the standard), the SIR_NEGO_FAIL interrupt
** will be raised eventually.
** The handler removes the HS_NEGOTIATE status, and sets the
** Same as option 1, but also deal with
** misconfigured interrupts.
**
-** - Edge triggerred instead of level sensitive.
+** - Edge triggered instead of level sensitive.
** - No interrupt line connected.
** - IRQ number misconfigured.
**
/*
** Initial setup.
-** Can be overriden at startup by a command line.
+** Can be overridden at startup by a command line.
*/
#define SCSI_NCR_DRIVER_SETUP \
{ \
**-----------------------------------------------------------
** On 810A, 860, 825A, 875, 895 and 896 chips the content
** of SFBR register can be used as data (SCR_SFBR_DATA).
-** The 896 has additionnal IO registers starting at
+** The 896 has additional IO registers starting at
** offset 0x80. Bit 7 of register offset is stored in
** bit 7 of the SCRIPTS instruction first DWORD.
**-----------------------------------------------------------
int usb_ftdi_elan_write_pcimem(struct platform_device *pdev, u8 addressofs,
u8 width, u32 data);
/*
-* these can not be inlines because we need the structure offset!!
+* these cannot be inlines because we need the structure offset!!
* Does anyone have a better way?????
*/
#define u132_read_pcimem(u132, member, data) \
* This function may be called by the USB core whilst the "usb_all_devices_rwsem"
* is held for writing, thus this module must not call usb_remove_hcd()
* synchronously - but instead should immediately stop activity to the
-* device and ansynchronously call usb_remove_hcd()
+* device and asynchronously call usb_remove_hcd()
*/
static int __devexit u132_remove(struct platform_device *pdev)
{
#define u132_resume NULL
#endif
/*
-* this driver is loaded explicitely by ftdi_u132
+* this driver is loaded explicitly by ftdi_u132
*
* the platform_driver struct is static because it is per type of module
*/
* the kernel to load the "u132-hcd" module.
*
* The "ftdi-u132" module provides the interface to the inserted
-* PC card and the "u132-hcd" module uses the API to send and recieve
+* PC card and the "u132-hcd" module uses the API to send and receive
* data. The API features call-backs, so that part of the "u132-hcd"
* module code will run in the context of one of the kernel threads
* of the "ftdi-u132" module.
* to TASK_RUNNING will be lost and write_chan's subsequent call to
* schedule() will never return (unless it catches a signal).
* This race condition occurs because write_bulk_callback() (and thus
-* the wakeup) are called asynchonously from an interrupt, rather than
+* the wakeup) are called asynchronously from an interrupt, rather than
* from the scheduler. We can avoid the race by calling the wakeup
* from the scheduler queue and that's our fix: Now, at the end of
* write_bulk_callback() we queue up a wakeup call on the scheduler
}
/* if someone has this block in a newer transaction, just make
- ** sure they are commited, and don't try writing it to disk
+ ** sure they are committed, and don't try writing it to disk
*/
if (pjl) {
if (atomic_read(&pjl->j_commit_left))
/*
** for any cnode in a journal list, it can only be dirtied of all the
-** transactions that include it are commited to disk.
+** transactions that include it are committed to disk.
** this checks through each transaction, and returns 1 if you are allowed to dirty,
** and 0 if you aren't
**
}
/* syncs the commit blocks, but does not force the real buffers to disk
-** will wait until the current transaction is done/commited before returning
+** will wait until the current transaction is done/committed before returning
*/
int journal_end_sync(struct reiserfs_transaction_handle *th,
struct super_block *p_s_sb, unsigned long nblocks)
#define MCFMBUS_MFDR_MBC(a) ((a)&0x3F) /*M-Bus Clock*/
/*
-* Define bit flags in Controll Register
+* Define bit flags in Control Register
*/
#define MCFMBUS_MBCR_MEN (0x80) /* M-Bus Enable */
/*
** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up
-** (or rather not merge) DMA's into managable chunks.
+** (or rather not merge) DMAs into manageable chunks.
** On parisc, this is more of the software/tuning constraint
-** rather than the HW. I/O MMU allocation alogorithms can be
-** faster with smaller size is (to some degree).
+** rather than the HW. I/O MMU allocation algorithms can be
+** faster with smaller sizes (to some degree).
*/
#define DMA_CHUNK_SIZE (BITS_PER_LONG*PAGE_SIZE)
/*
** Most PCI devices (eg Tulip, NCR720) also export the same registers
** to both MMIO and I/O port space. Due to poor performance of I/O Port
-** access under HP PCI bus adapters, strongly reccomend use of MMIO
+** access under HP PCI bus adapters, strongly recommend the use of MMIO
** address space.
**
** While I'm at it more PA programming notes:
#endif
/*
-** The number of pdir entries to "free" before issueing
+** The number of pdir entries to "free" before issuing
** a read to PCOM register to flush out PCOM writes.
** Interacts with allocation granularity (ie 4 or 8 entries
** allocated and free'd/purged at a time might make this
* structures. If the freq0 variable is non-zero, the tone table contents
* for the tone_index are updated to the frequencies and gains defined. It
* should be noted that DTMF tones cannot be reassigned, so if DTMF tone
-* table indexs are used in a cadence the frequency and gain variables will
+* table indexes are used in a cadence the frequency and gain variables will
* be ignored.
*
* If the array elements contain frequency parameters the driver will
/* -o hash={tea, rupasov, r5, detect} is meant for properly mounting
** reiserfs disks from 3.5.19 or earlier. 99% of the time, this option
** is not required. If the normal autodection code can't determine which
-** hash to use (because both hases had the same value for a file)
+** hash to use (because both hashes had the same value for a file)
** use this option to force a specific hash. It won't allow you to override
** the existing hash on the FS, so if you have a tea hash disk, and mount
** with -o hash=rupasov, the mount will fail.
* Due Credit:
* Wanpipe socket layer is based on Packet and
* the X25 socket layers. The above sockets were
-* used for the specific use of Sangoma Technoloiges
+* used for the specific use of Sangoma Technologies
* API programs.
* Packet socket Authors: Ross Biro, Fred N. van Kempen and
* Alan Cox.
* Apr 25, 2000 Nenad Corbic o Added the ability to send zero length packets.
* Mar 13, 2000 Nenad Corbic o Added a tx buffer check via ioctl call.
* Mar 06, 2000 Nenad Corbic o Fixed the corrupt sock lcn problem.
-* Server and client applicaton can run
+* Server and client application can run
* simultaneously without conflicts.
* Feb 29, 2000 Nenad Corbic o Added support for PVC protocols, such as
* CHDLC, Frame Relay and HDLC API.
*
* This module is completely hardware-independent and provides
* the following common services for the WAN Link Drivers:
-* o WAN device managenment (registering, unregistering)
+* o WAN device management (registering, unregistering)
* o Network interface management
* o Physical connection management (dial-up, incoming calls)
* o Logical connection management (switched virtual circuits)
rate = 48000 / 9;
/*
- * We can not capture at at rate greater than the Input Rate (48000).
+ * We cannot capture at at rate greater than the Input Rate (48000).
* Return an error if an attempt is made to stray outside that limit.
*/
if (rate > 48000)
mdelay(5 * cs_laptop_wait); /* Shouldnt be needed ?? */
/*
-* If we are resuming under 2.2.x then we can not schedule a timeout.
-* so, just spin the CPU.
+* If we are resuming under 2.2.x then we cannot schedule a timeout,
+* so just spin the CPU.
*/
if (card->pm.flags & CS46XX_PM_IDLE) {
/*
projects / linux-drm-fsl-dcu.git / commitdiff