MIPS: Fix a preemption issue with thread's FPU defaults
authorMaciej W. Rozycki <macro@linux-mips.org>
Tue, 12 May 2015 14:20:57 +0000 (15:20 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Tue, 12 May 2015 21:15:49 +0000 (23:15 +0200)
Fix "BUG: using smp_processor_id() in preemptible" reported in accesses
to thread's FPU defaults: the value to initialise FSCR to at program
startup, the FCSR r/w mask and the contents of FIR in full FPU
emulation, removing a regression introduced with 9b26616c [MIPS: Respect
the ISA level in FCSR handling] and f6843626 [MIPS: math-emu: Set FIR
feature flags for full emulation].

Use `boot_cpu_data' to obtain the data from, following the approach that
`cpu_has_*' macros take and avoiding the call to `smp_processor_id' made
in the reference to `current_cpu_data'.  The contents of FSCR have to be
consistent across processors in an SMP system, the settings there must
not change as a thread is migrated across processors.  And the contents
of FIR are guaranteed to be consistent in FPU emulation, by definition.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Tested-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Tested-by: Paul Martin <paul.martin@codethink.co.uk>
Cc: Markos Chandras <Markos.Chandras@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10030/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/elf.h
arch/mips/kernel/ptrace.c
arch/mips/math-emu/cp1emu.c

index a594d8ed96980cd1e96c8bf3eb593368203fe53c..f19e890b99d2744ae4984ea54e2ca9e5128ce7fe 100644 (file)
@@ -304,7 +304,7 @@ do {                                                                        \
                                                                        \
        current->thread.abi = &mips_abi;                                \
                                                                        \
-       current->thread.fpu.fcr31 = current_cpu_data.fpu_csr31;         \
+       current->thread.fpu.fcr31 = boot_cpu_data.fpu_csr31;            \
 } while (0)
 
 #endif /* CONFIG_32BIT */
@@ -366,7 +366,7 @@ do {                                                                        \
        else                                                            \
                current->thread.abi = &mips_abi;                        \
                                                                        \
-       current->thread.fpu.fcr31 = current_cpu_data.fpu_csr31;         \
+       current->thread.fpu.fcr31 = boot_cpu_data.fpu_csr31;            \
                                                                        \
        p = personality(current->personality);                          \
        if (p != PER_LINUX32 && p != PER_LINUX)                         \
index d544e774eea6b1b6e0f811099290600b1fc5b534..e933a309f2ea5fa4498153a9b6a3caa0af4a1587 100644 (file)
@@ -176,7 +176,7 @@ int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
 
        __get_user(value, data + 64);
        fcr31 = child->thread.fpu.fcr31;
-       mask = current_cpu_data.fpu_msk31;
+       mask = boot_cpu_data.fpu_msk31;
        child->thread.fpu.fcr31 = (value & ~mask) | (fcr31 & mask);
 
        /* FIR may not be written.  */
index d31c537ace1d11b7f742fd9ead71d3f273cfa2d3..22b9b2cb9219fa4e4eb7b9cc340125a4c9aa4053 100644 (file)
@@ -889,7 +889,7 @@ static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                break;
 
        case FPCREG_RID:
-               value = current_cpu_data.fpu_id;
+               value = boot_cpu_data.fpu_id;
                break;
 
        default:
@@ -921,7 +921,7 @@ static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                         (void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
 
                /* Preserve read-only bits.  */
-               mask = current_cpu_data.fpu_msk31;
+               mask = boot_cpu_data.fpu_msk31;
                fcr31 = (value & ~mask) | (fcr31 & mask);
                break;