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MIPS: mm: scache: Add secondary cache support for MIPS R6 cores
authorMarkos Chandras <markos.chandras@imgtec.com>
Thu, 15 Jan 2015 10:28:29 +0000 (10:28 +0000)
committerMarkos Chandras <markos.chandras@imgtec.com>
Tue, 17 Feb 2015 15:37:31 +0000 (15:37 +0000)
commitb5ad2c21934951bbf6aadd8adbdd9889baad0ac0
tree23c9d24715f1e3f8da4936f41fccb4217cb5a0d1tree | snapshot
parent4ee486274ec1e63f056c991e2523c32780670d08commit | diff
MIPS: mm: scache: Add secondary cache support for MIPS R6 cores

The secondary cache initialization and configuration code is processor
specific so we need to handle MIPS R6 cores as well.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
arch/mips/mm/c-r4k.c diff | blob | history
arch/mips/mm/sc-mips.c diff | blob | history
Freescale DCU DRM driver