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(parent: ca9f26a) | patch
spi: mediatek: fix spi clock usage error
authorLeilk Liu <leilk.liu@mediatek.com>
Mon, 31 Aug 2015 13:18:57 +0000 (21:18 +0800)
committerMark Brown <broonie@kernel.org>
Mon, 31 Aug 2015 14:26:50 +0000 (15:26 +0100)
commitadcbcfea15d62fab5ba40ac28f9d2a590cc5e5e8
tree5c9d4db20afeb1b95bc03efb49ba3237c4023bcdtree | snapshot
parentca9f26a27949ba3b295e4f0841c0bec9ef440141commit | diff
spi: mediatek: fix spi clock usage error

spi clock manages flow:
  CLK_TOP_SYSPLL3_D2 ---> CLK_TOP_SPI_SEL ---> CLK_PERI_SPI0
     (source clock)           (clock mux)       (clock gate)
spi driver should choose source clock by clock mux, then enable
clock gate.

Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
drivers/spi/spi-mt65xx.c diff | blob | history
Freescale DCU DRM driver