ide: pdc202xx_new PLL input clock fix
authorAlbert Lee <albertcc@tw.ibm.com>
Tue, 3 Jul 2007 20:28:36 +0000 (22:28 +0200)
committerBartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Tue, 3 Jul 2007 20:28:36 +0000 (22:28 +0200)
commit8006bf56e360a4db71d304df778870a371a9e930
tree9471ba5fd85ce42c8ec6253893520371762e513e
parent52374f890c1d0d64148d55a20d995a0b3e0ae987
ide: pdc202xx_new PLL input clock fix

Recently the PLL input clock of Promise 2027x is sometimes detected
higher than expected (e.g. 20.027 MHz compared to 16.714 MHz).
It seems sometimes the mdelay() function is not as precise as it
used to be. Per Alan's advice, HT or power management might affect
the precision of mdelay().

This patch calls gettimeofday() to measure the time elapsed and
calculate the PLL input clock accordingly.

Signed-off-by: Albert Lee <albertcc@tw.ibm.com>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: Bahadir Balban <bahadir.balban@gmail.com>
Acked-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
drivers/ide/pci/pdc202xx_new.c