Pull button into test branch

[linux-drm-fsl-dcu.git] / arch / xtensa / kernel / head.S

diff --git a/arch/xtensa/kernel/head.S b/arch/xtensa/kernel/head.S
index c07cb25229931b1198895c291947c59c8ce3e4e9..ea89910efa44f523e928ffc6a1b33938e5e97d45 100644 (file)
--- a/arch/xtensa/kernel/head.S
+++ b/arch/xtensa/kernel/head.S
@@ -15,9 +15,9 @@
  * Kevin Chea
  */
 
-#include <xtensa/cacheasm.h>
 #include <asm/processor.h>
 #include <asm/page.h>
+#include <asm/cacheasm.h>
 
 /*
  * This module contains the entry code for kernel images. It performs the
@@ -32,13 +32,6 @@
  *
  */
 
-       .macro  iterate from, to , cmd
-               .ifeq   ((\to - \from) & ~0xfff)
-                       \cmd    \from
-                       iterate "(\from+1)", \to, \cmd
-               .endif
-       .endm
-
 /*
  *  _start
  *
@@ -64,7 +57,7 @@ _startup:
 
        /* Disable interrupts and exceptions. */
 
-       movi    a0, XCHAL_PS_EXCM_MASK
+       movi    a0, LOCKLEVEL
        wsr     a0, PS
 
        /* Preserve the pointer to the boot parameter list in EXCSAVE_1 */
@@ -91,11 +84,11 @@ _startup:
        movi    a1, 15
        wsr     a0, ICOUNTLEVEL
 
-       .macro reset_dbreak num
-       wsr     a0, DBREAKC + \num
-       .endm
-
-        iterate 0, XCHAL_NUM_IBREAK-1, reset_dbreak
+       .set    _index, 0
+       .rept   XCHAL_NUM_DBREAK - 1
+       wsr     a0, DBREAKC + _index
+       .set    _index, _index + 1
+       .endr
 #endif
 
        /* Clear CCOUNT (not really necessary, but nice) */
@@ -110,10 +103,11 @@ _startup:
 
        /* Disable all timers. */
 
-       .macro  reset_timer     num
-       wsr     a0, CCOMPARE_0 + \num
-       .endm
-       iterate 0, XCHAL_NUM_TIMERS-1, reset_timer
+       .set    _index, 0
+       .rept   XCHAL_NUM_TIMERS - 1
+       wsr     a0, CCOMPARE + _index
+       .set    _index, _index + 1
+       .endr
 
        /* Interrupt initialization. */
 
@@ -139,12 +133,21 @@ _startup:
        rsync
 
        /*  Initialize the caches.
-        *  Does not include flushing writeback d-cache.
-        *  a6, a7 are just working registers (clobbered).
+        *  a2, a3 are just working registers (clobbered).
         */
 
-       icache_reset  a2, a3
-       dcache_reset  a2, a3
+#if XCHAL_DCACHE_LINE_LOCKABLE
+       ___unlock_dcache_all a2 a3
+#endif
+
+#if XCHAL_ICACHE_LINE_LOCKABLE
+       ___unlock_icache_all a2 a3
+#endif
+
+       ___invalidate_dcache_all a2 a3
+       ___invalidate_icache_all a2 a3
+
+       isync
 
        /* Unpack data sections
         *
@@ -181,9 +184,9 @@ _startup:
        movi    a2, _bss_start  # start of BSS
        movi    a3, _bss_end    # end of BSS
 
-1:     addi    a2, a2, 4
+       __loopt a2, a3, a4, 2
        s32i    a0, a2, 0
-       blt     a2, a3, 1b
+       __endla a2, a4, 4
 
 #if XCHAL_DCACHE_IS_WRITEBACK
 
@@ -191,7 +194,7 @@ _startup:
         * instructions/data are available.
         */
 
-       dcache_writeback_all    a2, a3
+       ___flush_dcache_all a2 a3
 #endif
 
        /* Setup stack and enable window exceptions (keep irqs disabled) */