-/* $Id: pci_sabre.c,v 1.42 2002/01/23 11:27:32 davem Exp $
- * pci_sabre.c: Sabre specific PCI controller support.
+/* pci_sabre.c: Sabre specific PCI controller support.
*
- * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
+ * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
* Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
* Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
*/
return 0;
return ((pbm->parent == 0) ||
- ((pbm == &pbm->parent->pbm_B) &&
- (bus == pbm->pci_first_busno) &&
- PCI_SLOT(devfn) > 8) ||
((pbm == &pbm->parent->pbm_A) &&
(bus == pbm->pci_first_busno) &&
PCI_SLOT(devfn) > 8));
static int sabre_read_pci_cfg(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *value)
{
+ struct pci_pbm_info *pbm = bus->sysdata;
+
+ if (bus == pbm->pci_bus && devfn == 0x00)
+ return pci_host_bridge_read_pci_cfg(bus, devfn, where,
+ size, value);
+
if (!bus->number && sabre_out_of_range(devfn)) {
switch (size) {
case 1:
static int sabre_write_pci_cfg(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 value)
{
+ struct pci_pbm_info *pbm = bus->sysdata;
+
+ if (bus == pbm->pci_bus && devfn == 0x00)
+ return pci_host_bridge_write_pci_cfg(bus, devfn, where,
+ size, value);
+
if (bus->number)
return __sabre_write_pci_cfg(bus, devfn, where, size, value);
unsigned long afsr,
unsigned long afar)
{
- struct pci_iommu *iommu = p->pbm_A.iommu;
+ struct iommu *iommu = p->pbm_A.iommu;
unsigned long iommu_tag[16];
unsigned long iommu_data[16];
unsigned long flags;
spin_unlock_irqrestore(&iommu->lock, flags);
}
-static irqreturn_t sabre_ue_intr(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
{
struct pci_controller_info *p = dev_id;
unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_UE_AFSR;
return IRQ_HANDLED;
}
-static irqreturn_t sabre_ce_intr(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
{
struct pci_controller_info *p = dev_id;
unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_CE_AFSR;
p->index);
ret = IRQ_HANDLED;
}
- pci_read_config_word(sabre_root_bus->self,
- PCI_STATUS, &stat);
+ pci_bus_read_config_word(sabre_root_bus, 0,
+ PCI_STATUS, &stat);
if (stat & (PCI_STATUS_PARITY |
PCI_STATUS_SIG_TARGET_ABORT |
PCI_STATUS_REC_TARGET_ABORT |
PCI_STATUS_SIG_SYSTEM_ERROR)) {
printk("SABRE%d: PCI bus error, PCI_STATUS[%04x]\n",
p->index, stat);
- pci_write_config_word(sabre_root_bus->self,
- PCI_STATUS, 0xffff);
+ pci_bus_write_config_word(sabre_root_bus, 0,
+ PCI_STATUS, 0xffff);
ret = IRQ_HANDLED;
}
return ret;
}
-static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id)
{
struct pci_controller_info *p = dev_id;
unsigned long afsr_reg, afar_reg;
if (error_bits & (SABRE_PIOAFSR_PTA | SABRE_PIOAFSR_STA)) {
sabre_check_iommu_error(p, afsr, afar);
pci_scan_for_target_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
- pci_scan_for_target_abort(p, &p->pbm_B, p->pbm_B.pci_bus);
}
- if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA)) {
+ if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA))
pci_scan_for_master_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
- pci_scan_for_master_abort(p, &p->pbm_B, p->pbm_B.pci_bus);
- }
+
/* For excessive retries, SABRE/PBM will abort the device
* and there is no way to specifically check for excessive
* retries in the config space status registers. So what
* abort events.
*/
- if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR)) {
+ if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR))
pci_scan_for_parity_error(p, &p->pbm_A, p->pbm_A.pci_bus);
- pci_scan_for_parity_error(p, &p->pbm_B, p->pbm_B.pci_bus);
- }
return IRQ_HANDLED;
}
sabre_write(base + SABRE_PCICTRL, tmp);
}
-static void sabre_resource_adjust(struct pci_dev *pdev,
- struct resource *res,
- struct resource *root)
-{
- struct pci_pbm_info *pbm = pdev->bus->sysdata;
- unsigned long base;
-
- if (res->flags & IORESOURCE_IO)
- base = pbm->controller_regs + SABRE_IOSPACE;
- else
- base = pbm->controller_regs + SABRE_MEMSPACE;
-
- res->start += base;
- res->end += base;
-}
-
-static void sabre_base_address_update(struct pci_dev *pdev, int resource)
-{
- struct pcidev_cookie *pcp = pdev->sysdata;
- struct pci_pbm_info *pbm = pcp->pbm;
- struct resource *res;
- unsigned long base;
- u32 reg;
- int where, size, is_64bit;
-
- res = &pdev->resource[resource];
- if (resource < 6) {
- where = PCI_BASE_ADDRESS_0 + (resource * 4);
- } else if (resource == PCI_ROM_RESOURCE) {
- where = pdev->rom_base_reg;
- } else {
- /* Somebody might have asked allocation of a non-standard resource */
- return;
- }
-
- is_64bit = 0;
- if (res->flags & IORESOURCE_IO)
- base = pbm->controller_regs + SABRE_IOSPACE;
- else {
- base = pbm->controller_regs + SABRE_MEMSPACE;
- if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
- == PCI_BASE_ADDRESS_MEM_TYPE_64)
- is_64bit = 1;
- }
-
- size = res->end - res->start;
- pci_read_config_dword(pdev, where, ®);
- reg = ((reg & size) |
- (((u32)(res->start - base)) & ~size));
- if (resource == PCI_ROM_RESOURCE) {
- reg |= PCI_ROM_ADDRESS_ENABLE;
- res->flags |= IORESOURCE_ROM_ENABLE;
- }
- pci_write_config_dword(pdev, where, reg);
-
- /* This knows that the upper 32-bits of the address
- * must be zero. Our PCI common layer enforces this.
- */
- if (is_64bit)
- pci_write_config_dword(pdev, where + 4, 0);
-}
-
static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus)
{
struct pci_dev *pdev;
list_for_each_entry(pdev, &sabre_bus->devices, bus_list) {
-
if (pdev->vendor == PCI_VENDOR_ID_SUN &&
pdev->device == PCI_DEVICE_ID_SUN_SIMBA) {
- u32 word32;
u16 word16;
- sabre_read_pci_cfg(pdev->bus, pdev->devfn,
- PCI_COMMAND, 2, &word32);
- word16 = (u16) word32;
+ pci_read_config_word(pdev, PCI_COMMAND, &word16);
word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
PCI_COMMAND_IO;
- word32 = (u32) word16;
- sabre_write_pci_cfg(pdev->bus, pdev->devfn,
- PCI_COMMAND, 2, word32);
+ pci_write_config_word(pdev, PCI_COMMAND, word16);
/* Status register bits are "write 1 to clear". */
- sabre_write_pci_cfg(pdev->bus, pdev->devfn,
- PCI_STATUS, 2, 0xffff);
- sabre_write_pci_cfg(pdev->bus, pdev->devfn,
- PCI_SEC_STATUS, 2, 0xffff);
+ pci_write_config_word(pdev, PCI_STATUS, 0xffff);
+ pci_write_config_word(pdev, PCI_SEC_STATUS, 0xffff);
/* Use a primary/seconday latency timer value
* of 64.
*/
- sabre_write_pci_cfg(pdev->bus, pdev->devfn,
- PCI_LATENCY_TIMER, 1, 64);
- sabre_write_pci_cfg(pdev->bus, pdev->devfn,
- PCI_SEC_LATENCY_TIMER, 1, 64);
+ pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
+ pci_write_config_byte(pdev, PCI_SEC_LATENCY_TIMER, 64);
/* Enable reporting/forwarding of master aborts,
* parity, and SERR.
*/
- sabre_write_pci_cfg(pdev->bus, pdev->devfn,
- PCI_BRIDGE_CONTROL, 1,
- (PCI_BRIDGE_CTL_PARITY |
- PCI_BRIDGE_CTL_SERR |
- PCI_BRIDGE_CTL_MASTER_ABORT));
+ pci_write_config_byte(pdev, PCI_BRIDGE_CONTROL,
+ (PCI_BRIDGE_CTL_PARITY |
+ PCI_BRIDGE_CTL_SERR |
+ PCI_BRIDGE_CTL_MASTER_ABORT));
}
}
}
-static struct pcidev_cookie *alloc_bridge_cookie(struct pci_pbm_info *pbm)
-{
- struct pcidev_cookie *cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
-
- if (!cookie) {
- prom_printf("SABRE: Critical allocation failure.\n");
- prom_halt();
- }
-
- /* All we care about is the PBM. */
- cookie->pbm = pbm;
-
- return cookie;
-}
-
static void sabre_scan_bus(struct pci_controller_info *p)
{
static int once;
- struct pci_bus *sabre_bus, *pbus;
- struct pci_pbm_info *pbm;
- struct pcidev_cookie *cookie;
- int sabres_scanned;
+ struct pci_bus *pbus;
/* The APB bridge speaks to the Sabre host PCI bridge
* at 66Mhz, but the front side of APB runs at 33Mhz
* for both segments.
*/
p->pbm_A.is_66mhz_capable = 0;
- p->pbm_B.is_66mhz_capable = 0;
/* This driver has not been verified to handle
* multiple SABREs yet, so trap this.
}
once++;
- cookie = alloc_bridge_cookie(&p->pbm_A);
-
- sabre_bus = pci_scan_bus(p->pci_first_busno,
- p->pci_ops,
- &p->pbm_A);
- pci_fixup_host_bridge_self(sabre_bus);
- sabre_bus->self->sysdata = cookie;
-
- sabre_root_bus = sabre_bus;
-
- apb_init(p, sabre_bus);
-
- sabres_scanned = 0;
-
- list_for_each_entry(pbus, &sabre_bus->children, node) {
-
- if (pbus->number == p->pbm_A.pci_first_busno) {
- pbm = &p->pbm_A;
- } else if (pbus->number == p->pbm_B.pci_first_busno) {
- pbm = &p->pbm_B;
- } else
- continue;
-
- cookie = alloc_bridge_cookie(pbm);
- pbus->self->sysdata = cookie;
-
- sabres_scanned++;
+ pbus = pci_scan_one_pbm(&p->pbm_A);
+ if (!pbus)
+ return;
- pbus->sysdata = pbm;
- pbm->pci_bus = pbus;
- pci_fill_in_pbm_cookies(pbus, pbm, pbm->prom_node);
- pci_record_assignments(pbm, pbus);
- pci_assign_unassigned(pbm, pbus);
- pci_fixup_irq(pbm, pbus);
- pci_determine_66mhz_disposition(pbm, pbus);
- pci_setup_busmastering(pbm, pbus);
- }
+ sabre_root_bus = pbus;
- if (!sabres_scanned) {
- /* Hummingbird, no APBs. */
- pbm = &p->pbm_A;
- sabre_bus->sysdata = pbm;
- pbm->pci_bus = sabre_bus;
- pci_fill_in_pbm_cookies(sabre_bus, pbm, pbm->prom_node);
- pci_record_assignments(pbm, sabre_bus);
- pci_assign_unassigned(pbm, sabre_bus);
- pci_fixup_irq(pbm, sabre_bus);
- pci_determine_66mhz_disposition(pbm, sabre_bus);
- pci_setup_busmastering(pbm, sabre_bus);
- }
+ apb_init(p, pbus);
sabre_register_error_handlers(p);
}
int tsbsize, unsigned long dvma_offset,
u32 dma_mask)
{
- struct pci_iommu *iommu = p->pbm_A.iommu;
+ struct iommu *iommu = p->pbm_A.iommu;
unsigned long i;
u64 control;
sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
}
-static void pbm_register_toplevel_resources(struct pci_controller_info *p,
- struct pci_pbm_info *pbm)
-{
- char *name = pbm->name;
- unsigned long ibase = p->pbm_A.controller_regs + SABRE_IOSPACE;
- unsigned long mbase = p->pbm_A.controller_regs + SABRE_MEMSPACE;
- unsigned int devfn;
- unsigned long first, last, i;
- u8 *addr, map;
-
- sprintf(name, "SABRE%d PBM%c",
- p->index,
- (pbm == &p->pbm_A ? 'A' : 'B'));
- pbm->io_space.name = pbm->mem_space.name = name;
-
- devfn = PCI_DEVFN(1, (pbm == &p->pbm_A) ? 0 : 1);
- addr = sabre_pci_config_mkaddr(pbm, 0, devfn, APB_IO_ADDRESS_MAP);
- map = 0;
- pci_config_read8(addr, &map);
-
- first = 8;
- last = 0;
- for (i = 0; i < 8; i++) {
- if ((map & (1 << i)) != 0) {
- if (first > i)
- first = i;
- if (last < i)
- last = i;
- }
- }
- pbm->io_space.start = ibase + (first << 21UL);
- pbm->io_space.end = ibase + (last << 21UL) + ((1 << 21UL) - 1);
- pbm->io_space.flags = IORESOURCE_IO;
-
- addr = sabre_pci_config_mkaddr(pbm, 0, devfn, APB_MEM_ADDRESS_MAP);
- map = 0;
- pci_config_read8(addr, &map);
-
- first = 8;
- last = 0;
- for (i = 0; i < 8; i++) {
- if ((map & (1 << i)) != 0) {
- if (first > i)
- first = i;
- if (last < i)
- last = i;
- }
- }
- pbm->mem_space.start = mbase + (first << 29UL);
- pbm->mem_space.end = mbase + (last << 29UL) + ((1 << 29UL) - 1);
- pbm->mem_space.flags = IORESOURCE_MEM;
-
- if (request_resource(&ioport_resource, &pbm->io_space) < 0) {
- prom_printf("Cannot register PBM-%c's IO space.\n",
- (pbm == &p->pbm_A ? 'A' : 'B'));
- prom_halt();
- }
- if (request_resource(&iomem_resource, &pbm->mem_space) < 0) {
- prom_printf("Cannot register PBM-%c's MEM space.\n",
- (pbm == &p->pbm_A ? 'A' : 'B'));
- prom_halt();
- }
-
- /* Register legacy regions if this PBM covers that area. */
- if (pbm->io_space.start == ibase &&
- pbm->mem_space.start == mbase)
- pci_register_legacy_regions(&pbm->io_space,
- &pbm->mem_space);
-}
-
-static void sabre_pbm_init(struct pci_controller_info *p, struct device_node *dp, u32 dma_begin)
+static void sabre_pbm_init(struct pci_controller_info *p, struct device_node *dp)
{
struct pci_pbm_info *pbm;
- struct device_node *node;
- struct property *prop;
- u32 *busrange;
- int len, simbas_found;
-
- simbas_found = 0;
- node = dp->child;
- while (node != NULL) {
- if (strcmp(node->name, "pci"))
- goto next_pci;
-
- prop = of_find_property(node, "model", NULL);
- if (!prop || strncmp(prop->value, "SUNW,simba", prop->length))
- goto next_pci;
-
- simbas_found++;
-
- prop = of_find_property(node, "bus-range", NULL);
- busrange = prop->value;
- if (busrange[0] == 1)
- pbm = &p->pbm_B;
- else
- pbm = &p->pbm_A;
-
- pbm->name = node->full_name;
- printk("%s: SABRE PCI Bus Module\n", pbm->name);
-
- pbm->chip_type = PBM_CHIP_TYPE_SABRE;
- pbm->parent = p;
- pbm->prom_node = node;
- pbm->pci_first_slot = 1;
- pbm->pci_first_busno = busrange[0];
- pbm->pci_last_busno = busrange[1];
-
- prop = of_find_property(node, "ranges", &len);
- if (prop) {
- pbm->pbm_ranges = prop->value;
- pbm->num_pbm_ranges =
- (len / sizeof(struct linux_prom_pci_ranges));
- } else {
- pbm->num_pbm_ranges = 0;
- }
- prop = of_find_property(node, "interrupt-map", &len);
- if (prop) {
- pbm->pbm_intmap = prop->value;
- pbm->num_pbm_intmap =
- (len / sizeof(struct linux_prom_pci_intmap));
-
- prop = of_find_property(node, "interrupt-map-mask",
- NULL);
- pbm->pbm_intmask = prop->value;
- } else {
- pbm->num_pbm_intmap = 0;
- }
-
- pbm_register_toplevel_resources(p, pbm);
-
- next_pci:
- node = node->sibling;
- }
- if (simbas_found == 0) {
- /* No APBs underneath, probably this is a hummingbird
- * system.
- */
- pbm = &p->pbm_A;
- pbm->parent = p;
- pbm->prom_node = dp;
- pbm->pci_first_busno = p->pci_first_busno;
- pbm->pci_last_busno = p->pci_last_busno;
-
- prop = of_find_property(dp, "ranges", &len);
- if (prop) {
- pbm->pbm_ranges = prop->value;
- pbm->num_pbm_ranges =
- (len / sizeof(struct linux_prom_pci_ranges));
- } else {
- pbm->num_pbm_ranges = 0;
- }
-
- prop = of_find_property(dp, "interrupt-map", &len);
- if (prop) {
- pbm->pbm_intmap = prop->value;
- pbm->num_pbm_intmap =
- (len / sizeof(struct linux_prom_pci_intmap));
-
- prop = of_find_property(dp, "interrupt-map-mask",
- NULL);
- pbm->pbm_intmask = prop->value;
- } else {
- pbm->num_pbm_intmap = 0;
- }
-
- pbm->name = dp->full_name;
- printk("%s: SABRE PCI Bus Module\n", pbm->name);
-
- pbm->io_space.name = pbm->mem_space.name = pbm->name;
+ pbm = &p->pbm_A;
+ pbm->name = dp->full_name;
+ printk("%s: SABRE PCI Bus Module\n", pbm->name);
- /* Hack up top-level resources. */
- pbm->io_space.start = p->pbm_A.controller_regs + SABRE_IOSPACE;
- pbm->io_space.end = pbm->io_space.start + (1UL << 24) - 1UL;
- pbm->io_space.flags = IORESOURCE_IO;
+ pbm->chip_type = PBM_CHIP_TYPE_SABRE;
+ pbm->parent = p;
+ pbm->prom_node = dp;
+ pbm->pci_first_busno = p->pci_first_busno;
+ pbm->pci_last_busno = p->pci_last_busno;
- pbm->mem_space.start = p->pbm_A.controller_regs + SABRE_MEMSPACE;
- pbm->mem_space.end = pbm->mem_space.start + (unsigned long)dma_begin - 1UL;
- pbm->mem_space.flags = IORESOURCE_MEM;
-
- if (request_resource(&ioport_resource, &pbm->io_space) < 0) {
- prom_printf("Cannot register Hummingbird's IO space.\n");
- prom_halt();
- }
- if (request_resource(&iomem_resource, &pbm->mem_space) < 0) {
- prom_printf("Cannot register Hummingbird's MEM space.\n");
- prom_halt();
- }
-
- pci_register_legacy_regions(&pbm->io_space,
- &pbm->mem_space);
- }
+ pci_determine_mem_io_space(pbm);
}
void sabre_init(struct device_node *dp, char *model_name)
{
- struct linux_prom64_registers *pr_regs;
+ const struct linux_prom64_registers *pr_regs;
struct pci_controller_info *p;
- struct pci_iommu *iommu;
- struct property *prop;
+ struct iommu *iommu;
int tsbsize;
- u32 *busrange;
- u32 *vdma;
+ const u32 *busrange;
+ const u32 *vdma;
u32 upa_portid, dma_mask;
u64 clear_irq;
if (!strcmp(model_name, "pci108e,a001"))
hummingbird_p = 1;
else if (!strcmp(model_name, "SUNW,sabre")) {
- prop = of_find_property(dp, "compatible", NULL);
- if (prop) {
- const char *compat = prop->value;
-
- if (!strcmp(compat, "pci108e,a001"))
- hummingbird_p = 1;
- }
+ const char *compat = of_get_property(dp, "compatible", NULL);
+ if (compat && !strcmp(compat, "pci108e,a001"))
+ hummingbird_p = 1;
if (!hummingbird_p) {
struct device_node *dp;
prom_printf("SABRE: Error, kmalloc(pci_iommu) failed.\n");
prom_halt();
}
- p->pbm_A.iommu = p->pbm_B.iommu = iommu;
+ p->pbm_A.iommu = iommu;
- upa_portid = 0xff;
- prop = of_find_property(dp, "upa-portid", NULL);
- if (prop)
- upa_portid = *(u32 *) prop->value;
+ upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
p->next = pci_controller_root;
pci_controller_root = p;
p->pbm_A.portid = upa_portid;
- p->pbm_B.portid = upa_portid;
p->index = pci_num_controllers++;
- p->pbms_same_domain = 1;
p->scan_bus = sabre_scan_bus;
- p->base_address_update = sabre_base_address_update;
- p->resource_adjust = sabre_resource_adjust;
p->pci_ops = &sabre_ops;
/*
* Map in SABRE register set and report the presence of this SABRE.
*/
- prop = of_find_property(dp, "reg", NULL);
- pr_regs = prop->value;
+ pr_regs = of_get_property(dp, "reg", NULL);
/*
* First REG in property is base of entire SABRE register space.
*/
p->pbm_A.controller_regs = pr_regs[0].phys_addr;
- p->pbm_B.controller_regs = pr_regs[0].phys_addr;
/* Clear interrupts */
SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN));
/* Now map in PCI config space for entire SABRE. */
- p->pbm_A.config_space = p->pbm_B.config_space =
+ p->pbm_A.config_space =
(p->pbm_A.controller_regs + SABRE_CONFIGSPACE);
- prop = of_find_property(dp, "virtual-dma", NULL);
- vdma = prop->value;
+ vdma = of_get_property(dp, "virtual-dma", NULL);
dma_mask = vdma[0];
switch(vdma[1]) {
sabre_iommu_init(p, tsbsize, vdma[0], dma_mask);
- prop = of_find_property(dp, "bus-range", NULL);
- busrange = prop->value;
+ busrange = of_get_property(dp, "bus-range", NULL);
p->pci_first_busno = busrange[0];
p->pci_last_busno = busrange[1];
/*
* Look for APB underneath.
*/
- sabre_pbm_init(p, dp, vdma[0]);
+ sabre_pbm_init(p, dp);
}
projects / linux-drm-fsl-dcu.git / blobdiff