*
* Copyright (C) 2000 Takashi YOSHII
* Copyright (C) 2003, 2004 Paul Mundt
+ * Copyright (C) 2005 Andriy Skulysh
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
-
-#include <linux/config.h>
#include <linux/init.h>
-#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/module.h>
-#include <asm/signal.h>
-#include <asm/irq.h>
+#include <asm/dreamcast/dma.h>
#include <asm/dma.h>
#include <asm/io.h>
#include "dma-sh.h"
-/*
- * The SuperH DMAC supports a number of transmit sizes, we list them here,
- * with their respective values as they appear in the CHCR registers.
- *
- * Defaults to a 64-bit transfer size.
- */
-enum {
- XMIT_SZ_64BIT,
- XMIT_SZ_8BIT,
- XMIT_SZ_16BIT,
- XMIT_SZ_32BIT,
- XMIT_SZ_256BIT,
-};
-
-/*
- * The DMA count is defined as the number of bytes to transfer.
- */
-static unsigned int ts_shift[] = {
- [XMIT_SZ_64BIT] = 3,
- [XMIT_SZ_8BIT] = 0,
- [XMIT_SZ_16BIT] = 1,
- [XMIT_SZ_32BIT] = 2,
- [XMIT_SZ_256BIT] = 5,
-};
-static inline unsigned int get_dmte_irq(unsigned int chan)
-{
- unsigned int irq;
+#ifdef CONFIG_CPU_SH4
+static struct ipr_data dmae_ipr_map[] = {
+ { DMAE_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
+};
+#endif
+static struct ipr_data dmte_ipr_map[] = {
/*
* Normally we could just do DMTE0_IRQ + chan outright, though in the
* case of the 7751R, the DMTE IRQs for channels > 4 start right above
* the SCIF
*/
+ { DMTE0_IRQ + 0, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
+ { DMTE0_IRQ + 1, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
+ { DMTE0_IRQ + 2, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
+ { DMTE0_IRQ + 3, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
+ { DMTE4_IRQ + 0, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
+ { DMTE4_IRQ + 1, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
+ { DMTE4_IRQ + 2, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
+ { DMTE4_IRQ + 3, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
+};
- if (chan < 4) {
- irq = DMTE0_IRQ + chan;
- } else {
- irq = DMTE4_IRQ + chan - 4;
- }
-
+static inline unsigned int get_dmte_irq(unsigned int chan)
+{
+ unsigned int irq = 0;
+ if (chan < ARRAY_SIZE(dmte_ipr_map))
+ irq = dmte_ipr_map[chan].irq;
return irq;
}
{
u32 chcr = ctrl_inl(CHCR[chan->chan]);
- chcr >>= 4;
-
- return ts_shift[chcr & 0x0007];
+ return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT];
}
/*
* Besides that it needs to waken any waiting process, which should handle
* setting up the next transfer.
*/
-static irqreturn_t dma_tei(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t dma_tei(int irq, void *dev_id)
{
- struct dma_channel *chan = (struct dma_channel *)dev_id;
+ struct dma_channel *chan = dev_id;
u32 chcr;
chcr = ctrl_inl(CHCR[chan->chan]);
static int sh_dmac_request_dma(struct dma_channel *chan)
{
+ if (unlikely(!chan->flags & DMA_TEI_CAPABLE))
+ return 0;
+
+ chan->name = kzalloc(32, GFP_KERNEL);
+ if (unlikely(chan->name == NULL))
+ return -ENOMEM;
+ snprintf(chan->name, 32, "DMAC Transfer End (Channel %d)",
+ chan->chan);
+
return request_irq(get_dmte_irq(chan->chan), dma_tei,
- SA_INTERRUPT, "DMAC Transfer End", chan);
+ IRQF_DISABLED, chan->name, chan);
}
static void sh_dmac_free_dma(struct dma_channel *chan)
{
free_irq(get_dmte_irq(chan->chan), chan);
+ kfree(chan->name);
}
-static void sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
+static void
+sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
{
if (!chcr)
- chcr = RS_DUAL;
+ chcr = RS_DUAL | CHCR_IE;
+
+ if (chcr & CHCR_IE) {
+ chcr &= ~CHCR_IE;
+ chan->flags |= DMA_TEI_CAPABLE;
+ } else {
+ chan->flags &= ~DMA_TEI_CAPABLE;
+ }
ctrl_outl(chcr, CHCR[chan->chan]);
static void sh_dmac_enable_dma(struct dma_channel *chan)
{
- int irq = get_dmte_irq(chan->chan);
+ int irq;
u32 chcr;
chcr = ctrl_inl(CHCR[chan->chan]);
- chcr |= CHCR_DE | CHCR_IE;
+ chcr |= CHCR_DE;
+
+ if (chan->flags & DMA_TEI_CAPABLE)
+ chcr |= CHCR_IE;
+
ctrl_outl(chcr, CHCR[chan->chan]);
- enable_irq(irq);
+ if (chan->flags & DMA_TEI_CAPABLE) {
+ irq = get_dmte_irq(chan->chan);
+ enable_irq(irq);
+ }
}
static void sh_dmac_disable_dma(struct dma_channel *chan)
{
- int irq = get_dmte_irq(chan->chan);
+ int irq;
u32 chcr;
- disable_irq(irq);
+ if (chan->flags & DMA_TEI_CAPABLE) {
+ irq = get_dmte_irq(chan->chan);
+ disable_irq(irq);
+ }
chcr = ctrl_inl(CHCR[chan->chan]);
chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
* If we haven't pre-configured the channel with special flags, use
* the defaults.
*/
- if (!(chan->flags & DMA_CONFIGURED))
+ if (unlikely(!(chan->flags & DMA_CONFIGURED)))
sh_dmac_configure_channel(chan, 0);
sh_dmac_disable_dma(chan);
* cascading to the PVR2 DMAC. In this case, we still need to write
* SAR and DAR, regardless of value, in order for cascading to work.
*/
- if (chan->sar || (mach_is_dreamcast() && chan->chan == 2))
+ if (chan->sar || (mach_is_dreamcast() &&
+ chan->chan == PVR2_CASCADE_CHAN))
ctrl_outl(chan->sar, SAR[chan->chan]);
- if (chan->dar || (mach_is_dreamcast() && chan->chan == 2))
+ if (chan->dar || (mach_is_dreamcast() &&
+ chan->chan == PVR2_CASCADE_CHAN))
ctrl_outl(chan->dar, DAR[chan->chan]);
ctrl_outl(chan->count >> calc_xmit_shift(chan), DMATCR[chan->chan]);
return ctrl_inl(DMATCR[chan->chan]) << calc_xmit_shift(chan);
}
-#if defined(CONFIG_CPU_SH4)
-static irqreturn_t dma_err(int irq, void *dev_id, struct pt_regs *regs)
+#ifdef CONFIG_CPU_SUBTYPE_SH7780
+#define dmaor_read_reg() ctrl_inw(DMAOR)
+#define dmaor_write_reg(data) ctrl_outw(data, DMAOR)
+#else
+#define dmaor_read_reg() ctrl_inl(DMAOR)
+#define dmaor_write_reg(data) ctrl_outl(data, DMAOR)
+#endif
+
+static inline int dmaor_reset(void)
{
- unsigned long dmaor = ctrl_inl(DMAOR);
+ unsigned long dmaor = dmaor_read_reg();
+
+ /* Try to clear the error flags first, incase they are set */
+ dmaor &= ~(DMAOR_NMIF | DMAOR_AE);
+ dmaor_write_reg(dmaor);
- printk("DMAE: DMAOR=%lx\n", dmaor);
+ dmaor |= DMAOR_INIT;
+ dmaor_write_reg(dmaor);
- ctrl_outl(ctrl_inl(DMAOR)&~DMAOR_NMIF, DMAOR);
- ctrl_outl(ctrl_inl(DMAOR)&~DMAOR_AE, DMAOR);
- ctrl_outl(ctrl_inl(DMAOR)|DMAOR_DME, DMAOR);
+ /* See if we got an error again */
+ if ((dmaor_read_reg() & (DMAOR_AE | DMAOR_NMIF))) {
+ printk(KERN_ERR "dma-sh: Can't initialize DMAOR.\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+#if defined(CONFIG_CPU_SH4)
+static irqreturn_t dma_err(int irq, void *dummy)
+{
+ dmaor_reset();
disable_irq(irq);
return IRQ_HANDLED;
};
static struct dma_info sh_dmac_info = {
- .name = "SuperH DMAC",
- .nr_channels = 4,
+ .name = "sh_dmac",
+ .nr_channels = CONFIG_NR_ONCHIP_DMA_CHANNELS,
.ops = &sh_dmac_ops,
.flags = DMAC_CHANNELS_TEI_CAPABLE,
};
int i;
#ifdef CONFIG_CPU_SH4
- make_ipr_irq(DMAE_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
- i = request_irq(DMAE_IRQ, dma_err, SA_INTERRUPT, "DMAC Address Error", 0);
- if (i < 0)
+ make_ipr_irq(dmae_ipr_map, ARRAY_SIZE(dmae_ipr_map));
+ i = request_irq(DMAE_IRQ, dma_err, IRQF_DISABLED, "DMAC Address Error", 0);
+ if (unlikely(i < 0))
return i;
#endif
- for (i = 0; i < info->nr_channels; i++) {
- int irq = get_dmte_irq(i);
+ i = info->nr_channels;
+ if (i > ARRAY_SIZE(dmte_ipr_map))
+ i = ARRAY_SIZE(dmte_ipr_map);
+ make_ipr_irq(dmte_ipr_map, i);
- make_ipr_irq(irq, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
- }
-
- ctrl_outl(0x8000 | DMAOR_DME, DMAOR);
+ /*
+ * Initialize DMAOR, and clean up any error flags that may have
+ * been set.
+ */
+ i = dmaor_reset();
+ if (unlikely(i != 0))
+ return i;
return register_dmac(info);
}
#ifdef CONFIG_CPU_SH4
free_irq(DMAE_IRQ, 0);
#endif
+ unregister_dmac(&sh_dmac_info);
}
subsys_initcall(sh_dmac_init);
module_exit(sh_dmac_exit);
+MODULE_AUTHOR("Takashi YOSHII, Paul Mundt, Andriy Skulysh");
+MODULE_DESCRIPTION("SuperH On-Chip DMAC Support");
MODULE_LICENSE("GPL");
-
projects / linux-drm-fsl-dcu.git / blobdiff