Merge branch 'drm-patches' of master.kernel.org:/pub/scm/linux/kernel/git/airlied...

[linux-drm-fsl-dcu.git] / arch / s390 / kernel / head64.S

diff --git a/arch/s390/kernel/head64.S b/arch/s390/kernel/head64.S
index b8fec4e5c5d4ac3bd5e8da5b527901445ee78542..a87b1976d409e3b94a7972998379731d08bcab6a 100644 (file)
--- a/arch/s390/kernel/head64.S
+++ b/arch/s390/kernel/head64.S
@@ -39,7 +39,69 @@ startup_continue:
        basr    %r13,0                  # get base
 .LPG1: sll     %r13,1                  # remove high order bit
        srl     %r13,1
-       lhi     %r1,1                   # mode 1 = esame
+
+#ifdef CONFIG_ZFCPDUMP
+
+       # check if we have been ipled using zfcp dump:
+
+       tm      0xb9,0x01               # test if subchannel is enabled
+       jno     .nodump                 # subchannel disabled
+       l       %r1,0xb8
+       la      %r5,.Lipl_schib-.LPG1(%r13)
+       stsch   0(%r5)                  # get schib of subchannel
+       jne     .nodump                 # schib not available
+       tm      5(%r5),0x01             # devno valid?
+       jno     .nodump
+       tm      4(%r5),0x80             # qdio capable device?
+       jno     .nodump
+       l       %r2,20(%r0)             # address of ipl parameter block
+       lhi     %r3,0
+       ic      %r3,0x148(%r2)          # get opt field
+       chi     %r3,0x20                # load with dump?
+       jne     .nodump
+
+       # store all prefix registers in case of load with dump:
+
+       la      %r7,0                   # base register for 0 page
+       la      %r8,0                   # first cpu
+       l       %r11,.Lpref_arr_ptr-.LPG1(%r13) # address of prefix array
+       ahi     %r11,4                  # skip boot cpu
+       lr      %r12,%r11
+       ahi     %r12,(CONFIG_NR_CPUS*4) # end of prefix array
+       stap    .Lcurrent_cpu+2-.LPG1(%r13)     # store current cpu addr
+1:
+       cl      %r8,.Lcurrent_cpu-.LPG1(%r13)   # is ipl cpu ?
+       je      4f                              # if yes get next cpu
+2:
+       lr      %r9,%r7
+       sigp    %r9,%r8,0x9             # stop & store status of cpu
+       brc     8,3f                    # accepted
+       brc     4,4f                    # status stored: next cpu
+       brc     2,2b                    # busy:          try again
+       brc     1,4f                    # not op:        next cpu
+3:
+       mvc     0(4,%r11),264(%r7)      # copy prefix register to prefix array
+       ahi     %r11,4                  # next element in prefix array
+       clr     %r11,%r12
+       je      5f                      # no more space in prefix array
+4:
+       ahi     %r8,1                           # next cpu (r8 += 1)
+       cl      %r8,.Llast_cpu-.LPG1(%r13)      # is last possible cpu ?
+       jl      1b                              # jump if not last cpu
+5:
+       lhi     %r1,2                   # mode 2 = esame (dump)
+       j       6f
+       .align 4
+.Lipl_schib:
+       .rept 13
+       .long 0
+       .endr
+.nodump:
+       lhi     %r1,1                   # mode 1 = esame (normal ipl)
+6:
+#else
+       lhi     %r1,1                   # mode 1 = esame (normal ipl)
+#endif /* CONFIG_ZFCPDUMP */
        mvi     __LC_AR_MODE_ID,1       # set esame flag
        slr     %r0,%r0                 # set cpuid to zero
        sigp    %r1,%r0,0x12            # switch to esame mode
@@ -134,7 +196,7 @@ startup_continue:
        .quad   .Lduct                  # cr2: dispatchable unit control table
        .quad   0                       # cr3: instruction authorization
        .quad   0                       # cr4: instruction authorization
-       .quad   0xffffffffffffffff      # cr5: primary-aste origin
+       .quad   .Lduct                  # cr5: primary-aste origin
        .quad   0                       # cr6:  I/O interrupts
        .quad   0                       # cr7:  secondary space segment table
        .quad   0                       # cr8:  access registers translation
@@ -145,30 +207,31 @@ startup_continue:
        .quad   0                       # cr13: home space segment table
        .quad   0xc0000000              # cr14: machine check handling off
        .quad   0                       # cr15: linkage stack operations
-.Lduct: .long  0,0,0,0,0,0,0,0
-       .long   0,0,0,0,0,0,0,0
 .Lpcmsk:.quad  0x0000000180000000
 .L4malign:.quad 0xffffffffffc00000
 .Lscan2g:.quad 0x80000000 + 0x20000 - 8        # 2GB + 128K - 8
 .Lnop: .long   0x07000700
+#ifdef CONFIG_ZFCPDUMP
+.Lcurrent_cpu:
+       .long 0x0
+.Llast_cpu:
+       .long 0x0000ffff
+.Lpref_arr_ptr:
+       .long zfcpdump_prefix_array
+#endif /* CONFIG_ZFCPDUMP */
 .Lparmaddr:
        .quad   PARMAREA
-
-       .globl  ipl_schib
-ipl_schib:
-       .rept 13
-       .long 0
+       .align  64
+.Lduct: .long  0,0,0,0,.Lduald,0,0,0
+       .long   0,0,0,0,0,0,0,0
+       .align  128
+.Lduald:.rept  8
+       .long   0x80000000,0,0,0        # invalid access-list entries
        .endr
 
-       .globl  ipl_flags
-ipl_flags:
-       .long   0
-       .globl  ipl_devno
-ipl_devno:
-       .word 0
-
        .org    0x12000
-
+       .globl  _ehead
+_ehead:
 #ifdef CONFIG_SHARED_KERNEL
        .org    0x100000
 #endif