Pull thermal into release branch

[linux-drm-fsl-dcu.git] / arch / powerpc / platforms / cell / spufs / hw_ops.c

diff --git a/arch/powerpc/platforms/cell/spufs/hw_ops.c b/arch/powerpc/platforms/cell/spufs/hw_ops.c
index efc452e71ab0f03b93b4d3178d28cc05ef1200c1..fc4ed1ffbd4ffb379da5e25aad08c78b0bdf7057 100644 (file)
--- a/arch/powerpc/platforms/cell/spufs/hw_ops.c
+++ b/arch/powerpc/platforms/cell/spufs/hw_ops.c
@@ -25,7 +25,6 @@
 #include <linux/mm.h>
 #include <linux/poll.h>
 #include <linux/smp.h>
-#include <linux/smp_lock.h>
 #include <linux/stddef.h>
 #include <linux/unistd.h>
 
@@ -135,21 +134,11 @@ static int spu_hw_wbox_write(struct spu_context *ctx, u32 data)
        return ret;
 }
 
-static u32 spu_hw_signal1_read(struct spu_context *ctx)
-{
-       return in_be32(&ctx->spu->problem->signal_notify1);
-}
-
 static void spu_hw_signal1_write(struct spu_context *ctx, u32 data)
 {
        out_be32(&ctx->spu->problem->signal_notify1, data);
 }
 
-static u32 spu_hw_signal2_read(struct spu_context *ctx)
-{
-       return in_be32(&ctx->spu->problem->signal_notify1);
-}
-
 static void spu_hw_signal2_write(struct spu_context *ctx, u32 data)
 {
        out_be32(&ctx->spu->problem->signal_notify2, data);
@@ -217,21 +206,42 @@ static char *spu_hw_get_ls(struct spu_context *ctx)
        return ctx->spu->local_store;
 }
 
-static void spu_hw_runcntl_write(struct spu_context *ctx, u32 val)
+static u32 spu_hw_runcntl_read(struct spu_context *ctx)
 {
-       eieio();
-       out_be32(&ctx->spu->problem->spu_runcntl_RW, val);
+       return in_be32(&ctx->spu->problem->spu_runcntl_RW);
 }
 
-static void spu_hw_runcntl_stop(struct spu_context *ctx)
+static void spu_hw_runcntl_write(struct spu_context *ctx, u32 val)
 {
        spin_lock_irq(&ctx->spu->register_lock);
-       out_be32(&ctx->spu->problem->spu_runcntl_RW, SPU_RUNCNTL_STOP);
-       while (in_be32(&ctx->spu->problem->spu_status_R) & SPU_STATUS_RUNNING)
-               cpu_relax();
+       if (val & SPU_RUNCNTL_ISOLATE)
+               out_be64(&ctx->spu->priv2->spu_privcntl_RW, 4LL);
+       out_be32(&ctx->spu->problem->spu_runcntl_RW, val);
        spin_unlock_irq(&ctx->spu->register_lock);
 }
 
+static void spu_hw_master_start(struct spu_context *ctx)
+{
+       struct spu *spu = ctx->spu;
+       u64 sr1;
+
+       spin_lock_irq(&spu->register_lock);
+       sr1 = spu_mfc_sr1_get(spu) | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
+       spu_mfc_sr1_set(spu, sr1);
+       spin_unlock_irq(&spu->register_lock);
+}
+
+static void spu_hw_master_stop(struct spu_context *ctx)
+{
+       struct spu *spu = ctx->spu;
+       u64 sr1;
+
+       spin_lock_irq(&spu->register_lock);
+       sr1 = spu_mfc_sr1_get(spu) & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
+       spu_mfc_sr1_set(spu, sr1);
+       spin_unlock_irq(&spu->register_lock);
+}
+
 static int spu_hw_set_mfc_query(struct spu_context * ctx, u32 mask, u32 mode)
 {
        struct spu_problem __iomem *prob = ctx->spu->problem;
@@ -285,15 +295,21 @@ static int spu_hw_send_mfc_command(struct spu_context *ctx,
        }
 }
 
+static void spu_hw_restart_dma(struct spu_context *ctx)
+{
+       struct spu_priv2 __iomem *priv2 = ctx->spu->priv2;
+
+       if (!test_bit(SPU_CONTEXT_SWITCH_PENDING, &ctx->spu->flags))
+               out_be64(&priv2->mfc_control_RW, MFC_CNTL_RESTART_DMA_COMMAND);
+}
+
 struct spu_context_ops spu_hw_ops = {
        .mbox_read = spu_hw_mbox_read,
        .mbox_stat_read = spu_hw_mbox_stat_read,
        .mbox_stat_poll = spu_hw_mbox_stat_poll,
        .ibox_read = spu_hw_ibox_read,
        .wbox_write = spu_hw_wbox_write,
-       .signal1_read = spu_hw_signal1_read,
        .signal1_write = spu_hw_signal1_write,
-       .signal2_read = spu_hw_signal2_read,
        .signal2_write = spu_hw_signal2_write,
        .signal1_type_set = spu_hw_signal1_type_set,
        .signal1_type_get = spu_hw_signal1_type_get,
@@ -303,10 +319,13 @@ struct spu_context_ops spu_hw_ops = {
        .npc_write = spu_hw_npc_write,
        .status_read = spu_hw_status_read,
        .get_ls = spu_hw_get_ls,
+       .runcntl_read = spu_hw_runcntl_read,
        .runcntl_write = spu_hw_runcntl_write,
-       .runcntl_stop = spu_hw_runcntl_stop,
+       .master_start = spu_hw_master_start,
+       .master_stop = spu_hw_master_stop,
        .set_mfc_query = spu_hw_set_mfc_query,
        .read_mfc_tagstatus = spu_hw_read_mfc_tagstatus,
        .get_mfc_free_elements = spu_hw_get_mfc_free_elements,
        .send_mfc_command = spu_hw_send_mfc_command,
+       .restart_dma = spu_hw_restart_dma,
 };