ACPI: delete un-reliable concept of cooling mode
[linux-drm-fsl-dcu.git] / arch / mips / pci / ops-gt64111.c
index c1807934768d499d9f27a27aa27b551316720cca..ecd3991bd0e41cd4ec6d41d14cef1bf424a761a5 100644 (file)
@@ -15,7 +15,7 @@
 #include <asm/io.h>
 #include <asm/gt64120.h>
 
-#include <asm/cobalt/cobalt.h>
+#include <asm/mach-cobalt/cobalt.h>
 
 /*
  * Device 31 on the GT64111 is used to generate PCI special
@@ -38,18 +38,18 @@ static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn,
        switch (size) {
        case 4:
                PCI_CFG_SET(devfn, where);
-               *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS);
+               *val = GT_READ(GT_PCI0_CFGDATA_OFS);
                return PCIBIOS_SUCCESSFUL;
 
        case 2:
                PCI_CFG_SET(devfn, (where & ~0x3));
-               *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS)
+               *val = GT_READ(GT_PCI0_CFGDATA_OFS)
                    >> ((where & 3) * 8);
                return PCIBIOS_SUCCESSFUL;
 
        case 1:
                PCI_CFG_SET(devfn, (where & ~0x3));
-               *val = GALILEO_INL(GT_PCI0_CFGDATA_OFS)
+               *val = GT_READ(GT_PCI0_CFGDATA_OFS)
                    >> ((where & 3) * 8);
                return PCIBIOS_SUCCESSFUL;
        }
@@ -68,25 +68,25 @@ static int gt64111_pci_write_config(struct pci_bus *bus, unsigned int devfn,
        switch (size) {
        case 4:
                PCI_CFG_SET(devfn, where);
-               GALILEO_OUTL(val, GT_PCI0_CFGDATA_OFS);
+               GT_WRITE(GT_PCI0_CFGDATA_OFS, val);
 
                return PCIBIOS_SUCCESSFUL;
 
        case 2:
                PCI_CFG_SET(devfn, (where & ~0x3));
-               tmp = GALILEO_INL(GT_PCI0_CFGDATA_OFS);
+               tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
                tmp &= ~(0xffff << ((where & 0x3) * 8));
                tmp |= (val << ((where & 0x3) * 8));
-               GALILEO_OUTL(tmp, GT_PCI0_CFGDATA_OFS);
+               GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
 
                return PCIBIOS_SUCCESSFUL;
 
        case 1:
                PCI_CFG_SET(devfn, (where & ~0x3));
-               tmp = GALILEO_INL(GT_PCI0_CFGDATA_OFS);
+               tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
                tmp &= ~(0xff << ((where & 0x3) * 8));
                tmp |= (val << ((where & 0x3) * 8));
-               GALILEO_OUTL(tmp, GT_PCI0_CFGDATA_OFS);
+               GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
 
                return PCIBIOS_SUCCESSFUL;
        }