#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
-#include <asm/ptrace.h>
#include <asm/hardirq.h>
#include <asm/irq.h>
#include <asm/div64.h>
}
}
-static void mips_timer_dispatch (struct pt_regs *regs)
+static void mips_timer_dispatch(void)
{
- do_IRQ (mips_cpu_timer_irq, regs);
+ do_IRQ(mips_cpu_timer_irq);
}
/*
* Redeclare until I get around mopping the timer code insanity on MIPS.
*/
-extern int null_perf_irq(struct pt_regs *regs);
+extern int null_perf_irq(void);
-extern int (*perf_irq)(struct pt_regs *regs);
+extern int (*perf_irq)(void);
-irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+irqreturn_t mips_timer_interrupt(int irq, void *dev_id)
{
int cpu = smp_processor_id();
* perf counter overflow, or both.
*/
if (read_c0_cause() & (1 << 26))
- perf_irq(regs);
+ perf_irq();
if (read_c0_cause() & (1 << 30)) {
/* If timer interrupt, make it de-assert */
* the tick on VPE 0 to run the full timer_interrupt().
*/
if (cpu_data[cpu].vpe_id == 0) {
- timer_interrupt(irq, NULL, regs);
+ timer_interrupt(irq, NULL);
smtc_timer_broadcast(cpu_data[cpu].vpe_id);
scroll_display_message();
} else {
write_c0_compare(read_c0_count() +
(mips_hpt_frequency/HZ));
- local_timer_interrupt(irq, dev_id, regs);
+ local_timer_interrupt(irq, dev_id);
smtc_timer_broadcast(cpu_data[cpu].vpe_id);
}
}
* timer int.
*/
if (!r2 || (read_c0_cause() & (1 << 26)))
- if (perf_irq(regs))
+ if (perf_irq())
goto out;
/* we keep interrupt disabled all the time */
if (!r2 || (read_c0_cause() & (1 << 30)))
- timer_interrupt(irq, NULL, regs);
+ timer_interrupt(irq, NULL);
scroll_display_message();
} else {
/*
* Other CPUs should do profiling and process accounting
*/
- local_timer_interrupt(irq, dev_id, regs);
+ local_timer_interrupt(irq, dev_id);
}
out:
#endif /* CONFIG_MIPS_MT_SMTC */
}
/*
- * Estimate CPU frequency. Sets mips_counter_frequency as a side-effect
+ * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
*/
static unsigned int __init estimate_cpu_frequency(void)
{
count = 6000000;
#endif
#if defined(CONFIG_MIPS_ATLAS) || defined(CONFIG_MIPS_MALTA)
- unsigned int flags;
+ unsigned long flags;
+ unsigned int start;
local_irq_save(flags);
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
/* Start r4k counter. */
- write_c0_count(0);
+ start = read_c0_count();
/* Read counter exactly on falling edge of update flag */
while (CMOS_READ(RTC_REG_A) & RTC_UIP);
while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
- count = read_c0_count();
+ count = read_c0_count() - start;
/* restore interrupts */
local_irq_restore(flags);