MIPS: math-emu: Add support for the MIPS R6 MSUBF FPU instruction

[linux-drm-fsl-dcu.git] / arch / mips / math-emu / cp1emu.c

diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 67390ec2c2f8ec70723314bf78575e96f4742105..54964b372992f5f41184eed16f7384962e4d8f19 100644 (file)
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -1778,6 +1778,19 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
                        break;
                }
 
+               case fmsubf_op: {
+                       union ieee754sp ft, fs, fd;
+
+                       if (!cpu_has_mips_r6)
+                               return SIGILL;
+
+                       SPFROMREG(ft, MIPSInst_FT(ir));
+                       SPFROMREG(fs, MIPSInst_FS(ir));
+                       SPFROMREG(fd, MIPSInst_FD(ir));
+                       rv.s = ieee754sp_msubf(fd, fs, ft);
+                       break;
+               }
+
                case fabs_op:
                        handler.u = ieee754sp_abs;
                        goto scopuop;
@@ -2011,6 +2024,19 @@ copcsr:
                        break;
                }
 
+               case fmsubf_op: {
+                       union ieee754dp ft, fs, fd;
+
+                       if (!cpu_has_mips_r6)
+                               return SIGILL;
+
+                       DPFROMREG(ft, MIPSInst_FT(ir));
+                       DPFROMREG(fs, MIPSInst_FS(ir));
+                       DPFROMREG(fd, MIPSInst_FD(ir));
+                       rv.d = ieee754dp_msubf(fd, fs, ft);
+                       break;
+               }
+
                case fabs_op:
                        handler.u = ieee754dp_abs;
                        goto dcopuop;