Merge master.kernel.org:/pub/scm/linux/kernel/git/davej/agpgart

[linux-drm-fsl-dcu.git] / arch / mips / kernel / irq_cpu.c

diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 0e455a8ad860d612fa282a775d962275cc5f589e..7b66e03b58994e1e7f3daf6f88ead0628a1a4e12 100644 (file)
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -25,7 +25,7 @@
  * Don't even think about using this on SMP.  You have been warned.
  *
  * This file exports one global function:
- *     void mips_cpu_irq_init(int irq_base);
+ *     void mips_cpu_irq_init(void);
  */
 #include <linux/init.h>
 #include <linux/interrupt.h>
@@ -36,72 +36,25 @@
 #include <asm/mipsmtregs.h>
 #include <asm/system.h>
 
-static int mips_cpu_irq_base;
-
 static inline void unmask_mips_irq(unsigned int irq)
 {
-       set_c0_status(0x100 << (irq - mips_cpu_irq_base));
+       set_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
        irq_enable_hazard();
 }
 
 static inline void mask_mips_irq(unsigned int irq)
 {
-       clear_c0_status(0x100 << (irq - mips_cpu_irq_base));
+       clear_c0_status(0x100 << (irq - MIPS_CPU_IRQ_BASE));
        irq_disable_hazard();
 }
 
-static inline void mips_cpu_irq_enable(unsigned int irq)
-{
-       unsigned long flags;
-
-       local_irq_save(flags);
-       unmask_mips_irq(irq);
-       back_to_back_c0_hazard();
-       local_irq_restore(flags);
-}
-
-static void mips_cpu_irq_disable(unsigned int irq)
-{
-       unsigned long flags;
-
-       local_irq_save(flags);
-       mask_mips_irq(irq);
-       back_to_back_c0_hazard();
-       local_irq_restore(flags);
-}
-
-static unsigned int mips_cpu_irq_startup(unsigned int irq)
-{
-       mips_cpu_irq_enable(irq);
-
-       return 0;
-}
-
-#define        mips_cpu_irq_shutdown           mips_cpu_irq_disable
-
-/*
- * While we ack the interrupt interrupts are disabled and thus we don't need
- * to deal with concurrency issues.  Same for mips_cpu_irq_end.
- */
-static void mips_cpu_irq_ack(unsigned int irq)
-{
-       mask_mips_irq(irq);
-}
-
-static void mips_cpu_irq_end(unsigned int irq)
-{
-       if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-               unmask_mips_irq(irq);
-}
-
-static hw_irq_controller mips_cpu_irq_controller = {
-       .typename       = "MIPS",
-       .startup        = mips_cpu_irq_startup,
-       .shutdown       = mips_cpu_irq_shutdown,
-       .enable         = mips_cpu_irq_enable,
-       .disable        = mips_cpu_irq_disable,
-       .ack            = mips_cpu_irq_ack,
-       .end            = mips_cpu_irq_end,
+static struct irq_chip mips_cpu_irq_controller = {
+       .name           = "MIPS",
+       .ack            = mask_mips_irq,
+       .mask           = mask_mips_irq,
+       .mask_ack       = mask_mips_irq,
+       .unmask         = unmask_mips_irq,
+       .eoi            = unmask_mips_irq,
 };
 
 /*
@@ -110,22 +63,18 @@ static hw_irq_controller mips_cpu_irq_controller = {
 
 #define unmask_mips_mt_irq     unmask_mips_irq
 #define mask_mips_mt_irq       mask_mips_irq
-#define mips_mt_cpu_irq_enable mips_cpu_irq_enable
-#define mips_mt_cpu_irq_disable        mips_cpu_irq_disable
 
 static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
 {
        unsigned int vpflags = dvpe();
 
-       clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
+       clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
        evpe(vpflags);
-       mips_mt_cpu_irq_enable(irq);
+       unmask_mips_mt_irq(irq);
 
        return 0;
 }
 
-#define        mips_mt_cpu_irq_shutdown        mips_mt_cpu_irq_disable
-
 /*
  * While we ack the interrupt interrupts are disabled and thus we don't need
  * to deal with concurrency issues.  Same for mips_cpu_irq_end.
@@ -133,25 +82,24 @@ static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
 static void mips_mt_cpu_irq_ack(unsigned int irq)
 {
        unsigned int vpflags = dvpe();
-       clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
+       clear_c0_cause(0x100 << (irq - MIPS_CPU_IRQ_BASE));
        evpe(vpflags);
        mask_mips_mt_irq(irq);
 }
 
-#define mips_mt_cpu_irq_end mips_cpu_irq_end
-
-static hw_irq_controller mips_mt_cpu_irq_controller = {
-       .typename       = "MIPS",
+static struct irq_chip mips_mt_cpu_irq_controller = {
+       .name           = "MIPS",
        .startup        = mips_mt_cpu_irq_startup,
-       .shutdown       = mips_mt_cpu_irq_shutdown,
-       .enable         = mips_mt_cpu_irq_enable,
-       .disable        = mips_mt_cpu_irq_disable,
        .ack            = mips_mt_cpu_irq_ack,
-       .end            = mips_mt_cpu_irq_end,
+       .mask           = mask_mips_mt_irq,
+       .mask_ack       = mips_mt_cpu_irq_ack,
+       .unmask         = unmask_mips_mt_irq,
+       .eoi            = unmask_mips_mt_irq,
 };
 
-void __init mips_cpu_irq_init(int irq_base)
+void __init mips_cpu_irq_init(void)
 {
+       int irq_base = MIPS_CPU_IRQ_BASE;
        int i;
 
        /* Mask interrupts. */
@@ -163,19 +111,10 @@ void __init mips_cpu_irq_init(int irq_base)
         * leave them uninitialized for other processors.
         */
        if (cpu_has_mipsmt)
-               for (i = irq_base; i < irq_base + 2; i++) {
-                       irq_desc[i].status = IRQ_DISABLED;
-                       irq_desc[i].action = NULL;
-                       irq_desc[i].depth = 1;
-                       irq_desc[i].chip = &mips_mt_cpu_irq_controller;
-               }
-
-       for (i = irq_base + 2; i < irq_base + 8; i++) {
-               irq_desc[i].status = IRQ_DISABLED;
-               irq_desc[i].action = NULL;
-               irq_desc[i].depth = 1;
-               irq_desc[i].chip = &mips_cpu_irq_controller;
-       }
-
-       mips_cpu_irq_base = irq_base;
+               for (i = irq_base; i < irq_base + 2; i++)
+                       set_irq_chip(i, &mips_mt_cpu_irq_controller);
+
+       for (i = irq_base + 2; i < irq_base + 8; i++)
+               set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
+                                        handle_level_irq);
 }