MIPS: MT: Remove SMTC support

[linux-drm-fsl-dcu.git] / arch / mips / kernel / cpu-probe.c

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 6e8fb85ce7c3b076fd6bec6b2b770ed3b425c597..e8638c5b7d11709dc8a1f87593dd69c51334b895 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -62,7 +62,7 @@ static inline void check_errata(void)
        case CPU_34K:
                /*
                 * Erratum "RPS May Cause Incorrect Instruction Execution"
-                * This code only handles VPE0, any SMP/SMTC/RTOS code
+                * This code only handles VPE0, any SMP/RTOS code
                 * making use of VPE1 will be responsable for that VPE.
                 */
                if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
@@ -684,21 +684,6 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
                 */
                c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
                break;
-       case PRID_IMP_RM9000:
-               c->cputype = CPU_RM9000;
-               __cpu_name[cpu] = "RM9000";
-               set_isa(c, MIPS_CPU_ISA_IV);
-               c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
-                            MIPS_CPU_LLSC;
-               /*
-                * Bit 29 in the info register of the RM9000
-                * indicates if the TLB has 48 or 64 entries.
-                *
-                * 29      1 =>    64 entry JTLB
-                *         0 =>    48 entry JTLB
-                */
-               c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
-               break;
        case PRID_IMP_R8000:
                c->cputype = CPU_R8000;
                __cpu_name[cpu] = "RM8000";