[MIPS] define Hit_Invalidate_I to Index_Invalidate_I for loongson2

[linux-drm-fsl-dcu.git] / arch / mips / kernel / cpu-probe.c

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index f59ef271d2472d97bc65e3a76ad74fc3088ee363..23d8a3b7dd7556d60612efd83f781811a877bee7 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -16,6 +16,7 @@
 #include <linux/ptrace.h>
 #include <linux/stddef.h>
 
+#include <asm/bugs.h>
 #include <asm/cpu.h>
 #include <asm/fpu.h>
 #include <asm/mipsregs.h>
@@ -97,7 +98,7 @@ static void au1k_wait(void)
 
 static int __initdata nowait = 0;
 
-int __init wait_disable(char *s)
+static int __init wait_disable(char *s)
 {
        nowait = 1;
 
@@ -136,14 +137,24 @@ static inline void check_wait(void)
        case CPU_4KEC:
        case CPU_4KSC:
        case CPU_5KC:
-/*     case CPU_20KC:*/
-       case CPU_24K:
        case CPU_25KF:
+       case CPU_PR4450:
+               cpu_wait = r4k_wait;
+               break;
+
+       case CPU_24K:
        case CPU_34K:
+               cpu_wait = r4k_wait;
+               if (read_c0_config7() & MIPS_CONF7_WII)
+                       cpu_wait = r4k_wait_irqoff;
+               break;
+
        case CPU_74K:
-       case CPU_PR4450:
                cpu_wait = r4k_wait;
+               if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
+                       cpu_wait = r4k_wait_irqoff;
                break;
+
        case CPU_TX49XX:
                cpu_wait = r4k_wait_irqoff;
                break;
@@ -155,6 +166,17 @@ static inline void check_wait(void)
                if (allow_au1k_wait)
                        cpu_wait = au1k_wait;
                break;
+       case CPU_20KC:
+               /*
+                * WAIT on Rev1.0 has E1, E2, E3 and E16.
+                * WAIT on Rev2.0 and Rev3.0 has E16.
+                * Rev3.1 WAIT is nop, why bother
+                */
+               if ((c->processor_id & 0xff) <= 0x64)
+                       break;
+
+               cpu_wait = r4k_wait;
+               break;
        case CPU_RM9000:
                if ((c->processor_id & 0x00ff) >= 0x40)
                        cpu_wait = r4k_wait;
@@ -463,6 +485,14 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                             MIPS_CPU_LLSC;
                c->tlbsize = 64;
                break;
+       case PRID_IMP_LOONGSON2:
+               c->cputype = CPU_LOONGSON2;
+               c->isa_level = MIPS_CPU_ISA_III;
+               c->options = R4K_OPTS |
+                            MIPS_CPU_FPU | MIPS_CPU_LLSC |
+                            MIPS_CPU_32FPR;
+               c->tlbsize = 64;
+               break;
        }
 }
 
@@ -566,6 +596,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
                c->options |= MIPS_CPU_VEIC;
        if (config3 & MIPS_CONF3_MT)
                c->ases |= MIPS_ASE_MIPSMT;
+       if (config3 & MIPS_CONF3_ULRI)
+               c->options |= MIPS_CPU_ULRI;
 
        return config3 & MIPS_CONF_M;
 }