MIPS: Whitespace cleanup.

[linux-drm-fsl-dcu.git] / arch / mips / include / asm / pgtable-bits.h

diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index f6a0439a40858a5b29190825f0ddc820cc8755d7..32aea4852fb0796045efcbc9fbd6414b67a4fe77 100644 (file)
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -21,7 +21,7 @@
  * Similar to the Alpha port, we need to keep track of the ref
  * and mod bits in software.  We have a software "yeah you can read
  * from this page" bit, and a hardware one which actually lets the
- * process read from the page.  On the same token we have a software
+ * process read from the page. On the same token we have a software
  * writable bit and the real hardware one which actually lets the
  * process write to the page, this keeps a mod bit via the hardware
  * dirty bit.
@@ -41,9 +41,9 @@
 #define _PAGE_GLOBAL           (1 << 0)
 #define _PAGE_VALID_SHIFT      1
 #define _PAGE_VALID            (1 << _PAGE_VALID_SHIFT)
-#define _PAGE_SILENT_READ      (1 << 1)  /* synonym                 */
+#define _PAGE_SILENT_READ      (1 << 1)  /* synonym                 */
 #define _PAGE_DIRTY_SHIFT      2
-#define _PAGE_DIRTY            (1 << _PAGE_DIRTY_SHIFT)  /* The MIPS dirty bit      */
+#define _PAGE_DIRTY            (1 << _PAGE_DIRTY_SHIFT)  /* The MIPS dirty bit      */
 #define _PAGE_SILENT_WRITE     (1 << 2)
 #define _CACHE_SHIFT           3
 #define _CACHE_MASK            (7 << 3)
@@ -52,7 +52,7 @@
  * The following bits are implemented in software
  *
  * _PAGE_FILE semantics: set:pagecache unset:swap
- */ 
+ */
 #define _PAGE_PRESENT_SHIFT    6
 #define _PAGE_PRESENT          (1 << _PAGE_PRESENT_SHIFT)
 #define _PAGE_READ_SHIFT       7
@@ -134,7 +134,7 @@
 #define _PAGE_HUGE             (1 << _PAGE_HUGE_SHIFT)
 #else
 #define _PAGE_HUGE_SHIFT       (_PAGE_MODIFIED_SHIFT)
-#define _PAGE_HUGE             ({BUG(); 1; })  /* Dummy value */
+#define _PAGE_HUGE             ({BUG(); 1; })  /* Dummy value */
 #endif
 
 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
@@ -143,7 +143,7 @@
 #define _PAGE_SPLITTING                (1 << _PAGE_SPLITTING_SHIFT)
 #else
 #define _PAGE_SPLITTING_SHIFT  (_PAGE_HUGE_SHIFT)
-#define _PAGE_SPLITTING                ({BUG(); 1; })  /* Dummy value */
+#define _PAGE_SPLITTING                ({BUG(); 1; })  /* Dummy value */
 #endif
 
 /* Page cannot be executed */
@@ -159,10 +159,10 @@
 
 #define _PAGE_VALID_SHIFT      (_PAGE_GLOBAL_SHIFT + 1)
 #define _PAGE_VALID            (1 << _PAGE_VALID_SHIFT)
-/* synonym                 */
+/* synonym                */
 #define _PAGE_SILENT_READ      (_PAGE_VALID)
 
-/* The MIPS dirty bit      */
+/* The MIPS dirty bit     */
 #define _PAGE_DIRTY_SHIFT      (_PAGE_VALID_SHIFT + 1)
 #define _PAGE_DIRTY            (1 << _PAGE_DIRTY_SHIFT)
 #define _PAGE_SILENT_WRITE     (_PAGE_DIRTY)
@@ -175,7 +175,7 @@
 #endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */
 
 #ifndef _PFN_SHIFT
-#define _PFN_SHIFT                  PAGE_SHIFT
+#define _PFN_SHIFT                 PAGE_SHIFT
 #endif
 #define _PFN_MASK              (~((1 << (_PFN_SHIFT)) - 1))
 
@@ -230,28 +230,28 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
 /* No penalty for being coherent on the SB1, so just
    use it for "noncoherent" spaces, too.  Shouldn't hurt. */
 
-#define _CACHE_UNCACHED             (2<<_CACHE_SHIFT)
-#define _CACHE_CACHABLE_COW         (5<<_CACHE_SHIFT)
+#define _CACHE_UNCACHED                    (2<<_CACHE_SHIFT)
+#define _CACHE_CACHABLE_COW        (5<<_CACHE_SHIFT)
 #define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
 
 #else
 
-#define _CACHE_CACHABLE_NO_WA      (0<<_CACHE_SHIFT)  /* R4600 only      */
-#define _CACHE_CACHABLE_WA         (1<<_CACHE_SHIFT)  /* R4600 only      */
-#define _CACHE_UNCACHED             (2<<_CACHE_SHIFT)  /* R4[0246]00      */
-#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* R4[0246]00      */
-#define _CACHE_CACHABLE_CE          (4<<_CACHE_SHIFT)  /* R4[04]00MC only */
-#define _CACHE_CACHABLE_COW         (5<<_CACHE_SHIFT)  /* R4[04]00MC only */
-#define _CACHE_CACHABLE_COHERENT    (5<<_CACHE_SHIFT)  /* MIPS32R2 CMP    */
-#define _CACHE_CACHABLE_CUW         (6<<_CACHE_SHIFT)  /* R4[04]00MC only */
-#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)  /* R10000 only     */
+#define _CACHE_CACHABLE_NO_WA      (0<<_CACHE_SHIFT)  /* R4600 only      */
+#define _CACHE_CACHABLE_WA         (1<<_CACHE_SHIFT)  /* R4600 only      */
+#define _CACHE_UNCACHED                    (2<<_CACHE_SHIFT)  /* R4[0246]00      */
+#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* R4[0246]00     */
+#define _CACHE_CACHABLE_CE         (4<<_CACHE_SHIFT)  /* R4[04]00MC only */
+#define _CACHE_CACHABLE_COW        (5<<_CACHE_SHIFT)  /* R4[04]00MC only */
+#define _CACHE_CACHABLE_COHERENT    (5<<_CACHE_SHIFT)  /* MIPS32R2 CMP   */
+#define _CACHE_CACHABLE_CUW        (6<<_CACHE_SHIFT)  /* R4[04]00MC only */
+#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)  /* R10000 only    */
 
 #endif
 
 #define __READABLE     (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ))
 #define __WRITEABLE    (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
 
-#define _PAGE_CHG_MASK  (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
+#define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
 
 #endif /* _ASM_PGTABLE_BITS_H */