MIPS: Whitespace cleanup.

[linux-drm-fsl-dcu.git] / arch / mips / include / asm / mach-au1x00 / au1xxx_ide.h

diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
index e306384b1414f2cd35301e81f9705e3d052d0f6c..bb91b8923a49e22bb0683e3b0ee60ec4cefdcf15 100644 (file)
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_ide.h
@@ -1,5 +1,5 @@
 /*
- * include/asm-mips/mach-au1x00/au1xxx_ide.h  version 01.30.00   Aug. 02 2005
+ * include/asm-mips/mach-au1x00/au1xxx_ide.h  version 01.30.00  Aug. 02 2005
  *
  * BRIEF MODULE DESCRIPTION
  * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
@@ -27,14 +27,14 @@
  * 675 Mass Ave, Cambridge, MA 02139, USA.
  *
  * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
- *       Interface and Linux Device Driver" Application Note.
+ *      Interface and Linux Device Driver" Application Note.
  */
 
 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
 #define DMA_WAIT_TIMEOUT       100
-#define NUM_DESCRIPTORS        PRD_ENTRIES
+#define NUM_DESCRIPTORS                PRD_ENTRIES
 #else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
-#define NUM_DESCRIPTORS        2
+#define NUM_DESCRIPTORS                2
 #endif
 
 #ifndef AU1XXX_ATA_RQSIZE
@@ -84,8 +84,8 @@ typedef struct {
 #define TWP_MASK               (0x3F << 14)
 #define TCSW_MASK              (0x0F << 10)
 #define TPM_MASK               (0x0F << 6)
-#define TA_MASK                (0x3F << 0)
-#define TS_MASK                (1 << 8)
+#define TA_MASK                        (0x3F << 0)
+#define TS_MASK                        (1 << 8)
 
 /* Timing parameters PIO mode 0 */
 #define SBC_IDE_PIO0_TCSOE     (0x04 << 29)
@@ -96,7 +96,7 @@ typedef struct {
 #define SBC_IDE_PIO0_TWP       (0x10 << 14)
 #define SBC_IDE_PIO0_TCSW      (0x04 << 10)
 #define SBC_IDE_PIO0_TPM       (0x00 << 6)
-#define SBC_IDE_PIO0_TA        (0x15 << 0)
+#define SBC_IDE_PIO0_TA                (0x15 << 0)
 /* Timing parameters PIO mode 1 */
 #define SBC_IDE_PIO1_TCSOE     (0x03 << 29)
 #define SBC_IDE_PIO1_TOECS     (0x01 << 26)
@@ -106,7 +106,7 @@ typedef struct {
 #define SBC_IDE_PIO1_TWP       (0x08 << 14)
 #define SBC_IDE_PIO1_TCSW      (0x03 << 10)
 #define SBC_IDE_PIO1_TPM       (0x00 << 6)
-#define SBC_IDE_PIO1_TA        (0x0B << 0)
+#define SBC_IDE_PIO1_TA                (0x0B << 0)
 /* Timing parameters PIO mode 2 */
 #define SBC_IDE_PIO2_TCSOE     (0x05 << 29)
 #define SBC_IDE_PIO2_TOECS     (0x01 << 26)
@@ -116,7 +116,7 @@ typedef struct {
 #define SBC_IDE_PIO2_TWP       (0x1F << 14)
 #define SBC_IDE_PIO2_TCSW      (0x05 << 10)
 #define SBC_IDE_PIO2_TPM       (0x00 << 6)
-#define SBC_IDE_PIO2_TA        (0x22 << 0)
+#define SBC_IDE_PIO2_TA                (0x22 << 0)
 /* Timing parameters PIO mode 3 */
 #define SBC_IDE_PIO3_TCSOE     (0x05 << 29)
 #define SBC_IDE_PIO3_TOECS     (0x01 << 26)
@@ -126,7 +126,7 @@ typedef struct {
 #define SBC_IDE_PIO3_TWP       (0x15 << 14)
 #define SBC_IDE_PIO3_TCSW      (0x05 << 10)
 #define SBC_IDE_PIO3_TPM       (0x00 << 6)
-#define SBC_IDE_PIO3_TA        (0x1A << 0)
+#define SBC_IDE_PIO3_TA                (0x1A << 0)
 /* Timing parameters PIO mode 4 */
 #define SBC_IDE_PIO4_TCSOE     (0x04 << 29)
 #define SBC_IDE_PIO4_TOECS     (0x01 << 26)
@@ -136,7 +136,7 @@ typedef struct {
 #define SBC_IDE_PIO4_TWP       (0x0D << 14)
 #define SBC_IDE_PIO4_TCSW      (0x03 << 10)
 #define SBC_IDE_PIO4_TPM       (0x00 << 6)
-#define SBC_IDE_PIO4_TA        (0x12 << 0)
+#define SBC_IDE_PIO4_TA                (0x12 << 0)
 /* Timing parameters MDMA mode 0 */
 #define SBC_IDE_MDMA0_TCSOE    (0x03 << 29)
 #define SBC_IDE_MDMA0_TOECS    (0x01 << 26)