MIPS: Respect the ISA level in FCSR handling

[linux-drm-fsl-dcu.git] / arch / mips / include / asm / fpu.h

diff --git a/arch/mips/include/asm/fpu.h b/arch/mips/include/asm/fpu.h
index dd083e999b08a14ffdbef46d5f5f4a0731e9f18e..83d50d563a0f5d5c556ac78cd16352af25958684 100644 (file)
--- a/arch/mips/include/asm/fpu.h
+++ b/arch/mips/include/asm/fpu.h
@@ -30,7 +30,7 @@
 struct sigcontext;
 struct sigcontext32;
 
-extern void _init_fpu(void);
+extern void _init_fpu(unsigned int);
 extern void _save_fp(struct task_struct *);
 extern void _restore_fp(struct task_struct *);
 
@@ -182,6 +182,7 @@ static inline void lose_fpu(int save)
 
 static inline int init_fpu(void)
 {
+       unsigned int fcr31 = current->thread.fpu.fcr31;
        int ret = 0;
 
        if (cpu_has_fpu) {
@@ -192,7 +193,7 @@ static inline int init_fpu(void)
                        return ret;
 
                if (!cpu_has_fre) {
-                       _init_fpu();
+                       _init_fpu(fcr31);
 
                        return 0;
                }
@@ -206,7 +207,7 @@ static inline int init_fpu(void)
                config5 = clear_c0_config5(MIPS_CONF5_FRE);
                enable_fpu_hazard();
 
-               _init_fpu();
+               _init_fpu(fcr31);
 
                /* Restore FRE */
                write_c0_config5(config5);