MIPS: Whitespace cleanup.

[linux-drm-fsl-dcu.git] / arch / mips / include / asm / cacheops.h

diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 8f99c11ab6657d8f8ab68a61155f01b1ff20bfdb..68f37e3eccc7f5032e98a7aa854eeceeb1783ace 100644 (file)
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -8,20 +8,20 @@
  * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
  * (C) Copyright 1999 Silicon Graphics, Inc.
  */
-#ifndef        __ASM_CACHEOPS_H
-#define        __ASM_CACHEOPS_H
+#ifndef __ASM_CACHEOPS_H
+#define __ASM_CACHEOPS_H
 
 /*
  * Cache Operations available on all MIPS processors with R4000-style caches
  */
-#define Index_Invalidate_I      0x00
-#define Index_Writeback_Inv_D   0x01
+#define Index_Invalidate_I     0x00
+#define Index_Writeback_Inv_D  0x01
 #define Index_Load_Tag_I       0x04
 #define Index_Load_Tag_D       0x05
 #define Index_Store_Tag_I      0x08
 #define Index_Store_Tag_D      0x09
 #if defined(CONFIG_CPU_LOONGSON2)
-#define Hit_Invalidate_I       0x00
+#define Hit_Invalidate_I       0x00
 #else
 #define Hit_Invalidate_I       0x10
 #endif
@@ -39,8 +39,8 @@
 /*
  * R4000SC and R4400SC-specific cacheops
  */
-#define Index_Invalidate_SI     0x02
-#define Index_Writeback_Inv_SD  0x03
+#define Index_Invalidate_SI    0x02
+#define Index_Writeback_Inv_SD 0x03
 #define Index_Load_Tag_SI      0x06
 #define Index_Load_Tag_SD      0x07
 #define Index_Store_Tag_SI     0x0A