Pull video into test branch

[linux-drm-fsl-dcu.git] / arch / ia64 / pci / pci.c

diff --git a/arch/ia64/pci/pci.c b/arch/ia64/pci/pci.c
index b30be7c48ba8d9e79c8476181d47d15da1776fe8..474d179966dc02e221ee81d8083ae566e255e804 100644 (file)
--- a/arch/ia64/pci/pci.c
+++ b/arch/ia64/pci/pci.c
@@ -125,11 +125,10 @@ alloc_pci_controller (int seg)
 {
        struct pci_controller *controller;
 
-       controller = kmalloc(sizeof(*controller), GFP_KERNEL);
+       controller = kzalloc(sizeof(*controller), GFP_KERNEL);
        if (!controller)
                return NULL;
 
-       memset(controller, 0, sizeof(*controller));
        controller->segment = seg;
        controller->node = -1;
        return controller;
@@ -469,10 +468,11 @@ pcibios_fixup_resources(struct pci_dev *dev, int start, int limit)
        }
 }
 
-static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
+void __devinit pcibios_fixup_device_resources(struct pci_dev *dev)
 {
        pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES);
 }
+EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources);
 
 static void __devinit pcibios_fixup_bridge_resources(struct pci_dev *dev)
 {
@@ -493,6 +493,7 @@ pcibios_fixup_bus (struct pci_bus *b)
        }
        list_for_each_entry(dev, &b->devices, bus_list)
                pcibios_fixup_device_resources(dev);
+       platform_pci_fixup_bus(b);
 
        return;
 }
@@ -562,8 +563,8 @@ pcibios_enable_device (struct pci_dev *dev, int mask)
 void
 pcibios_disable_device (struct pci_dev *dev)
 {
-       if (dev->is_enabled)
-               acpi_pci_irq_disable(dev);
+       BUG_ON(atomic_read(&dev->enable_cnt));
+       acpi_pci_irq_disable(dev);
 }
 
 void
@@ -738,75 +739,44 @@ int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
        return ret;
 }
 
+/* It's defined in drivers/pci/pci.c */
+extern u8 pci_cache_line_size;
+
 /**
- * pci_cacheline_size - determine cacheline size for PCI devices
- * @dev: void
+ * set_pci_cacheline_size - determine cacheline size for PCI devices
  *
  * We want to use the line-size of the outer-most cache.  We assume
  * that this line-size is the same for all CPUs.
  *
  * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
- *
- * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
  */
-static unsigned long
-pci_cacheline_size (void)
+static void __init set_pci_cacheline_size(void)
 {
        u64 levels, unique_caches;
        s64 status;
        pal_cache_config_info_t cci;
-       static u8 cacheline_size;
-
-       if (cacheline_size)
-               return cacheline_size;
 
        status = ia64_pal_cache_summary(&levels, &unique_caches);
        if (status != 0) {
-               printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
-                      __FUNCTION__, status);
-               return SMP_CACHE_BYTES;
+               printk(KERN_ERR "%s: ia64_pal_cache_summary() failed "
+                       "(status=%ld)\n", __FUNCTION__, status);
+               return;
        }
 
-       status = ia64_pal_cache_config_info(levels - 1, /* cache_type (data_or_unified)= */ 2,
-                                           &cci);
+       status = ia64_pal_cache_config_info(levels - 1,
+                               /* cache_type (data_or_unified)= */ 2, &cci);
        if (status != 0) {
-               printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed (status=%ld)\n",
-                      __FUNCTION__, status);
-               return SMP_CACHE_BYTES;
+               printk(KERN_ERR "%s: ia64_pal_cache_config_info() failed "
+                       "(status=%ld)\n", __FUNCTION__, status);
+               return;
        }
-       cacheline_size = 1 << cci.pcci_line_size;
-       return cacheline_size;
+       pci_cache_line_size = (1 << cci.pcci_line_size) / 4;
 }
 
-/**
- * pcibios_prep_mwi - helper function for drivers/pci/pci.c:pci_set_mwi()
- * @dev: the PCI device for which MWI is enabled
- *
- * For ia64, we can get the cacheline sizes from PAL.
- *
- * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
- */
-int
-pcibios_prep_mwi (struct pci_dev *dev)
-{
-       unsigned long desired_linesize, current_linesize;
-       int rc = 0;
-       u8 pci_linesize;
-
-       desired_linesize = pci_cacheline_size();
-
-       pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &pci_linesize);
-       current_linesize = 4 * pci_linesize;
-       if (desired_linesize != current_linesize) {
-               printk(KERN_WARNING "PCI: slot %s has incorrect PCI cache line size of %lu bytes,",
-                      pci_name(dev), current_linesize);
-               if (current_linesize > desired_linesize) {
-                       printk(" expected %lu bytes instead\n", desired_linesize);
-                       rc = -EINVAL;
-               } else {
-                       printk(" correcting to %lu\n", desired_linesize);
-                       pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, desired_linesize / 4);
-               }
-       }
-       return rc;
+static int __init pcibios_init(void)
+{
+       set_pci_cacheline_size();
+       return 0;
 }
+
+subsys_initcall(pcibios_init);