Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

[linux-drm-fsl-dcu.git] / arch / arm64 / boot / dts / freescale / fsl-ls2080a.dtsi

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
index 925552e7b4f3eaf6ce23fc1e8dd2d77f50073121..2b23d03606839795c1cb3687e28fc117ffeec83f 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
@@ -153,6 +153,18 @@
                };
        };
 
+       rstcr: syscon@1e60000 {
+               compatible = "fsl,ls2080a-rstcr", "syscon";
+               reg = <0x0 0x1e60000 0x0 0x4>;
+       };
+
+       reboot {
+               compatible ="syscon-reboot";
+               regmap = <&rstcr>;
+               offset = <0x0>;
+               mask = <0x2>;
+       };
+
        timer {
                compatible = "arm,armv8-timer";
                interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
@@ -193,6 +205,62 @@
                        interrupts = <0 32 0x4>; /* Level high type */
                };
 
+               cluster1_core0_watchdog: wdt@c000000 {
+                       compatible = "arm,sp805-wdt", "arm,primecell";
+                       reg = <0x0 0xc000000 0x0 0x1000>;
+                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                       clock-names = "apb_pclk", "wdog_clk";
+               };
+
+               cluster1_core1_watchdog: wdt@c010000 {
+                       compatible = "arm,sp805-wdt", "arm,primecell";
+                       reg = <0x0 0xc010000 0x0 0x1000>;
+                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                       clock-names = "apb_pclk", "wdog_clk";
+               };
+
+               cluster2_core0_watchdog: wdt@c100000 {
+                       compatible = "arm,sp805-wdt", "arm,primecell";
+                       reg = <0x0 0xc100000 0x0 0x1000>;
+                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                       clock-names = "apb_pclk", "wdog_clk";
+               };
+
+               cluster2_core1_watchdog: wdt@c110000 {
+                       compatible = "arm,sp805-wdt", "arm,primecell";
+                       reg = <0x0 0xc110000 0x0 0x1000>;
+                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                       clock-names = "apb_pclk", "wdog_clk";
+               };
+
+               cluster3_core0_watchdog: wdt@c200000 {
+                       compatible = "arm,sp805-wdt", "arm,primecell";
+                       reg = <0x0 0xc200000 0x0 0x1000>;
+                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                       clock-names = "apb_pclk", "wdog_clk";
+               };
+
+               cluster3_core1_watchdog: wdt@c210000 {
+                       compatible = "arm,sp805-wdt", "arm,primecell";
+                       reg = <0x0 0xc210000 0x0 0x1000>;
+                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                       clock-names = "apb_pclk", "wdog_clk";
+               };
+
+               cluster4_core0_watchdog: wdt@c300000 {
+                       compatible = "arm,sp805-wdt", "arm,primecell";
+                       reg = <0x0 0xc300000 0x0 0x1000>;
+                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                       clock-names = "apb_pclk", "wdog_clk";
+               };
+
+               cluster4_core1_watchdog: wdt@c310000 {
+                       compatible = "arm,sp805-wdt", "arm,primecell";
+                       reg = <0x0 0xc310000 0x0 0x1000>;
+                       clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+                       clock-names = "apb_pclk", "wdog_clk";
+               };
+
                fsl_mc: fsl-mc@80c000000 {
                        compatible = "fsl,qoriq-mc";
                        reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */