Pull button into test branch

[linux-drm-fsl-dcu.git] / arch / arm / mm / proc-xscale.S

diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 3ca0c92e98a2ddba5a3b2f3d21a09cb775700abd..490e11b342319077e5c3be51c7e9a95562941991 100644 (file)
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -23,7 +23,7 @@
 #include <linux/linkage.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
-#include <asm/procinfo.h>
+#include <asm/elf.h>
 #include <asm/pgtable.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/page.h>
@@ -311,12 +311,6 @@ ENTRY(xscale_flush_kern_dcache_page)
  *     - end    - virtual end address
  */
 ENTRY(xscale_dma_inv_range)
-       mrc     p15, 0, r2, c0, c0, 0           @ read ID
-       eor     r2, r2, #0x69000000
-       eor     r2, r2, #0x00052000
-       bics    r2, r2, #1
-       beq     xscale_dma_flush_range
-
        tst     r0, #CACHELINESIZE - 1
        bic     r0, r0, #CACHELINESIZE - 1
        mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -375,6 +369,30 @@ ENTRY(xscale_cache_fns)
        .long   xscale_dma_clean_range
        .long   xscale_dma_flush_range
 
+/*
+ * On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't
+ * clear the dirty bits, which means that if we invalidate a dirty line,
+ * the dirty data can still be written back to external memory later on.
+ *
+ * The recommended workaround is to always do a clean D-cache line before
+ * doing an invalidate D-cache line, so on the affected processors,
+ * dma_inv_range() is implemented as dma_flush_range().
+ *
+ * See erratum #25 of "Intel 80200 Processor Specification Update",
+ * revision January 22, 2003, available at:
+ *     http://www.intel.com/design/iio/specupdt/273415.htm
+ */
+ENTRY(xscale_80200_A0_A1_cache_fns)
+       .long   xscale_flush_kern_cache_all
+       .long   xscale_flush_user_cache_all
+       .long   xscale_flush_user_cache_range
+       .long   xscale_coherent_kern_range
+       .long   xscale_coherent_user_range
+       .long   xscale_flush_kern_dcache_page
+       .long   xscale_dma_flush_range
+       .long   xscale_dma_clean_range
+       .long   xscale_dma_flush_range
+
 ENTRY(cpu_xscale_dcache_clean_area)
 1:     mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        add     r0, r0, #CACHELINESIZE
@@ -403,14 +421,14 @@ ENTRY(cpu_xscale_switch_mm)
        cpwait_ret lr, ip
 
 /*
- * cpu_xscale_set_pte(ptep, pte)
+ * cpu_xscale_set_pte_ext(ptep, pte, ext)
  *
  * Set a PTE and flush it out
  *
  * Errata 40: must set memory to write-through for user read-only pages.
  */
        .align  5
-ENTRY(cpu_xscale_set_pte)
+ENTRY(cpu_xscale_set_pte_ext)
        str     r1, [r0], #-2048                @ linux version
 
        bic     r2, r1, #0xff0
@@ -473,12 +491,7 @@ __xscale_setup:
        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I, D caches & BTB
        mcr     p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I, D TLBs
-#ifdef CONFIG_IWMMXT
-       mov     r0, #0                          @ initially disallow access to CP0/CP1
-#else
-       mov     r0, #1                          @ Allow access to CP0
-#endif
-       orr     r0, r0, #1 << 6                 @ cp6 for IOP3xx and Bulverde
+       mov     r0, #1 << 6                     @ cp6 for IOP3xx and Bulverde
        orr     r0, r0, #1 << 13                @ Its undefined whether this
        mcr     p15, 0, r0, c15, c1, 0          @ affects USR or SVC modes
 
@@ -516,7 +529,7 @@ ENTRY(xscale_processor_functions)
        .word   cpu_xscale_do_idle
        .word   cpu_xscale_dcache_clean_area
        .word   cpu_xscale_switch_mm
-       .word   cpu_xscale_set_pte
+       .word   cpu_xscale_set_pte_ext
        .size   xscale_processor_functions, . - xscale_processor_functions
 
        .section ".rodata"
@@ -531,6 +544,11 @@ cpu_elf_name:
        .asciz  "v5"
        .size   cpu_elf_name, . - cpu_elf_name
 
+       .type   cpu_80200_A0_A1_name, #object
+cpu_80200_A0_A1_name:
+       .asciz  "XScale-80200 A0/A1"
+       .size   cpu_80200_A0_A1_name, . - cpu_80200_A0_A1_name
+
        .type   cpu_80200_name, #object
 cpu_80200_name:
        .asciz  "XScale-80200"
@@ -595,6 +613,29 @@ cpu_pxa270_name:
 
        .section ".proc.info.init", #alloc, #execinstr
 
+       .type   __80200_A0_A1_proc_info,#object
+__80200_A0_A1_proc_info:
+       .long   0x69052000
+       .long   0xfffffffe
+       .long   PMD_TYPE_SECT | \
+               PMD_SECT_BUFFERABLE | \
+               PMD_SECT_CACHEABLE | \
+               PMD_SECT_AP_WRITE | \
+               PMD_SECT_AP_READ
+       .long   PMD_TYPE_SECT | \
+               PMD_SECT_AP_WRITE | \
+               PMD_SECT_AP_READ
+       b       __xscale_setup
+       .long   cpu_arch_name
+       .long   cpu_elf_name
+       .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+       .long   cpu_80200_name
+       .long   xscale_processor_functions
+       .long   v4wbi_tlb_fns
+       .long   xscale_mc_user_fns
+       .long   xscale_80200_A0_A1_cache_fns
+       .size   __80200_A0_A1_proc_info, . - __80200_A0_A1_proc_info
+
        .type   __80200_proc_info,#object
 __80200_proc_info:
        .long   0x69052000