Merge ../linus

[linux-drm-fsl-dcu.git] / arch / arm / mm / proc-arm1020.S

diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index efeebe77891fdc1ec24cc4dbf7aa75b51ee9146e..289b8e6f504dc656a75c8e1f2f2a3c82f631e626 100644 (file)
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -26,15 +26,16 @@
  *  CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
  */
 #include <linux/linkage.h>
-#include <linux/config.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/elf.h>
 #include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
-#include <asm/procinfo.h>
 #include <asm/ptrace.h>
 
+#include "proc-macros.S"
+
 /*
  * This is the maximum size of an area which will be invalidated
  * using the single invalidate entry instructions.  Anything larger
@@ -440,11 +441,12 @@ __arm1020_setup:
 #ifdef CONFIG_MMU
        mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
 #endif
+
+       adr     r5, arm1020_crval
+       ldmia   r5, {r5, r6}
        mrc     p15, 0, r0, c1, c0              @ get control register v4
-       ldr     r5, arm1020_cr1_clear
        bic     r0, r0, r5
-       ldr     r5, arm1020_cr1_set
-       orr     r0, r0, r5
+       orr     r0, r0, r6
 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
        orr     r0, r0, #0x4000                 @ .R.. .... .... ....
 #endif
@@ -456,12 +458,9 @@ __arm1020_setup:
         * .RVI ZFRS BLDP WCAM
         * .011 1001 ..11 0101
         */
-       .type   arm1020_cr1_clear, #object
-       .type   arm1020_cr1_set, #object
-arm1020_cr1_clear:
-       .word   0x593f
-arm1020_cr1_set:
-       .word   0x3935
+       .type   arm1020_crval, #object
+arm1020_crval:
+       crval   clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
 
        __INITDATA