ARM: v7 setup function should invalidate L1 cache

[linux-drm-fsl-dcu.git] / arch / arm / mach-zynq / headsmp.S

diff --git a/arch/arm/mach-zynq/headsmp.S b/arch/arm/mach-zynq/headsmp.S
index dd8c071941e7ff3b9f991989ede3acc5aaac856b..045c72720a4d5e1c69dd22efd3fdbfdcfe811184 100644 (file)
--- a/arch/arm/mach-zynq/headsmp.S
+++ b/arch/arm/mach-zynq/headsmp.S
@@ -22,8 +22,3 @@ zynq_secondary_trampoline_jump:
 .globl zynq_secondary_trampoline_end
 zynq_secondary_trampoline_end:
 ENDPROC(zynq_secondary_trampoline)
-
-ENTRY(zynq_secondary_startup)
-       bl      v7_invalidate_l1
-       b       secondary_startup
-ENDPROC(zynq_secondary_startup)