ARM: v7 setup function should invalidate L1 cache

[linux-drm-fsl-dcu.git] / arch / arm / mach-socfpga / core.h

diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index a0f3b1cd497cc70656637c6dd2215a07942c0b1e..767c09e954a0f905f5bb2e791273f1bcc96f370f 100644 (file)
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -31,7 +31,6 @@
 
 #define RSTMGR_MPUMODRST_CPU1          0x2     /* CPU1 Reset */
 
-extern void socfpga_secondary_startup(void);
 extern void __iomem *socfpga_scu_base_addr;
 
 extern void socfpga_init_clocks(void);