* Demux handler for GPIO>=2 edge detect interrupts
*/
-static void pxa_gpio_demux_handler(unsigned int irq, struct irqdesc *desc,
- struct pt_regs *regs)
+static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
{
unsigned int mask;
int loop;
mask >>= 2;
do {
if (mask & 1)
- desc_handle_irq(irq, desc, regs);
+ desc_handle_irq(irq, desc);
irq++;
desc++;
mask >>= 1;
desc = irq_desc + irq;
do {
if (mask & 1)
- desc_handle_irq(irq, desc, regs);
+ desc_handle_irq(irq, desc);
irq++;
desc++;
mask >>= 1;
desc = irq_desc + irq;
do {
if (mask & 1)
- desc_handle_irq(irq, desc, regs);
+ desc_handle_irq(irq, desc);
irq++;
desc++;
mask >>= 1;
desc = irq_desc + irq;
do {
if (mask & 1)
- desc_handle_irq(irq, desc, regs);
+ desc_handle_irq(irq, desc);
irq++;
desc++;
mask >>= 1;
for (irq = PXA_IRQ(PXA_IRQ_SKIP); irq <= PXA_IRQ(31); irq++) {
set_irq_chip(irq, &pxa_internal_chip_low);
- set_irq_handler(irq, do_level_IRQ);
+ set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
#if PXA_INTERNAL_IRQS > 32
for (irq = PXA_IRQ(32); irq < PXA_IRQ(PXA_INTERNAL_IRQS); irq++) {
set_irq_chip(irq, &pxa_internal_chip_high);
- set_irq_handler(irq, do_level_IRQ);
+ set_irq_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID);
}
#endif
for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
set_irq_chip(irq, &pxa_low_gpio_chip);
- set_irq_handler(irq, do_edge_IRQ);
+ set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
for (irq = IRQ_GPIO(2); irq <= IRQ_GPIO(PXA_LAST_GPIO); irq++) {
set_irq_chip(irq, &pxa_muxed_gpio_chip);
- set_irq_handler(irq, do_edge_IRQ);
+ set_irq_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}