Pull video into test branch

[linux-drm-fsl-dcu.git] / arch / arm / mach-pnx4008 / irq.c

diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
index 9b0a8e084e99f71cb23f19449ec0aef6817d5086..968d0b027597399fa88d3d627756dddb1abc7316 100644 (file)
--- a/arch/arm/mach-pnx4008/irq.c
+++ b/arch/arm/mach-pnx4008/irq.c
@@ -22,8 +22,8 @@
 #include <linux/init.h>
 #include <linux/ioport.h>
 #include <linux/device.h>
+#include <linux/irq.h>
 #include <asm/hardware.h>
-#include <asm/irq.h>
 #include <asm/io.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -59,22 +59,22 @@ static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
        case IRQT_RISING:
                __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq));        /*edge sensitive */
                __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq));        /*rising edge */
-               set_irq_handler(irq, do_edge_IRQ);
+               set_irq_handler(irq, handle_edge_irq);
                break;
        case IRQT_FALLING:
                __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq));        /*edge sensitive */
                __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq));       /*falling edge */
-               set_irq_handler(irq, do_edge_IRQ);
+               set_irq_handler(irq, handle_edge_irq);
                break;
        case IRQT_LOW:
                __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq));       /*level sensitive */
                __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq));       /*low level */
-               set_irq_handler(irq, do_level_IRQ);
+               set_irq_handler(irq, handle_level_irq);
                break;
        case IRQT_HIGH:
                __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq));       /*level sensitive */
                __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq));        /* high level */
-               set_irq_handler(irq, do_level_IRQ);
+               set_irq_handler(irq, handle_level_irq);
                break;
 
        /* IRQT_BOTHEDGE is not supported */
@@ -85,7 +85,7 @@ static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
        return 0;
 }
 
-static struct irqchip pnx4008_irq_chip = {
+static struct irq_chip pnx4008_irq_chip = {
        .ack = pnx4008_mask_ack_irq,
        .mask = pnx4008_mask_irq,
        .unmask = pnx4008_unmask_irq,
@@ -96,26 +96,24 @@ void __init pnx4008_init_irq(void)
 {
        unsigned int i;
 
-       /* configure and enable IRQ 0,1,30,31 (cascade interrupts) mask all others */
+       /* configure IRQ's */
+       for (i = 0; i < NR_IRQS; i++) {
+               set_irq_flags(i, IRQF_VALID);
+               set_irq_chip(i, &pnx4008_irq_chip);
+               pnx4008_set_irq_type(i, pnx4008_irq_type[i]);
+       }
+
+       /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */
        pnx4008_set_irq_type(SUB1_IRQ_N, pnx4008_irq_type[SUB1_IRQ_N]);
        pnx4008_set_irq_type(SUB2_IRQ_N, pnx4008_irq_type[SUB2_IRQ_N]);
        pnx4008_set_irq_type(SUB1_FIQ_N, pnx4008_irq_type[SUB1_FIQ_N]);
        pnx4008_set_irq_type(SUB2_FIQ_N, pnx4008_irq_type[SUB2_FIQ_N]);
 
+       /* mask all others */
        __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |
                        (1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N),
                INTC_ER(MAIN_BASE_INT));
        __raw_writel(0, INTC_ER(SIC1_BASE_INT));
        __raw_writel(0, INTC_ER(SIC2_BASE_INT));
-
-       /* configure all other IRQ's */
-       for (i = 0; i < NR_IRQS; i++) {
-               if (i == SUB2_FIQ_N || i == SUB1_FIQ_N ||
-                       i == SUB2_IRQ_N || i == SUB1_IRQ_N)
-                       continue;
-               set_irq_flags(i, IRQF_VALID);
-               set_irq_chip(i, &pnx4008_irq_chip);
-               pnx4008_set_irq_type(i, pnx4008_irq_type[i]);
-       }
 }