drivers/usb/dwc2/hcd.c

   1 /*
   2  * hcd.c - DesignWare HS OTG Controller host-mode routines
   3  *
   4  * Copyright (C) 2004-2013 Synopsys, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /*
  38  * This file contains the core HCD code, and implements the Linux hc_driver
  39  * API
  40  */
  41 #include <linux/kernel.h>
  42 #include <linux/module.h>
  43 #include <linux/spinlock.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/delay.h>
  47 #include <linux/io.h>
  48 #include <linux/slab.h>
  49 #include <linux/usb.h>
  50
  51 #include <linux/usb/hcd.h>
  52 #include <linux/usb/ch11.h>
  53
  54 #include "core.h"
  55 #include "hcd.h"
  56
  57 /**
  58  * dwc2_dump_channel_info() - Prints the state of a host channel
  59  *
  60  * @hsotg: Programming view of DWC_otg controller
  61  * @chan:  Pointer to the channel to dump
  62  *
  63  * Must be called with interrupt disabled and spinlock held
  64  *
  65  * NOTE: This function will be removed once the peripheral controller code
  66  * is integrated and the driver is stable
  67  */
  68 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
  69                                    struct dwc2_host_chan *chan)
  70 {
  71 #ifdef VERBOSE_DEBUG
  72         int num_channels = hsotg->core_params->host_channels;
  73         struct dwc2_qh *qh;
  74         u32 hcchar;
  75         u32 hcsplt;
  76         u32 hctsiz;
  77         u32 hc_dma;
  78         int i;
  79
  80         if (chan == NULL)
  81                 return;
  82
  83         hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
  84         hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num));
  85         hctsiz = readl(hsotg->regs + HCTSIZ(chan->hc_num));
  86         hc_dma = readl(hsotg->regs + HCDMA(chan->hc_num));
  87
  88         dev_dbg(hsotg->dev, "  Assigned to channel %p:\n", chan);
  89         dev_dbg(hsotg->dev, "    hcchar 0x%08x, hcsplt 0x%08x\n",
  90                 hcchar, hcsplt);
  91         dev_dbg(hsotg->dev, "    hctsiz 0x%08x, hc_dma 0x%08x\n",
  92                 hctsiz, hc_dma);
  93         dev_dbg(hsotg->dev, "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
  94                 chan->dev_addr, chan->ep_num, chan->ep_is_in);
  95         dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
  96         dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
  97         dev_dbg(hsotg->dev, "    data_pid_start: %d\n", chan->data_pid_start);
  98         dev_dbg(hsotg->dev, "    xfer_started: %d\n", chan->xfer_started);
  99         dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
 100         dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
 101         dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
 102                 (unsigned long)chan->xfer_dma);
 103         dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
 104         dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
 105         dev_dbg(hsotg->dev, "  NP inactive sched:\n");
 106         list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
 107                             qh_list_entry)
 108                 dev_dbg(hsotg->dev, "    %p\n", qh);
 109         dev_dbg(hsotg->dev, "  NP active sched:\n");
 110         list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
 111                             qh_list_entry)
 112                 dev_dbg(hsotg->dev, "    %p\n", qh);
 113         dev_dbg(hsotg->dev, "  Channels:\n");
 114         for (i = 0; i < num_channels; i++) {
 115                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
 116
 117                 dev_dbg(hsotg->dev, "    %2d: %p\n", i, chan);
 118         }
 119 #endif /* VERBOSE_DEBUG */
 120 }
 121
 122 /*
 123  * Processes all the URBs in a single list of QHs. Completes them with
 124  * -ETIMEDOUT and frees the QTD.
 125  *
 126  * Must be called with interrupt disabled and spinlock held
 127  */
 128 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
 129                                       struct list_head *qh_list)
 130 {
 131         struct dwc2_qh *qh, *qh_tmp;
 132         struct dwc2_qtd *qtd, *qtd_tmp;
 133
 134         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
 135                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
 136                                          qtd_list_entry) {
 137                         dwc2_host_complete(hsotg, qtd, -ETIMEDOUT);
 138                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 139                 }
 140         }
 141 }
 142
 143 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
 144                               struct list_head *qh_list)
 145 {
 146         struct dwc2_qtd *qtd, *qtd_tmp;
 147         struct dwc2_qh *qh, *qh_tmp;
 148         unsigned long flags;
 149
 150         if (!qh_list->next)
 151                 /* The list hasn't been initialized yet */
 152                 return;
 153
 154         spin_lock_irqsave(&hsotg->lock, flags);
 155
 156         /* Ensure there are no QTDs or URBs left */
 157         dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
 158
 159         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
 160                 dwc2_hcd_qh_unlink(hsotg, qh);
 161
 162                 /* Free each QTD in the QH's QTD list */
 163                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
 164                                          qtd_list_entry)
 165                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 166
 167                 spin_unlock_irqrestore(&hsotg->lock, flags);
 168                 dwc2_hcd_qh_free(hsotg, qh);
 169                 spin_lock_irqsave(&hsotg->lock, flags);
 170         }
 171
 172         spin_unlock_irqrestore(&hsotg->lock, flags);
 173 }
 174
 175 /*
 176  * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
 177  * and periodic schedules. The QTD associated with each URB is removed from
 178  * the schedule and freed. This function may be called when a disconnect is
 179  * detected or when the HCD is being stopped.
 180  *
 181  * Must be called with interrupt disabled and spinlock held
 182  */
 183 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
 184 {
 185         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
 186         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
 187         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
 188         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
 189         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
 190         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
 191 }
 192
 193 /**
 194  * dwc2_hcd_start() - Starts the HCD when switching to Host mode
 195  *
 196  * @hsotg: Pointer to struct dwc2_hsotg
 197  */
 198 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
 199 {
 200         u32 hprt0;
 201
 202         if (hsotg->op_state == OTG_STATE_B_HOST) {
 203                 /*
 204                  * Reset the port. During a HNP mode switch the reset
 205                  * needs to occur within 1ms and have a duration of at
 206                  * least 50ms.
 207                  */
 208                 hprt0 = dwc2_read_hprt0(hsotg);
 209                 hprt0 |= HPRT0_RST;
 210                 writel(hprt0, hsotg->regs + HPRT0);
 211         }
 212
 213         queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
 214                            msecs_to_jiffies(50));
 215 }
 216
 217 /* Must be called with interrupt disabled and spinlock held */
 218 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
 219 {
 220         int num_channels = hsotg->core_params->host_channels;
 221         struct dwc2_host_chan *channel;
 222         u32 hcchar;
 223         int i;
 224
 225         if (hsotg->core_params->dma_enable <= 0) {
 226                 /* Flush out any channel requests in slave mode */
 227                 for (i = 0; i < num_channels; i++) {
 228                         channel = hsotg->hc_ptr_array[i];
 229                         if (!list_empty(&channel->hc_list_entry))
 230                                 continue;
 231                         hcchar = readl(hsotg->regs + HCCHAR(i));
 232                         if (hcchar & HCCHAR_CHENA) {
 233                                 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
 234                                 hcchar |= HCCHAR_CHDIS;
 235                                 writel(hcchar, hsotg->regs + HCCHAR(i));
 236                         }
 237                 }
 238         }
 239
 240         for (i = 0; i < num_channels; i++) {
 241                 channel = hsotg->hc_ptr_array[i];
 242                 if (!list_empty(&channel->hc_list_entry))
 243                         continue;
 244                 hcchar = readl(hsotg->regs + HCCHAR(i));
 245                 if (hcchar & HCCHAR_CHENA) {
 246                         /* Halt the channel */
 247                         hcchar |= HCCHAR_CHDIS;
 248                         writel(hcchar, hsotg->regs + HCCHAR(i));
 249                 }
 250
 251                 dwc2_hc_cleanup(hsotg, channel);
 252                 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
 253                 /*
 254                  * Added for Descriptor DMA to prevent channel double cleanup in
 255                  * release_channel_ddma(), which is called from ep_disable when
 256                  * device disconnects
 257                  */
 258                 channel->qh = NULL;
 259         }
 260         /* All channels have been freed, mark them available */
 261         if (hsotg->core_params->uframe_sched > 0) {
 262                 hsotg->available_host_channels =
 263                         hsotg->core_params->host_channels;
 264         } else {
 265                 hsotg->non_periodic_channels = 0;
 266                 hsotg->periodic_channels = 0;
 267         }
 268 }
 269
 270 /**
 271  * dwc2_hcd_disconnect() - Handles disconnect of the HCD
 272  *
 273  * @hsotg: Pointer to struct dwc2_hsotg
 274  *
 275  * Must be called with interrupt disabled and spinlock held
 276  */
 277 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg)
 278 {
 279         u32 intr;
 280
 281         /* Set status flags for the hub driver */
 282         hsotg->flags.b.port_connect_status_change = 1;
 283         hsotg->flags.b.port_connect_status = 0;
 284
 285         /*
 286          * Shutdown any transfers in process by clearing the Tx FIFO Empty
 287          * interrupt mask and status bits and disabling subsequent host
 288          * channel interrupts.
 289          */
 290         intr = readl(hsotg->regs + GINTMSK);
 291         intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
 292         writel(intr, hsotg->regs + GINTMSK);
 293         intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
 294         writel(intr, hsotg->regs + GINTSTS);
 295
 296         /*
 297          * Turn off the vbus power only if the core has transitioned to device
 298          * mode. If still in host mode, need to keep power on to detect a
 299          * reconnection.
 300          */
 301         if (dwc2_is_device_mode(hsotg)) {
 302                 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
 303                         dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
 304                         writel(0, hsotg->regs + HPRT0);
 305                 }
 306
 307                 dwc2_disable_host_interrupts(hsotg);
 308         }
 309
 310         /* Respond with an error status to all URBs in the schedule */
 311         dwc2_kill_all_urbs(hsotg);
 312
 313         if (dwc2_is_host_mode(hsotg))
 314                 /* Clean up any host channels that were in use */
 315                 dwc2_hcd_cleanup_channels(hsotg);
 316
 317         dwc2_host_disconnect(hsotg);
 318 }
 319
 320 /**
 321  * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
 322  *
 323  * @hsotg: Pointer to struct dwc2_hsotg
 324  */
 325 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
 326 {
 327         if (hsotg->lx_state == DWC2_L2) {
 328                 hsotg->flags.b.port_suspend_change = 1;
 329                 usb_hcd_resume_root_hub(hsotg->priv);
 330         } else {
 331                 hsotg->flags.b.port_l1_change = 1;
 332         }
 333 }
 334
 335 /**
 336  * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
 337  *
 338  * @hsotg: Pointer to struct dwc2_hsotg
 339  *
 340  * Must be called with interrupt disabled and spinlock held
 341  */
 342 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
 343 {
 344         dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
 345
 346         /*
 347          * The root hub should be disconnected before this function is called.
 348          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
 349          * and the QH lists (via ..._hcd_endpoint_disable).
 350          */
 351
 352         /* Turn off all host-specific interrupts */
 353         dwc2_disable_host_interrupts(hsotg);
 354
 355         /* Turn off the vbus power */
 356         dev_dbg(hsotg->dev, "PortPower off\n");
 357         writel(0, hsotg->regs + HPRT0);
 358 }
 359
 360 /* Caller must hold driver lock */
 361 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
 362                                 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
 363                                 struct dwc2_qtd *qtd)
 364 {
 365         u32 intr_mask;
 366         int retval;
 367         int dev_speed;
 368
 369         if (!hsotg->flags.b.port_connect_status) {
 370                 /* No longer connected */
 371                 dev_err(hsotg->dev, "Not connected\n");
 372                 return -ENODEV;
 373         }
 374
 375         dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
 376
 377         /* Some configurations cannot support LS traffic on a FS root port */
 378         if ((dev_speed == USB_SPEED_LOW) &&
 379             (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
 380             (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
 381                 u32 hprt0 = readl(hsotg->regs + HPRT0);
 382                 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
 383
 384                 if (prtspd == HPRT0_SPD_FULL_SPEED)
 385                         return -ENODEV;
 386         }
 387
 388         if (!qtd)
 389                 return -EINVAL;
 390
 391         dwc2_hcd_qtd_init(qtd, urb);
 392         retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
 393         if (retval) {
 394                 dev_err(hsotg->dev,
 395                         "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
 396                         retval);
 397                 return retval;
 398         }
 399
 400         intr_mask = readl(hsotg->regs + GINTMSK);
 401         if (!(intr_mask & GINTSTS_SOF)) {
 402                 enum dwc2_transaction_type tr_type;
 403
 404                 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
 405                     !(qtd->urb->flags & URB_GIVEBACK_ASAP))
 406                         /*
 407                          * Do not schedule SG transactions until qtd has
 408                          * URB_GIVEBACK_ASAP set
 409                          */
 410                         return 0;
 411
 412                 tr_type = dwc2_hcd_select_transactions(hsotg);
 413                 if (tr_type != DWC2_TRANSACTION_NONE)
 414                         dwc2_hcd_queue_transactions(hsotg, tr_type);
 415         }
 416
 417         return 0;
 418 }
 419
 420 /* Must be called with interrupt disabled and spinlock held */
 421 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
 422                                 struct dwc2_hcd_urb *urb)
 423 {
 424         struct dwc2_qh *qh;
 425         struct dwc2_qtd *urb_qtd;
 426
 427         urb_qtd = urb->qtd;
 428         if (!urb_qtd) {
 429                 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
 430                 return -EINVAL;
 431         }
 432
 433         qh = urb_qtd->qh;
 434         if (!qh) {
 435                 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
 436                 return -EINVAL;
 437         }
 438
 439         urb->priv = NULL;
 440
 441         if (urb_qtd->in_process && qh->channel) {
 442                 dwc2_dump_channel_info(hsotg, qh->channel);
 443
 444                 /* The QTD is in process (it has been assigned to a channel) */
 445                 if (hsotg->flags.b.port_connect_status)
 446                         /*
 447                          * If still connected (i.e. in host mode), halt the
 448                          * channel so it can be used for other transfers. If
 449                          * no longer connected, the host registers can't be
 450                          * written to halt the channel since the core is in
 451                          * device mode.
 452                          */
 453                         dwc2_hc_halt(hsotg, qh->channel,
 454                                      DWC2_HC_XFER_URB_DEQUEUE);
 455         }
 456
 457         /*
 458          * Free the QTD and clean up the associated QH. Leave the QH in the
 459          * schedule if it has any remaining QTDs.
 460          */
 461         if (hsotg->core_params->dma_desc_enable <= 0) {
 462                 u8 in_process = urb_qtd->in_process;
 463
 464                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
 465                 if (in_process) {
 466                         dwc2_hcd_qh_deactivate(hsotg, qh, 0);
 467                         qh->channel = NULL;
 468                 } else if (list_empty(&qh->qtd_list)) {
 469                         dwc2_hcd_qh_unlink(hsotg, qh);
 470                 }
 471         } else {
 472                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
 473         }
 474
 475         return 0;
 476 }
 477
 478 /* Must NOT be called with interrupt disabled or spinlock held */
 479 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
 480                                      struct usb_host_endpoint *ep, int retry)
 481 {
 482         struct dwc2_qtd *qtd, *qtd_tmp;
 483         struct dwc2_qh *qh;
 484         unsigned long flags;
 485         int rc;
 486
 487         spin_lock_irqsave(&hsotg->lock, flags);
 488
 489         qh = ep->hcpriv;
 490         if (!qh) {
 491                 rc = -EINVAL;
 492                 goto err;
 493         }
 494
 495         while (!list_empty(&qh->qtd_list) && retry--) {
 496                 if (retry == 0) {
 497                         dev_err(hsotg->dev,
 498                                 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
 499                         rc = -EBUSY;
 500                         goto err;
 501                 }
 502
 503                 spin_unlock_irqrestore(&hsotg->lock, flags);
 504                 usleep_range(20000, 40000);
 505                 spin_lock_irqsave(&hsotg->lock, flags);
 506                 qh = ep->hcpriv;
 507                 if (!qh) {
 508                         rc = -EINVAL;
 509                         goto err;
 510                 }
 511         }
 512
 513         dwc2_hcd_qh_unlink(hsotg, qh);
 514
 515         /* Free each QTD in the QH's QTD list */
 516         list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
 517                 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 518
 519         ep->hcpriv = NULL;
 520         spin_unlock_irqrestore(&hsotg->lock, flags);
 521         dwc2_hcd_qh_free(hsotg, qh);
 522
 523         return 0;
 524
 525 err:
 526         ep->hcpriv = NULL;
 527         spin_unlock_irqrestore(&hsotg->lock, flags);
 528
 529         return rc;
 530 }
 531
 532 /* Must be called with interrupt disabled and spinlock held */
 533 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
 534                                    struct usb_host_endpoint *ep)
 535 {
 536         struct dwc2_qh *qh = ep->hcpriv;
 537
 538         if (!qh)
 539                 return -EINVAL;
 540
 541         qh->data_toggle = DWC2_HC_PID_DATA0;
 542
 543         return 0;
 544 }
 545
 546 /*
 547  * Initializes dynamic portions of the DWC_otg HCD state
 548  *
 549  * Must be called with interrupt disabled and spinlock held
 550  */
 551 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
 552 {
 553         struct dwc2_host_chan *chan, *chan_tmp;
 554         int num_channels;
 555         int i;
 556
 557         hsotg->flags.d32 = 0;
 558         hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
 559
 560         if (hsotg->core_params->uframe_sched > 0) {
 561                 hsotg->available_host_channels =
 562                         hsotg->core_params->host_channels;
 563         } else {
 564                 hsotg->non_periodic_channels = 0;
 565                 hsotg->periodic_channels = 0;
 566         }
 567
 568         /*
 569          * Put all channels in the free channel list and clean up channel
 570          * states
 571          */
 572         list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
 573                                  hc_list_entry)
 574                 list_del_init(&chan->hc_list_entry);
 575
 576         num_channels = hsotg->core_params->host_channels;
 577         for (i = 0; i < num_channels; i++) {
 578                 chan = hsotg->hc_ptr_array[i];
 579                 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
 580                 dwc2_hc_cleanup(hsotg, chan);
 581         }
 582
 583         /* Initialize the DWC core for host mode operation */
 584         dwc2_core_host_init(hsotg);
 585 }
 586
 587 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
 588                                struct dwc2_host_chan *chan,
 589                                struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
 590 {
 591         int hub_addr, hub_port;
 592
 593         chan->do_split = 1;
 594         chan->xact_pos = qtd->isoc_split_pos;
 595         chan->complete_split = qtd->complete_split;
 596         dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
 597         chan->hub_addr = (u8)hub_addr;
 598         chan->hub_port = (u8)hub_port;
 599 }
 600
 601 static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
 602                                struct dwc2_host_chan *chan,
 603                                struct dwc2_qtd *qtd, void *bufptr)
 604 {
 605         struct dwc2_hcd_urb *urb = qtd->urb;
 606         struct dwc2_hcd_iso_packet_desc *frame_desc;
 607
 608         switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
 609         case USB_ENDPOINT_XFER_CONTROL:
 610                 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
 611
 612                 switch (qtd->control_phase) {
 613                 case DWC2_CONTROL_SETUP:
 614                         dev_vdbg(hsotg->dev, "  Control setup transaction\n");
 615                         chan->do_ping = 0;
 616                         chan->ep_is_in = 0;
 617                         chan->data_pid_start = DWC2_HC_PID_SETUP;
 618                         if (hsotg->core_params->dma_enable > 0)
 619                                 chan->xfer_dma = urb->setup_dma;
 620                         else
 621                                 chan->xfer_buf = urb->setup_packet;
 622                         chan->xfer_len = 8;
 623                         bufptr = NULL;
 624                         break;
 625
 626                 case DWC2_CONTROL_DATA:
 627                         dev_vdbg(hsotg->dev, "  Control data transaction\n");
 628                         chan->data_pid_start = qtd->data_toggle;
 629                         break;
 630
 631                 case DWC2_CONTROL_STATUS:
 632                         /*
 633                          * Direction is opposite of data direction or IN if no
 634                          * data
 635                          */
 636                         dev_vdbg(hsotg->dev, "  Control status transaction\n");
 637                         if (urb->length == 0)
 638                                 chan->ep_is_in = 1;
 639                         else
 640                                 chan->ep_is_in =
 641                                         dwc2_hcd_is_pipe_out(&urb->pipe_info);
 642                         if (chan->ep_is_in)
 643                                 chan->do_ping = 0;
 644                         chan->data_pid_start = DWC2_HC_PID_DATA1;
 645                         chan->xfer_len = 0;
 646                         if (hsotg->core_params->dma_enable > 0)
 647                                 chan->xfer_dma = hsotg->status_buf_dma;
 648                         else
 649                                 chan->xfer_buf = hsotg->status_buf;
 650                         bufptr = NULL;
 651                         break;
 652                 }
 653                 break;
 654
 655         case USB_ENDPOINT_XFER_BULK:
 656                 chan->ep_type = USB_ENDPOINT_XFER_BULK;
 657                 break;
 658
 659         case USB_ENDPOINT_XFER_INT:
 660                 chan->ep_type = USB_ENDPOINT_XFER_INT;
 661                 break;
 662
 663         case USB_ENDPOINT_XFER_ISOC:
 664                 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
 665                 if (hsotg->core_params->dma_desc_enable > 0)
 666                         break;
 667
 668                 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 669                 frame_desc->status = 0;
 670
 671                 if (hsotg->core_params->dma_enable > 0) {
 672                         chan->xfer_dma = urb->dma;
 673                         chan->xfer_dma += frame_desc->offset +
 674                                         qtd->isoc_split_offset;
 675                 } else {
 676                         chan->xfer_buf = urb->buf;
 677                         chan->xfer_buf += frame_desc->offset +
 678                                         qtd->isoc_split_offset;
 679                 }
 680
 681                 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
 682
 683                 /* For non-dword aligned buffers */
 684                 if (hsotg->core_params->dma_enable > 0 &&
 685                     (chan->xfer_dma & 0x3))
 686                         bufptr = (u8 *)urb->buf + frame_desc->offset +
 687                                         qtd->isoc_split_offset;
 688                 else
 689                         bufptr = NULL;
 690
 691                 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
 692                         if (chan->xfer_len <= 188)
 693                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
 694                         else
 695                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
 696                 }
 697                 break;
 698         }
 699
 700         return bufptr;
 701 }
 702
 703 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
 704                                    struct dwc2_host_chan *chan,
 705                                    struct dwc2_hcd_urb *urb, void *bufptr)
 706 {
 707         u32 buf_size;
 708         struct urb *usb_urb;
 709         struct usb_hcd *hcd;
 710
 711         if (!qh->dw_align_buf) {
 712                 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC)
 713                         buf_size = hsotg->core_params->max_transfer_size;
 714                 else
 715                         /* 3072 = 3 max-size Isoc packets */
 716                         buf_size = 3072;
 717
 718                 qh->dw_align_buf = kmalloc(buf_size, GFP_ATOMIC | GFP_DMA);
 719                 if (!qh->dw_align_buf)
 720                         return -ENOMEM;
 721                 qh->dw_align_buf_size = buf_size;
 722         }
 723
 724         if (chan->xfer_len) {
 725                 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
 726                 usb_urb = urb->priv;
 727
 728                 if (usb_urb) {
 729                         if (usb_urb->transfer_flags &
 730                             (URB_SETUP_MAP_SINGLE | URB_DMA_MAP_SG |
 731                              URB_DMA_MAP_PAGE | URB_DMA_MAP_SINGLE)) {
 732                                 hcd = dwc2_hsotg_to_hcd(hsotg);
 733                                 usb_hcd_unmap_urb_for_dma(hcd, usb_urb);
 734                         }
 735                         if (!chan->ep_is_in)
 736                                 memcpy(qh->dw_align_buf, bufptr,
 737                                        chan->xfer_len);
 738                 } else {
 739                         dev_warn(hsotg->dev, "no URB in dwc2_urb\n");
 740                 }
 741         }
 742
 743         qh->dw_align_buf_dma = dma_map_single(hsotg->dev,
 744                         qh->dw_align_buf, qh->dw_align_buf_size,
 745                         chan->ep_is_in ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
 746         if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) {
 747                 dev_err(hsotg->dev, "can't map align_buf\n");
 748                 chan->align_buf = 0;
 749                 return -EINVAL;
 750         }
 751
 752         chan->align_buf = qh->dw_align_buf_dma;
 753         return 0;
 754 }
 755
 756 /**
 757  * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
 758  * channel and initializes the host channel to perform the transactions. The
 759  * host channel is removed from the free list.
 760  *
 761  * @hsotg: The HCD state structure
 762  * @qh:    Transactions from the first QTD for this QH are selected and assigned
 763  *         to a free host channel
 764  */
 765 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
 766 {
 767         struct dwc2_host_chan *chan;
 768         struct dwc2_hcd_urb *urb;
 769         struct dwc2_qtd *qtd;
 770         void *bufptr = NULL;
 771
 772         if (dbg_qh(qh))
 773                 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
 774
 775         if (list_empty(&qh->qtd_list)) {
 776                 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
 777                 return -ENOMEM;
 778         }
 779
 780         if (list_empty(&hsotg->free_hc_list)) {
 781                 dev_dbg(hsotg->dev, "No free channel to assign\n");
 782                 return -ENOMEM;
 783         }
 784
 785         chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
 786                                 hc_list_entry);
 787
 788         /* Remove host channel from free list */
 789         list_del_init(&chan->hc_list_entry);
 790
 791         qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
 792         urb = qtd->urb;
 793         qh->channel = chan;
 794         qtd->in_process = 1;
 795
 796         /*
 797          * Use usb_pipedevice to determine device address. This address is
 798          * 0 before the SET_ADDRESS command and the correct address afterward.
 799          */
 800         chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
 801         chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
 802         chan->speed = qh->dev_speed;
 803         chan->max_packet = dwc2_max_packet(qh->maxp);
 804
 805         chan->xfer_started = 0;
 806         chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
 807         chan->error_state = (qtd->error_count > 0);
 808         chan->halt_on_queue = 0;
 809         chan->halt_pending = 0;
 810         chan->requests = 0;
 811
 812         /*
 813          * The following values may be modified in the transfer type section
 814          * below. The xfer_len value may be reduced when the transfer is
 815          * started to accommodate the max widths of the XferSize and PktCnt
 816          * fields in the HCTSIZn register.
 817          */
 818
 819         chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
 820         if (chan->ep_is_in)
 821                 chan->do_ping = 0;
 822         else
 823                 chan->do_ping = qh->ping_state;
 824
 825         chan->data_pid_start = qh->data_toggle;
 826         chan->multi_count = 1;
 827
 828         if (urb->actual_length > urb->length &&
 829                 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
 830                 urb->actual_length = urb->length;
 831
 832         if (hsotg->core_params->dma_enable > 0) {
 833                 chan->xfer_dma = urb->dma + urb->actual_length;
 834
 835                 /* For non-dword aligned case */
 836                 if (hsotg->core_params->dma_desc_enable <= 0 &&
 837                     (chan->xfer_dma & 0x3))
 838                         bufptr = (u8 *)urb->buf + urb->actual_length;
 839         } else {
 840                 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
 841         }
 842
 843         chan->xfer_len = urb->length - urb->actual_length;
 844         chan->xfer_count = 0;
 845
 846         /* Set the split attributes if required */
 847         if (qh->do_split)
 848                 dwc2_hc_init_split(hsotg, chan, qtd, urb);
 849         else
 850                 chan->do_split = 0;
 851
 852         /* Set the transfer attributes */
 853         bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr);
 854
 855         /* Non DWORD-aligned buffer case */
 856         if (bufptr) {
 857                 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
 858                 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, urb, bufptr)) {
 859                         dev_err(hsotg->dev,
 860                                 "%s: Failed to allocate memory to handle non-dword aligned buffer\n",
 861                                 __func__);
 862                         /* Add channel back to free list */
 863                         chan->align_buf = 0;
 864                         chan->multi_count = 0;
 865                         list_add_tail(&chan->hc_list_entry,
 866                                       &hsotg->free_hc_list);
 867                         qtd->in_process = 0;
 868                         qh->channel = NULL;
 869                         return -ENOMEM;
 870                 }
 871         } else {
 872                 chan->align_buf = 0;
 873         }
 874
 875         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
 876             chan->ep_type == USB_ENDPOINT_XFER_ISOC)
 877                 /*
 878                  * This value may be modified when the transfer is started
 879                  * to reflect the actual transfer length
 880                  */
 881                 chan->multi_count = dwc2_hb_mult(qh->maxp);
 882
 883         if (hsotg->core_params->dma_desc_enable > 0)
 884                 chan->desc_list_addr = qh->desc_list_dma;
 885
 886         dwc2_hc_init(hsotg, chan);
 887         chan->qh = qh;
 888
 889         return 0;
 890 }
 891
 892 /**
 893  * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
 894  * schedule and assigns them to available host channels. Called from the HCD
 895  * interrupt handler functions.
 896  *
 897  * @hsotg: The HCD state structure
 898  *
 899  * Return: The types of new transactions that were assigned to host channels
 900  */
 901 enum dwc2_transaction_type dwc2_hcd_select_transactions(
 902                 struct dwc2_hsotg *hsotg)
 903 {
 904         enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
 905         struct list_head *qh_ptr;
 906         struct dwc2_qh *qh;
 907         int num_channels;
 908
 909 #ifdef DWC2_DEBUG_SOF
 910         dev_vdbg(hsotg->dev, "  Select Transactions\n");
 911 #endif
 912
 913         /* Process entries in the periodic ready list */
 914         qh_ptr = hsotg->periodic_sched_ready.next;
 915         while (qh_ptr != &hsotg->periodic_sched_ready) {
 916                 if (list_empty(&hsotg->free_hc_list))
 917                         break;
 918                 if (hsotg->core_params->uframe_sched > 0) {
 919                         if (hsotg->available_host_channels <= 1)
 920                                 break;
 921                         hsotg->available_host_channels--;
 922                 }
 923                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
 924                 if (dwc2_assign_and_init_hc(hsotg, qh))
 925                         break;
 926
 927                 /*
 928                  * Move the QH from the periodic ready schedule to the
 929                  * periodic assigned schedule
 930                  */
 931                 qh_ptr = qh_ptr->next;
 932                 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned);
 933                 ret_val = DWC2_TRANSACTION_PERIODIC;
 934         }
 935
 936         /*
 937          * Process entries in the inactive portion of the non-periodic
 938          * schedule. Some free host channels may not be used if they are
 939          * reserved for periodic transfers.
 940          */
 941         num_channels = hsotg->core_params->host_channels;
 942         qh_ptr = hsotg->non_periodic_sched_inactive.next;
 943         while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
 944                 if (hsotg->core_params->uframe_sched <= 0 &&
 945                     hsotg->non_periodic_channels >= num_channels -
 946                                                 hsotg->periodic_channels)
 947                         break;
 948                 if (list_empty(&hsotg->free_hc_list))
 949                         break;
 950                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
 951                 if (hsotg->core_params->uframe_sched > 0) {
 952                         if (hsotg->available_host_channels < 1)
 953                                 break;
 954                         hsotg->available_host_channels--;
 955                 }
 956
 957                 if (dwc2_assign_and_init_hc(hsotg, qh))
 958                         break;
 959
 960                 /*
 961                  * Move the QH from the non-periodic inactive schedule to the
 962                  * non-periodic active schedule
 963                  */
 964                 qh_ptr = qh_ptr->next;
 965                 list_move(&qh->qh_list_entry,
 966                           &hsotg->non_periodic_sched_active);
 967
 968                 if (ret_val == DWC2_TRANSACTION_NONE)
 969                         ret_val = DWC2_TRANSACTION_NON_PERIODIC;
 970                 else
 971                         ret_val = DWC2_TRANSACTION_ALL;
 972
 973                 if (hsotg->core_params->uframe_sched <= 0)
 974                         hsotg->non_periodic_channels++;
 975         }
 976
 977         return ret_val;
 978 }
 979
 980 /**
 981  * dwc2_queue_transaction() - Attempts to queue a single transaction request for
 982  * a host channel associated with either a periodic or non-periodic transfer
 983  *
 984  * @hsotg: The HCD state structure
 985  * @chan:  Host channel descriptor associated with either a periodic or
 986  *         non-periodic transfer
 987  * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
 988  *                     for periodic transfers or the non-periodic Tx FIFO
 989  *                     for non-periodic transfers
 990  *
 991  * Return: 1 if a request is queued and more requests may be needed to
 992  * complete the transfer, 0 if no more requests are required for this
 993  * transfer, -1 if there is insufficient space in the Tx FIFO
 994  *
 995  * This function assumes that there is space available in the appropriate
 996  * request queue. For an OUT transfer or SETUP transaction in Slave mode,
 997  * it checks whether space is available in the appropriate Tx FIFO.
 998  *
 999  * Must be called with interrupt disabled and spinlock held
1000  */
1001 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
1002                                   struct dwc2_host_chan *chan,
1003                                   u16 fifo_dwords_avail)
1004 {
1005         int retval = 0;
1006
1007         if (hsotg->core_params->dma_enable > 0) {
1008                 if (hsotg->core_params->dma_desc_enable > 0) {
1009                         if (!chan->xfer_started ||
1010                             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1011                                 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
1012                                 chan->qh->ping_state = 0;
1013                         }
1014                 } else if (!chan->xfer_started) {
1015                         dwc2_hc_start_transfer(hsotg, chan);
1016                         chan->qh->ping_state = 0;
1017                 }
1018         } else if (chan->halt_pending) {
1019                 /* Don't queue a request if the channel has been halted */
1020         } else if (chan->halt_on_queue) {
1021                 dwc2_hc_halt(hsotg, chan, chan->halt_status);
1022         } else if (chan->do_ping) {
1023                 if (!chan->xfer_started)
1024                         dwc2_hc_start_transfer(hsotg, chan);
1025         } else if (!chan->ep_is_in ||
1026                    chan->data_pid_start == DWC2_HC_PID_SETUP) {
1027                 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
1028                         if (!chan->xfer_started) {
1029                                 dwc2_hc_start_transfer(hsotg, chan);
1030                                 retval = 1;
1031                         } else {
1032                                 retval = dwc2_hc_continue_transfer(hsotg, chan);
1033                         }
1034                 } else {
1035                         retval = -1;
1036                 }
1037         } else {
1038                 if (!chan->xfer_started) {
1039                         dwc2_hc_start_transfer(hsotg, chan);
1040                         retval = 1;
1041                 } else {
1042                         retval = dwc2_hc_continue_transfer(hsotg, chan);
1043                 }
1044         }
1045
1046         return retval;
1047 }
1048
1049 /*
1050  * Processes periodic channels for the next frame and queues transactions for
1051  * these channels to the DWC_otg controller. After queueing transactions, the
1052  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1053  * to queue as Periodic Tx FIFO or request queue space becomes available.
1054  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1055  *
1056  * Must be called with interrupt disabled and spinlock held
1057  */
1058 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
1059 {
1060         struct list_head *qh_ptr;
1061         struct dwc2_qh *qh;
1062         u32 tx_status;
1063         u32 fspcavail;
1064         u32 gintmsk;
1065         int status;
1066         int no_queue_space = 0;
1067         int no_fifo_space = 0;
1068         u32 qspcavail;
1069
1070         if (dbg_perio())
1071                 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
1072
1073         tx_status = readl(hsotg->regs + HPTXSTS);
1074         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1075                     TXSTS_QSPCAVAIL_SHIFT;
1076         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1077                     TXSTS_FSPCAVAIL_SHIFT;
1078
1079         if (dbg_perio()) {
1080                 dev_vdbg(hsotg->dev, "  P Tx Req Queue Space Avail (before queue): %d\n",
1081                          qspcavail);
1082                 dev_vdbg(hsotg->dev, "  P Tx FIFO Space Avail (before queue): %d\n",
1083                          fspcavail);
1084         }
1085
1086         qh_ptr = hsotg->periodic_sched_assigned.next;
1087         while (qh_ptr != &hsotg->periodic_sched_assigned) {
1088                 tx_status = readl(hsotg->regs + HPTXSTS);
1089                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1090                             TXSTS_QSPCAVAIL_SHIFT;
1091                 if (qspcavail == 0) {
1092                         no_queue_space = 1;
1093                         break;
1094                 }
1095
1096                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
1097                 if (!qh->channel) {
1098                         qh_ptr = qh_ptr->next;
1099                         continue;
1100                 }
1101
1102                 /* Make sure EP's TT buffer is clean before queueing qtds */
1103                 if (qh->tt_buffer_dirty) {
1104                         qh_ptr = qh_ptr->next;
1105                         continue;
1106                 }
1107
1108                 /*
1109                  * Set a flag if we're queuing high-bandwidth in slave mode.
1110                  * The flag prevents any halts to get into the request queue in
1111                  * the middle of multiple high-bandwidth packets getting queued.
1112                  */
1113                 if (hsotg->core_params->dma_enable <= 0 &&
1114                                 qh->channel->multi_count > 1)
1115                         hsotg->queuing_high_bandwidth = 1;
1116
1117                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1118                             TXSTS_FSPCAVAIL_SHIFT;
1119                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1120                 if (status < 0) {
1121                         no_fifo_space = 1;
1122                         break;
1123                 }
1124
1125                 /*
1126                  * In Slave mode, stay on the current transfer until there is
1127                  * nothing more to do or the high-bandwidth request count is
1128                  * reached. In DMA mode, only need to queue one request. The
1129                  * controller automatically handles multiple packets for
1130                  * high-bandwidth transfers.
1131                  */
1132                 if (hsotg->core_params->dma_enable > 0 || status == 0 ||
1133                     qh->channel->requests == qh->channel->multi_count) {
1134                         qh_ptr = qh_ptr->next;
1135                         /*
1136                          * Move the QH from the periodic assigned schedule to
1137                          * the periodic queued schedule
1138                          */
1139                         list_move(&qh->qh_list_entry,
1140                                   &hsotg->periodic_sched_queued);
1141
1142                         /* done queuing high bandwidth */
1143                         hsotg->queuing_high_bandwidth = 0;
1144                 }
1145         }
1146
1147         if (hsotg->core_params->dma_enable <= 0) {
1148                 tx_status = readl(hsotg->regs + HPTXSTS);
1149                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1150                             TXSTS_QSPCAVAIL_SHIFT;
1151                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1152                             TXSTS_FSPCAVAIL_SHIFT;
1153                 if (dbg_perio()) {
1154                         dev_vdbg(hsotg->dev,
1155                                  "  P Tx Req Queue Space Avail (after queue): %d\n",
1156                                  qspcavail);
1157                         dev_vdbg(hsotg->dev,
1158                                  "  P Tx FIFO Space Avail (after queue): %d\n",
1159                                  fspcavail);
1160                 }
1161
1162                 if (!list_empty(&hsotg->periodic_sched_assigned) ||
1163                     no_queue_space || no_fifo_space) {
1164                         /*
1165                          * May need to queue more transactions as the request
1166                          * queue or Tx FIFO empties. Enable the periodic Tx
1167                          * FIFO empty interrupt. (Always use the half-empty
1168                          * level to ensure that new requests are loaded as
1169                          * soon as possible.)
1170                          */
1171                         gintmsk = readl(hsotg->regs + GINTMSK);
1172                         gintmsk |= GINTSTS_PTXFEMP;
1173                         writel(gintmsk, hsotg->regs + GINTMSK);
1174                 } else {
1175                         /*
1176                          * Disable the Tx FIFO empty interrupt since there are
1177                          * no more transactions that need to be queued right
1178                          * now. This function is called from interrupt
1179                          * handlers to queue more transactions as transfer
1180                          * states change.
1181                          */
1182                         gintmsk = readl(hsotg->regs + GINTMSK);
1183                         gintmsk &= ~GINTSTS_PTXFEMP;
1184                         writel(gintmsk, hsotg->regs + GINTMSK);
1185                 }
1186         }
1187 }
1188
1189 /*
1190  * Processes active non-periodic channels and queues transactions for these
1191  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1192  * FIFO Empty interrupt is enabled if there are more transactions to queue as
1193  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1194  * FIFO Empty interrupt is disabled.
1195  *
1196  * Must be called with interrupt disabled and spinlock held
1197  */
1198 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
1199 {
1200         struct list_head *orig_qh_ptr;
1201         struct dwc2_qh *qh;
1202         u32 tx_status;
1203         u32 qspcavail;
1204         u32 fspcavail;
1205         u32 gintmsk;
1206         int status;
1207         int no_queue_space = 0;
1208         int no_fifo_space = 0;
1209         int more_to_do = 0;
1210
1211         dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
1212
1213         tx_status = readl(hsotg->regs + GNPTXSTS);
1214         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1215                     TXSTS_QSPCAVAIL_SHIFT;
1216         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1217                     TXSTS_FSPCAVAIL_SHIFT;
1218         dev_vdbg(hsotg->dev, "  NP Tx Req Queue Space Avail (before queue): %d\n",
1219                  qspcavail);
1220         dev_vdbg(hsotg->dev, "  NP Tx FIFO Space Avail (before queue): %d\n",
1221                  fspcavail);
1222
1223         /*
1224          * Keep track of the starting point. Skip over the start-of-list
1225          * entry.
1226          */
1227         if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
1228                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1229         orig_qh_ptr = hsotg->non_periodic_qh_ptr;
1230
1231         /*
1232          * Process once through the active list or until no more space is
1233          * available in the request queue or the Tx FIFO
1234          */
1235         do {
1236                 tx_status = readl(hsotg->regs + GNPTXSTS);
1237                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1238                             TXSTS_QSPCAVAIL_SHIFT;
1239                 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
1240                         no_queue_space = 1;
1241                         break;
1242                 }
1243
1244                 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
1245                                 qh_list_entry);
1246                 if (!qh->channel)
1247                         goto next;
1248
1249                 /* Make sure EP's TT buffer is clean before queueing qtds */
1250                 if (qh->tt_buffer_dirty)
1251                         goto next;
1252
1253                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1254                             TXSTS_FSPCAVAIL_SHIFT;
1255                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1256
1257                 if (status > 0) {
1258                         more_to_do = 1;
1259                 } else if (status < 0) {
1260                         no_fifo_space = 1;
1261                         break;
1262                 }
1263 next:
1264                 /* Advance to next QH, skipping start-of-list entry */
1265                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1266                 if (hsotg->non_periodic_qh_ptr ==
1267                                 &hsotg->non_periodic_sched_active)
1268                         hsotg->non_periodic_qh_ptr =
1269                                         hsotg->non_periodic_qh_ptr->next;
1270         } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
1271
1272         if (hsotg->core_params->dma_enable <= 0) {
1273                 tx_status = readl(hsotg->regs + GNPTXSTS);
1274                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1275                             TXSTS_QSPCAVAIL_SHIFT;
1276                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1277                             TXSTS_FSPCAVAIL_SHIFT;
1278                 dev_vdbg(hsotg->dev,
1279                          "  NP Tx Req Queue Space Avail (after queue): %d\n",
1280                          qspcavail);
1281                 dev_vdbg(hsotg->dev,
1282                          "  NP Tx FIFO Space Avail (after queue): %d\n",
1283                          fspcavail);
1284
1285                 if (more_to_do || no_queue_space || no_fifo_space) {
1286                         /*
1287                          * May need to queue more transactions as the request
1288                          * queue or Tx FIFO empties. Enable the non-periodic
1289                          * Tx FIFO empty interrupt. (Always use the half-empty
1290                          * level to ensure that new requests are loaded as
1291                          * soon as possible.)
1292                          */
1293                         gintmsk = readl(hsotg->regs + GINTMSK);
1294                         gintmsk |= GINTSTS_NPTXFEMP;
1295                         writel(gintmsk, hsotg->regs + GINTMSK);
1296                 } else {
1297                         /*
1298                          * Disable the Tx FIFO empty interrupt since there are
1299                          * no more transactions that need to be queued right
1300                          * now. This function is called from interrupt
1301                          * handlers to queue more transactions as transfer
1302                          * states change.
1303                          */
1304                         gintmsk = readl(hsotg->regs + GINTMSK);
1305                         gintmsk &= ~GINTSTS_NPTXFEMP;
1306                         writel(gintmsk, hsotg->regs + GINTMSK);
1307                 }
1308         }
1309 }
1310
1311 /**
1312  * dwc2_hcd_queue_transactions() - Processes the currently active host channels
1313  * and queues transactions for these channels to the DWC_otg controller. Called
1314  * from the HCD interrupt handler functions.
1315  *
1316  * @hsotg:   The HCD state structure
1317  * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
1318  *           or both)
1319  *
1320  * Must be called with interrupt disabled and spinlock held
1321  */
1322 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
1323                                  enum dwc2_transaction_type tr_type)
1324 {
1325 #ifdef DWC2_DEBUG_SOF
1326         dev_vdbg(hsotg->dev, "Queue Transactions\n");
1327 #endif
1328         /* Process host channels associated with periodic transfers */
1329         if ((tr_type == DWC2_TRANSACTION_PERIODIC ||
1330              tr_type == DWC2_TRANSACTION_ALL) &&
1331             !list_empty(&hsotg->periodic_sched_assigned))
1332                 dwc2_process_periodic_channels(hsotg);
1333
1334         /* Process host channels associated with non-periodic transfers */
1335         if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
1336             tr_type == DWC2_TRANSACTION_ALL) {
1337                 if (!list_empty(&hsotg->non_periodic_sched_active)) {
1338                         dwc2_process_non_periodic_channels(hsotg);
1339                 } else {
1340                         /*
1341                          * Ensure NP Tx FIFO empty interrupt is disabled when
1342                          * there are no non-periodic transfers to process
1343                          */
1344                         u32 gintmsk = readl(hsotg->regs + GINTMSK);
1345
1346                         gintmsk &= ~GINTSTS_NPTXFEMP;
1347                         writel(gintmsk, hsotg->regs + GINTMSK);
1348                 }
1349         }
1350 }
1351
1352 static void dwc2_conn_id_status_change(struct work_struct *work)
1353 {
1354         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
1355                                                 wf_otg);
1356         u32 count = 0;
1357         u32 gotgctl;
1358
1359         dev_dbg(hsotg->dev, "%s()\n", __func__);
1360
1361         gotgctl = readl(hsotg->regs + GOTGCTL);
1362         dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
1363         dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
1364                 !!(gotgctl & GOTGCTL_CONID_B));
1365
1366         /* B-Device connector (Device Mode) */
1367         if (gotgctl & GOTGCTL_CONID_B) {
1368                 /* Wait for switch to device mode */
1369                 dev_dbg(hsotg->dev, "connId B\n");
1370                 while (!dwc2_is_device_mode(hsotg)) {
1371                         dev_info(hsotg->dev,
1372                                  "Waiting for Peripheral Mode, Mode=%s\n",
1373                                  dwc2_is_host_mode(hsotg) ? "Host" :
1374                                  "Peripheral");
1375                         usleep_range(20000, 40000);
1376                         if (++count > 250)
1377                                 break;
1378                 }
1379                 if (count > 250)
1380                         dev_err(hsotg->dev,
1381                                 "Connection id status change timed out\n");
1382                 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
1383                 dwc2_core_init(hsotg, false, -1);
1384                 dwc2_enable_global_interrupts(hsotg);
1385                 s3c_hsotg_core_init_disconnected(hsotg, false);
1386                 s3c_hsotg_core_connect(hsotg);
1387         } else {
1388                 /* A-Device connector (Host Mode) */
1389                 dev_dbg(hsotg->dev, "connId A\n");
1390                 while (!dwc2_is_host_mode(hsotg)) {
1391                         dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
1392                                  dwc2_is_host_mode(hsotg) ?
1393                                  "Host" : "Peripheral");
1394                         usleep_range(20000, 40000);
1395                         if (++count > 250)
1396                                 break;
1397                 }
1398                 if (count > 250)
1399                         dev_err(hsotg->dev,
1400                                 "Connection id status change timed out\n");
1401                 hsotg->op_state = OTG_STATE_A_HOST;
1402
1403                 /* Initialize the Core for Host mode */
1404                 dwc2_core_init(hsotg, false, -1);
1405                 dwc2_enable_global_interrupts(hsotg);
1406                 dwc2_hcd_start(hsotg);
1407         }
1408 }
1409
1410 static void dwc2_wakeup_detected(unsigned long data)
1411 {
1412         struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
1413         u32 hprt0;
1414
1415         dev_dbg(hsotg->dev, "%s()\n", __func__);
1416
1417         /*
1418          * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
1419          * so that OPT tests pass with all PHYs.)
1420          */
1421         hprt0 = dwc2_read_hprt0(hsotg);
1422         dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
1423         hprt0 &= ~HPRT0_RES;
1424         writel(hprt0, hsotg->regs + HPRT0);
1425         dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
1426                 readl(hsotg->regs + HPRT0));
1427
1428         dwc2_hcd_rem_wakeup(hsotg);
1429
1430         /* Change to L0 state */
1431         hsotg->lx_state = DWC2_L0;
1432 }
1433
1434 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1435 {
1436         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
1437
1438         return hcd->self.b_hnp_enable;
1439 }
1440
1441 /* Must NOT be called with interrupt disabled or spinlock held */
1442 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1443 {
1444         unsigned long flags;
1445         u32 hprt0;
1446         u32 pcgctl;
1447         u32 gotgctl;
1448
1449         dev_dbg(hsotg->dev, "%s()\n", __func__);
1450
1451         spin_lock_irqsave(&hsotg->lock, flags);
1452
1453         if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
1454                 gotgctl = readl(hsotg->regs + GOTGCTL);
1455                 gotgctl |= GOTGCTL_HSTSETHNPEN;
1456                 writel(gotgctl, hsotg->regs + GOTGCTL);
1457                 hsotg->op_state = OTG_STATE_A_SUSPEND;
1458         }
1459
1460         hprt0 = dwc2_read_hprt0(hsotg);
1461         hprt0 |= HPRT0_SUSP;
1462         writel(hprt0, hsotg->regs + HPRT0);
1463
1464         /* Update lx_state */
1465         hsotg->lx_state = DWC2_L2;
1466
1467         /* Suspend the Phy Clock */
1468         pcgctl = readl(hsotg->regs + PCGCTL);
1469         pcgctl |= PCGCTL_STOPPCLK;
1470         writel(pcgctl, hsotg->regs + PCGCTL);
1471         udelay(10);
1472
1473         /* For HNP the bus must be suspended for at least 200ms */
1474         if (dwc2_host_is_b_hnp_enabled(hsotg)) {
1475                 pcgctl = readl(hsotg->regs + PCGCTL);
1476                 pcgctl &= ~PCGCTL_STOPPCLK;
1477                 writel(pcgctl, hsotg->regs + PCGCTL);
1478
1479                 spin_unlock_irqrestore(&hsotg->lock, flags);
1480
1481                 usleep_range(200000, 250000);
1482         } else {
1483                 spin_unlock_irqrestore(&hsotg->lock, flags);
1484         }
1485 }
1486
1487 /* Handles hub class-specific requests */
1488 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
1489                                 u16 wvalue, u16 windex, char *buf, u16 wlength)
1490 {
1491         struct usb_hub_descriptor *hub_desc;
1492         int retval = 0;
1493         u32 hprt0;
1494         u32 port_status;
1495         u32 speed;
1496         u32 pcgctl;
1497
1498         switch (typereq) {
1499         case ClearHubFeature:
1500                 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
1501
1502                 switch (wvalue) {
1503                 case C_HUB_LOCAL_POWER:
1504                 case C_HUB_OVER_CURRENT:
1505                         /* Nothing required here */
1506                         break;
1507
1508                 default:
1509                         retval = -EINVAL;
1510                         dev_err(hsotg->dev,
1511                                 "ClearHubFeature request %1xh unknown\n",
1512                                 wvalue);
1513                 }
1514                 break;
1515
1516         case ClearPortFeature:
1517                 if (wvalue != USB_PORT_FEAT_L1)
1518                         if (!windex || windex > 1)
1519                                 goto error;
1520                 switch (wvalue) {
1521                 case USB_PORT_FEAT_ENABLE:
1522                         dev_dbg(hsotg->dev,
1523                                 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
1524                         hprt0 = dwc2_read_hprt0(hsotg);
1525                         hprt0 |= HPRT0_ENA;
1526                         writel(hprt0, hsotg->regs + HPRT0);
1527                         break;
1528
1529                 case USB_PORT_FEAT_SUSPEND:
1530                         dev_dbg(hsotg->dev,
1531                                 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
1532                         writel(0, hsotg->regs + PCGCTL);
1533                         usleep_range(20000, 40000);
1534
1535                         hprt0 = dwc2_read_hprt0(hsotg);
1536                         hprt0 |= HPRT0_RES;
1537                         writel(hprt0, hsotg->regs + HPRT0);
1538                         hprt0 &= ~HPRT0_SUSP;
1539                         msleep(USB_RESUME_TIMEOUT);
1540
1541                         hprt0 &= ~HPRT0_RES;
1542                         writel(hprt0, hsotg->regs + HPRT0);
1543                         break;
1544
1545                 case USB_PORT_FEAT_POWER:
1546                         dev_dbg(hsotg->dev,
1547                                 "ClearPortFeature USB_PORT_FEAT_POWER\n");
1548                         hprt0 = dwc2_read_hprt0(hsotg);
1549                         hprt0 &= ~HPRT0_PWR;
1550                         writel(hprt0, hsotg->regs + HPRT0);
1551                         break;
1552
1553                 case USB_PORT_FEAT_INDICATOR:
1554                         dev_dbg(hsotg->dev,
1555                                 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
1556                         /* Port indicator not supported */
1557                         break;
1558
1559                 case USB_PORT_FEAT_C_CONNECTION:
1560                         /*
1561                          * Clears driver's internal Connect Status Change flag
1562                          */
1563                         dev_dbg(hsotg->dev,
1564                                 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
1565                         hsotg->flags.b.port_connect_status_change = 0;
1566                         break;
1567
1568                 case USB_PORT_FEAT_C_RESET:
1569                         /* Clears driver's internal Port Reset Change flag */
1570                         dev_dbg(hsotg->dev,
1571                                 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
1572                         hsotg->flags.b.port_reset_change = 0;
1573                         break;
1574
1575                 case USB_PORT_FEAT_C_ENABLE:
1576                         /*
1577                          * Clears the driver's internal Port Enable/Disable
1578                          * Change flag
1579                          */
1580                         dev_dbg(hsotg->dev,
1581                                 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
1582                         hsotg->flags.b.port_enable_change = 0;
1583                         break;
1584
1585                 case USB_PORT_FEAT_C_SUSPEND:
1586                         /*
1587                          * Clears the driver's internal Port Suspend Change
1588                          * flag, which is set when resume signaling on the host
1589                          * port is complete
1590                          */
1591                         dev_dbg(hsotg->dev,
1592                                 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
1593                         hsotg->flags.b.port_suspend_change = 0;
1594                         break;
1595
1596                 case USB_PORT_FEAT_C_PORT_L1:
1597                         dev_dbg(hsotg->dev,
1598                                 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
1599                         hsotg->flags.b.port_l1_change = 0;
1600                         break;
1601
1602                 case USB_PORT_FEAT_C_OVER_CURRENT:
1603                         dev_dbg(hsotg->dev,
1604                                 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
1605                         hsotg->flags.b.port_over_current_change = 0;
1606                         break;
1607
1608                 default:
1609                         retval = -EINVAL;
1610                         dev_err(hsotg->dev,
1611                                 "ClearPortFeature request %1xh unknown or unsupported\n",
1612                                 wvalue);
1613                 }
1614                 break;
1615
1616         case GetHubDescriptor:
1617                 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
1618                 hub_desc = (struct usb_hub_descriptor *)buf;
1619                 hub_desc->bDescLength = 9;
1620                 hub_desc->bDescriptorType = USB_DT_HUB;
1621                 hub_desc->bNbrPorts = 1;
1622                 hub_desc->wHubCharacteristics =
1623                         cpu_to_le16(HUB_CHAR_COMMON_LPSM |
1624                                     HUB_CHAR_INDV_PORT_OCPM);
1625                 hub_desc->bPwrOn2PwrGood = 1;
1626                 hub_desc->bHubContrCurrent = 0;
1627                 hub_desc->u.hs.DeviceRemovable[0] = 0;
1628                 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
1629                 break;
1630
1631         case GetHubStatus:
1632                 dev_dbg(hsotg->dev, "GetHubStatus\n");
1633                 memset(buf, 0, 4);
1634                 break;
1635
1636         case GetPortStatus:
1637                 dev_vdbg(hsotg->dev,
1638                          "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
1639                          hsotg->flags.d32);
1640                 if (!windex || windex > 1)
1641                         goto error;
1642
1643                 port_status = 0;
1644                 if (hsotg->flags.b.port_connect_status_change)
1645                         port_status |= USB_PORT_STAT_C_CONNECTION << 16;
1646                 if (hsotg->flags.b.port_enable_change)
1647                         port_status |= USB_PORT_STAT_C_ENABLE << 16;
1648                 if (hsotg->flags.b.port_suspend_change)
1649                         port_status |= USB_PORT_STAT_C_SUSPEND << 16;
1650                 if (hsotg->flags.b.port_l1_change)
1651                         port_status |= USB_PORT_STAT_C_L1 << 16;
1652                 if (hsotg->flags.b.port_reset_change)
1653                         port_status |= USB_PORT_STAT_C_RESET << 16;
1654                 if (hsotg->flags.b.port_over_current_change) {
1655                         dev_warn(hsotg->dev, "Overcurrent change detected\n");
1656                         port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1657                 }
1658
1659                 if (!hsotg->flags.b.port_connect_status) {
1660                         /*
1661                          * The port is disconnected, which means the core is
1662                          * either in device mode or it soon will be. Just
1663                          * return 0's for the remainder of the port status
1664                          * since the port register can't be read if the core
1665                          * is in device mode.
1666                          */
1667                         *(__le32 *)buf = cpu_to_le32(port_status);
1668                         break;
1669                 }
1670
1671                 hprt0 = readl(hsotg->regs + HPRT0);
1672                 dev_vdbg(hsotg->dev, "  HPRT0: 0x%08x\n", hprt0);
1673
1674                 if (hprt0 & HPRT0_CONNSTS)
1675                         port_status |= USB_PORT_STAT_CONNECTION;
1676                 if (hprt0 & HPRT0_ENA)
1677                         port_status |= USB_PORT_STAT_ENABLE;
1678                 if (hprt0 & HPRT0_SUSP)
1679                         port_status |= USB_PORT_STAT_SUSPEND;
1680                 if (hprt0 & HPRT0_OVRCURRACT)
1681                         port_status |= USB_PORT_STAT_OVERCURRENT;
1682                 if (hprt0 & HPRT0_RST)
1683                         port_status |= USB_PORT_STAT_RESET;
1684                 if (hprt0 & HPRT0_PWR)
1685                         port_status |= USB_PORT_STAT_POWER;
1686
1687                 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1688                 if (speed == HPRT0_SPD_HIGH_SPEED)
1689                         port_status |= USB_PORT_STAT_HIGH_SPEED;
1690                 else if (speed == HPRT0_SPD_LOW_SPEED)
1691                         port_status |= USB_PORT_STAT_LOW_SPEED;
1692
1693                 if (hprt0 & HPRT0_TSTCTL_MASK)
1694                         port_status |= USB_PORT_STAT_TEST;
1695                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
1696
1697                 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
1698                 *(__le32 *)buf = cpu_to_le32(port_status);
1699                 break;
1700
1701         case SetHubFeature:
1702                 dev_dbg(hsotg->dev, "SetHubFeature\n");
1703                 /* No HUB features supported */
1704                 break;
1705
1706         case SetPortFeature:
1707                 dev_dbg(hsotg->dev, "SetPortFeature\n");
1708                 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
1709                         goto error;
1710
1711                 if (!hsotg->flags.b.port_connect_status) {
1712                         /*
1713                          * The port is disconnected, which means the core is
1714                          * either in device mode or it soon will be. Just
1715                          * return without doing anything since the port
1716                          * register can't be written if the core is in device
1717                          * mode.
1718                          */
1719                         break;
1720                 }
1721
1722                 switch (wvalue) {
1723                 case USB_PORT_FEAT_SUSPEND:
1724                         dev_dbg(hsotg->dev,
1725                                 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
1726                         if (windex != hsotg->otg_port)
1727                                 goto error;
1728                         dwc2_port_suspend(hsotg, windex);
1729                         break;
1730
1731                 case USB_PORT_FEAT_POWER:
1732                         dev_dbg(hsotg->dev,
1733                                 "SetPortFeature - USB_PORT_FEAT_POWER\n");
1734                         hprt0 = dwc2_read_hprt0(hsotg);
1735                         hprt0 |= HPRT0_PWR;
1736                         writel(hprt0, hsotg->regs + HPRT0);
1737                         break;
1738
1739                 case USB_PORT_FEAT_RESET:
1740                         hprt0 = dwc2_read_hprt0(hsotg);
1741                         dev_dbg(hsotg->dev,
1742                                 "SetPortFeature - USB_PORT_FEAT_RESET\n");
1743                         pcgctl = readl(hsotg->regs + PCGCTL);
1744                         pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
1745                         writel(pcgctl, hsotg->regs + PCGCTL);
1746                         /* ??? Original driver does this */
1747                         writel(0, hsotg->regs + PCGCTL);
1748
1749                         hprt0 = dwc2_read_hprt0(hsotg);
1750                         /* Clear suspend bit if resetting from suspend state */
1751                         hprt0 &= ~HPRT0_SUSP;
1752
1753                         /*
1754                          * When B-Host the Port reset bit is set in the Start
1755                          * HCD Callback function, so that the reset is started
1756                          * within 1ms of the HNP success interrupt
1757                          */
1758                         if (!dwc2_hcd_is_b_host(hsotg)) {
1759                                 hprt0 |= HPRT0_PWR | HPRT0_RST;
1760                                 dev_dbg(hsotg->dev,
1761                                         "In host mode, hprt0=%08x\n", hprt0);
1762                                 writel(hprt0, hsotg->regs + HPRT0);
1763                         }
1764
1765                         /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
1766                         usleep_range(50000, 70000);
1767                         hprt0 &= ~HPRT0_RST;
1768                         writel(hprt0, hsotg->regs + HPRT0);
1769                         hsotg->lx_state = DWC2_L0; /* Now back to On state */
1770                         break;
1771
1772                 case USB_PORT_FEAT_INDICATOR:
1773                         dev_dbg(hsotg->dev,
1774                                 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
1775                         /* Not supported */
1776                         break;
1777
1778                 case USB_PORT_FEAT_TEST:
1779                         hprt0 = dwc2_read_hprt0(hsotg);
1780                         dev_dbg(hsotg->dev,
1781                                 "SetPortFeature - USB_PORT_FEAT_TEST\n");
1782                         hprt0 &= ~HPRT0_TSTCTL_MASK;
1783                         hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
1784                         writel(hprt0, hsotg->regs + HPRT0);
1785                         break;
1786
1787                 default:
1788                         retval = -EINVAL;
1789                         dev_err(hsotg->dev,
1790                                 "SetPortFeature %1xh unknown or unsupported\n",
1791                                 wvalue);
1792                         break;
1793                 }
1794                 break;
1795
1796         default:
1797 error:
1798                 retval = -EINVAL;
1799                 dev_dbg(hsotg->dev,
1800                         "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
1801                         typereq, windex, wvalue);
1802                 break;
1803         }
1804
1805         return retval;
1806 }
1807
1808 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
1809 {
1810         int retval;
1811
1812         if (port != 1)
1813                 return -EINVAL;
1814
1815         retval = (hsotg->flags.b.port_connect_status_change ||
1816                   hsotg->flags.b.port_reset_change ||
1817                   hsotg->flags.b.port_enable_change ||
1818                   hsotg->flags.b.port_suspend_change ||
1819                   hsotg->flags.b.port_over_current_change);
1820
1821         if (retval) {
1822                 dev_dbg(hsotg->dev,
1823                         "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
1824                 dev_dbg(hsotg->dev, "  port_connect_status_change: %d\n",
1825                         hsotg->flags.b.port_connect_status_change);
1826                 dev_dbg(hsotg->dev, "  port_reset_change: %d\n",
1827                         hsotg->flags.b.port_reset_change);
1828                 dev_dbg(hsotg->dev, "  port_enable_change: %d\n",
1829                         hsotg->flags.b.port_enable_change);
1830                 dev_dbg(hsotg->dev, "  port_suspend_change: %d\n",
1831                         hsotg->flags.b.port_suspend_change);
1832                 dev_dbg(hsotg->dev, "  port_over_current_change: %d\n",
1833                         hsotg->flags.b.port_over_current_change);
1834         }
1835
1836         return retval;
1837 }
1838
1839 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1840 {
1841         u32 hfnum = readl(hsotg->regs + HFNUM);
1842
1843 #ifdef DWC2_DEBUG_SOF
1844         dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
1845                  (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
1846 #endif
1847         return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
1848 }
1849
1850 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
1851 {
1852         return hsotg->op_state == OTG_STATE_B_HOST;
1853 }
1854
1855 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
1856                                                int iso_desc_count,
1857                                                gfp_t mem_flags)
1858 {
1859         struct dwc2_hcd_urb *urb;
1860         u32 size = sizeof(*urb) + iso_desc_count *
1861                    sizeof(struct dwc2_hcd_iso_packet_desc);
1862
1863         urb = kzalloc(size, mem_flags);
1864         if (urb)
1865                 urb->packet_count = iso_desc_count;
1866         return urb;
1867 }
1868
1869 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
1870                                       struct dwc2_hcd_urb *urb, u8 dev_addr,
1871                                       u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
1872 {
1873         if (dbg_perio() ||
1874             ep_type == USB_ENDPOINT_XFER_BULK ||
1875             ep_type == USB_ENDPOINT_XFER_CONTROL)
1876                 dev_vdbg(hsotg->dev,
1877                          "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
1878                          dev_addr, ep_num, ep_dir, ep_type, mps);
1879         urb->pipe_info.dev_addr = dev_addr;
1880         urb->pipe_info.ep_num = ep_num;
1881         urb->pipe_info.pipe_type = ep_type;
1882         urb->pipe_info.pipe_dir = ep_dir;
1883         urb->pipe_info.mps = mps;
1884 }
1885
1886 /*
1887  * NOTE: This function will be removed once the peripheral controller code
1888  * is integrated and the driver is stable
1889  */
1890 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
1891 {
1892 #ifdef DEBUG
1893         struct dwc2_host_chan *chan;
1894         struct dwc2_hcd_urb *urb;
1895         struct dwc2_qtd *qtd;
1896         int num_channels;
1897         u32 np_tx_status;
1898         u32 p_tx_status;
1899         int i;
1900
1901         num_channels = hsotg->core_params->host_channels;
1902         dev_dbg(hsotg->dev, "\n");
1903         dev_dbg(hsotg->dev,
1904                 "************************************************************\n");
1905         dev_dbg(hsotg->dev, "HCD State:\n");
1906         dev_dbg(hsotg->dev, "  Num channels: %d\n", num_channels);
1907
1908         for (i = 0; i < num_channels; i++) {
1909                 chan = hsotg->hc_ptr_array[i];
1910                 dev_dbg(hsotg->dev, "  Channel %d:\n", i);
1911                 dev_dbg(hsotg->dev,
1912                         "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1913                         chan->dev_addr, chan->ep_num, chan->ep_is_in);
1914                 dev_dbg(hsotg->dev, "    speed: %d\n", chan->speed);
1915                 dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
1916                 dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
1917                 dev_dbg(hsotg->dev, "    data_pid_start: %d\n",
1918                         chan->data_pid_start);
1919                 dev_dbg(hsotg->dev, "    multi_count: %d\n", chan->multi_count);
1920                 dev_dbg(hsotg->dev, "    xfer_started: %d\n",
1921                         chan->xfer_started);
1922                 dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
1923                 dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
1924                         (unsigned long)chan->xfer_dma);
1925                 dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
1926                 dev_dbg(hsotg->dev, "    xfer_count: %d\n", chan->xfer_count);
1927                 dev_dbg(hsotg->dev, "    halt_on_queue: %d\n",
1928                         chan->halt_on_queue);
1929                 dev_dbg(hsotg->dev, "    halt_pending: %d\n",
1930                         chan->halt_pending);
1931                 dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
1932                 dev_dbg(hsotg->dev, "    do_split: %d\n", chan->do_split);
1933                 dev_dbg(hsotg->dev, "    complete_split: %d\n",
1934                         chan->complete_split);
1935                 dev_dbg(hsotg->dev, "    hub_addr: %d\n", chan->hub_addr);
1936                 dev_dbg(hsotg->dev, "    hub_port: %d\n", chan->hub_port);
1937                 dev_dbg(hsotg->dev, "    xact_pos: %d\n", chan->xact_pos);
1938                 dev_dbg(hsotg->dev, "    requests: %d\n", chan->requests);
1939                 dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
1940
1941                 if (chan->xfer_started) {
1942                         u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
1943
1944                         hfnum = readl(hsotg->regs + HFNUM);
1945                         hcchar = readl(hsotg->regs + HCCHAR(i));
1946                         hctsiz = readl(hsotg->regs + HCTSIZ(i));
1947                         hcint = readl(hsotg->regs + HCINT(i));
1948                         hcintmsk = readl(hsotg->regs + HCINTMSK(i));
1949                         dev_dbg(hsotg->dev, "    hfnum: 0x%08x\n", hfnum);
1950                         dev_dbg(hsotg->dev, "    hcchar: 0x%08x\n", hcchar);
1951                         dev_dbg(hsotg->dev, "    hctsiz: 0x%08x\n", hctsiz);
1952                         dev_dbg(hsotg->dev, "    hcint: 0x%08x\n", hcint);
1953                         dev_dbg(hsotg->dev, "    hcintmsk: 0x%08x\n", hcintmsk);
1954                 }
1955
1956                 if (!(chan->xfer_started && chan->qh))
1957                         continue;
1958
1959                 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
1960                         if (!qtd->in_process)
1961                                 break;
1962                         urb = qtd->urb;
1963                         dev_dbg(hsotg->dev, "    URB Info:\n");
1964                         dev_dbg(hsotg->dev, "      qtd: %p, urb: %p\n",
1965                                 qtd, urb);
1966                         if (urb) {
1967                                 dev_dbg(hsotg->dev,
1968                                         "      Dev: %d, EP: %d %s\n",
1969                                         dwc2_hcd_get_dev_addr(&urb->pipe_info),
1970                                         dwc2_hcd_get_ep_num(&urb->pipe_info),
1971                                         dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
1972                                         "IN" : "OUT");
1973                                 dev_dbg(hsotg->dev,
1974                                         "      Max packet size: %d\n",
1975                                         dwc2_hcd_get_mps(&urb->pipe_info));
1976                                 dev_dbg(hsotg->dev,
1977                                         "      transfer_buffer: %p\n",
1978                                         urb->buf);
1979                                 dev_dbg(hsotg->dev,
1980                                         "      transfer_dma: %08lx\n",
1981                                         (unsigned long)urb->dma);
1982                                 dev_dbg(hsotg->dev,
1983                                         "      transfer_buffer_length: %d\n",
1984                                         urb->length);
1985                                 dev_dbg(hsotg->dev, "      actual_length: %d\n",
1986                                         urb->actual_length);
1987                         }
1988                 }
1989         }
1990
1991         dev_dbg(hsotg->dev, "  non_periodic_channels: %d\n",
1992                 hsotg->non_periodic_channels);
1993         dev_dbg(hsotg->dev, "  periodic_channels: %d\n",
1994                 hsotg->periodic_channels);
1995         dev_dbg(hsotg->dev, "  periodic_usecs: %d\n", hsotg->periodic_usecs);
1996         np_tx_status = readl(hsotg->regs + GNPTXSTS);
1997         dev_dbg(hsotg->dev, "  NP Tx Req Queue Space Avail: %d\n",
1998                 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
1999         dev_dbg(hsotg->dev, "  NP Tx FIFO Space Avail: %d\n",
2000                 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
2001         p_tx_status = readl(hsotg->regs + HPTXSTS);
2002         dev_dbg(hsotg->dev, "  P Tx Req Queue Space Avail: %d\n",
2003                 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
2004         dev_dbg(hsotg->dev, "  P Tx FIFO Space Avail: %d\n",
2005                 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
2006         dwc2_hcd_dump_frrem(hsotg);
2007         dwc2_dump_global_registers(hsotg);
2008         dwc2_dump_host_registers(hsotg);
2009         dev_dbg(hsotg->dev,
2010                 "************************************************************\n");
2011         dev_dbg(hsotg->dev, "\n");
2012 #endif
2013 }
2014
2015 /*
2016  * NOTE: This function will be removed once the peripheral controller code
2017  * is integrated and the driver is stable
2018  */
2019 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
2020 {
2021 #ifdef DWC2_DUMP_FRREM
2022         dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
2023         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2024                 hsotg->frrem_samples, hsotg->frrem_accum,
2025                 hsotg->frrem_samples > 0 ?
2026                 hsotg->frrem_accum / hsotg->frrem_samples : 0);
2027         dev_dbg(hsotg->dev, "\n");
2028         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
2029         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2030                 hsotg->hfnum_7_samples,
2031                 hsotg->hfnum_7_frrem_accum,
2032                 hsotg->hfnum_7_samples > 0 ?
2033                 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
2034         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
2035         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2036                 hsotg->hfnum_0_samples,
2037                 hsotg->hfnum_0_frrem_accum,
2038                 hsotg->hfnum_0_samples > 0 ?
2039                 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
2040         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
2041         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2042                 hsotg->hfnum_other_samples,
2043                 hsotg->hfnum_other_frrem_accum,
2044                 hsotg->hfnum_other_samples > 0 ?
2045                 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
2046                 0);
2047         dev_dbg(hsotg->dev, "\n");
2048         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
2049         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2050                 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
2051                 hsotg->hfnum_7_samples_a > 0 ?
2052                 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
2053         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
2054         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2055                 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
2056                 hsotg->hfnum_0_samples_a > 0 ?
2057                 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
2058         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
2059         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2060                 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
2061                 hsotg->hfnum_other_samples_a > 0 ?
2062                 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
2063                 : 0);
2064         dev_dbg(hsotg->dev, "\n");
2065         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
2066         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2067                 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
2068                 hsotg->hfnum_7_samples_b > 0 ?
2069                 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
2070         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
2071         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2072                 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
2073                 (hsotg->hfnum_0_samples_b > 0) ?
2074                 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
2075         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
2076         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2077                 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
2078                 (hsotg->hfnum_other_samples_b > 0) ?
2079                 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
2080                 : 0);
2081 #endif
2082 }
2083
2084 struct wrapper_priv_data {
2085         struct dwc2_hsotg *hsotg;
2086 };
2087
2088 /* Gets the dwc2_hsotg from a usb_hcd */
2089 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
2090 {
2091         struct wrapper_priv_data *p;
2092
2093         p = (struct wrapper_priv_data *) &hcd->hcd_priv;
2094         return p->hsotg;
2095 }
2096
2097 static int _dwc2_hcd_start(struct usb_hcd *hcd);
2098
2099 void dwc2_host_start(struct dwc2_hsotg *hsotg)
2100 {
2101         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2102
2103         hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
2104         _dwc2_hcd_start(hcd);
2105 }
2106
2107 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
2108 {
2109         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2110
2111         hcd->self.is_b_host = 0;
2112 }
2113
2114 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
2115                         int *hub_port)
2116 {
2117         struct urb *urb = context;
2118
2119         if (urb->dev->tt)
2120                 *hub_addr = urb->dev->tt->hub->devnum;
2121         else
2122                 *hub_addr = 0;
2123         *hub_port = urb->dev->ttport;
2124 }
2125
2126 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
2127 {
2128         struct urb *urb = context;
2129
2130         return urb->dev->speed;
2131 }
2132
2133 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2134                                         struct urb *urb)
2135 {
2136         struct usb_bus *bus = hcd_to_bus(hcd);
2137
2138         if (urb->interval)
2139                 bus->bandwidth_allocated += bw / urb->interval;
2140         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2141                 bus->bandwidth_isoc_reqs++;
2142         else
2143                 bus->bandwidth_int_reqs++;
2144 }
2145
2146 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2147                                     struct urb *urb)
2148 {
2149         struct usb_bus *bus = hcd_to_bus(hcd);
2150
2151         if (urb->interval)
2152                 bus->bandwidth_allocated -= bw / urb->interval;
2153         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2154                 bus->bandwidth_isoc_reqs--;
2155         else
2156                 bus->bandwidth_int_reqs--;
2157 }
2158
2159 /*
2160  * Sets the final status of an URB and returns it to the upper layer. Any
2161  * required cleanup of the URB is performed.
2162  *
2163  * Must be called with interrupt disabled and spinlock held
2164  */
2165 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
2166                         int status)
2167 {
2168         struct urb *urb;
2169         int i;
2170
2171         if (!qtd) {
2172                 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
2173                 return;
2174         }
2175
2176         if (!qtd->urb) {
2177                 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
2178                 return;
2179         }
2180
2181         urb = qtd->urb->priv;
2182         if (!urb) {
2183                 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
2184                 return;
2185         }
2186
2187         urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
2188
2189         if (dbg_urb(urb))
2190                 dev_vdbg(hsotg->dev,
2191                          "%s: urb %p device %d ep %d-%s status %d actual %d\n",
2192                          __func__, urb, usb_pipedevice(urb->pipe),
2193                          usb_pipeendpoint(urb->pipe),
2194                          usb_pipein(urb->pipe) ? "IN" : "OUT", status,
2195                          urb->actual_length);
2196
2197         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
2198                 for (i = 0; i < urb->number_of_packets; i++)
2199                         dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
2200                                  i, urb->iso_frame_desc[i].status);
2201         }
2202
2203         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2204                 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
2205                 for (i = 0; i < urb->number_of_packets; ++i) {
2206                         urb->iso_frame_desc[i].actual_length =
2207                                 dwc2_hcd_urb_get_iso_desc_actual_length(
2208                                                 qtd->urb, i);
2209                         urb->iso_frame_desc[i].status =
2210                                 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
2211                 }
2212         }
2213
2214         urb->status = status;
2215         if (!status) {
2216                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
2217                     urb->actual_length < urb->transfer_buffer_length)
2218                         urb->status = -EREMOTEIO;
2219         }
2220
2221         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2222             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2223                 struct usb_host_endpoint *ep = urb->ep;
2224
2225                 if (ep)
2226                         dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
2227                                         dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2228                                         urb);
2229         }
2230
2231         usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
2232         urb->hcpriv = NULL;
2233         kfree(qtd->urb);
2234         qtd->urb = NULL;
2235
2236         spin_unlock(&hsotg->lock);
2237         usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
2238         spin_lock(&hsotg->lock);
2239 }
2240
2241 /*
2242  * Work queue function for starting the HCD when A-Cable is connected
2243  */
2244 static void dwc2_hcd_start_func(struct work_struct *work)
2245 {
2246         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2247                                                 start_work.work);
2248
2249         dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
2250         dwc2_host_start(hsotg);
2251 }
2252
2253 /*
2254  * Reset work queue function
2255  */
2256 static void dwc2_hcd_reset_func(struct work_struct *work)
2257 {
2258         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2259                                                 reset_work.work);
2260         u32 hprt0;
2261
2262         dev_dbg(hsotg->dev, "USB RESET function called\n");
2263         hprt0 = dwc2_read_hprt0(hsotg);
2264         hprt0 &= ~HPRT0_RST;
2265         writel(hprt0, hsotg->regs + HPRT0);
2266         hsotg->flags.b.port_reset_change = 1;
2267 }
2268
2269 /*
2270  * =========================================================================
2271  *  Linux HC Driver Functions
2272  * =========================================================================
2273  */
2274
2275 /*
2276  * Initializes the DWC_otg controller and its root hub and prepares it for host
2277  * mode operation. Activates the root port. Returns 0 on success and a negative
2278  * error code on failure.
2279  */
2280 static int _dwc2_hcd_start(struct usb_hcd *hcd)
2281 {
2282         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2283         struct usb_bus *bus = hcd_to_bus(hcd);
2284         unsigned long flags;
2285
2286         dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
2287
2288         spin_lock_irqsave(&hsotg->lock, flags);
2289
2290         hcd->state = HC_STATE_RUNNING;
2291
2292         if (dwc2_is_device_mode(hsotg)) {
2293                 spin_unlock_irqrestore(&hsotg->lock, flags);
2294                 return 0;       /* why 0 ?? */
2295         }
2296
2297         dwc2_hcd_reinit(hsotg);
2298
2299         /* Initialize and connect root hub if one is not already attached */
2300         if (bus->root_hub) {
2301                 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
2302                 /* Inform the HUB driver to resume */
2303                 usb_hcd_resume_root_hub(hcd);
2304         }
2305
2306         spin_unlock_irqrestore(&hsotg->lock, flags);
2307         return 0;
2308 }
2309
2310 /*
2311  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
2312  * stopped.
2313  */
2314 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
2315 {
2316         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2317         unsigned long flags;
2318
2319         spin_lock_irqsave(&hsotg->lock, flags);
2320         dwc2_hcd_stop(hsotg);
2321         spin_unlock_irqrestore(&hsotg->lock, flags);
2322
2323         usleep_range(1000, 3000);
2324 }
2325
2326 static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
2327 {
2328         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2329
2330         hsotg->lx_state = DWC2_L2;
2331         return 0;
2332 }
2333
2334 static int _dwc2_hcd_resume(struct usb_hcd *hcd)
2335 {
2336         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2337
2338         hsotg->lx_state = DWC2_L0;
2339         return 0;
2340 }
2341
2342 /* Returns the current frame number */
2343 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
2344 {
2345         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2346
2347         return dwc2_hcd_get_frame_number(hsotg);
2348 }
2349
2350 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
2351                                char *fn_name)
2352 {
2353 #ifdef VERBOSE_DEBUG
2354         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2355         char *pipetype;
2356         char *speed;
2357
2358         dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
2359         dev_vdbg(hsotg->dev, "  Device address: %d\n",
2360                  usb_pipedevice(urb->pipe));
2361         dev_vdbg(hsotg->dev, "  Endpoint: %d, %s\n",
2362                  usb_pipeendpoint(urb->pipe),
2363                  usb_pipein(urb->pipe) ? "IN" : "OUT");
2364
2365         switch (usb_pipetype(urb->pipe)) {
2366         case PIPE_CONTROL:
2367                 pipetype = "CONTROL";
2368                 break;
2369         case PIPE_BULK:
2370                 pipetype = "BULK";
2371                 break;
2372         case PIPE_INTERRUPT:
2373                 pipetype = "INTERRUPT";
2374                 break;
2375         case PIPE_ISOCHRONOUS:
2376                 pipetype = "ISOCHRONOUS";
2377                 break;
2378         default:
2379                 pipetype = "UNKNOWN";
2380                 break;
2381         }
2382
2383         dev_vdbg(hsotg->dev, "  Endpoint type: %s %s (%s)\n", pipetype,
2384                  usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
2385                  "IN" : "OUT");
2386
2387         switch (urb->dev->speed) {
2388         case USB_SPEED_HIGH:
2389                 speed = "HIGH";
2390                 break;
2391         case USB_SPEED_FULL:
2392                 speed = "FULL";
2393                 break;
2394         case USB_SPEED_LOW:
2395                 speed = "LOW";
2396                 break;
2397         default:
2398                 speed = "UNKNOWN";
2399                 break;
2400         }
2401
2402         dev_vdbg(hsotg->dev, "  Speed: %s\n", speed);
2403         dev_vdbg(hsotg->dev, "  Max packet size: %d\n",
2404                  usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
2405         dev_vdbg(hsotg->dev, "  Data buffer length: %d\n",
2406                  urb->transfer_buffer_length);
2407         dev_vdbg(hsotg->dev, "  Transfer buffer: %p, Transfer DMA: %08lx\n",
2408                  urb->transfer_buffer, (unsigned long)urb->transfer_dma);
2409         dev_vdbg(hsotg->dev, "  Setup buffer: %p, Setup DMA: %08lx\n",
2410                  urb->setup_packet, (unsigned long)urb->setup_dma);
2411         dev_vdbg(hsotg->dev, "  Interval: %d\n", urb->interval);
2412
2413         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2414                 int i;
2415
2416                 for (i = 0; i < urb->number_of_packets; i++) {
2417                         dev_vdbg(hsotg->dev, "  ISO Desc %d:\n", i);
2418                         dev_vdbg(hsotg->dev, "    offset: %d, length %d\n",
2419                                  urb->iso_frame_desc[i].offset,
2420                                  urb->iso_frame_desc[i].length);
2421                 }
2422         }
2423 #endif
2424 }
2425
2426 /*
2427  * Starts processing a USB transfer request specified by a USB Request Block
2428  * (URB). mem_flags indicates the type of memory allocation to use while
2429  * processing this URB.
2430  */
2431 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
2432                                  gfp_t mem_flags)
2433 {
2434         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2435         struct usb_host_endpoint *ep = urb->ep;
2436         struct dwc2_hcd_urb *dwc2_urb;
2437         int i;
2438         int retval;
2439         int alloc_bandwidth = 0;
2440         u8 ep_type = 0;
2441         u32 tflags = 0;
2442         void *buf;
2443         unsigned long flags;
2444         struct dwc2_qh *qh;
2445         bool qh_allocated = false;
2446         struct dwc2_qtd *qtd;
2447
2448         if (dbg_urb(urb)) {
2449                 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
2450                 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
2451         }
2452
2453         if (ep == NULL)
2454                 return -EINVAL;
2455
2456         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2457             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2458                 spin_lock_irqsave(&hsotg->lock, flags);
2459                 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
2460                         alloc_bandwidth = 1;
2461                 spin_unlock_irqrestore(&hsotg->lock, flags);
2462         }
2463
2464         switch (usb_pipetype(urb->pipe)) {
2465         case PIPE_CONTROL:
2466                 ep_type = USB_ENDPOINT_XFER_CONTROL;
2467                 break;
2468         case PIPE_ISOCHRONOUS:
2469                 ep_type = USB_ENDPOINT_XFER_ISOC;
2470                 break;
2471         case PIPE_BULK:
2472                 ep_type = USB_ENDPOINT_XFER_BULK;
2473                 break;
2474         case PIPE_INTERRUPT:
2475                 ep_type = USB_ENDPOINT_XFER_INT;
2476                 break;
2477         default:
2478                 dev_warn(hsotg->dev, "Wrong ep type\n");
2479         }
2480
2481         dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
2482                                       mem_flags);
2483         if (!dwc2_urb)
2484                 return -ENOMEM;
2485
2486         dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
2487                                   usb_pipeendpoint(urb->pipe), ep_type,
2488                                   usb_pipein(urb->pipe),
2489                                   usb_maxpacket(urb->dev, urb->pipe,
2490                                                 !(usb_pipein(urb->pipe))));
2491
2492         buf = urb->transfer_buffer;
2493
2494         if (hcd->self.uses_dma) {
2495                 if (!buf && (urb->transfer_dma & 3)) {
2496                         dev_err(hsotg->dev,
2497                                 "%s: unaligned transfer with no transfer_buffer",
2498                                 __func__);
2499                         retval = -EINVAL;
2500                         goto fail0;
2501                 }
2502         }
2503
2504         if (!(urb->transfer_flags & URB_NO_INTERRUPT))
2505                 tflags |= URB_GIVEBACK_ASAP;
2506         if (urb->transfer_flags & URB_ZERO_PACKET)
2507                 tflags |= URB_SEND_ZERO_PACKET;
2508
2509         dwc2_urb->priv = urb;
2510         dwc2_urb->buf = buf;
2511         dwc2_urb->dma = urb->transfer_dma;
2512         dwc2_urb->length = urb->transfer_buffer_length;
2513         dwc2_urb->setup_packet = urb->setup_packet;
2514         dwc2_urb->setup_dma = urb->setup_dma;
2515         dwc2_urb->flags = tflags;
2516         dwc2_urb->interval = urb->interval;
2517         dwc2_urb->status = -EINPROGRESS;
2518
2519         for (i = 0; i < urb->number_of_packets; ++i)
2520                 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
2521                                                  urb->iso_frame_desc[i].offset,
2522                                                  urb->iso_frame_desc[i].length);
2523
2524         urb->hcpriv = dwc2_urb;
2525         qh = (struct dwc2_qh *) ep->hcpriv;
2526         /* Create QH for the endpoint if it doesn't exist */
2527         if (!qh) {
2528                 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
2529                 if (!qh) {
2530                         retval = -ENOMEM;
2531                         goto fail0;
2532                 }
2533                 ep->hcpriv = qh;
2534                 qh_allocated = true;
2535         }
2536
2537         qtd = kzalloc(sizeof(*qtd), mem_flags);
2538         if (!qtd) {
2539                 retval = -ENOMEM;
2540                 goto fail1;
2541         }
2542
2543         spin_lock_irqsave(&hsotg->lock, flags);
2544         retval = usb_hcd_link_urb_to_ep(hcd, urb);
2545         if (retval)
2546                 goto fail2;
2547
2548         retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
2549         if (retval)
2550                 goto fail3;
2551
2552         if (alloc_bandwidth) {
2553                 dwc2_allocate_bus_bandwidth(hcd,
2554                                 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2555                                 urb);
2556         }
2557
2558         spin_unlock_irqrestore(&hsotg->lock, flags);
2559
2560         return 0;
2561
2562 fail3:
2563         dwc2_urb->priv = NULL;
2564         usb_hcd_unlink_urb_from_ep(hcd, urb);
2565 fail2:
2566         spin_unlock_irqrestore(&hsotg->lock, flags);
2567         urb->hcpriv = NULL;
2568         kfree(qtd);
2569 fail1:
2570         if (qh_allocated) {
2571                 struct dwc2_qtd *qtd2, *qtd2_tmp;
2572
2573                 ep->hcpriv = NULL;
2574                 dwc2_hcd_qh_unlink(hsotg, qh);
2575                 /* Free each QTD in the QH's QTD list */
2576                 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
2577                                                          qtd_list_entry)
2578                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
2579                 dwc2_hcd_qh_free(hsotg, qh);
2580         }
2581 fail0:
2582         kfree(dwc2_urb);
2583
2584         return retval;
2585 }
2586
2587 /*
2588  * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
2589  */
2590 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
2591                                  int status)
2592 {
2593         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2594         int rc;
2595         unsigned long flags;
2596
2597         dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
2598         dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
2599
2600         spin_lock_irqsave(&hsotg->lock, flags);
2601
2602         rc = usb_hcd_check_unlink_urb(hcd, urb, status);
2603         if (rc)
2604                 goto out;
2605
2606         if (!urb->hcpriv) {
2607                 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
2608                 goto out;
2609         }
2610
2611         rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
2612
2613         usb_hcd_unlink_urb_from_ep(hcd, urb);
2614
2615         kfree(urb->hcpriv);
2616         urb->hcpriv = NULL;
2617
2618         /* Higher layer software sets URB status */
2619         spin_unlock(&hsotg->lock);
2620         usb_hcd_giveback_urb(hcd, urb, status);
2621         spin_lock(&hsotg->lock);
2622
2623         dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
2624         dev_dbg(hsotg->dev, "  urb->status = %d\n", urb->status);
2625 out:
2626         spin_unlock_irqrestore(&hsotg->lock, flags);
2627
2628         return rc;
2629 }
2630
2631 /*
2632  * Frees resources in the DWC_otg controller related to a given endpoint. Also
2633  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
2634  * must already be dequeued.
2635  */
2636 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
2637                                        struct usb_host_endpoint *ep)
2638 {
2639         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2640
2641         dev_dbg(hsotg->dev,
2642                 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
2643                 ep->desc.bEndpointAddress, ep->hcpriv);
2644         dwc2_hcd_endpoint_disable(hsotg, ep, 250);
2645 }
2646
2647 /*
2648  * Resets endpoint specific parameter values, in current version used to reset
2649  * the data toggle (as a WA). This function can be called from usb_clear_halt
2650  * routine.
2651  */
2652 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
2653                                      struct usb_host_endpoint *ep)
2654 {
2655         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2656         unsigned long flags;
2657
2658         dev_dbg(hsotg->dev,
2659                 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
2660                 ep->desc.bEndpointAddress);
2661
2662         spin_lock_irqsave(&hsotg->lock, flags);
2663         dwc2_hcd_endpoint_reset(hsotg, ep);
2664         spin_unlock_irqrestore(&hsotg->lock, flags);
2665 }
2666
2667 /*
2668  * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
2669  * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
2670  * interrupt.
2671  *
2672  * This function is called by the USB core when an interrupt occurs
2673  */
2674 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
2675 {
2676         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2677
2678         return dwc2_handle_hcd_intr(hsotg);
2679 }
2680
2681 /*
2682  * Creates Status Change bitmap for the root hub and root port. The bitmap is
2683  * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
2684  * is the status change indicator for the single root port. Returns 1 if either
2685  * change indicator is 1, otherwise returns 0.
2686  */
2687 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
2688 {
2689         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2690
2691         buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
2692         return buf[0] != 0;
2693 }
2694
2695 /* Handles hub class-specific requests */
2696 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
2697                                  u16 windex, char *buf, u16 wlength)
2698 {
2699         int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
2700                                           wvalue, windex, buf, wlength);
2701         return retval;
2702 }
2703
2704 /* Handles hub TT buffer clear completions */
2705 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
2706                                                struct usb_host_endpoint *ep)
2707 {
2708         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2709         struct dwc2_qh *qh;
2710         unsigned long flags;
2711
2712         qh = ep->hcpriv;
2713         if (!qh)
2714                 return;
2715
2716         spin_lock_irqsave(&hsotg->lock, flags);
2717         qh->tt_buffer_dirty = 0;
2718
2719         if (hsotg->flags.b.port_connect_status)
2720                 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
2721
2722         spin_unlock_irqrestore(&hsotg->lock, flags);
2723 }
2724
2725 static struct hc_driver dwc2_hc_driver = {
2726         .description = "dwc2_hsotg",
2727         .product_desc = "DWC OTG Controller",
2728         .hcd_priv_size = sizeof(struct wrapper_priv_data),
2729
2730         .irq = _dwc2_hcd_irq,
2731         .flags = HCD_MEMORY | HCD_USB2,
2732
2733         .start = _dwc2_hcd_start,
2734         .stop = _dwc2_hcd_stop,
2735         .urb_enqueue = _dwc2_hcd_urb_enqueue,
2736         .urb_dequeue = _dwc2_hcd_urb_dequeue,
2737         .endpoint_disable = _dwc2_hcd_endpoint_disable,
2738         .endpoint_reset = _dwc2_hcd_endpoint_reset,
2739         .get_frame_number = _dwc2_hcd_get_frame_number,
2740
2741         .hub_status_data = _dwc2_hcd_hub_status_data,
2742         .hub_control = _dwc2_hcd_hub_control,
2743         .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
2744
2745         .bus_suspend = _dwc2_hcd_suspend,
2746         .bus_resume = _dwc2_hcd_resume,
2747 };
2748
2749 /*
2750  * Frees secondary storage associated with the dwc2_hsotg structure contained
2751  * in the struct usb_hcd field
2752  */
2753 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
2754 {
2755         u32 ahbcfg;
2756         u32 dctl;
2757         int i;
2758
2759         dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
2760
2761         /* Free memory for QH/QTD lists */
2762         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
2763         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
2764         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
2765         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
2766         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
2767         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
2768
2769         /* Free memory for the host channels */
2770         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
2771                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
2772
2773                 if (chan != NULL) {
2774                         dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
2775                                 i, chan);
2776                         hsotg->hc_ptr_array[i] = NULL;
2777                         kfree(chan);
2778                 }
2779         }
2780
2781         if (hsotg->core_params->dma_enable > 0) {
2782                 if (hsotg->status_buf) {
2783                         dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
2784                                           hsotg->status_buf,
2785                                           hsotg->status_buf_dma);
2786                         hsotg->status_buf = NULL;
2787                 }
2788         } else {
2789                 kfree(hsotg->status_buf);
2790                 hsotg->status_buf = NULL;
2791         }
2792
2793         ahbcfg = readl(hsotg->regs + GAHBCFG);
2794
2795         /* Disable all interrupts */
2796         ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
2797         writel(ahbcfg, hsotg->regs + GAHBCFG);
2798         writel(0, hsotg->regs + GINTMSK);
2799
2800         if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
2801                 dctl = readl(hsotg->regs + DCTL);
2802                 dctl |= DCTL_SFTDISCON;
2803                 writel(dctl, hsotg->regs + DCTL);
2804         }
2805
2806         if (hsotg->wq_otg) {
2807                 if (!cancel_work_sync(&hsotg->wf_otg))
2808                         flush_workqueue(hsotg->wq_otg);
2809                 destroy_workqueue(hsotg->wq_otg);
2810         }
2811
2812         del_timer(&hsotg->wkp_timer);
2813 }
2814
2815 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
2816 {
2817         /* Turn off all host-specific interrupts */
2818         dwc2_disable_host_interrupts(hsotg);
2819
2820         dwc2_hcd_free(hsotg);
2821 }
2822
2823 /*
2824  * Initializes the HCD. This function allocates memory for and initializes the
2825  * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
2826  * USB bus with the core and calls the hc_driver->start() function. It returns
2827  * a negative error on failure.
2828  */
2829 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
2830 {
2831         struct usb_hcd *hcd;
2832         struct dwc2_host_chan *channel;
2833         u32 hcfg;
2834         int i, num_channels;
2835         int retval;
2836
2837         if (usb_disabled())
2838                 return -ENODEV;
2839
2840         dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
2841
2842         retval = -ENOMEM;
2843
2844         hcfg = readl(hsotg->regs + HCFG);
2845         dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
2846
2847 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2848         hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
2849                                          FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
2850         if (!hsotg->frame_num_array)
2851                 goto error1;
2852         hsotg->last_frame_num_array = kzalloc(
2853                         sizeof(*hsotg->last_frame_num_array) *
2854                         FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
2855         if (!hsotg->last_frame_num_array)
2856                 goto error1;
2857         hsotg->last_frame_num = HFNUM_MAX_FRNUM;
2858 #endif
2859
2860         /* Check if the bus driver or platform code has setup a dma_mask */
2861         if (hsotg->core_params->dma_enable > 0 &&
2862             hsotg->dev->dma_mask == NULL) {
2863                 dev_warn(hsotg->dev,
2864                          "dma_mask not set, disabling DMA\n");
2865                 hsotg->core_params->dma_enable = 0;
2866                 hsotg->core_params->dma_desc_enable = 0;
2867         }
2868
2869         /* Set device flags indicating whether the HCD supports DMA */
2870         if (hsotg->core_params->dma_enable > 0) {
2871                 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
2872                         dev_warn(hsotg->dev, "can't set DMA mask\n");
2873                 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
2874                         dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
2875         }
2876
2877         hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
2878         if (!hcd)
2879                 goto error1;
2880
2881         if (hsotg->core_params->dma_enable <= 0)
2882                 hcd->self.uses_dma = 0;
2883
2884         hcd->has_tt = 1;
2885
2886         ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg;
2887         hsotg->priv = hcd;
2888
2889         /*
2890          * Disable the global interrupt until all the interrupt handlers are
2891          * installed
2892          */
2893         dwc2_disable_global_interrupts(hsotg);
2894
2895         /* Initialize the DWC_otg core, and select the Phy type */
2896         retval = dwc2_core_init(hsotg, true, irq);
2897         if (retval)
2898                 goto error2;
2899
2900         /* Create new workqueue and init work */
2901         retval = -ENOMEM;
2902         hsotg->wq_otg = create_singlethread_workqueue("dwc2");
2903         if (!hsotg->wq_otg) {
2904                 dev_err(hsotg->dev, "Failed to create workqueue\n");
2905                 goto error2;
2906         }
2907         INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
2908
2909         setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
2910                     (unsigned long)hsotg);
2911
2912         /* Initialize the non-periodic schedule */
2913         INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
2914         INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
2915
2916         /* Initialize the periodic schedule */
2917         INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
2918         INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
2919         INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
2920         INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
2921
2922         /*
2923          * Create a host channel descriptor for each host channel implemented
2924          * in the controller. Initialize the channel descriptor array.
2925          */
2926         INIT_LIST_HEAD(&hsotg->free_hc_list);
2927         num_channels = hsotg->core_params->host_channels;
2928         memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
2929
2930         for (i = 0; i < num_channels; i++) {
2931                 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
2932                 if (channel == NULL)
2933                         goto error3;
2934                 channel->hc_num = i;
2935                 hsotg->hc_ptr_array[i] = channel;
2936         }
2937
2938         if (hsotg->core_params->uframe_sched > 0)
2939                 dwc2_hcd_init_usecs(hsotg);
2940
2941         /* Initialize hsotg start work */
2942         INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
2943
2944         /* Initialize port reset work */
2945         INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
2946
2947         /*
2948          * Allocate space for storing data on status transactions. Normally no
2949          * data is sent, but this space acts as a bit bucket. This must be
2950          * done after usb_add_hcd since that function allocates the DMA buffer
2951          * pool.
2952          */
2953         if (hsotg->core_params->dma_enable > 0)
2954                 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
2955                                         DWC2_HCD_STATUS_BUF_SIZE,
2956                                         &hsotg->status_buf_dma, GFP_KERNEL);
2957         else
2958                 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
2959                                           GFP_KERNEL);
2960
2961         if (!hsotg->status_buf)
2962                 goto error3;
2963
2964         hsotg->otg_port = 1;
2965         hsotg->frame_list = NULL;
2966         hsotg->frame_list_dma = 0;
2967         hsotg->periodic_qh_count = 0;
2968
2969         /* Initiate lx_state to L3 disconnected state */
2970         hsotg->lx_state = DWC2_L3;
2971
2972         hcd->self.otg_port = hsotg->otg_port;
2973
2974         /* Don't support SG list at this point */
2975         hcd->self.sg_tablesize = 0;
2976
2977         if (!IS_ERR_OR_NULL(hsotg->uphy))
2978                 otg_set_host(hsotg->uphy->otg, &hcd->self);
2979
2980         /*
2981          * Finish generic HCD initialization and start the HCD. This function
2982          * allocates the DMA buffer pool, registers the USB bus, requests the
2983          * IRQ line, and calls hcd_start method.
2984          */
2985         retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
2986         if (retval < 0)
2987                 goto error3;
2988
2989         device_wakeup_enable(hcd->self.controller);
2990
2991         dwc2_hcd_dump_state(hsotg);
2992
2993         dwc2_enable_global_interrupts(hsotg);
2994
2995         return 0;
2996
2997 error3:
2998         dwc2_hcd_release(hsotg);
2999 error2:
3000         usb_put_hcd(hcd);
3001 error1:
3002         kfree(hsotg->core_params);
3003
3004 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3005         kfree(hsotg->last_frame_num_array);
3006         kfree(hsotg->frame_num_array);
3007 #endif
3008
3009         dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
3010         return retval;
3011 }
3012
3013 /*
3014  * Removes the HCD.
3015  * Frees memory and resources associated with the HCD and deregisters the bus.
3016  */
3017 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
3018 {
3019         struct usb_hcd *hcd;
3020
3021         dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
3022
3023         hcd = dwc2_hsotg_to_hcd(hsotg);
3024         dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
3025
3026         if (!hcd) {
3027                 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
3028                         __func__);
3029                 return;
3030         }
3031
3032         if (!IS_ERR_OR_NULL(hsotg->uphy))
3033                 otg_set_host(hsotg->uphy->otg, NULL);
3034
3035         usb_remove_hcd(hcd);
3036         hsotg->priv = NULL;
3037         dwc2_hcd_release(hsotg);
3038         usb_put_hcd(hcd);
3039
3040 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3041         kfree(hsotg->last_frame_num_array);
3042         kfree(hsotg->frame_num_array);
3043 #endif
3044 }