drivers/staging/imx-drm/ipu-v3/ipu-common.c

   1 /*
   2  * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
   3  * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/export.h>
  17 #include <linux/types.h>
  18 #include <linux/init.h>
  19 #include <linux/reset.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/err.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/clk.h>
  27 #include <linux/list.h>
  28 #include <linux/irq.h>
  29 #include <linux/irqchip/chained_irq.h>
  30 #include <linux/irqdomain.h>
  31 #include <linux/of_device.h>
  32
  33 #include <drm/drm_fourcc.h>
  34
  35 #include "imx-ipu-v3.h"
  36 #include "ipu-prv.h"
  37
  38 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
  39 {
  40         return readl(ipu->cm_reg + offset);
  41 }
  42
  43 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
  44 {
  45         writel(value, ipu->cm_reg + offset);
  46 }
  47
  48 static inline u32 ipu_idmac_read(struct ipu_soc *ipu, unsigned offset)
  49 {
  50         return readl(ipu->idmac_reg + offset);
  51 }
  52
  53 static inline void ipu_idmac_write(struct ipu_soc *ipu, u32 value,
  54                 unsigned offset)
  55 {
  56         writel(value, ipu->idmac_reg + offset);
  57 }
  58
  59 void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
  60 {
  61         u32 val;
  62
  63         val = ipu_cm_read(ipu, IPU_SRM_PRI2);
  64         val |= 0x8;
  65         ipu_cm_write(ipu, val, IPU_SRM_PRI2);
  66 }
  67 EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
  68
  69 struct ipu_ch_param __iomem *ipu_get_cpmem(struct ipuv3_channel *channel)
  70 {
  71         struct ipu_soc *ipu = channel->ipu;
  72
  73         return ipu->cpmem_base + channel->num;
  74 }
  75 EXPORT_SYMBOL_GPL(ipu_get_cpmem);
  76
  77 void ipu_cpmem_set_high_priority(struct ipuv3_channel *channel)
  78 {
  79         struct ipu_soc *ipu = channel->ipu;
  80         struct ipu_ch_param __iomem *p = ipu_get_cpmem(channel);
  81         u32 val;
  82
  83         if (ipu->ipu_type == IPUV3EX)
  84                 ipu_ch_param_write_field(p, IPU_FIELD_ID, 1);
  85
  86         val = ipu_idmac_read(ipu, IDMAC_CHA_PRI(channel->num));
  87         val |= 1 << (channel->num % 32);
  88         ipu_idmac_write(ipu, val, IDMAC_CHA_PRI(channel->num));
  89 };
  90 EXPORT_SYMBOL_GPL(ipu_cpmem_set_high_priority);
  91
  92 void ipu_ch_param_write_field(struct ipu_ch_param __iomem *base, u32 wbs, u32 v)
  93 {
  94         u32 bit = (wbs >> 8) % 160;
  95         u32 size = wbs & 0xff;
  96         u32 word = (wbs >> 8) / 160;
  97         u32 i = bit / 32;
  98         u32 ofs = bit % 32;
  99         u32 mask = (1 << size) - 1;
 100         u32 val;
 101
 102         pr_debug("%s %d %d %d\n", __func__, word, bit , size);
 103
 104         val = readl(&base->word[word].data[i]);
 105         val &= ~(mask << ofs);
 106         val |= v << ofs;
 107         writel(val, &base->word[word].data[i]);
 108
 109         if ((bit + size - 1) / 32 > i) {
 110                 val = readl(&base->word[word].data[i + 1]);
 111                 val &= ~(mask >> (ofs ? (32 - ofs) : 0));
 112                 val |= v >> (ofs ? (32 - ofs) : 0);
 113                 writel(val, &base->word[word].data[i + 1]);
 114         }
 115 }
 116 EXPORT_SYMBOL_GPL(ipu_ch_param_write_field);
 117
 118 u32 ipu_ch_param_read_field(struct ipu_ch_param __iomem *base, u32 wbs)
 119 {
 120         u32 bit = (wbs >> 8) % 160;
 121         u32 size = wbs & 0xff;
 122         u32 word = (wbs >> 8) / 160;
 123         u32 i = bit / 32;
 124         u32 ofs = bit % 32;
 125         u32 mask = (1 << size) - 1;
 126         u32 val = 0;
 127
 128         pr_debug("%s %d %d %d\n", __func__, word, bit , size);
 129
 130         val = (readl(&base->word[word].data[i]) >> ofs) & mask;
 131
 132         if ((bit + size - 1) / 32 > i) {
 133                 u32 tmp;
 134                 tmp = readl(&base->word[word].data[i + 1]);
 135                 tmp &= mask >> (ofs ? (32 - ofs) : 0);
 136                 val |= tmp << (ofs ? (32 - ofs) : 0);
 137         }
 138
 139         return val;
 140 }
 141 EXPORT_SYMBOL_GPL(ipu_ch_param_read_field);
 142
 143 int ipu_cpmem_set_format_rgb(struct ipu_ch_param __iomem *p,
 144                 const struct ipu_rgb *rgb)
 145 {
 146         int bpp = 0, npb = 0, ro, go, bo, to;
 147
 148         ro = rgb->bits_per_pixel - rgb->red.length - rgb->red.offset;
 149         go = rgb->bits_per_pixel - rgb->green.length - rgb->green.offset;
 150         bo = rgb->bits_per_pixel - rgb->blue.length - rgb->blue.offset;
 151         to = rgb->bits_per_pixel - rgb->transp.length - rgb->transp.offset;
 152
 153         ipu_ch_param_write_field(p, IPU_FIELD_WID0, rgb->red.length - 1);
 154         ipu_ch_param_write_field(p, IPU_FIELD_OFS0, ro);
 155         ipu_ch_param_write_field(p, IPU_FIELD_WID1, rgb->green.length - 1);
 156         ipu_ch_param_write_field(p, IPU_FIELD_OFS1, go);
 157         ipu_ch_param_write_field(p, IPU_FIELD_WID2, rgb->blue.length - 1);
 158         ipu_ch_param_write_field(p, IPU_FIELD_OFS2, bo);
 159
 160         if (rgb->transp.length) {
 161                 ipu_ch_param_write_field(p, IPU_FIELD_WID3,
 162                                 rgb->transp.length - 1);
 163                 ipu_ch_param_write_field(p, IPU_FIELD_OFS3, to);
 164         } else {
 165                 ipu_ch_param_write_field(p, IPU_FIELD_WID3, 7);
 166                 ipu_ch_param_write_field(p, IPU_FIELD_OFS3,
 167                                 rgb->bits_per_pixel);
 168         }
 169
 170         switch (rgb->bits_per_pixel) {
 171         case 32:
 172                 bpp = 0;
 173                 npb = 15;
 174                 break;
 175         case 24:
 176                 bpp = 1;
 177                 npb = 19;
 178                 break;
 179         case 16:
 180                 bpp = 3;
 181                 npb = 31;
 182                 break;
 183         case 8:
 184                 bpp = 5;
 185                 npb = 63;
 186                 break;
 187         default:
 188                 return -EINVAL;
 189         }
 190         ipu_ch_param_write_field(p, IPU_FIELD_BPP, bpp);
 191         ipu_ch_param_write_field(p, IPU_FIELD_NPB, npb);
 192         ipu_ch_param_write_field(p, IPU_FIELD_PFS, 7); /* rgb mode */
 193
 194         return 0;
 195 }
 196 EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_rgb);
 197
 198 int ipu_cpmem_set_format_passthrough(struct ipu_ch_param __iomem *p,
 199                 int width)
 200 {
 201         int bpp = 0, npb = 0;
 202
 203         switch (width) {
 204         case 32:
 205                 bpp = 0;
 206                 npb = 15;
 207                 break;
 208         case 24:
 209                 bpp = 1;
 210                 npb = 19;
 211                 break;
 212         case 16:
 213                 bpp = 3;
 214                 npb = 31;
 215                 break;
 216         case 8:
 217                 bpp = 5;
 218                 npb = 63;
 219                 break;
 220         default:
 221                 return -EINVAL;
 222         }
 223
 224         ipu_ch_param_write_field(p, IPU_FIELD_BPP, bpp);
 225         ipu_ch_param_write_field(p, IPU_FIELD_NPB, npb);
 226         ipu_ch_param_write_field(p, IPU_FIELD_PFS, 6); /* raw mode */
 227
 228         return 0;
 229 }
 230 EXPORT_SYMBOL_GPL(ipu_cpmem_set_format_passthrough);
 231
 232 void ipu_cpmem_set_yuv_interleaved(struct ipu_ch_param __iomem *p,
 233                                    u32 pixel_format)
 234 {
 235         switch (pixel_format) {
 236         case V4L2_PIX_FMT_UYVY:
 237                 ipu_ch_param_write_field(p, IPU_FIELD_BPP, 3);    /* bits/pixel */
 238                 ipu_ch_param_write_field(p, IPU_FIELD_PFS, 0xA);  /* pix format */
 239                 ipu_ch_param_write_field(p, IPU_FIELD_NPB, 31);   /* burst size */
 240                 break;
 241         case V4L2_PIX_FMT_YUYV:
 242                 ipu_ch_param_write_field(p, IPU_FIELD_BPP, 3);    /* bits/pixel */
 243                 ipu_ch_param_write_field(p, IPU_FIELD_PFS, 0x8);  /* pix format */
 244                 ipu_ch_param_write_field(p, IPU_FIELD_NPB, 31);   /* burst size */
 245                 break;
 246         }
 247 }
 248 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_interleaved);
 249
 250 void ipu_cpmem_set_yuv_planar_full(struct ipu_ch_param __iomem *p,
 251                 u32 pixel_format, int stride, int u_offset, int v_offset)
 252 {
 253         switch (pixel_format) {
 254         case V4L2_PIX_FMT_YUV420:
 255                 ipu_ch_param_write_field(p, IPU_FIELD_SLUV, (stride / 2) - 1);
 256                 ipu_ch_param_write_field(p, IPU_FIELD_UBO, u_offset / 8);
 257                 ipu_ch_param_write_field(p, IPU_FIELD_VBO, v_offset / 8);
 258                 break;
 259         case V4L2_PIX_FMT_YVU420:
 260                 ipu_ch_param_write_field(p, IPU_FIELD_SLUV, (stride / 2) - 1);
 261                 ipu_ch_param_write_field(p, IPU_FIELD_UBO, v_offset / 8);
 262                 ipu_ch_param_write_field(p, IPU_FIELD_VBO, u_offset / 8);
 263                 break;
 264         }
 265 }
 266 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar_full);
 267
 268 void ipu_cpmem_set_yuv_planar(struct ipu_ch_param __iomem *p, u32 pixel_format,
 269                 int stride, int height)
 270 {
 271         int u_offset, v_offset;
 272         int uv_stride = 0;
 273
 274         switch (pixel_format) {
 275         case V4L2_PIX_FMT_YUV420:
 276         case V4L2_PIX_FMT_YVU420:
 277                 uv_stride = stride / 2;
 278                 u_offset = stride * height;
 279                 v_offset = u_offset + (uv_stride * height / 2);
 280                 ipu_cpmem_set_yuv_planar_full(p, pixel_format, stride,
 281                                 u_offset, v_offset);
 282                 break;
 283         }
 284 }
 285 EXPORT_SYMBOL_GPL(ipu_cpmem_set_yuv_planar);
 286
 287 static const struct ipu_rgb def_rgb_32 = {
 288         .red    = { .offset = 16, .length = 8, },
 289         .green  = { .offset =  8, .length = 8, },
 290         .blue   = { .offset =  0, .length = 8, },
 291         .transp = { .offset = 24, .length = 8, },
 292         .bits_per_pixel = 32,
 293 };
 294
 295 static const struct ipu_rgb def_bgr_32 = {
 296         .red    = { .offset =  0, .length = 8, },
 297         .green  = { .offset =  8, .length = 8, },
 298         .blue   = { .offset = 16, .length = 8, },
 299         .transp = { .offset = 24, .length = 8, },
 300         .bits_per_pixel = 32,
 301 };
 302
 303 static const struct ipu_rgb def_rgb_24 = {
 304         .red    = { .offset = 16, .length = 8, },
 305         .green  = { .offset =  8, .length = 8, },
 306         .blue   = { .offset =  0, .length = 8, },
 307         .transp = { .offset =  0, .length = 0, },
 308         .bits_per_pixel = 24,
 309 };
 310
 311 static const struct ipu_rgb def_bgr_24 = {
 312         .red    = { .offset =  0, .length = 8, },
 313         .green  = { .offset =  8, .length = 8, },
 314         .blue   = { .offset = 16, .length = 8, },
 315         .transp = { .offset =  0, .length = 0, },
 316         .bits_per_pixel = 24,
 317 };
 318
 319 static const struct ipu_rgb def_rgb_16 = {
 320         .red    = { .offset = 11, .length = 5, },
 321         .green  = { .offset =  5, .length = 6, },
 322         .blue   = { .offset =  0, .length = 5, },
 323         .transp = { .offset =  0, .length = 0, },
 324         .bits_per_pixel = 16,
 325 };
 326
 327 static const struct ipu_rgb def_bgr_16 = {
 328         .red    = { .offset =  0, .length = 5, },
 329         .green  = { .offset =  5, .length = 6, },
 330         .blue   = { .offset = 11, .length = 5, },
 331         .transp = { .offset =  0, .length = 0, },
 332         .bits_per_pixel = 16,
 333 };
 334
 335 #define Y_OFFSET(pix, x, y)     ((x) + pix->width * (y))
 336 #define U_OFFSET(pix, x, y)     ((pix->width * pix->height) + \
 337                                         (pix->width * (y) / 4) + (x) / 2)
 338 #define V_OFFSET(pix, x, y)     ((pix->width * pix->height) + \
 339                                         (pix->width * pix->height / 4) + \
 340                                         (pix->width * (y) / 4) + (x) / 2)
 341
 342 int ipu_cpmem_set_fmt(struct ipu_ch_param __iomem *cpmem, u32 drm_fourcc)
 343 {
 344         switch (drm_fourcc) {
 345         case DRM_FORMAT_YUV420:
 346         case DRM_FORMAT_YVU420:
 347                 /* pix format */
 348                 ipu_ch_param_write_field(cpmem, IPU_FIELD_PFS, 2);
 349                 /* burst size */
 350                 ipu_ch_param_write_field(cpmem, IPU_FIELD_NPB, 63);
 351                 break;
 352         case DRM_FORMAT_UYVY:
 353                 /* bits/pixel */
 354                 ipu_ch_param_write_field(cpmem, IPU_FIELD_BPP, 3);
 355                 /* pix format */
 356                 ipu_ch_param_write_field(cpmem, IPU_FIELD_PFS, 0xA);
 357                 /* burst size */
 358                 ipu_ch_param_write_field(cpmem, IPU_FIELD_NPB, 31);
 359                 break;
 360         case DRM_FORMAT_YUYV:
 361                 /* bits/pixel */
 362                 ipu_ch_param_write_field(cpmem, IPU_FIELD_BPP, 3);
 363                 /* pix format */
 364                 ipu_ch_param_write_field(cpmem, IPU_FIELD_PFS, 0x8);
 365                 /* burst size */
 366                 ipu_ch_param_write_field(cpmem, IPU_FIELD_NPB, 31);
 367                 break;
 368         case DRM_FORMAT_ABGR8888:
 369         case DRM_FORMAT_XBGR8888:
 370                 ipu_cpmem_set_format_rgb(cpmem, &def_bgr_32);
 371                 break;
 372         case DRM_FORMAT_ARGB8888:
 373         case DRM_FORMAT_XRGB8888:
 374                 ipu_cpmem_set_format_rgb(cpmem, &def_rgb_32);
 375                 break;
 376         case DRM_FORMAT_BGR888:
 377                 ipu_cpmem_set_format_rgb(cpmem, &def_bgr_24);
 378                 break;
 379         case DRM_FORMAT_RGB888:
 380                 ipu_cpmem_set_format_rgb(cpmem, &def_rgb_24);
 381                 break;
 382         case DRM_FORMAT_RGB565:
 383                 ipu_cpmem_set_format_rgb(cpmem, &def_rgb_16);
 384                 break;
 385         case DRM_FORMAT_BGR565:
 386                 ipu_cpmem_set_format_rgb(cpmem, &def_bgr_16);
 387                 break;
 388         default:
 389                 return -EINVAL;
 390         }
 391
 392         return 0;
 393 }
 394 EXPORT_SYMBOL_GPL(ipu_cpmem_set_fmt);
 395
 396 /*
 397  * The V4L2 spec defines packed RGB formats in memory byte order, which from
 398  * point of view of the IPU corresponds to little-endian words with the first
 399  * component in the least significant bits.
 400  * The DRM pixel formats and IPU internal representation are ordered the other
 401  * way around, with the first named component ordered at the most significant
 402  * bits. Further, V4L2 formats are not well defined:
 403  *     http://linuxtv.org/downloads/v4l-dvb-apis/packed-rgb.html
 404  * We choose the interpretation which matches GStreamer behavior.
 405  */
 406 static int v4l2_pix_fmt_to_drm_fourcc(u32 pixelformat)
 407 {
 408         switch (pixelformat) {
 409         case V4L2_PIX_FMT_RGB565:
 410                 /*
 411                  * Here we choose the 'corrected' interpretation of RGBP, a
 412                  * little-endian 16-bit word with the red component at the most
 413                  * significant bits:
 414                  * g[2:0]b[4:0] r[4:0]g[5:3] <=> [16:0] R:G:B
 415                  */
 416                 return DRM_FORMAT_RGB565;
 417         case V4L2_PIX_FMT_BGR24:
 418                 /* B G R <=> [24:0] R:G:B */
 419                 return DRM_FORMAT_RGB888;
 420         case V4L2_PIX_FMT_RGB24:
 421                 /* R G B <=> [24:0] B:G:R */
 422                 return DRM_FORMAT_BGR888;
 423         case V4L2_PIX_FMT_BGR32:
 424                 /* B G R A <=> [32:0] A:B:G:R */
 425                 return DRM_FORMAT_XRGB8888;
 426         case V4L2_PIX_FMT_RGB32:
 427                 /* R G B A <=> [32:0] A:B:G:R */
 428                 return DRM_FORMAT_XBGR8888;
 429         case V4L2_PIX_FMT_UYVY:
 430                 return DRM_FORMAT_UYVY;
 431         case V4L2_PIX_FMT_YUYV:
 432                 return DRM_FORMAT_YUYV;
 433         case V4L2_PIX_FMT_YUV420:
 434                 return DRM_FORMAT_YUV420;
 435         case V4L2_PIX_FMT_YVU420:
 436                 return DRM_FORMAT_YVU420;
 437         }
 438
 439         return -EINVAL;
 440 }
 441
 442 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
 443 {
 444         switch (drm_fourcc) {
 445         case DRM_FORMAT_RGB565:
 446         case DRM_FORMAT_BGR565:
 447         case DRM_FORMAT_RGB888:
 448         case DRM_FORMAT_BGR888:
 449         case DRM_FORMAT_XRGB8888:
 450         case DRM_FORMAT_XBGR8888:
 451         case DRM_FORMAT_RGBX8888:
 452         case DRM_FORMAT_BGRX8888:
 453         case DRM_FORMAT_ARGB8888:
 454         case DRM_FORMAT_ABGR8888:
 455         case DRM_FORMAT_RGBA8888:
 456         case DRM_FORMAT_BGRA8888:
 457                 return IPUV3_COLORSPACE_RGB;
 458         case DRM_FORMAT_YUYV:
 459         case DRM_FORMAT_UYVY:
 460         case DRM_FORMAT_YUV420:
 461         case DRM_FORMAT_YVU420:
 462                 return IPUV3_COLORSPACE_YUV;
 463         default:
 464                 return IPUV3_COLORSPACE_UNKNOWN;
 465         }
 466 }
 467 EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace);
 468
 469 int ipu_cpmem_set_image(struct ipu_ch_param __iomem *cpmem,
 470                 struct ipu_image *image)
 471 {
 472         struct v4l2_pix_format *pix = &image->pix;
 473         int y_offset, u_offset, v_offset;
 474
 475         pr_debug("%s: resolution: %dx%d stride: %d\n",
 476                         __func__, pix->width, pix->height,
 477                         pix->bytesperline);
 478
 479         ipu_cpmem_set_resolution(cpmem, image->rect.width,
 480                         image->rect.height);
 481         ipu_cpmem_set_stride(cpmem, pix->bytesperline);
 482
 483         ipu_cpmem_set_fmt(cpmem, v4l2_pix_fmt_to_drm_fourcc(pix->pixelformat));
 484
 485         switch (pix->pixelformat) {
 486         case V4L2_PIX_FMT_YUV420:
 487         case V4L2_PIX_FMT_YVU420:
 488                 y_offset = Y_OFFSET(pix, image->rect.left, image->rect.top);
 489                 u_offset = U_OFFSET(pix, image->rect.left,
 490                                 image->rect.top) - y_offset;
 491                 v_offset = V_OFFSET(pix, image->rect.left,
 492                                 image->rect.top) - y_offset;
 493
 494                 ipu_cpmem_set_yuv_planar_full(cpmem, pix->pixelformat,
 495                                 pix->bytesperline, u_offset, v_offset);
 496                 ipu_cpmem_set_buffer(cpmem, 0, image->phys + y_offset);
 497                 break;
 498         case V4L2_PIX_FMT_UYVY:
 499         case V4L2_PIX_FMT_YUYV:
 500                 ipu_cpmem_set_buffer(cpmem, 0, image->phys +
 501                                 image->rect.left * 2 +
 502                                 image->rect.top * image->pix.bytesperline);
 503                 break;
 504         case V4L2_PIX_FMT_RGB32:
 505         case V4L2_PIX_FMT_BGR32:
 506                 ipu_cpmem_set_buffer(cpmem, 0, image->phys +
 507                                 image->rect.left * 4 +
 508                                 image->rect.top * image->pix.bytesperline);
 509                 break;
 510         case V4L2_PIX_FMT_RGB565:
 511                 ipu_cpmem_set_buffer(cpmem, 0, image->phys +
 512                                 image->rect.left * 2 +
 513                                 image->rect.top * image->pix.bytesperline);
 514                 break;
 515         case V4L2_PIX_FMT_RGB24:
 516         case V4L2_PIX_FMT_BGR24:
 517                 ipu_cpmem_set_buffer(cpmem, 0, image->phys +
 518                                 image->rect.left * 3 +
 519                                 image->rect.top * image->pix.bytesperline);
 520                 break;
 521         default:
 522                 return -EINVAL;
 523         }
 524
 525         return 0;
 526 }
 527 EXPORT_SYMBOL_GPL(ipu_cpmem_set_image);
 528
 529 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
 530 {
 531         switch (pixelformat) {
 532         case V4L2_PIX_FMT_YUV420:
 533         case V4L2_PIX_FMT_YVU420:
 534         case V4L2_PIX_FMT_UYVY:
 535         case V4L2_PIX_FMT_YUYV:
 536                 return IPUV3_COLORSPACE_YUV;
 537         case V4L2_PIX_FMT_RGB32:
 538         case V4L2_PIX_FMT_BGR32:
 539         case V4L2_PIX_FMT_RGB24:
 540         case V4L2_PIX_FMT_BGR24:
 541         case V4L2_PIX_FMT_RGB565:
 542                 return IPUV3_COLORSPACE_RGB;
 543         default:
 544                 return IPUV3_COLORSPACE_UNKNOWN;
 545         }
 546 }
 547 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
 548
 549 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
 550 {
 551         struct ipuv3_channel *channel;
 552
 553         dev_dbg(ipu->dev, "%s %d\n", __func__, num);
 554
 555         if (num > 63)
 556                 return ERR_PTR(-ENODEV);
 557
 558         mutex_lock(&ipu->channel_lock);
 559
 560         channel = &ipu->channel[num];
 561
 562         if (channel->busy) {
 563                 channel = ERR_PTR(-EBUSY);
 564                 goto out;
 565         }
 566
 567         channel->busy = true;
 568         channel->num = num;
 569
 570 out:
 571         mutex_unlock(&ipu->channel_lock);
 572
 573         return channel;
 574 }
 575 EXPORT_SYMBOL_GPL(ipu_idmac_get);
 576
 577 void ipu_idmac_put(struct ipuv3_channel *channel)
 578 {
 579         struct ipu_soc *ipu = channel->ipu;
 580
 581         dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
 582
 583         mutex_lock(&ipu->channel_lock);
 584
 585         channel->busy = false;
 586
 587         mutex_unlock(&ipu->channel_lock);
 588 }
 589 EXPORT_SYMBOL_GPL(ipu_idmac_put);
 590
 591 #define idma_mask(ch)                   (1 << (ch & 0x1f))
 592
 593 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
 594                 bool doublebuffer)
 595 {
 596         struct ipu_soc *ipu = channel->ipu;
 597         unsigned long flags;
 598         u32 reg;
 599
 600         spin_lock_irqsave(&ipu->lock, flags);
 601
 602         reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
 603         if (doublebuffer)
 604                 reg |= idma_mask(channel->num);
 605         else
 606                 reg &= ~idma_mask(channel->num);
 607         ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
 608
 609         spin_unlock_irqrestore(&ipu->lock, flags);
 610 }
 611 EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
 612
 613 int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
 614 {
 615         unsigned long lock_flags;
 616         u32 val;
 617
 618         spin_lock_irqsave(&ipu->lock, lock_flags);
 619
 620         val = ipu_cm_read(ipu, IPU_DISP_GEN);
 621
 622         if (mask & IPU_CONF_DI0_EN)
 623                 val |= IPU_DI0_COUNTER_RELEASE;
 624         if (mask & IPU_CONF_DI1_EN)
 625                 val |= IPU_DI1_COUNTER_RELEASE;
 626
 627         ipu_cm_write(ipu, val, IPU_DISP_GEN);
 628
 629         val = ipu_cm_read(ipu, IPU_CONF);
 630         val |= mask;
 631         ipu_cm_write(ipu, val, IPU_CONF);
 632
 633         spin_unlock_irqrestore(&ipu->lock, lock_flags);
 634
 635         return 0;
 636 }
 637 EXPORT_SYMBOL_GPL(ipu_module_enable);
 638
 639 int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
 640 {
 641         unsigned long lock_flags;
 642         u32 val;
 643
 644         spin_lock_irqsave(&ipu->lock, lock_flags);
 645
 646         val = ipu_cm_read(ipu, IPU_CONF);
 647         val &= ~mask;
 648         ipu_cm_write(ipu, val, IPU_CONF);
 649
 650         val = ipu_cm_read(ipu, IPU_DISP_GEN);
 651
 652         if (mask & IPU_CONF_DI0_EN)
 653                 val &= ~IPU_DI0_COUNTER_RELEASE;
 654         if (mask & IPU_CONF_DI1_EN)
 655                 val &= ~IPU_DI1_COUNTER_RELEASE;
 656
 657         ipu_cm_write(ipu, val, IPU_DISP_GEN);
 658
 659         spin_unlock_irqrestore(&ipu->lock, lock_flags);
 660
 661         return 0;
 662 }
 663 EXPORT_SYMBOL_GPL(ipu_module_disable);
 664
 665 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
 666 {
 667         struct ipu_soc *ipu = channel->ipu;
 668         unsigned int chno = channel->num;
 669         unsigned long flags;
 670
 671         spin_lock_irqsave(&ipu->lock, flags);
 672
 673         /* Mark buffer as ready. */
 674         if (buf_num == 0)
 675                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
 676         else
 677                 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
 678
 679         spin_unlock_irqrestore(&ipu->lock, flags);
 680 }
 681 EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
 682
 683 int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
 684 {
 685         struct ipu_soc *ipu = channel->ipu;
 686         u32 val;
 687         unsigned long flags;
 688
 689         spin_lock_irqsave(&ipu->lock, flags);
 690
 691         val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
 692         val |= idma_mask(channel->num);
 693         ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
 694
 695         spin_unlock_irqrestore(&ipu->lock, flags);
 696
 697         return 0;
 698 }
 699 EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
 700
 701 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
 702 {
 703         struct ipu_soc *ipu = channel->ipu;
 704         unsigned long timeout;
 705
 706         timeout = jiffies + msecs_to_jiffies(ms);
 707         while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
 708                         idma_mask(channel->num)) {
 709                 if (time_after(jiffies, timeout))
 710                         return -ETIMEDOUT;
 711                 cpu_relax();
 712         }
 713
 714         return 0;
 715 }
 716 EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
 717
 718 int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
 719 {
 720         struct ipu_soc *ipu = channel->ipu;
 721         u32 val;
 722         unsigned long flags;
 723
 724         spin_lock_irqsave(&ipu->lock, flags);
 725
 726         /* Disable DMA channel(s) */
 727         val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
 728         val &= ~idma_mask(channel->num);
 729         ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
 730
 731         /* Set channel buffers NOT to be ready */
 732         ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
 733
 734         if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
 735                         idma_mask(channel->num)) {
 736                 ipu_cm_write(ipu, idma_mask(channel->num),
 737                              IPU_CHA_BUF0_RDY(channel->num));
 738         }
 739
 740         if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
 741                         idma_mask(channel->num)) {
 742                 ipu_cm_write(ipu, idma_mask(channel->num),
 743                              IPU_CHA_BUF1_RDY(channel->num));
 744         }
 745
 746         ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
 747
 748         /* Reset the double buffer */
 749         val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
 750         val &= ~idma_mask(channel->num);
 751         ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
 752
 753         spin_unlock_irqrestore(&ipu->lock, flags);
 754
 755         return 0;
 756 }
 757 EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
 758
 759 static int ipu_memory_reset(struct ipu_soc *ipu)
 760 {
 761         unsigned long timeout;
 762
 763         ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
 764
 765         timeout = jiffies + msecs_to_jiffies(1000);
 766         while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
 767                 if (time_after(jiffies, timeout))
 768                         return -ETIME;
 769                 cpu_relax();
 770         }
 771
 772         return 0;
 773 }
 774
 775 struct ipu_devtype {
 776         const char *name;
 777         unsigned long cm_ofs;
 778         unsigned long cpmem_ofs;
 779         unsigned long srm_ofs;
 780         unsigned long tpm_ofs;
 781         unsigned long disp0_ofs;
 782         unsigned long disp1_ofs;
 783         unsigned long dc_tmpl_ofs;
 784         unsigned long vdi_ofs;
 785         enum ipuv3_type type;
 786 };
 787
 788 static struct ipu_devtype ipu_type_imx51 = {
 789         .name = "IPUv3EX",
 790         .cm_ofs = 0x1e000000,
 791         .cpmem_ofs = 0x1f000000,
 792         .srm_ofs = 0x1f040000,
 793         .tpm_ofs = 0x1f060000,
 794         .disp0_ofs = 0x1e040000,
 795         .disp1_ofs = 0x1e048000,
 796         .dc_tmpl_ofs = 0x1f080000,
 797         .vdi_ofs = 0x1e068000,
 798         .type = IPUV3EX,
 799 };
 800
 801 static struct ipu_devtype ipu_type_imx53 = {
 802         .name = "IPUv3M",
 803         .cm_ofs = 0x06000000,
 804         .cpmem_ofs = 0x07000000,
 805         .srm_ofs = 0x07040000,
 806         .tpm_ofs = 0x07060000,
 807         .disp0_ofs = 0x06040000,
 808         .disp1_ofs = 0x06048000,
 809         .dc_tmpl_ofs = 0x07080000,
 810         .vdi_ofs = 0x06068000,
 811         .type = IPUV3M,
 812 };
 813
 814 static struct ipu_devtype ipu_type_imx6q = {
 815         .name = "IPUv3H",
 816         .cm_ofs = 0x00200000,
 817         .cpmem_ofs = 0x00300000,
 818         .srm_ofs = 0x00340000,
 819         .tpm_ofs = 0x00360000,
 820         .disp0_ofs = 0x00240000,
 821         .disp1_ofs = 0x00248000,
 822         .dc_tmpl_ofs = 0x00380000,
 823         .vdi_ofs = 0x00268000,
 824         .type = IPUV3H,
 825 };
 826
 827 static const struct of_device_id imx_ipu_dt_ids[] = {
 828         { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
 829         { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
 830         { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
 831         { /* sentinel */ }
 832 };
 833 MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
 834
 835 static int ipu_submodules_init(struct ipu_soc *ipu,
 836                 struct platform_device *pdev, unsigned long ipu_base,
 837                 struct clk *ipu_clk)
 838 {
 839         char *unit;
 840         int ret;
 841         struct device *dev = &pdev->dev;
 842         const struct ipu_devtype *devtype = ipu->devtype;
 843
 844         ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
 845                         IPU_CONF_DI0_EN, ipu_clk);
 846         if (ret) {
 847                 unit = "di0";
 848                 goto err_di_0;
 849         }
 850
 851         ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
 852                         IPU_CONF_DI1_EN, ipu_clk);
 853         if (ret) {
 854                 unit = "di1";
 855                 goto err_di_1;
 856         }
 857
 858         ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
 859                         IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
 860         if (ret) {
 861                 unit = "dc_template";
 862                 goto err_dc;
 863         }
 864
 865         ret = ipu_dmfc_init(ipu, dev, ipu_base +
 866                         devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
 867         if (ret) {
 868                 unit = "dmfc";
 869                 goto err_dmfc;
 870         }
 871
 872         ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
 873         if (ret) {
 874                 unit = "dp";
 875                 goto err_dp;
 876         }
 877
 878         return 0;
 879
 880 err_dp:
 881         ipu_dmfc_exit(ipu);
 882 err_dmfc:
 883         ipu_dc_exit(ipu);
 884 err_dc:
 885         ipu_di_exit(ipu, 1);
 886 err_di_1:
 887         ipu_di_exit(ipu, 0);
 888 err_di_0:
 889         dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
 890         return ret;
 891 }
 892
 893 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
 894 {
 895         unsigned long status;
 896         int i, bit, irq;
 897
 898         for (i = 0; i < num_regs; i++) {
 899
 900                 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
 901                 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
 902
 903                 for_each_set_bit(bit, &status, 32) {
 904                         irq = irq_linear_revmap(ipu->domain, regs[i] * 32 + bit);
 905                         if (irq)
 906                                 generic_handle_irq(irq);
 907                 }
 908         }
 909 }
 910
 911 static void ipu_irq_handler(unsigned int irq, struct irq_desc *desc)
 912 {
 913         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
 914         const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
 915         struct irq_chip *chip = irq_get_chip(irq);
 916
 917         chained_irq_enter(chip, desc);
 918
 919         ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
 920
 921         chained_irq_exit(chip, desc);
 922 }
 923
 924 static void ipu_err_irq_handler(unsigned int irq, struct irq_desc *desc)
 925 {
 926         struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
 927         const int int_reg[] = { 4, 5, 8, 9};
 928         struct irq_chip *chip = irq_get_chip(irq);
 929
 930         chained_irq_enter(chip, desc);
 931
 932         ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
 933
 934         chained_irq_exit(chip, desc);
 935 }
 936
 937 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
 938                 enum ipu_channel_irq irq_type)
 939 {
 940         int irq = irq_linear_revmap(ipu->domain, irq_type + channel->num);
 941
 942         if (!irq)
 943                 irq = irq_create_mapping(ipu->domain, irq_type + channel->num);
 944
 945         return irq;
 946 }
 947 EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
 948
 949 static void ipu_submodules_exit(struct ipu_soc *ipu)
 950 {
 951         ipu_dp_exit(ipu);
 952         ipu_dmfc_exit(ipu);
 953         ipu_dc_exit(ipu);
 954         ipu_di_exit(ipu, 1);
 955         ipu_di_exit(ipu, 0);
 956 }
 957
 958 static int platform_remove_devices_fn(struct device *dev, void *unused)
 959 {
 960         struct platform_device *pdev = to_platform_device(dev);
 961
 962         platform_device_unregister(pdev);
 963
 964         return 0;
 965 }
 966
 967 static void platform_device_unregister_children(struct platform_device *pdev)
 968 {
 969         device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
 970 }
 971
 972 struct ipu_platform_reg {
 973         struct ipu_client_platformdata pdata;
 974         const char *name;
 975 };
 976
 977 static const struct ipu_platform_reg client_reg[] = {
 978         {
 979                 .pdata = {
 980                         .di = 0,
 981                         .dc = 5,
 982                         .dp = IPU_DP_FLOW_SYNC_BG,
 983                         .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
 984                         .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
 985                 },
 986                 .name = "imx-ipuv3-crtc",
 987         }, {
 988                 .pdata = {
 989                         .di = 1,
 990                         .dc = 1,
 991                         .dp = -EINVAL,
 992                         .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
 993                         .dma[1] = -EINVAL,
 994                 },
 995                 .name = "imx-ipuv3-crtc",
 996         },
 997 };
 998
 999 static DEFINE_MUTEX(ipu_client_id_mutex);
1000 static int ipu_client_id;
1001
1002 static int ipu_add_client_devices(struct ipu_soc *ipu)
1003 {
1004         struct device *dev = ipu->dev;
1005         unsigned i;
1006         int id, ret;
1007
1008         mutex_lock(&ipu_client_id_mutex);
1009         id = ipu_client_id;
1010         ipu_client_id += ARRAY_SIZE(client_reg);
1011         mutex_unlock(&ipu_client_id_mutex);
1012
1013         for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
1014                 const struct ipu_platform_reg *reg = &client_reg[i];
1015                 struct platform_device *pdev;
1016
1017                 pdev = platform_device_register_data(dev, reg->name,
1018                         id++, &reg->pdata, sizeof(reg->pdata));
1019
1020                 if (IS_ERR(pdev))
1021                         goto err_register;
1022         }
1023
1024         return 0;
1025
1026 err_register:
1027         platform_device_unregister_children(to_platform_device(dev));
1028
1029         return ret;
1030 }
1031
1032
1033 static int ipu_irq_init(struct ipu_soc *ipu)
1034 {
1035         struct irq_chip_generic *gc;
1036         struct irq_chip_type *ct;
1037         unsigned long unused[IPU_NUM_IRQS / 32] = {
1038                 0x400100d0, 0xffe000fd,
1039                 0x400100d0, 0xffe000fd,
1040                 0x400100d0, 0xffe000fd,
1041                 0x4077ffff, 0xffe7e1fd,
1042                 0x23fffffe, 0x8880fff0,
1043                 0xf98fe7d0, 0xfff81fff,
1044                 0x400100d0, 0xffe000fd,
1045                 0x00000000,
1046         };
1047         int ret, i;
1048
1049         ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
1050                                             &irq_generic_chip_ops, ipu);
1051         if (!ipu->domain) {
1052                 dev_err(ipu->dev, "failed to add irq domain\n");
1053                 return -ENODEV;
1054         }
1055
1056         ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
1057                                              handle_level_irq, 0, IRQF_VALID, 0);
1058         if (ret < 0) {
1059                 dev_err(ipu->dev, "failed to alloc generic irq chips\n");
1060                 irq_domain_remove(ipu->domain);
1061                 return ret;
1062         }
1063
1064         for (i = 0; i < IPU_NUM_IRQS; i += 32) {
1065                 gc = irq_get_domain_generic_chip(ipu->domain, i);
1066                 gc->reg_base = ipu->cm_reg;
1067                 gc->unused = unused[i / 32];
1068                 ct = gc->chip_types;
1069                 ct->chip.irq_ack = irq_gc_ack_set_bit;
1070                 ct->chip.irq_mask = irq_gc_mask_clr_bit;
1071                 ct->chip.irq_unmask = irq_gc_mask_set_bit;
1072                 ct->regs.ack = IPU_INT_STAT(i / 32);
1073                 ct->regs.mask = IPU_INT_CTRL(i / 32);
1074         }
1075
1076         irq_set_chained_handler(ipu->irq_sync, ipu_irq_handler);
1077         irq_set_handler_data(ipu->irq_sync, ipu);
1078         irq_set_chained_handler(ipu->irq_err, ipu_err_irq_handler);
1079         irq_set_handler_data(ipu->irq_err, ipu);
1080
1081         return 0;
1082 }
1083
1084 static void ipu_irq_exit(struct ipu_soc *ipu)
1085 {
1086         int i, irq;
1087
1088         irq_set_chained_handler(ipu->irq_err, NULL);
1089         irq_set_handler_data(ipu->irq_err, NULL);
1090         irq_set_chained_handler(ipu->irq_sync, NULL);
1091         irq_set_handler_data(ipu->irq_sync, NULL);
1092
1093         /* TODO: remove irq_domain_generic_chips */
1094
1095         for (i = 0; i < IPU_NUM_IRQS; i++) {
1096                 irq = irq_linear_revmap(ipu->domain, i);
1097                 if (irq)
1098                         irq_dispose_mapping(irq);
1099         }
1100
1101         irq_domain_remove(ipu->domain);
1102 }
1103
1104 static int ipu_probe(struct platform_device *pdev)
1105 {
1106         const struct of_device_id *of_id =
1107                         of_match_device(imx_ipu_dt_ids, &pdev->dev);
1108         struct ipu_soc *ipu;
1109         struct resource *res;
1110         unsigned long ipu_base;
1111         int i, ret, irq_sync, irq_err;
1112         const struct ipu_devtype *devtype;
1113
1114         devtype = of_id->data;
1115
1116         irq_sync = platform_get_irq(pdev, 0);
1117         irq_err = platform_get_irq(pdev, 1);
1118         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1119
1120         dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
1121                         irq_sync, irq_err);
1122
1123         if (!res || irq_sync < 0 || irq_err < 0)
1124                 return -ENODEV;
1125
1126         ipu_base = res->start;
1127
1128         ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
1129         if (!ipu)
1130                 return -ENODEV;
1131
1132         for (i = 0; i < 64; i++)
1133                 ipu->channel[i].ipu = ipu;
1134         ipu->devtype = devtype;
1135         ipu->ipu_type = devtype->type;
1136
1137         spin_lock_init(&ipu->lock);
1138         mutex_init(&ipu->channel_lock);
1139
1140         dev_dbg(&pdev->dev, "cm_reg:   0x%08lx\n",
1141                         ipu_base + devtype->cm_ofs);
1142         dev_dbg(&pdev->dev, "idmac:    0x%08lx\n",
1143                         ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
1144         dev_dbg(&pdev->dev, "cpmem:    0x%08lx\n",
1145                         ipu_base + devtype->cpmem_ofs);
1146         dev_dbg(&pdev->dev, "disp0:    0x%08lx\n",
1147                         ipu_base + devtype->disp0_ofs);
1148         dev_dbg(&pdev->dev, "disp1:    0x%08lx\n",
1149                         ipu_base + devtype->disp1_ofs);
1150         dev_dbg(&pdev->dev, "srm:      0x%08lx\n",
1151                         ipu_base + devtype->srm_ofs);
1152         dev_dbg(&pdev->dev, "tpm:      0x%08lx\n",
1153                         ipu_base + devtype->tpm_ofs);
1154         dev_dbg(&pdev->dev, "dc:       0x%08lx\n",
1155                         ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
1156         dev_dbg(&pdev->dev, "ic:       0x%08lx\n",
1157                         ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
1158         dev_dbg(&pdev->dev, "dmfc:     0x%08lx\n",
1159                         ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
1160         dev_dbg(&pdev->dev, "vdi:      0x%08lx\n",
1161                         ipu_base + devtype->vdi_ofs);
1162
1163         ipu->cm_reg = devm_ioremap(&pdev->dev,
1164                         ipu_base + devtype->cm_ofs, PAGE_SIZE);
1165         ipu->idmac_reg = devm_ioremap(&pdev->dev,
1166                         ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
1167                         PAGE_SIZE);
1168         ipu->cpmem_base = devm_ioremap(&pdev->dev,
1169                         ipu_base + devtype->cpmem_ofs, PAGE_SIZE);
1170
1171         if (!ipu->cm_reg || !ipu->idmac_reg || !ipu->cpmem_base)
1172                 return -ENOMEM;
1173
1174         ipu->clk = devm_clk_get(&pdev->dev, "bus");
1175         if (IS_ERR(ipu->clk)) {
1176                 ret = PTR_ERR(ipu->clk);
1177                 dev_err(&pdev->dev, "clk_get failed with %d", ret);
1178                 return ret;
1179         }
1180
1181         platform_set_drvdata(pdev, ipu);
1182
1183         ret = clk_prepare_enable(ipu->clk);
1184         if (ret) {
1185                 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1186                 return ret;
1187         }
1188
1189         ipu->dev = &pdev->dev;
1190         ipu->irq_sync = irq_sync;
1191         ipu->irq_err = irq_err;
1192
1193         ret = ipu_irq_init(ipu);
1194         if (ret)
1195                 goto out_failed_irq;
1196
1197         ret = device_reset(&pdev->dev);
1198         if (ret) {
1199                 dev_err(&pdev->dev, "failed to reset: %d\n", ret);
1200                 goto out_failed_reset;
1201         }
1202         ret = ipu_memory_reset(ipu);
1203         if (ret)
1204                 goto out_failed_reset;
1205
1206         /* Set MCU_T to divide MCU access window into 2 */
1207         ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
1208                         IPU_DISP_GEN);
1209
1210         ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
1211         if (ret)
1212                 goto failed_submodules_init;
1213
1214         ret = ipu_add_client_devices(ipu);
1215         if (ret) {
1216                 dev_err(&pdev->dev, "adding client devices failed with %d\n",
1217                                 ret);
1218                 goto failed_add_clients;
1219         }
1220
1221         dev_info(&pdev->dev, "%s probed\n", devtype->name);
1222
1223         return 0;
1224
1225 failed_add_clients:
1226         ipu_submodules_exit(ipu);
1227 failed_submodules_init:
1228 out_failed_reset:
1229         ipu_irq_exit(ipu);
1230 out_failed_irq:
1231         clk_disable_unprepare(ipu->clk);
1232         return ret;
1233 }
1234
1235 static int ipu_remove(struct platform_device *pdev)
1236 {
1237         struct ipu_soc *ipu = platform_get_drvdata(pdev);
1238
1239         platform_device_unregister_children(pdev);
1240         ipu_submodules_exit(ipu);
1241         ipu_irq_exit(ipu);
1242
1243         clk_disable_unprepare(ipu->clk);
1244
1245         return 0;
1246 }
1247
1248 static struct platform_driver imx_ipu_driver = {
1249         .driver = {
1250                 .name = "imx-ipuv3",
1251                 .of_match_table = imx_ipu_dt_ids,
1252         },
1253         .probe = ipu_probe,
1254         .remove = ipu_remove,
1255 };
1256
1257 module_platform_driver(imx_ipu_driver);
1258
1259 MODULE_ALIAS("platform:imx-ipuv3");
1260 MODULE_DESCRIPTION("i.MX IPU v3 driver");
1261 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1262 MODULE_LICENSE("GPL");